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1 parent 195103b commit b6634d8Copy full SHA for b6634d8
regression/ebmc-spot/sva-buechi/disable_iff1.bdd.desc
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-KNOWNBUG
+CORE
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../../verilog/SVA/disable_iff1.sv
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--buechi --module main --bdd --numbered-trace
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^\[main\.p0\] always \(disable iff \(main.counter == 0\) main\.counter != 0\): PROVED$
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