Instrument $past when generating SMV word level

This removes Verilog's $past when outputting SMV word level, which does not
have an equivalent of $past.

Author: kroening

regression/ebmc/smv-word-level/verilog5.desc

@@ -0,0 +1,9 @@
+CORE
+verilog5.sv
+--smv-word-level
+^INIT ebmc::\$past1@1 = FALSE$
+^TRANS next\(ebmc::\$past1@1\) = main\.in$
+^LTLSPEC G main\.in = \(X ebmc::\$past1@1\)$
+^EXIT=0$
+^SIGNAL=0$
+--

regression/ebmc/smv-word-level/verilog5.sv

@@ -0,0 +1,5 @@
+module main(input clk, input in);
+
+  p1: assert property (in iff s_nexttime $past(in));
+
+endmodule