Merge pull request #1310 from diffblue/basic_config1

Verilog: KNOWNBUG test for config

Author: tautschnig

regression/verilog/config/basic_config1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+basic_config1.sv
+--module top
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This does not parse.

regression/verilog/config/basic_config1.sv

@@ -0,0 +1,13 @@
+module SUB;
+  parameter P = 1;
+endmodule
+
+module top;
+  SUB sub();
+endmodule
+
+config some_config;
+  design top;
+  instance top.sub use #(.P(2));
+endconfig
+