SystemVerilog: allow typedefs as port names in named port connections

This allows the use of identifiers that are typedefs in the local scope as
the name of the port in a named port connection.

Author: kroening

src/verilog/parser.y

@@ -3218,10 +3218,12 @@ named_port_connection_brace:
 	;
 
 named_port_connection:
-	  '.' port_identifier '(' expression_opt ')'
+	  // This needs to be 'any_identifier' to allow identifiers that
+	  // are typedefs in the local scope.
+	  '.' any_identifier '(' expression_opt ')'
 		{ init($$, ID_named_port_connection);
-                  mto($$, $2);
-                  mto($$, $4); }
+		  mto($$, $2);
+		  mto($$, $4); }
 	;
 
 // System Verilog standard 1800-2017