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+ CORE
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+ basic1.sv
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+ --cegar
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+ ^VERIFICATION SUCCESSFUL -- PROPERTY HOLDS$
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+ ^EXIT=0$
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+ ^SIGNAL=0$
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+ module top (input clk);
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+
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+ reg important;
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+ reg not_important;
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+
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+ initial important = 1 ;
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+ always @ (posedge clk)
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+ important = important;
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+
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+ assert property (important == 1 );
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+
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+ endmodule
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+ KNOWNBUG
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+ basic2.sv
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+ --cegar
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+ ^VERIFICATION FAILED -- PROPERTY REFUTED$
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+ ^EXIT=0$
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+ ^SIGNAL=0$
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+ module top (input clk);
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+
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+ reg important;
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+ reg not_important;
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+
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+ initial important = 1 ;
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+ always @ (posedge clk)
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+ important = 0 ;
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+
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+ // should fail after one transition
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+ assert property (important == 1 );
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+
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+ endmodule
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