PostDoc at EPFL and Director of Eng. in the OpenHW Group. He received his Ph.D. from ETH Zurich.
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EPFL, OpenHW Group
- Geneva
- @DavideSchiavo10
- in/pasquale-davide-schiavone-96812758
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esl-epfl/x-heep
esl-epfl/x-heep PubliceXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
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openhwgroup/cv32e40p
openhwgroup/cv32e40p PublicCV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
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lowRISC/ibex
lowRISC/ibex PublicIbex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
228 contributions in the last year
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Activity overview
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Contribution activity
March 2025
Created 2 commits in 1 repository
Opened 2 pull requests in 2 repositories
esl-epfl/x-heep
1
open
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fix OBI bus combinatorial paths
This contribution was made on Mar 20
openhwgroup/cve2
1
closed
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fix rf_we
This contribution was made on Mar 17
Reviewed 10 pull requests in 2 repositories
esl-epfl/x-heep
6 pull requests
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X-HEEP Generator - Adding peripherals to the mcu-gen flow
This contribution was made on Mar 25
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[doc] improve Debug.md
This contribution was made on Mar 24
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📖 Add X-TRELA to the ASIC page in doc
This contribution was made on Mar 17
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SPI slave work on Questasim
This contribution was made on Mar 11
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Prune the compiled code to its minimum expression
This contribution was made on Mar 10
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Update of the setup guide
This contribution was made on Mar 4
openhwgroup/cve2
4 pull requests
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Fix remaining sec inconsistency regarding the X-IF addition
This contribution was made on Mar 25
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Changes to make the X_if addition compatible with the golden version …
This contribution was made on Mar 17
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Logical Equivalence Checking with Yosys EQY
This contribution was made on Mar 17
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Modification of some Debug Modules parameters into (static) signals, as part of (#269)
This contribution was made on Mar 3