Fix config registers

danodus · Nov 1, 2024 · 4ab72a6 · 4ab72a6
1 parent d379f7f
commit 4ab72a6
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Showing 6 changed files with 9 additions and 95 deletions.
diff --git a/doc/config.rst b/doc/config.rst
@@ -10,8 +10,8 @@ Registers
 Register        Address
 =============== =============
 CONFIG          BASE_IO + 36
-FB_ADDR         BASE_IO + 44
-VSYNC           BASE_IO + 48
+FB_ADDR         BASE_IO + 40
+VSYNC           BASE_IO + 44
 =============== =============
 
 CONFIG

diff --git a/doc/index.rst b/doc/index.rst
@@ -16,8 +16,6 @@ Graphite System
    led.rst
    uart.rst
    sd_card.rst
-   keyboard.rst
-   mouse.rst
    graphite.rst
    config.rst
 

diff --git a/doc/keyboard.rst b/doc/keyboard.rst
diff --git a/doc/memory_map.rst b/doc/memory_map.rst
@@ -18,9 +18,9 @@ CLOCK               BASE_IO + 0
 LED                 BASE_IO + 4
 UART                BASE_IO + 8
 SD_CARD             BASE_IO + 16
-KEYBOARD            BASE_IO + 24
 GRAPHITE            BASE_IO + 32
-CONFIG              BASE_IO + 36
-MOUSE               BASE_IO + 40
-CONFIG (2)          BASE_IO + 44
+CONFIG (1)          BASE_IO + 36
+CONFIG (2)          BASE_IO + 40
+CONFIG (3)          BASE_IO + 44
+USB                 BASE_IO + 64
 ==================  ===============
diff --git a/doc/mouse.rst b/doc/mouse.rst
diff --git a/soc/rtl/soc_top.sv b/soc/rtl/soc_top.sv
@@ -425,7 +425,8 @@ module soc_top #(
         (iowadr == 7) ? {32'b0} :
         (iowadr == 8) ? {31'b0, graphite_cmd_axis_tready} :
         (iowadr == 9) ? {16'(H_RES), 16'(V_RES)} :
-        (iowadr == 12) ? fb_addr :
+        (iowadr == 10) ? fb_addr :
+        (iowadr == 11) ? {31'b0, vga_vsync} :
         (iowadr >= 16 && iowadr < 32) ? sie_di : 32'd0);
 
     assign dataTx = outbus[7:0];
@@ -471,7 +472,7 @@ module soc_top #(
                 end else if (iowadr == 9) begin
                     if (outbus[0])
                         req_flush_cache <= 1'b1;
-                end else if (iowadr == 12) begin
+                end else if (iowadr == 10) begin
                     fb_addr <= outbus[31:0];
                     use_graphite_front_addr <= 1'b0;
                 end