Changes for version 0.17.16

Added instructions and scripts for kisei cvc
calibre_cvc pauses if calibre not found
cvc_probe.il allows arrays and multiple selections
Forward bias diode are after first min/max or second min/max depending on CVC_LOGIC_DIODE flag
Unexpected power in Calculate power prints message instead of terminating q

configure.ac

@@ -2,7 +2,7 @@
 # Process this file with autoconf to produce a configure script.
 
 AC_PREREQ([2.69])
-AC_INIT(CVC, [0.17.15], [[email protected]])
+AC_INIT(CVC, [0.17.16], [[email protected]])
 AC_CONFIG_SRCDIR(src)
 AC_CONFIG_HEADERS([config.h])
 AC_USE_SYSTEM_EXTENSIONS

doc/Makefile.am

@@ -1,4 +1,5 @@
 
 docdir = $(datadir)/doc/@PACKAGE@
 doc_DATA = Doxyfile \
-	error_codes
+	error_codes \
+	kisei_instructions.txt

doc/kisei_instructions.txt

@@ -0,0 +1,41 @@
+#1 Run calibre extraction and lvs with automatch and hcells
+# filter kisei devices
+# no need to write output netlist
+# reduce series RES
+calibre -lvs -hier -automatch -hcell hcell chip.kisei.svrf | tee calibre_lvs.log1
+
+#2 Run calibre svs with new hcell file, removing unmatched hcells until lvs ok
+# filter kisei devices
+# no need to write output netlist
+# reduce series RES
+calibre -lvs -hier -hcell hcell.number chip.kisei-svs.svrf | tee calibre_lvs.log2
+
+#3 Run calibre svs to create cross reference
+# filter kisei devices
+# no need to write output netlist
+# reduce series RES
+calibre -lvs -hier -hcell hcell.number -nxf chip.kisei-svs.svrf | tee calibre_lvs.log3
+
+#4 Create output netlists
+# do not filter kisei devices
+# write output netlists
+# do not reduce series RES
+calibre -lvs -hier -hcell hcell.number chip.kisei-cvc.svrf | tee calibre_lvs.log4
+
+#5 Extract kisei devices from layout netlist and annotate net names
+# kisei.out is the list of cells to update in the netlist
+annotate_kisei top.lvs.rep.nxf < top.lay.net > kisei.out
+
+# cp kisei.out kisei.fix
+# fix it diff kisei.out kisei.fix
+
+#6 Add kisei devices to netlist.
+add_kisei kisei.fix < top.src.net > top.kisei.cdl
+
+sed 's/^\(.\)\1/\1/' top.kisei.cdl > top.fix.cdl
+#run svs on lay.net and fix.cdl
+
+#7 Run svs for top.cdl top.kisei.cdl
+# ignore kisei diodes.
+calibre -lvs -hier -hcell hcell.number net-kisei.svrf | tee calibre_lvs.log7
+

scripts/Makefile.am

@@ -1,5 +1,7 @@
 
-bin_SCRIPTS = calibre_cvc \
+bin_SCRIPTS = add_kisei \
+	annotate_kisei \
+	calibre_cvc \
 	clean_cvc_log \
 	cvc_probe.il \
 	cvc_select.tcl \

scripts/add_kisei

@@ -0,0 +1,51 @@
+#! /bin/csh -f
+
+set kisei = $1
+
+awk '\
+FILENAME == "'$kisei'" {\
+        if ( /^\*/ ) {\
+                next;\
+        }\
+        cell = $1;\
+        $1 = $2;\
+        $2 = "";\
+        if ( (cell, $0) in duplicate ) {\
+                next;\
+        }\
+        duplicate[cell, $0] = "";\
+        if ( cell in kisei ) {\
+                kisei[cell] = kisei[cell] "\n" $0;\
+        } else {\
+                kisei[cell] = $0;\
+                printed[cell] = 0;\
+        }\
+        #print kisei[cell] > "/dev/tty";\
+        next;\
+}\
+/^\.ENDS/ {\
+        if ( kisei[cell] != "" ) {\
+                printed[cell] = 1;\
+                print kisei[cell];\
+        }\
+        cell = "";\
+}\
+$1 ~ /^R/ && $4 == "RES" {\
+        print "*" $0;\
+        next;\
+}\
+/^\.SUBCKT/ {\
+        cell = $2;\
+}\
+ {\
+        print $0;\
+}\
+END {\
+        for ( cell in printed ) {\
+                if ( printed[cell] == 0 ) {\
+                        print "* skipped diodes for cell", cell;\
+                }\
+        }\
+}' $kisei - | \
+        sed 's/^\(.\)\1/\1/'
+

scripts/annotate_kisei

@@ -0,0 +1,50 @@
+#! /bin/csh -f
+# extract RES and parasitic diodes from layout netlist and annotate with source netlist names
+
+set nxf = $1
+
+awk '\
+FILENAME == "'$nxf'" {\
+        if ( /^%/ ) {\
+                layout_cell = $2;\
+                netlist_cell = $4;\
+                if ( layout_cell in mapped ) {\
+                        print "*ERROR:", layout_cell, "mapped to", mapped[layout_cell], "and", netlist_cell;\
+                } else {\
+                        mapped[layout_cell] = netlist_cell;\
+                }\
+        } else if ( /^[-0-9]/ ) {\
+                signal[layout_cell, $2] = $4;\
+        }\
+        next;\
+}\
+/^\.ENDS/ {\
+        cell = "";\
+        next;\
+}\
+/^\.SUBCKT/ {\
+        cell = $2;\
+}\
+$1 !~ /^D/ || $4 !~ /^K/ {\
+        if ( $1 !~ /^R/ || $4 != "RES" ) {\
+                # skip everything except parasitic diodes and RES\
+                next;\
+        }\
+}\
+cell != "" {\
+        if ( cell in mapped ) {\
+                for ( field = 2; field <= 3; field++ ) {\
+                        if ( (cell, $field) in signal ) {\
+                                $field = signal[cell, $field];\
+                        } else {\
+                                print "*ERROR:", cell, "missing", $field;\
+                                $field = "cvc-" $field;\
+                        }\
+                }\
+        } else {\
+                print "*ERROR:", cell, "not mapped";\
+        }\
+        $1 = $1 "-cvc";\
+        print mapped[cell], $0;\
+        next;\
+}' $nxf -

scripts/calibre_cvc

@@ -133,9 +133,14 @@ if [[ -f $OUTPUT.0 ]]; then
 	mv $OUTPUT.0 $OUTPUT.0.bak
 fi
 
-echo "Performing SVS..."
-calibre -hier -automatch -lvs -64 $rulefile > $log
-tail -15 $log
+which calibre &> /dev/null
+if [[ $? -eq 1 ]]; then
+	read -p "Run SVS and hit return..."
+else
+	echo "Performing SVS..."
+	calibre -hier -automatch -lvs -64 $rulefile > $log
+	tail -15 $log
+fi
 
 echo "Removing leading double characters and changing commented parameters ..."
 # ^RR -> R

scripts/cvc_probe.il

@@ -1,4 +1,4 @@
-; cvc_probe_selection, cvc_probe_device, cvc_probe_net: loads a hierarchy 
+; cvc_probe_selection, cvc_probe_device, cvc_probe_net: loads a hierarchy
 
 ; Copyright 2016 D. Mitch Bailey, Shuhari System
 
@@ -16,8 +16,10 @@
 ;   along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
 ; Set the following 2 variables for each project
-myTopLib = ???
-myTopBlock = ???
+myTopLib = "????"
+myTopBlock = "????"
+myArrayStart = '_
+myArrayEnd = '_
 
 procedure(cvc_probe_selection()
 	; Probe the clipboard text.
@@ -43,23 +45,24 @@ procedure(cvc_probe_device(theDevicePath)
 		?viewType "schematic"
 		?mode "r"
 	)
-;	print(myDb~>instances->??)
+;       print(myDb~>instances->??)
 	myHierarchy = parseString(myDevicePath "/")
 	myDevice = car(reverse(myHierarchy))
 	myCellPath = reverse(cdr(reverse(myHierarchy)))
 	println(list(myHierarchy myCellPath myDevice))
 	while(myCellPath != '() && myDb != nil
-		myDb = find_cvc_instance(geGetWindowCellView() car(myCellPath))
+		myInstance = split_array_instance(car(myCellPath))
+		myDb = find_cvc_instance(geGetWindowCellView() car(myInstance))
 		if(myDb then
-			geSwitch(myWindow "r" myDb 0 0 0)
+			geSwitch(myWindow "r" myDb get_offset(myDb cadr(myInstance)) 0 0)
 			myCellPath = cdr(myCellPath)
 		)
 	)
 	geSelectObject(find_cvc_instance(geGetWindowCellView() myDevice))
 )
 
 procedure(cvc_probe_net()
-;	myNetPath = clipboard
+;       myNetPath = clipboard
 	myNetPath = "/IO/I"
 	myDb = dbOpenCellViewByType("cvc_test" "test" "schematic")
 	myWindow = geOpen(
@@ -70,34 +73,35 @@ procedure(cvc_probe_net()
 		?viewType "schematic"
 		?mode "r"
 	)
-;	print(myDb~>instances->??)
+;       print(myDb~>instances->??)
 	myHierarchy = parseString(myNetPath "/")
 	myNet = car(reverse(myHierarchy))
 	myCellPath = reverse(cdr(reverse(myHierarchy)))
 	println(list(myHierarchy myCellPath myNet))
 	while(myCellPath != '() && myDb != nil
-		myDb = find_cvc_instance(geGetWindowCellView() car(myCellPath))
+		myInstance = split_array_instance(car(myCellPath))
+		myDb = find_cvc_instance(geGetWindowCellView() car(myInstance))
 		if(myDb then
-			geSwitch(myWindow "r" myDb 0 0 0)
+			geSwitch(myWindow "r" myDb get_offset(myDb cadr(myInstance)) 0 0)
 			myCellPath = cdr(myCellPath)
 		)
 	)
 	geAddNetProbe(find_cvc_instance(geGetWindowCellView() myNet))
 )
 
 procedure(find_cvc_instance(myDb instanceName)
-	prog((myInstances)
+	prog((myInstances myInstance)
 		myInstances = myDb~>instances
 		while( car(myInstances)
 			myInstance = car(myInstances)
 			; Skip the first letter. CDL adds 'X', 'M', 'R', etc. not in schematic.
-			if( myInstance~>name == substring(instanceName 2) then
+			if( myInstance~>baseName == substring(instanceName 2) then
 				println(strcat("found " instanceName))
 				return(myInstance)
 			)
 			; Skip the first two letters.
 			; Flattened cells may add 'MX' to schematic instance name.
-			if( myInstance~>name == substring(instanceName 3) then
+			if( myInstance~>baseName == substring(instanceName 3) then
 				println(strcat("found " instanceName))
 				return(myInstance)
 			)
@@ -108,3 +112,33 @@ procedure(find_cvc_instance(myDb instanceName)
 	)
 )
 
+procedure(split_array_instance(instanceName)
+	prog((myArrayBase myOffsetString myIndexLength)
+		if(getchar(instanceName strlen(instanceName)) == myArrayEnd then
+			myArrayBase = substring(instanceName 1 strlen(instanceName)-1)
+			myOffsetString = substring(rindex(myArrayBase myArrayStart) 2)
+			myIndexLength = strlen(myOffsetString) + 2
+			println(strcat("array " substring(instanceName 1 strlen(instanceName)-myIndexLength) " " myOffsetString))
+			return(list(substring(instanceName 1 strlen(instanceName)-myIndexLength) evalstring(myOffsetString)))
+		)
+		return(list(instanceName 0))
+	)
+)
+
+procedure(get_offset(instance offset)
+	prog((myArray myRange myStart myEnd)
+		myArray = index(instance~>name "<")
+		if( myArray then
+			myRange = parseString(myArray "<:>")
+			myStart = evalstring(car(myRange))
+			myEnd = evalstring(cadr(myRange))
+			println(list("range " myStart ":" myEnd " index " offset ))
+			if( myStart < myEnd then
+				return(offset - myStart)
+			else
+				return(myStart - offset)
+			)
+		)
+		return(0)
+	)
+)

src/CCvcDb_error.cc

@@ -1012,18 +1012,18 @@ void CCvcDb::FindForwardBiasDiodes() {
 					}
 				}
 				if ( mySourceVoltage == UNKNOWN_VOLTAGE ) {
-					if ( cvcParameters.cvcLogicDiodes && myDiodeConnections.simSourceVoltage != UNKNOWN_VOLTAGE ) {
-						mySourceVoltage = myDiodeConnections.simSourceVoltage;
-					} else {
+//					if ( cvcParameters.cvcLogicDiodes && myDiodeConnections.simSourceVoltage != UNKNOWN_VOLTAGE ) {
+//						mySourceVoltage = myDiodeConnections.simSourceVoltage;
+//					} else {
 						mySourceVoltage = myDiodeConnections.maxSourceVoltage;
-					}
+//					}
 				}
 				if ( myDrainVoltage == UNKNOWN_VOLTAGE ) {
-					if ( cvcParameters.cvcLogicDiodes && myDiodeConnections.simDrainVoltage != UNKNOWN_VOLTAGE ) {
-						myDrainVoltage = myDiodeConnections.simDrainVoltage;
-					} else {
+//					if ( cvcParameters.cvcLogicDiodes && myDiodeConnections.simDrainVoltage != UNKNOWN_VOLTAGE ) {
+//						myDrainVoltage = myDiodeConnections.simDrainVoltage;
+//					} else {
 						myDrainVoltage = myDiodeConnections.minDrainVoltage;
-					}
+//					}
 				}
 				if ( mySourceVoltage - myDrainVoltage > cvcParameters.cvcForwardErrorThreshold ) {
 					if ( myDiodeConnections.maxSourcePower_p->type[HIZ_BIT] || myDiodeConnections.minDrainPower_p->type[HIZ_BIT] ) {

src/CCvcDb_main.cc

@@ -184,7 +184,9 @@ void CCvcDb::VerifyCircuitForAllModes(int argc, const char * argv[]) {
 		reportFile << PrintProgress(&lastSnapshot, "MIN/MAX1 ") << endl;
 		reportFile << "Power nets " << CPower::powerCount << endl;
 		if ( detectErrorFlag ) {
-			//FindForwardBiasDiodes();
+			if ( ! cvcParameters.cvcLogicDiodes ) {
+				FindForwardBiasDiodes();
+			}
 			if ( ! cvcParameters.cvcSOI ) {
 				FindNmosSourceVsBulkErrors();
 			}
@@ -239,7 +241,7 @@ void CCvcDb::VerifyCircuitForAllModes(int argc, const char * argv[]) {
 		cvcCircuitList.PrintAndResetCircuitErrors(this, cvcParameters.cvcCircuitErrorLimit, logFile, errorFile, "! Logic shorts 2");
 		if ( detectErrorFlag ) {
 			FindLDDErrors();
-			FindForwardBiasDiodes();
+//			FindForwardBiasDiodes();
 		}
 		if ( gInteractive_cvc && --gContinueCount < 1
 				&& InteractiveCvc(STAGE_SECOND_SIM) == SKIP ) continue;
@@ -255,6 +257,9 @@ void CCvcDb::VerifyCircuitForAllModes(int argc, const char * argv[]) {
 		reportFile << PrintProgress(&lastSnapshot, "MIN/MAX2 ") << endl;
 		reportFile << "Power nets " << CPower::powerCount << endl;
 		if ( detectErrorFlag ) {
+			if ( cvcParameters.cvcLogicDiodes ) {
+				FindForwardBiasDiodes();
+			}
 			FindAllOverVoltageErrors();
 			//FindOverVoltageErrors("Vbg", OVERVOLTAGE_VBG);
 			//FindOverVoltageErrors("Vbs", OVERVOLTAGE_VBS);

src/CPower.cc

@@ -899,7 +899,8 @@ void CPowerPtrVector::CalculatePower(CEventQueue& theEventQueue, voltage_t theSh
 	}
 	if ( theEventQueue.queueType == MIN_QUEUE ) {
 		if ( myPower_p->minVoltage != UNKNOWN_VOLTAGE ) {
-			throw EDatabaseError("CalculatePower: Min " + to_string<voltage_t>(myPower_p->minVoltage) + " at " + theCvcDb_p->NetName(theNetId));
+			cout << "DEBUG: CalculatePower: Min " << to_string<voltage_t>(myPower_p->minVoltage) << " at " << theCvcDb_p->NetName(theNetId) << endl;
+			//throw EDatabaseError("CalculatePower: Min " + to_string<voltage_t>(myPower_p->minVoltage) + " at " + theCvcDb_p->NetName(theNetId));
 		}
 		myPower_p->minVoltage = theShortVoltage;
 		myPower_p->defaultMinNet = theDefaultNetId;
@@ -922,7 +923,8 @@ void CPowerPtrVector::CalculatePower(CEventQueue& theEventQueue, voltage_t theSh
 	}
 	if ( theEventQueue.queueType == MAX_QUEUE ) {
 		if ( myPower_p->maxVoltage != UNKNOWN_VOLTAGE ) {
-			throw EDatabaseError("CalculatePower: Max " + to_string<voltage_t>(myPower_p->maxVoltage) + " at " + theCvcDb_p->NetName(theNetId));
+			cout << "DEBUG: CalculatePower: Max " << to_string<voltage_t>(myPower_p->maxVoltage) << " at " << theCvcDb_p->NetName(theNetId) << endl;
+			//throw EDatabaseError("CalculatePower: Max " + to_string<voltage_t>(myPower_p->maxVoltage) + " at " + theCvcDb_p->NetName(theNetId));
 		}
 		myPower_p->maxVoltage = theShortVoltage;
 		myPower_p->defaultMaxNet = theDefaultNetId;

src/Cvc.hh

@@ -24,7 +24,7 @@
 #ifndef CVC_H_
 #define CVC_H_
 
-#define CVC_VERSION "0.17.15"
+#define CVC_VERSION "0.17.16"
 
 extern bool gDebug_cvc;
 extern bool gSetup_cvc;