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APO-slides - The Basic Computer Architecture Course Slides

The slides prepared for computer architecture courses at Czech Technical University in Prague.

In particular, the next courses are based on the materials at this time:

QtRvSim - Companion Simulator for Education

The processor description uses QtRvSim simulator to demonstrate basic single cycle and pipelined processor structure, as well as memory hierarchy, cache, branch prediction, and interrupt handling.

The simulator is available for download and online execution in a web browser at the Computer Architectures Education site

The sources are available on GitHub

Slides Sources Locations

The main CTU FEE repository for the APO slides on the faculty GitLab

The CTU students and colleagues should report issues there.

The GitHub copy of the slides sources is provided on GitHub to allow public reuse, problems report, and contributions pull requests

The Slides Build Process

The slides are based on the LaTeX Beamer style. The diagrams and figures sources are developed in SVG format and converted to PDF format by Inkscape. The actual version supports Czech and English language. The language is selected by DOC_LANG variable. Use the following command in the individual slide/lecture topics directory

  • make DOC_LANG=en

Slides Project Progress Tracking

The Czech slides for lectures 01 to 11 and 13 are completed.

The English variant offers slides for lectures 01 to 10.

The older LibreOffice-based slides for Czech and English lecture variants are complete for the whole course; see the subject pages for PDF outputs and ODP files.

Resources and Publications

Please reference above article, if you use QtRvSim in education or research related materials and publications.

LICENSE

The slides source and generated files are provided under following license

  • CC BY-SA - Attribution-ShareAlike

Slides authors:

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