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Merged
jdicorpo merged 6 commits into from
Sep 8, 2025
Merged

Update Makefile #3

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f66450d
Update Makefile
marwaneltoukhy Sep 6, 2025
428c31e
Update Makefile
marwaneltoukhy Sep 6, 2025
d74011c
Update Makefile
marwaneltoukhy Sep 6, 2025
d3e0247
Update lvs_config.json
marwaneltoukhy Sep 6, 2025
1c514e3
Update lvs_config.json
marwaneltoukhy Sep 6, 2025
2b2992f
Update dependencies.json
marwaneltoukhy Sep 6, 2025
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11 changes: 4 additions & 7 deletions Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,7 @@ export PDKPATH?=$(PDK_ROOT)/$(PDK)
PYTHON_BIN ?= python3

ROOTLESS ?= 0
export CIEL_DATA_SOURCE=static-web:https://chipfoundry.github.io/ciel-releases
USER_ARGS = -u $$(id -u $$USER):$$(id -g $$USER)
ifeq ($(ROOTLESS), 1)
USER_ARGS =
Expand All @@ -46,9 +47,7 @@ export DISABLE_LVS?=0
export ROOTLESS

ifeq ($(PDK),sky130A)
SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
export OPEN_PDKS_COMMIT_LVS?=6d4d11780c40b20ee63cc98e645307a9bf2b2ab8
export OPEN_PDKS_COMMIT?=0fe599b2afb6708d281543108caf8310912f54af
export OPEN_PDKS_COMMIT?=3e0e31dcce8519a7dbb82590346db16d91b7244f
MPW_TAG ?= CC2509
ifeq ($(CARAVEL_LITE),1)
CARAVEL_NAME := caravel-lite
Expand All @@ -62,9 +61,7 @@ endif
endif

ifeq ($(PDK),sky130B)
SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
export OPEN_PDKS_COMMIT_LVS?=6d4d11780c40b20ee63cc98e645307a9bf2b2ab8
export OPEN_PDKS_COMMIT?=0fe599b2afb6708d281543108caf8310912f54af
export OPEN_PDKS_COMMIT?=3e0e31dcce8519a7dbb82590346db16d91b7244f
MPW_TAG ?= 2024.09.12-1
ifeq ($(CARAVEL_LITE),1)
CARAVEL_NAME := caravel-lite
Expand Down Expand Up @@ -224,7 +221,7 @@ precheck:
@docker pull chipfoundry/mpw_precheck:latest

.PHONY: run-precheck
run-precheck: check-pdk check-precheck enable-lvs-pdk
run-precheck: check-pdk check-precheck
@if [ "$$DISABLE_LVS" = "1" ]; then\
$(eval INPUT_DIRECTORY := $(shell pwd)) \
cd $(PRECHECK_ROOT) && \
Expand Down
2 changes: 1 addition & 1 deletion ip/dependencies.json
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@@ -1 +1 @@
{"IP": [{"CF_SRAM_1024x32": "v1.1.0"}]}
{"IP": [{"CF_SRAM_1024x32": "v1.2.1"}]}
6 changes: 3 additions & 3 deletions lvs/user_project_wrapper/lvs_config.json
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Expand Up @@ -8,7 +8,7 @@
"*__fill_*",
"*__fakediode_*",
"*__tapvpwrvgnd_*",
"CF_SRAM_1024x32"
"*CF_SRAM_1024x32"
],
"LVS_FLATTEN": [
""
Expand All @@ -20,12 +20,12 @@
""
],
"LVS_SPICE_FILES": [
"$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice",
"$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap*.spice",
"$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
],
"LVS_VERILOG_FILES": [
"$UPRJ_ROOT/verilog/gl/CF_SRAM_1024x32_wb_wrapper.v",
"$UPRJ_ROOT/verilog/gl/$TOP_SOURCE.v"
],
"LAYOUT_FILE": "$UPRJ_ROOT/gds/$TOP_LAYOUT.gds"
}
}
2 changes: 1 addition & 1 deletion openlane/Makefile
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Expand Up @@ -27,7 +27,7 @@ ifeq ($(origin LIBRELANE_RUN_TAG), undefined)
export LIBRELANE_RUN_TAG := $(shell date '+%y_%m_%d_%H_%M')
endif
ifeq ($(origin LIBRELANE_TAG), undefined)
export CF_LIBRELANE_TAG := CC2509
export CF_LIBRELANE_TAG := CC2509c
endif

export CARAVEL_ROOT := $(CARAVEL_ROOT)
Expand Down
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