analogdevicesinc · podgori · Jan 23, 2025
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+####################################################################################
+####################################################################################
+## Copyright 2025(c) Analog Devices, Inc.
+####################################################################################
+####################################################################################
+
+# Makeincludes
+include ../../../scripts/make_tb_path.mk
+include $(TB_LIBRARY_PATH)/includes/Makeinclude_common.mk
+include $(TB_LIBRARY_PATH)/includes/Makeinclude_data_offload.mk
+include $(TB_LIBRARY_PATH)/includes/Makeinclude_dmac.mk
+include $(TB_LIBRARY_PATH)/includes/Makeinclude_jesd.mk
+include $(TB_LIBRARY_PATH)/includes/Makeinclude_xcvr.mk
+
+# Remaining test-bench dependencies except test programs
+SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_dac_pkg.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_common_pkg.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_adc_pkg.sv
+
+LIB_DEPS += axi_dmac
+LIB_DEPS += data_offload
+LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
+LIB_DEPS += jesd204/axi_jesd204_tx
+LIB_DEPS += jesd204/jesd204_tx
+LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
+LIB_DEPS += jesd204/axi_jesd204_rx
+LIB_DEPS += jesd204/jesd204_rx
+LIB_DEPS += xilinx/axi_adxcvr
+LIB_DEPS += xilinx/util_adxcvr
+LIB_DEPS += util_do_ram
+LIB_DEPS += util_pack/util_upack2
+LIB_DEPS += util_pack/util_cpack2
+LIB_DEPS += xilinx/axi_adxcvr
+LIB_DEPS += xilinx/util_adxcvr
+LIB_DEPS += axi_sysid
+LIB_DEPS += sysid_rom
+
+# default test program
+TP := test_program
+
+# config files should have the following format
+#  cfg_<param1>_<param2>.tcl
+CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl))
+#$(warning $(CFG_FILES))
+
+# List of tests and configuration combinations that has to be run
+# Format is:  <configuration>:<test name>
+TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP))
+#TESTS += cfg1:test_program
+#TESTS += cfg2:test_program
+
+include $(ADI_TB_DIR)/scripts/project-sim.mk
+
+# usage :
+#
+# run specific test on a specific configuration in gui mode
+# 	make CFG=cfg2_fsync TST=test_frame_delay MODE=gui
+#
+# run all test from a configuration
+# 	make cfg1_mm2mm_default
+
+####################################################################################
+####################################################################################
@@ -0,0 +1,27 @@
+Usage :
+
+Run all tests in batch mode:
+
+	make
+
+
+Run all tests in GUI mode:
+
+	make MODE=gui
+
+
+Run specific test on a specific configuration in gui mode:
+
+	make CFG=<name of cfg> TST=<name of test> MODE=gui
+
+
+Run all test from a configuration:
+
+	make <name of cfg>
+
+
+Where:
+
+ * <name of cfg> is a file from the cfgs directory without the tcl extension of format cfg\*
+ * <name of test> is a file from the tests directory without the tcl extension
+
@@ -0,0 +1,25 @@
+global ad_project_params
+
+set ad_project_params(DAC_OFFLOAD_TYPE) 0
+set ad_project_params(DAC_OFFLOAD_SIZE) [expr 1*1024*1024]
+set ad_project_params(PLDDR_OFFLOAD_DATA_WIDTH) 0
+set ad_project_params(RD_DATA_REGISTERED) 0
+set ad_project_params(RD_FIFO_ADDRESS_WIDTH) 2
+
+set ad_project_params(REF_CLK_RATE) 500
+set ad_project_params(RX_LANE_RATE) 10
+set ad_project_params(TX_LANE_RATE) 10
+
+set ad_project_params(RX_JESD_M) 8
+set ad_project_params(RX_JESD_L) 4
+set ad_project_params(RX_JESD_S) 1
+set ad_project_params(RX_JESD_NP) 16
+set ad_project_params(RX_JESD_F) 4
+set ad_project_params(RX_JESD_K) 32
+
+set ad_project_params(TX_JESD_M) 8
+set ad_project_params(TX_JESD_L) 4
+set ad_project_params(TX_JESD_S) 1
+set ad_project_params(TX_JESD_NP) 16
+set ad_project_params(TX_JESD_F) 4
+set ad_project_params(TX_JESD_K) 32
@@ -0,0 +1,25 @@
+global ad_project_params
+
+set ad_project_params(DAC_OFFLOAD_TYPE) 0
+set ad_project_params(DAC_OFFLOAD_SIZE) [expr 1*1024*1024]
+set ad_project_params(PLDDR_OFFLOAD_DATA_WIDTH) 0
+set ad_project_params(RD_DATA_REGISTERED) 1
+set ad_project_params(RD_FIFO_ADDRESS_WIDTH) 3
+
+set ad_project_params(REF_CLK_RATE) 500
+set ad_project_params(RX_LANE_RATE) 10
+set ad_project_params(TX_LANE_RATE) 10
+
+set ad_project_params(RX_JESD_M) 8
+set ad_project_params(RX_JESD_L) 4
+set ad_project_params(RX_JESD_S) 1
+set ad_project_params(RX_JESD_NP) 16
+set ad_project_params(RX_JESD_F) 4
+set ad_project_params(RX_JESD_K) 32
+
+set ad_project_params(TX_JESD_M) 8
+set ad_project_params(TX_JESD_L) 4
+set ad_project_params(TX_JESD_S) 1
+set ad_project_params(TX_JESD_NP) 16
+set ad_project_params(TX_JESD_F) 4
+set ad_project_params(TX_JESD_K) 32
@@ -0,0 +1,144 @@
+# ***************************************************************************
+# ***************************************************************************
+# Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+#
+# In this HDL repository, there are many different and unique modules, consisting
+# of various HDL (Verilog or VHDL) components. The individual modules are
+# developed independently, and may be accompanied by separate and unique license
+# terms.
+#
+# The user should read each of these license terms, and understand the
+# freedoms and responsibilities that he or she has by using this source/core.
+#
+# This core is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE.
+#
+# Redistribution and use of source or resulting binaries, with or without modification
+# of this file, are permitted under one of the following two license terms:
+#
+#   1. The GNU General Public License version 2 as published by the
+#      Free Software Foundation, which can be found in the top level directory
+#      of this repository (LICENSE_GPL2), and also online at:
+#      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+#
+# OR
+#
+#   2. An ADI specific BSD license, which can be found in the top level directory
+#      of this repository (LICENSE_ADIBSD), and also on-line at:
+#      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+#      This will allow to generate bit files and not release the source code,
+#      as long as it attaches to an ADI device.
+#
+# ***************************************************************************
+# ***************************************************************************
+
+global ad_project_params
+
+set dac_offload_type $ad_project_params(DAC_OFFLOAD_TYPE)
+set dac_offload_size $ad_project_params(DAC_OFFLOAD_SIZE)
+set plddr_offload_axi_data_width $ad_project_params(PLDDR_OFFLOAD_DATA_WIDTH)
+set rd_data_registered $ad_project_params(RD_DATA_REGISTERED)
+set rd_fifo_address_width $ad_project_params(RD_FIFO_ADDRESS_WIDTH)
+
+# Ref clk
+ad_ip_instance clk_vip ref_clk_vip [ list \
+  INTERFACE_MODE {MASTER} \
+  FREQ_HZ 250000000 \
+]
+adi_sim_add_define "REF_CLK=ref_clk_vip"
+create_bd_port -dir O ref_clk_out
+ad_connect ref_clk_out ref_clk_vip/clk_out
+
+# SYSREF clk
+ad_ip_instance clk_vip sysref_clk_vip [ list \
+  INTERFACE_MODE {MASTER} \
+  FREQ_HZ 5000000 \
+]
+adi_sim_add_define "SYSREF_CLK=sysref_clk_vip"
+create_bd_port -dir O sysref_clk_out
+ad_connect sysref_clk_out sysref_clk_vip/clk_out
+
+#
+#  Block design under test
+#
+
+source $ad_hdl_dir/projects/daq3/common/daq3_bd.tcl
+
+ad_ip_parameter $dac_offload_name/storage_unit CONFIG.RD_DATA_REGISTERED $rd_data_registered
+ad_ip_parameter $dac_offload_name/storage_unit CONFIG.RD_FIFO_ADDRESS_WIDTH $rd_fifo_address_width
+
+# Import configuration from daq3/zcu102
+ad_ip_parameter util_daq3_xcvr CONFIG.CPLL_CFG0 0x03fe
+ad_ip_parameter util_daq3_xcvr CONFIG.CPLL_CFG1 0x0021
+ad_ip_parameter util_daq3_xcvr CONFIG.CPLL_CFG2 0x0203
+
+ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV 20
+ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_REFCLK_DIV 1
+
+ad_ip_parameter axi_ad9152_dma CONFIG.FIFO_SIZE 32
+ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_SRC 1
+ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_DEST 1
+ad_ip_parameter axi_ad9152_dma CONFIG.CYCLIC 1
+ad_ip_parameter axi_ad9152_dma CONFIG.MAX_BYTES_PER_BURST 256
+
+ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_SRC 2
+ad_ip_parameter axi_ad9680_dma CONFIG.FIFO_SIZE 32
+ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 128
+ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 128
+ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_SRC 1
+ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_DEST 1
+ad_ip_parameter axi_ad9680_dma CONFIG.MAX_BYTES_PER_BURST 256
+
+ad_connect sys_dma_clk $dac_offload_name/s_axis_aclk
+ad_connect sys_dma_resetn $dac_offload_name/s_axis_aresetn
+ad_connect sys_dma_clk axi_ad9152_dma/m_axis_aclk
+ad_connect sys_dma_resetn axi_ad9152_dma/m_src_axi_aresetn
+
+ad_connect sys_dma_resetn axi_ad9680_dma/m_dest_axi_aresetn
+ad_connect axi_ad9680_dma/fifo_wr_clk util_daq3_xcvr/rx_out_clk_0
+ad_connect axi_ad9680_cpack/packed_fifo_wr axi_ad9680_dma/fifo_wr
+ad_connect axi_ad9680_cpack/fifo_wr_overflow axi_ad9680_tpl_core/adc_dovf
+
+ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
+ad_mem_hp0_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi
+ad_mem_hp1_interconnect sys_dma_clk sys_ps7/S_AXI_HP1
+ad_mem_hp1_interconnect sys_dma_clk axi_ad9680_dma/m_dest_axi
+ad_mem_hp3_interconnect sys_dma_clk sys_ps7/S_AXI_HP3
+ad_mem_hp3_interconnect sys_dma_clk axi_ad9152_dma/m_src_axi
+
+set RX_DMA 0x7C400000
+set_property offset $RX_DMA [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ad9680_dma}]
+adi_sim_add_define "RX_DMA_BA=[format "%d" ${RX_DMA}]"
+
+set RX_XCVR 0x44A50000
+set_property offset $RX_XCVR [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ad9680_xcvr}]
+adi_sim_add_define "RX_XCVR_BA=[format "%d" ${RX_XCVR}]"
+
+set TX_DMA 0x7C420000
+set_property offset $TX_DMA [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ad9152_dma}]
+adi_sim_add_define "TX_DMA_BA=[format "%d" ${TX_DMA}]"
+
+set TX_XCVR 0x44A60000
+set_property offset $TX_XCVR [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ad9152_xcvr}]
+adi_sim_add_define "TX_XCVR_BA=[format "%d" ${TX_XCVR}]"
+
+set AXI_JESD_RX 0x44AA0000
+set_property offset $AXI_JESD_RX [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ad9680_jesd}]
+adi_sim_add_define "AXI_JESD_RX_BA=[format "%d" ${AXI_JESD_RX}]"
+
+set ADC_TPL 0x44A10000
+set_property offset $ADC_TPL [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ad9680_tpl_core}]
+adi_sim_add_define "ADC_TPL_BA=[format "%d" ${ADC_TPL}]"
+
+set DAC_TPL 0x44A04000
+set_property offset $DAC_TPL [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ad9152_tpl_core}]
+adi_sim_add_define "DAC_TPL_BA=[format "%d" ${DAC_TPL}]"
+
+set AXI_JESD_TX 0x44A90000
+set_property offset $AXI_JESD_TX [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ad9152_jesd}]
+adi_sim_add_define "AXI_JESD_TX_BA=[format "%d" ${AXI_JESD_TX}]"
+
+set TX_OFFLOAD 0x7C430000
+set_property offset $TX_OFFLOAD [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_ad9152_data_offload}]
+adi_sim_add_define "TX_OFFLOAD_BA=[format "%d" ${TX_OFFLOAD}]"
@@ -0,0 +1,35 @@
+source ../../../scripts/adi_sim.tcl
+
+if {$argc < 1} {
+  puts "Expecting at least one argument that specifies the test configuration"
+  exit 1
+} else {
+  set cfg_file [lindex $argv 0]
+}
+
+# Read common config file
+source "cfgs/${cfg_file}"
+
+# Set the project name
+set project_name [file rootname $cfg_file]
+
+# Create the project
+adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e"
+
+source $ad_tb_dir/library/includes/sp_include_data_offload.tcl
+source $ad_tb_dir/library/includes/sp_include_dmac.tcl
+source $ad_tb_dir/library/includes/sp_include_jesd.tcl
+source $ad_tb_dir/library/includes/sp_include_xcvr.tcl
+
+# Add test files to the project
+adi_sim_project_files [list \
+  "$ad_tb_dir/library/regmaps/adi_regmap_dac_pkg.sv" \
+  "$ad_tb_dir/library/regmaps/adi_regmap_common_pkg.sv" \
+  "$ad_tb_dir/library/regmaps/adi_regmap_adc_pkg.sv" \
+  "tests/test_program.sv" \
+]
+
+#set a default test program
+adi_sim_add_define "TEST_PROGRAM=test_program"
+
+adi_sim_generate $project_name
@@ -0,0 +1,72 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsabilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/1ps
+
+`include "utils.svh"
+
+module system_tb();
+
+  `TEST_PROGRAM test();
+
+  test_harness `TH (
+    .ref_clk_out    (ref_clk),
+    .sysref_clk_out (sysref),
+
+    .rx_data_0_n    (data_0_n),        //-dir I
+    .rx_data_0_p    (data_0_p),        //-dir I
+    .rx_data_1_n    (data_1_n),        //-dir I
+    .rx_data_1_p    (data_1_p),        //-dir I
+    .rx_data_2_n    (data_2_n),        //-dir I
+    .rx_data_2_p    (data_2_p),        //-dir I
+    .rx_data_3_n    (data_3_n),        //-dir I
+    .rx_data_3_p    (data_3_p),        //-dir I
+    .tx_data_0_n    (data_0_n),        //-dir O
+    .tx_data_0_p    (data_0_p),        //-dir O
+    .tx_data_1_n    (data_3_n),        //-dir O
+    .tx_data_1_p    (data_3_p),        //-dir O
+    .tx_data_2_n    (data_1_n),        //-dir O
+    .tx_data_2_p    (data_1_p),        //-dir O
+    .tx_data_3_n    (data_2_n),        //-dir O
+    .tx_data_3_p    (data_2_p),        //-dir O
+    .rx_sync_0      (rx_sync_0),       //-dir O
+    .tx_sync_0      (rx_sync_0),       //-dir I
+    .rx_sysref_0    (sysref),          //-dir I
+    .tx_sysref_0    (sysref),          //-dir I
+    .rx_ref_clk_0   (ref_clk),         //-dir I
+    .tx_ref_clk_0   (ref_clk)          //-dir I
+  );
+
+endmodule