Fix adrv9361 hold timing violations

[phlfm]

⚠️ Warning - these changes have not been tested on the corresponding hardware / setup / boards!

PR Description

Similar to #1909, this PR addresses timing violations observed following the upgrade to Vivado 2025.1, without requiring any HDL modifications. The solution for this project was to rerun route_design as suggested by AMD Employee on the Xilinx forums.

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)
• Documentation

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have compiled all hdl projects and libraries affected by this PR
• I have tested in hardware affected projects, at least on relevant boards
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Critical Warnings on compilation
• I have added new hdl testbenches or updated existing ones

[bia1708]

RetriggerCI

[sarpadi]

i think you meant AMD

[LBFFilho]

It looks good, apart from the comment error @sarpadi pointed out.

This is quite a quirky problem with an equally quirky workaround :)
Let's hope Xilinx fixes the root cause in the next release.

[caosjr]

compiled the project and it seems fine, no timing issues. Maybe adding that it is a quick fix for this version of Vivado in the documentation? I don't think it is reasonable to run twice "route_design" in the future (where I hope AMD fixes this issue lol)