projects: ad9084_ebz: Initial design #1901
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FilipG24
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Found a few invalid paths when cloned repo isn't called hdl
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Updated Versal projects to use the Transceiver Subsystem which was merged to main |
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RetriggerCI |
Adds AD9084-EBZ (Apollo) base design for the following carriers: - vcu118 - vck190 - vpk180 - fm87 Signed-off-by: Bogdan Luncan <[email protected]>
Allow to be sourced from testbench Signed-off-by: Jorge Marques <[email protected]>
Simplifies identifying which SPI are 4-wire or 3-wire. Also, for vck190, since the SPI interface only has 3 outputs, route adf4030 to the third. The adf4030 linux driver defaults to 4-wire, and 3-wire (datasheet default) can be set through devicetree property adi,spi-3wire-enable. Signed-off-by: Jorge Marques <[email protected]>
…/4w and unused slave devices Signed-off-by: Filip Gherman <[email protected]>
Signed-off-by: Bogdan Luncan <[email protected]>
…ility cores Signed-off-by: Bogdan Luncan <[email protected]>
…e automatically Signed-off-by: Bogdan Luncan <[email protected]>
Signed-off-by: Bogdan Luncan <[email protected]>
…from description Signed-off-by: Bogdan Luncan <[email protected]>
Signed-off-by: Bogdan Luncan <[email protected]>
Signed-off-by: Bogdan Luncan <[email protected]>
Signed-off-by: Bogdan Luncan <[email protected]>
Signed-off-by: Filip Gherman <[email protected]>
Signed-off-by: Filip Gherman <[email protected]>
Signed-off-by: Filip Gherman <[email protected]>
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…x_jesd Signed-off-by: Filip Gherman <[email protected]>
The first time the board is powered on, because the reference clock going to the transceivers is not stable until the clock chip is programmerd, the LCPLLs are being locked wrong and the master reset controller inside the QUADs gets stuck. The fix is to manually reset the LCPLLs and ILOs inside the QUAD after the clock chip is programmed. Signed-off-by: Bogdan Luncan <[email protected]>
Signed-off-by: Bogdan Luncan <[email protected]>
…tive quads The versal transceiver subsystem doesn't allow you to route lanes to non-consecutive quads. This caused issues on AD9084 for use cases where L < 4 because we couldn't connect side A to one quad and side B to another quad. Signed-off-by: Bogdan Luncan <[email protected]>
Because side B is connected to the first quad and side A on the second one, the Versal transceiver subsystem didn't allow us to swap them. Becaus we now support non-consecutive quads we can map them correctly. We can also support building side B use cases only for VCK190. Signed-off-by: Bogdan Luncan <[email protected]>
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gastmaier
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Side inversion fix working on vck190. |
Signed-off-by: Bogdan Luncan <[email protected]>
Signed-off-by: Bogdan Luncan <[email protected]>
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…support for non-consecutive quads Removed duplicate code by wrapping code fragments in functions. Non-consecutive quad mode is needed by AD9084 because its sides are mapped backwards to the quads (side B goes to the first one, side A goes to the second one). The Versal Transceiver Subsystem doesn't allow you to map Quad0 to Quad1 and vice-versa so you need to instantiate two of them with one quad each. This method also allows us to build the VCK190 design for side B only or to build the VCK190/VPK180 designs with less than 4 lanes. Signed-off-by: Bogdan Luncan <[email protected]>
… VCK190 Side B only Signed-off-by: Bogdan Luncan <[email protected]>
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…tion Signed-off-by: Bogdan Luncan <[email protected]>
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PR Description
Adds the AD9084 (Apollo) design.
Requires the following PRs to be merged to main before this one:
After they are merged, I'll rebase this branch and re-check that the projects are building.
PR Type
PR Checklist