Skip to content

projects/adrv9009: Updated README files #1730

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 1 commit into
base: main
Choose a base branch
from
Open

projects/adrv9009: Updated README files #1730

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
18 changes: 18 additions & 0 deletions projects/adrv9009/README.md
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,18 @@
# ADRV9009 HDL Project

- Evaluation board product page: [EVAL-ADRV9008-9009](https://www.analog.com/eval-adrv9008-9009)
- System documentation:
- [User Guide](https://analogdevicesinc.github.io/documentation/eval/user-guide/transceiver/adrv9009/index.html)
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Leave just the first link, for the user guide

- [IIO Oscilloscope](https://analogdevicesinc.github.io/documentation/software/iio-oscilloscope/adrv9009/index.html)
- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/adrv9009/index.html

## Supported parts

| Part name | Description |
|---------------------------------------------|------------------------------------------------------------------|
| [ADRV9009](https://www.analog.com/adrv9009) | Integrated Dual RF Tx, Rx, and Observation Rx |
| [AD7291](https://www.analog.com/ad7291) | 8 channels, I2C, 12-bit SAR ADC with built-in temperature sensor |

## Building the project

Please enter the folder for the FPGA carrier you want to use and read the README.md.
9 changes: 0 additions & 9 deletions projects/adrv9009/Readme.md
View file
Open in desktop

This file was deleted.

12 changes: 12 additions & 0 deletions projects/adrv9009/a10soc/README.md
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@
# ADRV9009/A10SOC HDL Project

## Building the project

This project is not parameterizable, it has a fixed configuration.

```
cd projects/adrv9001/a10soc
make
```

Corresponding device tree: [socfpga_arria10_socdk_adrv9009_jesd204_fsm.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_adrv9009_jesd204_fsm.dts)
10 changes: 10 additions & 0 deletions projects/adrv9009/s10soc/README.md
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,10 @@
# ADRV9009/S10SOC HDL Project

## Building the project

This project is not parameterizable, it has a fixed configuration.

```
cd projects/adrv9001/s10soc
make
```
23 changes: 23 additions & 0 deletions projects/adrv9009/zc706/README.md
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,23 @@
# ADRV9009/ZC706 HDL Project

## Building the project

```
cd projects/adrv9001/zc706
make
```

All of the RX/TX link modes can be found in the [ADRV9009 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/ADRV9009.pdf). We offer support for only a few of them.

If other configurations are desired, then the parameters from the HDL project (found in *zc706/system_project.tcl*) need to be changed, as well as the Linux/no-OS project configurations.

The overwritable parameters from the environment:

- [RX/TX]_JESD_M: RX: **4** & TX: **4**; [RX/TX] number of converters per link
- [RX/TX]_JESD_L: RX: **2** & TX: **4**; [RX/TX] number of lanes per link
- [RX/TX]_JESD_S: RX: **1** & TX: **1**; [RX/TX] number of samples per converter per frame
- RX_OS_JESD_M: **2**; number of converters per link
- RX_OS_JESD_L: **2**; number of lanes per link
- RX_OS_JESD_S: **1**; number of samples per frame

Corresponding device tree: [zynq-zc706-adv7511-adrv9009-jesd204-fsm.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zc706-adv7511-adrv9009-jesd204-fsm.dts)
23 changes: 23 additions & 0 deletions projects/adrv9009/zcu102/README.md
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,23 @@
# ADRV9009/ZCU102 HDL Project

## Building the project

```
cd projects/adrv9001/zcu102
make
```

All of the RX/TX link modes can be found in the [ADRV9009 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/ADRV9009.pdf). We offer support for only a few of them.

If other configurations are desired, then the parameters from the HDL project (found in *zcu102/system_project.tcl*) need to be changed, as well as the Linux/no-OS project configurations.

The overwritable parameters from the environment:

- [RX/TX]_JESD_M: RX: **4** & TX: **4**; [RX/TX] number of converters per link
- [RX/TX]_JESD_L: RX: **2** & TX: **4**; [RX/TX] number of lanes per link
- [RX/TX]_JESD_S: RX: **1** & TX: **1**; [RX/TX] number of samples per converter per frame
- RX_OS_JESD_M: **2**; number of converters per link
- RX_OS_JESD_L: **2**; number of lanes per link
- RX_OS_JESD_S: **1**; number of samples per frame

Corresponding device tree: [zynqmp-zcu102-rev10-adrv9009-jesd204-fsm.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9009-jesd204-fsm.dts)
Loading