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ADRV9026 readme & doc #1683

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docs/projects/adrv9026:Add supported devices
BCapota Apr 16, 2025
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projects/adrv9026:Add READMEs
BCapota Apr 16, 2025
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13 changes: 10 additions & 3 deletions docs/projects/adrv9026/index.rst
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Expand Up @@ -17,6 +17,13 @@ Supported boards

- :adi:`ADRV9026/ADRV9029 <EVAL-ADRV9026>`

Supported devices
-------------------------------------------------------------------------------

- :adi:`ADRV9026`
- :adi:`ADRV9029`
- ADRV9025 (OBSOLETE)

Supported carriers
-------------------------------------------------------------------------------

Expand All @@ -30,12 +37,12 @@ Supported carriers
* - :adi:`ADRV9026/ADRV9029 <EVAL-ADRV9026>`
- :intel:`A10SoC <content/www/us/en/products/details/fpga/development-kits/arria/10-sx.html>`
- FMCA
* -
- :xilinx:`ZCU102`
- FMC HPC1
* -
- :xilinx:`VCU118`
- FMCP
* -
- :xilinx:`ZCU102`
- FMC HPC1

Block design
-------------------------------------------------------------------------------
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16 changes: 16 additions & 0 deletions projects/adrv9026/README.md
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# ADRV9026 HDL Project

- Evaluation board product page: [EVAL-ADRV9026/ADRV9029](https://www.analog.com/eval-adrv9026)
- System documentation: https://wiki.analog.com/resources/eval/user-guides/adrv9026/quickstart
- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/adrv9026/index.html

## Supported parts

| Part name | Description |
|---------------------------------------------|-----------------------------------------------------------|
| [ADRV9026](https://www.analog.com/ADRV9026) | Integrated, Quad RF Transceiver with Observation Path |
| [ADRV9029](https://www.analog.com/ADRV9029) | Integrated, Quad RF Transceiver with Observation Path |

## Building the project

Please enter the folder for the FPGA carrier you want to use and read the README.md.
10 changes: 10 additions & 0 deletions projects/adrv9026/a10soc/README.md
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# ADRV9026/A10SOC HDL Project

## Building the project

```
cd projects/adrv9026/a10soc
make
```

Corresponding device tree: [socfpga_arria10_socdk_adrv9025.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_adrv9025.dts)
23 changes: 23 additions & 0 deletions projects/adrv9026/vcu118/README.md
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# ADRV9026/VCU118 HDL Project

## Building the project

```
cd projects/adrv9026/vcu118
make
```

All of the RX/TX link modes can be found in the [ADRV9026 data sheet](https://www.analog.com/media/radioverse-adrv9026/adrv9026.pdf). We offer support for only a few of them.

The overwritable parameters from the environment:

- JESD_MODE - link layer encoder mode used;
- 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical layer
- 64B66B - 64b66b link layer defined in JESD204C, uses Xilinx IP as Physical layer
- [RX/TX]_LANE_RATE - lane rate of the [RX/TX] link (RX: MxFE to FPGA/TX: FPGA to MxFE)
- [RX/TX]_NUM_LINKS - [RX/TX] number of links, which matches the number of MxFE devices
- [RX/TX]_JESD_M - [RX/TX] number of converters per link
- [RX/TX]_JESD_L - [RX/TX] number of lanes per link
- [RX/TX]_JESD_S - [RX/TX] number of samples per converter per frame

Corresponding device tree: [vcu118_adrv9025.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/microblaze/boot/dts/vcu118_adrv9025.dts)
23 changes: 23 additions & 0 deletions projects/adrv9026/zcu102/README.md
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# ADRV9026/ZCU102 HDL Project

## Building the project

```
cd projects/adrv9026/zcu102
make
```

All of the RX/TX link modes can be found in the [ADRV9026 data sheet](https://www.analog.com/media/radioverse-adrv9026/adrv9026.pdf). We offer support for only a few of them.

The overwritable parameters from the environment:

- JESD_MODE - link layer encoder mode used;
- 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical layer
- 64B66B - 64b66b link layer defined in JESD204C, uses Xilinx IP as Physical layer
- [RX/TX]_LANE_RATE - lane rate of the [RX/TX] link (RX: MxFE to FPGA/TX: FPGA to MxFE)
- [RX/TX]_NUM_LINKS - [RX/TX] number of links, which matches the number of MxFE devices
- [RX/TX]_JESD_M - [RX/TX] number of converters per link
- [RX/TX]_JESD_L - [RX/TX] number of lanes per link
- [RX/TX]_JESD_S - [RX/TX] number of samples per converter per frame

Corresponding device tree: [zynqmp-zcu102-rev10-adrv9025.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9025.dts)
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