All pull requests

Pull requests

• Write EDIF as parallel pieces; ParallelismTools joinOrdered()/joinUnordered() and chunking

  needs new release
  #1475·eddieh-xlnx opened Oct 20, 2026Collaborator·

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• 2026.1.2

  #1472·clavin-xlnx opened Oct 16, 2026Member·

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• Write out libraries in the correct order in EDIFNetlist.exportEDIF

  #1470·dkter opened Oct 16, 2026·

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  2

• Add opt_design-style netlist constant propagation and sweep

  #1468·clavin-xlnx opened Oct 15, 2026Member·

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• [CombineDcps] Add a command-line tool to combine a design with implementations of its black boxes

  #1465·clavin-xlnx opened Oct 12, 2026Member·

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  7

• [DesignTools] populateBlackBox(): carry over the circuits' BEL attributes

  #1464·clavin-xlnx opened Oct 12, 2026Member·

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  5

• [ConstraintTools] Scope get_ports to the black box in merged constraints

  #1463·clavin-xlnx opened Oct 12, 2026Member·

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  11

• [ConstraintTools] Add addBlackBoxConstraints()

  #1457·clavin-xlnx opened Oct 9, 2026Member·

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  16

• [DesignTools] populateBlackBox(): keep each PIP once on merged nets

  #1454·clavin-xlnx opened Oct 9, 2026Member·

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  5

• [DesignTools] populateBlackBox(): replace site instances that only lock BELs

  needs new release
  #1451·clavin-xlnx opened Oct 9, 2026Member·

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  7

• [DesignTools] Accept black box inouts resolved by the filling circuit

  #1450·clavin-xlnx opened Oct 9, 2026Member·

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  6

• Drop populateBlackBox()'s workarounds

  needs new release
  #1440·eddieh-xlnx opened Oct 6, 2026Collaborator·

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  1

• [TestSiteInst] Add testGetSiteWireIndicesFromNetRoundTripsWithinSiteWireCount()

  bugneeds new release
  #1428·eddieh-xlnx opened Sep 18, 2026Collaborator·

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• Add SDF parser, writer, and timing graph annotator

  #1419·clavin-xlnx opened Sep 2, 2026Member·

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  8

• ModuleInst: reject placements landing on depopulated SLL UBUMP nodes

  #1401·andrewb1999 opened Aug 4, 2026Contributor·

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  3

• Add PBlockStaticNetFixer to Simplify Relocation of Vivado Routed Modules

  #1400·andrewb1999 opened Aug 4, 2026Contributor·

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  12

• [EDIFNetlist] NetlistValidator - A tool for checking output EDIF for inconsistencies before they are found on Vivado import

  #1387·clavin-xlnx opened Jun 25, 2026Member·

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• Enumerate Versal Delay Paths [No timing information]

  #1371·clavin-xlnx opened May 21, 2026Member·

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• Add backward routing for RapidWright.

  #1346·kylepham-amd opened Jan 7, 2026Contributor·

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  9

• Fix DesignTools.getConnectionPips for sinks driven by lut constant generators

  #1231·reillymck opened Jun 20, 2025Contributor·

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  5

• Example Clock Signal Tracer

  #1216·clavin-xlnx opened Jun 12, 2025Member·

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• [TestExamples] Test PipelineGenerator with Vivado

  #1193·eddieh-xlnx opened May 20, 2025Collaborator·

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• [EDIFNetlist] exportEDIF() to use getLibrariesInExportOrder()

  #1148·eddieh-xlnx opened Feb 14, 2025Collaborator·

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  1

• [DREAMPlaceFPGA] Add placeDesign() wrapper for DREAMPlaceFPGA

  #1137·eddieh-xlnx opened Jan 13, 2025Collaborator·

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  1

• [RWRoute] Adjust wire base costs + cross SLR estimates

  #1030·eddieh-xlnx opened Jul 12, 2024Collaborator·

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  1