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184 Open 449 Closed
184 Open 449 Closed
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Issues list

ghdl compiled with llvm-jit support
#1105 opened Mar 12, 2025 by csantosb
Instructions on installing with Guix
#1104 opened Mar 9, 2025 by csantosb
Limit which variables to dump to waveform file
#1103 opened Mar 7, 2025 by oscargus
nvc: Waveform files are only generated with --gui option
#1099 opened Feb 25, 2025 by tmeissner
1
3
Verification Component Context missing axi_lite_master
#1093 opened Jan 16, 2025 by F2g-attocube
Feature Request: Compile Files in Chunks
#1088 opened Jan 10, 2025 by bwabbersen
1
Add option "add_help=False" when creating an ArgumentParser object.
#1083 opened Dec 12, 2024 by PelleEikeberg
2
Add support for feature complete external VHDL parser Parsing
#1080 opened Dec 11, 2024 by LarsAsplund
[BUG] Get wrong tcl on Python 3.10 or lator with Windows
#1075 opened Dec 1, 2024 by mikeda-nagano
2
[Bug] Riviera-PRO component binding not working between libraries
#1073 opened Nov 20, 2024 by SzymonHitachi
1
28
ghdl Coverage : unknown command option '-fprofile-arcs'
#1066 opened Oct 8, 2024 by Electronics4ever
1
Check code quality in a continuous way
#1059 opened Sep 20, 2024 by racodond
3
Doesn't work with the GHDL Snap package
#1058 opened Sep 15, 2024 by interfect
1
[FEATURE] Print/save commands outputs/logs from (ModelSim/QuestaSim/Questa Base)
#1057 opened Sep 12, 2024 by nselvara
2
Runtime data input from Python to VHDL
#1050 opened Aug 9, 2024 by suryabvsp
1
OSVVM update
#1046 opened Aug 2, 2024 by c-thaler
9
[Feature] Make check_equal a generic procedure Enhancement
#1030 opened Jun 17, 2024 by nselvara
5
Unaligned access to AXI read slave yields incorrect data
#1019 opened May 24, 2024 by ru551n
4
Is there a way to specify minimum cycles between stalls for AXI stream VC?
#1013 opened May 1, 2024 by cjmeyer
1
Question about "blocking" specifically around the bus_master VCI
#1012 opened May 1, 2024 by nathanaelhuffman
1
Indexing order for 3D integer_array_t doesn't make sense
#1011 opened Apr 30, 2024 by bradleyharden
How to specify test case(s) to run after creating a VUnit instance?
#1010 opened Apr 23, 2024 by cjmeyer
2
VUnit testcases fail if the testcase name contains a colon (SystemVerilog)
#1009 opened Apr 17, 2024 by PossenigM
2
VUnit testcases fail if the last character in a testcase name is a whitespace (VHDL) Bug
#1008 opened Apr 17, 2024 by PossenigM
Force stop simulation
#1006 opened Mar 22, 2024 by nselvara
4
ProTip! no:milestone will show everything without a milestone.