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Update tricore td files #4

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99 changes: 94 additions & 5 deletions lib/Target/TriCore/TriCore.td
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Original file line number Diff line number Diff line change
Expand Up @@ -21,25 +21,114 @@ include "llvm/Target/Target.td"
// Descriptions
//===----------------------------------------------------------------------===//

// Specify whether target support specific TRICORE ISA variants.

def HasV110Ops : SubtargetFeature<"v1.1", "HasV110Ops", "true",
"Support TriCore v1.1 instructions",
[]>;
def HasV120Ops : SubtargetFeature<"v1.2", "HasV120Ops", "true",
"Support TriCore v1.2 instructions",
[]>;
def HasV130Ops : SubtargetFeature<"v1.3", "HasV130Ops", "true",
"Support TriCore v1.3 instructions",
[]>;
def HasV131Ops : SubtargetFeature<"v1.3.1", "HasV131Ops", "true",
"Support TriCore v1.3.1 instructions",
[]>;
def HasV160Ops : SubtargetFeature<"v1.6", "HasV160Ops", "true",
"Support TriCore v1.6 instructions",
[]>;
def HasV161Ops : SubtargetFeature<"v1.6.1", "HasV161Ops", "true",
"Support TriCore v1.6.1 instructions",
[]>;
def HasV162Ops : SubtargetFeature<"v1.6.2", "HasV162Ops", "true",
"Support TriCore v1.6.2 instructions",
[]>;

def HasV110 : Predicate<"HasV120Ops()">, AssemblerPredicate<(all_of HasV110Ops), "v1.1">;
def HasV120 : Predicate<"HasV120Ops()">, AssemblerPredicate<(all_of HasV120Ops), "v1.2">;
def HasV130 : Predicate<"HasV130Ops()">, AssemblerPredicate<(all_of HasV130Ops), "v1.3">;
def HasV131 : Predicate<"HasV131Ops()">, AssemblerPredicate<(all_of HasV131Ops), "v1.3.1">;
def HasV160 : Predicate<"HasV160Ops()">, AssemblerPredicate<(all_of HasV160Ops), "v1.6">;
def HasV161 : Predicate<"HasV161Ops()">, AssemblerPredicate<(all_of HasV161Ops), "v1.6.1">;
def HasV162 : Predicate<"HasV162Ops()">, AssemblerPredicate<(all_of HasV162Ops), "v1.6.2">;

def HasV120_UP : Predicate<"HasV120Ops() || HasV130Ops() || HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops()">
, AssemblerPredicate<(any_of HasV120Ops, HasV130Ops, HasV131Ops, HasV160Ops, HasV161Ops, HasV162Ops), "v120up">;
def HasV130_UP : Predicate<"HasV130Ops() || HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops()">
, AssemblerPredicate<(any_of HasV130Ops, HasV131Ops, HasV160Ops, HasV161Ops, HasV162Ops), "v130up">;
def HasV131_UP : Predicate<"HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops()">
, AssemblerPredicate<(any_of HasV131Ops, HasV160Ops, HasV161Ops, HasV162Ops), "v131up">;
def HasV160_UP : Predicate<"HasV160Ops() || HasV161Ops() || HasV162Ops()">
, AssemblerPredicate<(any_of HasV160Ops, HasV161Ops, HasV162Ops), "v160up">;
def HasV161_UP : Predicate<"HasV161Ops() || HasV162Ops()">
, AssemblerPredicate<(any_of HasV161Ops, HasV162Ops), "v161up">;
def HasV162_UP : Predicate<"HasV162Ops()">
, AssemblerPredicate<(any_of HasV162Ops), "v162up">;

def HasV120_DN : Predicate<"HasV120Ops() || HasV110Ops()">,
AssemblerPredicate<(any_of HasV120Ops, HasV110Ops), "v120dn">;
def HasV130_DN : Predicate<"HasV130Ops() || HasV120Ops() || HasV110Ops()">,
AssemblerPredicate<(any_of HasV130Ops, HasV120Ops, HasV110Ops), "v130dn">;
def HasV131_DN : Predicate<"HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">,
AssemblerPredicate<(any_of HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v131dn">;
def HasV160_DN : Predicate<"HasV160Ops() || HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">,
AssemblerPredicate<(any_of HasV160Ops, HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v160dn">;
def HasV161_DN : Predicate<"HasV161Ops() || HasV160Ops() || HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">,
AssemblerPredicate<(any_of HasV161Ops, HasV160Ops, HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v161dn">;
def HasV162_DN : Predicate<"HasV162Ops() || HasV161Ops() || HasV160Ops() || HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">,
AssemblerPredicate<(any_of HasV162Ops, HasV161Ops, HasV160Ops, HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v162dn">;


class Architecture<string fname, string aname, list<SubtargetFeature> features = []>
: SubtargetFeature<fname, "TriCoreArch", aname,
!strconcat(aname, " architecture"), features>;

class ProcNoItin<string Name, list<SubtargetFeature> Features>
: Processor<Name, NoItineraries, Features>;


def TRICORE_V1_1 : Architecture<"tricore-v1.1", "TRICOREv110", [HasV110Ops]>;
def TRICORE_V1_2 : Architecture<"tricore-V1.2", "TRICOREv120", [HasV120Ops]>;
def TRICORE_V1_3 : Architecture<"tricore-V1.3", "TRICOREv130", [HasV130Ops]>;
def TRICORE_V1_3_1 : Architecture<"tricore-V1.3.1", "TRICOREv131", [HasV131Ops]>;
def TRICORE_V1_6 : Architecture<"tricore-V1.6", "TRICOREv160", [HasV160Ops]>;
def TRICORE_V1_6_1 : Architecture<"tricore-V1.6.1", "TRICOREv161", [HasV161Ops]>;
def TRICORE_V1_6_2 : Architecture<"tricore-V1.6.2", "TRICOREv162", [HasV162Ops]>;
def TRICORE_PCP : Architecture<"tricore-PCP", "TRICOREpcp">;
def TRICORE_PCP2 : Architecture<"tricore-PCP2", "TRICOREpcp2">;

def TRICORE_RIDER_A : Architecture<"tricore-rider-a", "TRICOREv110", [TRICORE_V1_1]>;


include "TriCoreRegisterInfo.td"
include "TriCoreInstrInfo.td"
include "TriCoreCallingConv.td"

def TriCoreInstrInfo : InstrInfo;

//===----------------------------------------------------------------------===//
// TriCore processors supported.
//===----------------------------------------------------------------------===//

class Proc<string Name, list<SubtargetFeature> Features>
: Processor<Name, NoItineraries, Features>;
def : ProcNoItin<"tc1796", [TRICORE_V1_3]>;
def : ProcNoItin<"tc1797", [TRICORE_V1_3_1]>;
def : ProcNoItin<"tc27x", [TRICORE_V1_6_1]>;
def : ProcNoItin<"tc161", [TRICORE_V1_6_1]>;
def : ProcNoItin<"tc162", [TRICORE_V1_6_2]>;
def : ProcNoItin<"tc16", [TRICORE_V1_6]>;
def : ProcNoItin<"tc131", [TRICORE_V1_3_1]>;
def : ProcNoItin<"tc13", [TRICORE_V1_3]>;

def TriCoreAsmWriter : AsmWriter {
int PassSubtarget = 1;
}

def : Proc<"generic", []>;
def TriCoreInstrInfo : InstrInfo;

//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//

def TriCore : Target {
let InstructionSet = TriCoreInstrInfo;
let AssemblyWriters = [TriCoreAsmWriter];
}
42 changes: 21 additions & 21 deletions lib/Target/TriCore/TriCoreInstrFormats.td
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7,8 +7,6 @@
//
//===----------------------------------------------------------------------===//

//include "llvm/Target/Target.td" // Include for debugging purpose only

//===----------------------------------------------------------------------===//
// Describe TriCore instructions format
//
Expand All @@ -18,10 +16,17 @@
// op2 - secondary operation code
// s1 - source register 1
// s2 - source register 2
// s3 - source register 3
// d - destination register
// n - multiplication shift value (0b00 or 0b01)
// const9 - 9 bits immediate value
// disp24 - 24 bits displacement value
// b - bit value
// n -
// - multiplication result shift value (0b00 or 0b01)
// - address shift value in add scale
// - default to zero in all other operations using the RR format
// - coprocessor number for coprocessor instructions
// const[b=(4|9|16)] - b bits immediate value
// disp[b=(4|8|15|24)] - b bits displacement value
// off[b=(4|10|16)] - b bits offset value
//
//===----------------------------------------------------------------------===//

Expand Down Expand Up @@ -168,7 +173,6 @@ class SLRO<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
class SR<bits<8> op1, bits<4> op2, dag outs, dag ins, string asmstr,
list<dag> pattern> : T16<outs, ins, asmstr, pattern> {

bits<4> op2;
bits<4> s1_d;

let Inst{15-12} = op2;
Expand Down Expand Up @@ -226,11 +230,7 @@ class SRR<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
// 16-bit SRRS Instruction Format: <s2|s1/d|n|op1>
//===----------------------------------------------------------------------===//
class SRRS<bits<6> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstTriCore<outs, ins, asmstr, pattern> {

field bits<16> Inst;
let Size = 2;
field bits<16> SoftFail = 0;
: T16<outs, ins, asmstr, pattern> {

bits<4> s2;
bits<4> s1_d;
Expand Down Expand Up @@ -489,7 +489,7 @@ class RCPW<bits<8> op1, bits<2> op2 , dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
// 32-bit RCR Instruction Format: <d|s3|op2|const9|s1|op1>
//===----------------------------------------------------------------------===//
class RCR<bits<8> op1, bits<3> op2 , dag outs, dag ins, string asmstr,
class RCR<bits<8> op1, bits<3> op2, dag outs, dag ins, string asmstr,
list<dag> pattern> : T32<outs, ins, asmstr, pattern> {

bits<4> d;
Expand All @@ -509,7 +509,7 @@ class RCR<bits<8> op1, bits<3> op2 , dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
// 32-bit RCRR Instruction Format: <d|s3|op2|-|const4|s1|op1>
//===----------------------------------------------------------------------===//
class RCRR<bits<8> op1, bits<3> op2 , dag outs, dag ins, string asmstr,
class RCRR<bits<8> op1, bits<3> op2, dag outs, dag ins, string asmstr,
list<dag> pattern> : T32<outs, ins, asmstr, pattern> {

bits<4> d;
Expand All @@ -530,7 +530,7 @@ class RCRR<bits<8> op1, bits<3> op2 , dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
// 32-bit RCRW Instruction Format: <d|s3|op2|width|const4|s1|op1>
//===----------------------------------------------------------------------===//
class RCRW<bits<8> op1, bits<3> op2 , dag outs, dag ins, string asmstr,
class RCRW<bits<8> op1, bits<3> op2, dag outs, dag ins, string asmstr,
list<dag> pattern> : T32<outs, ins, asmstr, pattern> {

bits<4> d;
Expand Down Expand Up @@ -629,7 +629,7 @@ class RR2<bits<8> op1, bits<12> op2, dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
// 32-bit RRPW Instruction Format: <d|pos|op2|width|s2|s1|op1>
//===----------------------------------------------------------------------===//
class RRPW<bits<8> op1, bits<2> op2 , dag outs, dag ins, string asmstr,
class RRPW<bits<8> op1, bits<2> op2, dag outs, dag ins, string asmstr,
list<dag> pattern> : T32<outs, ins, asmstr, pattern> {

bits<4> d;
Expand All @@ -651,7 +651,7 @@ class RRPW<bits<8> op1, bits<2> op2 , dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
// 32-bit RRR Instruction Format: <d|s3|op2|-|n|s2|s1|op1>
//===----------------------------------------------------------------------===//
class RRR<bits<8> op1, bits<4> op2 , dag outs, dag ins, string asmstr,
class RRR<bits<8> op1, bits<4> op2, dag outs, dag ins, string asmstr,
list<dag> pattern> : T32<outs, ins, asmstr, pattern> {

bits<4> d;
Expand All @@ -674,7 +674,7 @@ class RRR<bits<8> op1, bits<4> op2 , dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
// 32-bit RRR1 Instruction Format: <d|s3|op2|n|s2|s1|op1>
//===----------------------------------------------------------------------===//
class RRR1<bits<8> op1, bits<6> op2 , dag outs, dag ins, string asmstr,
class RRR1<bits<8> op1, bits<6> op2, dag outs, dag ins, string asmstr,
list<dag> pattern> : T32<outs, ins, asmstr, pattern> {

bits<4> d;
Expand All @@ -696,7 +696,7 @@ class RRR1<bits<8> op1, bits<6> op2 , dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
// 32-bit RRR2 Instruction Format: <d|s3|op2|s2|s1|op1>
//===----------------------------------------------------------------------===//
class RRR2<bits<8> op1, bits<8> op2 , dag outs, dag ins, string asmstr,
class RRR2<bits<8> op1, bits<8> op2, dag outs, dag ins, string asmstr,
list<dag> pattern> : T32<outs, ins, asmstr, pattern> {

bits<4> s1;
Expand All @@ -716,7 +716,7 @@ class RRR2<bits<8> op1, bits<8> op2 , dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
// 32-bit RRRR Instruction Format: <d|s3|op2|-|s2|s1|op1>
//===----------------------------------------------------------------------===//
class RRRR<bits<8> op1, bits<3> op2 , dag outs, dag ins, string asmstr,
class RRRR<bits<8> op1, bits<3> op2, dag outs, dag ins, string asmstr,
list<dag> pattern> : T32<outs, ins, asmstr, pattern> {

bits<4> d;
Expand All @@ -737,7 +737,7 @@ class RRRR<bits<8> op1, bits<3> op2 , dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
// 32-bit RRRW Instruction Format: <d|s3|op2|width|s2|s1|op1>
//===----------------------------------------------------------------------===//
class RRRW<bits<8> op1, bits<3> op2 , dag outs, dag ins, string asmstr,
class RRRW<bits<8> op1, bits<3> op2, dag outs, dag ins, string asmstr,
list<dag> pattern> : T32<outs, ins, asmstr, pattern> {

bits<4> d;
Expand All @@ -759,7 +759,7 @@ class RRRW<bits<8> op1, bits<3> op2 , dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
// 32-bit SYS Instruction Format: <-|op2|-|s1/d|op1>
//===----------------------------------------------------------------------===//
class SYS<bits<8> op1, bits<6> op2 , dag outs, dag ins, string asmstr,
class SYS<bits<8> op1, bits<6> op2, dag outs, dag ins, string asmstr,
list<dag> pattern> : T32<outs, ins, asmstr, pattern> {

bits<4> s1_d;
Expand Down
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