[pull] master from verilog-to-routing:master #565
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github-actions
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removed
VPR
libarchfpga
lang-python
scripts
libvtrutil
tests
liblog
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[Pack] Removed Pb Pin Scratchpad
Remove an unsed hash functor
…hout_extension_leads_to_segfault attempt to load arch xml file without extension leads to segfault
update taskresolver to handle latest critical path UI layout
…sub-tiles of different types
[Router] Fix intra-cluster pin handling for tiles with heterogeneous subtiles
The CAD types header file does not belong in libarchfpga since it was only really used in the prepacker of VPR. It makes several references to the pb_graph structure which I would ultimately like to move into VPR entirely.
…ypes [LibArchFPGA] Moved CAD Types out of Lib
The format test for CPP was done through a bash script which calls make format under the hood. The issue was that if make format fails, it thinks that the formatting is good, which is bad. I have fixed the script so that it actually fails if make format fails. The thing that was causing make format to fail was that the dependencies that VPR needs to build were not installed. Added these dependencies.
The formatter was failing on some python files since they were using the Python2 syntax for the print statements instead of the Python3 syntax.
Run make format-py to fix all Python format issues.
Now that the CI test is fixed, I have resolved all outstanding format issues.
[CI] Fix CPP Format Issue
Removing 3D Attributes Script
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