Fix sp align

.gitignore

@@ -1,3 +1,5 @@
 /target
 /.vscode
 .DS_Store
+*.swp
+*.swo

src/aarch64/asm.rs

@@ -139,7 +139,7 @@ pub fn flush_tlb(vaddr: Option<VirtAddr>) {
         #[cfg(not(feature = "arm-el2"))]
         unsafe {
             // TLB Invalidate by VMID, All at stage 1, EL1
-            asm!("tlbi vmalle1; dsb sy; isb")
+            asm!("dsb sy; isb; tlbi vmalle1; dsb sy; isb")
         }
         #[cfg(feature = "arm-el2")]
         unsafe {

src/aarch64/context.rs

@@ -12,6 +12,9 @@ pub struct TrapFrame {
     pub elr: u64,
     /// Saved Process Status Register (SPSR_EL1).
     pub spsr: u64,
+
+    /// make sure the size is 16 bytes aligned
+    pub __pad: [u8; 8],
 }
 
 impl fmt::Debug for TrapFrame {

src/aarch64/trap.rs

@@ -104,12 +104,14 @@ fn aarch64_trap_handler(tf: &mut TrapFrame, kind: TrapKind, source: TrapSource)
                     tf.elr += 4;
                 }
                 e => {
+                    let vaddr = va!(FAR_EL1.get() as usize);
                     panic!(
-                        "Unhandled synchronous exception {:?} @ {:#x}: ESR={:#x} (EC {:#08b}, ISS {:#x})\n{}",
+                        "Unhandled synchronous exception {:?} @ {:#x}: ESR={:#x} (EC {:#08b}, FAR: {:#x} ISS {:#x})\n{}",
                         e,
                         tf.elr,
                         esr.get(),
                         esr.read(ESR_EL1::EC),
+                        vaddr,
                         iss,
                         tf.backtrace()
                     );

src/aarch64/uspace.rs

@@ -39,6 +39,7 @@ impl UserContext {
                     + SPSR_EL1::I::Unmasked
                     + SPSR_EL1::F::Masked)
                     .value,
+                __pad: [0; 8],
             },
             sp: ustack_top.as_usize() as _,
             tpidr: 0,