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Use multiclock mode in formal verification #38

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Use multiclock mode in formal verification #38

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4a441dd
Use multiclock mode in formal verification
janschiefer Feb 19, 2024
10dcbf0
Sync reset fixes
janschiefer Feb 19, 2024
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2 changes: 1 addition & 1 deletion build.sbt
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Expand Up @@ -2,7 +2,7 @@ ThisBuild / version := "1.0"
ThisBuild / scalaVersion := "2.12.18"
ThisBuild / organization := "org.example"

val spinalVersion = "1.10.1"
val spinalVersion = "dev"
val spinalCore = "com.github.spinalhdl" %% "spinalhdl-core" % spinalVersion
val spinalLib = "com.github.spinalhdl" %% "spinalhdl-lib" % spinalVersion
val spinalIdslPlugin = compilerPlugin("com.github.spinalhdl" %% "spinalhdl-idsl-plugin" % spinalVersion)
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3 changes: 2 additions & 1 deletion hw/spinal/projectname/Config.scala
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Expand Up @@ -7,7 +7,8 @@ object Config {
def spinal = SpinalConfig(
targetDirectory = "hw/gen",
defaultConfigForClockDomains = ClockDomainConfig(
resetActiveLevel = HIGH
resetActiveLevel = HIGH,
resetKind = SYNC
),
onlyStdLogicVectorAtTopLevelIo = true
)
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1 change: 1 addition & 0 deletions hw/spinal/projectname/MyTopLevelFormal.scala
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Expand Up @@ -7,6 +7,7 @@ import spinal.core.formal._
// See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Formal%20verification/index.html#installing-requirements
object MyTopLevelFormal extends App {
FormalConfig
.withConfig( Config.spinal )
.withBMC(10)
.doVerify(new Component {
val dut = FormalDut(MyTopLevel())
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2 changes: 1 addition & 1 deletion project/build.properties
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@@ -1 +1 @@
sbt.version=1.6.0
sbt.version=1.9.8