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Merged
merged 2 commits into from
May 19, 2025
Merged

Add riscv64 and Imagination Technologies GPUs support #232

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6621830
gh-231: add riscv64 and img gpu support
vkutuev May 16, 2025
d31dcaf
gh-231: add commentis with data copying workaround on img gpu
vkutuev May 18, 2025
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11 changes: 9 additions & 2 deletions CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -35,8 +35,15 @@ if (${CMAKE_SYSTEM_NAME} MATCHES "Windows")
list(APPEND SPLA_DEFINES SPLA_TARGET_WINDOWS)
elseif (${CMAKE_SYSTEM_NAME} MATCHES "Linux")
set(SPLA_TARGET_LINUX YES)
set(SPLA_ARCH "x64")
set(SPLA_EXT "so")
if (NOT SPLA_ARCH)
if (CMAKE_SYSTEM_PROCESSOR MATCHES riscv)
set(SPLA_ARCH "riscv")
else ()
set(SPLA_ARCH "x64")
endif ()
endif()
message(STATUS "Build Linux binaries for ${SPLA_ARCH} architecture")
list(APPEND SPLA_DEFINES SPLA_TARGET_LINUX)
elseif (${CMAKE_SYSTEM_NAME} MATCHES "Darwin")
set(SPLA_TARGET_MACOSX YES)
Expand Down Expand Up @@ -417,4 +424,4 @@ if (SPLA_BUILD_TESTS)
COMMENT "Copy ${TARGET_FILE} into test directory")
endforeach ()
endif ()
endif ()
endif ()
10 changes: 10 additions & 0 deletions src/opencl/cl_accelerator.cpp
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Expand Up @@ -108,6 +108,7 @@ namespace spla {
m_is_nvidia = false;
m_is_amd = false;
m_is_intel = false;
m_is_img = false;

if (m_vendor_name.find("Intel") != std::string::npos ||
m_vendor_name.find("intel") != std::string::npos ||
Expand Down Expand Up @@ -141,6 +142,15 @@ namespace spla {
// Likely, it is an integrated amd device
if (m_max_wgs <= 256 || m_max_cu == 1) m_wave_size = 16;
}
if (m_vendor_name.find("Imagination Technologies") != std::string::npos ||
m_vendor_name.find("IMG") != std::string::npos ||
m_vendor_name.find("img") != std::string::npos ||
m_vendor_id == 0x1010) {
m_vendor_code = VENDOR_CODE_IMG;
m_default_wgs = 32;
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Why you decided to set default wgs = 32, and not 64? It seems that 64 suits in most cases well

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RECOMMENDATION: If possible use a workgroup size of 32.

This is a recommendation from the official Imagination Technologies blog

m_wave_size = 32;
m_is_img = true;
}

if (m_vendor_code.empty()) {
LOG_MSG(Status::Error, "failed to match one of the pre-defined vendors");
Expand Down
3 changes: 3 additions & 0 deletions src/opencl/cl_accelerator.hpp
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Expand Up @@ -49,6 +49,7 @@
#define VENDOR_CODE_NVIDIA "nvidia"
#define VENDOR_CODE_INTEL "intel"
#define VENDOR_CODE_AMD "amd"
#define VENDOR_CODE_IMG "img"

namespace spla {

Expand Down Expand Up @@ -96,6 +97,7 @@ namespace spla {
[[nodiscard]] bool is_nvidia() const { return m_is_nvidia; }
[[nodiscard]] bool is_amd() const { return m_is_amd; }
[[nodiscard]] bool is_intel() const { return m_is_intel; }
[[nodiscard]] bool is_img() const { return m_is_img; }

private:
cl::Platform m_platform;
Expand Down Expand Up @@ -123,6 +125,7 @@ namespace spla {
bool m_is_nvidia = false;
bool m_is_amd = false;
bool m_is_intel = false;
bool m_is_img = false;

ankerl::svector<cl::CommandQueue, 2> m_queues;
};
Expand Down
8 changes: 4 additions & 4 deletions src/opencl/cl_format_coo_vec.hpp
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Expand Up @@ -105,18 +105,18 @@ namespace spla {
T* Ax,
const CLCooVec<T>& storage,
cl::CommandQueue& queue,
bool blocking = true) {
cl_mem_flags staging_flags = CL_MEM_READ_ONLY | CL_MEM_HOST_READ_ONLY | CL_MEM_ALLOC_HOST_PTR,
bool blocking = true) {
if (n_values == 0) {
LOG_MSG(Status::Ok, "nothing to do");
return;
}

const std::size_t buffer_size_Ai = n_values * sizeof(uint);
const std::size_t buffer_size_Ax = n_values * sizeof(T);
const auto flags = CL_MEM_READ_ONLY | CL_MEM_HOST_READ_ONLY | CL_MEM_ALLOC_HOST_PTR;

cl::Buffer staging_Ai(get_acc_cl()->get_context(), flags, buffer_size_Ai);
cl::Buffer staging_Ax(get_acc_cl()->get_context(), flags, buffer_size_Ax);
cl::Buffer staging_Ai(get_acc_cl()->get_context(), staging_flags, buffer_size_Ai);
cl::Buffer staging_Ax(get_acc_cl()->get_context(), staging_flags, buffer_size_Ax);

queue.enqueueCopyBuffer(storage.Ai, staging_Ai, 0, 0, buffer_size_Ai);
queue.enqueueCopyBuffer(storage.Ax, staging_Ax, 0, 0, buffer_size_Ax);
Expand Down
11 changes: 5 additions & 6 deletions src/opencl/cl_format_csr.hpp
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Expand Up @@ -84,16 +84,15 @@ namespace spla {
T* Ax,
CLCsr<T>& storage,
cl::CommandQueue& queue,
bool blocking = true) {
cl_mem_flags staging_flags = CL_MEM_READ_ONLY | CL_MEM_HOST_READ_ONLY | CL_MEM_ALLOC_HOST_PTR,
bool blocking = true) {
const std::size_t buffer_size_Ap = (n_rows + 1) * sizeof(uint);
const std::size_t buffer_size_Aj = n_values * sizeof(uint);
const std::size_t buffer_size_Ax = n_values * sizeof(T);

const auto flags = CL_MEM_READ_ONLY | CL_MEM_HOST_READ_ONLY | CL_MEM_ALLOC_HOST_PTR;

cl::Buffer staging_Ap(get_acc_cl()->get_context(), flags, buffer_size_Ap);
cl::Buffer staging_Aj(get_acc_cl()->get_context(), flags, buffer_size_Aj);
cl::Buffer staging_Ax(get_acc_cl()->get_context(), flags, buffer_size_Ax);
cl::Buffer staging_Ap(get_acc_cl()->get_context(), staging_flags, buffer_size_Ap);
cl::Buffer staging_Aj(get_acc_cl()->get_context(), staging_flags, buffer_size_Aj);
cl::Buffer staging_Ax(get_acc_cl()->get_context(), staging_flags, buffer_size_Ax);

queue.enqueueCopyBuffer(storage.Ap, staging_Ap, 0, 0, buffer_size_Ap);
queue.enqueueCopyBuffer(storage.Aj, staging_Aj, 0, 0, buffer_size_Aj);
Expand Down
5 changes: 3 additions & 2 deletions src/opencl/cl_format_dense_vec.hpp
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Expand Up @@ -77,9 +77,10 @@ namespace spla {
T* values,
CLDenseVec<T>& storage,
cl::CommandQueue& queue,
bool blocking = true) {
cl_mem_flags staging_flags = CL_MEM_READ_ONLY | CL_MEM_HOST_READ_ONLY | CL_MEM_ALLOC_HOST_PTR,
bool blocking = true) {
const std::size_t buffer_size = n_rows * sizeof(T);
cl::Buffer staging(get_acc_cl()->get_context(), CL_MEM_READ_ONLY | CL_MEM_HOST_READ_ONLY | CL_MEM_ALLOC_HOST_PTR, buffer_size);
cl::Buffer staging(get_acc_cl()->get_context(), staging_flags, buffer_size);

queue.enqueueCopyBuffer(storage.Ax, staging, 0, 0, buffer_size);
queue.enqueueReadBuffer(staging, blocking, 0, buffer_size, values);
Expand Down
10 changes: 9 additions & 1 deletion src/storage/storage_manager_matrix.hpp
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Expand Up @@ -146,7 +146,15 @@ namespace spla {
auto* cl_csr = s.template get<CLCsr<T>>();
auto* cpu_csr = s.template get<CpuCsr<T>>();
cpu_csr_resize(s.get_n_rows(), cl_csr->values, *cpu_csr);
cl_csr_read(s.get_n_rows(), cl_csr->values, cpu_csr->Ap.data(), cpu_csr->Aj.data(), cpu_csr->Ax.data(), *cl_csr, cl_acc->get_queue_default());
if (!cl_acc->is_img()) {
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I guess, comments with explanation and references to related documents are necessary here.

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Done

cl_csr_read(s.get_n_rows(), cl_csr->values, cpu_csr->Ap.data(), cpu_csr->Aj.data(), cpu_csr->Ax.data(), *cl_csr, cl_acc->get_queue_default());
} else {
// On Imagination Technologies devices copying data to staging buffer created with CL_MEM_READ_ONLY flag does not affect this buffer.
// According to the [documentation](https://registry.khronos.org/OpenCL/specs/3.0-unified/html/OpenCL_API.html#clEnqueueCopyBuffer),
// this flag should not affect copying, but you have to create a buffer without this flag to keep it correct.
cl_csr_read(s.get_n_rows(), cl_csr->values, cpu_csr->Ap.data(), cpu_csr->Aj.data(), cpu_csr->Ax.data(), *cl_csr, cl_acc->get_queue_default(),
CL_MEM_HOST_READ_ONLY | CL_MEM_ALLOC_HOST_PTR);
}
});
#endif
}
Expand Down
20 changes: 18 additions & 2 deletions src/storage/storage_manager_vector.hpp
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Expand Up @@ -126,7 +126,15 @@ namespace spla {
auto* cl_acc = get_acc_cl();
auto* cl_dense = s.template get<CLDenseVec<T>>();
auto* cpu_dense = s.template get<CpuDenseVec<T>>();
cl_dense_vec_read(s.get_n_rows(), cpu_dense->Ax.data(), *cl_dense, cl_acc->get_queue_default());
if (!cl_acc->is_img()) {
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I guess, comments with explanation and references to related documents are necessary here.

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Done

cl_dense_vec_read(s.get_n_rows(), cpu_dense->Ax.data(), *cl_dense, cl_acc->get_queue_default());
} else {
// On Imagination Technologies devices copying data to staging buffer created with CL_MEM_READ_ONLY flag does not affect this buffer.
// According to the [documentation](https://registry.khronos.org/OpenCL/specs/3.0-unified/html/OpenCL_API.html#clEnqueueCopyBuffer),
// this flag should not affect copying, but you have to create a buffer without this flag to keep it correct.
cl_dense_vec_read(s.get_n_rows(), cpu_dense->Ax.data(), *cl_dense, cl_acc->get_queue_default(),
CL_MEM_HOST_READ_ONLY | CL_MEM_ALLOC_HOST_PTR);
}
});
manager.register_converter(FormatVector::CpuCoo, FormatVector::AccCoo, [](Storage& s) {
auto* cpu_coo = s.template get<CpuCooVec<T>>();
Expand All @@ -138,7 +146,15 @@ namespace spla {
auto* cl_coo = s.template get<CLCooVec<T>>();
auto* cpu_coo = s.template get<CpuCooVec<T>>();
cpu_coo_vec_resize(cl_coo->values, *cpu_coo);
cl_coo_vec_read(cl_coo->values, cpu_coo->Ai.data(), cpu_coo->Ax.data(), *cl_coo, cl_acc->get_queue_default());
if (!cl_acc->is_img()) {
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I guess, comments with explanation and references to related documents are necessary here.

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Done

cl_coo_vec_read(cl_coo->values, cpu_coo->Ai.data(), cpu_coo->Ax.data(), *cl_coo, cl_acc->get_queue_default());
} else {
// On Imagination Technologies devices copying data to staging buffer created with CL_MEM_READ_ONLY flag does not affect this buffer.
// According to the [documentation](https://registry.khronos.org/OpenCL/specs/3.0-unified/html/OpenCL_API.html#clEnqueueCopyBuffer),
// this flag should not affect copying, but you have to create a buffer without this flag to keep it correct.
cl_coo_vec_read(cl_coo->values, cpu_coo->Ai.data(), cpu_coo->Ax.data(), *cl_coo, cl_acc->get_queue_default(),
CL_MEM_HOST_READ_ONLY | CL_MEM_ALLOC_HOST_PTR);
}
});
manager.register_converter(FormatVector::AccCoo, FormatVector::AccDense, [](Storage& s) {
auto* cl_acc = get_acc_cl();
Expand Down
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