Skip to content
View Sidshx's full-sized avatar
:octocat:
:octocat:
18 followers · 32 following

Achievements

Achievement: QuickdrawAchievement: Pull Sharkx2

Achievements

Achievement: QuickdrawAchievement: Pull Sharkx2

Block or report Sidshx

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Sidshx/README.md

Hi 👋! My name is Siddesh
A Digital Design & Verification Enthusiast! 🤖

c logo c logo c logo vim logo linux logo python logo ruby logo


GitHub Activity Snake 

Hello World!! 👋  
I'm Siddesh  

Passionate about **Computer Architecture, Memory Hierarchy, RTL Design, and Verification methodologies**, with extensive hands-on experience.  

🔹 Experience 

🚀 Design Verification (RV32IMFDAC and Vector on SHAKTI SoC) | Vyoma Systems, IIT Madras  
- Developed **design verification test plans**, generating **500+ assembly test cases** for RV32IMFDAC on SHAKTI SoC.  
- Explored RV-Vector extension, debugged, and documented **open-source test generators**, creating **reconfigurable assembly tests**.

⚡ Hardware Accelerator: ALRESCHA | CASL, UMD  
- Designed in **Verilog HDL**, optimized **sparse matrix computations**, achieving a **20% throughput improvement**.  

🔍 And diving deeper... 🚀

Pinned Loading

  1. LLC-cache-simulator LLC-cache-simulator Public

    A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement, multi-mode simulations, and comprehensive testing strategie…

    SystemVerilog 6 1

  2. siddharth23-8/32-bit-RISC-V-Cpu-Core siddharth23-8/32-bit-RISC-V-Cpu-Core Public

    Python 32 3

  3. Satya7733/Asyc_FIFO Satya7733/Asyc_FIFO Public

    This project contains asynchronous FIFO in System Verilog Design and Verification done in Class Based Verification and UVM

    SystemVerilog 2

  4. CMOS-NOR-Gate_IITH-Hackathon CMOS-NOR-Gate_IITH-Hackathon Public

    CMOS Implemented NOR Gate is designed using Synopsys custom design tools.