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feat(standalone):new operators and platform-standard RISC-V asm backend - #95
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CSR sparse ops (SpmmCsr) need col_indices/row_ptr laid out verbatim as one 32-bit word per element, never through the Q16.16 float conversion. - add ONNX_INT32 constant - parse int32_data (field 5) and raw_data, restoring negative values - shape fallback for INT32 tensors - layout_weights INT32 branch packs raw int32 words Tests: tests/test_standalone_int32_weights.py (4 passed). Full-suite failed set unchanged vs baseline (226 pre-existing llvm-mca/env).
…h (F1) spike_sim.py hardcoded /home/kinsomwang/... which is unusable elsewhere. Now: SCRATCHV_SPIKE / SCRATCHV_SPIKE_DASM / SCRATCHV_SPIKE_LOG_PARSER override, else PATH lookup, else bare command name. Tests: tests/test_standalone_spike_paths.py (4 passed).
Pin the interpreter to 3.11+ and add optional requirements for the RISC-V toolchain and simulation runtime.
- Conv/Gemm: accept models without a bias input - Fwht: scalar fast Walsh-Hadamard transform with forward/inverse directions, boundary handling and impulse-property regression - SpmmCsr: CSR sparse matrix-multiply operator with Q16.16 reference test - WinogradConv: F(2,3) kernel transform and convolution code generation - Conv: infer kernel size from the weight shape (fixes non-3x3 kernels) - Conv: support batch (N>1) via compile-time unrolling
…ed kernels - --platform-asm: clang-assemblable listing (global cnn_entry, label branches, inline .word data, la gp) - size-independent kernels for Fwht / Conv2D / SpmmCsr that read all dimensions from the argument block at runtime - tests: one kernel per operator verified end-to-end over many shapes, plus fast regression cases
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