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1 change: 1 addition & 0 deletions src/systems/system.jl
Original file line number Diff line number Diff line change
Expand Up @@ -773,6 +773,7 @@ function flatten(sys::System, noeqs = false)
# later removed by the user will be re-added. Right now, we just want to
# retain `defaults(sys)` as-is.
discover_from_metadata = false, metadata = get_metadata(sys),
gui_metadata = get_gui_metadata(sys),
description = description(sys), name = nameof(sys))
end

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3 changes: 2 additions & 1 deletion src/systems/systems.jl
Original file line number Diff line number Diff line change
Expand Up @@ -165,7 +165,8 @@ function __mtkcompile(sys::AbstractSystem; simplify = false,
assertions = assertions(sys),
guesses = guesses(sys), initialization_eqs = initialization_equations(sys),
continuous_events = continuous_events(sys),
discrete_events = discrete_events(sys))
discrete_events = discrete_events(sys),
gui_metadata = get_gui_metadata(sys))
@set! ssys.parameter_dependencies = get_parameter_dependencies(sys)
return ssys
end
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7 changes: 6 additions & 1 deletion test/components.jl
Original file line number Diff line number Diff line change
Expand Up @@ -46,6 +46,10 @@ include("common/rc_model.jl")
@test get_component_type(pin).name == :Pin
@test get_component_type(rc_model.resistor).name == :Resistor

@mtkcompile rc_model_compile = RCModel()
@test get_component_type(rc_model).name == :RCModel
@test get_component_type(rc_model_compile).name == :RCModel

completed_rc_model = complete(rc_model)
@test isequal(completed_rc_model.resistor.n.i, resistor.n.i)
@test ModelingToolkit.n_expanded_connection_equations(capacitor) == 2
Expand Down Expand Up @@ -352,7 +356,8 @@ end
@named comp1 = System(Equation[], t; systems = [input])
@named output = RealOutput()
@named comp2 = System(Equation[], t; systems = [output])
@named sys = System([connect(comp2.output.u, comp1.input.u)], t; systems = [comp1, comp2])
@named sys = System([connect(comp2.output.u, comp1.input.u)], t; systems = [
comp1, comp2])
eq = only(equations(expand_connections(sys)))
# as opposed to `output.u ~ input.u`
@test isequal(eq, comp1.input.u ~ comp2.output.u)
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