revise logic gates

SageMathOER-CCC · Jan 5, 2025 · ff7f1eb · ff7f1eb
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diff --git a/source/logic-gates/sec-combined-logic-gates.ptx b/source/logic-gates/sec-combined-logic-gates.ptx
@@ -5,11 +5,7 @@
         Logic gates can be combined to create more complex circuits that perform specific tasks. By linking gates together, we can create circuits that process multiple inputs to produce a desired output. For example, combining an <c>AND</c> gate and a <c>NOT</c> gate results in a <c>NAND</c> gate, which inverts the output of the <c>AND</c> gate. More complex circuits, such as half-adders and multiplexers, are built by combining basic gates in strategic ways.
     </p>
     <p>
-        Let's look at a circuit:
-    </p>
-
-    <p>
-        We will evaluate this circuit by setting True for <m>X</m>, <m>Y</m>, and False for <m>Z</m> below using Sage.
+        Let's look at a circuit. We evaluate this circuit by setting True for <m>X</m>, <m>Y</m>, and False for <m>Z</m> below using Sage.
     </p>
     <sage>
         <input>

diff --git a/source/logic-gates/sec-intro-logic-gates.ptx b/source/logic-gates/sec-intro-logic-gates.ptx
@@ -1,30 +1,30 @@
 <section xml:id="sec-intro-logic-gates" xmlns:xi="http://www.w3.org/2001/XInclude">
-
-    <title>Basic Logic Gates</title>
-        <idx>
-            <h>logic gates</h>
-            <h>AND</h>
-            <h>OR</h>
-            <h>NOT</h>
-            <h>NAND</h>
-            <h>NOR</h>
-            <h>XOR</h>
-            <h>XNOR</h>
-        </idx>
+    <title>Logic Gates</title>
+    <idx>
+        <h>logic gates</h>
+        <h>AND</h>
+        <h>OR</h>
+        <h>NOT</h>
+        <h>NAND</h>
+        <h>NOR</h>
+        <h>XOR</h>
+        <h>XNOR</h>
+    </idx>
+    <introduction>
         <p>
-            Logic gates are the foundation of digital circuits. They process binary inputs (<c>0</c>s and <c>1</c>s) to produce specific outputs, defined by truth tables. The basic logic gates are AND, OR, and NOT which correspond to the logical operators reviewed in previous sections. Other commonly used gates as NAND, NOR, XOR, and XNOR are composites of the basic ones. Each gate has its own symbol and truth table representing outputs for all combinations of inputs. These gates combine to form complex systems such as CPUs and memory circuits.
+           Logic gates are the foundation of digital circuits. They process binary inputs to produce specific outputs. The basic logic gates are <m>AND</m>, <m>OR</m>, and <m>NOT</m>. Derived gates include <m>NAND</m>, <m>NOR</m>, <m>XOR</m>, and <m>XNOR</m>. Each gate has its own symbol and behavior defined by a truth table.
         </p>
-        <aside>
-            <title>Notes</title>
-            <p>
-                Logic gates underpin modern computing, enabling operations like addition, decision-making, and data processing.
-            </p>
-        </aside>
-
-
-
+    </introduction>
+    <aside>
+        <title>Notes</title>
+        <p>
+            Logic gates combine to form complex systems such as CPUs and memory circuits.
+        </p>
+    </aside>
+    <subsection xml:id="subsec-AND-Gate">
+        <title>AND Gate</title>
         <p>
-            The <c>AND</c> gate produces a <c>1</c> only when both inputs are <c>1</c>.
+        The <c>AND</c> gate produces a <c>1</c> only when both inputs are <c>1</c>.
         </p>
         <figure xml:id="fig-AND-Gate">
             <caption>AND Gate</caption>
@@ -56,11 +56,11 @@
                         print(f"{int(A)} | {int(B)} | {int(bool(And(A, B)))}")
             </input>
         </sage>
-
-
-
+    </subsection>
+    <subsection xml:id="subsec-OR-GATE">
+        <title>OR GATE</title>
         <p>
-            The <c>OR</c> gate produces a <c>1</c> if at least one input is <c>1</c>.
+        The <c>OR</c> gate produces a <c>1</c> if at least one input is <c>1</c>.
         </p>
         <figure xml:id="fig-OR-Gate">
             <caption>OR Gate</caption>
@@ -92,7 +92,9 @@
                         print(f"{int(A)} | {int(B)} | {int(bool(Or(A, B)))}")
             </input>
         </sage>
+    </subsection>
 
+    <subsection xml:id="subsec-NOT-Gate">
         <title>NOT Gate</title>
         <p>
             The <c>NOT</c> gate inverts the input: <c>1</c> becomes <c>0</c>, and <c>0</c> becomes <c>1</c>.
@@ -126,10 +128,9 @@
                     print(f"{int(A)} | {int(bool(Not(A)))}")
             </input>
         </sage>
-
-
-
-        <title>Derived Gates</title>
+    </subsection>
+        <subsection xml:id="subsec-NAND-Gate">
+        <title>NAND Gate</title>
         <p><c>NAND</c>: Produces <c>0</c> only when both inputs are <c>1</c>.</p>
         <figure xml:id="fig-NAND-Gate">
             <caption>NAND Gate</caption>
@@ -141,14 +142,10 @@
             </latex-image>
             </image>
         </figure>
+    </subsection>
 
-                <aside>
-            <title>Notes</title>
-            <p>
-                These gates are critical for advanced functions, like error detection (<c>XOR</c>) and parity checking (<c>XNOR</c>).
-            </p>
-        </aside>
-
+    <subsection xml:id="subsec-NOR-Gate">
+        <title>NOR Gate</title>
         <p><c>NOR</c>: Produces <c>1</c> only when both inputs are <c>0</c>.</p>
         <figure xml:id="fig-NOR-Gate">
             <caption>NOR Gate</caption>
@@ -160,7 +157,10 @@
             </latex-image>
             </image>
         </figure>
+    </subsection>
 
+    <subsection xml:id="subsec-XOR-Gate">
+        <title>XOR Gate</title>
         <p><c>XOR</c>: Produces <c>1</c> when inputs differ.</p>
         <figure xml:id="fig-XOR-Gate">
             <caption>XOR Gate</caption>
@@ -172,7 +172,10 @@
             </latex-image>
             </image>
         </figure>
+    </subsection>
 
+    <subsection xml:id="subsec-XNOR-Gate">
+        <title>XNOR Gate</title>
         <p><c>XNOR</c>: Produces <c>1</c> when inputs are the same.</p>
         <figure xml:id="fig-XNOR-Gate">
             <caption>XNOR Gate</caption>
@@ -184,8 +187,7 @@
             </latex-image>
             </image>
         </figure>
-
-<sage>
+        <sage>
     <input>
         from sympy.logic.boolalg import And, Or, Not, Xor
 
@@ -222,10 +224,6 @@
     </input>
     <output>
     </output>
-</sage>
-
-
-
-
-
-</section>
+    </sage>
+    </subsection>
+</section>
diff --git a/source/logic-gates/sec-logic-gates-in-action.ptx b/source/logic-gates/sec-logic-gates-in-action.ptx
@@ -2,7 +2,7 @@
     <title>Logic Gates in Action</title>
     <introduction>
         <p>
-            Voting systems are fundamental in decision-making processes, from simple classroom polls to national elections. In this section, we’ll use logic gates to build a simple digital voting machine. The machine will count binary votes (Yes = 1, No = 0) and determine the majority outcome. We’ll break the system into smaller functions, each implemented using logic gates, and then combine them to form the complete voting machine.
+            Voting systems are fundamental in decision-making processes like national elections. In this section, we use logic gates to build a simple digital voting machine. The machine will count binary votes and determine the majority outcome. We break the system into smaller functions, each implemented using logic gates, and then combine them to form the complete voting machine.
         </p>
     </introduction>
 
@@ -61,9 +61,7 @@
         <title>Majority Decider</title>
         <p>
             The majority decider uses logic gates to determine whether "Yes" votes are greater than "No" votes. For three votes, the logic can be expressed as:
-            <display>
-                Majority = (V1 AND V2) OR (V2 AND V3) OR (V1 AND V3)
-            </display>
+            <me>Majority = (V1 AND V2) OR (V2 AND V3) OR (V1 AND V3)</me>
             This formula ensures that if at least two out of three votes are "Yes," the output will indicate a majority.
         </p>
         <sage>