GitHub - Rickisterr/ModelSim-Practice-VLSI-design: Modelsim Practice from VLSI design externship course

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
work		work
ALU.v		ALU.v
ALU.v.bak		ALU.v.bak
ALU_tb.v		ALU_tb.v
ALU_tb.v.bak		ALU_tb.v.bak
Branch_Unit.v		Branch_Unit.v
Branch_Unit.v.bak		Branch_Unit.v.bak
Branch_Unit_tb.v		Branch_Unit_tb.v
Branch_Unit_tb.v.bak		Branch_Unit_tb.v.bak
Decoder.v		Decoder.v
Decoder.v.bak		Decoder.v.bak
Decoder_tb.v		Decoder_tb.v
Decoder_tb.v.bak		Decoder_tb.v.bak
Immediate_adder.v		Immediate_adder.v
Immediate_adder.v.bak		Immediate_adder.v.bak
Immediate_adder_tb.v		Immediate_adder_tb.v
Immediate_adder_tb.v.bak		Immediate_adder_tb.v.bak
Immediate_generator.v		Immediate_generator.v
Immediate_generator.v.bak		Immediate_generator.v.bak
Immediate_generator_tb.v		Immediate_generator_tb.v
Immediate_generator_tb.v.bak		Immediate_generator_tb.v.bak
Instruction_Mux.v		Instruction_Mux.v
Instruction_Mux.v.bak		Instruction_Mux.v.bak
Instruction_Mux_tb.v		Instruction_Mux_tb.v
Instruction_Mux_tb.v.bak		Instruction_Mux_tb.v.bak
Integer_File.v		Integer_File.v
Integer_File.v.bak		Integer_File.v.bak
Integer_File_tb.v		Integer_File_tb.v
Integer_File_tb.v.bak		Integer_File_tb.v.bak
Load_Unit.v		Load_Unit.v
Load_Unit.v.bak		Load_Unit.v.bak
Load_Unit_tb.v		Load_Unit_tb.v
Load_Unit_tb.v.bak		Load_Unit_tb.v.bak
PC_MUX.v		PC_MUX.v
PC_MUX.v.bak		PC_MUX.v.bak
PC_MUX_tb.v		PC_MUX_tb.v
PC_MUX_tb.v.bak		PC_MUX_tb.v.bak
Processor.cr.mti		Processor.cr.mti
Processor.mpf		Processor.mpf
RISCV_RV32I.cr.mti		RISCV_RV32I.cr.mti
RISCV_RV32I.mpf		RISCV_RV32I.mpf
Reg_Block_1.v		Reg_Block_1.v
Reg_Block_1.v.bak		Reg_Block_1.v.bak
Reg_Block_1_tb.v		Reg_Block_1_tb.v
Reg_Block_1_tb.v.bak		Reg_Block_1_tb.v.bak
Reg_Block_2.v		Reg_Block_2.v
Reg_Block_2.v.bak		Reg_Block_2.v.bak
Reg_Block_2_tb.v		Reg_Block_2_tb.v
Reg_Block_2_tb.v.bak		Reg_Block_2_tb.v.bak
Store_Unit.v		Store_Unit.v
Store_Unit.v.bak		Store_Unit.v.bak
Store_Unit_tb.v		Store_Unit_tb.v
Store_Unit_tb.v.bak		Store_Unit_tb.v.bak
VLSIlab1.cr.mti		VLSIlab1.cr.mti
VLSIlab1.mpf		VLSIlab1.mpf
WB_Mux_Selection_Unit.v		WB_Mux_Selection_Unit.v
WB_Mux_Selection_Unit.v.bak		WB_Mux_Selection_Unit.v.bak
WB_Mux_Selection_Unit_tb.v		WB_Mux_Selection_Unit_tb.v
WB_Mux_Selection_Unit_tb.v.bak		WB_Mux_Selection_Unit_tb.v.bak
Write_Enable_Generator.v		Write_Enable_Generator.v
Write_Enable_Generator.v.bak		Write_Enable_Generator.v.bak
Write_Enable_Generator_tb.v		Write_Enable_Generator_tb.v
Write_Enable_Generator_tb.v.bak		Write_Enable_Generator_tb.v.bak
msrv32_csr_file.v		msrv32_csr_file.v
msrv32_csr_file.v.bak		msrv32_csr_file.v.bak
msrv32_machine_control.v		msrv32_machine_control.v
msrv32_machine_control.v.bak		msrv32_machine_control.v.bak
msrv32_top.v		msrv32_top.v
msrv32_top.v.bak		msrv32_top.v.bak
transcript		transcript
vsim.dbg		vsim.dbg
vsim.wlf		vsim.wlf