sync: rvck #355: riscv: backport mainline xtheadvector support - #251
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dist inclusion category: cleanup Link: RVCK-Project/rvck#354 -------------------------------- This reverts commit e51330b7afda ("xtheadvector: fix it used as v-ext when hwprobe is used"). Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com> [sync from rvck.] Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
dist inclusion category: cleanup Link: RVCK-Project/rvck#354 -------------------------------- This reverts commit 4f7f71aa5ad7 ("riscv: xtheadvector: enable vector function"). Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com> [sync from rvck.] Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
mainline inclusion
from mainline-6.10
commit c3f7c14856ebbeb8e9e19439b9f5ec66f88744b9 ("riscv: dts: allwinner: convert isa detection to new properties")
category: feature
Link: RVCK-Project/rvck#354
--------------------------------
Convert the D1 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231009-moonlight-gray-92debdc89f30@wendy
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
[sync from rvck.]
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
mainline inclusion
from mainline-6.14
commit bf6279b38a4bbdb2954c3d159523d41367763a48 ("dt-bindings: cpus: add a thead vlen register length property")
category: feature
Link: RVCK-Project/rvck#354
--------------------------------
Add a property analogous to the vlenb CSR so that software can detect
the vector length of each CPU prior to it being brought online.
Currently software has to assume that the vector length read from the
boot CPU applies to all possible CPUs. On T-Head CPUs implementing
pre-ratification vector, reading the th.vlenb CSR may produce an illegal
instruction trap, so this property is required on such systems.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-2-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
[sync from rvck.]
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
mainline inclusion
from mainline-6.14
commit ce1daeeba600a79b776864f12d19e799f1eb124f ("riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree")
category: feature
Link: RVCK-Project/rvck#354
--------------------------------
The D1/D1s SoCs support xtheadvector so it can be included in the
devicetree. Also include vlenb for the cpu.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-3-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
[sync from rvck.]
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
mainline inclusion
from mainline-6.14
commit cddd63869f9214f2bc5c4b89a8ea1bd0ff4d89c5 ("riscv: Add thead and xtheadvector as a vendor extension")
category: feature
Link: RVCK-Project/rvck#354
--------------------------------
Add support to the kernel for THead vendor extensions with the target of
the new extension xtheadvector.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-4-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
[sync from rvck.]
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
mainline inclusion
from mainline-6.14
commit 377be47f90e411c10440650864d72d2ecb639bd7 ("riscv: vector: Use vlenb from DT for thead")
category: feature
Link: RVCK-Project/rvck#354
--------------------------------
If thead,vlenb is provided in the device tree, prefer that over reading
the vlenb csr.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-5-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
[sync from rvck.]
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
mainline inclusion
from mainline-6.14
commit 66f197785d515d3fe5257ed65e189e4ee0b9b4e3 ("RISC-V: define the elements of the VCSR vector CSR")
category: feature
Link: RVCK-Project/rvck#354
--------------------------------
The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0].
Define constants for those to access the elements in a readable way.
Acked-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-6-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
[sync from rvck.]
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
mainline inclusion
from mainline-6.14
commit b9a9314424512e536db5e54ff554c2f10759c657 ("riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT")
category: feature
Link: RVCK-Project/rvck#354
The xtheadvector symbolic CSR names and masks added by this upstream
commit were already introduced in the rvck baseline by commit 11ca164
("riscv: add Zicfiss / Zicfilp extension CSR and bit definitions").
This cherry-pick only removes the old VCSR_-prefixed macros to avoid
duplicate definitions.
--------------------------------
The VXRM vector csr for xtheadvector has an encoding of 0xa and VXSAT
has an encoding of 0x9.
Co-developed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-7-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
[sync from rvck.]
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
mainline inclusion
from mainline-6.14
commit 01e3313e34d0e3912a7031c217367df051603149 ("riscv: Add xtheadvector instruction definitions")
category: feature
Link: RVCK-Project/rvck#354
--------------------------------
xtheadvector uses different encodings than standard vector for
vsetvli and vector loads/stores. Write the instruction formats to be
used in assembly code.
Co-developed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-8-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
[sync from rvck.]
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
mainline inclusion
from mainline-6.14
commit d863910eabaffc68eb28aaf476dd870fc3f7197d ("riscv: vector: Support xtheadvector save/restore")
category: feature
Link: RVCK-Project/rvck#354
The setup_sigcontext hunk that changes has_vector() to
(has_vector() || has_xtheadvector()) was already incorporated into
the rvck baseline by commit 26279be ("riscv: signal: abstract header
saving for setup_sigcontext"), which moved this check into
save_v_state(). This cherry-pick omits that hunk.
--------------------------------
Use alternatives to add support for xtheadvector vector save/restore
routines.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-9-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
[sync from rvck.]
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
…ension
mainline inclusion
from mainline-6.14
commit 7fa00fd6ff5366b50dcba2525b9743e1612da2aa ("riscv: hwprobe: Document thead vendor extensions and xtheadvector extension")
category: feature
Link: RVCK-Project/rvck#354
--------------------------------
Document support for thead vendor extensions using the key
RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 and xtheadvector extension using
the key RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-11-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
[sync from rvck.]
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
mainline inclusion
from mainline-6.14
commit 57d7713af93e4b7344d3022fad9ddf0f10f815ec ("selftests: riscv: Fix vector tests")
category: feature
Link: RVCK-Project/rvck#354
--------------------------------
Overhaul the riscv vector tests to use kselftest_harness to help the
test cases correctly report the results and decouple the individual test
cases from each other. With this refactoring, only run the test cases if
vector is reported and properly report the test case as skipped
otherwise. The v_initval_nolibc test was previously not checking if
vector was supported and used a function (malloc) which invalidates
the state of the vector registers.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-12-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
[sync from rvck.]
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
mainline inclusion
from mainline-6.14
commit c384c5d4a2aed5b6a10de1fcc2f5b46ad4aeeea8 ("selftests: riscv: Support xtheadvector in vector tests")
category: feature
Link: RVCK-Project/rvck#354
--------------------------------
Extend existing vector tests to be compatible with the xtheadvector
instructions.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-13-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
[sync from rvck.]
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
mainline inclusion
from mainline-6.16
commit 4262bd0d9cc704ea1365ac00afc1272400c2cbef ("riscv: vector: Fix context save/restore with xtheadvector")
category: feature
Link: RVCK-Project/rvck#354
--------------------------------
Previously only v0-v7 were correctly saved/restored,
and the context of v8-v31 are damanged.
Correctly save/restore v8-v31 to avoid breaking userspace.
Fixes: d863910eabaf ("riscv: vector: Support xtheadvector save/restore")
Cc: stable@vger.kernel.org
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Tested-by: Xiongchuan Tan <tanxiongchuan@isrc.iscas.ac.cn>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Yanteng Si <si.yanteng@linux.dev>
Reviewed-by: Andy Chiu <andybnac@gmail.com>
Link: https://lore.kernel.org/r/9b9eb2337f3d5336ce813721f8ebea51e0b2b553.1747994822.git.rabenda.cn@gmail.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
[sync from rvck.]
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
…ous_vlenb()
mainline inclusion
from mainline-6.18
commit 2dc99ea2727640b2fe12f9aa0e38ea2fc3cbb92d ("riscv: cpufeature: avoid uninitialized variable in has_thead_homogeneous_vlenb()")
category: feature
Link: RVCK-Project/rvck#354
--------------------------------
In has_thead_homogeneous_vlenb(), smatch detected that the vlenb variable
could be used while uninitialized. It appears that this could happen if
no CPUs described in DT have the "thead,vlenb" property.
Fix by initializing vlenb to 0, which will keep thead_vlenb_of set to 0
(as it was statically initialized). This in turn will cause
riscv_v_setup_vsize() to fall back to CSR probing - the desired result if
thead,vlenb isn't provided in the DT data.
While here, fix a nearby comment typo.
Cc: stable@vger.kernel.org
Cc: Charlie Jenkins <charlie@rivosinc.com>
Fixes: 377be47f90e41 ("riscv: vector: Use vlenb from DT for thead")
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Link: https://lore.kernel.org/r/22674afb-2fe8-2a83-1818-4c37bd554579@kernel.org
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
[sync from rvck.]
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
mainline inclusion
from mainline-6.18
commit 9f393d8e757f79060baf4b2e703bd6b2d0d8d323 ("riscv: dts: allwinner: d1: fix vlenb property")
category: feature
Link: RVCK-Project/rvck#354
--------------------------------
According to [1], the C906 vector registers are 128 bits wide.
The 'thead,vlenb' property specifies the vector register length
in bytes, so its value must be set to 16.
[1] https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
Fixes: ce1daeeba600 ("riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree")
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
Link: https://patch.msgid.link/20251119203508.1032716-1-geomatsi@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
[sync from rvck.]
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
mainline inclusion
from mainline-6.19
commit aef6dc006696c20ccc58c4c0235a14e7b4b317a0 ("riscv: dts: thead: add xtheadvector to the th1520 devicetree")
category: feature
Link: RVCK-Project/rvck#354
--------------------------------
The th1520 support xtheadvector [1] so it can be included in the
devicetree. Also include vlenb for the cpu. And set vlenb=16 [2].
This can be tested by passing the "mitigations=off" kernel parameter.
Link: https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-4-236c22791ef9@rivosinc.com/ [1]
Link: https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/ [2]
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Drew Fustini <fustini@kernel.org>
[zhenxing.zhu@linux.alibaba.com: xtheadvector already in isa, only added thead,vlenb property]
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
[sync from rvck.]
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
mainline inclusion
from mainline-6.11
commit ac295b67422d1a6627866453543b4880ab144572 ("riscv: vector: adjust minimum Vector requirement to ZVE32X")
category: feature
Link: RVCK-Project/rvck#354
--------------------------------
Make has_vector() to check for ZVE32X. Every in-kernel usage of V that
requires a more complicate version of V must then call out explicitly.
Also, change riscv_v_first_use_handler(), and boot code that calls
riscv_v_setup_vsize() to accept ZVE32X.
Most kernel/user interfaces requires minimum of ZVE32X. Thus, programs
compiled and run with ZVE32X should be supported by the kernel on most
aspects. This includes context-switch, signal, ptrace, prctl, and
hwprobe.
One exception is that ELF_HWCAP returns 'V' only if full V is supported
on the platform. This means that the system without a full V must not
rely on ELF_HWCAP to tell whether it is allowable to execute Vector
without first invoking a prctl() check.
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Acked-by: Joel Granados <j.granados@samsung.com>
Link: https://lore.kernel.org/r/20240510-zve-detection-v5-7-0711bdd26c12@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
[zhenxing.zhu@linux.alibaba.com: partial backport, vector.h/cpufeature.c/vector.c already applied via baseline, only sys_hwprobe.c and uaccess.S hunks added]
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
[sync from rvck.]
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
|
开始测试 log: https://github.com/RVCK-Project/rvck-olk/actions/runs/32619539471 参数解析结果
测试完成 详细结果:
Kunit Test Result[05:11:53] Testing complete. Ran 482 tests: passed: 466, skipped: 16
Kernel Build Result
Check Patch Result
LAVA Check (qemu)
result: Lava check done!
|
Contributor
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Sync commits from rvck PR 355.
Source PR: RVCK-Project/rvck#355