Repository navigation
[rocjitsu] Expose backed CDNA3 and CDNA4 hardware identity fields - #13899
Conversation
github-actions
Bot
added
documentation
❌ PR Check — Action Required
📖 Need help? See the Policy FAQ for details on every check and how to fix failures. |
|
🚫 Please fix the failed policies before requesting reviews. The following policy checks failed:
The |
kuhar
changed the title
sjain-stanford
left a comment
sjain-stanford
left a comment
There was a problem hiding this comment.
We should commit regression coverage for the identity limits and the end-to-end kernel mentioned in the description. Removing only the CU-width guard still passes all 112 HWREG/configuration/checkpoint tests, while the separate 16/17-CU probe catches the alias.
In emulation/rocjitsu/tests/instruction_execution_harness_test.cpp:8935, add CDNA3/4 boundary pairs:
- CU_ID:
(cu_index, width, engine_count)of(15, 16, 16)succeeds with 15;(16, 17, 17)returnsUnsupportedand zero for full and partial CU_ID reads. SE_ID should remain readable. - WAVE_ID: slot 63 succeeds with 15; slot 64 returns
Unsupportedand zero; SIMD_ID at slot 64 should still succeed with zero. - XCC_ID: rank 15 succeeds with 15; rank 16 returns
Unsupportedand zero for both the full register and its four-bit slice.
Also retain a small gfx942/gfx950 multi-XCD kernel in emulation/rocjitsu/tests/hip_hw_id_test.cpp:26 that reads HW_ID[5:0], HW_ID[15:8], XCC_ID and __smid(), checks the configured identity bounds and SH_ID == 0, and compares __smid() with the recomposed fields. The existing HIP test reads SIMD_ID only; the new configuration tests place waves directly, so they do not cover the added fields through HIP/AQL dispatch.
| fields; SH_ID reads zero as specified by the ISA. CU_ID requires a known, | ||
| single-array geometry with 1–16 CUs per shader engine. SE_ID must fit in | ||
| three bits. `XCC_ID` reads the physical command-processor rank only after | ||
| SoC topology initialization, independently of scratch-addressing overrides. |
There was a problem hiding this comment.
It would be useful to state the access limits explicitly here: an HW_ID slice touching any unsupported bit rejects the entire read, so the default 32-bit HW_ID read still warns and writes zero; XCC_ID requires an XCD index in 0–15.
For example, ROCR's runtime/hsa-runtime/core/runtime/trap_handler/trap_handler.s:559 reads the whole HW_ID register. Saying only that other fields are unsupported can sound like that read returns the backed fields with zeros elsewhere. Describing XCC_ID as the XCD index within its SoC would also avoid referring to test-only scratch overrides.
sjain-stanford
left a comment
sjain-stanford
left a comment
There was a problem hiding this comment.
LGTM modulo two suggestions.
4bc00f1 to
06d3225
Compare
S_GETREG can read SIMD_ID on CDNA3 and CDNA4, but rejects the wave, compute-unit, shader-engine and XCC fields used to identify placement. Derive WAVE_ID and SIMD_ID from resident wave slots, CU_ID and SE_ID from the configured topology, and XCC_ID from the physical command processor rank. Keep XCC identity independent of scratch addressing. Reject unassigned XCC topology, unknown HW_ID fields and unrepresentable topology instead of returning truncated or aliased identities. Cover decoded reads, read-only writes, absent topology, multi-array CU rejection and CU/WAVE/XCC field limits. Check physical identities through configuration loading and checkpoint restoration. Exercise HW_ID, XCC_ID and __smid() in gfx942/gfx950 HIP kernels dispatched across multiple XCDs. Document whole-read rejection for unsupported HW_ID slices. Keep CI independent of the uninitialized tensor-DMA fixtures added upstream by temporarily excluding only the 11 affected cases. Exclude the multi-XCD HIP cases from the TSan lane while ROCr completion synchronization remains invisible to the sanitizer. Retain their functional coverage in the other supported configurations.
06d3225 to
364cf42
Compare
github-actions
Bot
added
the
github actions
TheRock Submodule Bump ActivityNewest first
|
S_GETREG can read SIMD_ID on CDNA3 and CDNA4, but rejects the wave,
compute-unit, shader-engine and XCC fields used to identify placement.
Derive WAVE_ID and SIMD_ID from resident wave slots, CU_ID and SE_ID
from the configured topology, and XCC_ID from the physical command
processor rank. Keep XCC identity independent of scratch addressing.
Reject unassigned XCC topology, unknown HW_ID fields and unrepresentable
topology instead of returning truncated or aliased identities.
Cover decoded reads, read-only writes, absent topology and multi-array
CU rejection. Check physical identities through configuration loading and
checkpoint restoration. All 76 selected hardware-register, configuration
and checkpoint tests pass; end-to-end identity kernels pass for gfx942
and gfx950.