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rocr: scope the VOP3PX trap PC fixup to gfx1250 revision 0 - #13797
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Revision-specific trap behavior and generated-blob equivalence need toolchain and hardware validation before approval.
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What changed in this PR
Scopes ROCr’s gfx1250 VOP3PX trap-PC fixup to revision 0 while preserving the S_SET_VGPR_MSB fixup for all revisions.
Changes:
- Adds an assembler guard around the VOP3PX fixup.
- Generates a separate gfx1250 handler for later revisions.
- Selects the handler using the ASIC revision, with fallback to the existing blob.
| File | Description |
|---|---|
| projects/rocr-runtime/runtime/hsa-runtime/core/runtime/trap_handler/trap_handler_gfx12.s | Conditionally assembles the VOP3PX fixup. |
| projects/rocr-runtime/runtime/hsa-runtime/core/runtime/trap_handler/CMakeLists.txt | Builds the later-revision handler using a symbol override. |
| projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp | Selects the revision-specific handler. |
Review effort: Balanced
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The second-level trap handler's VOP3PX instruction-boundary PC fixup applies to gfx1250 revision 0 only. Guard it behind an assembler symbol so it is compiled out for later revisions, emit a second trap handler without it, and select between them from the ASIC revision the kernel reports. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Name the revision-specific handler slot after the revision it serves, and narrow the revision check so later minor versions are unaffected. Default the assembler symbol off so the revision 0 build requests the PC rewind explicitly rather than every other build switching it off. A target added to the build lists without a matching assembler-symbol entry then assembles without the rewind, which is correct for every revision except revision 0. Catch an incomplete per-revision shader table entry instead of silently falling back, and fail configure early if the parallel target lists fall out of step. Keep the masking instruction with the compares it feeds so it is not emitted when those compares are not, and drop a stale comment reference to the first-level handler. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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🤖 AI-assisted pre-review (for @cfreeamd)
[Required] PR title format: rocr: scope the VOP3PX trap PC fixup to gfx1250 revision 0 is missing the type(component): prefix. ROCm squash-merges PRs, so the title becomes the permanent commit message. Suggested: fix(rocr): scope the VOP3PX trap PC fixup to gfx1250 revision 0.
All code findings from earlier review passes have been addressed (assert added for the rev0.code == NULL fallback; macro direction corrected to opt-in). This title correction is the only remaining item.
Summary
The second-level trap handler's trap-during-VOP3PX PC fixup applies to gfx1250
revision 0 only. This scopes it to that revision instead of applying it to every
gfx1250 part.
JIRA ID : PLAT-212250
Changes
trap_handler_gfx12.s— the two VOP3PX encoding compares and the.fixup_vop3px_middlePC-rewind block are guarded by a new assembler symbolHAVE_VOP3PX_FIXUP. The symbol defaults to1under.ifndef, so a build thatdoes not override it produces the handler exactly as before. The
S_SET_VGPR_MSBfixup is deliberately left unguarded — it applies to every revision.
trap_handler/CMakeLists.txt— gfx1250 is built twice from the same source.The build that keeps the fixup emits
kCodeTrapHandlerV2_1250_rev0. The secondbuild passes
-Wa,-defsym,HAVE_VOP3PX_FIXUP=0and emitskCodeTrapHandlerV2_1250, which serves revision 1 and later. The per-targetlists gain a parallel
ASM_DEFSYMlist so any future target can pass assemblersymbol overrides the same way.
amd_gpu_agent.cpp—GpuAgent::AssembleShaderselectscompute_1250_rev0when the agent's ISA minor version is 5, itsproperties_.Capability.ui32.ASICRevisionis 0, and that slot is populated.Every later revision, and every later minor version, takes
compute_1250— theblob assembled without the fixup. Shaders that do not vary by revision leave the
revision-0 slot zeroed and are served by
compute_1250for every revision.Relationship to the kernel driver
This change stands on its own and does not depend on any kernel change landing.
It scopes the second-level trap handler only.
For context, a matching change to the KFD first-level CWSR handler has been
proposed but is not merged. In that proposal
HAVE_INSTRUCTION_FIXUPsplitsinto
HAVE_VOP3PX_FIXUPandHAVE_VGPR_MSB_FIXUP— both still keyed onASIC_FAMILY, not on revision — and the revision discrimination is done inkfd_cwsr_init, which selects the revision-0 handler onadev->rev_id == 0.In the currently merged kernel baseline there is no revision term at all:
HAVE_INSTRUCTION_FIXUPis gated on family alone, so the first-level handlercarries the VOP3PX fixup on every revision. That mismatch is the thing this
patch scopes on the ROCr side, and it is worth knowing when reviewing.
Effect on existing targets
The blob a revision 0 part receives is byte-identical to the pre-patch gfx1250
blob — md5
038cbb5a02520657c1bf1e14597af07b, measured against a purpose-builtpre-patch tree with a negative control.
That blob is the newly added symbol, so the byte-identity should not be read as
"nothing moved". The pre-existing symbol
kCodeTrapHandlerV2_1250now holdsdifferent bytes (md5
138d64ed3657ce336d813aa98e2ff33f), because after thischange it is the blob assembled without the fixup.
No other target's output changes.
HAVE_VOP3PX_FIXUPdefaults to1under.ifndefand the only entry that overrides it is the second gfx1250 build, soevery other target — including gfx1200, which assembles the same source file —
is built from source that is unchanged in effect. That is a source-level
argument; only the two gfx1250 blobs were measured.
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