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Exercise arbitrary instruction streams through wavefront and compute-unit execution across every supported AMDGPU ISA family, with deterministic register and memory initialization, bounded instruction budgets, automatic target and async-mode selection, and generated instruction seeds. Route unsupported guest encodings encountered during CU stepping through ordinary wave-failure diagnostics while preserving direct instruction execution behavior. Add multithreaded standalone, AFL++, sanitizer, and TSan entry points plus a resumable campaign runner that preserves active inputs, deduplicates findings, and tolerates partial deadline records. Cover target selection, execution reachability, unsupported fetched encodings, concurrent async WMMA work, replay behavior, campaign checkpointing, and CLI contracts.
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removed this pull request from stack #13711
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Exercise arbitrary instruction streams through wavefront and compute-unit execution across every supported AMDGPU ISA family, with deterministic register and memory initialization, bounded instruction budgets, automatic target and async-mode selection, and generated instruction seeds.
Route unsupported guest encodings encountered during CU stepping through ordinary wave-failure diagnostics while preserving direct instruction execution behavior.
Add multithreaded standalone, AFL++, sanitizer, and TSan entry points plus a resumable campaign runner that preserves active inputs, deduplicates findings, and tolerates partial deadline records.
Cover target selection, execution reachability, unsupported fetched encodings, concurrent async WMMA work, replay behavior, campaign checkpointing, and CLI contracts.