This repository contains my personal solutions to laboratory exercises from FPGAcademy: https://fpgacademy.org/courses.html
Click a course name below to expand the related laboratories and topics.
| Lab Folder | Lab Description |
|---|---|
| LAB 1 | Switches, Lights, and Multiplexers |
| LAB 2 | Numbers and Displays |
| LAB 3 | Latches, Flip-flops and Registers |
| LAB 4 | Counters |
| LAB 5 | Timers and Real-Time Clocks |
| LAB 6 | Adders, Subtracters, and Multipliers |
| LAB 7 | Finite State Machines |
| LAB 8 | Memory Blocks |
| LAB 9 | A Simple Processor |
| LAB 10 | An Enhanced Processor |
| LAB 11 | A More Enhanced Processor |
| Lab Folder | Lab Description |
|---|---|
| LAB 1 | Using a Nios® V System |
| LAB 2 | Using Logic Instructions with the Nios® V Processor |
| LAB 3 | Memory-mapped I/O, Polling and Timers |
| LAB 4 | Using Subroutines, the Stack, and the Terminal Window |
| LAB 5 | Using Interrupts with Assembly Code |
| LAB 6 | Using C Code with the Nios® V Processor |
| LAB 7 | Using Interrupts with C Code |
| LAB 8 | Introduction to Graphics and Animation |
Each laboratory folder contains:
- The original PDF with exercise instructions, and an archive with the provided design files (if applicable)
- Solution for each part of the laboratory
The PDFs and accompanying design archives are included for educational reference only. All rights to the original materials belong to FPGAcademy.
All laboratories use the DE1-SoC (Revision H) board.
The tools used for each part of the course are as follows:
-
Digital Logic:
- HDL: Verilog
- Toolchain: Quartus Prime Lite Edition 20.1
- Simulation Environment: ModelSim 2020.1
-
Computer Organization:
- CPUlator: https://cpulator.01xz.net/
- Compiler: Ashling RiscFree IDE for FPGAs 24.1
- FPGA Programmer: Quartus Prime Programmer and Tools 24.1
The source code in this repository is intended for educational use.
All laboratory exercise PDFs are copyrighted materials of FPGAcademy and are included in accordance with their license terms.