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[None][feat] MiniMax-M3 NVFP4 low latency decode megakernel for Rubin (sm_107) TP2 / TP4 / TP8 in modeling_v2 - #20623

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[None][feat] MiniMax-M3 NVFP4 low latency decode megakernel for Rubin (sm_107) TP2 / TP4 / TP8 in modeling_v2#20623
peihu-nv wants to merge 49 commits into
NVIDIA:mainfrom
peihu-nv:peihengh/m3-vr-sm107-decode

[None][fix] Merge M3 shared fake-op layout prerequisite

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