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initial vunit support #6

Merged
merged 2 commits into from
Jun 7, 2023
Merged

initial vunit support #6

merged 2 commits into from
Jun 7, 2023

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Ruskuls
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@Ruskuls Ruskuls commented May 28, 2023 •
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Vunit simulation - preferred simulator, that supports also Verilog files. For tests Modelsim were used.

Possible improvements:

  • better name for simulation-vunit folder
  • remove testbench file duplication (delay.vhd, tb_clk.vhd)
  • free simulator that supports vhdl and verilog files. In that case code coverage from OSVVM also could be used

@MJoergen
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Thank you! I'll look at it tomorrow - its my wife's birthday today :-)

@MJoergen
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Ok, I just tried your patch, and I get the following error (after I did pip install vunit_hdl):

mike@mike-desktop2 ~/git/Ruskuls/HyperRAM/simulation-vunit (vunit-support=) $ ./run.py 
modelsim
WARNING - Entity tb_clk matches testbench name regex ^(tb_.*)|(.*_tb)$ but has no generic runner_cfg and will therefore not be run.
in file /home/mike/git/Ruskuls/HyperRAM/simulation-vunit/test/tb_clk.vhd
Traceback (most recent call last):
  File "/home/mike/.local/lib/python3.10/site-packages/vunit/ui/__init__.py", line 735, in main
    all_ok = self._main(post_run)
  File "/home/mike/.local/lib/python3.10/site-packages/vunit/ui/__init__.py", line 779, in _main
    all_ok = self._main_run(post_run)
  File "/home/mike/.local/lib/python3.10/site-packages/vunit/ui/__init__.py", line 806, in _main_run
    self._compile(simulator_if)
  File "/home/mike/.local/lib/python3.10/site-packages/vunit/ui/__init__.py", line 950, in _compile
    simulator_if.compile_project(
  File "/home/mike/.local/lib/python3.10/site-packages/vunit/sim_if/__init__.py", line 209, in compile_project
    self.add_simulator_specific(project)
  File "/home/mike/.local/lib/python3.10/site-packages/vunit/sim_if/modelsim.py", line 118, in add_simulator_specific
    mapped_libraries = self._get_mapped_libraries()
  File "/home/mike/.local/lib/python3.10/site-packages/vunit/sim_if/modelsim.py", line 225, in _get_mapped_libraries
    cfg = parse_modelsimini(self._sim_cfg_file_name)
  File "/home/mike/.local/lib/python3.10/site-packages/vunit/sim_if/modelsim.py", line 426, in parse_modelsimini
    cfg.read_file(fptr)
  File "/usr/lib/python3.10/configparser.py", line 719, in read_file
    self._read(f, source)
  File "/usr/lib/python3.10/configparser.py", line 1117, in _read
    raise e
configparser.ParsingError: Source contains parsing errors: '/home/mike/git/Ruskuls/HyperRAM/simulation-vunit/vunit_out/modelsim/modelsim.ini'
	[line 1970]: 'l   arraymode    - consider rand_mode of unpacked array field independently from its elements\n'

I don't have any experience with VUnit, so I'm unsure how to debug/proceed here. It seems like it is selecting the wrong top-level testbench, maybe? Could you please help me?

BTW: I really appreciate you making this pull request and adding support for VUnit. This is a great improvement!! Now I just need to get it to work on my machine ...

@Ruskuls
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Ruskuls commented May 29, 2023

Ou, sorry, that I forgot to add a clear instructions how to use it!

Added quick installation guide - https://github.com/Ruskuls/HyperRAM/tree/vunit-support/simulation-vunit

I hope it will help!

**Note! 1 ** I'm using Ubuntu machine with installed Lattice development tools (Modelsim is shipped as a part). But it should be similiar process if Quartus tools are used.

**Note! 2 ** WARNING - Entity tb_clk matches testbench name regex ^(tb.)|(.tb)$. Vunit detects this module as a tesbench, but can't find Vunit related initialization precudures. To fix this warning, it has to be renamed, can't contain tb_. for now this warning can be ignored.

@Ruskuls
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Ruskuls commented May 29, 2023

I was able to reproduce the same error. It's because env is missing VUNIT_MODELSIM_PATH. Please checkout out readme.

I don't have any experience with VUnit, so I'm unsure how to debug/proceed here. It seems like it is selecting the wrong top-level testbench, maybe? Could you please help me?

@MJoergen
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MJoergen commented Jun 2, 2023

Ok, I made some progress, but I still get (new) errors.

Just to add to the confusion, I'm working alternately on two different machines (home and work). So, I'm currently trying on an "Ubuntu 22.04.2 LTS" (with QuestaSim installed as part of Quartus Lite version), but with very restricted Internet access (pip install does not work). I therefore had to manually download and install the VUnit package from GitHub. I chose version 4.7, because version 5 has some updates that break backwards compatibility (VUnit/vunit#777).

Anyway, with VUnit version 4.7 manually installed I now get the result shown below. This error seems related to OSVVM. Do you think this problem is related to the manual install? I can't check on my other machine at the moment. Any idea how to proceed?

WARNING - /usr/local/lib/python3.10/dist-packages/vunit_hdl-4.7.0-py3.10.egg/vunit/vhdl/osvvm/MemoryPkg.vhd: package 'memorypkg_orig' previously defined in /usr/local/lib/python3.10/dist-packages/vunit_hdl-4.7.0-py3.10.egg/vunit/vhdl/osvvm/MemoryPkg_orig_c.vhd
WARNING - /usr/local/lib/python3.10/dist-packages/vunit_hdl-4.7.0-py3.10.egg/vunit/vhdl/osvvm/MemoryPkg_c.vhd: package 'memorypkg' previously defined in /usr/local/lib/python3.10/dist-packages/vunit_hdl-4.7.0-py3.10.egg/vunit/vhdl/osvvm/MemoryPkg.vhd
modelsim
WARNING - Entity tb_clk matches testbench name regex ^(tb_.*)|(.*_tb)$ but has no generic runner_cfg and will therefore not be run.
in file /home/mfj/git/PRIVATE/Ruskuls/HyperRAM/simulation-vunit/test/tb_clk.vhd
Re-compile not needed

Starting tb_lib.hyperram_tb.bulk_write_bulk_read_operation
Output file: /home/mfj/git/PRIVATE/Ruskuls/HyperRAM/simulation-vunit/vunit_out/test_output/tb_lib.hyperram_tb.bulk_write_bulk_read_operation_6136157e753207deb6e4e1b3df8ddaee336c276e/output.txt
# vsim -modelsimini /home/mfj/git/PRIVATE/Ruskuls/HyperRAM/simulation-vunit/vunit_out/modelsim/modelsim.ini -wlf /home/mfj/git/PRIVATE/Ruskuls/HyperRAM/simulation-vunit/vunit_out/test_output/tb_lib.hyperram_tb.bulk_write_bulk_read_operation_6136157e753207deb6e4e1b3df8ddaee336c276e/modelsim/vsim.wlf -quiet -t ps -onfinish stop tb_lib.hyperram_tb(bench) -L vunit_lib -L osvvm -L src_lib -L tb_lib -g/hyperram_tb/runner_cfg="active python runner : true,enabled_test_cases : bulk_write_bulk_read_operation,output path : /home/mfj/git/PRIVATE/Ruskuls/HyperRAM/simulation-vunit/vunit_out/test_output/tb_lib.hyperram_tb.bulk_write_bulk_read_operation_6136157e753207deb6e4e1b3df8ddaee336c276e/,tb path : /home/mfj/git/PRIVATE/Ruskuls/HyperRAM/simulation-vunit/test/,use_color : true"
# Start time: 11:04:48 on Jun 02,2023
# ** Note: (vsim-8009) Loading existing optimized design _opt
# //  Questa Intel Starter FPGA Edition-64
# //  Version 2021.2 linux_x86_64 Apr 14 2021
# //
# //  Copyright 1991-2021 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# ** Error: (vsim-3171) Could not find machine code for '/home/mfj/git/PRIVATE/Ruskuls/HyperRAM/simulation-vunit/vunit_out/modelsim/libraries/osvvm.memorypkg'.
# No such file or directory. (errno = ENOENT)
# Error loading design
Error loading design
# End time: 11:04:48 on Jun 02,2023, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
fail (P=0 S=0 F=1 T=2) tb_lib.hyperram_tb.bulk_write_bulk_read_operation (1.0 seconds)

Starting tb_lib.hyperram_tb.seq_write_read_operation
Output file: /home/mfj/git/PRIVATE/Ruskuls/HyperRAM/simulation-vunit/vunit_out/test_output/tb_lib.hyperram_tb.seq_write_read_operation_917269d7a97d77486a99e6bbe21f47d14b526816/output.txt
# vsim -modelsimini /home/mfj/git/PRIVATE/Ruskuls/HyperRAM/simulation-vunit/vunit_out/modelsim/modelsim.ini -wlf /home/mfj/git/PRIVATE/Ruskuls/HyperRAM/simulation-vunit/vunit_out/test_output/tb_lib.hyperram_tb.seq_write_read_operation_917269d7a97d77486a99e6bbe21f47d14b526816/modelsim/vsim.wlf -quiet -t ps -onfinish stop tb_lib.hyperram_tb(bench) -L vunit_lib -L osvvm -L src_lib -L tb_lib -g/hyperram_tb/runner_cfg="active python runner : true,enabled_test_cases : seq_write_read_operation,output path : /home/mfj/git/PRIVATE/Ruskuls/HyperRAM/simulation-vunit/vunit_out/test_output/tb_lib.hyperram_tb.seq_write_read_operation_917269d7a97d77486a99e6bbe21f47d14b526816/,tb path : /home/mfj/git/PRIVATE/Ruskuls/HyperRAM/simulation-vunit/test/,use_color : true"
# Start time: 11:04:49 on Jun 02,2023
# ** Note: (vsim-8009) Loading existing optimized design _opt1
# //  Questa Intel Starter FPGA Edition-64
# //  Version 2021.2 linux_x86_64 Apr 14 2021
# //
# //  Copyright 1991-2021 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# ** Error: (vsim-3171) Could not find machine code for '/home/mfj/git/PRIVATE/Ruskuls/HyperRAM/simulation-vunit/vunit_out/modelsim/libraries/osvvm.memorypkg'.
# No such file or directory. (errno = ENOENT)
# Error loading design
Error loading design
# End time: 11:04:49 on Jun 02,2023, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
fail (P=0 S=0 F=2 T=2) tb_lib.hyperram_tb.seq_write_read_operation (1.0 seconds)

==== Summary =============================================================
fail tb_lib.hyperram_tb.bulk_write_bulk_read_operation (1.0 seconds)
fail tb_lib.hyperram_tb.seq_write_read_operation       (1.0 seconds)
==========================================================================
pass 0 of 2
fail 2 of 2
==========================================================================
Total time was 2.0 seconds
Elapsed time was 2.0 seconds
==========================================================================
Some failed!

@Ruskuls
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Ruskuls commented Jun 2, 2023

I will try to install Questa Sim on my local machine and replicate this error.

@Ruskuls
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Ruskuls commented Jun 6, 2023 •
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Hi, I did manage to install Questa simulator on my work machine (windows 10).
ENV looks like this
image

after running run.py script all is working as expected.
image

did you install vunit like this?
pip install vunit-hdl

P.S. Python 3.10.10 is used

@MJoergen
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MJoergen commented Jun 7, 2023

Thank you for this extra information. I've finally managed to run this test on my own machine. It turned out I had a very old version of ModelSim (10.6c). I've now installed intelFPGA_lite/22.1std (with the QuestaSim Free Starter Edition), and now I can run the simulation as well.

@MJoergen MJoergen merged commit acd91ea into MJoergen:main Jun 7, 2023
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@Ruskuls @MJoergen