A bilingual engineering course on Software-Defined Radio that connects signal theory, DSP, fixed-point modeling, HDL/FPGA flow, RF frontend understanding, TX/RX chains, synchronization, IQ recording, practical electronics and final engineering reports.
Это двуязычный инженерный курс по SDR, который связывает теорию сигналов, DSP, fixed-point моделирование, HDL/FPGA flow, радиотракт, TX/RX цепочки, синхронизацию, запись IQ, практическую электронику и итоговые инженерные отчёты.
git clone https://github.com/Lay007/zynq-sdr-course.git
cd zynq-sdr-course
python tools/tasks.py install
python tools/tasks.py docs
python tools/tasks.py labsFor the full local smoke check, install Icarus Verilog (iverilog) and run:
python tools/tasks.py smokeДля полной локальной проверки установите Icarus Verilog (iverilog) и выполните:
python tools/tasks.py smokeUseful commands:
| Command | Purpose |
|---|---|
python tools/tasks.py install |
install Python dependencies |
python tools/tasks.py docs |
strict MkDocs build |
python tools/tasks.py serve |
local MkDocs preview |
python tools/tasks.py labs |
run representative executable Python labs |
python tools/tasks.py hdl |
run Block 5 Verilog smoke tests |
python tools/tasks.py smoke |
run docs + labs + HDL checks |
python tools/tasks.py clean |
remove generated local build artifacts |
GNU Make targets remain available as a shorthand for Unix-like environments.
| Page | Why open it |
|---|---|
| Course demo dashboard | fast visual overview of executable course artifacts |
| Visual course map | complete engineering route from theory to final project |
| Portfolio view | what this repository demonstrates professionally |
| Model → FPGA → RF → Measurement | core system-level route |
| Real data policy | how to store and describe real IQ captures |
| Reproducibility guide | how to reproduce generated results |
| Layer | Engineering result |
|---|---|
| Signals and spectra | sampling, bandwidth, aliasing, modulation basics |
| DSP modeling | FFT, FIR, mixing, decimation, reference plots |
| Fixed-point DSP | word length, scaling, quantization, implementation error |
| HDL / FPGA | Verilog blocks, streaming DSP, latency, testbenches |
| Zynq + AD9363 hardware | RF configuration, board-level signal generation and capture |
| TX/RX chains | DUC/DDC, frequency plans, loopback metrics |
| Synchronization | CFO, phase, timing recovery, EVM and BER |
| IQ recording | CI16/CU8/CF32 readers, metadata and capture quality checks |
| Electronics / KiCad | attenuators, RC filters, RF safety and schematic discipline |
| Integrated project | requirements, architecture, measurement report and portfolio output |
This repository is not just a collection of markdown notes. It is structured as a teaching, implementation and verification path from first SDR concepts to measurement-oriented project work.
Этот репозиторий — не просто набор markdown-файлов. Он оформлен как учебный, инженерный и верифицируемый маршрут от первых понятий SDR до проектной работы с измерениями.
The course is designed around a complete engineering chain:
theory -> modeling -> fixed-point -> HDL/FPGA -> RF frontend -> TX/RX -> synchronization -> IQ recording -> electronics -> integrated project
теория -> моделирование -> fixed-point -> HDL/FPGA -> радиотракт -> TX/RX -> синхронизация -> запись IQ -> электроника -> интегрированный проект
Representative executable labs can be launched with one command:
python tools/run_all_labs.pyThe script creates:
docs/assets/course_reproducibility_summary.json
docs/assets/course_reproducibility_summary.md
The full smoke workflow checks:
- MkDocs strict build;
- representative Python labs;
- Block 5 Verilog testbenches;
- generated summary artifacts.
Auto-generated IEEE-style plots are produced by GitHub Actions and stored in docs/assets.
Графики в IEEE-style автоматически генерируются через GitHub Actions и сохраняются в docs/assets.
| Lab | Demo plot | Engineering meaning |
|---|---|---|
| Lab 1 | Tone FFT | Peak frequency and noise floor |
| Lab 2 | AM vs FM spectrum | Modulation bandwidth comparison |
| Lab 3 | QPSK constellation | IQ quality and phase/noise effects |
| Lab 4 | Synchronization impact | CFO correction effect |
| Lab 5 | EVM vs impairments | Quantitative impairment comparison |
| Lab 6 | BER performance | End-to-end receiver quality |
The current hands-on setup includes an external receiver and a board-level SDR platform for practical experiments.
Текущая практическая аппаратная база включает внешний приёмник и SDR-платформу на уровне платы для лабораторных работ и экспериментов.
flowchart TB
MODEL["1. Reference model<br/>MATLAB / Simulink expected waveform"]
CFG["2. Experiment configuration<br/>frequency, gain, bandwidth and sample rate"]
ZYNQ["3. Zynq-7020 + AD9363<br/>FPGA, ARM control and RF frontend"]
PATH["4. RF path<br/>coax + attenuation or controlled over-the-air link"]
RX["5. External receiver<br/>RTL-SDR as independent observation instrument"]
RECORD["6. Observation and recording<br/>HDSDR spectrum, waterfall and IQ capture"]
ANALYSIS["7. Offline analysis<br/>MATLAB, Python, C++ or GNU Radio replay"]
MODEL --> CFG --> ZYNQ --> PATH --> RX --> RECORD --> ANALYSIS
ANALYSIS -. model correction .-> MODEL
ANALYSIS -. parameter tuning .-> CFG
Practical flow: generate a signal on the Zynq/AD9363 platform → receive it with RTL-SDR → observe it in HDSDR → record IQ samples → analyze the recording in multiple software environments.
Практический поток: сформировать сигнал на платформе Zynq/AD9363 → принять его через RTL-SDR → наблюдать в HDSDR → записать IQ-данные → проанализировать запись в нескольких программных средах.
blocks/block_01_intro_sdrblocks/block_02_signals_and_samplingblocks/block_03_dsp_basicsblocks/block_04_simulink_and_fixed_pointblocks/block_05_fpga_hdl_flowblocks/block_06_rf_frontend_and_ad9363blocks/block_07_tx_rx_chainsblocks/block_08_modulation_and_synchronizationblocks/block_09_recording_and_analysis_toolsblocks/block_10_kicad_and_basic_electronicsblocks/block_11_integrated_sdr_projectblocks/block_12_final_projects
Reusable templates are stored in templates/:
templates/capture_metadata.template.json
templates/lab_report.template.md
templates/final_project_report.template.md
templates/rf_safety_checklist.template.md
templates/measurement_uncertainty_budget.template.md
MIT License