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KubEF
commented
Mar 2, 2026
KubEF
commented
- Black box wrapper for UART Master IP-core
- Helper functions for iteration over ram by bytes
- Script for build and synthesis
- Implement UART transmitter in the main circuit
gsvgit
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Mar 3, 2026
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gsvgit
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I think we should start adding comments to the code, at least with a description of each file's content and purpose.
| set_option -top_module topEntity | ||
| set_option -verilog_std sysv2017 | ||
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| # add_file -type verilog ../lamagraph-core/hdl/systemverilog/Core.Core.topEntity/topEntity.sv |
| @@ -0,0 +1,37 @@ | |||
| {-# LANGUAGE MultiParamTypeClasses #-} | |||
| @@ -0,0 +1 @@ | |||
| ((S(K((S(K((S(KS))K)))((S(KS))K))))(S(K((S(K((S(KS))K)))((S(KS))K))))) | |||
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Please, add readme with brief description of tests. I guess that these are well-known examples for SKI, but it may be not do obvious.
| @@ -0,0 +1,25 @@ | |||
| import qualified Clash.Prelude as C | |||
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I think we should start adding comments to the code, at least with a description of each file's content and purpose.
| @@ -1,6 +1,217 @@ | |||
| {-# LANGUAGE UndecidableInstances #-} | |||
Also bump graph rewriting version for versions resolving
Ability to convert data to and from binary format
* Iterating by ram (via RamForm) * Iterating by bytes in `Maybe (Node pn at)` * Black box wrapper for UART Master IP-core * Configuration of UART in data types according to the documentation: https://www.gowinsemi.com/upload/database_doc/2072/document/626a18f79b6dc.pdf
Codecov Report❌ Patch coverage is 📢 Thoughts on this report? Let us know! |
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