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feat(arithmetization): support sharding of interpreter() function #3850

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feat(arithmetization): support sharding of interpreter() function #3850

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4040534
feat: support sharding of interpreter() function
DavePearce Aug 25, 2026
6193532
fix: update ZkC to specific commit
DavePearce Aug 25, 2026
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2 changes: 1 addition & 1 deletion arithmetization/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ REPO_ROOT := $(abspath $(MAKEFILE_DIR)/..)
ZKC ?= $(REPO_ROOT)/zkc
ZKC_REPO ?= https://github.com/LFDT-Lineth/zkc.git
# Optional: pin a commit or branch (e.g. 763f30878e5fc260f0d88863c9883c904f8fc056). Leave empty for default branch.
ZKC_REF ?= v1.2.29
ZKC_REF ?= 0df4374902997b241279b75582ef843ae4048426

# Used to install Sail for ACT4 host builds.
ACT4_RISCV_DIR ?= $(HOME)/riscv
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12 changes: 6 additions & 6 deletions arithmetization/src/main/lib/keccak/impl.zkc
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Expand Up @@ -193,7 +193,7 @@ fn kec_theta<keccak_state>() {

for i_minus_one:u5 = 0; i_minus_one<5; i_minus_one = i_minus_one + 1 {
var i:u5 = i_minus_one + 1
keccak_state[D + (mod5(i) as u7)] = keccak_state[C + (i_minus_one as u7)] ^ bit_rotl64(keccak_state[C + (mod5(i + 1) as u7)], 1)
keccak_state[D + (mod5[i] as u7)] = keccak_state[C + (i_minus_one as u7)] ^ bit_rotl64(keccak_state[C + (mod5[i + 1] as u7)], 1)
}

for j:u7 = 0; j<5; j = j + 1 {
Expand All @@ -211,11 +211,11 @@ fn kec_theta<keccak_state>() {
fn kec_rho<keccak_state>() {

for j:u3 = 0; j<5; j = j + 1 {
keccak_state[ROW0 + (j as u7)] = bit_rotl64(keccak_state[ROW0 + (j as u7)], rot_offset(0, j))
keccak_state[ROW1 + (j as u7)] = bit_rotl64(keccak_state[ROW1 + (j as u7)], rot_offset(1, j))
keccak_state[ROW2 + (j as u7)] = bit_rotl64(keccak_state[ROW2 + (j as u7)], rot_offset(2, j))
keccak_state[ROW3 + (j as u7)] = bit_rotl64(keccak_state[ROW3 + (j as u7)], rot_offset(3, j))
keccak_state[ROW4 + (j as u7)] = bit_rotl64(keccak_state[ROW4 + (j as u7)], rot_offset(4, j))
keccak_state[ROW0 + (j as u7)] = bit_rotl64(keccak_state[ROW0 + (j as u7)], rot_offset[0, j])
keccak_state[ROW1 + (j as u7)] = bit_rotl64(keccak_state[ROW1 + (j as u7)], rot_offset[1, j])
keccak_state[ROW2 + (j as u7)] = bit_rotl64(keccak_state[ROW2 + (j as u7)], rot_offset[2, j])
keccak_state[ROW3 + (j as u7)] = bit_rotl64(keccak_state[ROW3 + (j as u7)], rot_offset[3, j])
keccak_state[ROW4 + (j as u7)] = bit_rotl64(keccak_state[ROW4 + (j as u7)], rot_offset[4, j])
}
}

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35 changes: 25 additions & 10 deletions arithmetization/src/main/riscv/interpreter.zkc
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Expand Up @@ -8,13 +8,20 @@ include "instruction_processing/s_type.zkc"
include "instruction_processing/j_type.zkc"
include "instruction_processing/u_type.zkc"

fn interpreter<registers, ram, keccak_state, poseidon2_state>(instruction:u32, pc:Address, output_write_address:OutputAddress) -> (new_pc:Address, new_output_write_address:OutputAddress) {
fn interpreter<registers, ram, keccak_state, poseidon2_state>(clk:u32, pc:Address, output_write_address:OutputAddress) -> ! {

var instruction:Instruction
var instruction_parameters:u25
var instruction_type:Type
var opcode:Opcode
var new_output_write_address:OutputAddress
var new_pc:Address
//
printf "\n----------------------------------------------------------------- PC=%d, clock cycle: %d\n", pc, clk
// Decode
instruction = read_32(pc) as Instruction
instruction_parameters::opcode = instruction
instruction_type = instruction_type_from_opcode(opcode)
instruction_type = instruction_type_from_opcode[opcode]

// TODO: handle the case where rd = 0: we will handle this in RAM itself, likely by adding an extra read-write pair
// to reset the value in registers[rd] to 0
Expand All @@ -23,40 +30,48 @@ fn interpreter<registers, ram, keccak_state, poseidon2_state>(instruction:u32, p
case R_TYPE: {
new_output_write_address = process_R_type_instruction(opcode, instruction_parameters, output_write_address)
new_pc = pc + 4 as Address
// TODO: rm me one handle by RAM itself
registers[0] = 0
return
}
case I_TYPE: {
new_pc = process_I_type_instruction(opcode, instruction_parameters, pc)
new_output_write_address = output_write_address
}
case S_TYPE: {
process_S_type_instruction(instruction_parameters)
new_pc = pc + 4 as Address
new_output_write_address = output_write_address
}
case B_TYPE: {
new_pc = process_B_type_instruction(instruction_parameters, pc)
new_output_write_address = output_write_address
}
case U_TYPE: {
process_U_type_instruction(opcode, instruction_parameters, pc)
new_output_write_address = output_write_address
new_pc = pc + 4 as Address
}
case J_TYPE: {
new_pc = process_J_type_instruction(instruction_parameters, pc)
new_output_write_address = output_write_address
}
case MISC_MEM_TYPE: {
// FENCE / FENCE.I — no caches, single hart, so this is a no-op.
new_pc = pc + 4 as Address
new_output_write_address = output_write_address
}
default: {
printf "[ERROR] Unsupported instruction type %d\n", instruction_type
fail
}
}
// Check whether or not this has terminated
if new_pc != MAX_UINT_64 {
// Forcefully set registers[0] = zero back to 0
registers[0] = 0
//
interpreter!(clk + 1, new_pc, new_output_write_address)
}
// Termination
done
}

// Forcefully set registers[0] = zero back to 0
registers[0] = 0

// true in all cases, except potentially for R_TYPE instructions, for which already returned
new_output_write_address = output_write_address
}
24 changes: 5 additions & 19 deletions arithmetization/src/main/riscv/main.zkc
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Expand Up @@ -14,12 +14,9 @@ include "memory.zkc"

// TODO @Ghost
fn main<registers, ram, keccak_state, poseidon2_state>() {
var instruction:Instruction
var clock_cycle:u32 = 0
var entry_point:Address
var pc:Address
var blobs_count:u64
entry_point, blobs_count = entry_point_and_blobs_count[0]
var pc:Address = entry_point
pc, blobs_count = entry_point_and_blobs_count[0]

var internal_offset:Length = 0 // internal offset to blobs_data
for i:u64 = 0; i<blobs_count; i = i + 1 {
Expand All @@ -33,19 +30,8 @@ fn main<registers, ram, keccak_state, poseidon2_state>() {
}
internal_offset = internal_offset + blob_size
}

var output_write_address:OutputAddress = 0

// We interpret pc == MAX_UINT_64 as the stop signal, which is set by the ecall instruction
while pc != MAX_UINT_64 {
instruction = read_32(pc) as Instruction

// clock cycle starts at 1
clock_cycle = clock_cycle + 1
printf "\n----------------------------------------------------------------- PC=%d, clock cycle: %d\n", pc, clock_cycle

// update pc and output_write_address
pc, output_write_address = interpreter(instruction, pc, output_write_address)
}
// Begin execution
interpreter!(0, pc, 0)
}


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