Add UpSample2D Layer Support for Encoder-Decoder Architectures#17

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STAmirr wants to merge 611 commits intoKastnerRG:masterfrom

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Commits on Jul 9, 2023

Update testbench structure to allow multiple iterations
Aba
committed

Commits on Jul 11, 2023

Fix: multiple iterations
Aba
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Commits on Jul 21, 2023

Fix bug in axis_pixels. Update alex_axis_adapter_any for verilator
Aba
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Commits on Jul 22, 2023

Change linux sim to verilator
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Commits on Jul 23, 2023

Refactor
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Get compiled verilator
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Commits on Jul 25, 2023

Add notebooks for pynq firmware & perfomance
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Commits on Jul 29, 2023

Add new bundle from zhenghua
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Commits on Jul 30, 2023

Refactor
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Commits on Aug 1, 2023

Refactor
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Commits on Aug 2, 2023

Add export
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Commits on Aug 14, 2023

Integerate new bundle into param_test
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Commits on Aug 21, 2023

Feature: allow CI > WRAM/KH
Aba
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Commits on Aug 24, 2023

Entire model in testbench - sv structs
Aba
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Commits on Aug 25, 2023

Replace AXI-Stream output with ping-pong buffer. Works for K!=1
Aba
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Commits on Aug 26, 2023

Commits on Aug 31, 2023

Commits on Sep 2, 2023

Commits on Sep 3, 2023

Commits on Sep 4, 2023

Commits on Sep 5, 2023

Update counters in callback with all indices
Aba
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Commits on Sep 6, 2023

Update README
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Commits on Sep 11, 2023

Write to byte memory from C and read into files
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Commits on Sep 12, 2023

Add all Ps together in runtime
Aba
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Add new bundle for p=1 case
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Move all memory from SV to C. Works in Verilator
Aba
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Commits on Sep 13, 2023

Mark output ports with m_ for ASIC pin placement
Aba
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Commits on Sep 15, 2023

Add bias; works for all conv2d, not dense
Aba
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Commits on Sep 16, 2023

Commits on Sep 17, 2023

Add support for quantized_bits(keep_neg=False) and quantized_relu(slope=0)
Aba
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Commits on Oct 18, 2023

Add & test tiling in python
Aba
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Commits on Oct 19, 2023

Fix bits=8
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Commits on Oct 24, 2023

Fix H-padding
Aba
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Fix runtime - switch order of N and L
Aba
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Commits on Oct 26, 2023

Fix tiling (py) cm/cmp0
Aba
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Python - tiling all layers
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Temp disable last layer (since hwc tiling)
Aba
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Refactor runtime
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Seperate debug outputs for raw, summed and processed
Aba
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Commits on Oct 27, 2023

Commits on Oct 28, 2023

Refactor runtime
Aba
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Commits on Oct 29, 2023

Commits on Oct 30, 2023

Commits on Nov 1, 2023

Make const
Aba
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Cleanup
Aba
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Cleanup spacing in model.h
Aba
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Commits on Nov 4, 2023

Add bit-packing in C runtime
Aba
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Commits on Nov 6, 2023

Add buffer allocation. Prepare for chaining
Aba
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Commits on Nov 7, 2023

Commits on Nov 9, 2023

Update readme
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Commits on Nov 11, 2023

Commits on Nov 13, 2023

Add residual add
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More complex residual add example
Aba
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Fix bug in N_BUNDLES=1 case
Aba
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Commits on Nov 15, 2023

Python packaging & documentation
Aba
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Commits on Nov 16, 2023

Commits on Nov 17, 2023

Move dependencies to TOML
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Commits on Nov 18, 2023

Integrate Hardware class into param_test.py
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Fix vivado flow
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Commits on Nov 19, 2023

Move hw params to pytest product
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Reorganize tcl files
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Commits on Nov 20, 2023

Commits on Nov 21, 2023

Replace OUT_RAM_SWITCH with regular S2MM DMA
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Update firmware with for loop and wait
Aba
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Clean up indent
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Add FPGA firmware - single_transfer.c
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Commits on Nov 22, 2023

Update firmware to compile on Vitis
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Update model to export W+B+X as one bin
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Refactor: p_mem-> mem.
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Commits on Nov 29, 2023

Commits on Nov 30, 2023

Fix verilator error for pipeline
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Fix all verilator warnings
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Commits on Dec 1, 2023

Update title
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Commits on Dec 3, 2023

Full network runs on FPGA - except softmax
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Commits on Dec 4, 2023

Commits on Dec 5, 2023

Update vivado.tcl to have 3, 128-bit S_AXI ports
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Rename example to sim.c to avoid confusion
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Add resnet50
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Commits on Dec 6, 2023

Commits on Dec 7, 2023

update example
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Fix width mismatch issue in zcy102.tcl
Aba
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Fix acc_width < y_bits issue
Aba
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Add support for add & pool quant
Aba
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Commits on Dec 9, 2023

Update README.md
abarajithan11
authored

Commits on Dec 22, 2023

Commits on Dec 26, 2023

Fix edges count
Aba
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Commits on Feb 16, 2024

Relative paths added to tcl files, SRAM generation tcl automation, Verified for 1000MHz synthesis and PnR
RaviduHM99
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Commits on Mar 16, 2024

Commits on Mar 19, 2024

Commits on Mar 20, 2024

Fix VCS errors & warnings
Aba
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Commits on Mar 21, 2024

Update delay mul to avoid VCS warning
Aba
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Commits on Mar 25, 2024

Remove all X: Add reset to all registers, add initial zeros to tb, remove unused wires
Aba
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Commits on Apr 16, 2024

Fix prob=1 bug
Aba
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Avoid duplicate clocking
Aba
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Commits on Apr 22, 2024

Seperate ocm in runtime
Aba
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Commits on Apr 25, 2024

Move cache-flush to after each write
Aba
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Commits on May 1, 2024

Add signal m_bpt to give bytes per transfer
Aba
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Update Y_BITS to Y_OUT_BITS
Aba
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Commits on May 5, 2024

Remove KH/2 padding for KH=0
Aba
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Update readme & swicth testbench from clocking blocks
Aba
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Update README.md

abarajithan11
authored and
Aba
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Commits on May 13, 2024

Commits on May 17, 2024

cleanup
awengz
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reversed pipeline
awengz
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Commits on May 21, 2024

cleanup for asic
awengz
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Commits on Jun 17, 2024

Commits on Jun 20, 2024

new output shifter working
awengz
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Commits on Jun 26, 2024

new_api: core+act float works
Aba
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new_api: pool+act float works
Aba
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Commits on Jun 30, 2024

stash
awengz
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Commits on Jul 2, 2024

new_api: add,softmax float works
Aba
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new_api: dense float works
Aba
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Commits on Jul 8, 2024

move stuff around
awengz
committed

Commits on Jul 12, 2024

stash
awengz
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Commits on Jul 13, 2024

working?
awengz
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Commits on Jul 15, 2024

Commits on Jul 17, 2024

Commits on Jul 18, 2024

passing -- cleanup needed
awengz
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new_api: Act works
Aba
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new_api: Pool works
Aba
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new_api: export_inference() works
Aba
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cleanup, added comments
awengz
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Commits on Jul 19, 2024

Commits on Jul 20, 2024

Fix some verilator warnings
Aba
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Fix merge
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Rename load_y, demo_full
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Rename top
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Fix verilator issue
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Update alex ips for asic
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Parametrize config & mem base addr
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Merge with dma_controller
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Zero verilator warnings
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Take max_n_bundles as a param=64
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Commits on Jul 21, 2024

New API matches param_test.py
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Merge new_api + dma_controller + pipelined
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Make new api the default
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Update types in runtime to i8,u8
Aba
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Move pixel header to DMA tuser
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Commits on Jul 22, 2024

Move axis_header to DMA, change AXI_WIDTH=32
Aba
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Make non-debug mode default
Aba
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Make vivado happy
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Rename, remove debug buffers
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synthesis on quartus
awengz
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Commits on Jul 23, 2024

Verified on FPGA
zhenghuama
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Added restrict to firmware
Aba
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Minor cleanup
Aba
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Tested multiple runs
Aba
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Clean up Bundle_t
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Commits on Jul 25, 2024

Commits on Jul 31, 2024

Add & fix resnet50
Aba
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Commits on Aug 1, 2024

Commits on Aug 2, 2024

fix stuck.py issue
awengz
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ResNet-50 passed
Aba
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Commits on Aug 3, 2024

Add jettagger
Aba
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Commits on Nov 22, 2024

Fix example & readme
abarajithan11
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Commits on Feb 7, 2025

Minor changes
Aba
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Commits on Apr 28, 2025

Update package dependancy
Aba
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Add vcd
Aba
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Commits on Sep 25, 2025

Add optional trace
abarajithan11
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Commits on Oct 17, 2025

Update resnet settings
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Commits on Oct 21, 2025

Add matmul
Aba
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Update zcu104
abarajithan11
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