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@KULeuven-MICAS

MICAS (KU Leuven)

We initiate, drive and realize breakthroughs in micro and nano-electronic systems, for a better and more comfortable life for everyone.
README.md

This is the GitHub organization for the MICAS research group at KU Leuven. Here you can find open-source projects made by us and our collaborators.

SNAX Framework

Snax is an end-to-end, open-source multi-accelerator cluster design framework. It consists of the snax-mlir compile toolchain and the snax cluster hardware framework.

SNAX-MLIR Repo

SNAX Cluster Repo

HeMAiA Repo

Fast DNN Accelerator Design Space Exploration Frameworks

ZigZag Repo | Documentation | Tutorial

ZigZag targets rapid DSE for DNN accelerator platforms supporting an broad set of hardware architectures and workload scheduling scenarios beyond other existing frameworks.
The latest version of ZigZag includes support for modeling of analog and digital in-memory computing accelerators and estimating both peak/workload performance at the macro and system level.

Stream Repo | Documentation | Tutorial

Stream is an extension of ZigZag capable of modeling multi-core DNN acceleration employing fine-grained layer-fused processing.

ZigZag-LLM Repo

ZigZag-LLM is a framework to rapidly model Large Language Models on dedicated, single-core accelerators and facilitates early identification of energy bottlenecks within the hardware architecture.

DeFiNes Repo

DeFiNes extends ZigZag to enable the DSE of cross-layer depth-first scheduling (a.k.a. layer fusion, or cascaded execution)

Accelerator-aware Neural Network Deployment

HTVM Repo

HTVM is a neural network compiler based on Dory and TVM that allows for efficient neural network deployment on heterogenous TinyML platforms with scratchpad-memory accelerators.

Standalone hardware blocks

Chisel-Float

Floating point units (add, mul, FMA) for transprecision computing in arbitrary FP formats, wrapped and tested in Chisel.

Artificial Intelligence System on Chips (SoCs)

TinyVers Repo

TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme Edge (JSSC'23)

TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge (VLSI Technology and Circuits'23)

DIANA

DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC (ISSCC'22)

DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge (JSSC'23)

DPU Repo

DPU: DAG Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm (JSSC'22)

DPU-v2 Repo

DPU-v2: Energy-efficient execution of irregular directed acyclic graphs (MICRO'22)



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  1. zigzag zigzag Public

    HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators

    C++ 156 48

  2. stream stream Public

    Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.

    Python 58 27

  3. htvm htvm Public

    Efficient Neural Network Deployment on Heterogenous TinyML Platforms

    Python 15

  4. snax_cluster snax_cluster Public

    Forked from pulp-platform/snitch_cluster

    A heterogeneous accelerator-centric compute cluster

    SystemVerilog 24 12

  5. snax-mlir snax-mlir Public

    Driving Snax with MLIR

    Python 15 4

  6. zigzag-llm zigzag-llm Public

    Model LLM inference on single-core dataflow accelerators

    Python 13 3

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