GitHub - Elizaag/Phase-5: Phase 5, creating a multi cycle processor part of our pipeline.

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
ALU.v		ALU.v
ALU_CONTROL.v		ALU_CONTROL.v
BRANCH_JUMP.v		BRANCH_JUMP.v
CONTROL.v		CONTROL.v
DATA_MEMORY.v		DATA_MEMORY.v
DECODER.v		DECODER.v
EX_MEM.v		EX_MEM.v
FORWARDING_UNIT.v		FORWARDING_UNIT.v
HAZARD_DETECTION.v		HAZARD_DETECTION.v
ID_EX.v		ID_EX.v
IF_ID.v		IF_ID.v
INSTRUCTION_MEMORY.v		INSTRUCTION_MEMORY.v
MEM_WB.v		MEM_WB.v
MUX_2_1.v		MUX_2_1.v
MUX_3_1.v		MUX_3_1.v
Phase 5.pdf		Phase 5.pdf
REGISTER.v		REGISTER.v
RISCV_TOP.v		RISCV_TOP.v
assembler.py		assembler.py
group_contribution.pdf		group_contribution.pdf
make_submission.sh		make_submission.sh
signals.yaml		signals.yaml