C++ parser for SystemVerilog files using ANTLR4. Checks syntax and reports errors.
git clone --recurse-submodules https://github.com/DaryaNechaeva/SystemVerilog-parser.git
cd SystemVerilog-parser
mkdir build && cd build
cmake .. && make
./sv-parser design.sv# Single file
./sv-parser file.sv
# Multiple files
./sv-parser *.sv
# Output examples:
# PASS: design.sv
# FAIL: test.sv (2 errors)
# ERROR: missing.sv (cannot open)SystemVerilog-parser/
├── src/lib/main.cpp # Main code
├── generated/ # ANTLR4 parser files
├── antlr4/ # ANTLR4 runtime (submodule)
├── CMakeLists.txt # Build config
└── README.md
mkdir build
cd build
cmake ..
make- Main code: MIT License (see LICENSE)
- ANTLR4 runtime: BSD 3-Clause License (see licenses/ANTLR4-LICENSE)
Note: Independent project, not affiliated with The ANTLR Project.