-
Notifications
You must be signed in to change notification settings - Fork 242
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
feat(docs): added documentation for force gate #354
base: master
Are you sure you want to change the base?
Conversation
✅ Deploy Preview for cv-doc ready!
To edit notification comments on pull requests, go to your Netlify site configuration. |
cc @Prerna-0202 |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
What is a force gate? I got your idea but still wondering if this terminology even make sense ? Like I have never encountered this term "force gate" in VLSI design.
Can you please cite any source any paper or book where "force gate" term has been used ?
and I believe it is more of a tri-state buffer logic.
@ayan-biswas0412 When writing documentation, I couldn't find information outside of CircuitVerse. Based on what I learned using this element i wrote that. like its properties and all |
yeah got your point, @Prerna-0202 looking forward to your comments. Do we really need to add this as a "force gate" because it is simple a latch or a tri-state buffer which sense enable signal and sends input to output. |
Fixes #343
Changes done:
Screenshots:
Preview Link(s):
✅️ By submitting this PR, I have verified the following