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16 Open 42 Closed
16 Open 42 Closed
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Issues list

Load Hazard Unit Hardware race Design task Design is required, RTL intervention invalid
#88 opened Apr 5, 2022 by ChrisShakkour RTL0.3 - RV32I
@ChrisShakkour
Stack pointer register Tracker (sp) Feature added feature or enhancment Verification task verif task, testbench and env
#87 opened Feb 18, 2022 by ChrisShakkour RTL0.3 - RV32I
@ChrisShakkour
Data memory RTL cleaning Design task Design is required, RTL intervention
#84 opened Jan 26, 2022 by ChrisShakkour RTL0.5 - CSR
@ChrisShakkour
Assertions - Signal Indication that something wrong has happened. (Or coverage point - something should happen) Verification task verif task, testbench and env
#83 opened Jan 18, 2022 by amichai-bd RTL0.3 - RV32I
@ChrisShakkour @shahardror1
ALU tracker
#82 opened Jan 18, 2022 by ChrisShakkour RTL0.3 - RV32I
@ChrisShakkour @shahardror1
End of test checkers Feature added feature or enhancment Software task C/asm test creation, scripting
#78 opened Jan 16, 2022 by ChrisShakkour RTL0.5 - CSR
@ChrisShakkour @shahardror1
Load Hazzard validation Verification task verif task, testbench and env
#77 opened Jan 16, 2022 by ChrisShakkour RTL0.5 - CSR
@ChrisShakkour @shahardror1
RTL simulation automatic flow Feature added feature or enhancment Software task C/asm test creation, scripting
#75 opened Jan 13, 2022 by ChrisShakkour RTL0.5 - CSR
@ChrisShakkour
to add Code simulation run c test using risc-v toolchain elf-run Feature added feature or enhancment Software task C/asm test creation, scripting
#74 opened Jan 13, 2022 by ChrisShakkour RTL0.3 - RV32I
@ChrisShakkour
Decode module state machine documentation documentation Improvements or additions to documentation
#65 opened Jan 2, 2022 by ChrisShakkour RTL0.3 - RV32I
@ChrisShakkour
M-extension multi-cycle machine initial drafts Feature added feature or enhancment POC Proof-Of-Consept
#63 opened Jan 2, 2022 by ChrisShakkour RTL0.5 - CSR
@ChrisShakkour @shahardror1
memory Heavy validation test Software task C/asm test creation, scripting Verification task verif task, testbench and env
#62 opened Jan 2, 2022 by ChrisShakkour RTL0.3 - RV32I
@ChrisShakkour @shahardror1
1
stalling control signals Design task Design is required, RTL intervention Feature added feature or enhancment
#50 opened Dec 20, 2021 by ChrisShakkour RTL0.5 - CSR
@ChrisShakkour
Register File tracker Feature added feature or enhancment Verification task verif task, testbench and env
#41 opened Nov 29, 2021 by ChrisShakkour RTL0.5 - CSR
@shahardror1
to add a memory golden image snapshot from compiled Code. Feature added feature or enhancment Verification task verif task, testbench and env
#36 opened Nov 28, 2021 by ChrisShakkour RTL0.3 - RV32I
@shahardror1
Performance trackers Feature added feature or enhancment Verification task verif task, testbench and env
#35 opened Nov 28, 2021 by ChrisShakkour RTL0.5 - CSR
@ChrisShakkour
1
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