This project is a 4 - way traffic light controller modelled around a real world traffic intersection.

Key concepts involved :- a) Finite State Machine - working and design priniciples b) Debugging and testing on an FPGA platform : Cyclone IV E , DE2-115F29C7 board by Intel Altera. c) ModelSim testbench and familiarity with Quartus Prime version 20.11

This project will help you learn a simple time based FSM's working priniciple. System Verilog best practices and state machine concepts are the focus of this project , it involves 7 segment LEDs on the board as a traffic light indicator.

The lights are RED -> AMBER -> GREEN, from bottom to top respectively (only horizontally oriented segments).

Credits : CM341 University of Saskatchewan, Prof. Eric Salt and Prof.Brian Berscheid.