diff --git a/boards/nxp/frdm_mcxe31b/frdm_mcxe31b.dts b/boards/nxp/frdm_mcxe31b/frdm_mcxe31b.dts index ad17f368bb10c..8066e2de4b597 100644 --- a/boards/nxp/frdm_mcxe31b/frdm_mcxe31b.dts +++ b/boards/nxp/frdm_mcxe31b/frdm_mcxe31b.dts @@ -159,6 +159,10 @@ overdrive = <12>; }; +&pit_0 { + status = "okay"; +}; + &pll { status = "okay"; workmode = "Integer"; diff --git a/drivers/clock_control/clock_control_nxp_mc_cgm.c b/drivers/clock_control/clock_control_nxp_mc_cgm.c index 6a0ffdae8972a..20546807df609 100644 --- a/drivers/clock_control/clock_control_nxp_mc_cgm.c +++ b/drivers/clock_control/clock_control_nxp_mc_cgm.c @@ -42,8 +42,10 @@ const clock_pcfs_config_t pcfs_config = {.maxAllowableIDDchange = NXP_PLL_MAXIDO static int mc_cgm_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system) { + uint32_t clock_name = (uint32_t)sub_system; + + switch (clock_name) { #if defined(CONFIG_CAN_MCUX_FLEXCAN) - switch ((uint32_t)sub_system) { case MCUX_FLEXCAN0_CLK: CLOCK_EnableClock(kCLOCK_Flexcan0); break; @@ -62,13 +64,9 @@ static int mc_cgm_clock_control_on(const struct device *dev, clock_control_subsy case MCUX_FLEXCAN5_CLK: CLOCK_EnableClock(kCLOCK_Flexcan5); break; - default: - break; - } #endif /* defined(CONFIG_CAN_MCUX_MCAN) */ #if defined(CONFIG_UART_MCUX_LPUART) - switch ((uint32_t)sub_system) { case MCUX_LPUART0_CLK: CLOCK_EnableClock(kCLOCK_Lpuart0); break; @@ -117,13 +115,9 @@ static int mc_cgm_clock_control_on(const struct device *dev, clock_control_subsy case MCUX_LPUART15_CLK: CLOCK_EnableClock(kCLOCK_Lpuart15); break; - default: - break; - } #endif /* defined(CONFIG_UART_MCUX_LPUART) */ #if defined(CONFIG_SPI_NXP_LPSPI) - switch ((uint32_t)sub_system) { case MCUX_LPSPI0_CLK: CLOCK_EnableClock(kCLOCK_Lpspi0); break; @@ -142,36 +136,40 @@ static int mc_cgm_clock_control_on(const struct device *dev, clock_control_subsy case MCUX_LPSPI5_CLK: CLOCK_EnableClock(kCLOCK_Lpspi5); break; - default: - break; - } #endif /* defined(CONFIG_SPI_NXP_LPSPI) */ #if defined(CONFIG_I2C_MCUX_LPI2C) - switch ((uint32_t)sub_system) { case MCUX_LPI2C0_CLK: CLOCK_EnableClock(kCLOCK_Lpi2c0); break; case MCUX_LPI2C1_CLK: CLOCK_EnableClock(kCLOCK_Lpi2c1); break; - default: - break; - } #endif /* defined(CONFIG_I2C_MCUX_LPI2C) */ #if defined(CONFIG_COUNTER_MCUX_STM) - switch ((uint32_t)sub_system) { case MCUX_STM0_CLK: CLOCK_EnableClock(kCLOCK_Stm0); break; case MCUX_STM1_CLK: CLOCK_EnableClock(kCLOCK_Stm1); break; - default: +#endif /* defined(CONFIG_COUNTER_MCUX_STM) */ + +#ifdef CONFIG_COUNTER_NXP_PIT + case MCUX_PIT0_CLK: + CLOCK_EnableClock(kCLOCK_Pit0Clk); break; + case MCUX_PIT1_CLK: + CLOCK_EnableClock(kCLOCK_Pit1Clk); + break; + case MCUX_PIT2_CLK: + CLOCK_EnableClock(kCLOCK_Pit2Clk); + break; +#endif + default: + return -ENOTSUP; } -#endif /* defined(CONFIG_COUNTER_MCUX_STM) */ return 0; } @@ -262,6 +260,17 @@ static int mc_cgm_get_subsys_rate(const struct device *dev, clock_control_subsys *rate = CLOCK_GetStmClkFreq(1); break; #endif /* defined(CONFIG_COUNTER_MCUX_STM) */ + +#if defined(CONFIG_COUNTER_NXP_PIT) + case MCUX_PIT0_CLK: + case MCUX_PIT1_CLK: + case MCUX_PIT2_CLK: + *rate = CLOCK_GetAipsSlowClkFreq(); + break; +#endif /* defined(CONFIG_COUNTER_NXP_PIT) */ + + default: + return -ENOTSUP; } return 0; } diff --git a/dts/arm/nxp/nxp_mcxe31x_common.dtsi b/dts/arm/nxp/nxp_mcxe31x_common.dtsi index 5581bf87998b5..1f062ab7584df 100644 --- a/dts/arm/nxp/nxp_mcxe31x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxe31x_common.dtsi @@ -709,6 +709,32 @@ clocks = <&mc_cgm MCUX_PIT0_CLK>; max-load-value = <0xffffffff>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + pit_0_channel0: pit_0_channel@0 { + compatible = "nxp,pit-channel"; + reg = <0>; + status = "disabled"; + }; + + pit_0_channel1: pit_0_channel@1 { + compatible = "nxp,pit-channel"; + reg = <1>; + status = "disabled"; + }; + + pit_0_channel2: pit_0_channel@2 { + compatible = "nxp,pit-channel"; + reg = <2>; + status = "disabled"; + }; + + pit_0_channel3: pit_0_channel@3 { + compatible = "nxp,pit-channel"; + reg = <3>; + status = "disabled"; + }; }; pit_1: pit@b4000 { @@ -718,6 +744,32 @@ clocks = <&mc_cgm MCUX_PIT1_CLK>; max-load-value = <0xffffffff>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + pit_1_channel0: pit_1_channel@0 { + compatible = "nxp,pit-channel"; + reg = <0>; + status = "disabled"; + }; + + pit_1_channel1: pit_1_channel@1 { + compatible = "nxp,pit-channel"; + reg = <1>; + status = "disabled"; + }; + + pit_1_channel2: pit_1_channel@2 { + compatible = "nxp,pit-channel"; + reg = <2>; + status = "disabled"; + }; + + pit_1_channel3: pit_1_channel@3 { + compatible = "nxp,pit-channel"; + reg = <3>; + status = "disabled"; + }; }; pit_2: pit@2fc000 { @@ -727,6 +779,32 @@ clocks = <&mc_cgm MCUX_PIT2_CLK>; max-load-value = <0xffffffff>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + pit_2_channel0: pit_2_channel@0 { + compatible = "nxp,pit-channel"; + reg = <0>; + status = "disabled"; + }; + + pit_2_channel1: pit_2_channel@1 { + compatible = "nxp,pit-channel"; + reg = <1>; + status = "disabled"; + }; + + pit_2_channel2: pit_2_channel@2 { + compatible = "nxp,pit-channel"; + reg = <2>; + status = "disabled"; + }; + + pit_2_channel3: pit_2_channel@3 { + compatible = "nxp,pit-channel"; + reg = <3>; + status = "disabled"; + }; }; pll: plldig@402e0000 { diff --git a/include/zephyr/dt-bindings/clock/nxp_mc_cgm.h b/include/zephyr/dt-bindings/clock/nxp_mc_cgm.h index e47237fa73722..87af8cc275867 100644 --- a/include/zephyr/dt-bindings/clock/nxp_mc_cgm.h +++ b/include/zephyr/dt-bindings/clock/nxp_mc_cgm.h @@ -24,7 +24,8 @@ /* Note- clock identifiers in this file must be unique, * as the driver uses them in a switch case */ - +#define MCUX_MC_CGM_PERIPHERAL_MASK 0xFF00UL +#define MCUX_MC_CGM_INSTANCE_MASK 0xFFUL #define MCUX_MC_CGM_CLK_ID(high, low) ((high << 8) | (low)) /* These IDs are used within SOC macros, and thus cannot be defined diff --git a/tests/drivers/counter/counter_basic_api/boards/frdm_mcxe31b.overlay b/tests/drivers/counter/counter_basic_api/boards/frdm_mcxe31b.overlay new file mode 100644 index 0000000000000..693d95f77fc9e --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/frdm_mcxe31b.overlay @@ -0,0 +1,21 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pit_0_channel0 { + status = "okay"; +}; + +&pit_0_channel1 { + status = "okay"; +}; + +&pit_0_channel2 { + status = "okay"; +}; + +&pit_0_channel3 { + status = "okay"; +};