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| 1 | +# Copyright (c) 2022-2025 Macronix International Co., Ltd. |
| 2 | +# SPDX-License-Identifier: Apache-2.0 |
| 3 | + |
| 4 | +menuconfig SPI_NAND |
| 5 | + bool "SPI NAND Flash" |
| 6 | + default y |
| 7 | + depends on DT_HAS_JEDEC_SPI_NAND_ENABLED |
| 8 | + select FLASH_HAS_DRIVER_ENABLED |
| 9 | + select FLASH_HAS_EXPLICIT_ERASE |
| 10 | + select FLASH_HAS_PAGE_LAYOUT |
| 11 | + select SPI |
| 12 | + |
| 13 | +if SPI_NAND |
| 14 | + |
| 15 | +config SPI_NAND_INIT_PRIORITY |
| 16 | + int "SPI NAND init priority" |
| 17 | + default 80 |
| 18 | + help |
| 19 | + Device driver initialization priority. |
| 20 | + Device is connected to SPI bus, it has to |
| 21 | + be initialized after SPI driver. |
| 22 | + |
| 23 | +config SPI_NAND_SOFTWARE_ECC |
| 24 | + bool "Software ECC for SPI NAND flash" |
| 25 | + help |
| 26 | + Enable this option to use software-based ECC (Error Correction Code) |
| 27 | + when accessing SPI NAND flash devices. This is useful for platforms |
| 28 | + that do not support hardware ECC, or when additional software control |
| 29 | + over ECC handling is required. |
| 30 | + |
| 31 | +config SPI_NAND_ECC_STEP_SIZE |
| 32 | + int "ECC step size (bytes)" |
| 33 | + default 512 |
| 34 | + depends on SPI_NAND_SOFTWARE_ECC |
| 35 | + help |
| 36 | + Specifies the ECC (Error Correction Code) step size in bytes for SPI NAND |
| 37 | + flash operations. This value determines how many bytes of data are protected |
| 38 | + by one ECC block. |
| 39 | + |
| 40 | +config SPI_NAND_BCH_HEAP_SIZE |
| 41 | + int "BCH heap size (bytes)" |
| 42 | + default 51200 |
| 43 | + help |
| 44 | + Specify the heap size (in bytes) reserved for BCH (Bose-Chaudhuri-Hocquenghem) |
| 45 | + error correction in SPI NAND flash operations. |
| 46 | + |
| 47 | +endif # SPI_NAND |
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