diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 633294b6..c55efdfb 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -58,6 +58,7 @@ on: - xtensa-nxp_imx_adsp_zephyr-elf - xtensa-nxp_imx8m_adsp_zephyr-elf - xtensa-sample_controller_zephyr-elf + - xtensa-mtk_mvpu6_0226_zephyr-elf debug: description: 'Debug' type: choice @@ -166,6 +167,7 @@ jobs: xtensa-nxp_imx_adsp_zephyr-elf) build_target_xtensa_nxp_imx_adsp_zephyr_elf="y";; xtensa-nxp_imx8m_adsp_zephyr-elf) build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y";; xtensa-sample_controller_zephyr-elf) build_target_xtensa_sample_controller_zephyr_elf="y";; + xtensa-mtk_mvpu6_0226_zephyr-elf) build_target_xtensa_mtk_mvpu6_0226_zephyr_elf="y";; esac MATRIX_DEBUG="${{ github.event.inputs.debug }}" @@ -202,6 +204,7 @@ jobs: build_target_xtensa_nxp_imx_adsp_zephyr_elf="y" build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y" build_target_xtensa_sample_controller_zephyr_elf="y" + build_target_xtensa_mtk_mvpu6_0226_zephyr_elf="y" fi # Build 'linux_x86_64' by default if no host is selected @@ -278,6 +281,7 @@ jobs: [ "${build_target_xtensa_nxp_imx_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx_adsp_zephyr-elf",' [ "${build_target_xtensa_nxp_imx8m_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx8m_adsp_zephyr-elf",' [ "${build_target_xtensa_sample_controller_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-sample_controller_zephyr-elf",' + [ "${build_target_xtensa_mtk_mvpu6_0226_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-mtk_mvpu6_0226_zephyr-elf",' MATRIX_TARGETS+=']' # Generate test environment list @@ -1540,6 +1544,9 @@ jobs: xtensa-sample_controller_zephyr-elf) PLATFORM_ARGS+="-p qemu_xtensa " ;; + xtensa-mtk_mvpu6_0226_zephyr-elf) + PLATFORM_ARGS+="-p mtk_mvpu6_0226 " + ;; esac done diff --git a/configs/xtensa-mtk_mvpu6_0226_zephyr-elf.config b/configs/xtensa-mtk_mvpu6_0226_zephyr-elf.config new file mode 100644 index 00000000..deae041b --- /dev/null +++ b/configs/xtensa-mtk_mvpu6_0226_zephyr-elf.config @@ -0,0 +1,9 @@ +CT_CONFIG_VERSION="3" +CT_EXPERIMENTAL=y +CT_OVERLAY_LOCATION="overlays" +CT_OVERLAY_NAME="mtk_mvpu6_0226" +CT_ARCH_XTENSA=y +CT_XTENSA_CUSTOM=y +CT_TARGET_VENDOR="mtk_mvpu6_0026_zephyr" +CT_TARGET_CFLAGS="-ftls-model=local-exec" +CT_CC_GCC_CONFIG_TLS=n diff --git a/overlays/xtensa_mtk_mvpu6_0226/binutils/bfd/xtensa-modules.c b/overlays/xtensa_mtk_mvpu6_0226/binutils/bfd/xtensa-modules.c new file mode 100644 index 00000000..4ec19e71 --- /dev/null +++ b/overlays/xtensa_mtk_mvpu6_0226/binutils/bfd/xtensa-modules.c @@ -0,0 +1,211607 @@ +/* Xtensa configuration-specific ISA information. + + Copyright (c) 2003-2018 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "ansidecl.h" +#include +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "BR", 4, 0 }, + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "CONFIGID0", 176, 0 }, + { "CONFIGID1", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "GSERR", 116, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "MEMCTL", 97, 0 }, + { "SAR", 3, 0 }, + { "PS", 230, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "CACHEADRDIS", 98, 0 }, + { "MPUENB", 90, 0 }, + { "CPENABLE", 224, 0 }, + { "ATOMCTL", 99, 0 }, + { "THREADPTR", 231, 1 }, + { "APB_PIPE", 0, 1 } +}; + +#define NUM_SYSREGS 49 +#define MAX_SPECIAL_REG 241 +#define MAX_USER_REG 231 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "DDR", 32, 0 }, + { "INTERRUPT", 25, 0 }, + { "CCOUNT", 32, 0 }, + { "GSERR", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EPS2", 15, 0 }, + { "EPS3", 15, 0 }, + { "EPS4", 15, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSRING", 2, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 3, 0 }, + { "WindowStart", 8, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "MEMCTL", 24, 0 }, + { "SAR", 6, 0 }, + { "THREADPTR", 32, 0 }, + { "MPUNUMENTRIES", 6, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 25, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKC_SG0", 2, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKENABLE", 1, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "CACHEADRDIS", 8, 0 }, + { "MPUENB", 32, 0 }, + { "CPENABLE", 3, 0 }, + { "ATOMCTL", 9, 0 }, + { "ERI_RAW_INTERLOCK", 1, 0 }, + { "ERACCESS", 16, 0 }, + { "APB_PIPE", 1, 0 } +}; + +#define NUM_STATES 57 + +enum xtensa_state_id { + STATE_LCOUNT, + STATE_PC, + STATE_ICOUNT, + STATE_DDR, + STATE_INTERRUPT, + STATE_CCOUNT, + STATE_GSERR, + STATE_XTSYNC, + STATE_VECBASE, + STATE_EPC1, + STATE_EPC2, + STATE_EPC3, + STATE_EPC4, + STATE_EXCSAVE1, + STATE_EXCSAVE2, + STATE_EXCSAVE3, + STATE_EXCSAVE4, + STATE_EPS2, + STATE_EPS3, + STATE_EPS4, + STATE_EXCCAUSE, + STATE_PSINTLEVEL, + STATE_PSUM, + STATE_PSWOE, + STATE_PSRING, + STATE_PSEXCM, + STATE_DEPC, + STATE_EXCVADDR, + STATE_WindowBase, + STATE_WindowStart, + STATE_PSCALLINC, + STATE_PSOWB, + STATE_LBEG, + STATE_LEND, + STATE_MEMCTL, + STATE_SAR, + STATE_THREADPTR, + STATE_MPUNUMENTRIES, + STATE_InOCDMode, + STATE_INTENABLE, + STATE_DBREAKA0, + STATE_DBREAKC0, + STATE_DBREAKC_SG0, + STATE_IBREAKA0, + STATE_IBREAKENABLE, + STATE_ICOUNTLEVEL, + STATE_DEBUGCAUSE, + STATE_DBNUM, + STATE_CCOMPARE0, + STATE_CCOMPARE1, + STATE_CACHEADRDIS, + STATE_MPUENB, + STATE_CPENABLE, + STATE_ATOMCTL, + STATE_ERI_RAW_INTERLOCK, + STATE_ERACCESS, + STATE_APB_PIPE +}; + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_inst_23_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_fld_inst_23_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_inst_3_0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_inst_3_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_inst_23_16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fld_inst_23_16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_inst_11_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_inst_11_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_inst_23_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_inst_23_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s0_ldst_33_19_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 13) | (insn[0] >> 19); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_19_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfff80000) | (tie_t << 19); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 13); +} + +static unsigned +Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s0_ldst_33_20_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_20_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 12); +} + +static unsigned +Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 14); +} + +static unsigned +Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 16); +} + +static unsigned +Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_f0_s0_ldst_7_6_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_7_6_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 17); +} + +static unsigned +Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 19) | (insn[0] >> 13); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffffe000) | (tie_t << 13); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 19); +} + +static unsigned +Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 15) | (insn[0] >> 17); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfffe0000) | (tie_t << 17); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 15); +} + +static unsigned +Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 18); +} + +static unsigned +Field_fld_f0_s0_ldst_7_7_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_7_7_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f0_s0_ldst_15_15_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_15_15_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f0_s0_ldst_12_8_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_12_8_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s0_ldst_12_4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_12_4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s0_ldst_12_2_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_12_2_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f0_s0_ldst_12_0_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_12_0_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 23) | (insn[0] >> 9); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffe00) | (tie_t << 9); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 23); +} + +static unsigned +Field_fld_f0_s0_ldst_13_9_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_13_9_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_f0_s0_ldst_7_5_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_7_5_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f0_s0_ldst_33_11_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 21) | (insn[0] >> 11); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_11_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xfffff800) | (tie_t << 11); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 21); +} + +static unsigned +Field_fld_f0_s0_ldst_12_11_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_12_11_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_f0_s0_ldst_8_0_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_8_0_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 20); +} + +static unsigned +Field_fld_f0_s0_ldst_3_0_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_3_0_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s0_ldst_8_4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_8_4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s0_ldst_8_8_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_8_8_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 5) | (insn[0] >> 27); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 5); +} + +static unsigned +Field_fld_f0_s0_ldst_11_4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_11_4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s0_ldst_11_9_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_11_9_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 7) >> 23); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_f0_s1_ld_7_6_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_7_6_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_f0_s1_ld_24_17_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 7) >> 24); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_24_17_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 7) >> 20); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 7) >> 25); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f0_s1_ld_15_10_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 16) >> 26); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_15_10_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc00) | (tie_t << 10); +} + +static unsigned +Field_fld_f0_s1_ld_15_8_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_15_8_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s1_ld_15_4_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_15_4_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s1_ld_15_2_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 16) >> 18); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_15_2_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f0_s1_ld_7_7_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_7_7_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 7) >> 19); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f0_s1_ld_24_11_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 7) >> 18); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_24_11_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x1fff800) | (tie_t << 11); +} + +static unsigned +Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f0_s1_ld_7_5_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_7_5_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f0_s1_ld_15_15_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_15_15_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f0_s1_ld_15_14_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_15_14_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f0_s1_ld_24_0_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 7) >> 7); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_24_0_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s1_ld_24_14_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 7) >> 21); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_24_14_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f0_s1_ld_24_8_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 7) >> 15); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_24_8_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 5) >> 19); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x7ffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 5) >> 26); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e00000) | (tie_t << 21); +} + +static unsigned +Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 13) >> 25); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f000) | (tie_t << 12); +} + +static unsigned +Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f0_s2_mul_13_12_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_13_12_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_f0_s2_mul_11_8_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_11_8_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s2_mul_4_4_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_4_4_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s2_mul_18_9_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 13) >> 22); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_18_9_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f0_s2_mul_7_4_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_7_4_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s2_mul_26_2_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_26_2_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f0_s2_mul_1_0_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_1_0_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s2_mul_26_13_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 5) >> 18); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_26_13_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f0_s2_mul_26_20_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_26_20_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f0_s3_alu_33_26_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 6) | (insn[0] >> 26); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_26_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 6); +} + +static unsigned +Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s3_alu_33_27_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 5) | (insn[0] >> 27); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_27_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 5); +} + +static unsigned +Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 12); +} + +static unsigned +Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 4) | (insn[0] >> 28); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xf0000000) | (tie_t << 28); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 4); +} + +static unsigned +Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 7) >> 20); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f0_s3_alu_9_7_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_9_7_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 19) | (insn[0] >> 13); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffffe000) | (tie_t << 13); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 19); +} + +static unsigned +Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_f0_s3_alu_7_3_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_7_3_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f0_s3_alu_3_3_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_3_3_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_f0_s3_alu_3_2_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_3_2_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f0_s3_alu_14_11_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_14_11_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); +} + +static unsigned +Field_fld_f0_s3_alu_33_25_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_25_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 7); +} + +static unsigned +Field_fld_f0_s3_alu_7_7_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_7_7_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f0_s3_alu_14_14_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_14_14_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_f0_s3_alu_33_9_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 23) | (insn[0] >> 9); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_9_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffe00) | (tie_t << 9); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 23); +} + +static unsigned +Field_fld_f0_s3_alu_8_8_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_8_8_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s3_alu_33_18_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_18_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 14); +} + +static unsigned +Field_fld_f0_s3_alu_8_0_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_8_0_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_19_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 1) >> 20); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_19_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_20_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 1) >> 21); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_20_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 1) >> 19); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x7ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 1) >> 17); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f1_s0_ldstalu_7_5_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_7_5_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f1_s0_ldstalu_12_12_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_12_12_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 1) >> 16); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x7fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 1) >> 14); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x7fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 1) >> 18); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f1_s0_ldstalu_15_15_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_15_15_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f1_s0_ldstalu_12_8_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_12_8_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f1_s0_ldstalu_12_4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_12_4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f1_s0_ldstalu_12_2_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_12_2_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f1_s0_ldstalu_12_0_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_12_0_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 1) >> 10); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x7ffffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f1_s0_ldstalu_7_7_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_7_7_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 1) >> 13); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x7ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f1_s0_ldstalu_14_12_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_14_12_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_14_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 1) >> 15); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_14_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x7fffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f1_s0_ldstalu_14_14_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_14_14_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_6_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 1) >> 7); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_6_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f1_s0_ldstalu_5_0_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_5_0_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s0_ldstalu_3_0_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_3_0_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s0_ldstalu_5_4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_5_4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_8_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 1) >> 9); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_8_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 5) >> 21); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f1_s1_ld_12_10_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_12_10_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 5) >> 23); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 5) >> 18); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f1_s1_ld_12_9_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 19) >> 28); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_12_9_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e00) | (tie_t << 9); +} + +static unsigned +Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f1_s1_ld_3_0_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_3_0_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s1_ld_15_10_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 16) >> 26); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_15_10_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc00) | (tie_t << 10); +} + +static unsigned +Field_fld_f1_s1_ld_15_8_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_15_8_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f1_s1_ld_15_4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_15_4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f1_s1_ld_15_2_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 16) >> 18); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_15_2_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f1_s1_ld_7_7_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_7_7_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f1_s1_ld_7_6_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_7_6_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f1_s1_ld_26_11_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 5) >> 16); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_26_11_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x7fff800) | (tie_t << 11); +} + +static unsigned +Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f1_s1_ld_12_12_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_12_12_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_f1_s1_ld_7_5_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_7_5_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f1_s1_ld_15_14_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_15_14_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f1_s1_ld_26_2_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_26_2_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f1_s1_ld_1_0_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_1_0_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 3) >> 18); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x1fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 3) >> 19); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 3) >> 21); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f1_s2_mul_13_5_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 18) >> 23); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_13_5_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f1_s2_mul_3_2_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_3_2_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s2_mul_4_4_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_4_4_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_f1_s2_mul_13_2_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 18) >> 20); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_13_2_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f1_s2_mul_28_20_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 3) >> 23); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_28_20_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f1_s2_mul_9_6_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_9_6_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 3) >> 15); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f1_s2_mul_28_4_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 3) >> 7); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_28_4_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 1) >> 24); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f800000) | (tie_t << 23); +} + +static unsigned +Field_fld_f1_s3_alu_9_2_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_9_2_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); +} + +static unsigned +Field_fld_f1_s3_alu_9_3_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_9_3_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); +} + +static unsigned +Field_fld_f1_s3_alu_9_1_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 22) >> 23); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_9_1_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe) | (tie_t << 1); +} + +static unsigned +Field_fld_f1_s3_alu_19_7_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_19_7_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7); +} + +static unsigned +Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f1_s3_alu_30_8_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 1) >> 9); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_30_8_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f1_s3_alu_19_14_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_19_14_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 1) >> 21); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_f1_s3_alu_14_14_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_14_14_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f1_s3_alu_14_10_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_14_10_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 1) >> 16); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x7fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s3_alu_3_2_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_3_2_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f1_s3_alu_14_13_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_14_13_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_f1_s3_alu_9_7_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_9_7_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_f1_s3_alu_30_22_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 1) >> 23); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_30_22_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_f1_s3_alu_3_3_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_3_3_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_f1_s3_alu_30_17_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 1) >> 18); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_30_17_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f1_s3_alu_30_6_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 1) >> 7); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_30_6_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f1_s3_alu_5_0_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_5_0_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 3) >> 19); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f2_s0_ldst_12_10_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_12_10_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 3) >> 20); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 3) >> 16); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x1fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 3) >> 18); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x1fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 3) >> 21); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f2_s0_ldst_15_15_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_15_15_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f2_s0_ldst_12_4_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_12_4_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f2_s0_ldst_12_2_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_12_2_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f2_s0_ldst_12_0_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_12_0_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s0_ldst_28_14_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 3) >> 17); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_14_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f2_s0_ldst_7_2_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_7_2_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_f2_s0_ldst_28_4_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 3) >> 7); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_4_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 3) >> 15); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f2_s0_ldst_28_20_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 3) >> 23); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_20_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f2_s0_ldst_28_11_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 3) >> 14); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_11_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x1ffff800) | (tie_t << 11); +} + +static unsigned +Field_fld_f2_s0_ldst_28_8_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 3) >> 11); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_8_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x1fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 5) >> 21); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f2_s1_ld_12_10_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_12_10_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 5) >> 23); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 5) >> 18); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f2_s1_ld_12_9_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 19) >> 28); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_12_9_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e00) | (tie_t << 9); +} + +static unsigned +Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f2_s1_ld_3_0_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_3_0_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s1_ld_15_10_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 16) >> 26); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_15_10_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc00) | (tie_t << 10); +} + +static unsigned +Field_fld_f2_s1_ld_15_8_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_15_8_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f2_s1_ld_15_4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_15_4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f2_s1_ld_15_2_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 16) >> 18); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_15_2_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f2_s1_ld_7_7_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_7_7_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f2_s1_ld_7_6_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_7_6_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f2_s1_ld_26_11_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 5) >> 16); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_26_11_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x7fff800) | (tie_t << 11); +} + +static unsigned +Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f2_s1_ld_15_14_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_15_14_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f2_s1_ld_26_2_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_26_2_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f2_s1_ld_1_0_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_1_0_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 1) >> 21); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f2_s2_mul_14_11_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_14_11_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); +} + +static unsigned +Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 1) >> 20); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 1) >> 16); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x7fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 1) >> 22); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe00000) | (tie_t << 21); +} + +static unsigned +Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s2_mul_19_10_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_19_10_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_f2_s2_mul_30_18_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 1) >> 19); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_30_18_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x7ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f2_s2_mul_14_5_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_14_5_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f2_s2_mul_19_7_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_19_7_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7); +} + +static unsigned +Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 1) >> 13); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x7ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f2_s2_mul_30_6_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 1) >> 7); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_30_6_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f2_s2_mul_5_0_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_5_0_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 1) >> 24); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f800000) | (tie_t << 23); +} + +static unsigned +Field_fld_f2_s3_alu_9_2_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_9_2_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); +} + +static unsigned +Field_fld_f2_s3_alu_9_3_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_9_3_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); +} + +static unsigned +Field_fld_f2_s3_alu_9_1_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 22) >> 23); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_9_1_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe) | (tie_t << 1); +} + +static unsigned +Field_fld_f2_s3_alu_19_7_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_19_7_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7); +} + +static unsigned +Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f2_s3_alu_30_8_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 1) >> 9); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_30_8_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f2_s3_alu_19_14_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_19_14_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 1) >> 21); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_f2_s3_alu_14_14_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_14_14_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f2_s3_alu_14_10_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_14_10_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 1) >> 16); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x7fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s3_alu_3_2_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_3_2_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f2_s3_alu_14_13_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_14_13_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_f2_s3_alu_9_7_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_9_7_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_f2_s3_alu_9_9_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_9_9_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_f2_s3_alu_30_22_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 1) >> 23); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_30_22_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_f2_s3_alu_3_3_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_3_3_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_f2_s3_alu_30_18_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 1) >> 19); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_30_18_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x7ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f2_s3_alu_30_6_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 1) >> 7); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_30_6_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f2_s3_alu_5_0_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_5_0_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s0_ldst_25_19_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 6) >> 25); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_19_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f80000) | (tie_t << 19); +} + +static unsigned +Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f3_s0_ldst_25_20_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 6) >> 26); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_20_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 6) >> 24); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 6) >> 22); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f3_s0_ldst_7_5_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_7_5_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f3_s0_ldst_12_12_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_12_12_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 6) >> 21); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x3ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 6) >> 19); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 6) >> 23); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 6) >> 20); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f3_s0_ldst_7_7_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_7_7_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f3_s0_ldst_15_15_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_15_15_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f3_s0_ldst_12_8_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_12_8_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f3_s0_ldst_12_4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_12_4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f3_s0_ldst_12_11_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_12_11_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_f3_s0_ldst_8_0_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_8_0_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s0_ldst_12_0_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_12_0_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 6) >> 15); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f3_s0_ldst_13_9_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_13_9_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_f3_s0_ldst_25_11_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 6) >> 17); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_11_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x3fff800) | (tie_t << 11); +} + +static unsigned +Field_fld_f3_s0_ldst_25_1_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 6) >> 7); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_1_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe) | (tie_t << 1); +} + +static unsigned +Field_fld_f3_s0_ldst_0_0_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_0_0_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 6) >> 18); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f3_s0_ldst_3_0_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_3_0_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s0_ldst_25_4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 6) >> 10); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f3_s0_ldst_25_8_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_8_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 10) >> 21); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x3ff800) | (tie_t << 11); +} + +static unsigned +Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 10) >> 18); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_f3_s1_ld_21_10_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_10_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 10) >> 22); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f3_s1_ld_21_9_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 10) >> 19); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_9_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 10) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f3_s1_ld_3_0_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_3_0_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 10) >> 25); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f3_s1_ld_12_11_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_12_11_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_f3_s1_ld_12_8_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_12_8_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f3_s1_ld_12_4_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_12_4_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f3_s1_ld_12_2_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_12_2_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f3_s1_ld_7_7_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_7_7_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f3_s1_ld_7_0_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_7_0_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f3_s1_ld_21_16_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 10) >> 26); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_16_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f3_s1_ld_21_0_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 10) >> 10); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_0_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 10) >> 26); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s2_mul_11_8_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_11_8_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s2_mul_13_12_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_13_12_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_f3_s2_mul_7_5_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_7_5_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f3_s2_mul_13_7_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 18) >> 25); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_13_7_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f80) | (tie_t << 7); +} + +static unsigned +Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 10) >> 22); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f3_s2_mul_21_0_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 10) >> 10); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_21_0_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s2_mul_7_4_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_7_4_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f3_s2_mul_21_13_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_21_13_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f3_s2_mul_21_15_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 10) >> 25); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_21_15_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f3_s3_alu_28_20_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 3) >> 23); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_20_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_f3_s3_alu_28_21_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 3) >> 24); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_21_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe00000) | (tie_t << 21); +} + +static unsigned +Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 3) >> 22); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 3) >> 25); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_f3_s3_alu_18_7_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_18_7_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); +} + +static unsigned +Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 13) >> 16); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x7fff8) | (tie_t << 3); +} + +static unsigned +Field_fld_f3_s3_alu_18_8_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 13) >> 21); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_18_8_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s3_alu_28_9_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 3) >> 12); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_9_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0x1ffffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 3) >> 17); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 3) >> 16); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x1fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f3_s3_alu_18_14_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_18_14_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_f3_s3_alu_7_6_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_7_6_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f3_s3_alu_18_12_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 13) >> 25); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_18_12_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f000) | (tie_t << 12); +} + +static unsigned +Field_fld_f3_s3_alu_28_12_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 3) >> 15); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_12_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f3_s3_alu_3_2_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_3_2_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f3_s3_alu_28_25_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 3) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_25_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_f3_s3_alu_28_8_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 3) >> 11); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_8_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x1fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f3_s3_alu_18_13_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_18_13_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_fld_f3_s3_alu_28_4_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 3) >> 7); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_4_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 8) >> 23); + return tie_t; +} + +static void +Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + return tie_t; +} + +static void +Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f3_s4_alu_23_20_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s4_alu_23_20_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f3_s4_alu_9_6_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s4_alu_9_6_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_fld_f3_s4_alu_23_0_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_f3_s4_alu_23_0_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s4_alu_23_16_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fld_f3_s4_alu_23_16_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 0) >> 15); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 0) >> 13); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xffffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 0) >> 17); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 0) >> 18); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 0) >> 16); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f4_s0_ld_15_15_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_15_15_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f4_s0_ld_12_8_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_12_8_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f4_s0_ld_12_4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_12_4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f4_s0_ld_12_2_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_12_2_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f4_s0_ld_12_0_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_12_0_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f4_s0_ld_31_7_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 0) >> 7); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_7_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff80) | (tie_t << 7); +} + +static unsigned +Field_fld_f4_s0_ld_6_0_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_6_0_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 0) >> 12); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f4_s0_ld_31_20_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 0) >> 20); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_20_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f4_s0_ld_3_0_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_3_0_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s0_ld_6_4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_6_4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_f4_s0_ld_31_9_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 0) >> 9); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_9_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xfffffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f4_s0_ld_31_8_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 0) >> 8); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_8_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 0) >> 27); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); +} + +static unsigned +Field_fld_f4_s0_ld_11_4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_11_4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f4_s0_ld_11_9_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_11_9_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 8) >> 19); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff800) | (tie_t << 11); +} + +static unsigned +Field_fld_f4_s1_ld_4_0_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_4_0_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_f4_s1_ld_23_10_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 8) >> 18); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_10_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 8) >> 21); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f4_s1_ld_23_9_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_9_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 8) >> 23); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f4_s1_ld_12_10_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_12_10_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f4_s1_ld_12_8_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_12_8_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f4_s1_ld_12_4_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_12_4_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f4_s1_ld_12_2_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_12_2_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f4_s1_ld_7_7_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_7_7_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f4_s1_ld_7_6_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_7_6_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f4_s1_ld_7_0_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_7_0_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f4_s1_ld_23_16_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_16_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f4_s1_ld_23_0_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_0_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 6) | (insn[0] >> 26); + return tie_t; +} + +static void +Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 6); +} + +static unsigned +Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s2_mul_32_8_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 24) | (insn[0] >> 8); + return tie_t; +} + +static void +Field_fld_f4_s2_mul_32_8_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff00) | (tie_t << 8); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 24); +} + +static unsigned +Field_fld_f4_s2_mul_7_0_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_f4_s2_mul_7_0_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 0) >> 26); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); +} + +static unsigned +Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f4_s3_alu_24_21_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 7) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_24_21_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e00000) | (tie_t << 21); +} + +static unsigned +Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 0) >> 20); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 0) >> 23); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff800000) | (tie_t << 23); +} + +static unsigned +Field_fld_f4_s3_alu_19_6_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 12) >> 18); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_19_6_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_f4_s3_alu_19_8_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_19_8_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s3_alu_31_19_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 0) >> 19); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_31_19_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_f4_s3_alu_14_6_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 17) >> 23); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_14_6_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f4_s3_alu_3_3_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_3_3_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 7) >> 19); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); +} + +static unsigned +Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_f4_s3_alu_9_8_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_9_8_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 0) >> 13); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xffffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f4_s3_alu_24_13_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 7) >> 20); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_24_13_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f4_s3_alu_3_2_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_3_2_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 0) >> 25); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_f4_s3_alu_14_14_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_14_14_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_f4_s3_alu_31_28_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 0) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_31_28_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000000) | (tie_t << 28); +} + +static unsigned +Field_fld_f4_s3_alu_24_18_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 7) >> 25); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_24_18_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f4_s3_alu_19_13_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_19_13_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f4_s3_alu_31_8_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 0) >> 8); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_31_8_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f4_s3_alu_31_7_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 0) >> 7); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_31_7_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff80) | (tie_t << 7); +} + +static unsigned +Field_fld_f4_s3_alu_6_0_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_6_0_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 16); +} + +static unsigned +Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 20); +} + +static unsigned +Field_fld_f5_s0_base_36_20_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_f5_s0_base_36_20_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 12); +} + +static unsigned +Field_fld_f5_s0_base_36_17_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 15) | (insn[0] >> 17); + return tie_t; +} + +static void +Field_fld_f5_s0_base_36_17_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffe0000) | (tie_t << 17); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 15); +} + +static unsigned +Field_fld_f5_s0_base_36_18_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_f5_s0_base_36_18_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 14); +} + +static unsigned +Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f5_s0_base_7_4_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f5_s0_base_7_4_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f5_s0_base_11_0_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_fld_f5_s0_base_11_0_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_f5_s0_base_3_1_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_f5_s0_base_3_1_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_f5_s0_base_36_13_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 19) | (insn[0] >> 13); + return tie_t; +} + +static void +Field_fld_f5_s0_base_36_13_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffe000) | (tie_t << 13); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 19); +} + +static unsigned +Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 5) | (insn[0] >> 27); + return tie_t; +} + +static void +Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 5); +} + +static unsigned +Field_fld_f5_s0_base_11_9_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_f5_s0_base_11_9_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 4) >> 20); + return tie_t; +} + +static void +Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 4) >> 16); + return tie_t; +} + +static void +Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f5_s1_base_27_17_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 4) >> 21); + return tie_t; +} + +static void +Field_fld_f5_s1_base_27_17_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f5_s1_base_7_4_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f5_s1_base_7_4_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f5_s1_base_27_3_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 4) >> 7); + return tie_t; +} + +static void +Field_fld_f5_s1_base_27_3_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_f5_s1_base_2_0_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_f5_s1_base_2_0_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_f5_s1_base_3_0_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f5_s1_base_3_0_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f5_s1_base_27_13_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 4) >> 17); + return tie_t; +} + +static void +Field_fld_f5_s1_base_27_13_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f5_s2_base_26_16_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 5) >> 21); + return tie_t; +} + +static void +Field_fld_f5_s2_base_26_16_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f5_s2_base_7_4_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f5_s2_base_7_4_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f5_s2_base_26_2_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_f5_s2_base_26_2_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f5_s2_base_1_0_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_f5_s2_base_1_0_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_f5_s2_base_3_0_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f5_s2_base_3_0_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f5_s2_base_26_13_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 5) >> 18); + return tie_t; +} + +static void +Field_fld_f5_s2_base_26_13_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f5_s2_base_26_8_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 5) >> 13); + return tie_t; +} + +static void +Field_fld_f5_s2_base_26_8_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x7ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f5_s3_base_25_8_Slot_f5_s3_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14); + return tie_t; +} + +static void +Field_fld_f5_s3_base_25_8_Slot_f5_s3_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f5_s3_base_25_16_Slot_f5_s3_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 6) >> 22); + return tie_t; +} + +static void +Field_fld_f5_s3_base_25_16_Slot_f5_s3_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f5_s3_base_25_1_Slot_f5_s3_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 6) >> 7); + return tie_t; +} + +static void +Field_fld_f5_s3_base_25_1_Slot_f5_s3_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe) | (tie_t << 1); +} + +static unsigned +Field_fld_f5_s3_base_0_0_Slot_f5_s3_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_f5_s3_base_0_0_Slot_f5_s3_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s0_ld_23_4_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 8) >> 12); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_23_4_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f11_s0_ld_1_0_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_1_0_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s0_ld_23_16_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_23_16_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f11_s0_ld_23_20_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_23_20_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f11_s0_ld_23_17_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_23_17_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f11_s0_ld_23_0_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_23_0_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s0_ld_3_0_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_3_0_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s0_ld_7_4_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_7_4_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f11_s0_ld_23_13_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 8) >> 21); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_23_13_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f11_s1_alu_12_10_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_12_10_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 19) >> 22); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8) | (tie_t << 3); +} + +static unsigned +Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f11_s1_alu_12_9_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 19) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_12_9_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e00) | (tie_t << 9); +} + +static unsigned +Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f11_s1_alu_15_2_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 16) >> 18); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_15_2_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f11_s1_alu_12_11_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_12_11_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_f11_s1_alu_15_14_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_15_14_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f11_s1_alu_15_13_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_15_13_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f11_s1_alu_22_13_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 9) >> 22); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_22_13_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 9) >> 21); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f11_s1_alu_15_15_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_15_15_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f11_s1_alu_22_0_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 9) >> 9); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_22_0_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s1_alu_3_0_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_3_0_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s1_alu_22_14_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 9) >> 23); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_22_14_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f11_s1_alu_12_12_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_12_12_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 9) >> 23); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s2_mul_11_8_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_11_8_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s2_mul_13_12_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_13_12_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_f11_s2_mul_7_5_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_7_5_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f11_s2_mul_13_7_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 18) >> 25); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_13_7_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f80) | (tie_t << 7); +} + +static unsigned +Field_fld_f11_s2_mul_22_13_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 9) >> 22); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_22_13_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 9) >> 21); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f11_s2_mul_7_4_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_7_4_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f11_s2_mul_22_0_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 9) >> 9); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_22_0_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s2_mul_22_8_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 9) >> 17); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_22_8_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f11_s2_mul_22_15_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 9) >> 24); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_22_15_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 6) >> 21); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x3ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f11_s3_alu_25_16_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 6) >> 22); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_16_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f11_s3_alu_25_14_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 6) >> 20); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_14_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 6) >> 24); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); +} + +static unsigned +Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s3_alu_25_11_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 6) >> 17); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_11_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x3fff800) | (tie_t << 11); +} + +static unsigned +Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s3_alu_14_8_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_14_8_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_f11_s3_alu_9_9_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_9_9_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 6) >> 19); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f11_s3_alu_14_13_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_14_13_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_f11_s3_alu_25_22_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 6) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_22_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00000) | (tie_t << 22); +} + +static unsigned +Field_fld_f11_s3_alu_25_17_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 6) >> 23); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_17_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f11_s3_alu_25_8_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_8_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f11_s3_alu_25_1_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 6) >> 7); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_1_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe) | (tie_t << 1); +} + +static unsigned +Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 7) >> 22); + return tie_t; +} + +static void +Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 7) >> 25); + return tie_t; +} + +static void +Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f11_s4_alu_24_0_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 7) >> 7); + return tie_t; +} + +static void +Field_fld_f11_s4_alu_24_0_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s4_alu_24_16_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 7) >> 23); + return tie_t; +} + +static void +Field_fld_f11_s4_alu_24_16_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 5) >> 21); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_n1_s0_ldst_7_6_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_7_6_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 5) >> 22); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 5) >> 18); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_n1_s0_ldst_7_5_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_7_5_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 5) >> 23); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_n1_s0_ldst_15_15_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_15_15_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_n1_s0_ldst_12_8_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_12_8_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 5) >> 20); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_n1_s0_ldst_12_4_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_12_4_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_n1_s0_ldst_12_2_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_12_2_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_n1_s0_ldst_12_0_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_12_0_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_n1_s0_ldst_7_2_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_7_2_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_n1_s0_ldst_26_2_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_2_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_n1_s0_ldst_1_0_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_1_0_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_n1_s0_ldst_26_20_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_20_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_n1_s0_ldst_3_0_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_3_0_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_n1_s0_ldst_26_4_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 5) >> 9); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_4_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_n1_s0_ldst_26_9_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 5) >> 14); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_9_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x7fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_n1_s0_ldst_26_8_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 5) >> 13); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_8_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x7ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_n1_s1_none_3_0_Slot_n1_s1_none_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_n1_s1_none_3_0_Slot_n1_s1_none_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 6) >> 25); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f80000) | (tie_t << 19); +} + +static unsigned +Field_fld_n1_s2_mul_13_9_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_13_9_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 6) >> 20); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 6) >> 27); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00000) | (tie_t << 21); +} + +static unsigned +Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_n1_s2_mul_18_9_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 13) >> 22); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_18_9_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe00) | (tie_t << 9); +} + +static unsigned +Field_fld_n1_s2_mul_8_4_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_8_4_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_n1_s2_mul_18_6_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 13) >> 19); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_18_6_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x7ffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_n1_s2_mul_8_8_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_8_8_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 6) >> 18); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_n1_s2_mul_25_1_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 6) >> 7); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_25_1_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe) | (tie_t << 1); +} + +static unsigned +Field_fld_n1_s2_mul_0_0_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_0_0_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_n1_s2_mul_7_4_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_7_4_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 2) >> 18); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_n2_s0_ldst_7_6_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_7_6_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 2) >> 19); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 2) >> 15); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 2) >> 17); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x3fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_n2_s0_ldst_9_5_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_9_5_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 2) >> 20); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_n2_s0_ldst_15_15_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_15_15_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_n2_s0_ldst_12_8_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_12_8_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_n2_s0_ldst_12_4_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_12_4_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_n2_s0_ldst_12_11_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_12_11_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_n2_s0_ldst_8_0_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_8_0_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_n2_s0_ldst_12_0_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_12_0_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_n2_s0_ldst_29_20_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_20_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_n2_s0_ldst_9_6_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_9_6_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_fld_n2_s0_ldst_29_11_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 2) >> 13); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_11_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x3ffff800) | (tie_t << 11); +} + +static unsigned +Field_fld_n2_s0_ldst_13_11_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_13_11_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_fld_n2_s0_ldst_29_14_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 2) >> 16); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_14_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x3fffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_n2_s0_ldst_29_5_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 2) >> 7); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_5_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_n2_s0_ldst_4_0_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_4_0_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 2) >> 14); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_n2_s0_ldst_3_0_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_3_0_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_n2_s0_ldst_4_4_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_4_4_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_n2_s0_ldst_29_10_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 2) >> 12); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_10_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0x3ffffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_n2_s0_ldst_8_4_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_8_4_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_n2_s0_ldst_29_8_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 2) >> 10); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_8_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 5) >> 16); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x7fff800) | (tie_t << 11); +} + +static unsigned +Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 5) >> 13); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x7ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_n2_s1_ld_26_10_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 5) >> 15); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_10_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x7fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 5) >> 18); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_n2_s1_ld_26_9_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 5) >> 14); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_9_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x7fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 5) >> 22); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 5) >> 20); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_n2_s1_ld_12_10_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_12_10_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_n2_s1_ld_12_8_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_12_8_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_n2_s1_ld_12_4_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_12_4_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_n2_s1_ld_12_2_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_12_2_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_n2_s1_ld_7_7_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_7_7_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_n2_s1_ld_7_6_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_7_6_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_n2_s1_ld_7_0_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_7_0_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 5) >> 21); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_n2_s1_ld_26_2_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_2_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_n2_s1_ld_1_0_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_1_0_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 9) >> 26); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e0000) | (tie_t << 17); +} + +static unsigned +Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 9) >> 22); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_n0_s0_ldst_7_5_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_7_5_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 9) >> 24); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_n0_s0_ldst_12_12_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_12_12_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_n0_s0_ldst_7_6_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_7_6_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_n0_s0_ldst_12_8_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_12_8_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_n0_s0_ldst_12_4_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_12_4_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_n0_s0_ldst_12_2_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_12_2_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_n0_s0_ldst_12_0_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_12_0_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 9) >> 21); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_n0_s0_ldst_22_16_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_22_16_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_n0_s0_ldst_22_0_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 9) >> 9); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_22_0_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_n0_s0_ldst_3_0_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_3_0_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_n0_s1_none_2_0_Slot_n0_s1_none_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_n0_s1_none_2_0_Slot_n0_s1_none_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_n0_s2_none_2_0_Slot_n0_s2_none_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_n0_s2_none_2_0_Slot_n0_s2_none_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 4) >> 27); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf800000) | (tie_t << 23); +} + +static unsigned +Field_fld_n0_s3_alu_9_6_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_9_6_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_n0_s3_alu_9_7_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_9_7_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_n0_s3_alu_19_13_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_19_13_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13); +} + +static unsigned +Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_n0_s3_alu_27_13_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 4) >> 17); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_27_13_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_n0_s3_alu_19_12_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_19_12_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_fld_n0_s3_alu_7_0_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_7_0_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 4) >> 24); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_n0_s3_alu_14_14_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_14_14_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_n0_s3_alu_14_10_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_14_10_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_n0_s3_alu_27_15_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 4) >> 19); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_27_15_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_n0_s3_alu_14_13_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_14_13_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_n0_s3_alu_9_3_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_9_3_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); +} + +static unsigned +Field_fld_n0_s3_alu_9_9_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_9_9_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_n0_s3_alu_27_22_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 4) >> 26); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_27_22_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_n0_s3_alu_27_16_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 4) >> 20); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_27_16_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 4) >> 16); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_n0_s3_alu_27_3_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 4) >> 7); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_27_3_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_n0_s3_alu_2_0_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_2_0_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_f5_s3_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f5_s3_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_bbi_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_bbi_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_bbi_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_bbi_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_imm8_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_imm8_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_imm8_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_imm8_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); + tie_t = (val << 24) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_imm8_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_imm8_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_imm8_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 15) >> 25); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_imm8_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 24) >> 25; + insn[0] = (insn[0] & ~0x1fc00) | (tie_t << 10); +} + +static unsigned +Field_imm8_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_imm8_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_imm8_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 11) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_imm8_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 24) >> 26; + insn[0] = (insn[0] & ~0x1f8000) | (tie_t << 15); +} + +static unsigned +Field_imm8_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 14) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc00) | (tie_t << 10); +} + +static unsigned +Field_imm8_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_imm8_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); + tie_t = (val << 24) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_imm8_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_imm8_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); + tie_t = (val << 24) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_imm8_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f5_s3_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f5_s3_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_imm8_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_imm8_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_f5_s3_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f5_s3_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 20) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_imm12b_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 20) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_imm12b_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 20) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_imm12b_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_f5_s3_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f5_s3_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 20) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_imm12b_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_offset_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_op2_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_op2_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_op2_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_op2_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_op2_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_op2_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_op2_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_op2_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_op2_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_r_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); + return tie_t; +} + +static void +Field_r_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6) | (tie_t << 1); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_r_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_r_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_r_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_r_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sal_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_sal_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_sal_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sargt_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_sargt_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sargt_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sargt_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_sas_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_sas_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_t2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_s2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_t4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_s4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_t8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_r8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr15_imm_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wbr15_imm_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wbr15_imm_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_bbe_shflimm_s0_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_bbe_shflimm_s0_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_bbe_shflimm_s0_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_bbe_shflimm_s0_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_bbe_shflimm_s0_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_bbe_shflimm_s0_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_bbe_shflimm_s0_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_fld_bbe_shflimm_s0_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_fld_bbe_shflimm_s0_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_fld_bbe_shflimm_s0_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_fld_bbe_shflimm_s0_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_fld_bbe_shflimm_s0_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 21) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uus_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uus_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uus_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uus_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uus_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uus_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uus_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uus_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uus_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uus_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uus_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uus_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uus_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uus_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbre_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbre_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbre_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbre_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbre_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbre_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbre_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbre_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbre_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbre_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbre_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbre_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrr_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrr_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrr_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrr_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_arr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_arr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_arr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_arr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_arr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_arr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_saimm4_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2) | (tie_t << 1); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_saimm4_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_saimm4_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_saimm4_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_saimm4_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_saimm4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_saimm4_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm4_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2) | (tie_t << 1); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm4_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_saimm4_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_saimm5_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_saimm5_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6) | (tie_t << 1); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm5_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_saimm5_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_saimm5_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_saimm5_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_saimm5_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_saimm5_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_saimm5_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm5_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6) | (tie_t << 1); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm5_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm5_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_bbe_ltrx2nimm_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_bbe_ltrx2nimm_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrx2nimm_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrx2nimm_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrx2nimm_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrx2nimm_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrx2nimm_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrx2nimm_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrx2nimm_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrx2nimm_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrx2nimm_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrx2nimm_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrx2nimm_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrx2nimm_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxn_2imm_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_bbe_ltrxn_2imm_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxn_2imm_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxn_2imm_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxn_2imm_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxn_2imm_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxn_2imm_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxn_2imm_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxn_2imm_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxn_2imm_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxn_2imm_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxn_2imm_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxn_2imm_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxn_2imm_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxnimm_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_bbe_ltrxnimm_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxnimm_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxnimm_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxnimm_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxnimm_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxnimm_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxnimm_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxnimm_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxnimm_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxnimm_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxnimm_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxnimm_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxnimm_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_imm1_2n_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_imm1_2n_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_imm1_2n_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_imm1_2n_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_imm1_2n_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_imm1_2n_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_imm1_2n_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_imm1_2n_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_imm1_2n_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_imm1_2n_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_imm1_2n_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_sqz_vbr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vbr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_sqz_vbr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vbr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_sqz_vbr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vbr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_sqz_vbr_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vbr_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_sqz_vbr_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vbr_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_sqz_vt_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vt_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_sqz_vt_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vt_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_sqz_vt_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vt_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_sqz_vt_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vt_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_sqz_vt_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vt_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_arr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_arr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_arr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_arr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_arr_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_arr_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_arr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_arr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_arr_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_arr_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_arr_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_arr_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_vbr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_vbr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_vbr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_vbr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_vbr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_vbr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_vt_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_vt_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_vt_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_vt_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_vt_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_vt_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_vt_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_vt_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_vt_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_vt_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_vt_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_vt_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_wvr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_wvr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_wvr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_wvr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_wvr_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_wvr_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_wvr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_wvr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_wvr_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_wvr_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_wvr_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_wvr_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_arr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_arr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_arr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_arr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_arr_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_arr_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_arr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_arr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_arr_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_arr_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_arr_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_arr_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_vt_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_vt_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_vt_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_vt_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_vt_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_vt_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_vt_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_vt_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_vt_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_vt_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_vt_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_vt_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_wvr_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_wvr_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_multiply_arr_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_arr_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_multiply_arr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_arr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_multiply_arr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_arr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_multiply_arr_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_arr_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_multiply_arr_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_arr_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_multiply_arr_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_arr_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_multiply_arr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_arr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_multiply_vp_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vp_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_multiply_vp_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vp_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_multiply_vp_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vp_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_multiply_vp_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vp_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_multiply_vr_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vr_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_multiply_vr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_multiply_vr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_multiply_vr_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vr_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ivp_sem_multiply_vr_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vr_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_multiply_vr_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vr_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ivp_sem_multiply_vr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_multiply_vs_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vs_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ivp_sem_multiply_vs_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vs_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_multiply_vs_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vs_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_multiply_vs_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vs_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_multiply_vs_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vs_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_multiply_vs_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vs_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_multiply_vs_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vs_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_multiply_wvt_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_wvt_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_multiply_wvt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_wvt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_multiply_wvt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_wvt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_multiply_wvt_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_wvt_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_multiply_wvt_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 6) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_wvt_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ivp_sem_multiply_wvt_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_wvt_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_multiply_wvt_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_wvt_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f0_s3_alu_24_19_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 7) >> 26); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_24_19_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x1f80000) | (tie_t << 19); +} + +static unsigned +Field_fld_f0_s3_alu_33_10_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 22) | (insn[0] >> 10); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_10_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xfffffc00) | (tie_t << 10); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 22); +} + +static unsigned +Field_fld_f0_s3_alu_33_19_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 13) | (insn[0] >> 19); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_19_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfff80000) | (tie_t << 19); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 13); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vbr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vbr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vbr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vbr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vbr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vbr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vbr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vbr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vs_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vs_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vs_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vs_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vs_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vs_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vs_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vs_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vs_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vs_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vbr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vbr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vbr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vbr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vbr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vbr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vbr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vbr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vbr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vbr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vbr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vbr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vbr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vbr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vbr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vbr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vbr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vbr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vs_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vs_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vs_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vs_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vs_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vs_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vs_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vs_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vs_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vs_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vsm_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vsm_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vsm_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vsm_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vsm_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vsm_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vsm_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vsm_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vsm_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vsm_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vr_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vr_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vt_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vt_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vt_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vt_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_arr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_arr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_arr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_arr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_arr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_arr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_arr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_arr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_arr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_arr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_arr_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_arr_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_arr_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_arr_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_arr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_arr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_select_isel_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_isel_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_select_isel_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_isel_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_isel_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_isel_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_isel_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_isel_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_vec_select_isel_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_isel_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_isel_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 10) >> 25); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_isel_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_select_isel_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_isel_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_ishfl_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_ishfl_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_select_ishfl_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_ishfl_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_ishfl_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_ishfl_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_ishfl_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_ishfl_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_select_ishfl_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_ishfl_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_select_ishfl_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_ishfl_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_select_ishfl_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_ishfl_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_slct_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_slct_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_select_slct_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_slct_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_select_slct_h_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_slct_h_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_select_slct_h_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_slct_h_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_select_sr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_sr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_select_sr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_sr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_select_sr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_sr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_select_sr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_sr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_select_sr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_sr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vbr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vbr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vbr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vbr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vbr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vbr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vbr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vbr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vbr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vbr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vr_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vr_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vs_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vs_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vs_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vs_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vs_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vs_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vs_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vs_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vs_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vs_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vs_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vs_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vs_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vs_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vt_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vt_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vt_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vt_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vu_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vu_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vu_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vu_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vs_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vs_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vs_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vs_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vs_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vs_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vs_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vs_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vs_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vs_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vs_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vs_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vs_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vs_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_saimm6_31_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_saimm6_31_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm6_31_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_saimm6_31_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_saimm6_31_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_saimm6_31_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_saimm6_31_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_saimm6_31_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_saimm6_31_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_saimm6_31_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm6_31_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_saimm6_31_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm6_31_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_saimm6_31_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_bbe_selimm_s0_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_bbe_selimm_s0_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_bbe_selimm_s0_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_bbe_selimm_s0_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vr_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vr_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_f1_s2_mul_28_5_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 3) >> 8); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_28_5_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0x1fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_bbe_selimm_s2_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_bbe_selimm_s2_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_bbe_shflimm_s2_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_fld_bbe_shflimm_s2_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vbr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vbr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vbr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vbr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vbr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vbr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vs_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vs_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vs_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vs_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vs_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vs_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vt_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vt_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_multiply_vt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_multiply_vt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_multiply_vt_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vt_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_spfma_vbr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vbr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_spfma_vbr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vbr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_spfma_vbr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vbr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_spfma_vr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_spfma_vr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_spfma_vr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_spfma_vs_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vs_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_spfma_vs_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vs_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_spfma_vs_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vs_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_spfma_vt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spfma_vt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spfma_vt_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vt_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f1_s3_alu_19_19_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_19_19_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_f1_s3_alu_30_19_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 1) >> 20); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_30_19_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_arr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_arr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_arr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_arr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_arr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_arr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vs_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vs_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vs_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vs_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vs_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vs_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vt_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vt_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f2_s2_mul_30_10_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 1) >> 11); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_30_10_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x7ffffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_divide_lane_ctrl_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_divide_lane_ctrl_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_divide_vr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_divide_vr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_divide_vs_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_divide_vs_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_divide_vt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_divide_vt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_divide_vu_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_divide_vu_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_multiply_vbr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vbr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s3_alu_19_19_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_19_19_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_f2_s3_alu_30_19_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 1) >> 20); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_30_19_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_f3_s3_alu_18_18_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_18_18_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_f3_s3_alu_28_18_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 3) >> 21); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_18_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vbr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 7) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vbr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vbr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 7) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vbr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x1800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vbs_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vbs_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vbs_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vbs_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_bbe_selimm_s4_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_bbe_selimm_s4_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_bbe_shflimm_s4_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_fld_bbe_shflimm_s4_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_multiply_vq_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vq_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul2_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul2_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_n0_s3_alu_27_19_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 4) >> 23); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_27_19_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_mtk_andpopc_c_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_mtk_andpopc_c_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_mtk_andpopc_c_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_mtk_andpopc_c_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_mtk_andpopc_inb_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_mtk_andpopc_inb_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_mtk_andpopc_inb_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_mtk_andpopc_inb_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_mtk_andpopc_ina_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_mtk_andpopc_ina_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_mtk_andpopc_ina_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_mtk_andpopc_ina_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_mtk_andpopc_odata_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_mtk_andpopc_odata_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_mtk_andpopc_odata_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_mtk_andpopc_odata_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_iq_tie2apb_inq0_pop_qdata_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_iq_tie2apb_inq0_pop_qdata_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_iq_tie2apb_inq0_is_ready_is_ready_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_iq_tie2apb_inq0_is_ready_is_ready_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_iq_tie2apb_inq0_nonblocking_peek_success_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_iq_tie2apb_inq0_nonblocking_peek_success_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_iq_tie2apb_inq0_nonblocking_peek_qdata_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_iq_tie2apb_inq0_nonblocking_peek_qdata_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_iq_tie2apb_inq0_nonblocking_pop_success_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_iq_tie2apb_inq0_nonblocking_pop_success_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_iq_tie2apb_inq0_nonblocking_pop_qdata_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_iq_tie2apb_inq0_nonblocking_pop_qdata_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_iq_tie2apb_inq0_blocking_peek_qdata_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_iq_tie2apb_inq0_blocking_peek_qdata_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_push_read_qaddr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_push_read_qaddr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_push_read_qdata_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_push_read_qdata_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_push_write_qaddr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_push_write_qaddr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_push_write_qdata_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_push_write_qdata_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_is_ready_is_ready_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_is_ready_is_ready_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_nonblocking_push_read_success_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_nonblocking_push_read_success_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_nonblocking_push_read_qaddr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_nonblocking_push_read_qaddr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_nonblocking_push_read_qdata_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_nonblocking_push_read_qdata_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_nonblocking_push_write_success_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_nonblocking_push_write_success_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_nonblocking_push_write_qaddr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_nonblocking_push_write_qaddr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_nonblocking_push_write_qdata_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_nonblocking_push_write_qdata_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +static unsigned +Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +enum xtensa_field_id { + FIELD_t, + FIELD_bbi4, + FIELD_bbi, + FIELD_imm12, + FIELD_imm8, + FIELD_s, + FIELD_imm12b, + FIELD_imm16, + FIELD_m, + FIELD_n, + FIELD_offset, + FIELD_op0, + FIELD_op1, + FIELD_op2, + FIELD_r, + FIELD_sa4, + FIELD_sae4, + FIELD_sae, + FIELD_sal, + FIELD_sargt, + FIELD_sas4, + FIELD_sas, + FIELD_sr, + FIELD_st, + FIELD_thi3, + FIELD_imm4, + FIELD_mn, + FIELD_i, + FIELD_imm6lo, + FIELD_imm6hi, + FIELD_imm7lo, + FIELD_imm7hi, + FIELD_z, + FIELD_imm6, + FIELD_imm7, + FIELD_t2, + FIELD_s2, + FIELD_r2, + FIELD_t4, + FIELD_s4, + FIELD_r4, + FIELD_t8, + FIELD_s8, + FIELD_r8, + FIELD_xt_wbr15_imm, + FIELD_xt_wbr18_imm, + FIELD_fld_F0_S0_LdSt_11_4, + FIELD_fld_F0_S0_LdSt_11_8, + FIELD_fld_F0_S0_LdSt_11_9, + FIELD_fld_F0_S0_LdSt_12_0, + FIELD_fld_F0_S0_LdSt_12_11, + FIELD_fld_F0_S0_LdSt_12_12, + FIELD_fld_F0_S0_LdSt_12_2, + FIELD_fld_F0_S0_LdSt_12_4, + FIELD_fld_F0_S0_LdSt_12_8, + FIELD_fld_F0_S0_LdSt_13_9, + FIELD_fld_F0_S0_LdSt_15_15, + FIELD_fld_F0_S0_LdSt_33_11, + FIELD_fld_F0_S0_LdSt_33_12, + FIELD_fld_F0_S0_LdSt_33_13, + FIELD_fld_F0_S0_LdSt_33_14, + FIELD_fld_F0_S0_LdSt_33_15, + FIELD_fld_F0_S0_LdSt_33_16, + FIELD_fld_F0_S0_LdSt_33_17, + FIELD_fld_F0_S0_LdSt_33_18, + FIELD_fld_F0_S0_LdSt_33_19, + FIELD_fld_F0_S0_LdSt_33_20, + FIELD_fld_F0_S0_LdSt_33_27, + FIELD_fld_F0_S0_LdSt_33_9, + FIELD_fld_F0_S0_LdSt_3_0, + FIELD_fld_F0_S0_LdSt_7_4, + FIELD_fld_F0_S0_LdSt_7_5, + FIELD_fld_F0_S0_LdSt_7_6, + FIELD_fld_F0_S0_LdSt_7_7, + FIELD_fld_F0_S0_LdSt_8_0, + FIELD_fld_F0_S0_LdSt_8_4, + FIELD_fld_F0_S0_LdSt_8_8, + FIELD_fld_bbe_shflimm_S0, + FIELD_fld_ivp_sem_ld_st_i_bimm4, + FIELD_fld_ivp_sem_ld_st_i_bimm4b2n, + FIELD_fld_ivp_sem_ld_st_i_bimm4bn, + FIELD_fld_ivp_sem_ld_st_i_bimm4bn_2, + FIELD_fld_ivp_sem_ld_st_i_bimm4x1, + FIELD_fld_ivp_sem_ld_st_i_bimm4x2, + FIELD_fld_ivp_sem_ld_st_i_bimm4x4, + FIELD_fld_ivp_sem_ld_st_i_bimm6, + FIELD_fld_ivp_sem_ld_st_i_bimm6b2n, + FIELD_fld_ivp_sem_ld_st_i_bimm6bn, + FIELD_fld_ivp_sem_ld_st_i_bimm6bn_2, + FIELD_fld_ivp_sem_ld_st_i_bimm6x1, + FIELD_fld_ivp_sem_ld_st_i_bimm6x2, + FIELD_fld_ivp_sem_ld_st_i_bimm6x4, + FIELD_fld_ivp_sem_ld_st_i_bimm8, + FIELD_fld_ivp_sem_ld_st_i_bimm8x4, + FIELD_fld_ivp_sem_ld_st_i_bimmb4, + FIELD_fld_ivp_sem_ld_st_i_bimmb6, + FIELD_fld_ivp_sem_ld_st_i_bimmb8, + FIELD_fld_ivp_sem_ld_st_i_bimmh4, + FIELD_fld_ivp_sem_ld_st_i_bimmh6, + FIELD_fld_ivp_sem_ld_st_i_bimmh8, + FIELD_fld_ivp_sem_ld_st_uul, + FIELD_fld_ivp_sem_ld_st_uus, + FIELD_fld_ivp_sem_ld_st_valignr, + FIELD_fld_ivp_sem_ld_st_vbr, + FIELD_fld_ivp_sem_ld_st_vbre, + FIELD_fld_ivp_sem_ld_st_vr, + FIELD_fld_ivp_sem_ld_st_vrr, + FIELD_fld_ivp_sem_ld_st_vrul, + FIELD_fld_ivp_sem_vec_alu_arr, + FIELD_fld_ivp_sem_vec_alu_vbr, + FIELD_fld_ivp_sem_vec_alu_vr, + FIELD_fld_ivp_sem_vec_alu_vt, + FIELD_fld_ivp_sem_vec_rep_i, + FIELD_fld_ivp_sem_vec_rep_i32, + FIELD_fld_ivp_sem_vec_rep_i8, + FIELD_fld_ivp_sem_vec_rep_vr, + FIELD_fld_ivp_sem_vec_rep_vt, + FIELD_fld_ivp_sem_vec_scatter_gather_ars, + FIELD_fld_ivp_sem_vec_scatter_gather_gt, + FIELD_fld_ivp_sem_vec_scatter_gather_vbr, + FIELD_fld_ivp_sem_vec_scatter_gather_vs, + FIELD_fld_ivp_sem_vec_shift_vr, + FIELD_fld_ivp_sem_vec_shift_vt, + FIELD_fld_ivp_sem_vec_specialized_seli_vr, + FIELD_fld_ivp_sem_vec_specialized_seli_vt, + FIELD_fld_saimm4, + FIELD_fld_saimm5, + FIELD_fld_F0_S1_Ld_12_11, + FIELD_fld_F0_S1_Ld_12_12, + FIELD_fld_F0_S1_Ld_12_4, + FIELD_fld_F0_S1_Ld_15_10, + FIELD_fld_F0_S1_Ld_15_13, + FIELD_fld_F0_S1_Ld_15_14, + FIELD_fld_F0_S1_Ld_15_15, + FIELD_fld_F0_S1_Ld_15_2, + FIELD_fld_F0_S1_Ld_15_4, + FIELD_fld_F0_S1_Ld_15_8, + FIELD_fld_F0_S1_Ld_24_0, + FIELD_fld_F0_S1_Ld_24_11, + FIELD_fld_F0_S1_Ld_24_12, + FIELD_fld_F0_S1_Ld_24_13, + FIELD_fld_F0_S1_Ld_24_14, + FIELD_fld_F0_S1_Ld_24_16, + FIELD_fld_F0_S1_Ld_24_17, + FIELD_fld_F0_S1_Ld_24_18, + FIELD_fld_F0_S1_Ld_24_8, + FIELD_fld_F0_S1_Ld_3_0, + FIELD_fld_F0_S1_Ld_3_2, + FIELD_fld_F0_S1_Ld_7_0, + FIELD_fld_F0_S1_Ld_7_2, + FIELD_fld_F0_S1_Ld_7_3, + FIELD_fld_F0_S1_Ld_7_4, + FIELD_fld_F0_S1_Ld_7_5, + FIELD_fld_F0_S1_Ld_7_6, + FIELD_fld_F0_S1_Ld_7_7, + FIELD_fld_bbe_ltrx2nimm, + FIELD_fld_bbe_ltrxn_2imm, + FIELD_fld_bbe_ltrxnimm, + FIELD_fld_imm1_2N, + FIELD_fld_ivp_sem_sqz_vbr, + FIELD_fld_ivp_sem_sqz_vt, + FIELD_fld_ivp_sem_vbool_alu_ltr_art, + FIELD_fld_ivp_sem_vbool_alu_ltr_vbr, + FIELD_fld_ivp_sem_vbool_alu_ltr_vbs, + FIELD_fld_ivp_sem_vbool_alu_ltr_vbt, + FIELD_fld_ivp_sem_vec_mov_arr, + FIELD_fld_ivp_sem_vec_mov_i_IMM_movint, + FIELD_fld_ivp_sem_vec_mov_i_imm4, + FIELD_fld_ivp_sem_vec_mov_immmovvi, + FIELD_fld_ivp_sem_vec_mov_vbr, + FIELD_fld_ivp_sem_vec_mov_vt, + FIELD_fld_ivp_sem_vec_mov_wvr, + FIELD_fld_ivp_sem_vec_scatter_gather_gs, + FIELD_fld_ivp_sem_vec_scatter_gather_vt, + FIELD_fld_ivp_sem_wvec_pack_arr, + FIELD_fld_ivp_sem_wvec_pack_vt, + FIELD_fld_ivp_sem_wvec_pack_wvr, + FIELD_fld_F0_S2_Mul_11_8, + FIELD_fld_F0_S2_Mul_13_12, + FIELD_fld_F0_S2_Mul_18_12, + FIELD_fld_F0_S2_Mul_18_14, + FIELD_fld_F0_S2_Mul_18_9, + FIELD_fld_F0_S2_Mul_1_0, + FIELD_fld_F0_S2_Mul_26_12, + FIELD_fld_F0_S2_Mul_26_13, + FIELD_fld_F0_S2_Mul_26_14, + FIELD_fld_F0_S2_Mul_26_2, + FIELD_fld_F0_S2_Mul_26_20, + FIELD_fld_F0_S2_Mul_26_21, + FIELD_fld_F0_S2_Mul_3_0, + FIELD_fld_F0_S2_Mul_3_3, + FIELD_fld_F0_S2_Mul_4_4, + FIELD_fld_F0_S2_Mul_7_4, + FIELD_fld_F0_S2_Mul_7_5, + FIELD_fld_ivp_sem_multiply_arr, + FIELD_fld_ivp_sem_multiply_vp, + FIELD_fld_ivp_sem_multiply_vr, + FIELD_fld_ivp_sem_multiply_vs, + FIELD_fld_ivp_sem_multiply_wvt, + FIELD_fld_ivp_sem_unpack_wvec_mov_vr, + FIELD_fld_ivp_sem_unpack_wvec_mov_vs, + FIELD_fld_ivp_sem_unpack_wvec_mov_wvr, + FIELD_fld_ivp_sem_unpack_wvec_mov_wvt, + FIELD_fld_ivp_sem_vec_alu_vbt, + FIELD_fld_ivp_sem_vec_alu_vs, + FIELD_fld_F0_S3_ALU_0_0, + FIELD_fld_F0_S3_ALU_14_10, + FIELD_fld_F0_S3_ALU_14_11, + FIELD_fld_F0_S3_ALU_14_13, + FIELD_fld_F0_S3_ALU_14_14, + FIELD_fld_F0_S3_ALU_14_8, + FIELD_fld_F0_S3_ALU_24_10, + FIELD_fld_F0_S3_ALU_24_13, + FIELD_fld_F0_S3_ALU_24_19, + FIELD_fld_F0_S3_ALU_24_20, + FIELD_fld_F0_S3_ALU_33_10, + FIELD_fld_F0_S3_ALU_33_13, + FIELD_fld_F0_S3_ALU_33_18, + FIELD_fld_F0_S3_ALU_33_19, + FIELD_fld_F0_S3_ALU_33_20, + FIELD_fld_F0_S3_ALU_33_25, + FIELD_fld_F0_S3_ALU_33_26, + FIELD_fld_F0_S3_ALU_33_27, + FIELD_fld_F0_S3_ALU_33_28, + FIELD_fld_F0_S3_ALU_33_9, + FIELD_fld_F0_S3_ALU_3_0, + FIELD_fld_F0_S3_ALU_3_1, + FIELD_fld_F0_S3_ALU_3_2, + FIELD_fld_F0_S3_ALU_3_3, + FIELD_fld_F0_S3_ALU_7_3, + FIELD_fld_F0_S3_ALU_7_4, + FIELD_fld_F0_S3_ALU_7_7, + FIELD_fld_F0_S3_ALU_8_0, + FIELD_fld_F0_S3_ALU_8_8, + FIELD_fld_F0_S3_ALU_9_0, + FIELD_fld_F0_S3_ALU_9_7, + FIELD_fld_F0_S3_ALU_9_8, + FIELD_fld_fp_sem_hp_cnv_i_imm4, + FIELD_fld_fp_sem_hp_cnv_vbr, + FIELD_fld_fp_sem_hp_cnv_vr, + FIELD_fld_fp_sem_hp_cnv_vs, + FIELD_fld_fp_sem_hp_cnv_vt, + FIELD_fld_ivp_sem_sp32cvt_i_imm5, + FIELD_fld_ivp_sem_sp32cvt_vbr, + FIELD_fld_ivp_sem_sp32cvt_vr, + FIELD_fld_ivp_sem_sp32cvt_vt, + FIELD_fld_ivp_sem_spmisc_vbr, + FIELD_fld_ivp_sem_spmisc_vr, + FIELD_fld_ivp_sem_spmisc_vs, + FIELD_fld_ivp_sem_spmisc_vsM, + FIELD_fld_ivp_sem_spmisc_vt, + FIELD_fld_ivp_sem_vec_alu_i_imm3, + FIELD_fld_ivp_sem_vec_reduce_vbr, + FIELD_fld_ivp_sem_vec_reduce_vbt, + FIELD_fld_ivp_sem_vec_reduce_vr, + FIELD_fld_ivp_sem_vec_reduce_vt, + FIELD_fld_ivp_sem_vec_rep_arr, + FIELD_fld_ivp_sem_vec_select_isel, + FIELD_fld_ivp_sem_vec_select_ishfl, + FIELD_fld_ivp_sem_vec_select_slct, + FIELD_fld_ivp_sem_vec_select_slct_h, + FIELD_fld_ivp_sem_vec_select_sr, + FIELD_fld_ivp_sem_vec_select_vbr, + FIELD_fld_ivp_sem_vec_select_vr, + FIELD_fld_ivp_sem_vec_select_vs, + FIELD_fld_ivp_sem_vec_select_vt, + FIELD_fld_ivp_sem_vec_select_vu, + FIELD_fld_ivp_sem_vec_shift_vs, + FIELD_fld_saimm6_31, + FIELD_fld_F1_S0_LdStALU_12_0, + FIELD_fld_F1_S0_LdStALU_12_12, + FIELD_fld_F1_S0_LdStALU_12_2, + FIELD_fld_F1_S0_LdStALU_12_4, + FIELD_fld_F1_S0_LdStALU_12_8, + FIELD_fld_F1_S0_LdStALU_14_10, + FIELD_fld_F1_S0_LdStALU_14_12, + FIELD_fld_F1_S0_LdStALU_14_14, + FIELD_fld_F1_S0_LdStALU_15_15, + FIELD_fld_F1_S0_LdStALU_30_12, + FIELD_fld_F1_S0_LdStALU_30_13, + FIELD_fld_F1_S0_LdStALU_30_14, + FIELD_fld_F1_S0_LdStALU_30_15, + FIELD_fld_F1_S0_LdStALU_30_16, + FIELD_fld_F1_S0_LdStALU_30_17, + FIELD_fld_F1_S0_LdStALU_30_18, + FIELD_fld_F1_S0_LdStALU_30_19, + FIELD_fld_F1_S0_LdStALU_30_20, + FIELD_fld_F1_S0_LdStALU_30_6, + FIELD_fld_F1_S0_LdStALU_30_8, + FIELD_fld_F1_S0_LdStALU_30_9, + FIELD_fld_F1_S0_LdStALU_3_0, + FIELD_fld_F1_S0_LdStALU_5_0, + FIELD_fld_F1_S0_LdStALU_5_4, + FIELD_fld_F1_S0_LdStALU_7_4, + FIELD_fld_F1_S0_LdStALU_7_5, + FIELD_fld_F1_S0_LdStALU_7_7, + FIELD_fld_F1_S0_LdStALU_9_9, + FIELD_fld_bbe_selimm_S0, + FIELD_fld_ivp_sem_vec_scatter_gather_vr, + FIELD_fld_ivp_sem_vec_specialized_seli_vs, + FIELD_fld_F1_S1_Ld_12_10, + FIELD_fld_F1_S1_Ld_12_11, + FIELD_fld_F1_S1_Ld_12_12, + FIELD_fld_F1_S1_Ld_12_4, + FIELD_fld_F1_S1_Ld_12_9, + FIELD_fld_F1_S1_Ld_15_10, + FIELD_fld_F1_S1_Ld_15_13, + FIELD_fld_F1_S1_Ld_15_14, + FIELD_fld_F1_S1_Ld_15_15, + FIELD_fld_F1_S1_Ld_15_2, + FIELD_fld_F1_S1_Ld_15_4, + FIELD_fld_F1_S1_Ld_15_8, + FIELD_fld_F1_S1_Ld_1_0, + FIELD_fld_F1_S1_Ld_26_11, + FIELD_fld_F1_S1_Ld_26_12, + FIELD_fld_F1_S1_Ld_26_13, + FIELD_fld_F1_S1_Ld_26_16, + FIELD_fld_F1_S1_Ld_26_18, + FIELD_fld_F1_S1_Ld_26_2, + FIELD_fld_F1_S1_Ld_3_0, + FIELD_fld_F1_S1_Ld_3_2, + FIELD_fld_F1_S1_Ld_7_0, + FIELD_fld_F1_S1_Ld_7_2, + FIELD_fld_F1_S1_Ld_7_3, + FIELD_fld_F1_S1_Ld_7_4, + FIELD_fld_F1_S1_Ld_7_5, + FIELD_fld_F1_S1_Ld_7_6, + FIELD_fld_F1_S1_Ld_7_7, + FIELD_fld_F1_S2_Mul_13_10, + FIELD_fld_F1_S2_Mul_13_2, + FIELD_fld_F1_S2_Mul_13_5, + FIELD_fld_F1_S2_Mul_14_10, + FIELD_fld_F1_S2_Mul_28_12, + FIELD_fld_F1_S2_Mul_28_15, + FIELD_fld_F1_S2_Mul_28_16, + FIELD_fld_F1_S2_Mul_28_18, + FIELD_fld_F1_S2_Mul_28_20, + FIELD_fld_F1_S2_Mul_28_4, + FIELD_fld_F1_S2_Mul_28_5, + FIELD_fld_F1_S2_Mul_3_0, + FIELD_fld_F1_S2_Mul_3_2, + FIELD_fld_F1_S2_Mul_3_3, + FIELD_fld_F1_S2_Mul_4_4, + FIELD_fld_F1_S2_Mul_9_5, + FIELD_fld_F1_S2_Mul_9_6, + FIELD_fld_bbe_selimm_S2, + FIELD_fld_bbe_shflimm_S2, + FIELD_fld_fp_sem_hp_fma_vbr, + FIELD_fld_fp_sem_hp_fma_vr, + FIELD_fld_fp_sem_hp_fma_vs, + FIELD_fld_fp_sem_hp_fma_vt, + FIELD_fld_ivp_sem_multiply_vt, + FIELD_fld_ivp_sem_spfma_vbr, + FIELD_fld_ivp_sem_spfma_vr, + FIELD_fld_ivp_sem_spfma_vs, + FIELD_fld_ivp_sem_spfma_vt, + FIELD_fld_ivp_sem_unpack_wvec_mov_vt, + FIELD_fld_F1_S3_ALU_0_0, + FIELD_fld_F1_S3_ALU_14_10, + FIELD_fld_F1_S3_ALU_14_13, + FIELD_fld_F1_S3_ALU_14_14, + FIELD_fld_F1_S3_ALU_14_8, + FIELD_fld_F1_S3_ALU_19_14, + FIELD_fld_F1_S3_ALU_19_15, + FIELD_fld_F1_S3_ALU_19_19, + FIELD_fld_F1_S3_ALU_19_4, + FIELD_fld_F1_S3_ALU_19_7, + FIELD_fld_F1_S3_ALU_30_15, + FIELD_fld_F1_S3_ALU_30_17, + FIELD_fld_F1_S3_ALU_30_19, + FIELD_fld_F1_S3_ALU_30_20, + FIELD_fld_F1_S3_ALU_30_22, + FIELD_fld_F1_S3_ALU_30_23, + FIELD_fld_F1_S3_ALU_30_6, + FIELD_fld_F1_S3_ALU_30_8, + FIELD_fld_F1_S3_ALU_3_0, + FIELD_fld_F1_S3_ALU_3_1, + FIELD_fld_F1_S3_ALU_3_2, + FIELD_fld_F1_S3_ALU_3_3, + FIELD_fld_F1_S3_ALU_5_0, + FIELD_fld_F1_S3_ALU_9_0, + FIELD_fld_F1_S3_ALU_9_1, + FIELD_fld_F1_S3_ALU_9_2, + FIELD_fld_F1_S3_ALU_9_3, + FIELD_fld_F1_S3_ALU_9_7, + FIELD_fld_F1_S3_ALU_9_8, + FIELD_fld_F1_S3_ALU_9_9, + FIELD_fld_ivp_sem_vec_histogram_arr, + FIELD_fld_ivp_sem_vec_histogram_vr, + FIELD_fld_ivp_sem_vec_histogram_vs, + FIELD_fld_ivp_sem_vec_histogram_vt, + FIELD_fld_F2_S0_LdSt_12_0, + FIELD_fld_F2_S0_LdSt_12_10, + FIELD_fld_F2_S0_LdSt_12_2, + FIELD_fld_F2_S0_LdSt_12_4, + FIELD_fld_F2_S0_LdSt_12_8, + FIELD_fld_F2_S0_LdSt_15_15, + FIELD_fld_F2_S0_LdSt_28_11, + FIELD_fld_F2_S0_LdSt_28_12, + FIELD_fld_F2_S0_LdSt_28_13, + FIELD_fld_F2_S0_LdSt_28_14, + FIELD_fld_F2_S0_LdSt_28_15, + FIELD_fld_F2_S0_LdSt_28_16, + FIELD_fld_F2_S0_LdSt_28_17, + FIELD_fld_F2_S0_LdSt_28_18, + FIELD_fld_F2_S0_LdSt_28_20, + FIELD_fld_F2_S0_LdSt_28_4, + FIELD_fld_F2_S0_LdSt_28_8, + FIELD_fld_F2_S0_LdSt_3_0, + FIELD_fld_F2_S0_LdSt_3_2, + FIELD_fld_F2_S0_LdSt_7_2, + FIELD_fld_F2_S0_LdSt_7_4, + FIELD_fld_F2_S1_Ld_12_10, + FIELD_fld_F2_S1_Ld_12_11, + FIELD_fld_F2_S1_Ld_12_4, + FIELD_fld_F2_S1_Ld_12_9, + FIELD_fld_F2_S1_Ld_15_10, + FIELD_fld_F2_S1_Ld_15_13, + FIELD_fld_F2_S1_Ld_15_14, + FIELD_fld_F2_S1_Ld_15_15, + FIELD_fld_F2_S1_Ld_15_2, + FIELD_fld_F2_S1_Ld_15_4, + FIELD_fld_F2_S1_Ld_15_8, + FIELD_fld_F2_S1_Ld_1_0, + FIELD_fld_F2_S1_Ld_26_11, + FIELD_fld_F2_S1_Ld_26_12, + FIELD_fld_F2_S1_Ld_26_13, + FIELD_fld_F2_S1_Ld_26_16, + FIELD_fld_F2_S1_Ld_26_18, + FIELD_fld_F2_S1_Ld_26_2, + FIELD_fld_F2_S1_Ld_3_0, + FIELD_fld_F2_S1_Ld_3_2, + FIELD_fld_F2_S1_Ld_7_0, + FIELD_fld_F2_S1_Ld_7_2, + FIELD_fld_F2_S1_Ld_7_3, + FIELD_fld_F2_S1_Ld_7_4, + FIELD_fld_F2_S1_Ld_7_6, + FIELD_fld_F2_S1_Ld_7_7, + FIELD_fld_F2_S2_Mul_14_10, + FIELD_fld_F2_S2_Mul_14_11, + FIELD_fld_F2_S2_Mul_14_5, + FIELD_fld_F2_S2_Mul_19_10, + FIELD_fld_F2_S2_Mul_19_15, + FIELD_fld_F2_S2_Mul_19_7, + FIELD_fld_F2_S2_Mul_30_10, + FIELD_fld_F2_S2_Mul_30_12, + FIELD_fld_F2_S2_Mul_30_15, + FIELD_fld_F2_S2_Mul_30_18, + FIELD_fld_F2_S2_Mul_30_19, + FIELD_fld_F2_S2_Mul_30_20, + FIELD_fld_F2_S2_Mul_30_21, + FIELD_fld_F2_S2_Mul_30_6, + FIELD_fld_F2_S2_Mul_3_0, + FIELD_fld_F2_S2_Mul_4_0, + FIELD_fld_F2_S2_Mul_4_3, + FIELD_fld_F2_S2_Mul_5_0, + FIELD_fld_ivp_sem_divide_lane_ctrl, + FIELD_fld_ivp_sem_divide_vr, + FIELD_fld_ivp_sem_divide_vs, + FIELD_fld_ivp_sem_divide_vt, + FIELD_fld_ivp_sem_divide_vu, + FIELD_fld_ivp_sem_multiply_vbr, + FIELD_fld_F2_S3_ALU_0_0, + FIELD_fld_F2_S3_ALU_14_10, + FIELD_fld_F2_S3_ALU_14_13, + FIELD_fld_F2_S3_ALU_14_14, + FIELD_fld_F2_S3_ALU_14_8, + FIELD_fld_F2_S3_ALU_19_14, + FIELD_fld_F2_S3_ALU_19_15, + FIELD_fld_F2_S3_ALU_19_19, + FIELD_fld_F2_S3_ALU_19_4, + FIELD_fld_F2_S3_ALU_19_7, + FIELD_fld_F2_S3_ALU_30_15, + FIELD_fld_F2_S3_ALU_30_18, + FIELD_fld_F2_S3_ALU_30_19, + FIELD_fld_F2_S3_ALU_30_20, + FIELD_fld_F2_S3_ALU_30_22, + FIELD_fld_F2_S3_ALU_30_23, + FIELD_fld_F2_S3_ALU_30_6, + FIELD_fld_F2_S3_ALU_30_8, + FIELD_fld_F2_S3_ALU_3_0, + FIELD_fld_F2_S3_ALU_3_1, + FIELD_fld_F2_S3_ALU_3_2, + FIELD_fld_F2_S3_ALU_3_3, + FIELD_fld_F2_S3_ALU_5_0, + FIELD_fld_F2_S3_ALU_9_0, + FIELD_fld_F2_S3_ALU_9_1, + FIELD_fld_F2_S3_ALU_9_2, + FIELD_fld_F2_S3_ALU_9_3, + FIELD_fld_F2_S3_ALU_9_7, + FIELD_fld_F2_S3_ALU_9_8, + FIELD_fld_F2_S3_ALU_9_9, + FIELD_fld_F3_S0_LdSt_0_0, + FIELD_fld_F3_S0_LdSt_12_0, + FIELD_fld_F3_S0_LdSt_12_11, + FIELD_fld_F3_S0_LdSt_12_12, + FIELD_fld_F3_S0_LdSt_12_4, + FIELD_fld_F3_S0_LdSt_12_8, + FIELD_fld_F3_S0_LdSt_13_9, + FIELD_fld_F3_S0_LdSt_15_15, + FIELD_fld_F3_S0_LdSt_25_1, + FIELD_fld_F3_S0_LdSt_25_11, + FIELD_fld_F3_S0_LdSt_25_12, + FIELD_fld_F3_S0_LdSt_25_13, + FIELD_fld_F3_S0_LdSt_25_14, + FIELD_fld_F3_S0_LdSt_25_15, + FIELD_fld_F3_S0_LdSt_25_16, + FIELD_fld_F3_S0_LdSt_25_17, + FIELD_fld_F3_S0_LdSt_25_18, + FIELD_fld_F3_S0_LdSt_25_19, + FIELD_fld_F3_S0_LdSt_25_20, + FIELD_fld_F3_S0_LdSt_25_4, + FIELD_fld_F3_S0_LdSt_25_8, + FIELD_fld_F3_S0_LdSt_25_9, + FIELD_fld_F3_S0_LdSt_3_0, + FIELD_fld_F3_S0_LdSt_7_4, + FIELD_fld_F3_S0_LdSt_7_5, + FIELD_fld_F3_S0_LdSt_7_7, + FIELD_fld_F3_S0_LdSt_8_0, + FIELD_fld_F3_S1_Ld_12_11, + FIELD_fld_F3_S1_Ld_12_2, + FIELD_fld_F3_S1_Ld_12_4, + FIELD_fld_F3_S1_Ld_12_8, + FIELD_fld_F3_S1_Ld_21_0, + FIELD_fld_F3_S1_Ld_21_10, + FIELD_fld_F3_S1_Ld_21_11, + FIELD_fld_F3_S1_Ld_21_12, + FIELD_fld_F3_S1_Ld_21_13, + FIELD_fld_F3_S1_Ld_21_15, + FIELD_fld_F3_S1_Ld_21_16, + FIELD_fld_F3_S1_Ld_21_17, + FIELD_fld_F3_S1_Ld_21_8, + FIELD_fld_F3_S1_Ld_21_9, + FIELD_fld_F3_S1_Ld_3_0, + FIELD_fld_F3_S1_Ld_3_2, + FIELD_fld_F3_S1_Ld_4_0, + FIELD_fld_F3_S1_Ld_4_3, + FIELD_fld_F3_S1_Ld_4_4, + FIELD_fld_F3_S1_Ld_7_0, + FIELD_fld_F3_S1_Ld_7_2, + FIELD_fld_F3_S1_Ld_7_4, + FIELD_fld_F3_S1_Ld_7_7, + FIELD_fld_F3_S2_Mul_11_8, + FIELD_fld_F3_S2_Mul_13_12, + FIELD_fld_F3_S2_Mul_13_7, + FIELD_fld_F3_S2_Mul_21_0, + FIELD_fld_F3_S2_Mul_21_12, + FIELD_fld_F3_S2_Mul_21_13, + FIELD_fld_F3_S2_Mul_21_14, + FIELD_fld_F3_S2_Mul_21_15, + FIELD_fld_F3_S2_Mul_21_16, + FIELD_fld_F3_S2_Mul_3_0, + FIELD_fld_F3_S2_Mul_3_3, + FIELD_fld_F3_S2_Mul_4_0, + FIELD_fld_F3_S2_Mul_7_4, + FIELD_fld_F3_S2_Mul_7_5, + FIELD_fld_F3_S3_ALU_13_9, + FIELD_fld_F3_S3_ALU_18_12, + FIELD_fld_F3_S3_ALU_18_13, + FIELD_fld_F3_S3_ALU_18_14, + FIELD_fld_F3_S3_ALU_18_18, + FIELD_fld_F3_S3_ALU_18_3, + FIELD_fld_F3_S3_ALU_18_7, + FIELD_fld_F3_S3_ALU_18_8, + FIELD_fld_F3_S3_ALU_28_12, + FIELD_fld_F3_S3_ALU_28_13, + FIELD_fld_F3_S3_ALU_28_14, + FIELD_fld_F3_S3_ALU_28_18, + FIELD_fld_F3_S3_ALU_28_19, + FIELD_fld_F3_S3_ALU_28_20, + FIELD_fld_F3_S3_ALU_28_21, + FIELD_fld_F3_S3_ALU_28_22, + FIELD_fld_F3_S3_ALU_28_25, + FIELD_fld_F3_S3_ALU_28_4, + FIELD_fld_F3_S3_ALU_28_8, + FIELD_fld_F3_S3_ALU_28_9, + FIELD_fld_F3_S3_ALU_3_0, + FIELD_fld_F3_S3_ALU_3_2, + FIELD_fld_F3_S3_ALU_3_3, + FIELD_fld_F3_S3_ALU_7_3, + FIELD_fld_F3_S3_ALU_7_6, + FIELD_fld_F3_S3_ALU_7_7, + FIELD_fld_F3_S3_ALU_8_0, + FIELD_fld_ivp_sem_vec_histogram_vbr, + FIELD_fld_ivp_sem_vec_histogram_vbs, + FIELD_fld_F3_S4_ALU_14_10, + FIELD_fld_F3_S4_ALU_23_0, + FIELD_fld_F3_S4_ALU_23_15, + FIELD_fld_F3_S4_ALU_23_18, + FIELD_fld_F3_S4_ALU_23_20, + FIELD_fld_F3_S4_ALU_9_5, + FIELD_fld_F3_S4_ALU_9_6, + FIELD_fld_bbe_selimm_S4, + FIELD_fld_bbe_shflimm_S4, + FIELD_fld_F4_S0_Ld_11_4, + FIELD_fld_F4_S0_Ld_11_8, + FIELD_fld_F4_S0_Ld_11_9, + FIELD_fld_F4_S0_Ld_12_0, + FIELD_fld_F4_S0_Ld_12_2, + FIELD_fld_F4_S0_Ld_12_4, + FIELD_fld_F4_S0_Ld_12_8, + FIELD_fld_F4_S0_Ld_15_15, + FIELD_fld_F4_S0_Ld_31_12, + FIELD_fld_F4_S0_Ld_31_13, + FIELD_fld_F4_S0_Ld_31_15, + FIELD_fld_F4_S0_Ld_31_16, + FIELD_fld_F4_S0_Ld_31_17, + FIELD_fld_F4_S0_Ld_31_18, + FIELD_fld_F4_S0_Ld_31_20, + FIELD_fld_F4_S0_Ld_31_27, + FIELD_fld_F4_S0_Ld_31_7, + FIELD_fld_F4_S0_Ld_31_8, + FIELD_fld_F4_S0_Ld_31_9, + FIELD_fld_F4_S0_Ld_3_0, + FIELD_fld_F4_S0_Ld_6_0, + FIELD_fld_F4_S0_Ld_6_4, + FIELD_fld_F4_S0_Ld_7_4, + FIELD_fld_F4_S1_Ld_12_10, + FIELD_fld_F4_S1_Ld_12_2, + FIELD_fld_F4_S1_Ld_12_4, + FIELD_fld_F4_S1_Ld_12_8, + FIELD_fld_F4_S1_Ld_23_0, + FIELD_fld_F4_S1_Ld_23_10, + FIELD_fld_F4_S1_Ld_23_11, + FIELD_fld_F4_S1_Ld_23_12, + FIELD_fld_F4_S1_Ld_23_13, + FIELD_fld_F4_S1_Ld_23_15, + FIELD_fld_F4_S1_Ld_23_16, + FIELD_fld_F4_S1_Ld_23_17, + FIELD_fld_F4_S1_Ld_23_8, + FIELD_fld_F4_S1_Ld_23_9, + FIELD_fld_F4_S1_Ld_3_0, + FIELD_fld_F4_S1_Ld_3_2, + FIELD_fld_F4_S1_Ld_4_0, + FIELD_fld_F4_S1_Ld_4_3, + FIELD_fld_F4_S1_Ld_4_4, + FIELD_fld_F4_S1_Ld_7_0, + FIELD_fld_F4_S1_Ld_7_2, + FIELD_fld_F4_S1_Ld_7_4, + FIELD_fld_F4_S1_Ld_7_6, + FIELD_fld_F4_S1_Ld_7_7, + FIELD_fld_F4_S2_Mul_32_26, + FIELD_fld_F4_S2_Mul_32_8, + FIELD_fld_F4_S2_Mul_3_0, + FIELD_fld_F4_S2_Mul_7_0, + FIELD_fld_ivp_sem_multiply_vq, + FIELD_fld_F4_S3_ALU_0_0, + FIELD_fld_F4_S3_ALU_14_10, + FIELD_fld_F4_S3_ALU_14_11, + FIELD_fld_F4_S3_ALU_14_12, + FIELD_fld_F4_S3_ALU_14_13, + FIELD_fld_F4_S3_ALU_14_14, + FIELD_fld_F4_S3_ALU_14_6, + FIELD_fld_F4_S3_ALU_14_8, + FIELD_fld_F4_S3_ALU_19_13, + FIELD_fld_F4_S3_ALU_19_6, + FIELD_fld_F4_S3_ALU_19_8, + FIELD_fld_F4_S3_ALU_24_12, + FIELD_fld_F4_S3_ALU_24_13, + FIELD_fld_F4_S3_ALU_24_18, + FIELD_fld_F4_S3_ALU_24_20, + FIELD_fld_F4_S3_ALU_24_21, + FIELD_fld_F4_S3_ALU_31_13, + FIELD_fld_F4_S3_ALU_31_19, + FIELD_fld_F4_S3_ALU_31_20, + FIELD_fld_F4_S3_ALU_31_23, + FIELD_fld_F4_S3_ALU_31_25, + FIELD_fld_F4_S3_ALU_31_26, + FIELD_fld_F4_S3_ALU_31_28, + FIELD_fld_F4_S3_ALU_31_7, + FIELD_fld_F4_S3_ALU_31_8, + FIELD_fld_F4_S3_ALU_3_0, + FIELD_fld_F4_S3_ALU_3_1, + FIELD_fld_F4_S3_ALU_3_2, + FIELD_fld_F4_S3_ALU_3_3, + FIELD_fld_F4_S3_ALU_6_0, + FIELD_fld_F4_S3_ALU_7_4, + FIELD_fld_F4_S3_ALU_7_5, + FIELD_fld_F4_S3_ALU_9_8, + FIELD_fld_F5_S0_Base_11_0, + FIELD_fld_F5_S0_Base_11_8, + FIELD_fld_F5_S0_Base_11_9, + FIELD_fld_F5_S0_Base_36_12, + FIELD_fld_F5_S0_Base_36_13, + FIELD_fld_F5_S0_Base_36_16, + FIELD_fld_F5_S0_Base_36_17, + FIELD_fld_F5_S0_Base_36_18, + FIELD_fld_F5_S0_Base_36_20, + FIELD_fld_F5_S0_Base_36_27, + FIELD_fld_F5_S0_Base_3_0, + FIELD_fld_F5_S0_Base_3_1, + FIELD_fld_F5_S0_Base_7_4, + FIELD_fld_F5_S1_Base_27_12, + FIELD_fld_F5_S1_Base_27_13, + FIELD_fld_F5_S1_Base_27_16, + FIELD_fld_F5_S1_Base_27_17, + FIELD_fld_F5_S1_Base_27_3, + FIELD_fld_F5_S1_Base_2_0, + FIELD_fld_F5_S1_Base_3_0, + FIELD_fld_F5_S1_Base_7_4, + FIELD_fld_F5_S2_Base_1_0, + FIELD_fld_F5_S2_Base_26_12, + FIELD_fld_F5_S2_Base_26_13, + FIELD_fld_F5_S2_Base_26_16, + FIELD_fld_F5_S2_Base_26_2, + FIELD_fld_F5_S2_Base_26_8, + FIELD_fld_F5_S2_Base_3_0, + FIELD_fld_F5_S2_Base_7_4, + FIELD_fld_F5_S3_Base_0_0, + FIELD_fld_F5_S3_Base_25_1, + FIELD_fld_F5_S3_Base_25_16, + FIELD_fld_F5_S3_Base_25_8, + FIELD_fld_F11_S0_Ld_1_0, + FIELD_fld_F11_S0_Ld_23_0, + FIELD_fld_F11_S0_Ld_23_12, + FIELD_fld_F11_S0_Ld_23_13, + FIELD_fld_F11_S0_Ld_23_16, + FIELD_fld_F11_S0_Ld_23_17, + FIELD_fld_F11_S0_Ld_23_20, + FIELD_fld_F11_S0_Ld_23_4, + FIELD_fld_F11_S0_Ld_3_0, + FIELD_fld_F11_S0_Ld_7_4, + FIELD_fld_F11_S1_ALU_12_10, + FIELD_fld_F11_S1_ALU_12_11, + FIELD_fld_F11_S1_ALU_12_12, + FIELD_fld_F11_S1_ALU_12_3, + FIELD_fld_F11_S1_ALU_12_4, + FIELD_fld_F11_S1_ALU_12_9, + FIELD_fld_F11_S1_ALU_15_13, + FIELD_fld_F11_S1_ALU_15_14, + FIELD_fld_F11_S1_ALU_15_15, + FIELD_fld_F11_S1_ALU_15_2, + FIELD_fld_F11_S1_ALU_22_0, + FIELD_fld_F11_S1_ALU_22_12, + FIELD_fld_F11_S1_ALU_22_13, + FIELD_fld_F11_S1_ALU_22_14, + FIELD_fld_F11_S1_ALU_22_16, + FIELD_fld_F11_S1_ALU_22_18, + FIELD_fld_F11_S1_ALU_3_0, + FIELD_fld_F11_S1_ALU_7_4, + FIELD_fld_ivp_sem_ld_st_vrul2, + FIELD_fld_F11_S2_Mul_11_8, + FIELD_fld_F11_S2_Mul_13_12, + FIELD_fld_F11_S2_Mul_13_7, + FIELD_fld_F11_S2_Mul_22_0, + FIELD_fld_F11_S2_Mul_22_12, + FIELD_fld_F11_S2_Mul_22_13, + FIELD_fld_F11_S2_Mul_22_14, + FIELD_fld_F11_S2_Mul_22_15, + FIELD_fld_F11_S2_Mul_22_16, + FIELD_fld_F11_S2_Mul_22_8, + FIELD_fld_F11_S2_Mul_3_0, + FIELD_fld_F11_S2_Mul_3_3, + FIELD_fld_F11_S2_Mul_4_0, + FIELD_fld_F11_S2_Mul_7_4, + FIELD_fld_F11_S2_Mul_7_5, + FIELD_fld_F11_S3_ALU_0_0, + FIELD_fld_F11_S3_ALU_14_10, + FIELD_fld_F11_S3_ALU_14_11, + FIELD_fld_F11_S3_ALU_14_13, + FIELD_fld_F11_S3_ALU_14_8, + FIELD_fld_F11_S3_ALU_25_1, + FIELD_fld_F11_S3_ALU_25_11, + FIELD_fld_F11_S3_ALU_25_13, + FIELD_fld_F11_S3_ALU_25_14, + FIELD_fld_F11_S3_ALU_25_15, + FIELD_fld_F11_S3_ALU_25_16, + FIELD_fld_F11_S3_ALU_25_17, + FIELD_fld_F11_S3_ALU_25_18, + FIELD_fld_F11_S3_ALU_25_22, + FIELD_fld_F11_S3_ALU_25_8, + FIELD_fld_F11_S3_ALU_3_0, + FIELD_fld_F11_S3_ALU_3_1, + FIELD_fld_F11_S3_ALU_7_0, + FIELD_fld_F11_S3_ALU_7_4, + FIELD_fld_F11_S3_ALU_9_8, + FIELD_fld_F11_S3_ALU_9_9, + FIELD_fld_F11_S4_ALU_24_0, + FIELD_fld_F11_S4_ALU_24_15, + FIELD_fld_F11_S4_ALU_24_18, + FIELD_fld_F11_S4_ALU_9_5, + FIELD_fld_N1_S0_LdSt_12_0, + FIELD_fld_N1_S0_LdSt_12_12, + FIELD_fld_N1_S0_LdSt_12_2, + FIELD_fld_N1_S0_LdSt_12_4, + FIELD_fld_N1_S0_LdSt_12_8, + FIELD_fld_N1_S0_LdSt_15_15, + FIELD_fld_N1_S0_LdSt_1_0, + FIELD_fld_N1_S0_LdSt_26_12, + FIELD_fld_N1_S0_LdSt_26_13, + FIELD_fld_N1_S0_LdSt_26_15, + FIELD_fld_N1_S0_LdSt_26_16, + FIELD_fld_N1_S0_LdSt_26_17, + FIELD_fld_N1_S0_LdSt_26_18, + FIELD_fld_N1_S0_LdSt_26_2, + FIELD_fld_N1_S0_LdSt_26_20, + FIELD_fld_N1_S0_LdSt_26_4, + FIELD_fld_N1_S0_LdSt_26_8, + FIELD_fld_N1_S0_LdSt_26_9, + FIELD_fld_N1_S0_LdSt_3_0, + FIELD_fld_N1_S0_LdSt_3_2, + FIELD_fld_N1_S0_LdSt_7_2, + FIELD_fld_N1_S0_LdSt_7_4, + FIELD_fld_N1_S0_LdSt_7_5, + FIELD_fld_N1_S0_LdSt_7_6, + FIELD_fld_N1_S1_None_3_0, + FIELD_fld_N1_S2_Mul_0_0, + FIELD_fld_N1_S2_Mul_13_9, + FIELD_fld_N1_S2_Mul_18_14, + FIELD_fld_N1_S2_Mul_18_6, + FIELD_fld_N1_S2_Mul_18_9, + FIELD_fld_N1_S2_Mul_25_1, + FIELD_fld_N1_S2_Mul_25_12, + FIELD_fld_N1_S2_Mul_25_14, + FIELD_fld_N1_S2_Mul_25_19, + FIELD_fld_N1_S2_Mul_25_21, + FIELD_fld_N1_S2_Mul_3_0, + FIELD_fld_N1_S2_Mul_3_3, + FIELD_fld_N1_S2_Mul_7_4, + FIELD_fld_N1_S2_Mul_8_4, + FIELD_fld_N1_S2_Mul_8_8, + FIELD_fld_N2_S0_LdSt_12_0, + FIELD_fld_N2_S0_LdSt_12_10, + FIELD_fld_N2_S0_LdSt_12_11, + FIELD_fld_N2_S0_LdSt_12_12, + FIELD_fld_N2_S0_LdSt_12_4, + FIELD_fld_N2_S0_LdSt_12_8, + FIELD_fld_N2_S0_LdSt_13_11, + FIELD_fld_N2_S0_LdSt_15_15, + FIELD_fld_N2_S0_LdSt_29_10, + FIELD_fld_N2_S0_LdSt_29_11, + FIELD_fld_N2_S0_LdSt_29_12, + FIELD_fld_N2_S0_LdSt_29_13, + FIELD_fld_N2_S0_LdSt_29_14, + FIELD_fld_N2_S0_LdSt_29_15, + FIELD_fld_N2_S0_LdSt_29_16, + FIELD_fld_N2_S0_LdSt_29_17, + FIELD_fld_N2_S0_LdSt_29_18, + FIELD_fld_N2_S0_LdSt_29_20, + FIELD_fld_N2_S0_LdSt_29_5, + FIELD_fld_N2_S0_LdSt_29_8, + FIELD_fld_N2_S0_LdSt_3_0, + FIELD_fld_N2_S0_LdSt_4_0, + FIELD_fld_N2_S0_LdSt_4_4, + FIELD_fld_N2_S0_LdSt_7_4, + FIELD_fld_N2_S0_LdSt_7_6, + FIELD_fld_N2_S0_LdSt_8_0, + FIELD_fld_N2_S0_LdSt_8_4, + FIELD_fld_N2_S0_LdSt_9_5, + FIELD_fld_N2_S0_LdSt_9_6, + FIELD_fld_N2_S1_Ld_12_10, + FIELD_fld_N2_S1_Ld_12_2, + FIELD_fld_N2_S1_Ld_12_4, + FIELD_fld_N2_S1_Ld_12_8, + FIELD_fld_N2_S1_Ld_1_0, + FIELD_fld_N2_S1_Ld_26_10, + FIELD_fld_N2_S1_Ld_26_11, + FIELD_fld_N2_S1_Ld_26_12, + FIELD_fld_N2_S1_Ld_26_13, + FIELD_fld_N2_S1_Ld_26_15, + FIELD_fld_N2_S1_Ld_26_16, + FIELD_fld_N2_S1_Ld_26_17, + FIELD_fld_N2_S1_Ld_26_2, + FIELD_fld_N2_S1_Ld_26_8, + FIELD_fld_N2_S1_Ld_26_9, + FIELD_fld_N2_S1_Ld_3_0, + FIELD_fld_N2_S1_Ld_3_2, + FIELD_fld_N2_S1_Ld_4_0, + FIELD_fld_N2_S1_Ld_4_3, + FIELD_fld_N2_S1_Ld_4_4, + FIELD_fld_N2_S1_Ld_7_0, + FIELD_fld_N2_S1_Ld_7_2, + FIELD_fld_N2_S1_Ld_7_4, + FIELD_fld_N2_S1_Ld_7_6, + FIELD_fld_N2_S1_Ld_7_7, + FIELD_fld_N0_S0_LdSt_12_0, + FIELD_fld_N0_S0_LdSt_12_12, + FIELD_fld_N0_S0_LdSt_12_2, + FIELD_fld_N0_S0_LdSt_12_4, + FIELD_fld_N0_S0_LdSt_12_8, + FIELD_fld_N0_S0_LdSt_22_0, + FIELD_fld_N0_S0_LdSt_22_12, + FIELD_fld_N0_S0_LdSt_22_13, + FIELD_fld_N0_S0_LdSt_22_15, + FIELD_fld_N0_S0_LdSt_22_16, + FIELD_fld_N0_S0_LdSt_22_17, + FIELD_fld_N0_S0_LdSt_3_0, + FIELD_fld_N0_S0_LdSt_7_4, + FIELD_fld_N0_S0_LdSt_7_5, + FIELD_fld_N0_S0_LdSt_7_6, + FIELD_fld_N0_S1_None_2_0, + FIELD_fld_N0_S2_None_2_0, + FIELD_fld_N0_S3_ALU_14_10, + FIELD_fld_N0_S3_ALU_14_13, + FIELD_fld_N0_S3_ALU_14_14, + FIELD_fld_N0_S3_ALU_14_5, + FIELD_fld_N0_S3_ALU_19_12, + FIELD_fld_N0_S3_ALU_19_13, + FIELD_fld_N0_S3_ALU_19_15, + FIELD_fld_N0_S3_ALU_27_12, + FIELD_fld_N0_S3_ALU_27_13, + FIELD_fld_N0_S3_ALU_27_15, + FIELD_fld_N0_S3_ALU_27_16, + FIELD_fld_N0_S3_ALU_27_19, + FIELD_fld_N0_S3_ALU_27_20, + FIELD_fld_N0_S3_ALU_27_22, + FIELD_fld_N0_S3_ALU_27_23, + FIELD_fld_N0_S3_ALU_27_3, + FIELD_fld_N0_S3_ALU_2_0, + FIELD_fld_N0_S3_ALU_3_0, + FIELD_fld_N0_S3_ALU_7_0, + FIELD_fld_N0_S3_ALU_9_0, + FIELD_fld_N0_S3_ALU_9_3, + FIELD_fld_N0_S3_ALU_9_4, + FIELD_fld_N0_S3_ALU_9_5, + FIELD_fld_N0_S3_ALU_9_6, + FIELD_fld_N0_S3_ALU_9_7, + FIELD_fld_N0_S3_ALU_9_9, + FIELD_fld_MTK_AndPOPC_c, + FIELD_fld_MTK_AndPOPC_inB, + FIELD_fld_MTK_AndPOPC_inA, + FIELD_fld_MTK_AndPOPC_oData, + FIELD_fld_F11_S4_ALU_24_16, + FIELD_fld_F3_S4_ALU_23_16, + FIELD_fld_iq_tie2apb_inq0_pop_qdata, + FIELD_fld_iq_tie2apb_inq0_is_ready_is_ready, + FIELD_fld_Inst_11_8, + FIELD_fld_iq_tie2apb_inq0_nonblocking_peek_success, + FIELD_fld_iq_tie2apb_inq0_nonblocking_peek_qdata, + FIELD_fld_iq_tie2apb_inq0_nonblocking_pop_success, + FIELD_fld_iq_tie2apb_inq0_nonblocking_pop_qdata, + FIELD_fld_Inst_23_8, + FIELD_fld_iq_tie2apb_inq0_blocking_peek_qdata, + FIELD_fld_Inst_23_12, + FIELD_fld_oq_tie2apb_outq0_push_read_qaddr, + FIELD_fld_oq_tie2apb_outq0_push_read_qdata, + FIELD_fld_oq_tie2apb_outq0_push_write_qaddr, + FIELD_fld_oq_tie2apb_outq0_push_write_qdata, + FIELD_fld_oq_tie2apb_outq0_is_ready_is_ready, + FIELD_fld_Inst_3_0, + FIELD_fld_Inst_23_16, + FIELD_fld_oq_tie2apb_outq0_nonblocking_push_read_success, + FIELD_fld_oq_tie2apb_outq0_nonblocking_push_read_qaddr, + FIELD_fld_oq_tie2apb_outq0_nonblocking_push_read_qdata, + FIELD_fld_oq_tie2apb_outq0_nonblocking_push_write_success, + FIELD_fld_oq_tie2apb_outq0_nonblocking_push_write_qaddr, + FIELD_fld_oq_tie2apb_outq0_nonblocking_push_write_qdata, + FIELD__ar0, + FIELD__ar4, + FIELD__ar8, + FIELD__ar12, + FIELD__bt16, + FIELD__bs16, + FIELD__br16, + FIELD__brall +}; + + +/* Functional units. */ + +#define funcUnits 0 + + +/* Register files. */ + +enum xtensa_regfile_id { + REGFILE_AR, + REGFILE_BR, + REGFILE_vec, + REGFILE_vbool, + REGFILE_valign, + REGFILE_wvec, + REGFILE_gvr, + REGFILE_BR2, + REGFILE_BR4, + REGFILE_BR8, + REGFILE_BR16 +}; + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", REGFILE_AR, 32, 32 }, + { "BR", "b", REGFILE_BR, 1, 16 }, + { "vec", "v", REGFILE_vec, 512, 32 }, + { "vbool", "vb", REGFILE_vbool, 64, 8 }, + { "valign", "u", REGFILE_valign, 512, 4 }, + { "wvec", "wv", REGFILE_wvec, 1536, 4 }, + { "gvr", "gr", REGFILE_gvr, 512, 4 }, + { "BR2", "b", REGFILE_BR, 2, 8 }, + { "BR4", "b", REGFILE_BR, 4, 4 }, + { "BR8", "b", REGFILE_BR, 8, 2 }, + { "BR16", "b", REGFILE_BR, 16, 1 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "ERI_RD_Out", 14, 0, 0, 'o' }, + { "ERI_RD_In", 32, 0, 1, 'i' }, + { "ERI_RD_Rdy", 1, 0, 0, 'i' }, + { "ERI_WR_Out", 46, 0, 2, 'o' }, + { "ERI_WR_In", 1, 0, 3, 'i' }, + { "iq_tie2apb_inq0_Empty", 1, 0, 4, 'i' }, + { "iq_tie2apb_inq0", 32, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 4, 'i' }, + { "iq_tie2apb_inq0_NOTRDY", 1, 0, 4, 'i' }, + { "iq_tie2apb_inq0_KILL", 1, 0, 4, 'o' }, + { "oq_tie2apb_outq0_Full", 1, 0, 5, 'i' }, + { "oq_tie2apb_outq0", 65, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 5, 'o' }, + { "oq_tie2apb_outq0_NOTRDY", 1, 0, 5, 'i' }, + { "oq_tie2apb_outq0_KILL", 1, 0, 5, 'o' } +}; + +enum xtensa_interface_id { + INTERFACE_ERI_RD_Out, + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Rdy, + INTERFACE_ERI_WR_Out, + INTERFACE_ERI_WR_In, + INTERFACE_iq_tie2apb_inq0_Empty, + INTERFACE_iq_tie2apb_inq0, + INTERFACE_iq_tie2apb_inq0_NOTRDY, + INTERFACE_iq_tie2apb_inq0_KILL, + INTERFACE_oq_tie2apb_outq0_Full, + INTERFACE_oq_tie2apb_outq0, + INTERFACE_oq_tie2apb_outq0_NOTRDY, + INTERFACE_oq_tie2apb_outq0_KILL +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table imm1_2N_tab */ +static const unsigned CONST_TBL_imm1_2N_tab_0[] = { + 0x1 & 0x7f, + 0x2 & 0x7f, + 0x4 & 0x7f, + 0x8 & 0x7f, + 0x10 & 0x7f, + 0x20 & 0x7f, + 0x40 & 0x7f, + 0, + 0 +}; + +/* constant table tab_selimm_7b */ +static const unsigned CONST_TBL_tab_selimm_7b_0[] = { + 0 & 0x7f, + 0x1 & 0x7f, + 0x2 & 0x7f, + 0x3 & 0x7f, + 0x8 & 0x7f, + 0x9 & 0x7f, + 0xa & 0x7f, + 0xb & 0x7f, + 0x10 & 0x7f, + 0x11 & 0x7f, + 0x20 & 0x7f, + 0x21 & 0x7f, + 0x22 & 0x7f, + 0x23 & 0x7f, + 0x3b & 0x7f, + 0x3c & 0x7f, + 0x3d & 0x7f, + 0x3e & 0x7f, + 0x3f & 0x7f, + 0x40 & 0x7f, + 0x41 & 0x7f, + 0x42 & 0x7f, + 0x43 & 0x7f, + 0x44 & 0x7f, + 0x45 & 0x7f, + 0x46 & 0x7f, + 0x47 & 0x7f, + 0x48 & 0x7f, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table tab_shflimm_7b */ +static const unsigned CONST_TBL_tab_shflimm_7b_0[] = { + 0x8 & 0x7f, + 0x1e & 0x7f, + 0 +}; + +/* constant table imm5_19_tab */ +static const unsigned CONST_TBL_imm5_19_tab_0[] = { + 0, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0x10, + 0x11, + 0x12, + 0x13, + 0x14, + 0x15, + 0x16, + 0x17, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table imm6_39_tab */ +static const unsigned CONST_TBL_imm6_39_tab_0[] = { + 0, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0x10, + 0x11, + 0x12, + 0x13, + 0x14, + 0x15, + 0x16, + 0x17, + 0x18, + 0x19, + 0x1a, + 0x1b, + 0x1c, + 0x1d, + 0x1e, + 0x1f, + 0x20, + 0x21, + 0x22, + 0x23, + 0x24, + 0x25, + 0x26, + 0x27, + 0x28, + 0x29, + 0x2a, + 0x2b, + 0x2c, + 0x2d, + 0x2e, + 0x2f, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table imm7_79_tab */ +static const unsigned CONST_TBL_imm7_79_tab_0[] = { + 0, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0x10, + 0x11, + 0x12, + 0x13, + 0x14, + 0x15, + 0x16, + 0x17, + 0x18, + 0x19, + 0x1a, + 0x1b, + 0x1c, + 0x1d, + 0x1e, + 0x1f, + 0x20, + 0x21, + 0x22, + 0x23, + 0x24, + 0x25, + 0x26, + 0x27, + 0x28, + 0x29, + 0x2a, + 0x2b, + 0x2c, + 0x2d, + 0x2e, + 0x2f, + 0x30, + 0x31, + 0x32, + 0x33, + 0x34, + 0x35, + 0x36, + 0x37, + 0x38, + 0x39, + 0x3a, + 0x3b, + 0x3c, + 0x3d, + 0x3e, + 0x3f, + 0x40, + 0x41, + 0x42, + 0x43, + 0x44, + 0x45, + 0x46, + 0x47, + 0x48, + 0x49, + 0x4a, + 0x4b, + 0x4c, + 0x4d, + 0x4e, + 0x4f, + 0x50, + 0x51, + 0x52, + 0x53, + 0x54, + 0x55, + 0x56, + 0x57, + 0x58, + 0x59, + 0x5a, + 0x5b, + 0x5c, + 0x5d, + 0x5e, + 0x5f, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table0 */ +static const unsigned CONST_TBL_xd_seli_table0_0[] = { + 0x60a10182, + 0x80e18284, + 0xa1220386, + 0xc1628488, + 0x42648890, + 0xc3668c98, + 0x446890a0, + 0x1e3868c, + 0x28301fbe, + 0x7ef9ebc, + 0xe7af1dba, + 0xc76e9cb8, + 0x466c98b0, + 0xc56a94a8, + 0x446890a0, + 0x82e58a94, + 0x80a10080, + 0xa0e18182, + 0xc0e18080, + 0xe1220182, + 0x1628284, + 0x1220080, + 0x21628182, + 0x41a30284, + 0x61e38386, + 0x60608080, + 0x80a10182, + 0xa0e18284, + 0x80608080, + 0xc0e18284, + 0x40608080, + 0xc1628488, + 0x28300080, + 0x2c3810a0, + 0x48300080, + 0x68708182, + 0x48708080, + 0x608080, + 0x46890a0, + 0x608080, + 0x40e18284, + 0x40608080, + 0x40608080, + 0x446890a0, + 0x40608080, + 0xc1628488, + 0x40608080, + 0x28300080, + 0x608080, + 0x40608080, + 0x40608080, + 0x40608080, + 0x40608080, + 0x40608080, + 0x40608080, + 0x40608080, + 0x40608080, + 0x40608080, + 0x446890a0, + 0x28206000, + 0x2c287020, + 0x4840a000, + 0x5860e081, + 0x80c10100, + 0x90e14181, + 0x5080c101, + 0x3850603f, + 0x70c14203, + 0x180fdf3d, + 0x9101c305, + 0xf7cf5e3b, + 0xb1424407, + 0xd78edd39, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table1 */ +static const unsigned CONST_TBL_xd_seli_table1_0[] = { + 0x8a122038, + 0x8c162848, + 0x8e1a3058, + 0x901e3868, + 0x982e58a9, + 0xa03e78e9, + 0xa84e992a, + 0x94264889, + 0xc68b121c, + 0xc4870a0c, + 0xc28301fb, + 0xc07ef9eb, + 0xb86ed9ab, + 0xb05eb96a, + 0xa84e992a, + 0x9c3668c9, + 0x901a3048, + 0x921e3858, + 0x98264868, + 0x9a2a5078, + 0x9c2e5889, + 0xa0326089, + 0xa2366899, + 0xa43a70a9, + 0xa63e78b9, + 0x8c122038, + 0x8e162848, + 0x901a3058, + 0x90162848, + 0x941e3868, + 0x900e1828, + 0x981e3868, + 0x84870818, + 0xa4c7891a, + 0x888b1028, + 0x8a8f1838, + 0x888f1828, + 0x84870a0c, + 0xa4c78b0e, + 0x88870a0c, + 0x8c8f1a2c, + 0x888f1a2c, + 0xc00e1828, + 0xe04e992a, + 0xc00e1828, + 0xc81e3868, + 0xc80e1828, + 0xc68b121c, + 0xc4870a0c, + 0xc2830028, + 0xc00e1828, + 0x880e1828, + 0x880e1828, + 0x880e1828, + 0x880e1828, + 0x880e1828, + 0x880e1828, + 0x880e1828, + 0xa84e992a, + 0x4860e10, + 0x24c68f12, + 0x88c1a20, + 0x898e1e28, + 0x101c3050, + 0x911e3458, + 0x9101c30, + 0x478d1624, + 0xb142440, + 0x45890e14, + 0xd182c50, + 0x43850603, + 0xf1c3460, + 0x4180fdf3, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table2 */ +static const unsigned CONST_TBL_xd_seli_table2_0[] = { + 0x78e1a305, + 0x8901e386, + 0x99222407, + 0xa9426488, + 0xe9c3668c, + 0x2a446890, + 0x6ac56a94, + 0xc982e58a, + 0x5ca93223, + 0x4c88f1a2, + 0x3c68b121, + 0x2c4870a0, + 0xebc76e9c, + 0xab466c98, + 0x6ac56a94, + 0xa03e78e, + 0xc982a508, + 0xd9a2e589, + 0x2a43e78c, + 0x3a64280d, + 0x4a84688e, + 0x8b052a10, + 0x9b256a91, + 0xab45ab12, + 0xbb65eb93, + 0x9921e386, + 0xa9422407, + 0xb9626488, + 0xc9826488, + 0xe9c2e58a, + 0xa9426488, + 0xe9c3668c, + 0x3868b102, + 0x3a6cb912, + 0x68c93204, + 0x78e97285, + 0x68c97284, + 0x2c40e182, + 0x2e44e992, + 0x4c816284, + 0x6cc1e386, + 0x6cc16284, + 0x2c4870a0, + 0x2e4c78b0, + 0x2c4870a0, + 0x6cc972a4, + 0x6cc972a4, + 0x5ca93223, + 0x4c88f1a2, + 0x3c68b121, + 0x2c4870a0, + 0x1c283004, + 0xc016284, + 0x68c16284, + 0x68c16284, + 0x68c16284, + 0x68c16284, + 0x68c16284, + 0x6ac56a94, + 0x3068a162, + 0x326ca972, + 0x60c942a4, + 0x68d962e4, + 0xd182c509, + 0xd992e549, + 0x70d182c5, + 0x64b95264, + 0x80f1c346, + 0x549911e3, + 0x911203c7, + 0x4478d162, + 0xa1324448, + 0x345890e1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table3 */ +static const unsigned CONST_TBL_xd_seli_table3_0[] = { + 0x9922240, + 0x8a942648, + 0xb962a50, + 0x8c982e58, + 0x90a03e78, + 0x94a84e99, + 0x98b05eb9, + 0x8e9c3668, + 0x27ce9b32, + 0xa6cc972a, + 0x25ca9322, + 0xa4c88f1a, + 0xa0c07ef9, + 0x9cb86ed9, + 0x98b05eb9, + 0x92a44689, + 0x10a03a70, + 0x91a23e78, + 0x98b056a9, + 0x19b25ab1, + 0x9ab45eb9, + 0x20c072e1, + 0xa1c276e9, + 0x22c47af1, + 0xa3c67ef9, + 0x8c982a50, + 0xd9a2e58, + 0x8e9c3260, + 0x90a03668, + 0x92a43e78, + 0x90a02e58, + 0x94a83e78, + 0x4888f18, + 0x14a8cf99, + 0x8909b30, + 0x89929f38, + 0x88909f38, + 0x84888f1a, + 0x94a8cf9b, + 0x8890972a, + 0x8a949f3a, + 0x88909f3a, + 0x84888f1a, + 0x94a8cf9b, + 0x88908f1a, + 0x8c989f3a, + 0x88909f3a, + 0x27ce9b32, + 0xa6cc972a, + 0x25ca9322, + 0xa4c88f1a, + 0x23c68b12, + 0xa2c4870a, + 0x21c28300, + 0xa0c01e38, + 0xa8d01e38, + 0x88901e38, + 0x88901e38, + 0x98b05eb9, + 0x64088e1e, + 0x7428ce9f, + 0xa8109c3a, + 0xe8919e3e, + 0x11203c70, + 0x51a13e74, + 0xc911203c, + 0x684f9d36, + 0x4a132444, + 0xe74d992e, + 0xcb15284c, + 0x664b9526, + 0x4c172c54, + 0xe549911e, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table4 */ +static const unsigned CONST_TBL_xd_seli_table4_0[] = { + 0x60b962a5, + 0x68c982e5, + 0x70d9a326, + 0x78e9c366, + 0x992a4468, + 0xb96ac56a, + 0xd9ab466c, + 0x890a03e7, + 0x529d2a34, + 0x4a8d09f3, + 0x427ce9b3, + 0x3a6cc972, + 0x1a2c4870, + 0xf9ebc76e, + 0xd9ab466c, + 0xa94a84e9, + 0xb14a84a9, + 0xb95aa4e9, + 0x9ebc6ed, + 0x11fbe72e, + 0x1a0c076e, + 0x628d0932, + 0x6a9d2972, + 0x72ad49b3, + 0x7abd69f3, + 0x80f9e366, + 0x890a03a7, + 0x911a23e7, + 0xa94a8468, + 0xb96ac4e9, + 0x992a4468, + 0xb96ac56a, + 0x2858a932, + 0xa95aad3a, + 0x50a94a34, + 0x58b96a74, + 0x58a94a74, + 0x2a4c8162, + 0xab4e856a, + 0x4a8d0264, + 0x5aad42e5, + 0x5aad4264, + 0x3868c162, + 0xb96ac56a, + 0x58a94264, + 0x78e9c366, + 0x58a94264, + 0x529d2a34, + 0x4a8d09f3, + 0x427ce9b3, + 0x3a6cc972, + 0x325ca932, + 0x2a4c88f1, + 0x223c68b1, + 0x1a2c4870, + 0x5aad4a74, + 0x58a94264, + 0x58a94264, + 0xd9ab466c, + 0x2e50a922, + 0xaf52ad2a, + 0x5aa14a44, + 0x5ea95a64, + 0xb15284c9, + 0xb55a94e9, + 0x5cb15284, + 0x56a53a54, + 0x64c172c5, + 0x4e951a13, + 0x6cd19305, + 0x4684f9d3, + 0x74e1b346, + 0x3e74d992, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table5 */ +static const unsigned CONST_TBL_xd_seli_table5_0[] = { + 0xa70d9a32, + 0xe78e9c36, + 0x280f9e3a, + 0x6890a03e, + 0x6a94a84e, + 0x6c98b05e, + 0x6e9cb86e, + 0xe992a446, + 0x362bd6ab, + 0xf5aad4a7, + 0xb529d2a3, + 0x74a8d09f, + 0x72a4c88f, + 0x70a0c07e, + 0x6e9cb86e, + 0xeb96ac56, + 0xad18b05a, + 0xed99b25e, + 0xf3a4c887, + 0x3425ca8b, + 0x74a6cc8f, + 0x3a30e0b3, + 0x7ab1e2b7, + 0xbb32e4bb, + 0xfbb3e6bf, + 0xe992a442, + 0x2a13a646, + 0x6a94a84a, + 0x6c98b056, + 0xed9ab45e, + 0x6c98b04e, + 0x6e9cb85e, + 0xb3068c97, + 0xbb16acd7, + 0x360c98ab, + 0x768d9aaf, + 0x768c98af, + 0xe3868c97, + 0xeb96acd7, + 0x668c98a7, + 0xe78e9caf, + 0x668c98af, + 0x72a4c81e, + 0x7ab4e85e, + 0x74a8d02e, + 0x76acd83e, + 0x76acd82e, + 0x362bd6ab, + 0xf5aad4a7, + 0xb529d2a3, + 0x74a8d09f, + 0x3427ce9b, + 0xf3a6cc97, + 0xb325ca93, + 0x72a4c88f, + 0x76acd8af, + 0x668c982e, + 0x668c982e, + 0x6e9cb86e, + 0xa3660c96, + 0xab762cd6, + 0x46ac18ac, + 0x66ec99ae, + 0xcd19305c, + 0xed59b15e, + 0x86cd1930, + 0x566c57ad, + 0xc74e1b34, + 0x15eb55a9, + 0x7cf1d38, + 0xd56a53a5, + 0x48501f3c, + 0x94e951a1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table6 */ +static const unsigned CONST_TBL_xd_seli_table6_0[] = { + 0x4280f9e3, + 0x46890a03, + 0x4a911a24, + 0x4e992a44, + 0x5eb96ac5, + 0x6ed9ab46, + 0x7ef9ebc7, + 0x56a94a84, + 0xbb72ddab, + 0xb76acd8a, + 0xb362bd6a, + 0xaf5aad4a, + 0x9f3a6cc9, + 0x8f1a2c48, + 0x7ef9ebc7, + 0x66c98b05, + 0x7af1cb86, + 0x7ef9dba6, + 0xb76aad49, + 0xbb72bd6a, + 0xbf7acd8a, + 0xf3e38f0d, + 0xf7eb9f2d, + 0xfbf3af4d, + 0xfffbbf6d, + 0x5ab15aa4, + 0x5eb96ac5, + 0x62c17ae5, + 0x76e9cb86, + 0x7ef9ebc6, + 0x6ed9ab46, + 0x7ef9ebc7, + 0x9f3878e9, + 0xdfb97aed, + 0xbb70e9cb, + 0xbf78f9eb, + 0xbf78e9cb, + 0x9f3a6cc1, + 0xdfbb6ec5, + 0xb76acd83, + 0xbf7aedc3, + 0xbf7aedc3, + 0x9f3a6cc9, + 0xdfbb6ecd, + 0xaf5aad4a, + 0xbf7aedcb, + 0xbf7aedcb, + 0xbb72ddab, + 0xb76acd8a, + 0xb362bd6a, + 0xaf5aad4a, + 0xab529d2a, + 0xa74a8d09, + 0xa3427ce9, + 0x9f3a6cc9, + 0xbf7aedcb, + 0x3e78e9c3, + 0x3e78e9c3, + 0x7ef9ebc7, + 0x9e3e70e9, + 0xdebf72ed, + 0xbc7ae1cb, + 0xbe7ee9db, + 0x7cf1d386, + 0x7ef5db96, + 0x407cf1d3, + 0xbd76e5bb, + 0x448501f3, + 0xb96ed59b, + 0x488d1214, + 0xb566c57a, + 0x4c952234, + 0xb15eb55a, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table7 */ +static const unsigned CONST_TBL_xd_seli_table7_0[] = { + 0x64a911a2, + 0x84e992a4, + 0xa52a13a6, + 0xc56a94a8, + 0x466c98b0, + 0xc76e9cb8, + 0x4870a0c0, + 0x5eb96ac, + 0x2c382fde, + 0xbf7aedc, + 0xebb72dda, + 0xcb76acd8, + 0x4a74a8d0, + 0xc972a4c8, + 0x4870a0c0, + 0x86ed9ab4, + 0x88b120c0, + 0xa8f1a1c2, + 0xccf9b0e0, + 0xed3a31e2, + 0xd7ab2e4, + 0x1220080, + 0x21628182, + 0x41a30284, + 0x61e38386, + 0x666c98b0, + 0x86ad19b2, + 0xa6ed9ab4, + 0x8870a0c0, + 0xc8f1a2c4, + 0x4870a0c0, + 0xc972a4c8, + 0x2a340890, + 0x2e3c18b0, + 0x4c3810a0, + 0x6c7891a2, + 0x4c7890a0, + 0x2648890, + 0x66c98b0, + 0x46890a0, + 0x44e992a4, + 0x446890a0, + 0x42648890, + 0x466c98b0, + 0x446890a0, + 0xc56a94a8, + 0x446890a0, + 0x2c382fde, + 0xbf7aedc, + 0xebb72dda, + 0xcb76acd8, + 0xab362bd6, + 0x8af5aad4, + 0x6ab529d2, + 0x4a74a8d0, + 0x4c78b0e0, + 0x446890a0, + 0x4870a0c0, + 0x4c78b0e0, + 0x2a246810, + 0x2e2c7830, + 0x4c48b020, + 0x5c68f0a1, + 0x88d12140, + 0x98f161c1, + 0x5488d121, + 0x3c58705f, + 0x74c95223, + 0x1c17ef5d, + 0x9509d325, + 0xfbd76e5b, + 0xb54a5427, + 0xdb96ed59, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table8 */ +static const unsigned CONST_TBL_xd_seli_table8_0[] = { + 0xaa52a13a, + 0xac56a94a, + 0xae5ab15a, + 0xb05eb96a, + 0xb86ed9ab, + 0xc07ef9eb, + 0xc88f1a2c, + 0xb466c98b, + 0xe6cb931e, + 0xe4c78b0e, + 0xe2c382fd, + 0xe0bf7aed, + 0xd8af5aad, + 0xd09f3a6c, + 0xc88f1a2c, + 0xbc76e9cb, + 0xd09b324c, + 0xd29f3a5c, + 0xf8e7cb6e, + 0xfaebd37e, + 0xfcefdb8f, + 0xa0326089, + 0xa2366899, + 0xa43a70a9, + 0xa63e78b9, + 0xbc72e1bb, + 0xbe76e9cb, + 0xc07af1db, + 0xd0972a4c, + 0xd49f3a6c, + 0xd08f1a2c, + 0xd89f3a6c, + 0x94a74899, + 0xb4e7c99b, + 0xa8cb912a, + 0xaacf993a, + 0xa8cf992a, + 0x94a74a8d, + 0xb4e7cb8f, + 0xa8c78b0e, + 0xaccf9b2e, + 0xa8cf9b2e, + 0xd02e58a9, + 0xf06ed9ab, + 0xe04e992a, + 0xe85eb96a, + 0xe84e992a, + 0xe6cb931e, + 0xe4c78b0e, + 0xe2c382fd, + 0xe0bf7aed, + 0xdebb72dd, + 0xdcb76acd, + 0xdab362bd, + 0xd8af5aad, + 0xe8cf9b2e, + 0xa84e992a, + 0xc88f1a2c, + 0xe8cf9b2e, + 0x14a64e91, + 0x34e6cf93, + 0x28cc9b22, + 0xa9ce9f2a, + 0x509d3254, + 0xd19f365c, + 0x29509d32, + 0x67cd9726, + 0x2b54a542, + 0x65c98f16, + 0x2d58ad52, + 0x63c58705, + 0x2f5cb562, + 0x61c17ef5, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table9 */ +static const unsigned CONST_TBL_xd_seli_table9_0[] = { + 0x7ae5ab15, + 0x8b05eb96, + 0x9b262c17, + 0xab466c98, + 0xebc76e9c, + 0x2c4870a0, + 0x6cc972a4, + 0xcb86ed9a, + 0x5ead3a33, + 0x4e8cf9b2, + 0x3e6cb931, + 0x2e4c78b0, + 0xedcb76ac, + 0xad4a74a8, + 0x6cc972a4, + 0xc07ef9e, + 0xcd8ab528, + 0xddaaf5a9, + 0x284fffbc, + 0x3860203d, + 0x488060be, + 0x8b052a10, + 0x9b256a91, + 0xab45ab12, + 0xbb65eb93, + 0x1c27ef9e, + 0x2c48301f, + 0x3c6870a0, + 0xcd8a74a8, + 0xedcaf5aa, + 0xad4a74a8, + 0xedcb76ac, + 0xb96ab50a, + 0xbb6ebd1a, + 0x6acd3a14, + 0x7aed7a95, + 0x6acd7a94, + 0xad42e58a, + 0xaf46ed9a, + 0x4e856a94, + 0x6ec5eb96, + 0x6ec56a94, + 0xad4a74a8, + 0xaf4e7cb8, + 0x2e4c78b0, + 0x6ecd7ab4, + 0x6ecd7ab4, + 0x5ead3a33, + 0x4e8cf9b2, + 0x3e6cb931, + 0x2e4c78b0, + 0x1e2c382f, + 0xe0bf7ae, + 0xfdebb72d, + 0xedcb76ac, + 0x6ecd7ab4, + 0x6ac56a94, + 0x6cc972a4, + 0x6ecd7ab4, + 0xb16aa56a, + 0xb36ead7a, + 0x62cd4ab4, + 0x6add6af4, + 0xd58ad529, + 0xdd9af569, + 0x72d58ad5, + 0x66bd5a74, + 0x82f5cb56, + 0x569d19f3, + 0x93160bd7, + 0x467cd972, + 0xa3364c58, + 0x365c98f1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table10 */ +static const unsigned CONST_TBL_xd_seli_table10_0[] = { + 0x19b262c1, + 0x9ab466c9, + 0x1bb66ad1, + 0x9cb86ed9, + 0xa0c07ef9, + 0xa4c88f1a, + 0xa8d09f3a, + 0x9ebc76e9, + 0x37eedbb3, + 0xb6ecd7ab, + 0x35ead3a3, + 0xb4e8cf9b, + 0xb0e0bf7a, + 0xacd8af5a, + 0xa8d09f3a, + 0xa2c4870a, + 0x30e0bb72, + 0xb1e2bf7a, + 0x88901628, + 0x9921a30, + 0x8a941e38, + 0x20c072e1, + 0xa1c276e9, + 0x22c47af1, + 0xa3c67ef9, + 0xa4c88b12, + 0x25ca8f1a, + 0xa6cc9322, + 0xb0e0b76a, + 0xb2e4bf7a, + 0xb0e0af5a, + 0xb4e8bf7a, + 0xc98af58, + 0x1cb8efd9, + 0x18b0dbb1, + 0x99b2dfb9, + 0x98b0dfb9, + 0x8c98af5a, + 0x9cb8efdb, + 0x98b0d7ab, + 0x9ab4dfbb, + 0x98b0dfbb, + 0x8c98af5a, + 0x9cb8efdb, + 0x98b0cf9b, + 0x9cb8dfbb, + 0x98b0dfbb, + 0x37eedbb3, + 0xb6ecd7ab, + 0x35ead3a3, + 0xb4e8cf9b, + 0x33e6cb93, + 0xb2e4c78b, + 0x31e2c382, + 0xb0e0bf7a, + 0xb8f0dfbb, + 0xb8f05eb9, + 0xa8d09f3a, + 0xb8f0dfbb, + 0x6c18ae5e, + 0x7c38eedf, + 0xb830dcbb, + 0xf8b1debf, + 0x3160bd72, + 0x71e1bf76, + 0xd93160bd, + 0x786fddb7, + 0x5a3364c5, + 0xf76dd9af, + 0xdb3568cd, + 0x766bd5a7, + 0x5c376cd5, + 0xf569d19f, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table11 */ +static const unsigned CONST_TBL_xd_seli_table11_0[] = { + 0xe1bb66ad, + 0xe9cb86ed, + 0xf1dba72e, + 0xf9ebc76e, + 0x1a2c4870, + 0x3a6cc972, + 0x5aad4a74, + 0xa0c07ef, + 0xd39f2e3c, + 0xcb8f0dfb, + 0xc37eedbb, + 0xbb6ecd7a, + 0x9b2e4c78, + 0x7aedcb76, + 0x5aad4a74, + 0x2a4c88f1, + 0xb34e8cb9, + 0xbb5eacf9, + 0x88e9c2e5, + 0x90f9e326, + 0x990a0366, + 0x628d0932, + 0x6a9d2972, + 0x72ad49b3, + 0x7abd69f3, + 0x427ce972, + 0x4a8d09b3, + 0x529d29f3, + 0xab4e8c78, + 0xbb6eccf9, + 0x9b2e4c78, + 0xbb6ecd7a, + 0x68d9ab36, + 0xe9dbaf3e, + 0xd1ab4e3c, + 0xd9bb6e7c, + 0xd9ab4e7c, + 0x6acd8366, + 0xebcf876e, + 0xcb8f066c, + 0xdbaf46ed, + 0xdbaf466c, + 0x78e9c366, + 0xf9ebc76e, + 0xd9ab466c, + 0xf9ebc76e, + 0xd9ab466c, + 0xd39f2e3c, + 0xcb8f0dfb, + 0xc37eedbb, + 0xbb6ecd7a, + 0xb35ead3a, + 0xab4e8cf9, + 0xa33e6cb9, + 0x9b2e4c78, + 0xdbaf4e7c, + 0xdbaf4e7c, + 0x5aad4a74, + 0xdbaf4e7c, + 0x6ed1ab26, + 0xefd3af2e, + 0xdba34e4c, + 0xdfab5e6c, + 0xb3568cd9, + 0xb75e9cf9, + 0xddb3568c, + 0xd7a73e5c, + 0xe5c376cd, + 0xcf971e1b, + 0xedd3970d, + 0xc786fddb, + 0xf5e3b74e, + 0xbf76dd9a, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table12 */ +static const unsigned CONST_TBL_xd_seli_table12_0[] = { + 0xaf1dba72, + 0xef9ebc76, + 0x301fbe7a, + 0x70a0c07e, + 0x72a4c88f, + 0x74a8d09f, + 0x76acd8af, + 0xf1a2c487, + 0x3e3bf6eb, + 0xfdbaf4e7, + 0xbd39f2e3, + 0x7cb8f0df, + 0x7ab4e8cf, + 0x78b0e0bf, + 0x76acd8af, + 0xf3a6cc97, + 0xbd38f0db, + 0xfdb9f2df, + 0xeb94a846, + 0x2c15aa4a, + 0x6c96ac4e, + 0x3a30e0b3, + 0x7ab1e2b7, + 0xbb32e4bb, + 0xfbb3e6bf, + 0xf5aad4a3, + 0x362bd6a7, + 0x76acd8ab, + 0x7cb8f0d7, + 0xfdbaf4df, + 0x7cb8f0cf, + 0x7ebcf8df, + 0xb70e9cb7, + 0xbf1ebcf7, + 0x3e1cb8eb, + 0x7e9dbaef, + 0x7e9cb8ef, + 0xe78e9cb7, + 0xef9ebcf7, + 0x6e9cb8e7, + 0xef9ebcef, + 0x6e9cb8ef, + 0x76acd83e, + 0x7ebcf87e, + 0x7cb8f06e, + 0x7ebcf87e, + 0x7ebcf86e, + 0x3e3bf6eb, + 0xfdbaf4e7, + 0xbd39f2e3, + 0x7cb8f0df, + 0x3c37eedb, + 0xfbb6ecd7, + 0xbb35ead3, + 0x7ab4e8cf, + 0x7ebcf8ef, + 0x7ebcf8ef, + 0x76acd8af, + 0x7ebcf8ef, + 0xa76e1cb6, + 0xaf7e3cf6, + 0x4ebc38ec, + 0x6efcb9ee, + 0xdd3970dd, + 0xfd79f1df, + 0x8edd3970, + 0x5e7c77ed, + 0xcf5e3b74, + 0x1dfb75e9, + 0xfdf3d78, + 0xdd7a73e5, + 0x50603f7c, + 0x9cf971e1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table13 */ +static const unsigned CONST_TBL_xd_seli_table13_0[] = { + 0x8301fbe7, + 0x870a0c07, + 0x8b121c28, + 0x8f1a2c48, + 0x9f3a6cc9, + 0xaf5aad4a, + 0xbf7aedcb, + 0x972a4c88, + 0xfbf3dfaf, + 0xf7ebcf8e, + 0xf3e3bf6e, + 0xefdbaf4e, + 0xdfbb6ecd, + 0xcf9b2e4c, + 0xbf7aedcb, + 0xa74a8d09, + 0xfbf3cf8e, + 0xfffbdfae, + 0x76e9ab45, + 0x7af1bb66, + 0x7ef9cb86, + 0xf3e38f0d, + 0xf7eb9f2d, + 0xfbf3af4d, + 0xfffbbf6d, + 0xbb72ddaa, + 0xbf7aedcb, + 0xc382fdeb, + 0xf7ebcf8e, + 0xfffbefce, + 0xefdbaf4e, + 0xfffbefcf, + 0xbf78f9eb, + 0xfff9fbef, + 0xfbf1ebcf, + 0xfff9fbef, + 0xfff9ebcf, + 0xbf7aedc3, + 0xfffbefc7, + 0xf7ebcf87, + 0xfffbefc7, + 0xfffbefc7, + 0xbf7aedcb, + 0xfffbefcf, + 0xefdbaf4e, + 0xfffbefcf, + 0xfffbefcf, + 0xfbf3dfaf, + 0xf7ebcf8e, + 0xf3e3bf6e, + 0xefdbaf4e, + 0xebd39f2e, + 0xe7cb8f0d, + 0xe3c37eed, + 0xdfbb6ecd, + 0xfffbefcf, + 0xfffbefcf, + 0xbf7aedcb, + 0xfffbefcf, + 0xbe7ef1eb, + 0xfefff3ef, + 0xfcfbe3cf, + 0xfeffebdf, + 0xfdf3d78e, + 0xfff7df9e, + 0x80fdf3d7, + 0xfdf7e7bf, + 0x850603f7, + 0xf9efd79f, + 0x890e1418, + 0xf5e7c77e, + 0x8d162438, + 0xf1dfb75e, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_shfli_table0 */ +static const unsigned CONST_TBL_xd_shfli_table0_0[] = { + 0x440c2040, + 0x4c2ca248, + 0x544d2450, + 0x5c6da658, + 0x648e2860, + 0x6caeaa68, + 0x74cf2c70, + 0x7cefae78, + 0xc60400c2, + 0x401c6144, + 0x4c2ca248, + 0x544d2450, + 0xc2040040, + 0xe2860860, + 0x400c2040, + 0x608e2860, + 0x440c2040, + 0x648e2860, + 0x44040040, + 0xc60c20c2, + 0x400c2040, + 0x441c6144, + 0x440c2040, + 0x4c2ca248, + 0xfaf7cffe, + 0x78ffef7c, + 0x7cefae78, + 0x500c2040, + 0x600c2040, + 0x440c2040, + 0x82841800, + 0x648e2860, + 0 +}; + +/* constant table xd_shfli_table1 */ +static const unsigned CONST_TBL_xd_shfli_table1_0[] = { + 0x20401c61, + 0xa2483ce3, + 0x24505d65, + 0xa6587de7, + 0x28609e69, + 0xaa68beeb, + 0x2c70df6d, + 0xae78ffef, + 0x82ca1441, + 0xe34c0c20, + 0x20403ce3, + 0xa6585d65, + 0x41440c20, + 0x49648e28, + 0x61440c20, + 0x69648e28, + 0x20401c61, + 0x28609e69, + 0x82481441, + 0xa2ca1c61, + 0xa2480c20, + 0xe34c1c61, + 0x20401c61, + 0xa2483ce3, + 0x4df6e78e, + 0x6d74efae, + 0x2c70ffef, + 0x28604d24, + 0x24508e28, + 0xa2481c61, + 0x59048c38, + 0xaa689e69, + 0 +}; + +/* constant table xd_shfli_table2 */ +static const unsigned CONST_TBL_xd_shfli_table2_0[] = { + 0x1c61440c, + 0x3ce34c2c, + 0x5d65544d, + 0x7de75c6d, + 0x9e69648e, + 0xbeeb6cae, + 0xdf6d74cf, + 0xffef7cef, + 0x34c3ce24, + 0x2ca2483c, + 0x1c61440c, + 0x7de75c6d, + 0x1c61c614, + 0x9e69e696, + 0x1c61441c, + 0x9e69649e, + 0x1c61440c, + 0x9e69648e, + 0x34c34c24, + 0x3ce3ce2c, + 0x2ca2482c, + 0x3ce34c3c, + 0x1c61440c, + 0x3ce34c2c, + 0xc70cf2d7, + 0xcf2c70df, + 0xdf6d74cf, + 0xcf2c708e, + 0xcf2c704d, + 0x4d24502c, + 0x9c798694, + 0xbeeb6cae, + 0 +}; + +/* constant table xd_shfli_table3 */ +static const unsigned CONST_TBL_xd_shfli_table3_0[] = { + 0x440c2040, + 0x4c2ca248, + 0x544d2450, + 0x5c6da658, + 0x648e2860, + 0x6caeaa68, + 0x74cf2c70, + 0x7cefae78, + 0xd64504d2, + 0x505d6554, + 0x5c6da658, + 0x440c2040, + 0xca248248, + 0xeaa68a68, + 0x482ca248, + 0x68aeaa68, + 0x4c2ca248, + 0x6caeaa68, + 0x54450450, + 0xd64d24d2, + 0x504d2450, + 0x545d6554, + 0x544d2450, + 0x5c6da658, + 0xeab6cbee, + 0x68beeb6c, + 0x6caeaa68, + 0x541c6144, + 0x641c6144, + 0x585d6554, + 0x8aa49a08, + 0x74cf2c70, + 0 +}; + +/* constant table xd_shfli_table4 */ +static const unsigned CONST_TBL_xd_shfli_table4_0[] = { + 0x20401c61, + 0xa2483ce3, + 0x24505d65, + 0xa6587de7, + 0x28609e69, + 0xaa68beeb, + 0x2c70df6d, + 0xae78ffef, + 0x86da5545, + 0xe75c4d24, + 0x24507de7, + 0xa2481c61, + 0xc34c2ca2, + 0xcb6caeaa, + 0xe34c2ca2, + 0xeb6caeaa, + 0xa2483ce3, + 0xaa68beeb, + 0x86585545, + 0xa6da5d65, + 0xa6584d24, + 0xe75c5d65, + 0x24505d65, + 0xa6587de7, + 0x49e6a68a, + 0x6964aeaa, + 0x2860beeb, + 0x69645d65, + 0x65549e69, + 0x28606da6, + 0xdb0cacba, + 0xae78df6d, + 0 +}; + +/* constant table xd_shfli_table5 */ +static const unsigned CONST_TBL_xd_shfli_table5_0[] = { + 0x1c61440c, + 0x3ce34c2c, + 0x5d65544d, + 0x7de75c6d, + 0x9e69648e, + 0xbeeb6cae, + 0xdf6d74cf, + 0xffef7cef, + 0x75c7de65, + 0x6da6587d, + 0x5d65544d, + 0x3ce34c2c, + 0x3ce3ce34, + 0xbeebeeb6, + 0x3ce34c3c, + 0xbeeb6cbe, + 0x3ce34c2c, + 0xbeeb6cae, + 0x75c75c65, + 0x7de7de6d, + 0x6da6586d, + 0x7de75c7d, + 0x5d65544d, + 0x7de75c6d, + 0x8608e296, + 0x8e28609e, + 0x9e69648e, + 0xdf6d749e, + 0xdf6d745d, + 0x9e69648e, + 0xbcfb8eb4, + 0xffef7cef, + 0 +}; + +/* constant table xd_shfli_table6 */ +static const unsigned CONST_TBL_xd_shfli_table6_0[] = { + 0x440c2040, + 0x4c2ca248, + 0x544d2450, + 0x5c6da658, + 0x648e2860, + 0x6caeaa68, + 0x74cf2c70, + 0x7cefae78, + 0xe68608e2, + 0x609e6964, + 0x6caeaa68, + 0x74cf2c70, + 0xd2450450, + 0xf2c70c70, + 0x504d2450, + 0x70cf2c70, + 0x544d2450, + 0x74cf2c70, + 0x64860860, + 0xe68e28e2, + 0x608e2860, + 0x649e6964, + 0x648e2860, + 0x6caeaa68, + 0xda75c7de, + 0x587de75c, + 0x5c6da658, + 0x582ca248, + 0x682ca248, + 0x70aeaa68, + 0x92c51c10, + 0x440c2040, + 0 +}; + +/* constant table xd_shfli_table7 */ +static const unsigned CONST_TBL_xd_shfli_table7_0[] = { + 0x20401c61, + 0xa2483ce3, + 0x24505d65, + 0xa6587de7, + 0x28609e69, + 0xaa68beeb, + 0x2c70df6d, + 0xae78ffef, + 0x8aea9649, + 0xeb6c8e28, + 0x2860beeb, + 0xae78df6d, + 0x45544d24, + 0x4d74cf2c, + 0x65544d24, + 0x6d74cf2c, + 0x24505d65, + 0x2c70df6d, + 0x8a689649, + 0xaaea9e69, + 0xaa688e28, + 0xeb6c9e69, + 0x28609e69, + 0xaa68beeb, + 0x45d66586, + 0x65546da6, + 0x24507de7, + 0xaa686da6, + 0xa658aeaa, + 0x6d74cf2c, + 0x5d14cd3c, + 0xa2481c61, + 0 +}; + +/* constant table xd_shfli_table8 */ +static const unsigned CONST_TBL_xd_shfli_table8_0[] = { + 0x1c61440c, + 0x3ce34c2c, + 0x5d65544d, + 0x7de75c6d, + 0x9e69648e, + 0xbeeb6cae, + 0xdf6d74cf, + 0xffef7cef, + 0xb6cbeea6, + 0xaeaa68be, + 0x9e69648e, + 0xffef7cef, + 0x5d65d655, + 0xdf6df6d7, + 0x5d65545d, + 0xdf6d74df, + 0x5d65544d, + 0xdf6d74cf, + 0xb6cb6ca6, + 0xbeebeeae, + 0xaeaa68ae, + 0xbeeb6cbe, + 0x9e69648e, + 0xbeeb6cae, + 0x4504d255, + 0x4d24505d, + 0x5d65544d, + 0xefae78ae, + 0xefae786d, + 0xefae78df, + 0xdd7d96d5, + 0x3ce34c2c, + 0 +}; + +/* constant table xd_shfli_table9 */ +static const unsigned CONST_TBL_xd_shfli_table9_0[] = { + 0x440c2040, + 0x4c2ca248, + 0x544d2450, + 0x5c6da658, + 0x648e2860, + 0x6caeaa68, + 0x74cf2c70, + 0x7cefae78, + 0xf6c70cf2, + 0x70df6d74, + 0x7cefae78, + 0x648e2860, + 0xda658658, + 0xfae78e78, + 0x586da658, + 0x78efae78, + 0x5c6da658, + 0x7cefae78, + 0x74c70c70, + 0xf6cf2cf2, + 0x70cf2c70, + 0x74df6d74, + 0x74cf2c70, + 0x7cefae78, + 0xca34c3ce, + 0x483ce34c, + 0x4c2ca248, + 0x5c3ce34c, + 0x6c3ce34c, + 0x5c3ce34c, + 0x9ae59e18, + 0x544d2450, + 0 +}; + +/* constant table xd_shfli_table10 */ +static const unsigned CONST_TBL_xd_shfli_table10_0[] = { + 0x20401c61, + 0xa2483ce3, + 0x24505d65, + 0xa6587de7, + 0x28609e69, + 0xaa68beeb, + 0x2c70df6d, + 0xae78ffef, + 0x8efad74d, + 0xef7ccf2c, + 0x2c70ffef, + 0xaa689e69, + 0xc75c6da6, + 0xcf7cefae, + 0xe75c6da6, + 0xef7cefae, + 0xa6587de7, + 0xae78ffef, + 0x8e78d74d, + 0xaefadf6d, + 0xae78cf2c, + 0xef7cdf6d, + 0x2c70df6d, + 0xae78ffef, + 0x41c62482, + 0x61442ca2, + 0x20403ce3, + 0xeb6c7de7, + 0xe75cbeeb, + 0xeb6c7de7, + 0xdf1cedbe, + 0xa6585d65, + 0 +}; + +/* constant table xd_shfli_table11 */ +static const unsigned CONST_TBL_xd_shfli_table11_0[] = { + 0x1c61440c, + 0x3ce34c2c, + 0x5d65544d, + 0x7de75c6d, + 0x9e69648e, + 0xbeeb6cae, + 0xdf6d74cf, + 0xffef7cef, + 0xf7cffee7, + 0xefae78ff, + 0xdf6d74cf, + 0xbeeb6cae, + 0x7de7de75, + 0xffeffef7, + 0x7de75c7d, + 0xffef7cff, + 0x7de75c6d, + 0xffef7cef, + 0xf7cf7ce7, + 0xffeffeef, + 0xefae78ef, + 0xffef7cff, + 0xdf6d74cf, + 0xffef7cef, + 0x400c214, + 0xc20401c, + 0x1c61440c, + 0xffef7cbe, + 0xffef7c7d, + 0xffef7cbe, + 0xfdff9ef5, + 0x7de75c6d, + 0 +}; + +/* constant table bbe_ltrxnimm_tab */ +static const unsigned CONST_TBL_bbe_ltrxnimm_tab_0[] = { + 0, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0x10, + 0x11, + 0x12, + 0x13, + 0x14, + 0x15, + 0x16, + 0x17, + 0x18, + 0x19, + 0x1a, + 0x1b, + 0x1c, + 0x1d, + 0x1e, + 0x1f, + 0x20, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table bbe_ltrxn_2imm_tab */ +static const unsigned CONST_TBL_bbe_ltrxn_2imm_tab_0[] = { + 0, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0x10, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table bbe_ltrx2nimm_tab */ +static const unsigned CONST_TBL_bbe_ltrx2nimm_tab_0[] = { + 0, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0x10, + 0x11, + 0x12, + 0x13, + 0x14, + 0x15, + 0x16, + 0x17, + 0x18, + 0x19, + 0x1a, + 0x1b, + 0x1c, + 0x1d, + 0x1e, + 0x1f, + 0x20, + 0x21, + 0x22, + 0x23, + 0x24, + 0x25, + 0x26, + 0x27, + 0x28, + 0x29, + 0x2a, + 0x2b, + 0x2c, + 0x2d, + 0x2e, + 0x2f, + 0x30, + 0x31, + 0x32, + 0x33, + 0x34, + 0x35, + 0x36, + 0x37, + 0x38, + 0x39, + 0x3a, + 0x3b, + 0x3c, + 0x3d, + 0x3e, + 0x3f, + 0x40, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table es_dist8 */ +static const unsigned CONST_TBL_es_dist8_0[] = { + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 & 0xffff, + 0x1 & 0xffff, + 0x3 & 0xffff, + 0x7 & 0xffff, + 0xf & 0xffff, + 0x11e & 0xffff, + 0x33c & 0xffff, + 0x778 & 0xffff, + 0xff0 & 0xffff, + 0x1ee0 & 0xffff, + 0x3cc0 & 0xffff, + 0x7880 & 0xffff, + 0 +}; + +/* constant table es_dist4 */ +static const unsigned CONST_TBL_es_dist4_0[] = { + 0x3c0 & 0xffff, + 0x1680 & 0xffff, + 0x3c00 & 0xffff, + 0x6801 & 0xffff, + 0xc003 & 0xffff, + 0x8016 & 0xffff, + 0x3c & 0xffff, + 0x168 & 0xffff, + 0x3c0 & 0xffff, + 0x1680 & 0xffff, + 0x3c00 & 0xffff, + 0x6801 & 0xffff, + 0xc003 & 0xffff, + 0x8016 & 0xffff, + 0x3c & 0xffff, + 0x168 & 0xffff, + 0 +}; + +/* constant table es_dist2 */ +static const unsigned CONST_TBL_es_dist2_0[] = { + 0x1818 & 0xffff, + 0x6060 & 0xffff, + 0x8181 & 0xffff, + 0xe06 & 0xffff, + 0x3818 & 0xffff, + 0x6060 & 0xffff, + 0x81c1 & 0xffff, + 0x70e & 0xffff, + 0x1c38 & 0xffff, + 0x7060 & 0xffff, + 0x8181 & 0xffff, + 0xe06 & 0xffff, + 0x381c & 0xffff, + 0x6070 & 0xffff, + 0x8181 & 0xffff, + 0x606 & 0xffff, + 0 +}; + +/* constant table es_dist1 */ +static const unsigned CONST_TBL_es_dist1_0[] = { + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0 +}; + +/* constant table et_dist8 */ +static const unsigned CONST_TBL_et_dist8_0[] = { + 0xc00 & 0xffff, + 0x1800 & 0xffff, + 0x3000 & 0xffff, + 0x6000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 & 0xffff, + 0x1 & 0xffff, + 0x3 & 0xffff, + 0x6 & 0xffff, + 0xc & 0xffff, + 0x18 & 0xffff, + 0x30 & 0xffff, + 0x160 & 0xffff, + 0x3c0 & 0xffff, + 0x680 & 0xffff, + 0 +}; + +/* constant table et_dist4 */ +static const unsigned CONST_TBL_et_dist4_0[] = { + 0x8020 & 0xffff, + 0x40 & 0xffff, + 0x180 & 0xffff, + 0x200 & 0xffff, + 0x401 & 0xffff, + 0x1802 & 0xffff, + 0x2004 & 0xffff, + 0x4018 & 0xffff, + 0x8020 & 0xffff, + 0x40 & 0xffff, + 0x180 & 0xffff, + 0x200 & 0xffff, + 0x401 & 0xffff, + 0x1802 & 0xffff, + 0x2004 & 0xffff, + 0x4018 & 0xffff, + 0 +}; + +/* constant table et_dist2 */ +static const unsigned CONST_TBL_et_dist2_0[] = { + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8c21 & 0xffff, + 0x1842 & 0xffff, + 0x218c & 0xffff, + 0x4318 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0x3184 & 0xffff, + 0x4218 & 0xffff, + 0x8c31 & 0xffff, + 0x1842 & 0xffff, + 0 +}; + +/* constant table et_dist1 */ +static const unsigned CONST_TBL_et_dist1_0[] = { + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0 +}; + +/* constant table st_dist8 */ +static const unsigned CONST_TBL_st_dist8_0[] = { + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 & 0xffff, + 0x1 & 0xffff, + 0x3 & 0xffff, + 0x7 & 0xffff, + 0xf & 0xffff, + 0x11e & 0xffff, + 0x33c & 0xffff, + 0x778 & 0xffff, + 0xff0 & 0xffff, + 0x1ee0 & 0xffff, + 0x3cc0 & 0xffff, + 0x7880 & 0xffff, + 0 +}; + +/* constant table st_dist4 */ +static const unsigned CONST_TBL_st_dist4_0[] = { + 0x3c0 & 0xffff, + 0x1680 & 0xffff, + 0x3c00 & 0xffff, + 0x6801 & 0xffff, + 0xc003 & 0xffff, + 0x8016 & 0xffff, + 0x3c & 0xffff, + 0x168 & 0xffff, + 0x3c0 & 0xffff, + 0x1680 & 0xffff, + 0x3c00 & 0xffff, + 0x6801 & 0xffff, + 0xc003 & 0xffff, + 0x8016 & 0xffff, + 0x3c & 0xffff, + 0x168 & 0xffff, + 0 +}; + +/* constant table st_dist2 */ +static const unsigned CONST_TBL_st_dist2_0[] = { + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0 +}; + +/* constant table st_dist1 */ +static const unsigned CONST_TBL_st_dist1_0[] = { + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 +}; + +/* constant table re_dist_sel */ +static const unsigned CONST_TBL_re_dist_sel_0[] = { + 0x100 & 0xffff, + 0x1010 & 0xffff, + 0x4444 & 0xffff, + 0xaaaa & 0xffff, + 0 +}; + +/* constant table rs_dist_sel */ +static const unsigned CONST_TBL_rs_dist_sel_0[] = { + 0x300 & 0xffff, + 0x3030 & 0xffff, + 0xcccc & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table rt_dist_sel */ +static const unsigned CONST_TBL_rt_dist_sel_0[] = { + 0xf00 & 0xffff, + 0xf0f0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table r64_dist_sel */ +static const unsigned CONST_TBL_r64_dist_sel_0[] = { + 0xff00 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table align_dist8 */ +static const unsigned CONST_TBL_align_dist8_0[] = { + 0 & 0xffff, + 0x101 & 0xffff, + 0x303 & 0xffff, + 0x707 & 0xffff, + 0xf0f & 0xffff, + 0x1f1f & 0xffff, + 0x3f3f & 0xffff, + 0x7f7f & 0xffff, + 0xffff & 0xffff, + 0xfefe & 0xffff, + 0xfcfc & 0xffff, + 0xf8f8 & 0xffff, + 0xf0f0 & 0xffff, + 0xe0e0 & 0xffff, + 0xc0c0 & 0xffff, + 0x8080 & 0xffff, + 0 +}; + +/* constant table align_dist4 */ +static const unsigned CONST_TBL_align_dist4_0[] = { + 0 & 0xffff, + 0x1111 & 0xffff, + 0x3333 & 0xffff, + 0x7777 & 0xffff, + 0xffff & 0xffff, + 0xeeee & 0xffff, + 0xcccc & 0xffff, + 0x8888 & 0xffff, + 0 & 0xffff, + 0x1111 & 0xffff, + 0x3333 & 0xffff, + 0x7777 & 0xffff, + 0xffff & 0xffff, + 0xeeee & 0xffff, + 0xcccc & 0xffff, + 0x8888 & 0xffff, + 0 +}; + +/* constant table align_dist2 */ +static const unsigned CONST_TBL_align_dist2_0[] = { + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 +}; + +/* constant table align_dist1 */ +static const unsigned CONST_TBL_align_dist1_0[] = { + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 +}; + +/* constant table store_dist8 */ +static const unsigned CONST_TBL_store_dist8_0[] = { + 0 & 0xffff, + 0x8080 & 0xffff, + 0xc0c0 & 0xffff, + 0xe0e0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf8f8 & 0xffff, + 0xfcfc & 0xffff, + 0xfefe & 0xffff, + 0xffff & 0xffff, + 0x7f7f & 0xffff, + 0x3f3f & 0xffff, + 0x1f1f & 0xffff, + 0xf0f & 0xffff, + 0x707 & 0xffff, + 0x303 & 0xffff, + 0x101 & 0xffff, + 0 +}; + +/* constant table store_dist4 */ +static const unsigned CONST_TBL_store_dist4_0[] = { + 0 & 0xffff, + 0x888 & 0xffff, + 0xcccc & 0xffff, + 0xeee & 0xffff, + 0xffff & 0xffff, + 0x7777 & 0xffff, + 0x3333 & 0xffff, + 0x1111 & 0xffff, + 0 & 0xffff, + 0x8888 & 0xffff, + 0xcccc & 0xffff, + 0xee0e & 0xffff, + 0xffff & 0xffff, + 0x7077 & 0xffff, + 0x3333 & 0xffff, + 0x1011 & 0xffff, + 0 +}; + +/* constant table store_dist2 */ +static const unsigned CONST_TBL_store_dist2_0[] = { + 0 & 0xffff, + 0x22a & 0xffff, + 0xffff & 0xffff, + 0x7c44 & 0xffff, + 0 & 0xffff, + 0x223e & 0xffff, + 0xffff & 0xffff, + 0x4455 & 0xffff, + 0 & 0xffff, + 0x2222 & 0xffff, + 0xffff & 0xffff, + 0x7c7c & 0xffff, + 0 & 0xffff, + 0x3fe2 & 0xffff, + 0xffff & 0xffff, + 0x4045 & 0xffff, + 0 +}; + +/* constant table store_dist1 */ +static const unsigned CONST_TBL_store_dist1_0[] = { + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 +}; + +/* constant table pdx8_es_dist16 */ +static const unsigned CONST_TBL_pdx8_es_dist16_0[] = { + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0 +}; + +/* constant table pdx8_es_dist8 */ +static const unsigned CONST_TBL_pdx8_es_dist8_0[] = { + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0 +}; + +/* constant table pdx8_es_dist4 */ +static const unsigned CONST_TBL_pdx8_es_dist4_0[] = { + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table pdx8_es_dist2 */ +static const unsigned CONST_TBL_pdx8_es_dist2_0[] = { + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0 +}; + +/* constant table pdx8_es_dist1 */ +static const unsigned CONST_TBL_pdx8_es_dist1_0[] = { + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0 +}; + +/* constant table pdx8_et_dist16 */ +static const unsigned CONST_TBL_pdx8_et_dist16_0[] = { + 0xf00000, + 0x1e00000, + 0x3c00000, + 0x7800000, + 0xf000000, + 0x1e000000, + 0x3c000000, + 0x78000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1e, + 0x3c, + 0x78, + 0xf0, + 0x1e0, + 0x3c0, + 0x780, + 0xf00, + 0x11e00, + 0x33c00, + 0x77800, + 0xff000, + 0x1ee000, + 0x3cc000, + 0x788000, + 0 +}; + +/* constant table pdx8_et_dist8 */ +static const unsigned CONST_TBL_pdx8_et_dist8_0[] = { + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0 +}; + +/* constant table pdx8_et_dist4 */ +static const unsigned CONST_TBL_pdx8_et_dist4_0[] = { + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0 +}; + +/* constant table pdx8_et_dist2 */ +static const unsigned CONST_TBL_pdx8_et_dist2_0[] = { + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0 +}; + +/* constant table pdx8_et_dist1 */ +static const unsigned CONST_TBL_pdx8_et_dist1_0[] = { + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0 +}; + +/* constant table pdx8_st_dist16 */ +static const unsigned CONST_TBL_pdx8_st_dist16_0[] = { + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0 +}; + +/* constant table pdx8_st_dist8 */ +static const unsigned CONST_TBL_pdx8_st_dist8_0[] = { + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0 +}; + +/* constant table pdx8_st_dist4 */ +static const unsigned CONST_TBL_pdx8_st_dist4_0[] = { + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table pdx8_st_dist2 */ +static const unsigned CONST_TBL_pdx8_st_dist2_0[] = { + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0 +}; + +/* constant table pdx8_st_dist1 */ +static const unsigned CONST_TBL_pdx8_st_dist1_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table pdx8_re_dist_sel */ +static const unsigned CONST_TBL_pdx8_re_dist_sel_0[] = { + 0x10000, + 0x1000100, + 0x10101010, + 0x44444444, + 0xaaaaaaaa, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx8_rs_dist_sel */ +static const unsigned CONST_TBL_pdx8_rs_dist_sel_0[] = { + 0x30000, + 0x3000300, + 0x30303030, + 0xcccccccc, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx8_rt_dist_sel */ +static const unsigned CONST_TBL_pdx8_rt_dist_sel_0[] = { + 0xf0000, + 0xf000f00, + 0xf0f0f0f0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx8_r64_dist_sel */ +static const unsigned CONST_TBL_pdx8_r64_dist_sel_0[] = { + 0xff0000, + 0xff00ff00, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx8_align_dist16 */ +static const unsigned CONST_TBL_pdx8_align_dist16_0[] = { + 0, + 0x10001, + 0x30003, + 0x70007, + 0xf000f, + 0x1f001f, + 0x3f003f, + 0x7f007f, + 0xff00ff, + 0x1ff01ff, + 0x3ff03ff, + 0x7ff07ff, + 0xfff0fff, + 0x1fff1fff, + 0x3fff3fff, + 0x7fff7fff, + 0xffffffff, + 0xfffefffe, + 0xfffcfffc, + 0xfff8fff8, + 0xfff0fff0, + 0xffe0ffe0, + 0xffc0ffc0, + 0xff80ff80, + 0xff00ff00, + 0xfe00fe00, + 0xfc00fc00, + 0xf800f800, + 0xf000f000, + 0xe000e000, + 0xc000c000, + 0x80008000, + 0 +}; + +/* constant table pdx8_align_dist8 */ +static const unsigned CONST_TBL_pdx8_align_dist8_0[] = { + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0 +}; + +/* constant table pdx8_align_dist4 */ +static const unsigned CONST_TBL_pdx8_align_dist4_0[] = { + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0 +}; + +/* constant table pdx8_align_dist2 */ +static const unsigned CONST_TBL_pdx8_align_dist2_0[] = { + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0 +}; + +/* constant table pdx8_align_dist1 */ +static const unsigned CONST_TBL_pdx8_align_dist1_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table pdx16_es_dist32l */ +static const unsigned CONST_TBL_pdx16_es_dist32l_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x1ff, + 0x3ff, + 0x7ff, + 0xfff, + 0x1fff, + 0x3fff, + 0x7fff, + 0xffff, + 0x1fffe, + 0x3fffc, + 0x7fff8, + 0xffff0, + 0x1fffe0, + 0x3fffc0, + 0x7fff80, + 0xffff00, + 0x1fffe00, + 0x3fffc00, + 0x7fff800, + 0xffff000, + 0x1fffe000, + 0x3fffc000, + 0x7fff8000, + 0xffff0000, + 0xfffe0000, + 0xfffc0000, + 0xfff80000, + 0xfff00000, + 0xffe00000, + 0xffc00000, + 0xff800000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0 +}; + +/* constant table pdx16_es_dist32h */ +static const unsigned CONST_TBL_pdx16_es_dist32h_0[] = { + 0xffff0000, + 0xfffe0000, + 0xfffc0000, + 0xfff80000, + 0xfff00000, + 0xffe00000, + 0xffc00000, + 0xff800000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x1ff, + 0x3ff, + 0x7ff, + 0xfff, + 0x1fff, + 0x3fff, + 0x7fff, + 0xffff, + 0x1fffe, + 0x3fffc, + 0x7fff8, + 0xffff0, + 0x1fffe0, + 0x3fffc0, + 0x7fff80, + 0xffff00, + 0x1fffe00, + 0x3fffc00, + 0x7fff800, + 0xffff000, + 0x1fffe000, + 0x3fffc000, + 0x7fff8000, + 0 +}; + +/* constant table pdx16_es_dist16l */ +static const unsigned CONST_TBL_pdx16_es_dist16l_0[] = { + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0 +}; + +/* constant table pdx16_es_dist16h */ +static const unsigned CONST_TBL_pdx16_es_dist16h_0[] = { + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0 +}; + +/* constant table pdx16_es_dist8l */ +static const unsigned CONST_TBL_pdx16_es_dist8l_0[] = { + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0 +}; + +/* constant table pdx16_es_dist8h */ +static const unsigned CONST_TBL_pdx16_es_dist8h_0[] = { + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0 +}; + +/* constant table pdx16_es_dist4l */ +static const unsigned CONST_TBL_pdx16_es_dist4l_0[] = { + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table pdx16_es_dist4h */ +static const unsigned CONST_TBL_pdx16_es_dist4h_0[] = { + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table pdx16_es_dist2l */ +static const unsigned CONST_TBL_pdx16_es_dist2l_0[] = { + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0 +}; + +/* constant table pdx16_es_dist2h */ +static const unsigned CONST_TBL_pdx16_es_dist2h_0[] = { + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0 +}; + +/* constant table pdx16_es_dist1l */ +static const unsigned CONST_TBL_pdx16_es_dist1l_0[] = { + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0 +}; + +/* constant table pdx16_es_dist1h */ +static const unsigned CONST_TBL_pdx16_es_dist1h_0[] = { + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0 +}; + +/* constant table pdx16_et_dist32l */ +static const unsigned CONST_TBL_pdx16_et_dist32l_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x1fe, + 0x3fc, + 0x7f8, + 0xff0, + 0x1fe0, + 0x3fc0, + 0x7f80, + 0xff00, + 0x1fe00, + 0x3fc00, + 0x7f800, + 0xff000, + 0x1fe000, + 0x3fc000, + 0x7f8000, + 0xff0000, + 0x1fe0000, + 0x3fc0000, + 0x7f80000, + 0xff00000, + 0x1fe00000, + 0x3fc00000, + 0x7f800000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0 +}; + +/* constant table pdx16_et_dist32h */ +static const unsigned CONST_TBL_pdx16_et_dist32h_0[] = { + 0xff00, + 0x1fe00, + 0x3fc00, + 0x7f800, + 0xff000, + 0x1fe000, + 0x3fc000, + 0x7f8000, + 0xff0000, + 0x1fe0000, + 0x3fc0000, + 0x7f80000, + 0xff00000, + 0x1fe00000, + 0x3fc00000, + 0x7f800000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x1fe, + 0x3fc, + 0x7f8, + 0xff0, + 0x1fe0, + 0x3fc0, + 0x7f80, + 0 +}; + +/* constant table pdx16_et_dist16l */ +static const unsigned CONST_TBL_pdx16_et_dist16l_0[] = { + 0xf00000, + 0x1e00000, + 0x3c00000, + 0x7800000, + 0xf000000, + 0x1e000000, + 0x3c000000, + 0x78000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1e, + 0x3c, + 0x78, + 0xf0, + 0x1e0, + 0x3c0, + 0x780, + 0xf00, + 0x11e00, + 0x33c00, + 0x77800, + 0xff000, + 0x1ee000, + 0x3cc000, + 0x788000, + 0xf00000, + 0x1e00000, + 0x3c00000, + 0x7800000, + 0xf000000, + 0x1e000000, + 0x3c000000, + 0x78000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1e, + 0x3c, + 0x78, + 0xf0, + 0x1e0, + 0x3c0, + 0x780, + 0xf00, + 0x11e00, + 0x33c00, + 0x77800, + 0xff000, + 0x1ee000, + 0x3cc000, + 0x788000, + 0 +}; + +/* constant table pdx16_et_dist16h */ +static const unsigned CONST_TBL_pdx16_et_dist16h_0[] = { + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1e, + 0x3c, + 0x78, + 0xf0, + 0x1e0, + 0x3c0, + 0x780, + 0xf00, + 0x11e00, + 0x33c00, + 0x77800, + 0xff000, + 0x1ee000, + 0x3cc000, + 0x788000, + 0xf00000, + 0x1e00000, + 0x3c00000, + 0x7800000, + 0xf000000, + 0x1e000000, + 0x3c000000, + 0x78000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1e, + 0x3c, + 0x78, + 0xf0, + 0x1e0, + 0x3c0, + 0x780, + 0xf00, + 0x11e00, + 0x33c00, + 0x77800, + 0xff000, + 0x1ee000, + 0x3cc000, + 0x788000, + 0xf00000, + 0x1e00000, + 0x3c00000, + 0x7800000, + 0xf000000, + 0x1e000000, + 0x3c000000, + 0x78000000, + 0 +}; + +/* constant table pdx16_et_dist8l */ +static const unsigned CONST_TBL_pdx16_et_dist8l_0[] = { + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0 +}; + +/* constant table pdx16_et_dist8h */ +static const unsigned CONST_TBL_pdx16_et_dist8h_0[] = { + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0 +}; + +/* constant table pdx16_et_dist4l */ +static const unsigned CONST_TBL_pdx16_et_dist4l_0[] = { + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0 +}; + +/* constant table pdx16_et_dist4h */ +static const unsigned CONST_TBL_pdx16_et_dist4h_0[] = { + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0 +}; + +/* constant table pdx16_et_dist2l */ +static const unsigned CONST_TBL_pdx16_et_dist2l_0[] = { + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0 +}; + +/* constant table pdx16_et_dist2h */ +static const unsigned CONST_TBL_pdx16_et_dist2h_0[] = { + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0 +}; + +/* constant table pdx16_et_dist1l */ +static const unsigned CONST_TBL_pdx16_et_dist1l_0[] = { + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0 +}; + +/* constant table pdx16_et_dist1h */ +static const unsigned CONST_TBL_pdx16_et_dist1h_0[] = { + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0 +}; + +/* constant table pdx16_st_dist32l */ +static const unsigned CONST_TBL_pdx16_st_dist32l_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x1ff, + 0x3ff, + 0x7ff, + 0xfff, + 0x1fff, + 0x3fff, + 0x7fff, + 0xffff, + 0x1fffe, + 0x3fffc, + 0x7fff8, + 0xffff0, + 0x1fffe0, + 0x3fffc0, + 0x7fff80, + 0xffff00, + 0x1fffe00, + 0x3fffc00, + 0x7fff800, + 0xffff000, + 0x1fffe000, + 0x3fffc000, + 0x7fff8000, + 0xffff0000, + 0xfffe0000, + 0xfffc0000, + 0xfff80000, + 0xfff00000, + 0xffe00000, + 0xffc00000, + 0xff800000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0 +}; + +/* constant table pdx16_st_dist32h */ +static const unsigned CONST_TBL_pdx16_st_dist32h_0[] = { + 0xffff0000, + 0xfffe0000, + 0xfffc0000, + 0xfff80000, + 0xfff00000, + 0xffe00000, + 0xffc00000, + 0xff800000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x1ff, + 0x3ff, + 0x7ff, + 0xfff, + 0x1fff, + 0x3fff, + 0x7fff, + 0xffff, + 0x1fffe, + 0x3fffc, + 0x7fff8, + 0xffff0, + 0x1fffe0, + 0x3fffc0, + 0x7fff80, + 0xffff00, + 0x1fffe00, + 0x3fffc00, + 0x7fff800, + 0xffff000, + 0x1fffe000, + 0x3fffc000, + 0x7fff8000, + 0 +}; + +/* constant table pdx16_st_dist16l */ +static const unsigned CONST_TBL_pdx16_st_dist16l_0[] = { + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0 +}; + +/* constant table pdx16_st_dist16h */ +static const unsigned CONST_TBL_pdx16_st_dist16h_0[] = { + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0 +}; + +/* constant table pdx16_st_dist8l */ +static const unsigned CONST_TBL_pdx16_st_dist8l_0[] = { + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0 +}; + +/* constant table pdx16_st_dist8h */ +static const unsigned CONST_TBL_pdx16_st_dist8h_0[] = { + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0 +}; + +/* constant table pdx16_st_dist4l */ +static const unsigned CONST_TBL_pdx16_st_dist4l_0[] = { + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table pdx16_st_dist4h */ +static const unsigned CONST_TBL_pdx16_st_dist4h_0[] = { + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table pdx16_st_dist2l */ +static const unsigned CONST_TBL_pdx16_st_dist2l_0[] = { + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0 +}; + +/* constant table pdx16_st_dist2h */ +static const unsigned CONST_TBL_pdx16_st_dist2h_0[] = { + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0 +}; + +/* constant table pdx16_st_dist1l */ +static const unsigned CONST_TBL_pdx16_st_dist1l_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table pdx16_st_dist1h */ +static const unsigned CONST_TBL_pdx16_st_dist1h_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table pdx16_re_dist_sell */ +static const unsigned CONST_TBL_pdx16_re_dist_sell_0[] = { + 0, + 0x10000, + 0x1000100, + 0x10101010, + 0x44444444, + 0xaaaaaaaa, + 0, + 0, + 0 +}; + +/* constant table pdx16_re_dist_selh */ +static const unsigned CONST_TBL_pdx16_re_dist_selh_0[] = { + 0x1, + 0x10000, + 0x1000100, + 0x10101010, + 0x44444444, + 0xaaaaaaaa, + 0, + 0, + 0 +}; + +/* constant table pdx16_rs_dist_sell */ +static const unsigned CONST_TBL_pdx16_rs_dist_sell_0[] = { + 0, + 0x30000, + 0x3000300, + 0x30303030, + 0xcccccccc, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx16_rs_dist_selh */ +static const unsigned CONST_TBL_pdx16_rs_dist_selh_0[] = { + 0x3, + 0x30000, + 0x3000300, + 0x30303030, + 0xcccccccc, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx16_rt_dist_sell */ +static const unsigned CONST_TBL_pdx16_rt_dist_sell_0[] = { + 0, + 0xf0000, + 0xf000f00, + 0xf0f0f0f0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx16_rt_dist_selh */ +static const unsigned CONST_TBL_pdx16_rt_dist_selh_0[] = { + 0xf, + 0xf0000, + 0xf000f00, + 0xf0f0f0f0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx16_r64_dist_sell */ +static const unsigned CONST_TBL_pdx16_r64_dist_sell_0[] = { + 0, + 0xff0000, + 0xff00ff00, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx16_r64_dist_selh */ +static const unsigned CONST_TBL_pdx16_r64_dist_selh_0[] = { + 0xff, + 0xff0000, + 0xff00ff00, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx16_align_dist32l */ +static const unsigned CONST_TBL_pdx16_align_dist32l_0[] = { + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x1ff, + 0x3ff, + 0x7ff, + 0xfff, + 0x1fff, + 0x3fff, + 0x7fff, + 0xffff, + 0x1ffff, + 0x3ffff, + 0x7ffff, + 0xfffff, + 0x1fffff, + 0x3fffff, + 0x7fffff, + 0xffffff, + 0x1ffffff, + 0x3ffffff, + 0x7ffffff, + 0xfffffff, + 0x1fffffff, + 0x3fffffff, + 0x7fffffff, + 0xffffffff, + 0xfffffffe, + 0xfffffffc, + 0xfffffff8, + 0xfffffff0, + 0xffffffe0, + 0xffffffc0, + 0xffffff80, + 0xffffff00, + 0xfffffe00, + 0xfffffc00, + 0xfffff800, + 0xfffff000, + 0xffffe000, + 0xffffc000, + 0xffff8000, + 0xffff0000, + 0xfffe0000, + 0xfffc0000, + 0xfff80000, + 0xfff00000, + 0xffe00000, + 0xffc00000, + 0xff800000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0 +}; + +/* constant table pdx16_align_dist32h */ +static const unsigned CONST_TBL_pdx16_align_dist32h_0[] = { + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x1ff, + 0x3ff, + 0x7ff, + 0xfff, + 0x1fff, + 0x3fff, + 0x7fff, + 0xffff, + 0x1ffff, + 0x3ffff, + 0x7ffff, + 0xfffff, + 0x1fffff, + 0x3fffff, + 0x7fffff, + 0xffffff, + 0x1ffffff, + 0x3ffffff, + 0x7ffffff, + 0xfffffff, + 0x1fffffff, + 0x3fffffff, + 0x7fffffff, + 0xffffffff, + 0xfffffffe, + 0xfffffffc, + 0xfffffff8, + 0xfffffff0, + 0xffffffe0, + 0xffffffc0, + 0xffffff80, + 0xffffff00, + 0xfffffe00, + 0xfffffc00, + 0xfffff800, + 0xfffff000, + 0xffffe000, + 0xffffc000, + 0xffff8000, + 0xffff0000, + 0xfffe0000, + 0xfffc0000, + 0xfff80000, + 0xfff00000, + 0xffe00000, + 0xffc00000, + 0xff800000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0 +}; + +/* constant table pdx16_align_dist16l */ +static const unsigned CONST_TBL_pdx16_align_dist16l_0[] = { + 0, + 0x10001, + 0x30003, + 0x70007, + 0xf000f, + 0x1f001f, + 0x3f003f, + 0x7f007f, + 0xff00ff, + 0x1ff01ff, + 0x3ff03ff, + 0x7ff07ff, + 0xfff0fff, + 0x1fff1fff, + 0x3fff3fff, + 0x7fff7fff, + 0xffffffff, + 0xfffefffe, + 0xfffcfffc, + 0xfff8fff8, + 0xfff0fff0, + 0xffe0ffe0, + 0xffc0ffc0, + 0xff80ff80, + 0xff00ff00, + 0xfe00fe00, + 0xfc00fc00, + 0xf800f800, + 0xf000f000, + 0xe000e000, + 0xc000c000, + 0x80008000, + 0, + 0x10001, + 0x30003, + 0x70007, + 0xf000f, + 0x1f001f, + 0x3f003f, + 0x7f007f, + 0xff00ff, + 0x1ff01ff, + 0x3ff03ff, + 0x7ff07ff, + 0xfff0fff, + 0x1fff1fff, + 0x3fff3fff, + 0x7fff7fff, + 0xffffffff, + 0xfffefffe, + 0xfffcfffc, + 0xfff8fff8, + 0xfff0fff0, + 0xffe0ffe0, + 0xffc0ffc0, + 0xff80ff80, + 0xff00ff00, + 0xfe00fe00, + 0xfc00fc00, + 0xf800f800, + 0xf000f000, + 0xe000e000, + 0xc000c000, + 0x80008000, + 0 +}; + +/* constant table pdx16_align_dist16h */ +static const unsigned CONST_TBL_pdx16_align_dist16h_0[] = { + 0, + 0x10001, + 0x30003, + 0x70007, + 0xf000f, + 0x1f001f, + 0x3f003f, + 0x7f007f, + 0xff00ff, + 0x1ff01ff, + 0x3ff03ff, + 0x7ff07ff, + 0xfff0fff, + 0x1fff1fff, + 0x3fff3fff, + 0x7fff7fff, + 0xffffffff, + 0xfffefffe, + 0xfffcfffc, + 0xfff8fff8, + 0xfff0fff0, + 0xffe0ffe0, + 0xffc0ffc0, + 0xff80ff80, + 0xff00ff00, + 0xfe00fe00, + 0xfc00fc00, + 0xf800f800, + 0xf000f000, + 0xe000e000, + 0xc000c000, + 0x80008000, + 0, + 0x10001, + 0x30003, + 0x70007, + 0xf000f, + 0x1f001f, + 0x3f003f, + 0x7f007f, + 0xff00ff, + 0x1ff01ff, + 0x3ff03ff, + 0x7ff07ff, + 0xfff0fff, + 0x1fff1fff, + 0x3fff3fff, + 0x7fff7fff, + 0xffffffff, + 0xfffefffe, + 0xfffcfffc, + 0xfff8fff8, + 0xfff0fff0, + 0xffe0ffe0, + 0xffc0ffc0, + 0xff80ff80, + 0xff00ff00, + 0xfe00fe00, + 0xfc00fc00, + 0xf800f800, + 0xf000f000, + 0xe000e000, + 0xc000c000, + 0x80008000, + 0 +}; + +/* constant table pdx16_align_dist8l */ +static const unsigned CONST_TBL_pdx16_align_dist8l_0[] = { + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0 +}; + +/* constant table pdx16_align_dist8h */ +static const unsigned CONST_TBL_pdx16_align_dist8h_0[] = { + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0 +}; + +/* constant table pdx16_align_dist4l */ +static const unsigned CONST_TBL_pdx16_align_dist4l_0[] = { + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0 +}; + +/* constant table pdx16_align_dist4h */ +static const unsigned CONST_TBL_pdx16_align_dist4h_0[] = { + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0 +}; + +/* constant table pdx16_align_dist2l */ +static const unsigned CONST_TBL_pdx16_align_dist2l_0[] = { + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0 +}; + +/* constant table pdx16_align_dist2h */ +static const unsigned CONST_TBL_pdx16_align_dist2h_0[] = { + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0 +}; + +/* constant table pdx16_align_dist1l */ +static const unsigned CONST_TBL_pdx16_align_dist1l_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table pdx16_align_dist1h */ +static const unsigned CONST_TBL_pdx16_align_dist1h_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl0_low */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl0_low_0[] = { + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl0_high */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl0_high_0[] = { + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl1_low */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl1_low_0[] = { + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl1_high */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl1_high_0[] = { + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl2_low */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl2_low_0[] = { + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl2_high */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl2_high_0[] = { + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl3_low */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl3_low_0[] = { + 0x1000100, + 0x2000200, + 0x4000400, + 0x8000800, + 0x10001000, + 0x20002000, + 0x40004000, + 0x80008000, + 0x10001, + 0x20002, + 0x40004, + 0x80008, + 0x100010, + 0x200020, + 0x400040, + 0x800080, + 0x1000100, + 0x2000200, + 0x4000400, + 0x8000800, + 0x10001000, + 0x20002000, + 0x40004000, + 0x80008000, + 0x10001, + 0x20002, + 0x40004, + 0x80008, + 0x100010, + 0x200020, + 0x400040, + 0x800080, + 0x1000100, + 0x2000200, + 0x4000400, + 0x8000800, + 0x10001000, + 0x20002000, + 0x40004000, + 0x80008000, + 0x10001, + 0x20002, + 0x40004, + 0x80008, + 0x100010, + 0x200020, + 0x400040, + 0x800080, + 0x1000100, + 0x2000200, + 0x4000400, + 0x8000800, + 0x10001000, + 0x20002000, + 0x40004000, + 0x80008000, + 0x10001, + 0x20002, + 0x40004, + 0x80008, + 0x100010, + 0x200020, + 0x400040, + 0x800080, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl3_high */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl3_high_0[] = { + 0x1000100, + 0x2000200, + 0x4000400, + 0x8000800, + 0x10001000, + 0x20002000, + 0x40004000, + 0x80008000, + 0x10001, + 0x20002, + 0x40004, + 0x80008, + 0x100010, + 0x200020, + 0x400040, + 0x800080, + 0x1000100, + 0x2000200, + 0x4000400, + 0x8000800, + 0x10001000, + 0x20002000, + 0x40004000, + 0x80008000, + 0x10001, + 0x20002, + 0x40004, + 0x80008, + 0x100010, + 0x200020, + 0x400040, + 0x800080, + 0x1000100, + 0x2000200, + 0x4000400, + 0x8000800, + 0x10001000, + 0x20002000, + 0x40004000, + 0x80008000, + 0x10001, + 0x20002, + 0x40004, + 0x80008, + 0x100010, + 0x200020, + 0x400040, + 0x800080, + 0x1000100, + 0x2000200, + 0x4000400, + 0x8000800, + 0x10001000, + 0x20002000, + 0x40004000, + 0x80008000, + 0x10001, + 0x20002, + 0x40004, + 0x80008, + 0x100010, + 0x200020, + 0x400040, + 0x800080, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl4_low */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl4_low_0[] = { + 0x10000, + 0x20000, + 0x40000, + 0x80000, + 0x100000, + 0x200000, + 0x400000, + 0x800000, + 0x1000000, + 0x2000000, + 0x4000000, + 0x8000000, + 0x10000000, + 0x20000000, + 0x40000000, + 0x80000000, + 0x1, + 0x2, + 0x4, + 0x8, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0x200, + 0x400, + 0x800, + 0x1000, + 0x2000, + 0x4000, + 0x8000, + 0x10000, + 0x20000, + 0x40000, + 0x80000, + 0x100000, + 0x200000, + 0x400000, + 0x800000, + 0x1000000, + 0x2000000, + 0x4000000, + 0x8000000, + 0x10000000, + 0x20000000, + 0x40000000, + 0x80000000, + 0x1, + 0x2, + 0x4, + 0x8, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0x200, + 0x400, + 0x800, + 0x1000, + 0x2000, + 0x4000, + 0x8000, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl4_high */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl4_high_0[] = { + 0x10000, + 0x20000, + 0x40000, + 0x80000, + 0x100000, + 0x200000, + 0x400000, + 0x800000, + 0x1000000, + 0x2000000, + 0x4000000, + 0x8000000, + 0x10000000, + 0x20000000, + 0x40000000, + 0x80000000, + 0x1, + 0x2, + 0x4, + 0x8, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0x200, + 0x400, + 0x800, + 0x1000, + 0x2000, + 0x4000, + 0x8000, + 0x10000, + 0x20000, + 0x40000, + 0x80000, + 0x100000, + 0x200000, + 0x400000, + 0x800000, + 0x1000000, + 0x2000000, + 0x4000000, + 0x8000000, + 0x10000000, + 0x20000000, + 0x40000000, + 0x80000000, + 0x1, + 0x2, + 0x4, + 0x8, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0x200, + 0x400, + 0x800, + 0x1000, + 0x2000, + 0x4000, + 0x8000, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl5_low */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl5_low_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x2, + 0x4, + 0x8, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0x200, + 0x400, + 0x800, + 0x1000, + 0x2000, + 0x4000, + 0x8000, + 0x10000, + 0x20000, + 0x40000, + 0x80000, + 0x100000, + 0x200000, + 0x400000, + 0x800000, + 0x1000000, + 0x2000000, + 0x4000000, + 0x8000000, + 0x10000000, + 0x20000000, + 0x40000000, + 0x80000000, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl5_high */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl5_high_0[] = { + 0x1, + 0x2, + 0x4, + 0x8, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0x200, + 0x400, + 0x800, + 0x1000, + 0x2000, + 0x4000, + 0x8000, + 0x10000, + 0x20000, + 0x40000, + 0x80000, + 0x100000, + 0x200000, + 0x400000, + 0x800000, + 0x1000000, + 0x2000000, + 0x4000000, + 0x8000000, + 0x10000000, + 0x20000000, + 0x40000000, + 0x80000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx16_shft_rep16_lvl3_high */ +static const unsigned CONST_TBL_pdx16_shft_rep16_lvl3_high_0[] = { + 0x3000300, + 0x6000600, + 0xc000c00, + 0x18001800, + 0x30003000, + 0x60006000, + 0xc000c000, + 0x80018001, + 0x30003, + 0x60006, + 0xc000c, + 0x180018, + 0x300030, + 0x600060, + 0xc000c0, + 0x1800180, + 0x3000300, + 0x6000600, + 0xc000c00, + 0x18001800, + 0x30003000, + 0x60006000, + 0xc000c000, + 0x80018001, + 0x30003, + 0x60006, + 0xc000c, + 0x180018, + 0x300030, + 0x600060, + 0xc000c0, + 0x1800180, + 0x3000300, + 0x6000600, + 0xc000c00, + 0x18001800, + 0x30003000, + 0x60006000, + 0xc000c000, + 0x80018001, + 0x30003, + 0x60006, + 0xc000c, + 0x180018, + 0x300030, + 0x600060, + 0xc000c0, + 0x1800180, + 0x3000300, + 0x6000600, + 0xc000c00, + 0x18001800, + 0x30003000, + 0x60006000, + 0xc000c000, + 0x80018001, + 0x30003, + 0x60006, + 0xc000c, + 0x180018, + 0x300030, + 0x600060, + 0xc000c0, + 0x1800180, + 0 +}; + +/* constant table pdx16_shft_rep16_lvl3_low */ +static const unsigned CONST_TBL_pdx16_shft_rep16_lvl3_low_0[] = { + 0x3000300, + 0x6000600, + 0xc000c00, + 0x18001800, + 0x30003000, + 0x60006000, + 0xc000c000, + 0x80018001, + 0x30003, + 0x60006, + 0xc000c, + 0x180018, + 0x300030, + 0x600060, + 0xc000c0, + 0x1800180, + 0x3000300, + 0x6000600, + 0xc000c00, + 0x18001800, + 0x30003000, + 0x60006000, + 0xc000c000, + 0x80018001, + 0x30003, + 0x60006, + 0xc000c, + 0x180018, + 0x300030, + 0x600060, + 0xc000c0, + 0x1800180, + 0x3000300, + 0x6000600, + 0xc000c00, + 0x18001800, + 0x30003000, + 0x60006000, + 0xc000c000, + 0x80018001, + 0x30003, + 0x60006, + 0xc000c, + 0x180018, + 0x300030, + 0x600060, + 0xc000c0, + 0x1800180, + 0x3000300, + 0x6000600, + 0xc000c00, + 0x18001800, + 0x30003000, + 0x60006000, + 0xc000c000, + 0x80018001, + 0x30003, + 0x60006, + 0xc000c, + 0x180018, + 0x300030, + 0x600060, + 0xc000c0, + 0x1800180, + 0 +}; + +/* constant table pdx16_shft_rep16_lvl4_high */ +static const unsigned CONST_TBL_pdx16_shft_rep16_lvl4_high_0[] = { + 0x30000, + 0x60000, + 0xc0000, + 0x180000, + 0x300000, + 0x600000, + 0xc00000, + 0x1800000, + 0x3000000, + 0x6000000, + 0xc000000, + 0x18000000, + 0x30000000, + 0x60000000, + 0xc0000000, + 0x80000001, + 0x3, + 0x6, + 0xc, + 0x18, + 0x30, + 0x60, + 0xc0, + 0x180, + 0x300, + 0x600, + 0xc00, + 0x1800, + 0x3000, + 0x6000, + 0xc000, + 0x18000, + 0x30000, + 0x60000, + 0xc0000, + 0x180000, + 0x300000, + 0x600000, + 0xc00000, + 0x1800000, + 0x3000000, + 0x6000000, + 0xc000000, + 0x18000000, + 0x30000000, + 0x60000000, + 0xc0000000, + 0x80000001, + 0x3, + 0x6, + 0xc, + 0x18, + 0x30, + 0x60, + 0xc0, + 0x180, + 0x300, + 0x600, + 0xc00, + 0x1800, + 0x3000, + 0x6000, + 0xc000, + 0x18000, + 0 +}; + +/* constant table pdx16_shft_rep16_lvl4_low */ +static const unsigned CONST_TBL_pdx16_shft_rep16_lvl4_low_0[] = { + 0x30000, + 0x60000, + 0xc0000, + 0x180000, + 0x300000, + 0x600000, + 0xc00000, + 0x1800000, + 0x3000000, + 0x6000000, + 0xc000000, + 0x18000000, + 0x30000000, + 0x60000000, + 0xc0000000, + 0x80000001, + 0x3, + 0x6, + 0xc, + 0x18, + 0x30, + 0x60, + 0xc0, + 0x180, + 0x300, + 0x600, + 0xc00, + 0x1800, + 0x3000, + 0x6000, + 0xc000, + 0x18000, + 0x30000, + 0x60000, + 0xc0000, + 0x180000, + 0x300000, + 0x600000, + 0xc00000, + 0x1800000, + 0x3000000, + 0x6000000, + 0xc000000, + 0x18000000, + 0x30000000, + 0x60000000, + 0xc0000000, + 0x80000001, + 0x3, + 0x6, + 0xc, + 0x18, + 0x30, + 0x60, + 0xc0, + 0x180, + 0x300, + 0x600, + 0xc00, + 0x1800, + 0x3000, + 0x6000, + 0xc000, + 0x18000, + 0 +}; + +/* constant table pdx16_shft_rep16_lvl5_high */ +static const unsigned CONST_TBL_pdx16_shft_rep16_lvl5_high_0[] = { + 0x3, + 0x6, + 0xc, + 0x18, + 0x30, + 0x60, + 0xc0, + 0x180, + 0x300, + 0x600, + 0xc00, + 0x1800, + 0x3000, + 0x6000, + 0xc000, + 0x18000, + 0x30000, + 0x60000, + 0xc0000, + 0x180000, + 0x300000, + 0x600000, + 0xc00000, + 0x1800000, + 0x3000000, + 0x6000000, + 0xc000000, + 0x18000000, + 0x30000000, + 0x60000000, + 0xc0000000, + 0x80000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0 +}; + +/* constant table pdx16_shft_rep16_lvl5_low */ +static const unsigned CONST_TBL_pdx16_shft_rep16_lvl5_low_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x6, + 0xc, + 0x18, + 0x30, + 0x60, + 0xc0, + 0x180, + 0x300, + 0x600, + 0xc00, + 0x1800, + 0x3000, + 0x6000, + 0xc000, + 0x18000, + 0x30000, + 0x60000, + 0xc0000, + 0x180000, + 0x300000, + 0x600000, + 0xc00000, + 0x1800000, + 0x3000000, + 0x6000000, + 0xc000000, + 0x18000000, + 0x30000000, + 0x60000000, + 0xc0000000, + 0x80000000, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl0_low */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl0_low_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl1_low */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl1_low_0[] = { + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl2_low */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl2_low_0[] = { + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl3_low */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl3_low_0[] = { + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl4_low */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl4_low_0[] = { + 0xff0000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf000000f, + 0xf000000f, + 0xf000000f, + 0xf000000f, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff0, + 0xff0, + 0xff0, + 0xff0, + 0xff00, + 0xff00, + 0xff00, + 0xff00, + 0xff000, + 0xff000, + 0xff000, + 0xff000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf000000f, + 0xf000000f, + 0xf000000f, + 0xf000000f, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff0, + 0xff0, + 0xff0, + 0xff0, + 0xff00, + 0xff00, + 0xff00, + 0xff00, + 0xff000, + 0xff000, + 0xff000, + 0xff000, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl5_low */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl5_low_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0xf, + 0xf, + 0xf, + 0xf, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff0, + 0xff0, + 0xff0, + 0xff0, + 0xff00, + 0xff00, + 0xff00, + 0xff00, + 0xff000, + 0xff000, + 0xff000, + 0xff000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl0_high */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl0_high_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl1_high */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl1_high_0[] = { + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl2_high */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl2_high_0[] = { + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl3_high */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl3_high_0[] = { + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl4_high */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl4_high_0[] = { + 0xff0000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf000000f, + 0xf000000f, + 0xf000000f, + 0xf000000f, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff0, + 0xff0, + 0xff0, + 0xff0, + 0xff00, + 0xff00, + 0xff00, + 0xff00, + 0xff000, + 0xff000, + 0xff000, + 0xff000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf000000f, + 0xf000000f, + 0xf000000f, + 0xf000000f, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff0, + 0xff0, + 0xff0, + 0xff0, + 0xff00, + 0xff00, + 0xff00, + 0xff00, + 0xff000, + 0xff000, + 0xff000, + 0xff000, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl5_high */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl5_high_0[] = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff0, + 0xff0, + 0xff0, + 0xff0, + 0xff00, + 0xff00, + 0xff00, + 0xff00, + 0xff000, + 0xff000, + 0xff000, + 0xff000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0xf, + 0xf, + 0xf, + 0xf, + 0 +}; + +/* constant table la_32_high */ +static const unsigned CONST_TBL_la_32_high_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1e, + 0x3c, + 0x78, + 0xf0, + 0x1e0, + 0x3c0, + 0x780, + 0xf00, + 0x1e00, + 0x3c00, + 0x7800, + 0xf000, + 0x1e000, + 0x3c000, + 0x78000, + 0xf0000, + 0x1e0000, + 0x3c0000, + 0x780000, + 0xf00000, + 0x1e00000, + 0x3c00000, + 0x7800000, + 0xf000000, + 0x1e000000, + 0x3c000000, + 0x78000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0 +}; + +/* constant table la_32_low */ +static const unsigned CONST_TBL_la_32_low_0[] = { + 0xf, + 0x1e, + 0x3c, + 0x78, + 0xf0, + 0x1e0, + 0x3c0, + 0x780, + 0xf00, + 0x1e00, + 0x3c00, + 0x7800, + 0xf000, + 0x1e000, + 0x3c000, + 0x78000, + 0xf0000, + 0x1e0000, + 0x3c0000, + 0x780000, + 0xf00000, + 0x1e00000, + 0x3c00000, + 0x7800000, + 0xf000000, + 0x1e000000, + 0x3c000000, + 0x78000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x7, + 0 +}; + +/* constant table la_8_low */ +static const unsigned CONST_TBL_la_8_low_0[] = { + 0x1, + 0x2, + 0x4, + 0x8, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0x200, + 0x400, + 0x800, + 0x1000, + 0x2000, + 0x4000, + 0x8000, + 0x10000, + 0x20000, + 0x40000, + 0x80000, + 0x100000, + 0x200000, + 0x400000, + 0x800000, + 0x1000000, + 0x2000000, + 0x4000000, + 0x8000000, + 0x10000000, + 0x20000000, + 0x40000000, + 0x80000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table la_8_high */ +static const unsigned CONST_TBL_la_8_high_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x2, + 0x4, + 0x8, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0x200, + 0x400, + 0x800, + 0x1000, + 0x2000, + 0x4000, + 0x8000, + 0x10000, + 0x20000, + 0x40000, + 0x80000, + 0x100000, + 0x200000, + 0x400000, + 0x800000, + 0x1000000, + 0x2000000, + 0x4000000, + 0x8000000, + 0x10000000, + 0x20000000, + 0x40000000, + 0x80000000, + 0 +}; + +/* constant table la_16_high */ +static const unsigned CONST_TBL_la_16_high_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x6, + 0xc, + 0x18, + 0x30, + 0x60, + 0xc0, + 0x180, + 0x300, + 0x600, + 0xc00, + 0x1800, + 0x3000, + 0x6000, + 0xc000, + 0x18000, + 0x30000, + 0x60000, + 0xc0000, + 0x180000, + 0x300000, + 0x600000, + 0xc00000, + 0x1800000, + 0x3000000, + 0x6000000, + 0xc000000, + 0x18000000, + 0x30000000, + 0x60000000, + 0xc0000000, + 0x80000000, + 0 +}; + +/* constant table la_16_low */ +static const unsigned CONST_TBL_la_16_low_0[] = { + 0x3, + 0x6, + 0xc, + 0x18, + 0x30, + 0x60, + 0xc0, + 0x180, + 0x300, + 0x600, + 0xc00, + 0x1800, + 0x3000, + 0x6000, + 0xc000, + 0x18000, + 0x30000, + 0x60000, + 0xc0000, + 0x180000, + 0x300000, + 0x600000, + 0xc00000, + 0x1800000, + 0x3000000, + 0x6000000, + 0xc000000, + 0x18000000, + 0x30000000, + 0x60000000, + 0xc0000000, + 0x80000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0 +}; + +/* constant table shft_rep16_lvl0_high */ +static const unsigned CONST_TBL_shft_rep16_lvl0_high_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table shft_rep16_lvl0_low */ +static const unsigned CONST_TBL_shft_rep16_lvl0_low_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table shft_rep16_lvl1_high */ +static const unsigned CONST_TBL_shft_rep16_lvl1_high_0[] = { + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0 +}; + +/* constant table shft_rep16_lvl1_low */ +static const unsigned CONST_TBL_shft_rep16_lvl1_low_0[] = { + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0 +}; + +/* constant table shft_rep16_lvl2_high */ +static const unsigned CONST_TBL_shft_rep16_lvl2_high_0[] = { + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0 +}; + +/* constant table shft_rep16_lvl2_low */ +static const unsigned CONST_TBL_shft_rep16_lvl2_low_0[] = { + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0 +}; + +/* constant table leadzero_lvl0_es_high */ +static const unsigned CONST_TBL_leadzero_lvl0_es_high_0[] = { + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0 +}; + +/* constant table leadzero_lvl0_st_high */ +static const unsigned CONST_TBL_leadzero_lvl0_st_high_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table leadzero_lvl1_es_high */ +static const unsigned CONST_TBL_leadzero_lvl1_es_high_0[] = { + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0 +}; + +/* constant table leadzero_lvl1_st_high */ +static const unsigned CONST_TBL_leadzero_lvl1_st_high_0[] = { + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0 +}; + +/* constant table leadzero_lvl2_es_high */ +static const unsigned CONST_TBL_leadzero_lvl2_es_high_0[] = { + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table leadzero_lvl2_st_high */ +static const unsigned CONST_TBL_leadzero_lvl2_st_high_0[] = { + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table leadzero_lvl3_high */ +static const unsigned CONST_TBL_leadzero_lvl3_high_0[] = { + 0xffff000, + 0xffff000, + 0xffff000, + 0xffff000, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff000, + 0xffff000, + 0xffff000, + 0xffff000, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff000, + 0xffff000, + 0xffff000, + 0xffff000, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff000, + 0xffff000, + 0xffff000, + 0xffff000, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff0, + 0 +}; + +/* constant table leadzero_lvl4_high */ +static const unsigned CONST_TBL_leadzero_lvl4_high_0[] = { + 0xf0fff, + 0xf0fff, + 0xf0fff, + 0xf0fff, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfff0f000, + 0xfff0f000, + 0xfff0f000, + 0xfff0f000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf, + 0xf, + 0xf, + 0xf, + 0xff, + 0xff, + 0xff, + 0xff, + 0xf0fff, + 0xf0fff, + 0xf0fff, + 0xf0fff, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfff0f000, + 0xfff0f000, + 0xfff0f000, + 0xfff0f000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf, + 0xf, + 0xf, + 0xf, + 0xff, + 0xff, + 0xff, + 0xff, + 0 +}; + +/* constant table leadzero_lvl5_high */ +static const unsigned CONST_TBL_leadzero_lvl5_high_0[] = { + 0xffff0000, + 0xffff0000, + 0xffff0000, + 0xffff0000, + 0xfff00000, + 0xfff00000, + 0xfff00000, + 0xfff00000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0xf, + 0xf, + 0xf, + 0xf, + 0xff, + 0xff, + 0xff, + 0xff, + 0xfff, + 0xfff, + 0xfff, + 0xfff, + 0xffff, + 0xffff, + 0xffff, + 0xffff, + 0xfffff, + 0xfffff, + 0xfffff, + 0xfffff, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfffff000, + 0xfffff000, + 0xfffff000, + 0xfffff000, + 0 +}; + +/* constant table leadzero_lvl0_es_low */ +static const unsigned CONST_TBL_leadzero_lvl0_es_low_0[] = { + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0 +}; + +/* constant table leadzero_lvl0_st_low */ +static const unsigned CONST_TBL_leadzero_lvl0_st_low_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table leadzero_lvl1_es_low */ +static const unsigned CONST_TBL_leadzero_lvl1_es_low_0[] = { + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0 +}; + +/* constant table leadzero_lvl1_st_low */ +static const unsigned CONST_TBL_leadzero_lvl1_st_low_0[] = { + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0 +}; + +/* constant table leadzero_lvl2_es_low */ +static const unsigned CONST_TBL_leadzero_lvl2_es_low_0[] = { + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table leadzero_lvl2_st_low */ +static const unsigned CONST_TBL_leadzero_lvl2_st_low_0[] = { + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table leadzero_lvl3_low */ +static const unsigned CONST_TBL_leadzero_lvl3_low_0[] = { + 0xffff000, + 0xffff000, + 0xffff000, + 0xffff000, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff000, + 0xffff000, + 0xffff000, + 0xffff000, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff000, + 0xffff000, + 0xffff000, + 0xffff000, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff000, + 0xffff000, + 0xffff000, + 0xffff000, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff0, + 0 +}; + +/* constant table leadzero_lvl4_low */ +static const unsigned CONST_TBL_leadzero_lvl4_low_0[] = { + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf, + 0xf, + 0xf, + 0xf, + 0xff, + 0xff, + 0xff, + 0xff, + 0xf0fff, + 0xf0fff, + 0xf0fff, + 0xf0fff, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfff0f000, + 0xfff0f000, + 0xfff0f000, + 0xfff0f000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf, + 0xf, + 0xf, + 0xf, + 0xff, + 0xff, + 0xff, + 0xff, + 0xf0fff, + 0xf0fff, + 0xf0fff, + 0xf0fff, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfff0f000, + 0xfff0f000, + 0xfff0f000, + 0xfff0f000, + 0 +}; + +/* constant table leadzero_lvl5_low */ +static const unsigned CONST_TBL_leadzero_lvl5_low_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0xf, + 0xf, + 0xf, + 0xf, + 0xff, + 0xff, + 0xff, + 0xff, + 0xfff, + 0xfff, + 0xfff, + 0xfff, + 0xffff, + 0xffff, + 0xffff, + 0xffff, + 0xfffff, + 0xfffff, + 0xfffff, + 0xfffff, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfffff000, + 0xfffff000, + 0xfffff000, + 0xfffff000, + 0xffff0000, + 0xffff0000, + 0xffff0000, + 0xffff0000, + 0xfff00000, + 0xfff00000, + 0xfff00000, + 0xfff00000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_0 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_0_0[] = { + 0x1060000, + 0xc3081000, + 0xc2081040, + 0x30c2081, + 0xa186081f, + 0x6081f7de, + 0x41800800, + 0x440c2040, + 0x82041000, + 0x82041000, + 0x20041000, + 0x4041000, + 0x41820000, + 0x4082000, + 0x82041000, + 0x1060000, + 0xcd4b2f5, + 0xd3491410, + 0xcd75d34, + 0xb2c71c30, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_1 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_1_0[] = { + 0x30e10828, + 0x71861440, + 0x51441030, + 0x61851441, + 0x49238e28, + 0x38e28a18, + 0x28828418, + 0xa2481c61, + 0x18200c30, + 0x71860c30, + 0x30828618, + 0x92081451, + 0x20828610, + 0xa2081861, + 0x18200c30, + 0x30e10828, + 0xed8d3763, + 0x75965544, + 0xf38e34d3, + 0x7db6cf3c, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_2 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_2_0[] = { + 0x16210484, + 0x2ca24920, + 0x2071c618, + 0x2482071c, + 0x9e69a596, + 0x9a596492, + 0x8c38c388, + 0x3ce34c2c, + 0x14510486, + 0x2492081c, + 0x8e38a20c, + 0x34d30c24, + 0x8e30c38a, + 0x38e30c28, + 0x8e38a286, + 0x16210484, + 0xdcf3f738, + 0x6da65961, + 0xdf7db63c, + 0xe79e38df, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_3 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_3_0[] = { + 0xe3186885, + 0xcf38d30c, + 0xca289248, + 0xb2ca289, + 0xa9a68a27, + 0x68a279e6, + 0x45904904, + 0x544d2450, + 0xa21c7186, + 0x8e34d30c, + 0x24145104, + 0x14451410, + 0x45924104, + 0x14492410, + 0x86145104, + 0xe3186885, + 0x11478410, + 0xdf79d71c, + 0x92451410, + 0xbef7df3c, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_4 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_4_0[] = { + 0x42088c71, + 0x34924503, + 0xd34c30b2, + 0xe38d34c3, + 0xcb2baeaa, + 0xbaeaaa9a, + 0x69869459, + 0xa6585d65, + 0x92088e38, + 0x34923cf3, + 0x71869659, + 0x96185555, + 0x61869651, + 0xa6185965, + 0x59241c71, + 0x42088c71, + 0x34f9492e, + 0x38a28607, + 0x9e384d34, + 0x3082ffff, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_5 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_5_0[] = { + 0x28a90926, + 0x5d655551, + 0x40f3ce38, + 0x45040f3c, + 0xbeebadb6, + 0xbadb6cb2, + 0x9c79c798, + 0x7de75c6d, + 0x2cb28a24, + 0x5555144d, + 0x9e79a61c, + 0x75d71c65, + 0x9e71c79a, + 0x79e71c69, + 0x9e79a696, + 0x28a90926, + 0x57a514e5, + 0x9e696592, + 0x555514e7, + 0x1451040c, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_6 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_6_0[] = { + 0xc94b2e5, + 0xdb699618, + 0xd2491450, + 0x134d2491, + 0xb1c70c2f, + 0x70c2fbee, + 0x49a08a08, + 0x648e2860, + 0xc965924, + 0x9a659618, + 0x28249208, + 0x24861820, + 0x49a28208, + 0x248a2820, + 0x8a249208, + 0xc94b2e5, + 0xfb596e95, + 0xebaa9a28, + 0xba5d7596, + 0x8a249208, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_7 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_7_0[] = { + 0xe98d3663, + 0xf79e75c6, + 0x55545134, + 0x65955545, + 0x4d33cf2c, + 0x3cf2cb1c, + 0xaa8aa49a, + 0xaa689e69, + 0xf38e34d3, + 0xf79e6db6, + 0xb28aa69a, + 0x9a289659, + 0xa28aa692, + 0xaa289a69, + 0x9a282cb2, + 0xe98d3663, + 0xc618ed75, + 0xfbaeb6ca, + 0x9618efbe, + 0xf38e2cb2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_8 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_8_0[] = { + 0x9cf3e738, + 0x8e286181, + 0x6175d659, + 0x6586175d, + 0xdf6db5d7, + 0xdb5d74d3, + 0xacbacba8, + 0xbeeb6cae, + 0x9e79a63c, + 0x8618207d, + 0xaebaaa2c, + 0xb6db2ca6, + 0xaeb2cbaa, + 0xbaeb2caa, + 0xaebaaaa6, + 0x9cf3e738, + 0x69af1967, + 0xcf2c71c2, + 0x6db69a65, + 0x4514103c, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_9 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_9_0[] = { + 0x11468410, + 0xe79a5924, + 0xda699658, + 0x1b6da699, + 0xb9e78e37, + 0x78e37df6, + 0x4db0cb0c, + 0x74cf2c70, + 0x92451410, + 0xa6965924, + 0x2c34d30c, + 0x34c71c30, + 0x4db2c30c, + 0x34cb2c30, + 0x8e34d30c, + 0x11468410, + 0x1cf5b6fd, + 0xf7db5d34, + 0x1cf7df3c, + 0x96555514, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_10 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_10_0[] = { + 0x34e9492a, + 0xbaaaa689, + 0xd75c71b6, + 0xe79d75c7, + 0xcf3befae, + 0xbefaeb9e, + 0xeb8eb4db, + 0xae78df6d, + 0x9a284d34, + 0xbaaa9e79, + 0xf38eb6db, + 0x9e38d75d, + 0xe38eb6d3, + 0xae38db6d, + 0xdb2c3cf3, + 0x34e9492a, + 0xef9d77e7, + 0xbebae78d, + 0xf79e75d7, + 0xb69a5d75, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_11 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_11_0[] = { + 0x56a514a5, + 0xbeeb6db2, + 0x81f7de79, + 0x86081f7d, + 0xffefbdf7, + 0xfbdf7cf3, + 0xbcfbcfb8, + 0xffef7cef, + 0x555514a6, + 0xb6db2cae, + 0xbefbae3c, + 0xf7df3ce7, + 0xbef3cfba, + 0xfbef3ceb, + 0xbefbaeb6, + 0x56a514a5, + 0xfdf7ff79, + 0xffef7df3, + 0xffffbe7d, + 0x75d71c6d, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_lsb_8b_0 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_lsb_8b_0_0[] = { + 0xb2cb2cb2, + 0x66666666, + 0x55555555, + 0x55555555, + 0x55555555, + 0x55555555, + 0xcccccccc, + 0, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xb2cb2cb2, + 0x2cb2cb2c, + 0x66666666, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_lsb_8b_1 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_lsb_8b_1_0[] = { + 0x2cb2cb2c, + 0x66666666, + 0x55555555, + 0x55555555, + 0x55555555, + 0x55555555, + 0xcccccccc, + 0, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0x2cb2cb2c, + 0xcb2cb2cb, + 0x66666666, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_0 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_0_0[] = { + 0xeb596a95, + 0x7144081, + 0xc3082041, + 0x40c3082, + 0x618207df, + 0x207df79e, + 0x51c10c10, + 0x440c2040, + 0xaa5d7596, + 0x8a145104, + 0x30451410, + 0x860c3082, + 0x51c30410, + 0x450c3041, + 0x92451410, + 0xeb596a95, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_1 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_1_0[] = { + 0xc618ad75, + 0x38d2ca2, + 0x61451040, + 0x71861451, + 0x48e38a28, + 0x38a28618, + 0x2c92c51c, + 0xa2481c61, + 0x9618aeba, + 0x14102cb2, + 0x3492c71c, + 0xb28a1c71, + 0x2492c714, + 0xb2491c71, + 0x1c304d34, + 0xc618ad75, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_2 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_2_0[] = { + 0x69ab1966, + 0x5d651345, + 0x2081c718, + 0x2492081c, + 0x9a696592, + 0x9659248e, + 0xcd3cd3c9, + 0x3ce34c2c, + 0x6db69a65, + 0x5d759645, + 0xcf3cb24d, + 0x3cf38e2c, + 0xcf34d3cb, + 0x3cf34d2c, + 0xcf3cb2c7, + 0x69ab1966, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_3 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_3_0[] = { + 0x1cb5b6ed, + 0x1f75c699, + 0xcb28a249, + 0xc2cb28a, + 0x69a289e7, + 0x289e79a6, + 0x55d14d14, + 0x544d2450, + 0x1cb6db2c, + 0xa275d71c, + 0x34555514, + 0x964d3492, + 0x55d34514, + 0x554d3451, + 0x96555514, + 0x1cb5b6ed, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_4 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_4_0[] = { + 0xeb9d76e7, + 0x89a58e28, + 0xe34d30c2, + 0xf38e34d3, + 0xcaebaaaa, + 0xbaaaa69a, + 0x6d96d55d, + 0xa6585d65, + 0xf79e75d7, + 0x9a288e38, + 0x7596d75d, + 0xb69a5d75, + 0x6596d755, + 0xb6595d75, + 0x5d345d75, + 0xeb9d76e7, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_5 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_5_0[] = { + 0xbdf7ef79, + 0xbeeb2ba6, + 0x4103cf38, + 0x4514103c, + 0xbaeb6db2, + 0xb6db2cae, + 0xdd7dd7d9, + 0x7de75c6d, + 0xbefbae7d, + 0xbefbaea6, + 0xdf7db65d, + 0x7df79e6d, + 0xdf75d7db, + 0x7df75d6d, + 0xdf7db6d7, + 0xbdf7ef79, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_6 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_6_0[] = { + 0x1070000, + 0x17554491, + 0xd3492451, + 0x144d3492, + 0x71c30bef, + 0x30befbae, + 0x59e18e18, + 0x648e2860, + 0x82041000, + 0xbad75d34, + 0x38659618, + 0xa68e38a2, + 0x59e38618, + 0x658e3861, + 0x9a659618, + 0x1070000, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_7 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_7_0[] = { + 0x30f1082c, + 0x79d6da6, + 0x65555144, + 0x75965555, + 0x4cf3cb2c, + 0x3cb2c71c, + 0xae9ae59e, + 0xaa689e69, + 0x1c300c30, + 0x1000efbe, + 0xb69ae79e, + 0xbaaa9e79, + 0xa69ae796, + 0xba699e79, + 0x9e386db6, + 0x30f1082c, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_8 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_8_0[] = { + 0x172104c4, + 0x9e692386, + 0x6185d759, + 0x6596185d, + 0xdb6d75d3, + 0xd75d34cf, + 0xedbedbe9, + 0xbeeb6cae, + 0x145104c7, + 0x1c718604, + 0xefbeba6d, + 0xbefbaeae, + 0xefb6dbeb, + 0xbefb6dae, + 0xefbebae7, + 0x172104c4, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_9 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_9_0[] = { + 0xf3186c85, + 0x2fb6caa9, + 0xdb69a659, + 0x1c6db69a, + 0x79e38df7, + 0x38df7db6, + 0x5df1cf1c, + 0x74cf2c70, + 0xb21c7186, + 0x9234d30c, + 0x3c75d71c, + 0xb6cf3cb2, + 0x5df3c71c, + 0x75cf3c71, + 0x9e75d71c, + 0xf3186c85, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_10 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_10_0[] = { + 0x4208cc71, + 0x8db5cf2c, + 0xe75d71c6, + 0xf79e75d7, + 0xcefbebae, + 0xbebae79e, + 0xef9ef5df, + 0xae78df6d, + 0x9208cf3c, + 0x96184d34, + 0xf79ef7df, + 0xbebadf7d, + 0xe79ef7d7, + 0xbe79df7d, + 0xdf3c7df7, + 0x4208cc71, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_11 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_11_0[] = { + 0x28ad0927, + 0xffef3be7, + 0x8207df79, + 0x8618207d, + 0xfbef7df3, + 0xf7df3cef, + 0xfdffdff9, + 0xffef7cef, + 0x2cb28a24, + 0x7df79e65, + 0xffffbe7d, + 0xffffbeef, + 0xfff7dffb, + 0xffff7def, + 0xffffbef7, + 0x28ad0927, + 0 +}; + +/* constant table ivp_sem_dseli_hi_lsb_8b_0 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_lsb_8b_0_0[] = { + 0xcb2cb2cb, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xcccccccc, + 0xffffffff, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xcb2cb2cb, + 0 +}; + +/* constant table ivp_sem_dseli_hi_lsb_8b_1 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_lsb_8b_1_0[] = { + 0xb2cb2cb2, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xcccccccc, + 0xffffffff, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xb2cb2cb2, + 0 +}; + +/* constant table ivp_sem_special_seli8_0 */ +static const unsigned CONST_TBL_ivp_sem_special_seli8_0_0[] = { + 0x86082fbe, + 0x4f3cf3c, + 0xbafbeeba, + 0x38e38e38, + 0, + 0, + 0, + 0, + 0x82186082, + 0xc104104, + 0x8e28a186, + 0x8208208, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x4704307f, + 0xc11c10c1, + 0xc50fdffd, + 0x43147143, + 0x7bf7ff7b, + 0xcd2c51c5, + 0xf9ff9ef9, + 0x4f24b247, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_special_seli8_1 */ +static const unsigned CONST_TBL_ivp_sem_special_seli8_1_0[] = { + 0x238e0821, + 0xc30c1041, + 0xe28a186e, + 0x8208e38e, + 0, + 0, + 0, + 0, + 0x608238e0, + 0x410430c3, + 0xa18628a3, + 0x86182082, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x304f0430, + 0x10c13c10, + 0xd3cd0c51, + 0x714334f3, + 0xf34b1471, + 0x51c52cd3, + 0x92c91f9e, + 0xb64724b2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_special_seli8_2 */ +static const unsigned CONST_TBL_ivp_sem_special_seli8_2_0[] = { + 0x8218608, + 0x10410430, + 0x18628a38, + 0x20820820, + 0, + 0, + 0, + 0, + 0x79e08218, + 0x71c71c10, + 0x69a79e69, + 0x61861861, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x4304704, + 0x7c10c11c, + 0xc51c50c, + 0x75f74314, + 0x14714b34, + 0x6dd7dd6c, + 0x1c92c93c, + 0x65b65f65, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_special_seli8_3 */ +static const unsigned CONST_TBL_ivp_sem_special_seli8_3_0[] = { + 0x8608279e, + 0x471c71c, + 0x9a79e69a, + 0x18618618, + 0, + 0, + 0, + 0, + 0x82186082, + 0xc104104, + 0x8e28a186, + 0x8208208, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x4704305f, + 0xc11c10c1, + 0xc50dd7dd, + 0x43147143, + 0x5b75f75b, + 0xcd2c51c5, + 0xd97d96d9, + 0x4f24b247, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_special_seli8_4 */ +static const unsigned CONST_TBL_ivp_sem_special_seli8_4_0[] = { + 0x238e0821, + 0xc30c1041, + 0xe28a1866, + 0x82086186, + 0, + 0, + 0, + 0, + 0x608238e0, + 0x410430c3, + 0xa18628a3, + 0x8e382082, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x304f0430, + 0x10c13c10, + 0xd3cd0c51, + 0x714334f3, + 0xf34b1471, + 0x51c52cd3, + 0x92c91d96, + 0xbe4724b2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_special_seli8_5 */ +static const unsigned CONST_TBL_ivp_sem_special_seli8_5_0[] = { + 0x8218608, + 0x10410430, + 0x18628a38, + 0x20820820, + 0, + 0, + 0, + 0, + 0xfbe08218, + 0xf3cf3c10, + 0xebafbeeb, + 0xe38e38e3, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x4304704, + 0xfc10c11c, + 0xc51c50c, + 0xf7ff4314, + 0x14714b34, + 0xefdffdec, + 0x1c92c93c, + 0xe7be7fe7, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_special_seli8_msb_0 */ +static const unsigned CONST_TBL_ivp_sem_special_seli8_msb_0_0[] = { + 0x3, + 0xf, + 0x3f, + 0xff, + 0, + 0, + 0, + 0, + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0, + 0, + 0, + 0, + 0, + 0x11111111, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0x1, + 0xffffffff, + 0x7, + 0xffffffff, + 0x1f, + 0xffffffff, + 0x7f, + 0xffffffff, + 0xcccccccc, + 0xcccccccd, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_special_seli8_msb_1 */ +static const unsigned CONST_TBL_ivp_sem_special_seli8_msb_1_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x3fffffff, + 0xfffffff, + 0x3ffffff, + 0xffffff, + 0, + 0, + 0, + 0, + 0, + 0x11111111, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0, + 0x7fffffff, + 0, + 0x1fffffff, + 0, + 0x7ffffff, + 0, + 0x1ffffff, + 0xcccccccc, + 0xcccccccd, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + + +/* Instruction operands. */ + +static int +OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_out_0; + unsigned soffsetx4_in_0; + soffsetx4_in_0 = *valp & 0x3ffff; + soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); + *valp = soffsetx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) +{ + unsigned soffsetx4_in_0; + unsigned soffsetx4_out_0; + soffsetx4_out_0 = *valp; + soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; + *valp = soffsetx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_out_0; + unsigned uimm12x8_in_0; + uimm12x8_in_0 = *valp & 0xfff; + uimm12x8_out_0 = uimm12x8_in_0 << 3; + *valp = uimm12x8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) +{ + unsigned uimm12x8_in_0; + unsigned uimm12x8_out_0; + uimm12x8_out_0 = *valp; + uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); + *valp = uimm12x8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_decode (uint32 *valp) +{ + unsigned simm4_out_0; + unsigned simm4_in_0; + simm4_in_0 = *valp & 0xf; + simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; + *valp = simm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_encode (uint32 *valp) +{ + unsigned simm4_in_0; + unsigned simm4_out_0; + simm4_out_0 = *valp; + simm4_in_0 = (simm4_out_0 & 0xf); + *valp = simm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_0_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_1_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_2_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_3_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_4_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_out_0; + unsigned immrx4_in_0; + immrx4_in_0 = *valp & 0xf; + immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; + *valp = immrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immrx4_encode (uint32 *valp) +{ + unsigned immrx4_in_0; + unsigned immrx4_out_0; + immrx4_out_0 = *valp; + immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); + *valp = immrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_out_0; + unsigned lsi4x4_in_0; + lsi4x4_in_0 = *valp & 0xf; + lsi4x4_out_0 = lsi4x4_in_0 << 2; + *valp = lsi4x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) +{ + unsigned lsi4x4_in_0; + unsigned lsi4x4_out_0; + lsi4x4_out_0 = *valp; + lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); + *valp = lsi4x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_decode (uint32 *valp) +{ + unsigned simm7_out_0; + unsigned simm7_in_0; + simm7_in_0 = *valp & 0x7f; + simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; + *valp = simm7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_encode (uint32 *valp) +{ + unsigned simm7_in_0; + unsigned simm7_out_0; + simm7_out_0 = *valp; + simm7_in_0 = (simm7_out_0 & 0x7f); + *valp = simm7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_out_0; + unsigned uimm6_in_0; + uimm6_in_0 = *valp & 0x3f; + uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); + *valp = uimm6_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_encode (uint32 *valp) +{ + unsigned uimm6_in_0; + unsigned uimm6_out_0; + uimm6_out_0 = *valp; + uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; + *valp = uimm6_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_out_0; + unsigned ai4const_in_0; + ai4const_in_0 = *valp & 0xf; + ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; + *valp = ai4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_encode (uint32 *valp) +{ + unsigned ai4const_in_0; + unsigned ai4const_out_0; + ai4const_out_0 = *valp; + switch (ai4const_out_0) + { + case 0xffffffff: ai4const_in_0 = 0; break; + case 0x1: ai4const_in_0 = 0x1; break; + case 0x2: ai4const_in_0 = 0x2; break; + case 0x3: ai4const_in_0 = 0x3; break; + case 0x4: ai4const_in_0 = 0x4; break; + case 0x5: ai4const_in_0 = 0x5; break; + case 0x6: ai4const_in_0 = 0x6; break; + case 0x7: ai4const_in_0 = 0x7; break; + case 0x8: ai4const_in_0 = 0x8; break; + case 0x9: ai4const_in_0 = 0x9; break; + case 0xa: ai4const_in_0 = 0xa; break; + case 0xb: ai4const_in_0 = 0xb; break; + case 0xc: ai4const_in_0 = 0xc; break; + case 0xd: ai4const_in_0 = 0xd; break; + case 0xe: ai4const_in_0 = 0xe; break; + default: ai4const_in_0 = 0xf; break; + } + *valp = ai4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_decode (uint32 *valp) +{ + unsigned b4const_out_0; + unsigned b4const_in_0; + b4const_in_0 = *valp & 0xf; + b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; + *valp = b4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_encode (uint32 *valp) +{ + unsigned b4const_in_0; + unsigned b4const_out_0; + b4const_out_0 = *valp; + switch (b4const_out_0) + { + case 0xffffffff: b4const_in_0 = 0; break; + case 0x1: b4const_in_0 = 0x1; break; + case 0x2: b4const_in_0 = 0x2; break; + case 0x3: b4const_in_0 = 0x3; break; + case 0x4: b4const_in_0 = 0x4; break; + case 0x5: b4const_in_0 = 0x5; break; + case 0x6: b4const_in_0 = 0x6; break; + case 0x7: b4const_in_0 = 0x7; break; + case 0x8: b4const_in_0 = 0x8; break; + case 0xa: b4const_in_0 = 0x9; break; + case 0xc: b4const_in_0 = 0xa; break; + case 0x10: b4const_in_0 = 0xb; break; + case 0x20: b4const_in_0 = 0xc; break; + case 0x40: b4const_in_0 = 0xd; break; + case 0x80: b4const_in_0 = 0xe; break; + default: b4const_in_0 = 0xf; break; + } + *valp = b4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_out_0; + unsigned b4constu_in_0; + b4constu_in_0 = *valp & 0xf; + b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; + *valp = b4constu_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_encode (uint32 *valp) +{ + unsigned b4constu_in_0; + unsigned b4constu_out_0; + b4constu_out_0 = *valp; + switch (b4constu_out_0) + { + case 0x8000: b4constu_in_0 = 0; break; + case 0x10000: b4constu_in_0 = 0x1; break; + case 0x2: b4constu_in_0 = 0x2; break; + case 0x3: b4constu_in_0 = 0x3; break; + case 0x4: b4constu_in_0 = 0x4; break; + case 0x5: b4constu_in_0 = 0x5; break; + case 0x6: b4constu_in_0 = 0x6; break; + case 0x7: b4constu_in_0 = 0x7; break; + case 0x8: b4constu_in_0 = 0x8; break; + case 0xa: b4constu_in_0 = 0x9; break; + case 0xc: b4constu_in_0 = 0xa; break; + case 0x10: b4constu_in_0 = 0xb; break; + case 0x20: b4constu_in_0 = 0xc; break; + case 0x40: b4constu_in_0 = 0xd; break; + case 0x80: b4constu_in_0 = 0xe; break; + default: b4constu_in_0 = 0xf; break; + } + *valp = b4constu_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_out_0; + unsigned uimm8_in_0; + uimm8_in_0 = *valp & 0xff; + uimm8_out_0 = uimm8_in_0; + *valp = uimm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_encode (uint32 *valp) +{ + unsigned uimm8_in_0; + unsigned uimm8_out_0; + uimm8_out_0 = *valp; + uimm8_in_0 = (uimm8_out_0 & 0xff); + *valp = uimm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_out_0; + unsigned uimm8x2_in_0; + uimm8x2_in_0 = *valp & 0xff; + uimm8x2_out_0 = uimm8x2_in_0 << 1; + *valp = uimm8x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) +{ + unsigned uimm8x2_in_0; + unsigned uimm8x2_out_0; + uimm8x2_out_0 = *valp; + uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); + *valp = uimm8x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_out_0; + unsigned uimm8x4_in_0; + uimm8x4_in_0 = *valp & 0xff; + uimm8x4_out_0 = uimm8x4_in_0 << 2; + *valp = uimm8x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) +{ + unsigned uimm8x4_in_0; + unsigned uimm8x4_out_0; + uimm8x4_out_0 = *valp; + uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); + *valp = uimm8x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_out_0; + unsigned uimm4x16_in_0; + uimm4x16_in_0 = *valp & 0xf; + uimm4x16_out_0 = uimm4x16_in_0 << 4; + *valp = uimm4x16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) +{ + unsigned uimm4x16_in_0; + unsigned uimm4x16_out_0; + uimm4x16_out_0 = *valp; + uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); + *valp = uimm4x16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp) +{ + unsigned uimmrx4_out_0; + unsigned uimmrx4_in_0; + uimmrx4_in_0 = *valp & 0xf; + uimmrx4_out_0 = uimmrx4_in_0 << 2; + *valp = uimmrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp) +{ + unsigned uimmrx4_in_0; + unsigned uimmrx4_out_0; + uimmrx4_out_0 = *valp; + uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf); + *valp = uimmrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_decode (uint32 *valp) +{ + unsigned simm8_out_0; + unsigned simm8_in_0; + simm8_in_0 = *valp & 0xff; + simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; + *valp = simm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_encode (uint32 *valp) +{ + unsigned simm8_in_0; + unsigned simm8_out_0; + simm8_out_0 = *valp; + simm8_in_0 = (simm8_out_0 & 0xff); + *valp = simm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_out_0; + unsigned simm8x256_in_0; + simm8x256_in_0 = *valp & 0xff; + simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; + *valp = simm8x256_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) +{ + unsigned simm8x256_in_0; + unsigned simm8x256_out_0; + simm8x256_out_0 = *valp; + simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); + *valp = simm8x256_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_out_0; + unsigned simm12b_in_0; + simm12b_in_0 = *valp & 0xfff; + simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; + *valp = simm12b_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_encode (uint32 *valp) +{ + unsigned simm12b_in_0; + unsigned simm12b_out_0; + simm12b_out_0 = *valp; + simm12b_in_0 = (simm12b_out_0 & 0xfff); + *valp = simm12b_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_out_0; + unsigned msalp32_in_0; + msalp32_in_0 = *valp & 0x1f; + msalp32_out_0 = 0x20 - msalp32_in_0; + *valp = msalp32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_encode (uint32 *valp) +{ + unsigned msalp32_in_0; + unsigned msalp32_out_0; + msalp32_out_0 = *valp; + msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; + *valp = msalp32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_out_0; + unsigned op2p1_in_0; + op2p1_in_0 = *valp & 0xf; + op2p1_out_0 = op2p1_in_0 + 0x1; + *valp = op2p1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_encode (uint32 *valp) +{ + unsigned op2p1_in_0; + unsigned op2p1_out_0; + op2p1_out_0 = *valp; + op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; + *valp = op2p1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_decode (uint32 *valp) +{ + unsigned label8_out_0; + unsigned label8_in_0; + label8_in_0 = *valp & 0xff; + label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); + *valp = label8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_encode (uint32 *valp) +{ + unsigned label8_in_0; + unsigned label8_out_0; + label8_out_0 = *valp; + label8_in_0 = (label8_out_0 - 0x4) & 0xff; + *valp = label8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_out_0; + unsigned ulabel8_in_0; + ulabel8_in_0 = *valp & 0xff; + ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); + *valp = ulabel8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) +{ + unsigned ulabel8_in_0; + unsigned ulabel8_out_0; + ulabel8_out_0 = *valp; + ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; + *valp = ulabel8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_decode (uint32 *valp) +{ + unsigned label12_out_0; + unsigned label12_in_0; + label12_in_0 = *valp & 0xfff; + label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); + *valp = label12_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_encode (uint32 *valp) +{ + unsigned label12_in_0; + unsigned label12_out_0; + label12_out_0 = *valp; + label12_in_0 = (label12_out_0 - 0x4) & 0xfff; + *valp = label12_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_decode (uint32 *valp) +{ + unsigned soffset_out_0; + unsigned soffset_in_0; + soffset_in_0 = *valp & 0x3ffff; + soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); + *valp = soffset_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_encode (uint32 *valp) +{ + unsigned soffset_in_0; + unsigned soffset_out_0; + soffset_out_0 = *valp; + soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; + *valp = soffset_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_out_0; + unsigned uimm16x4_in_0; + uimm16x4_in_0 = *valp & 0xffff; + uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; + *valp = uimm16x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) +{ + unsigned uimm16x4_in_0; + unsigned uimm16x4_out_0; + uimm16x4_out_0 = *valp; + uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; + *valp = uimm16x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_decode (uint32 *valp) +{ + unsigned bbi_out_0; + unsigned bbi_in_0; + bbi_in_0 = *valp & 0x1f; + bbi_out_0 = (0 << 5) | bbi_in_0; + *valp = bbi_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_encode (uint32 *valp) +{ + unsigned bbi_in_0; + unsigned bbi_out_0; + bbi_out_0 = *valp; + bbi_in_0 = (bbi_out_0 & 0x1f); + *valp = bbi_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_imm16_decode (uint32 *valp) +{ + unsigned imm16_out_0; + unsigned imm16_in_0; + imm16_in_0 = *valp & 0xffff; + imm16_out_0 = (0 << 16) | imm16_in_0; + *valp = imm16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_imm16_encode (uint32 *valp) +{ + unsigned imm16_in_0; + unsigned imm16_out_0; + imm16_out_0 = *valp; + imm16_in_0 = (imm16_out_0 & 0xffff); + *valp = imm16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_decode (uint32 *valp) +{ + unsigned s_out_0; + unsigned s_in_0; + s_in_0 = *valp & 0xf; + s_out_0 = (0 << 4) | s_in_0; + *valp = s_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_encode (uint32 *valp) +{ + unsigned s_in_0; + unsigned s_out_0; + s_out_0 = *valp; + s_in_0 = (s_out_0 & 0xf); + *valp = s_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_decode (uint32 *valp) +{ + unsigned immt_out_0; + unsigned immt_in_0; + immt_in_0 = *valp & 0xf; + immt_out_0 = immt_in_0; + *valp = immt_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_encode (uint32 *valp) +{ + unsigned immt_in_0; + unsigned immt_out_0; + immt_out_0 = *valp; + immt_in_0 = immt_out_0 & 0xf; + *valp = immt_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_BR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16); + return error; +} + +static int +OperandSem_opnd_sem_BR2_decode (uint32 *valp) +{ + *valp = *valp << 1; + return 0; +} + +static int +OperandSem_opnd_sem_BR2_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 1) != 0); + *valp = *valp >> 1; + return error; +} + +static int +OperandSem_opnd_sem_BR4_decode (uint32 *valp) +{ + *valp = *valp << 2; + return 0; +} + +static int +OperandSem_opnd_sem_BR4_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 3) != 0); + *valp = *valp >> 2; + return error; +} + +static int +OperandSem_opnd_sem_BR8_decode (uint32 *valp) +{ + *valp = *valp << 3; + return 0; +} + +static int +OperandSem_opnd_sem_BR8_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 7) != 0); + *valp = *valp >> 3; + return error; +} + +static int +OperandSem_opnd_sem_BR16_decode (uint32 *valp) +{ + *valp = *valp << 4; + return 0; +} + +static int +OperandSem_opnd_sem_BR16_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 15) != 0); + *valp = *valp >> 4; + return error; +} + +static int +OperandSem_opnd_sem_tp7_decode (uint32 *valp) +{ + unsigned tp7_out_0; + unsigned tp7_in_0; + tp7_in_0 = *valp & 0xf; + tp7_out_0 = tp7_in_0 + 0x7; + *valp = tp7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_tp7_encode (uint32 *valp) +{ + unsigned tp7_in_0; + unsigned tp7_out_0; + tp7_out_0 = *valp; + tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; + *valp = tp7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_out_0; + unsigned xt_wbr15_label_in_0; + xt_wbr15_label_in_0 = *valp & 0x7fff; + xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); + *valp = xt_wbr15_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_label_in_0; + unsigned xt_wbr15_label_out_0; + xt_wbr15_label_out_0 = *valp; + xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp) +{ + unsigned xt_wbr18_label_out_0; + unsigned xt_wbr18_label_in_0; + xt_wbr18_label_in_0 = *valp & 0x3ffff; + xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14); + *valp = xt_wbr18_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp) +{ + unsigned xt_wbr18_label_in_0; + unsigned xt_wbr18_label_out_0; + xt_wbr18_label_out_0 = *valp; + xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff; + *valp = xt_wbr18_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_vec_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_vec_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_vbool_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_vbool_encode (uint32 *valp) +{ + int error; + error = (*valp >= 8); + return error; +} + +static int +OperandSem_opnd_sem_wvec_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_wvec_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_divide_lane_ctrl_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_divide_lane_ctrl_out_0; + unsigned opnd_ivp_sem_divide_lane_ctrl_in_0; + opnd_ivp_sem_divide_lane_ctrl_in_0 = *valp & 0x1; + opnd_ivp_sem_divide_lane_ctrl_out_0 = (0 << 1) | opnd_ivp_sem_divide_lane_ctrl_in_0; + *valp = opnd_ivp_sem_divide_lane_ctrl_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_divide_lane_ctrl_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_divide_lane_ctrl_in_0; + unsigned opnd_ivp_sem_divide_lane_ctrl_out_0; + opnd_ivp_sem_divide_lane_ctrl_out_0 = *valp; + opnd_ivp_sem_divide_lane_ctrl_in_0 = (((opnd_ivp_sem_divide_lane_ctrl_out_0 >> 0) & 1)) & 0x1; + *valp = opnd_ivp_sem_divide_lane_ctrl_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_i_imm4_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_vec_mov_i_imm4_out_0; + unsigned opnd_ivp_sem_vec_mov_i_imm4_in_0; + opnd_ivp_sem_vec_mov_i_imm4_in_0 = *valp & 0xf; + opnd_ivp_sem_vec_mov_i_imm4_out_0 = (0 << 4) | opnd_ivp_sem_vec_mov_i_imm4_in_0; + *valp = opnd_ivp_sem_vec_mov_i_imm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_i_imm4_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_vec_mov_i_imm4_in_0; + unsigned opnd_ivp_sem_vec_mov_i_imm4_out_0; + opnd_ivp_sem_vec_mov_i_imm4_out_0 = *valp; + opnd_ivp_sem_vec_mov_i_imm4_in_0 = (opnd_ivp_sem_vec_mov_i_imm4_out_0 & 0xf); + *valp = opnd_ivp_sem_vec_mov_i_imm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_vec_select_slct_h_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_vec_select_slct_h_out_0; + unsigned opnd_ivp_sem_vec_select_slct_h_in_0; + opnd_ivp_sem_vec_select_slct_h_in_0 = *valp & 0x3; + opnd_ivp_sem_vec_select_slct_h_out_0 = (0 << 2) | opnd_ivp_sem_vec_select_slct_h_in_0; + *valp = opnd_ivp_sem_vec_select_slct_h_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_vec_select_slct_h_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_vec_select_slct_h_in_0; + unsigned opnd_ivp_sem_vec_select_slct_h_out_0; + opnd_ivp_sem_vec_select_slct_h_out_0 = *valp; + opnd_ivp_sem_vec_select_slct_h_in_0 = (opnd_ivp_sem_vec_select_slct_h_out_0 & 0x3); + *valp = opnd_ivp_sem_vec_select_slct_h_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm4_decode (uint32 *valp) +{ + unsigned saimm4_out_0; + unsigned saimm4_in_0; + saimm4_in_0 = *valp & 0x7; + saimm4_out_0 = (0 << 3) | saimm4_in_0; + *valp = saimm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm4_encode (uint32 *valp) +{ + unsigned saimm4_in_0; + unsigned saimm4_out_0; + saimm4_out_0 = *valp; + saimm4_in_0 = (saimm4_out_0 & 0x7); + *valp = saimm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm5_decode (uint32 *valp) +{ + unsigned saimm5_out_0; + unsigned saimm5_in_0; + saimm5_in_0 = *valp & 0xf; + saimm5_out_0 = (0 << 4) | saimm5_in_0; + *valp = saimm5_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm5_encode (uint32 *valp) +{ + unsigned saimm5_in_0; + unsigned saimm5_out_0; + saimm5_out_0 = *valp; + saimm5_in_0 = (saimm5_out_0 & 0xf); + *valp = saimm5_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm6_31_decode (uint32 *valp) +{ + unsigned saimm6_31_out_0; + unsigned saimm6_31_in_0; + saimm6_31_in_0 = *valp & 0x1f; + saimm6_31_out_0 = (0 << 5) | saimm6_31_in_0; + *valp = saimm6_31_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm6_31_encode (uint32 *valp) +{ + unsigned saimm6_31_in_0; + unsigned saimm6_31_out_0; + saimm6_31_out_0 = *valp; + saimm6_31_in_0 = (saimm6_31_out_0 & 0x1f); + *valp = saimm6_31_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_valign_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_valign_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6_in_0; + opnd_ivp_sem_ld_st_i_bimm6_in_0 = *valp & 0x3f; + opnd_ivp_sem_ld_st_i_bimm6_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm6_in_0 >> 1) & 0x1f)) | 0xffffffe0)) == 0xffffffff))) & 0x3ffffff) << 6) | opnd_ivp_sem_ld_st_i_bimm6_in_0) << 6; + *valp = opnd_ivp_sem_ld_st_i_bimm6_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6_out_0; + opnd_ivp_sem_ld_st_i_bimm6_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm6_in_0 = ((opnd_ivp_sem_ld_st_i_bimm6_out_0 >> 6) & 0x3f); + *valp = opnd_ivp_sem_ld_st_i_bimm6_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4_in_0; + opnd_ivp_sem_ld_st_i_bimm4_in_0 = *valp & 0xf; + opnd_ivp_sem_ld_st_i_bimm4_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm4_in_0 >> 1) & 0x7)) | 0xfffffff8)) == 0xffffffff))) & 0xfffffff) << 4) | opnd_ivp_sem_ld_st_i_bimm4_in_0) << 6; + *valp = opnd_ivp_sem_ld_st_i_bimm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4_out_0; + opnd_ivp_sem_ld_st_i_bimm4_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm4_in_0 = ((opnd_ivp_sem_ld_st_i_bimm4_out_0 >> 6) & 0xf); + *valp = opnd_ivp_sem_ld_st_i_bimm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6b2n_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6b2n_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6b2n_in_0; + opnd_ivp_sem_ld_st_i_bimm6b2n_in_0 = *valp & 0x3f; + opnd_ivp_sem_ld_st_i_bimm6b2n_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm6b2n_in_0 >> 1) & 0x1f)) | 0xffffffe0)) == 0xffffffff))) & 0x3ffffff) << 6) | opnd_ivp_sem_ld_st_i_bimm6b2n_in_0) << 3; + *valp = opnd_ivp_sem_ld_st_i_bimm6b2n_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6b2n_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6b2n_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6b2n_out_0; + opnd_ivp_sem_ld_st_i_bimm6b2n_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm6b2n_in_0 = ((opnd_ivp_sem_ld_st_i_bimm6b2n_out_0 >> 3) & 0x3f); + *valp = opnd_ivp_sem_ld_st_i_bimm6b2n_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4b2n_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4b2n_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4b2n_in_0; + opnd_ivp_sem_ld_st_i_bimm4b2n_in_0 = *valp & 0xf; + opnd_ivp_sem_ld_st_i_bimm4b2n_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm4b2n_in_0 >> 1) & 0x7)) | 0xfffffff8)) == 0xffffffff))) & 0xfffffff) << 4) | opnd_ivp_sem_ld_st_i_bimm4b2n_in_0) << 3; + *valp = opnd_ivp_sem_ld_st_i_bimm4b2n_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4b2n_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4b2n_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4b2n_out_0; + opnd_ivp_sem_ld_st_i_bimm4b2n_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm4b2n_in_0 = ((opnd_ivp_sem_ld_st_i_bimm4b2n_out_0 >> 3) & 0xf); + *valp = opnd_ivp_sem_ld_st_i_bimm4b2n_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_2_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6bn_2_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6bn_2_in_0; + opnd_ivp_sem_ld_st_i_bimm6bn_2_in_0 = *valp & 0x3f; + opnd_ivp_sem_ld_st_i_bimm6bn_2_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm6bn_2_in_0 >> 1) & 0x1f)) | 0xffffffe0)) == 0xffffffff))) & 0x3ffffff) << 6) | opnd_ivp_sem_ld_st_i_bimm6bn_2_in_0) << 1; + *valp = opnd_ivp_sem_ld_st_i_bimm6bn_2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_2_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6bn_2_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6bn_2_out_0; + opnd_ivp_sem_ld_st_i_bimm6bn_2_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm6bn_2_in_0 = ((opnd_ivp_sem_ld_st_i_bimm6bn_2_out_0 >> 1) & 0x3f); + *valp = opnd_ivp_sem_ld_st_i_bimm6bn_2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_2_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4bn_2_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4bn_2_in_0; + opnd_ivp_sem_ld_st_i_bimm4bn_2_in_0 = *valp & 0xf; + opnd_ivp_sem_ld_st_i_bimm4bn_2_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm4bn_2_in_0 >> 1) & 0x7)) | 0xfffffff8)) == 0xffffffff))) & 0xfffffff) << 4) | opnd_ivp_sem_ld_st_i_bimm4bn_2_in_0) << 1; + *valp = opnd_ivp_sem_ld_st_i_bimm4bn_2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_2_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4bn_2_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4bn_2_out_0; + opnd_ivp_sem_ld_st_i_bimm4bn_2_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm4bn_2_in_0 = ((opnd_ivp_sem_ld_st_i_bimm4bn_2_out_0 >> 1) & 0xf); + *valp = opnd_ivp_sem_ld_st_i_bimm4bn_2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6bn_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6bn_in_0; + opnd_ivp_sem_ld_st_i_bimm6bn_in_0 = *valp & 0x3f; + opnd_ivp_sem_ld_st_i_bimm6bn_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm6bn_in_0 >> 1) & 0x1f)) | 0xffffffe0)) == 0xffffffff))) & 0x3ffffff) << 6) | opnd_ivp_sem_ld_st_i_bimm6bn_in_0) << 2; + *valp = opnd_ivp_sem_ld_st_i_bimm6bn_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6bn_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6bn_out_0; + opnd_ivp_sem_ld_st_i_bimm6bn_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm6bn_in_0 = ((opnd_ivp_sem_ld_st_i_bimm6bn_out_0 >> 2) & 0x3f); + *valp = opnd_ivp_sem_ld_st_i_bimm6bn_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4bn_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4bn_in_0; + opnd_ivp_sem_ld_st_i_bimm4bn_in_0 = *valp & 0xf; + opnd_ivp_sem_ld_st_i_bimm4bn_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm4bn_in_0 >> 1) & 0x7)) | 0xfffffff8)) == 0xffffffff))) & 0xfffffff) << 4) | opnd_ivp_sem_ld_st_i_bimm4bn_in_0) << 2; + *valp = opnd_ivp_sem_ld_st_i_bimm4bn_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4bn_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4bn_out_0; + opnd_ivp_sem_ld_st_i_bimm4bn_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm4bn_in_0 = ((opnd_ivp_sem_ld_st_i_bimm4bn_out_0 >> 2) & 0xf); + *valp = opnd_ivp_sem_ld_st_i_bimm4bn_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6x1_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6x1_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6x1_in_0; + opnd_ivp_sem_ld_st_i_bimm6x1_in_0 = *valp & 0x3f; + opnd_ivp_sem_ld_st_i_bimm6x1_out_0 = (((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm6x1_in_0 >> 1) & 0x1f)) | 0xffffffe0)) == 0xffffffff))) & 0x3ffffff) << 6) | opnd_ivp_sem_ld_st_i_bimm6x1_in_0; + *valp = opnd_ivp_sem_ld_st_i_bimm6x1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6x1_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6x1_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6x1_out_0; + opnd_ivp_sem_ld_st_i_bimm6x1_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm6x1_in_0 = (opnd_ivp_sem_ld_st_i_bimm6x1_out_0 & 0x3f); + *valp = opnd_ivp_sem_ld_st_i_bimm6x1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4x1_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4x1_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4x1_in_0; + opnd_ivp_sem_ld_st_i_bimm4x1_in_0 = *valp & 0xf; + opnd_ivp_sem_ld_st_i_bimm4x1_out_0 = (((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm4x1_in_0 >> 1) & 0x7)) | 0xfffffff8)) == 0xffffffff))) & 0xfffffff) << 4) | opnd_ivp_sem_ld_st_i_bimm4x1_in_0; + *valp = opnd_ivp_sem_ld_st_i_bimm4x1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4x1_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4x1_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4x1_out_0; + opnd_ivp_sem_ld_st_i_bimm4x1_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm4x1_in_0 = (opnd_ivp_sem_ld_st_i_bimm4x1_out_0 & 0xf); + *valp = opnd_ivp_sem_ld_st_i_bimm4x1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm8x4_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm8x4_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm8x4_in_0; + opnd_ivp_sem_ld_st_i_bimm8x4_in_0 = *valp & 0xff; + opnd_ivp_sem_ld_st_i_bimm8x4_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm8x4_in_0 >> 1) & 0x7f)) | 0xffffff80)) == 0xffffffff))) & 0xffffff) << 8) | opnd_ivp_sem_ld_st_i_bimm8x4_in_0) << 2; + *valp = opnd_ivp_sem_ld_st_i_bimm8x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm8x4_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm8x4_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm8x4_out_0; + opnd_ivp_sem_ld_st_i_bimm8x4_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm8x4_in_0 = ((opnd_ivp_sem_ld_st_i_bimm8x4_out_0 >> 2) & 0xff); + *valp = opnd_ivp_sem_ld_st_i_bimm8x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_ltrx2nimm_decode (uint32 *valp) +{ + unsigned bbe_ltrx2nimm_out_0; + unsigned bbe_ltrx2nimm_in_0; + bbe_ltrx2nimm_in_0 = *valp & 0x7f; + bbe_ltrx2nimm_out_0 = CONST_TBL_bbe_ltrx2nimm_tab_0[bbe_ltrx2nimm_in_0 & 0x7f]; + *valp = bbe_ltrx2nimm_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_ltrx2nimm_encode (uint32 *valp) +{ + unsigned bbe_ltrx2nimm_in_0; + unsigned bbe_ltrx2nimm_out_0; + bbe_ltrx2nimm_out_0 = *valp; + switch (bbe_ltrx2nimm_out_0) + { + case 0: bbe_ltrx2nimm_in_0 = 0; break; + case 0x1: bbe_ltrx2nimm_in_0 = 0x1; break; + case 0x2: bbe_ltrx2nimm_in_0 = 0x2; break; + case 0x3: bbe_ltrx2nimm_in_0 = 0x3; break; + case 0x4: bbe_ltrx2nimm_in_0 = 0x4; break; + case 0x5: bbe_ltrx2nimm_in_0 = 0x5; break; + case 0x6: bbe_ltrx2nimm_in_0 = 0x6; break; + case 0x7: bbe_ltrx2nimm_in_0 = 0x7; break; + case 0x8: bbe_ltrx2nimm_in_0 = 0x8; break; + case 0x9: bbe_ltrx2nimm_in_0 = 0x9; break; + case 0xa: bbe_ltrx2nimm_in_0 = 0xa; break; + case 0xb: bbe_ltrx2nimm_in_0 = 0xb; break; + case 0xc: bbe_ltrx2nimm_in_0 = 0xc; break; + case 0xd: bbe_ltrx2nimm_in_0 = 0xd; break; + case 0xe: bbe_ltrx2nimm_in_0 = 0xe; break; + case 0xf: bbe_ltrx2nimm_in_0 = 0xf; break; + case 0x10: bbe_ltrx2nimm_in_0 = 0x10; break; + case 0x11: bbe_ltrx2nimm_in_0 = 0x11; break; + case 0x12: bbe_ltrx2nimm_in_0 = 0x12; break; + case 0x13: bbe_ltrx2nimm_in_0 = 0x13; break; + case 0x14: bbe_ltrx2nimm_in_0 = 0x14; break; + case 0x15: bbe_ltrx2nimm_in_0 = 0x15; break; + case 0x16: bbe_ltrx2nimm_in_0 = 0x16; break; + case 0x17: bbe_ltrx2nimm_in_0 = 0x17; break; + case 0x18: bbe_ltrx2nimm_in_0 = 0x18; break; + case 0x19: bbe_ltrx2nimm_in_0 = 0x19; break; + case 0x1a: bbe_ltrx2nimm_in_0 = 0x1a; break; + case 0x1b: bbe_ltrx2nimm_in_0 = 0x1b; break; + case 0x1c: bbe_ltrx2nimm_in_0 = 0x1c; break; + case 0x1d: bbe_ltrx2nimm_in_0 = 0x1d; break; + case 0x1e: bbe_ltrx2nimm_in_0 = 0x1e; break; + case 0x1f: bbe_ltrx2nimm_in_0 = 0x1f; break; + case 0x20: bbe_ltrx2nimm_in_0 = 0x20; break; + case 0x21: bbe_ltrx2nimm_in_0 = 0x21; break; + case 0x22: bbe_ltrx2nimm_in_0 = 0x22; break; + case 0x23: bbe_ltrx2nimm_in_0 = 0x23; break; + case 0x24: bbe_ltrx2nimm_in_0 = 0x24; break; + case 0x25: bbe_ltrx2nimm_in_0 = 0x25; break; + case 0x26: bbe_ltrx2nimm_in_0 = 0x26; break; + case 0x27: bbe_ltrx2nimm_in_0 = 0x27; break; + case 0x28: bbe_ltrx2nimm_in_0 = 0x28; break; + case 0x29: bbe_ltrx2nimm_in_0 = 0x29; break; + case 0x2a: bbe_ltrx2nimm_in_0 = 0x2a; break; + case 0x2b: bbe_ltrx2nimm_in_0 = 0x2b; break; + case 0x2c: bbe_ltrx2nimm_in_0 = 0x2c; break; + case 0x2d: bbe_ltrx2nimm_in_0 = 0x2d; break; + case 0x2e: bbe_ltrx2nimm_in_0 = 0x2e; break; + case 0x2f: bbe_ltrx2nimm_in_0 = 0x2f; break; + case 0x30: bbe_ltrx2nimm_in_0 = 0x30; break; + case 0x31: bbe_ltrx2nimm_in_0 = 0x31; break; + case 0x32: bbe_ltrx2nimm_in_0 = 0x32; break; + case 0x33: bbe_ltrx2nimm_in_0 = 0x33; break; + case 0x34: bbe_ltrx2nimm_in_0 = 0x34; break; + case 0x35: bbe_ltrx2nimm_in_0 = 0x35; break; + case 0x36: bbe_ltrx2nimm_in_0 = 0x36; break; + case 0x37: bbe_ltrx2nimm_in_0 = 0x37; break; + case 0x38: bbe_ltrx2nimm_in_0 = 0x38; break; + case 0x39: bbe_ltrx2nimm_in_0 = 0x39; break; + case 0x3a: bbe_ltrx2nimm_in_0 = 0x3a; break; + case 0x3b: bbe_ltrx2nimm_in_0 = 0x3b; break; + case 0x3c: bbe_ltrx2nimm_in_0 = 0x3c; break; + case 0x3d: bbe_ltrx2nimm_in_0 = 0x3d; break; + case 0x3e: bbe_ltrx2nimm_in_0 = 0x3e; break; + case 0x3f: bbe_ltrx2nimm_in_0 = 0x3f; break; + case 0x40: bbe_ltrx2nimm_in_0 = 0x40; break; + default: bbe_ltrx2nimm_in_0 = 0; break; + } + *valp = bbe_ltrx2nimm_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_ltrxn_2imm_decode (uint32 *valp) +{ + unsigned bbe_ltrxn_2imm_out_0; + unsigned bbe_ltrxn_2imm_in_0; + bbe_ltrxn_2imm_in_0 = *valp & 0x1f; + bbe_ltrxn_2imm_out_0 = CONST_TBL_bbe_ltrxn_2imm_tab_0[bbe_ltrxn_2imm_in_0 & 0x1f]; + *valp = bbe_ltrxn_2imm_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_ltrxn_2imm_encode (uint32 *valp) +{ + unsigned bbe_ltrxn_2imm_in_0; + unsigned bbe_ltrxn_2imm_out_0; + bbe_ltrxn_2imm_out_0 = *valp; + switch (bbe_ltrxn_2imm_out_0) + { + case 0: bbe_ltrxn_2imm_in_0 = 0; break; + case 0x1: bbe_ltrxn_2imm_in_0 = 0x1; break; + case 0x2: bbe_ltrxn_2imm_in_0 = 0x2; break; + case 0x3: bbe_ltrxn_2imm_in_0 = 0x3; break; + case 0x4: bbe_ltrxn_2imm_in_0 = 0x4; break; + case 0x5: bbe_ltrxn_2imm_in_0 = 0x5; break; + case 0x6: bbe_ltrxn_2imm_in_0 = 0x6; break; + case 0x7: bbe_ltrxn_2imm_in_0 = 0x7; break; + case 0x8: bbe_ltrxn_2imm_in_0 = 0x8; break; + case 0x9: bbe_ltrxn_2imm_in_0 = 0x9; break; + case 0xa: bbe_ltrxn_2imm_in_0 = 0xa; break; + case 0xb: bbe_ltrxn_2imm_in_0 = 0xb; break; + case 0xc: bbe_ltrxn_2imm_in_0 = 0xc; break; + case 0xd: bbe_ltrxn_2imm_in_0 = 0xd; break; + case 0xe: bbe_ltrxn_2imm_in_0 = 0xe; break; + case 0xf: bbe_ltrxn_2imm_in_0 = 0xf; break; + case 0x10: bbe_ltrxn_2imm_in_0 = 0x10; break; + default: bbe_ltrxn_2imm_in_0 = 0; break; + } + *valp = bbe_ltrxn_2imm_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_ltrxnimm_decode (uint32 *valp) +{ + unsigned bbe_ltrxnimm_out_0; + unsigned bbe_ltrxnimm_in_0; + bbe_ltrxnimm_in_0 = *valp & 0x3f; + bbe_ltrxnimm_out_0 = CONST_TBL_bbe_ltrxnimm_tab_0[bbe_ltrxnimm_in_0 & 0x3f]; + *valp = bbe_ltrxnimm_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_ltrxnimm_encode (uint32 *valp) +{ + unsigned bbe_ltrxnimm_in_0; + unsigned bbe_ltrxnimm_out_0; + bbe_ltrxnimm_out_0 = *valp; + switch (bbe_ltrxnimm_out_0) + { + case 0: bbe_ltrxnimm_in_0 = 0; break; + case 0x1: bbe_ltrxnimm_in_0 = 0x1; break; + case 0x2: bbe_ltrxnimm_in_0 = 0x2; break; + case 0x3: bbe_ltrxnimm_in_0 = 0x3; break; + case 0x4: bbe_ltrxnimm_in_0 = 0x4; break; + case 0x5: bbe_ltrxnimm_in_0 = 0x5; break; + case 0x6: bbe_ltrxnimm_in_0 = 0x6; break; + case 0x7: bbe_ltrxnimm_in_0 = 0x7; break; + case 0x8: bbe_ltrxnimm_in_0 = 0x8; break; + case 0x9: bbe_ltrxnimm_in_0 = 0x9; break; + case 0xa: bbe_ltrxnimm_in_0 = 0xa; break; + case 0xb: bbe_ltrxnimm_in_0 = 0xb; break; + case 0xc: bbe_ltrxnimm_in_0 = 0xc; break; + case 0xd: bbe_ltrxnimm_in_0 = 0xd; break; + case 0xe: bbe_ltrxnimm_in_0 = 0xe; break; + case 0xf: bbe_ltrxnimm_in_0 = 0xf; break; + case 0x10: bbe_ltrxnimm_in_0 = 0x10; break; + case 0x11: bbe_ltrxnimm_in_0 = 0x11; break; + case 0x12: bbe_ltrxnimm_in_0 = 0x12; break; + case 0x13: bbe_ltrxnimm_in_0 = 0x13; break; + case 0x14: bbe_ltrxnimm_in_0 = 0x14; break; + case 0x15: bbe_ltrxnimm_in_0 = 0x15; break; + case 0x16: bbe_ltrxnimm_in_0 = 0x16; break; + case 0x17: bbe_ltrxnimm_in_0 = 0x17; break; + case 0x18: bbe_ltrxnimm_in_0 = 0x18; break; + case 0x19: bbe_ltrxnimm_in_0 = 0x19; break; + case 0x1a: bbe_ltrxnimm_in_0 = 0x1a; break; + case 0x1b: bbe_ltrxnimm_in_0 = 0x1b; break; + case 0x1c: bbe_ltrxnimm_in_0 = 0x1c; break; + case 0x1d: bbe_ltrxnimm_in_0 = 0x1d; break; + case 0x1e: bbe_ltrxnimm_in_0 = 0x1e; break; + case 0x1f: bbe_ltrxnimm_in_0 = 0x1f; break; + case 0x20: bbe_ltrxnimm_in_0 = 0x20; break; + default: bbe_ltrxnimm_in_0 = 0; break; + } + *valp = bbe_ltrxnimm_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm8_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm8_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm8_in_0; + opnd_ivp_sem_ld_st_i_bimm8_in_0 = *valp & 0xff; + opnd_ivp_sem_ld_st_i_bimm8_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm8_in_0 >> 1) & 0x7f)) | 0xffffff80)) == 0xffffffff))) & 0xffffff) << 8) | opnd_ivp_sem_ld_st_i_bimm8_in_0) << 6; + *valp = opnd_ivp_sem_ld_st_i_bimm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm8_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm8_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm8_out_0; + opnd_ivp_sem_ld_st_i_bimm8_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm8_in_0 = ((opnd_ivp_sem_ld_st_i_bimm8_out_0 >> 6) & 0xff); + *valp = opnd_ivp_sem_ld_st_i_bimm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb8_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimmb8_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimmb8_in_0; + opnd_ivp_sem_ld_st_i_bimmb8_in_0 = *valp & 0xff; + opnd_ivp_sem_ld_st_i_bimmb8_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimmb8_in_0 >> 1) & 0x7f)) | 0xffffff80)) == 0xffffffff))) & 0xffffff) << 8) | opnd_ivp_sem_ld_st_i_bimmb8_in_0) << 5; + *valp = opnd_ivp_sem_ld_st_i_bimmb8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb8_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimmb8_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimmb8_out_0; + opnd_ivp_sem_ld_st_i_bimmb8_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimmb8_in_0 = ((opnd_ivp_sem_ld_st_i_bimmb8_out_0 >> 5) & 0xff); + *valp = opnd_ivp_sem_ld_st_i_bimmb8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb4_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimmb4_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimmb4_in_0; + opnd_ivp_sem_ld_st_i_bimmb4_in_0 = *valp & 0xf; + opnd_ivp_sem_ld_st_i_bimmb4_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimmb4_in_0 >> 1) & 0x7)) | 0xfffffff8)) == 0xffffffff))) & 0xfffffff) << 4) | opnd_ivp_sem_ld_st_i_bimmb4_in_0) << 5; + *valp = opnd_ivp_sem_ld_st_i_bimmb4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb4_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimmb4_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimmb4_out_0; + opnd_ivp_sem_ld_st_i_bimmb4_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimmb4_in_0 = ((opnd_ivp_sem_ld_st_i_bimmb4_out_0 >> 5) & 0xf); + *valp = opnd_ivp_sem_ld_st_i_bimmb4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb6_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimmb6_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimmb6_in_0; + opnd_ivp_sem_ld_st_i_bimmb6_in_0 = *valp & 0x3f; + opnd_ivp_sem_ld_st_i_bimmb6_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimmb6_in_0 >> 1) & 0x1f)) | 0xffffffe0)) == 0xffffffff))) & 0x3ffffff) << 6) | opnd_ivp_sem_ld_st_i_bimmb6_in_0) << 5; + *valp = opnd_ivp_sem_ld_st_i_bimmb6_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb6_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimmb6_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimmb6_out_0; + opnd_ivp_sem_ld_st_i_bimmb6_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimmb6_in_0 = ((opnd_ivp_sem_ld_st_i_bimmb6_out_0 >> 5) & 0x3f); + *valp = opnd_ivp_sem_ld_st_i_bimmb6_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_i_IMM_movint_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_vec_mov_i_IMM_movint_out_0; + unsigned opnd_ivp_sem_vec_mov_i_IMM_movint_in_0; + opnd_ivp_sem_vec_mov_i_IMM_movint_in_0 = *valp & 0x7f; + opnd_ivp_sem_vec_mov_i_IMM_movint_out_0 = (((-(( ( ((((opnd_ivp_sem_vec_mov_i_IMM_movint_in_0 >> 5) & 0x3)) | 0xfffffffc)) == 0xffffffff))) & 0x1ffffff) << 7) | opnd_ivp_sem_vec_mov_i_IMM_movint_in_0; + *valp = opnd_ivp_sem_vec_mov_i_IMM_movint_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_i_IMM_movint_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_vec_mov_i_IMM_movint_in_0; + unsigned opnd_ivp_sem_vec_mov_i_IMM_movint_out_0; + opnd_ivp_sem_vec_mov_i_IMM_movint_out_0 = *valp; + opnd_ivp_sem_vec_mov_i_IMM_movint_in_0 = (opnd_ivp_sem_vec_mov_i_IMM_movint_out_0 & 0x7f); + *valp = opnd_ivp_sem_vec_mov_i_IMM_movint_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_immmovvi_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_vec_mov_immmovvi_out_0; + unsigned opnd_ivp_sem_vec_mov_immmovvi_in_0; + opnd_ivp_sem_vec_mov_immmovvi_in_0 = *valp & 0x3f; + opnd_ivp_sem_vec_mov_immmovvi_out_0 = (((-(( ( (((opnd_ivp_sem_vec_mov_immmovvi_in_0 & 0x3f)) | 0xffffffc0)) == 0xffffffff))) & 0x3ffffff) << 6) | opnd_ivp_sem_vec_mov_immmovvi_in_0; + *valp = opnd_ivp_sem_vec_mov_immmovvi_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_immmovvi_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_vec_mov_immmovvi_in_0; + unsigned opnd_ivp_sem_vec_mov_immmovvi_out_0; + opnd_ivp_sem_vec_mov_immmovvi_out_0 = *valp; + opnd_ivp_sem_vec_mov_immmovvi_in_0 = (opnd_ivp_sem_vec_mov_immmovvi_out_0 & 0x3f); + *valp = opnd_ivp_sem_vec_mov_immmovvi_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm7_63_decode (uint32 *valp) +{ + unsigned saimm7_63_out_0; + unsigned saimm7_63_in_0; + saimm7_63_in_0 = *valp & 0x3f; + saimm7_63_out_0 = (0 << 6) | saimm7_63_in_0; + *valp = saimm7_63_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm7_63_encode (uint32 *valp) +{ + unsigned saimm7_63_in_0; + unsigned saimm7_63_out_0; + saimm7_63_out_0 = *valp; + saimm7_63_in_0 = (saimm7_63_out_0 & 0x3f); + *valp = saimm7_63_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm7_decode (uint32 *valp) +{ + unsigned saimm7_out_0; + unsigned saimm7_in_0; + saimm7_in_0 = *valp & 0x7f; + saimm7_out_0 = (0 << 7) | saimm7_in_0; + *valp = saimm7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm7_encode (uint32 *valp) +{ + unsigned saimm7_in_0; + unsigned saimm7_out_0; + saimm7_out_0 = *valp; + saimm7_in_0 = (saimm7_out_0 & 0x7f); + *valp = saimm7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_gvr_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_gvr_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_imm1_2N_decode (uint32 *valp) +{ + unsigned imm1_2N_out_0; + unsigned imm1_2N_in_0; + imm1_2N_in_0 = *valp & 0x7; + imm1_2N_out_0 = CONST_TBL_imm1_2N_tab_0[imm1_2N_in_0 & 0x7]; + *valp = imm1_2N_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_imm1_2N_encode (uint32 *valp) +{ + unsigned imm1_2N_in_0; + unsigned imm1_2N_out_0; + imm1_2N_out_0 = *valp; + switch (imm1_2N_out_0) + { + case 0x1: imm1_2N_in_0 = 0; break; + case 0x2: imm1_2N_in_0 = 0x1; break; + case 0x4: imm1_2N_in_0 = 0x2; break; + case 0x8: imm1_2N_in_0 = 0x3; break; + case 0x10: imm1_2N_in_0 = 0x4; break; + case 0x20: imm1_2N_in_0 = 0x5; break; + case 0x40: imm1_2N_in_0 = 0x6; break; + default: imm1_2N_in_0 = 0; break; + } + *valp = imm1_2N_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_selimm_S0_decode (uint32 *valp) +{ + unsigned bbe_selimm_S0_out_0; + unsigned bbe_selimm_S0_in_0; + bbe_selimm_S0_in_0 = *valp & 0x1f; + bbe_selimm_S0_out_0 = CONST_TBL_tab_selimm_7b_0[bbe_selimm_S0_in_0 & 0x1f]; + *valp = bbe_selimm_S0_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_selimm_S0_encode (uint32 *valp) +{ + unsigned bbe_selimm_S0_in_0; + unsigned bbe_selimm_S0_out_0; + bbe_selimm_S0_out_0 = *valp; + switch (bbe_selimm_S0_out_0) + { + case 0: bbe_selimm_S0_in_0 = 0; break; + case 0x1: bbe_selimm_S0_in_0 = 0x1; break; + case 0x2: bbe_selimm_S0_in_0 = 0x2; break; + case 0x3: bbe_selimm_S0_in_0 = 0x3; break; + case 0x8: bbe_selimm_S0_in_0 = 0x4; break; + case 0x9: bbe_selimm_S0_in_0 = 0x5; break; + case 0xa: bbe_selimm_S0_in_0 = 0x6; break; + case 0xb: bbe_selimm_S0_in_0 = 0x7; break; + case 0x10: bbe_selimm_S0_in_0 = 0x8; break; + case 0x11: bbe_selimm_S0_in_0 = 0x9; break; + case 0x20: bbe_selimm_S0_in_0 = 0xa; break; + case 0x21: bbe_selimm_S0_in_0 = 0xb; break; + case 0x22: bbe_selimm_S0_in_0 = 0xc; break; + case 0x23: bbe_selimm_S0_in_0 = 0xd; break; + case 0x3b: bbe_selimm_S0_in_0 = 0xe; break; + case 0x3c: bbe_selimm_S0_in_0 = 0xf; break; + case 0x3d: bbe_selimm_S0_in_0 = 0x10; break; + case 0x3e: bbe_selimm_S0_in_0 = 0x11; break; + case 0x3f: bbe_selimm_S0_in_0 = 0x12; break; + case 0x40: bbe_selimm_S0_in_0 = 0x13; break; + case 0x41: bbe_selimm_S0_in_0 = 0x14; break; + case 0x42: bbe_selimm_S0_in_0 = 0x15; break; + case 0x43: bbe_selimm_S0_in_0 = 0x16; break; + case 0x44: bbe_selimm_S0_in_0 = 0x17; break; + case 0x45: bbe_selimm_S0_in_0 = 0x18; break; + case 0x46: bbe_selimm_S0_in_0 = 0x19; break; + case 0x47: bbe_selimm_S0_in_0 = 0x1a; break; + default: bbe_selimm_S0_in_0 = 0x1b; break; + } + *valp = bbe_selimm_S0_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_shflimm_S0_decode (uint32 *valp) +{ + unsigned bbe_shflimm_S0_out_0; + unsigned bbe_shflimm_S0_in_0; + bbe_shflimm_S0_in_0 = *valp & 0x1; + bbe_shflimm_S0_out_0 = CONST_TBL_tab_shflimm_7b_0[bbe_shflimm_S0_in_0 & 0x1]; + *valp = bbe_shflimm_S0_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_shflimm_S0_encode (uint32 *valp) +{ + unsigned bbe_shflimm_S0_in_0; + unsigned bbe_shflimm_S0_out_0; + bbe_shflimm_S0_out_0 = *valp; + bbe_shflimm_S0_in_0 = (((bbe_shflimm_S0_out_0 == (CONST_TBL_tab_shflimm_7b_0[0]))) ? 0 : 0x1) & 0x1; + *valp = bbe_shflimm_S0_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_MTK_AndPOPC_c_decode (uint32 *valp) +{ + unsigned opnd_MTK_AndPOPC_c_out_0; + unsigned opnd_MTK_AndPOPC_c_in_0; + opnd_MTK_AndPOPC_c_in_0 = *valp & 0x1; + opnd_MTK_AndPOPC_c_out_0 = (0 << 1) | opnd_MTK_AndPOPC_c_in_0; + *valp = opnd_MTK_AndPOPC_c_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_MTK_AndPOPC_c_encode (uint32 *valp) +{ + unsigned opnd_MTK_AndPOPC_c_in_0; + unsigned opnd_MTK_AndPOPC_c_out_0; + opnd_MTK_AndPOPC_c_out_0 = *valp; + opnd_MTK_AndPOPC_c_in_0 = (((opnd_MTK_AndPOPC_c_out_0 >> 0) & 1)) & 0x1; + *valp = opnd_MTK_AndPOPC_c_in_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, + { "uimm12x8", FIELD_imm12, -1, 0, + 0, + OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, + 0, 0 }, + { "simm4", FIELD_mn, -1, 0, + 0, + OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, + 0, 0 }, + { "arr", FIELD_r, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "ars", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "*ars_invisible", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "art", FIELD_t, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "ar0", FIELD__ar0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, + 0, 0 }, + { "ar4", FIELD__ar4, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode, + 0, 0 }, + { "ar8", FIELD__ar8, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode, + 0, 0 }, + { "ar12", FIELD__ar12, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode, + 0, 0 }, + { "ars_entry", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, + 0, 0 }, + { "immrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, + 0, 0 }, + { "lsi4x4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, + 0, 0 }, + { "simm7", FIELD_imm7, -1, 0, + 0, + OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, + 0, 0 }, + { "uimm6", FIELD_imm6, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa }, + { "ai4const", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, + 0, 0 }, + { "b4const", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, + 0, 0 }, + { "b4constu", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, + 0, 0 }, + { "uimm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, + 0, 0 }, + { "uimm8x2", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, + 0, 0 }, + { "uimm8x4", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, + 0, 0 }, + { "uimm4x16", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, + 0, 0 }, + { "uimmrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode, + 0, 0 }, + { "simm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, + 0, 0 }, + { "simm8x256", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, + 0, 0 }, + { "simm12b", FIELD_imm12b, -1, 0, + 0, + OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, + 0, 0 }, + { "msalp32", FIELD_sal, -1, 0, + 0, + OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, + 0, 0 }, + { "op2p1", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, + 0, 0 }, + { "label8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, + Operand_label8_ator, Operand_label8_rtoa }, + { "ulabel8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa }, + { "label12", FIELD_imm12, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, + Operand_label12_ator, Operand_label12_rtoa }, + { "soffset", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa }, + { "uimm16x4", FIELD_imm16, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, + { "bbi", FIELD_bbi, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "imm16", FIELD_imm16, -1, 0, + 0, + OperandSem_opnd_sem_imm16_encode, OperandSem_opnd_sem_imm16_decode, + 0, 0 }, + { "sae", FIELD_sae, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sas", FIELD_sas, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sargt", FIELD_sargt, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "s", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, + 0, 0 }, + { "immt", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0 }, + { "imms", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0 }, + { "bt", FIELD_t, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "bs", FIELD_s, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "br", FIELD_r, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "bt2", FIELD_t2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0 }, + { "bs2", FIELD_s2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0 }, + { "br2", FIELD_r2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0 }, + { "bt4", FIELD_t4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0 }, + { "bs4", FIELD_s4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0 }, + { "br4", FIELD_r4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0 }, + { "bt8", FIELD_t8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0 }, + { "bs8", FIELD_s8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0 }, + { "br8", FIELD_r8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0 }, + { "bt16", FIELD__bt16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "bs16", FIELD__bs16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "br16", FIELD__br16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "brall", FIELD__brall, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "tp7", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, + 0, 0 }, + { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, + { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode, + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, + { "opnd_ivp_sem_vec_alu_vr", FIELD_fld_ivp_sem_vec_alu_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_alu_vt", FIELD_fld_ivp_sem_vec_alu_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_alu_vs", FIELD_fld_ivp_sem_vec_alu_vs, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_alu_vbr", FIELD_fld_ivp_sem_vec_alu_vbr, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_multiply_vr", FIELD_fld_ivp_sem_multiply_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_multiply_vs", FIELD_fld_ivp_sem_multiply_vs, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_multiply_wvt", FIELD_fld_ivp_sem_multiply_wvt, REGFILE_wvec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_wvec_encode, OperandSem_opnd_sem_wvec_decode, + 0, 0 }, + { "opnd_ivp_sem_vbool_alu_ltr_vbr", FIELD_fld_ivp_sem_vbool_alu_ltr_vbr, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vbool_alu_ltr_vbs", FIELD_fld_ivp_sem_vbool_alu_ltr_vbs, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vbool_alu_ltr_vbt", FIELD_fld_ivp_sem_vbool_alu_ltr_vbt, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_alu_vbt", FIELD_fld_ivp_sem_vec_alu_vbt, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_histogram_arr", FIELD_fld_ivp_sem_vec_histogram_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_histogram_vr", FIELD_fld_ivp_sem_vec_histogram_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_histogram_vs", FIELD_fld_ivp_sem_vec_histogram_vs, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_histogram_vt", FIELD_fld_ivp_sem_vec_histogram_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_histogram_vbr", FIELD_fld_ivp_sem_vec_histogram_vbr, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_histogram_vbs", FIELD_fld_ivp_sem_vec_histogram_vbs, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_divide_lane_ctrl", FIELD_fld_ivp_sem_divide_lane_ctrl, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_divide_lane_ctrl_encode, OperandSem_opnd_sem_opnd_ivp_sem_divide_lane_ctrl_decode, + 0, 0 }, + { "opnd_ivp_sem_divide_vr", FIELD_fld_ivp_sem_divide_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_divide_vt", FIELD_fld_ivp_sem_divide_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_divide_vu", FIELD_fld_ivp_sem_divide_vu, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_divide_vs", FIELD_fld_ivp_sem_divide_vs, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_slct", FIELD_fld_ivp_sem_vec_select_slct, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_i_imm4_encode, OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_i_imm4_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_vr", FIELD_fld_ivp_sem_vec_select_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_vs", FIELD_fld_ivp_sem_vec_select_vs, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_vt", FIELD_fld_ivp_sem_vec_select_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_vu", FIELD_fld_ivp_sem_vec_select_vu, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_slct_h", FIELD_fld_ivp_sem_vec_select_slct_h, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_vec_select_slct_h_encode, OperandSem_opnd_sem_opnd_ivp_sem_vec_select_slct_h_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_sr", FIELD_fld_ivp_sem_vec_select_sr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_vbr", FIELD_fld_ivp_sem_vec_select_vbr, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_alu_i_imm3", FIELD_fld_ivp_sem_vec_alu_i_imm3, -1, 0, + 0, + OperandSem_opnd_sem_saimm4_encode, OperandSem_opnd_sem_saimm4_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_rep_i32", FIELD_fld_ivp_sem_vec_rep_i32, -1, 0, + 0, + OperandSem_opnd_sem_saimm5_encode, OperandSem_opnd_sem_saimm5_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_rep_vr", FIELD_fld_ivp_sem_vec_rep_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_rep_i", FIELD_fld_ivp_sem_vec_rep_i, -1, 0, + 0, + OperandSem_opnd_sem_saimm6_31_encode, OperandSem_opnd_sem_saimm6_31_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_uul", FIELD_fld_ivp_sem_ld_st_uul, REGFILE_valign, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_valign_encode, OperandSem_opnd_sem_valign_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_vrul", FIELD_fld_ivp_sem_ld_st_vrul, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_vrul2", FIELD_fld_ivp_sem_ld_st_vrul2, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm6", FIELD_fld_ivp_sem_ld_st_i_bimm6, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm4", FIELD_fld_ivp_sem_ld_st_i_bimm4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_vbr", FIELD_fld_ivp_sem_ld_st_vbr, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm6b2n", FIELD_fld_ivp_sem_ld_st_i_bimm6b2n, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6b2n_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6b2n_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm4b2n", FIELD_fld_ivp_sem_ld_st_i_bimm4b2n, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4b2n_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4b2n_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm6bn_2", FIELD_fld_ivp_sem_ld_st_i_bimm6bn_2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_2_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_2_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm4bn_2", FIELD_fld_ivp_sem_ld_st_i_bimm4bn_2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_2_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_2_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm6bn", FIELD_fld_ivp_sem_ld_st_i_bimm6bn, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm4bn", FIELD_fld_ivp_sem_ld_st_i_bimm4bn, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm6x1", FIELD_fld_ivp_sem_ld_st_i_bimm6x1, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6x1_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6x1_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_vr", FIELD_fld_ivp_sem_ld_st_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm4x1", FIELD_fld_ivp_sem_ld_st_i_bimm4x1, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4x1_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4x1_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm8x4", FIELD_fld_ivp_sem_ld_st_i_bimm8x4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm8x4_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm8x4_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm4x4", FIELD_fld_ivp_sem_ld_st_i_bimm4x4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm6x2", FIELD_fld_ivp_sem_ld_st_i_bimm6x2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_2_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_2_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm4x2", FIELD_fld_ivp_sem_ld_st_i_bimm4x2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_2_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_2_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_vrr", FIELD_fld_ivp_sem_ld_st_vrr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm6x4", FIELD_fld_ivp_sem_ld_st_i_bimm6x4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_decode, + 0, 0 }, + { "bbe_ltrx2nimm", FIELD_fld_bbe_ltrx2nimm, -1, 0, + 0, + OperandSem_opnd_sem_bbe_ltrx2nimm_encode, OperandSem_opnd_sem_bbe_ltrx2nimm_decode, + 0, 0 }, + { "bbe_ltrxn_2imm", FIELD_fld_bbe_ltrxn_2imm, -1, 0, + 0, + OperandSem_opnd_sem_bbe_ltrxn_2imm_encode, OperandSem_opnd_sem_bbe_ltrxn_2imm_decode, + 0, 0 }, + { "bbe_ltrxnimm", FIELD_fld_bbe_ltrxnimm, -1, 0, + 0, + OperandSem_opnd_sem_bbe_ltrxnimm_encode, OperandSem_opnd_sem_bbe_ltrxnimm_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm8", FIELD_fld_ivp_sem_ld_st_i_bimm8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm8_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm8_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_vbre", FIELD_fld_ivp_sem_ld_st_vbre, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimmh8", FIELD_fld_ivp_sem_ld_st_i_bimmh8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb8_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb8_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimmh4", FIELD_fld_ivp_sem_ld_st_i_bimmh4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb4_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb4_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimmh6", FIELD_fld_ivp_sem_ld_st_i_bimmh6, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb6_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb6_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimmb8", FIELD_fld_ivp_sem_ld_st_i_bimmb8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb8_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb8_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimmb4", FIELD_fld_ivp_sem_ld_st_i_bimmb4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb4_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb4_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimmb6", FIELD_fld_ivp_sem_ld_st_i_bimmb6, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb6_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb6_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_valignr", FIELD_fld_ivp_sem_ld_st_valignr, REGFILE_valign, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_valign_encode, OperandSem_opnd_sem_valign_decode, + 0, 0 }, + { "opnd_ivp_sem_unpack_wvec_mov_vr", FIELD_fld_ivp_sem_unpack_wvec_mov_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_unpack_wvec_mov_vs", FIELD_fld_ivp_sem_unpack_wvec_mov_vs, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_unpack_wvec_mov_wvt", FIELD_fld_ivp_sem_unpack_wvec_mov_wvt, REGFILE_wvec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_wvec_encode, OperandSem_opnd_sem_wvec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_mov_vt", FIELD_fld_ivp_sem_vec_mov_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_mov_wvr", FIELD_fld_ivp_sem_vec_mov_wvr, REGFILE_wvec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_wvec_encode, OperandSem_opnd_sem_wvec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_mov_arr", FIELD_fld_ivp_sem_vec_mov_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_mov_i_IMM_movint", FIELD_fld_ivp_sem_vec_mov_i_IMM_movint, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_i_IMM_movint_encode, OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_i_IMM_movint_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_mov_immmovvi", FIELD_fld_ivp_sem_vec_mov_immmovvi, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_immmovvi_encode, OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_immmovvi_decode, + 0, 0 }, + { "opnd_ivp_sem_unpack_wvec_mov_wvr", FIELD_fld_ivp_sem_unpack_wvec_mov_wvr, REGFILE_wvec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_wvec_encode, OperandSem_opnd_sem_wvec_decode, + 0, 0 }, + { "opnd_ivp_sem_multiply_arr", FIELD_fld_ivp_sem_multiply_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_ivp_sem_multiply_vp", FIELD_fld_ivp_sem_multiply_vp, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_multiply_vt", FIELD_fld_ivp_sem_multiply_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_multiply_vbr", FIELD_fld_ivp_sem_multiply_vbr, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_shift_vr", FIELD_fld_ivp_sem_vec_shift_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_shift_vt", FIELD_fld_ivp_sem_vec_shift_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_wvec_pack_vt", FIELD_fld_ivp_sem_wvec_pack_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_wvec_pack_wvr", FIELD_fld_ivp_sem_wvec_pack_wvr, REGFILE_wvec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_wvec_encode, OperandSem_opnd_sem_wvec_decode, + 0, 0 }, + { "opnd_ivp_sem_wvec_pack_arr", FIELD_fld_ivp_sem_wvec_pack_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_reduce_vr", FIELD_fld_ivp_sem_vec_reduce_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_reduce_vt", FIELD_fld_ivp_sem_vec_reduce_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_reduce_vbr", FIELD_fld_ivp_sem_vec_reduce_vbr, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_reduce_vbt", FIELD_fld_ivp_sem_vec_reduce_vbt, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_rep_i8", FIELD_fld_ivp_sem_vec_rep_i8, -1, 0, + 0, + OperandSem_opnd_sem_saimm7_63_encode, OperandSem_opnd_sem_saimm7_63_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_rep_vt", FIELD_fld_ivp_sem_vec_rep_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "saimm4", FIELD_fld_saimm4, -1, 0, + 0, + OperandSem_opnd_sem_saimm4_encode, OperandSem_opnd_sem_saimm4_decode, + 0, 0 }, + { "saimm6_31", FIELD_fld_saimm6_31, -1, 0, + 0, + OperandSem_opnd_sem_saimm6_31_encode, OperandSem_opnd_sem_saimm6_31_decode, + 0, 0 }, + { "saimm5", FIELD_fld_saimm5, -1, 0, + 0, + OperandSem_opnd_sem_saimm5_encode, OperandSem_opnd_sem_saimm5_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_shift_vs", FIELD_fld_ivp_sem_vec_shift_vs, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_uus", FIELD_fld_ivp_sem_ld_st_uus, REGFILE_valign, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_valign_encode, OperandSem_opnd_sem_valign_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_isel", FIELD_fld_ivp_sem_vec_select_isel, -1, 0, + 0, + OperandSem_opnd_sem_saimm7_encode, OperandSem_opnd_sem_saimm7_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_ishfl", FIELD_fld_ivp_sem_vec_select_ishfl, -1, 0, + 0, + OperandSem_opnd_sem_saimm7_encode, OperandSem_opnd_sem_saimm7_decode, + 0, 0 }, + { "opnd_ivp_sem_sqz_vbr", FIELD_fld_ivp_sem_sqz_vbr, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_sqz_vt", FIELD_fld_ivp_sem_sqz_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_unpack_wvec_mov_vt", FIELD_fld_ivp_sem_unpack_wvec_mov_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_scatter_gather_ars", FIELD_fld_ivp_sem_vec_scatter_gather_ars, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_scatter_gather_gt", FIELD_fld_ivp_sem_vec_scatter_gather_gt, REGFILE_gvr, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_gvr_encode, OperandSem_opnd_sem_gvr_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_scatter_gather_vs", FIELD_fld_ivp_sem_vec_scatter_gather_vs, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_scatter_gather_vbr", FIELD_fld_ivp_sem_vec_scatter_gather_vbr, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_scatter_gather_gs", FIELD_fld_ivp_sem_vec_scatter_gather_gs, REGFILE_gvr, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_gvr_encode, OperandSem_opnd_sem_gvr_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_scatter_gather_vt", FIELD_fld_ivp_sem_vec_scatter_gather_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_scatter_gather_vr", FIELD_fld_ivp_sem_vec_scatter_gather_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vbool_alu_ltr_art", FIELD_fld_ivp_sem_vbool_alu_ltr_art, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "imm1_2N", FIELD_fld_imm1_2N, -1, 0, + 0, + OperandSem_opnd_sem_imm1_2N_encode, OperandSem_opnd_sem_imm1_2N_decode, + 0, 0 }, + { "opnd_ivp_sem_multiply_vq", FIELD_fld_ivp_sem_multiply_vq, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_rep_arr", FIELD_fld_ivp_sem_vec_rep_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "bbe_selimm_S0", FIELD_fld_bbe_selimm_S0, -1, 0, + 0, + OperandSem_opnd_sem_bbe_selimm_S0_encode, OperandSem_opnd_sem_bbe_selimm_S0_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_specialized_seli_vr", FIELD_fld_ivp_sem_vec_specialized_seli_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_specialized_seli_vs", FIELD_fld_ivp_sem_vec_specialized_seli_vs, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_specialized_seli_vt", FIELD_fld_ivp_sem_vec_specialized_seli_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "bbe_selimm_S2", FIELD_fld_bbe_selimm_S2, -1, 0, + 0, + OperandSem_opnd_sem_bbe_selimm_S0_encode, OperandSem_opnd_sem_bbe_selimm_S0_decode, + 0, 0 }, + { "bbe_selimm_S4", FIELD_fld_bbe_selimm_S4, -1, 0, + 0, + OperandSem_opnd_sem_bbe_selimm_S0_encode, OperandSem_opnd_sem_bbe_selimm_S0_decode, + 0, 0 }, + { "bbe_shflimm_S0", FIELD_fld_bbe_shflimm_S0, -1, 0, + 0, + OperandSem_opnd_sem_bbe_shflimm_S0_encode, OperandSem_opnd_sem_bbe_shflimm_S0_decode, + 0, 0 }, + { "bbe_shflimm_S2", FIELD_fld_bbe_shflimm_S2, -1, 0, + 0, + OperandSem_opnd_sem_bbe_shflimm_S0_encode, OperandSem_opnd_sem_bbe_shflimm_S0_decode, + 0, 0 }, + { "bbe_shflimm_S4", FIELD_fld_bbe_shflimm_S4, -1, 0, + 0, + OperandSem_opnd_sem_bbe_shflimm_S0_encode, OperandSem_opnd_sem_bbe_shflimm_S0_decode, + 0, 0 }, + { "opnd_MTK_AndPOPC_c", FIELD_fld_MTK_AndPOPC_c, -1, 0, + 0, + OperandSem_opnd_sem_opnd_MTK_AndPOPC_c_encode, OperandSem_opnd_sem_opnd_MTK_AndPOPC_c_decode, + 0, 0 }, + { "opnd_MTK_AndPOPC_inB", FIELD_fld_MTK_AndPOPC_inB, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_MTK_AndPOPC_inA", FIELD_fld_MTK_AndPOPC_inA, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_MTK_AndPOPC_oData", FIELD_fld_MTK_AndPOPC_oData, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_iq_tie2apb_inq0_pop_qdata", FIELD_fld_iq_tie2apb_inq0_pop_qdata, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_iq_tie2apb_inq0_is_ready_is_ready", FIELD_fld_iq_tie2apb_inq0_is_ready_is_ready, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "opnd_iq_tie2apb_inq0_nonblocking_peek_success", FIELD_fld_iq_tie2apb_inq0_nonblocking_peek_success, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "opnd_iq_tie2apb_inq0_nonblocking_peek_qdata", FIELD_fld_iq_tie2apb_inq0_nonblocking_peek_qdata, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_iq_tie2apb_inq0_nonblocking_pop_success", FIELD_fld_iq_tie2apb_inq0_nonblocking_pop_success, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "opnd_iq_tie2apb_inq0_nonblocking_pop_qdata", FIELD_fld_iq_tie2apb_inq0_nonblocking_pop_qdata, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_iq_tie2apb_inq0_blocking_peek_qdata", FIELD_fld_iq_tie2apb_inq0_blocking_peek_qdata, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_push_read_qaddr", FIELD_fld_oq_tie2apb_outq0_push_read_qaddr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_push_read_qdata", FIELD_fld_oq_tie2apb_outq0_push_read_qdata, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_push_write_qaddr", FIELD_fld_oq_tie2apb_outq0_push_write_qaddr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_push_write_qdata", FIELD_fld_oq_tie2apb_outq0_push_write_qdata, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_is_ready_is_ready", FIELD_fld_oq_tie2apb_outq0_is_ready_is_ready, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_nonblocking_push_read_success", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_read_success, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_nonblocking_push_read_qaddr", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_read_qaddr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_nonblocking_push_read_qdata", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_read_qdata, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_nonblocking_push_write_success", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_write_success, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_nonblocking_push_write_qaddr", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_write_qaddr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_nonblocking_push_write_qdata", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_write_qdata, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, + { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, + { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, + { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, + { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, + { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, + { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, + { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, + { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, + { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, + { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, + { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, + { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, + { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, + { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_11_4", FIELD_fld_F0_S0_LdSt_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_11_8", FIELD_fld_F0_S0_LdSt_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_11_9", FIELD_fld_F0_S0_LdSt_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_12_0", FIELD_fld_F0_S0_LdSt_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_12_11", FIELD_fld_F0_S0_LdSt_12_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_12_12", FIELD_fld_F0_S0_LdSt_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_12_2", FIELD_fld_F0_S0_LdSt_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_12_4", FIELD_fld_F0_S0_LdSt_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_12_8", FIELD_fld_F0_S0_LdSt_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_13_9", FIELD_fld_F0_S0_LdSt_13_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_15_15", FIELD_fld_F0_S0_LdSt_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_11", FIELD_fld_F0_S0_LdSt_33_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_12", FIELD_fld_F0_S0_LdSt_33_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_13", FIELD_fld_F0_S0_LdSt_33_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_14", FIELD_fld_F0_S0_LdSt_33_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_15", FIELD_fld_F0_S0_LdSt_33_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_16", FIELD_fld_F0_S0_LdSt_33_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_17", FIELD_fld_F0_S0_LdSt_33_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_18", FIELD_fld_F0_S0_LdSt_33_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_19", FIELD_fld_F0_S0_LdSt_33_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_20", FIELD_fld_F0_S0_LdSt_33_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_27", FIELD_fld_F0_S0_LdSt_33_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_9", FIELD_fld_F0_S0_LdSt_33_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_3_0", FIELD_fld_F0_S0_LdSt_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_7_4", FIELD_fld_F0_S0_LdSt_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_7_5", FIELD_fld_F0_S0_LdSt_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_7_6", FIELD_fld_F0_S0_LdSt_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_7_7", FIELD_fld_F0_S0_LdSt_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_8_0", FIELD_fld_F0_S0_LdSt_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_8_4", FIELD_fld_F0_S0_LdSt_8_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_8_8", FIELD_fld_F0_S0_LdSt_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_bbe_shflimm_S0", FIELD_fld_bbe_shflimm_S0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm4", FIELD_fld_ivp_sem_ld_st_i_bimm4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm4b2n", FIELD_fld_ivp_sem_ld_st_i_bimm4b2n, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm4bn", FIELD_fld_ivp_sem_ld_st_i_bimm4bn, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm4bn_2", FIELD_fld_ivp_sem_ld_st_i_bimm4bn_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm4x1", FIELD_fld_ivp_sem_ld_st_i_bimm4x1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm4x2", FIELD_fld_ivp_sem_ld_st_i_bimm4x2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm4x4", FIELD_fld_ivp_sem_ld_st_i_bimm4x4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm6", FIELD_fld_ivp_sem_ld_st_i_bimm6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm6b2n", FIELD_fld_ivp_sem_ld_st_i_bimm6b2n, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm6bn", FIELD_fld_ivp_sem_ld_st_i_bimm6bn, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm6bn_2", FIELD_fld_ivp_sem_ld_st_i_bimm6bn_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm6x1", FIELD_fld_ivp_sem_ld_st_i_bimm6x1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm6x2", FIELD_fld_ivp_sem_ld_st_i_bimm6x2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm6x4", FIELD_fld_ivp_sem_ld_st_i_bimm6x4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm8", FIELD_fld_ivp_sem_ld_st_i_bimm8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm8x4", FIELD_fld_ivp_sem_ld_st_i_bimm8x4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimmb4", FIELD_fld_ivp_sem_ld_st_i_bimmb4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimmb6", FIELD_fld_ivp_sem_ld_st_i_bimmb6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimmb8", FIELD_fld_ivp_sem_ld_st_i_bimmb8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimmh4", FIELD_fld_ivp_sem_ld_st_i_bimmh4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimmh6", FIELD_fld_ivp_sem_ld_st_i_bimmh6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimmh8", FIELD_fld_ivp_sem_ld_st_i_bimmh8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_uul", FIELD_fld_ivp_sem_ld_st_uul, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_uus", FIELD_fld_ivp_sem_ld_st_uus, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_valignr", FIELD_fld_ivp_sem_ld_st_valignr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_vbr", FIELD_fld_ivp_sem_ld_st_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_vbre", FIELD_fld_ivp_sem_ld_st_vbre, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_vr", FIELD_fld_ivp_sem_ld_st_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_vrr", FIELD_fld_ivp_sem_ld_st_vrr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_vrul", FIELD_fld_ivp_sem_ld_st_vrul, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_alu_arr", FIELD_fld_ivp_sem_vec_alu_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_alu_vbr", FIELD_fld_ivp_sem_vec_alu_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_alu_vr", FIELD_fld_ivp_sem_vec_alu_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_alu_vt", FIELD_fld_ivp_sem_vec_alu_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_rep_i", FIELD_fld_ivp_sem_vec_rep_i, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_rep_i32", FIELD_fld_ivp_sem_vec_rep_i32, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_rep_i8", FIELD_fld_ivp_sem_vec_rep_i8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_rep_vr", FIELD_fld_ivp_sem_vec_rep_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_rep_vt", FIELD_fld_ivp_sem_vec_rep_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_scatter_gather_ars", FIELD_fld_ivp_sem_vec_scatter_gather_ars, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_scatter_gather_gt", FIELD_fld_ivp_sem_vec_scatter_gather_gt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_scatter_gather_vbr", FIELD_fld_ivp_sem_vec_scatter_gather_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_scatter_gather_vs", FIELD_fld_ivp_sem_vec_scatter_gather_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_shift_vr", FIELD_fld_ivp_sem_vec_shift_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_shift_vt", FIELD_fld_ivp_sem_vec_shift_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_specialized_seli_vr", FIELD_fld_ivp_sem_vec_specialized_seli_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_specialized_seli_vt", FIELD_fld_ivp_sem_vec_specialized_seli_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_saimm4", FIELD_fld_saimm4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_saimm5", FIELD_fld_saimm5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_12_11", FIELD_fld_F0_S1_Ld_12_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_12_12", FIELD_fld_F0_S1_Ld_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_12_4", FIELD_fld_F0_S1_Ld_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_15_10", FIELD_fld_F0_S1_Ld_15_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_15_13", FIELD_fld_F0_S1_Ld_15_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_15_14", FIELD_fld_F0_S1_Ld_15_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_15_15", FIELD_fld_F0_S1_Ld_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_15_2", FIELD_fld_F0_S1_Ld_15_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_15_4", FIELD_fld_F0_S1_Ld_15_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_15_8", FIELD_fld_F0_S1_Ld_15_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_24_0", FIELD_fld_F0_S1_Ld_24_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_24_11", FIELD_fld_F0_S1_Ld_24_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_24_12", FIELD_fld_F0_S1_Ld_24_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_24_13", FIELD_fld_F0_S1_Ld_24_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_24_14", FIELD_fld_F0_S1_Ld_24_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_24_16", FIELD_fld_F0_S1_Ld_24_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_24_17", FIELD_fld_F0_S1_Ld_24_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_24_18", FIELD_fld_F0_S1_Ld_24_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_24_8", FIELD_fld_F0_S1_Ld_24_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_3_0", FIELD_fld_F0_S1_Ld_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_3_2", FIELD_fld_F0_S1_Ld_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_7_0", FIELD_fld_F0_S1_Ld_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_7_2", FIELD_fld_F0_S1_Ld_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_7_3", FIELD_fld_F0_S1_Ld_7_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_7_4", FIELD_fld_F0_S1_Ld_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_7_5", FIELD_fld_F0_S1_Ld_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_7_6", FIELD_fld_F0_S1_Ld_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_7_7", FIELD_fld_F0_S1_Ld_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_bbe_ltrx2nimm", FIELD_fld_bbe_ltrx2nimm, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_bbe_ltrxn_2imm", FIELD_fld_bbe_ltrxn_2imm, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_bbe_ltrxnimm", FIELD_fld_bbe_ltrxnimm, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_imm1_2N", FIELD_fld_imm1_2N, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_sqz_vbr", FIELD_fld_ivp_sem_sqz_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_sqz_vt", FIELD_fld_ivp_sem_sqz_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vbool_alu_ltr_art", FIELD_fld_ivp_sem_vbool_alu_ltr_art, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vbool_alu_ltr_vbr", FIELD_fld_ivp_sem_vbool_alu_ltr_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vbool_alu_ltr_vbs", FIELD_fld_ivp_sem_vbool_alu_ltr_vbs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vbool_alu_ltr_vbt", FIELD_fld_ivp_sem_vbool_alu_ltr_vbt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_mov_arr", FIELD_fld_ivp_sem_vec_mov_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_mov_i_IMM_movint", FIELD_fld_ivp_sem_vec_mov_i_IMM_movint, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_mov_i_imm4", FIELD_fld_ivp_sem_vec_mov_i_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_mov_immmovvi", FIELD_fld_ivp_sem_vec_mov_immmovvi, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_mov_vbr", FIELD_fld_ivp_sem_vec_mov_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_mov_vt", FIELD_fld_ivp_sem_vec_mov_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_mov_wvr", FIELD_fld_ivp_sem_vec_mov_wvr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_scatter_gather_gs", FIELD_fld_ivp_sem_vec_scatter_gather_gs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_scatter_gather_vt", FIELD_fld_ivp_sem_vec_scatter_gather_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_wvec_pack_arr", FIELD_fld_ivp_sem_wvec_pack_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_wvec_pack_vt", FIELD_fld_ivp_sem_wvec_pack_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_wvec_pack_wvr", FIELD_fld_ivp_sem_wvec_pack_wvr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_11_8", FIELD_fld_F0_S2_Mul_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_13_12", FIELD_fld_F0_S2_Mul_13_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_18_12", FIELD_fld_F0_S2_Mul_18_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_18_14", FIELD_fld_F0_S2_Mul_18_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_18_9", FIELD_fld_F0_S2_Mul_18_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_1_0", FIELD_fld_F0_S2_Mul_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_26_12", FIELD_fld_F0_S2_Mul_26_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_26_13", FIELD_fld_F0_S2_Mul_26_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_26_14", FIELD_fld_F0_S2_Mul_26_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_26_2", FIELD_fld_F0_S2_Mul_26_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_26_20", FIELD_fld_F0_S2_Mul_26_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_26_21", FIELD_fld_F0_S2_Mul_26_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_3_0", FIELD_fld_F0_S2_Mul_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_3_3", FIELD_fld_F0_S2_Mul_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_4_4", FIELD_fld_F0_S2_Mul_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_7_4", FIELD_fld_F0_S2_Mul_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_7_5", FIELD_fld_F0_S2_Mul_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_multiply_arr", FIELD_fld_ivp_sem_multiply_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_multiply_vp", FIELD_fld_ivp_sem_multiply_vp, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_multiply_vr", FIELD_fld_ivp_sem_multiply_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_multiply_vs", FIELD_fld_ivp_sem_multiply_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_multiply_wvt", FIELD_fld_ivp_sem_multiply_wvt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_unpack_wvec_mov_vr", FIELD_fld_ivp_sem_unpack_wvec_mov_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_unpack_wvec_mov_vs", FIELD_fld_ivp_sem_unpack_wvec_mov_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_unpack_wvec_mov_wvr", FIELD_fld_ivp_sem_unpack_wvec_mov_wvr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_unpack_wvec_mov_wvt", FIELD_fld_ivp_sem_unpack_wvec_mov_wvt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_alu_vbt", FIELD_fld_ivp_sem_vec_alu_vbt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_alu_vs", FIELD_fld_ivp_sem_vec_alu_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_0_0", FIELD_fld_F0_S3_ALU_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_14_10", FIELD_fld_F0_S3_ALU_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_14_11", FIELD_fld_F0_S3_ALU_14_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_14_13", FIELD_fld_F0_S3_ALU_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_14_14", FIELD_fld_F0_S3_ALU_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_14_8", FIELD_fld_F0_S3_ALU_14_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_24_10", FIELD_fld_F0_S3_ALU_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_24_13", FIELD_fld_F0_S3_ALU_24_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_24_19", FIELD_fld_F0_S3_ALU_24_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_24_20", FIELD_fld_F0_S3_ALU_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_10", FIELD_fld_F0_S3_ALU_33_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_13", FIELD_fld_F0_S3_ALU_33_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_18", FIELD_fld_F0_S3_ALU_33_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_19", FIELD_fld_F0_S3_ALU_33_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_20", FIELD_fld_F0_S3_ALU_33_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_25", FIELD_fld_F0_S3_ALU_33_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_26", FIELD_fld_F0_S3_ALU_33_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_27", FIELD_fld_F0_S3_ALU_33_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_28", FIELD_fld_F0_S3_ALU_33_28, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_9", FIELD_fld_F0_S3_ALU_33_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_3_0", FIELD_fld_F0_S3_ALU_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_3_1", FIELD_fld_F0_S3_ALU_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_3_2", FIELD_fld_F0_S3_ALU_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_3_3", FIELD_fld_F0_S3_ALU_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_7_3", FIELD_fld_F0_S3_ALU_7_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_7_4", FIELD_fld_F0_S3_ALU_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_7_7", FIELD_fld_F0_S3_ALU_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_8_0", FIELD_fld_F0_S3_ALU_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_8_8", FIELD_fld_F0_S3_ALU_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_9_0", FIELD_fld_F0_S3_ALU_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_9_7", FIELD_fld_F0_S3_ALU_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_9_8", FIELD_fld_F0_S3_ALU_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_fp_sem_hp_cnv_i_imm4", FIELD_fld_fp_sem_hp_cnv_i_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_fp_sem_hp_cnv_vbr", FIELD_fld_fp_sem_hp_cnv_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_fp_sem_hp_cnv_vr", FIELD_fld_fp_sem_hp_cnv_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_fp_sem_hp_cnv_vs", FIELD_fld_fp_sem_hp_cnv_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_fp_sem_hp_cnv_vt", FIELD_fld_fp_sem_hp_cnv_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_sp32cvt_i_imm5", FIELD_fld_ivp_sem_sp32cvt_i_imm5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_sp32cvt_vbr", FIELD_fld_ivp_sem_sp32cvt_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_sp32cvt_vr", FIELD_fld_ivp_sem_sp32cvt_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_sp32cvt_vt", FIELD_fld_ivp_sem_sp32cvt_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_spmisc_vbr", FIELD_fld_ivp_sem_spmisc_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_spmisc_vr", FIELD_fld_ivp_sem_spmisc_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_spmisc_vs", FIELD_fld_ivp_sem_spmisc_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_spmisc_vsM", FIELD_fld_ivp_sem_spmisc_vsM, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_spmisc_vt", FIELD_fld_ivp_sem_spmisc_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_alu_i_imm3", FIELD_fld_ivp_sem_vec_alu_i_imm3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_reduce_vbr", FIELD_fld_ivp_sem_vec_reduce_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_reduce_vbt", FIELD_fld_ivp_sem_vec_reduce_vbt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_reduce_vr", FIELD_fld_ivp_sem_vec_reduce_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_reduce_vt", FIELD_fld_ivp_sem_vec_reduce_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_rep_arr", FIELD_fld_ivp_sem_vec_rep_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_isel", FIELD_fld_ivp_sem_vec_select_isel, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_ishfl", FIELD_fld_ivp_sem_vec_select_ishfl, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_slct", FIELD_fld_ivp_sem_vec_select_slct, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_slct_h", FIELD_fld_ivp_sem_vec_select_slct_h, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_sr", FIELD_fld_ivp_sem_vec_select_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_vbr", FIELD_fld_ivp_sem_vec_select_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_vr", FIELD_fld_ivp_sem_vec_select_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_vs", FIELD_fld_ivp_sem_vec_select_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_vt", FIELD_fld_ivp_sem_vec_select_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_vu", FIELD_fld_ivp_sem_vec_select_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_shift_vs", FIELD_fld_ivp_sem_vec_shift_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_saimm6_31", FIELD_fld_saimm6_31, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_12_0", FIELD_fld_F1_S0_LdStALU_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_12_12", FIELD_fld_F1_S0_LdStALU_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_12_2", FIELD_fld_F1_S0_LdStALU_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_12_4", FIELD_fld_F1_S0_LdStALU_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_12_8", FIELD_fld_F1_S0_LdStALU_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_14_10", FIELD_fld_F1_S0_LdStALU_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_14_12", FIELD_fld_F1_S0_LdStALU_14_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_14_14", FIELD_fld_F1_S0_LdStALU_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_15_15", FIELD_fld_F1_S0_LdStALU_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_12", FIELD_fld_F1_S0_LdStALU_30_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_13", FIELD_fld_F1_S0_LdStALU_30_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_14", FIELD_fld_F1_S0_LdStALU_30_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_15", FIELD_fld_F1_S0_LdStALU_30_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_16", FIELD_fld_F1_S0_LdStALU_30_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_17", FIELD_fld_F1_S0_LdStALU_30_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_18", FIELD_fld_F1_S0_LdStALU_30_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_19", FIELD_fld_F1_S0_LdStALU_30_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_20", FIELD_fld_F1_S0_LdStALU_30_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_6", FIELD_fld_F1_S0_LdStALU_30_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_8", FIELD_fld_F1_S0_LdStALU_30_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_9", FIELD_fld_F1_S0_LdStALU_30_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_3_0", FIELD_fld_F1_S0_LdStALU_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_5_0", FIELD_fld_F1_S0_LdStALU_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_5_4", FIELD_fld_F1_S0_LdStALU_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_7_4", FIELD_fld_F1_S0_LdStALU_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_7_5", FIELD_fld_F1_S0_LdStALU_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_7_7", FIELD_fld_F1_S0_LdStALU_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_9_9", FIELD_fld_F1_S0_LdStALU_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_bbe_selimm_S0", FIELD_fld_bbe_selimm_S0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_scatter_gather_vr", FIELD_fld_ivp_sem_vec_scatter_gather_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_specialized_seli_vs", FIELD_fld_ivp_sem_vec_specialized_seli_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_12_10", FIELD_fld_F1_S1_Ld_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_12_11", FIELD_fld_F1_S1_Ld_12_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_12_12", FIELD_fld_F1_S1_Ld_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_12_4", FIELD_fld_F1_S1_Ld_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_12_9", FIELD_fld_F1_S1_Ld_12_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_15_10", FIELD_fld_F1_S1_Ld_15_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_15_13", FIELD_fld_F1_S1_Ld_15_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_15_14", FIELD_fld_F1_S1_Ld_15_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_15_15", FIELD_fld_F1_S1_Ld_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_15_2", FIELD_fld_F1_S1_Ld_15_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_15_4", FIELD_fld_F1_S1_Ld_15_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_15_8", FIELD_fld_F1_S1_Ld_15_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_1_0", FIELD_fld_F1_S1_Ld_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_26_11", FIELD_fld_F1_S1_Ld_26_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_26_12", FIELD_fld_F1_S1_Ld_26_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_26_13", FIELD_fld_F1_S1_Ld_26_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_26_16", FIELD_fld_F1_S1_Ld_26_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_26_18", FIELD_fld_F1_S1_Ld_26_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_26_2", FIELD_fld_F1_S1_Ld_26_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_3_0", FIELD_fld_F1_S1_Ld_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_3_2", FIELD_fld_F1_S1_Ld_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_7_0", FIELD_fld_F1_S1_Ld_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_7_2", FIELD_fld_F1_S1_Ld_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_7_3", FIELD_fld_F1_S1_Ld_7_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_7_4", FIELD_fld_F1_S1_Ld_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_7_5", FIELD_fld_F1_S1_Ld_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_7_6", FIELD_fld_F1_S1_Ld_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_7_7", FIELD_fld_F1_S1_Ld_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_13_10", FIELD_fld_F1_S2_Mul_13_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_13_2", FIELD_fld_F1_S2_Mul_13_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_13_5", FIELD_fld_F1_S2_Mul_13_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_14_10", FIELD_fld_F1_S2_Mul_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_28_12", FIELD_fld_F1_S2_Mul_28_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_28_15", FIELD_fld_F1_S2_Mul_28_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_28_16", FIELD_fld_F1_S2_Mul_28_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_28_18", FIELD_fld_F1_S2_Mul_28_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_28_20", FIELD_fld_F1_S2_Mul_28_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_28_4", FIELD_fld_F1_S2_Mul_28_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_28_5", FIELD_fld_F1_S2_Mul_28_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_3_0", FIELD_fld_F1_S2_Mul_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_3_2", FIELD_fld_F1_S2_Mul_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_3_3", FIELD_fld_F1_S2_Mul_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_4_4", FIELD_fld_F1_S2_Mul_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_9_5", FIELD_fld_F1_S2_Mul_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_9_6", FIELD_fld_F1_S2_Mul_9_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_bbe_selimm_S2", FIELD_fld_bbe_selimm_S2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_bbe_shflimm_S2", FIELD_fld_bbe_shflimm_S2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_fp_sem_hp_fma_vbr", FIELD_fld_fp_sem_hp_fma_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_fp_sem_hp_fma_vr", FIELD_fld_fp_sem_hp_fma_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_fp_sem_hp_fma_vs", FIELD_fld_fp_sem_hp_fma_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_fp_sem_hp_fma_vt", FIELD_fld_fp_sem_hp_fma_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_multiply_vt", FIELD_fld_ivp_sem_multiply_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_spfma_vbr", FIELD_fld_ivp_sem_spfma_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_spfma_vr", FIELD_fld_ivp_sem_spfma_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_spfma_vs", FIELD_fld_ivp_sem_spfma_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_spfma_vt", FIELD_fld_ivp_sem_spfma_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_unpack_wvec_mov_vt", FIELD_fld_ivp_sem_unpack_wvec_mov_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_0_0", FIELD_fld_F1_S3_ALU_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_14_10", FIELD_fld_F1_S3_ALU_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_14_13", FIELD_fld_F1_S3_ALU_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_14_14", FIELD_fld_F1_S3_ALU_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_14_8", FIELD_fld_F1_S3_ALU_14_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_19_14", FIELD_fld_F1_S3_ALU_19_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_19_15", FIELD_fld_F1_S3_ALU_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_19_19", FIELD_fld_F1_S3_ALU_19_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_19_4", FIELD_fld_F1_S3_ALU_19_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_19_7", FIELD_fld_F1_S3_ALU_19_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_30_15", FIELD_fld_F1_S3_ALU_30_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_30_17", FIELD_fld_F1_S3_ALU_30_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_30_19", FIELD_fld_F1_S3_ALU_30_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_30_20", FIELD_fld_F1_S3_ALU_30_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_30_22", FIELD_fld_F1_S3_ALU_30_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_30_23", FIELD_fld_F1_S3_ALU_30_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_30_6", FIELD_fld_F1_S3_ALU_30_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_30_8", FIELD_fld_F1_S3_ALU_30_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_3_0", FIELD_fld_F1_S3_ALU_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_3_1", FIELD_fld_F1_S3_ALU_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_3_2", FIELD_fld_F1_S3_ALU_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_3_3", FIELD_fld_F1_S3_ALU_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_5_0", FIELD_fld_F1_S3_ALU_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_9_0", FIELD_fld_F1_S3_ALU_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_9_1", FIELD_fld_F1_S3_ALU_9_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_9_2", FIELD_fld_F1_S3_ALU_9_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_9_3", FIELD_fld_F1_S3_ALU_9_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_9_7", FIELD_fld_F1_S3_ALU_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_9_8", FIELD_fld_F1_S3_ALU_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_9_9", FIELD_fld_F1_S3_ALU_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_histogram_arr", FIELD_fld_ivp_sem_vec_histogram_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_histogram_vr", FIELD_fld_ivp_sem_vec_histogram_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_histogram_vs", FIELD_fld_ivp_sem_vec_histogram_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_histogram_vt", FIELD_fld_ivp_sem_vec_histogram_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_12_0", FIELD_fld_F2_S0_LdSt_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_12_10", FIELD_fld_F2_S0_LdSt_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_12_2", FIELD_fld_F2_S0_LdSt_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_12_4", FIELD_fld_F2_S0_LdSt_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_12_8", FIELD_fld_F2_S0_LdSt_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_15_15", FIELD_fld_F2_S0_LdSt_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_11", FIELD_fld_F2_S0_LdSt_28_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_12", FIELD_fld_F2_S0_LdSt_28_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_13", FIELD_fld_F2_S0_LdSt_28_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_14", FIELD_fld_F2_S0_LdSt_28_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_15", FIELD_fld_F2_S0_LdSt_28_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_16", FIELD_fld_F2_S0_LdSt_28_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_17", FIELD_fld_F2_S0_LdSt_28_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_18", FIELD_fld_F2_S0_LdSt_28_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_20", FIELD_fld_F2_S0_LdSt_28_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_4", FIELD_fld_F2_S0_LdSt_28_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_8", FIELD_fld_F2_S0_LdSt_28_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_3_0", FIELD_fld_F2_S0_LdSt_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_3_2", FIELD_fld_F2_S0_LdSt_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_7_2", FIELD_fld_F2_S0_LdSt_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_7_4", FIELD_fld_F2_S0_LdSt_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_12_10", FIELD_fld_F2_S1_Ld_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_12_11", FIELD_fld_F2_S1_Ld_12_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_12_4", FIELD_fld_F2_S1_Ld_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_12_9", FIELD_fld_F2_S1_Ld_12_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_15_10", FIELD_fld_F2_S1_Ld_15_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_15_13", FIELD_fld_F2_S1_Ld_15_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_15_14", FIELD_fld_F2_S1_Ld_15_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_15_15", FIELD_fld_F2_S1_Ld_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_15_2", FIELD_fld_F2_S1_Ld_15_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_15_4", FIELD_fld_F2_S1_Ld_15_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_15_8", FIELD_fld_F2_S1_Ld_15_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_1_0", FIELD_fld_F2_S1_Ld_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_26_11", FIELD_fld_F2_S1_Ld_26_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_26_12", FIELD_fld_F2_S1_Ld_26_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_26_13", FIELD_fld_F2_S1_Ld_26_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_26_16", FIELD_fld_F2_S1_Ld_26_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_26_18", FIELD_fld_F2_S1_Ld_26_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_26_2", FIELD_fld_F2_S1_Ld_26_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_3_0", FIELD_fld_F2_S1_Ld_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_3_2", FIELD_fld_F2_S1_Ld_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_7_0", FIELD_fld_F2_S1_Ld_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_7_2", FIELD_fld_F2_S1_Ld_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_7_3", FIELD_fld_F2_S1_Ld_7_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_7_4", FIELD_fld_F2_S1_Ld_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_7_6", FIELD_fld_F2_S1_Ld_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_7_7", FIELD_fld_F2_S1_Ld_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_14_10", FIELD_fld_F2_S2_Mul_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_14_11", FIELD_fld_F2_S2_Mul_14_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_14_5", FIELD_fld_F2_S2_Mul_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_19_10", FIELD_fld_F2_S2_Mul_19_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_19_15", FIELD_fld_F2_S2_Mul_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_19_7", FIELD_fld_F2_S2_Mul_19_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_30_10", FIELD_fld_F2_S2_Mul_30_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_30_12", FIELD_fld_F2_S2_Mul_30_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_30_15", FIELD_fld_F2_S2_Mul_30_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_30_18", FIELD_fld_F2_S2_Mul_30_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_30_19", FIELD_fld_F2_S2_Mul_30_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_30_20", FIELD_fld_F2_S2_Mul_30_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_30_21", FIELD_fld_F2_S2_Mul_30_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_30_6", FIELD_fld_F2_S2_Mul_30_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_3_0", FIELD_fld_F2_S2_Mul_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_4_0", FIELD_fld_F2_S2_Mul_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_4_3", FIELD_fld_F2_S2_Mul_4_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_5_0", FIELD_fld_F2_S2_Mul_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_divide_lane_ctrl", FIELD_fld_ivp_sem_divide_lane_ctrl, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_divide_vr", FIELD_fld_ivp_sem_divide_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_divide_vs", FIELD_fld_ivp_sem_divide_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_divide_vt", FIELD_fld_ivp_sem_divide_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_divide_vu", FIELD_fld_ivp_sem_divide_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_multiply_vbr", FIELD_fld_ivp_sem_multiply_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_0_0", FIELD_fld_F2_S3_ALU_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_14_10", FIELD_fld_F2_S3_ALU_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_14_13", FIELD_fld_F2_S3_ALU_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_14_14", FIELD_fld_F2_S3_ALU_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_14_8", FIELD_fld_F2_S3_ALU_14_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_19_14", FIELD_fld_F2_S3_ALU_19_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_19_15", FIELD_fld_F2_S3_ALU_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_19_19", FIELD_fld_F2_S3_ALU_19_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_19_4", FIELD_fld_F2_S3_ALU_19_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_19_7", FIELD_fld_F2_S3_ALU_19_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_30_15", FIELD_fld_F2_S3_ALU_30_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_30_18", FIELD_fld_F2_S3_ALU_30_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_30_19", FIELD_fld_F2_S3_ALU_30_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_30_20", FIELD_fld_F2_S3_ALU_30_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_30_22", FIELD_fld_F2_S3_ALU_30_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_30_23", FIELD_fld_F2_S3_ALU_30_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_30_6", FIELD_fld_F2_S3_ALU_30_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_30_8", FIELD_fld_F2_S3_ALU_30_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_3_0", FIELD_fld_F2_S3_ALU_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_3_1", FIELD_fld_F2_S3_ALU_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_3_2", FIELD_fld_F2_S3_ALU_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_3_3", FIELD_fld_F2_S3_ALU_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_5_0", FIELD_fld_F2_S3_ALU_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_9_0", FIELD_fld_F2_S3_ALU_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_9_1", FIELD_fld_F2_S3_ALU_9_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_9_2", FIELD_fld_F2_S3_ALU_9_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_9_3", FIELD_fld_F2_S3_ALU_9_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_9_7", FIELD_fld_F2_S3_ALU_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_9_8", FIELD_fld_F2_S3_ALU_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_9_9", FIELD_fld_F2_S3_ALU_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_0_0", FIELD_fld_F3_S0_LdSt_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_12_0", FIELD_fld_F3_S0_LdSt_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_12_11", FIELD_fld_F3_S0_LdSt_12_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_12_12", FIELD_fld_F3_S0_LdSt_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_12_4", FIELD_fld_F3_S0_LdSt_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_12_8", FIELD_fld_F3_S0_LdSt_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_13_9", FIELD_fld_F3_S0_LdSt_13_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_15_15", FIELD_fld_F3_S0_LdSt_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_1", FIELD_fld_F3_S0_LdSt_25_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_11", FIELD_fld_F3_S0_LdSt_25_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_12", FIELD_fld_F3_S0_LdSt_25_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_13", FIELD_fld_F3_S0_LdSt_25_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_14", FIELD_fld_F3_S0_LdSt_25_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_15", FIELD_fld_F3_S0_LdSt_25_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_16", FIELD_fld_F3_S0_LdSt_25_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_17", FIELD_fld_F3_S0_LdSt_25_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_18", FIELD_fld_F3_S0_LdSt_25_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_19", FIELD_fld_F3_S0_LdSt_25_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_20", FIELD_fld_F3_S0_LdSt_25_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_4", FIELD_fld_F3_S0_LdSt_25_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_8", FIELD_fld_F3_S0_LdSt_25_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_9", FIELD_fld_F3_S0_LdSt_25_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_3_0", FIELD_fld_F3_S0_LdSt_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_7_4", FIELD_fld_F3_S0_LdSt_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_7_5", FIELD_fld_F3_S0_LdSt_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_7_7", FIELD_fld_F3_S0_LdSt_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_8_0", FIELD_fld_F3_S0_LdSt_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_12_11", FIELD_fld_F3_S1_Ld_12_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_12_2", FIELD_fld_F3_S1_Ld_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_12_4", FIELD_fld_F3_S1_Ld_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_12_8", FIELD_fld_F3_S1_Ld_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_0", FIELD_fld_F3_S1_Ld_21_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_10", FIELD_fld_F3_S1_Ld_21_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_11", FIELD_fld_F3_S1_Ld_21_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_12", FIELD_fld_F3_S1_Ld_21_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_13", FIELD_fld_F3_S1_Ld_21_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_15", FIELD_fld_F3_S1_Ld_21_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_16", FIELD_fld_F3_S1_Ld_21_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_17", FIELD_fld_F3_S1_Ld_21_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_8", FIELD_fld_F3_S1_Ld_21_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_9", FIELD_fld_F3_S1_Ld_21_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_3_0", FIELD_fld_F3_S1_Ld_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_3_2", FIELD_fld_F3_S1_Ld_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_4_0", FIELD_fld_F3_S1_Ld_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_4_3", FIELD_fld_F3_S1_Ld_4_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_4_4", FIELD_fld_F3_S1_Ld_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_7_0", FIELD_fld_F3_S1_Ld_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_7_2", FIELD_fld_F3_S1_Ld_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_7_4", FIELD_fld_F3_S1_Ld_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_7_7", FIELD_fld_F3_S1_Ld_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_11_8", FIELD_fld_F3_S2_Mul_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_13_12", FIELD_fld_F3_S2_Mul_13_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_13_7", FIELD_fld_F3_S2_Mul_13_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_21_0", FIELD_fld_F3_S2_Mul_21_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_21_12", FIELD_fld_F3_S2_Mul_21_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_21_13", FIELD_fld_F3_S2_Mul_21_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_21_14", FIELD_fld_F3_S2_Mul_21_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_21_15", FIELD_fld_F3_S2_Mul_21_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_21_16", FIELD_fld_F3_S2_Mul_21_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_3_0", FIELD_fld_F3_S2_Mul_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_3_3", FIELD_fld_F3_S2_Mul_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_4_0", FIELD_fld_F3_S2_Mul_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_7_4", FIELD_fld_F3_S2_Mul_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_7_5", FIELD_fld_F3_S2_Mul_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_13_9", FIELD_fld_F3_S3_ALU_13_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_18_12", FIELD_fld_F3_S3_ALU_18_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_18_13", FIELD_fld_F3_S3_ALU_18_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_18_14", FIELD_fld_F3_S3_ALU_18_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_18_18", FIELD_fld_F3_S3_ALU_18_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_18_3", FIELD_fld_F3_S3_ALU_18_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_18_7", FIELD_fld_F3_S3_ALU_18_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_18_8", FIELD_fld_F3_S3_ALU_18_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_12", FIELD_fld_F3_S3_ALU_28_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_13", FIELD_fld_F3_S3_ALU_28_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_14", FIELD_fld_F3_S3_ALU_28_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_18", FIELD_fld_F3_S3_ALU_28_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_19", FIELD_fld_F3_S3_ALU_28_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_20", FIELD_fld_F3_S3_ALU_28_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_21", FIELD_fld_F3_S3_ALU_28_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_22", FIELD_fld_F3_S3_ALU_28_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_25", FIELD_fld_F3_S3_ALU_28_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_4", FIELD_fld_F3_S3_ALU_28_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_8", FIELD_fld_F3_S3_ALU_28_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_9", FIELD_fld_F3_S3_ALU_28_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_3_0", FIELD_fld_F3_S3_ALU_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_3_2", FIELD_fld_F3_S3_ALU_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_3_3", FIELD_fld_F3_S3_ALU_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_7_3", FIELD_fld_F3_S3_ALU_7_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_7_6", FIELD_fld_F3_S3_ALU_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_7_7", FIELD_fld_F3_S3_ALU_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_8_0", FIELD_fld_F3_S3_ALU_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_histogram_vbr", FIELD_fld_ivp_sem_vec_histogram_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_histogram_vbs", FIELD_fld_ivp_sem_vec_histogram_vbs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S4_ALU_14_10", FIELD_fld_F3_S4_ALU_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S4_ALU_23_0", FIELD_fld_F3_S4_ALU_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S4_ALU_23_15", FIELD_fld_F3_S4_ALU_23_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S4_ALU_23_18", FIELD_fld_F3_S4_ALU_23_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S4_ALU_23_20", FIELD_fld_F3_S4_ALU_23_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S4_ALU_9_5", FIELD_fld_F3_S4_ALU_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S4_ALU_9_6", FIELD_fld_F3_S4_ALU_9_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_bbe_selimm_S4", FIELD_fld_bbe_selimm_S4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_bbe_shflimm_S4", FIELD_fld_bbe_shflimm_S4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_11_4", FIELD_fld_F4_S0_Ld_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_11_8", FIELD_fld_F4_S0_Ld_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_11_9", FIELD_fld_F4_S0_Ld_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_12_0", FIELD_fld_F4_S0_Ld_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_12_2", FIELD_fld_F4_S0_Ld_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_12_4", FIELD_fld_F4_S0_Ld_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_12_8", FIELD_fld_F4_S0_Ld_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_15_15", FIELD_fld_F4_S0_Ld_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_12", FIELD_fld_F4_S0_Ld_31_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_13", FIELD_fld_F4_S0_Ld_31_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_15", FIELD_fld_F4_S0_Ld_31_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_16", FIELD_fld_F4_S0_Ld_31_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_17", FIELD_fld_F4_S0_Ld_31_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_18", FIELD_fld_F4_S0_Ld_31_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_20", FIELD_fld_F4_S0_Ld_31_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_27", FIELD_fld_F4_S0_Ld_31_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_7", FIELD_fld_F4_S0_Ld_31_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_8", FIELD_fld_F4_S0_Ld_31_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_9", FIELD_fld_F4_S0_Ld_31_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_3_0", FIELD_fld_F4_S0_Ld_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_6_0", FIELD_fld_F4_S0_Ld_6_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_6_4", FIELD_fld_F4_S0_Ld_6_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_7_4", FIELD_fld_F4_S0_Ld_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_12_10", FIELD_fld_F4_S1_Ld_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_12_2", FIELD_fld_F4_S1_Ld_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_12_4", FIELD_fld_F4_S1_Ld_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_12_8", FIELD_fld_F4_S1_Ld_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_0", FIELD_fld_F4_S1_Ld_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_10", FIELD_fld_F4_S1_Ld_23_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_11", FIELD_fld_F4_S1_Ld_23_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_12", FIELD_fld_F4_S1_Ld_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_13", FIELD_fld_F4_S1_Ld_23_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_15", FIELD_fld_F4_S1_Ld_23_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_16", FIELD_fld_F4_S1_Ld_23_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_17", FIELD_fld_F4_S1_Ld_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_8", FIELD_fld_F4_S1_Ld_23_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_9", FIELD_fld_F4_S1_Ld_23_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_3_0", FIELD_fld_F4_S1_Ld_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_3_2", FIELD_fld_F4_S1_Ld_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_4_0", FIELD_fld_F4_S1_Ld_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_4_3", FIELD_fld_F4_S1_Ld_4_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_4_4", FIELD_fld_F4_S1_Ld_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_7_0", FIELD_fld_F4_S1_Ld_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_7_2", FIELD_fld_F4_S1_Ld_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_7_4", FIELD_fld_F4_S1_Ld_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_7_6", FIELD_fld_F4_S1_Ld_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_7_7", FIELD_fld_F4_S1_Ld_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S2_Mul_32_26", FIELD_fld_F4_S2_Mul_32_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S2_Mul_32_8", FIELD_fld_F4_S2_Mul_32_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S2_Mul_3_0", FIELD_fld_F4_S2_Mul_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S2_Mul_7_0", FIELD_fld_F4_S2_Mul_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_multiply_vq", FIELD_fld_ivp_sem_multiply_vq, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_0_0", FIELD_fld_F4_S3_ALU_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_14_10", FIELD_fld_F4_S3_ALU_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_14_11", FIELD_fld_F4_S3_ALU_14_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_14_12", FIELD_fld_F4_S3_ALU_14_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_14_13", FIELD_fld_F4_S3_ALU_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_14_14", FIELD_fld_F4_S3_ALU_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_14_6", FIELD_fld_F4_S3_ALU_14_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_14_8", FIELD_fld_F4_S3_ALU_14_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_19_13", FIELD_fld_F4_S3_ALU_19_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_19_6", FIELD_fld_F4_S3_ALU_19_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_19_8", FIELD_fld_F4_S3_ALU_19_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_24_12", FIELD_fld_F4_S3_ALU_24_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_24_13", FIELD_fld_F4_S3_ALU_24_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_24_18", FIELD_fld_F4_S3_ALU_24_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_24_20", FIELD_fld_F4_S3_ALU_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_24_21", FIELD_fld_F4_S3_ALU_24_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_31_13", FIELD_fld_F4_S3_ALU_31_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_31_19", FIELD_fld_F4_S3_ALU_31_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_31_20", FIELD_fld_F4_S3_ALU_31_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_31_23", FIELD_fld_F4_S3_ALU_31_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_31_25", FIELD_fld_F4_S3_ALU_31_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_31_26", FIELD_fld_F4_S3_ALU_31_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_31_28", FIELD_fld_F4_S3_ALU_31_28, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_31_7", FIELD_fld_F4_S3_ALU_31_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_31_8", FIELD_fld_F4_S3_ALU_31_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_3_0", FIELD_fld_F4_S3_ALU_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_3_1", FIELD_fld_F4_S3_ALU_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_3_2", FIELD_fld_F4_S3_ALU_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_3_3", FIELD_fld_F4_S3_ALU_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_6_0", FIELD_fld_F4_S3_ALU_6_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_7_4", FIELD_fld_F4_S3_ALU_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_7_5", FIELD_fld_F4_S3_ALU_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_9_8", FIELD_fld_F4_S3_ALU_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_11_0", FIELD_fld_F5_S0_Base_11_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_11_8", FIELD_fld_F5_S0_Base_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_11_9", FIELD_fld_F5_S0_Base_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_36_12", FIELD_fld_F5_S0_Base_36_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_36_13", FIELD_fld_F5_S0_Base_36_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_36_16", FIELD_fld_F5_S0_Base_36_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_36_17", FIELD_fld_F5_S0_Base_36_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_36_18", FIELD_fld_F5_S0_Base_36_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_36_20", FIELD_fld_F5_S0_Base_36_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_36_27", FIELD_fld_F5_S0_Base_36_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_3_0", FIELD_fld_F5_S0_Base_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_3_1", FIELD_fld_F5_S0_Base_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_7_4", FIELD_fld_F5_S0_Base_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S1_Base_27_12", FIELD_fld_F5_S1_Base_27_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S1_Base_27_13", FIELD_fld_F5_S1_Base_27_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S1_Base_27_16", FIELD_fld_F5_S1_Base_27_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S1_Base_27_17", FIELD_fld_F5_S1_Base_27_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S1_Base_27_3", FIELD_fld_F5_S1_Base_27_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S1_Base_2_0", FIELD_fld_F5_S1_Base_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S1_Base_3_0", FIELD_fld_F5_S1_Base_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S1_Base_7_4", FIELD_fld_F5_S1_Base_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S2_Base_1_0", FIELD_fld_F5_S2_Base_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S2_Base_26_12", FIELD_fld_F5_S2_Base_26_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S2_Base_26_13", FIELD_fld_F5_S2_Base_26_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S2_Base_26_16", FIELD_fld_F5_S2_Base_26_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S2_Base_26_2", FIELD_fld_F5_S2_Base_26_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S2_Base_26_8", FIELD_fld_F5_S2_Base_26_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S2_Base_3_0", FIELD_fld_F5_S2_Base_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S2_Base_7_4", FIELD_fld_F5_S2_Base_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S3_Base_0_0", FIELD_fld_F5_S3_Base_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S3_Base_25_1", FIELD_fld_F5_S3_Base_25_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S3_Base_25_16", FIELD_fld_F5_S3_Base_25_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S3_Base_25_8", FIELD_fld_F5_S3_Base_25_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_1_0", FIELD_fld_F11_S0_Ld_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_23_0", FIELD_fld_F11_S0_Ld_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_23_12", FIELD_fld_F11_S0_Ld_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_23_13", FIELD_fld_F11_S0_Ld_23_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_23_16", FIELD_fld_F11_S0_Ld_23_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_23_17", FIELD_fld_F11_S0_Ld_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_23_20", FIELD_fld_F11_S0_Ld_23_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_23_4", FIELD_fld_F11_S0_Ld_23_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_3_0", FIELD_fld_F11_S0_Ld_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_7_4", FIELD_fld_F11_S0_Ld_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_12_10", FIELD_fld_F11_S1_ALU_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_12_11", FIELD_fld_F11_S1_ALU_12_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_12_12", FIELD_fld_F11_S1_ALU_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_12_3", FIELD_fld_F11_S1_ALU_12_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_12_4", FIELD_fld_F11_S1_ALU_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_12_9", FIELD_fld_F11_S1_ALU_12_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_15_13", FIELD_fld_F11_S1_ALU_15_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_15_14", FIELD_fld_F11_S1_ALU_15_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_15_15", FIELD_fld_F11_S1_ALU_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_15_2", FIELD_fld_F11_S1_ALU_15_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_22_0", FIELD_fld_F11_S1_ALU_22_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_22_12", FIELD_fld_F11_S1_ALU_22_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_22_13", FIELD_fld_F11_S1_ALU_22_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_22_14", FIELD_fld_F11_S1_ALU_22_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_22_16", FIELD_fld_F11_S1_ALU_22_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_22_18", FIELD_fld_F11_S1_ALU_22_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_3_0", FIELD_fld_F11_S1_ALU_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_7_4", FIELD_fld_F11_S1_ALU_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_vrul2", FIELD_fld_ivp_sem_ld_st_vrul2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_11_8", FIELD_fld_F11_S2_Mul_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_13_12", FIELD_fld_F11_S2_Mul_13_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_13_7", FIELD_fld_F11_S2_Mul_13_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_22_0", FIELD_fld_F11_S2_Mul_22_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_22_12", FIELD_fld_F11_S2_Mul_22_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_22_13", FIELD_fld_F11_S2_Mul_22_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_22_14", FIELD_fld_F11_S2_Mul_22_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_22_15", FIELD_fld_F11_S2_Mul_22_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_22_16", FIELD_fld_F11_S2_Mul_22_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_22_8", FIELD_fld_F11_S2_Mul_22_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_3_0", FIELD_fld_F11_S2_Mul_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_3_3", FIELD_fld_F11_S2_Mul_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_4_0", FIELD_fld_F11_S2_Mul_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_7_4", FIELD_fld_F11_S2_Mul_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_7_5", FIELD_fld_F11_S2_Mul_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_0_0", FIELD_fld_F11_S3_ALU_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_14_10", FIELD_fld_F11_S3_ALU_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_14_11", FIELD_fld_F11_S3_ALU_14_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_14_13", FIELD_fld_F11_S3_ALU_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_14_8", FIELD_fld_F11_S3_ALU_14_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_1", FIELD_fld_F11_S3_ALU_25_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_11", FIELD_fld_F11_S3_ALU_25_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_13", FIELD_fld_F11_S3_ALU_25_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_14", FIELD_fld_F11_S3_ALU_25_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_15", FIELD_fld_F11_S3_ALU_25_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_16", FIELD_fld_F11_S3_ALU_25_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_17", FIELD_fld_F11_S3_ALU_25_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_18", FIELD_fld_F11_S3_ALU_25_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_22", FIELD_fld_F11_S3_ALU_25_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_8", FIELD_fld_F11_S3_ALU_25_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_3_0", FIELD_fld_F11_S3_ALU_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_3_1", FIELD_fld_F11_S3_ALU_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_7_0", FIELD_fld_F11_S3_ALU_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_7_4", FIELD_fld_F11_S3_ALU_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_9_8", FIELD_fld_F11_S3_ALU_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_9_9", FIELD_fld_F11_S3_ALU_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S4_ALU_24_0", FIELD_fld_F11_S4_ALU_24_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S4_ALU_24_15", FIELD_fld_F11_S4_ALU_24_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S4_ALU_24_18", FIELD_fld_F11_S4_ALU_24_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S4_ALU_9_5", FIELD_fld_F11_S4_ALU_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_12_0", FIELD_fld_N1_S0_LdSt_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_12_12", FIELD_fld_N1_S0_LdSt_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_12_2", FIELD_fld_N1_S0_LdSt_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_12_4", FIELD_fld_N1_S0_LdSt_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_12_8", FIELD_fld_N1_S0_LdSt_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_15_15", FIELD_fld_N1_S0_LdSt_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_1_0", FIELD_fld_N1_S0_LdSt_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_12", FIELD_fld_N1_S0_LdSt_26_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_13", FIELD_fld_N1_S0_LdSt_26_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_15", FIELD_fld_N1_S0_LdSt_26_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_16", FIELD_fld_N1_S0_LdSt_26_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_17", FIELD_fld_N1_S0_LdSt_26_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_18", FIELD_fld_N1_S0_LdSt_26_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_2", FIELD_fld_N1_S0_LdSt_26_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_20", FIELD_fld_N1_S0_LdSt_26_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_4", FIELD_fld_N1_S0_LdSt_26_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_8", FIELD_fld_N1_S0_LdSt_26_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_9", FIELD_fld_N1_S0_LdSt_26_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_3_0", FIELD_fld_N1_S0_LdSt_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_3_2", FIELD_fld_N1_S0_LdSt_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_7_2", FIELD_fld_N1_S0_LdSt_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_7_4", FIELD_fld_N1_S0_LdSt_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_7_5", FIELD_fld_N1_S0_LdSt_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_7_6", FIELD_fld_N1_S0_LdSt_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S1_None_3_0", FIELD_fld_N1_S1_None_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_0_0", FIELD_fld_N1_S2_Mul_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_13_9", FIELD_fld_N1_S2_Mul_13_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_18_14", FIELD_fld_N1_S2_Mul_18_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_18_6", FIELD_fld_N1_S2_Mul_18_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_18_9", FIELD_fld_N1_S2_Mul_18_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_25_1", FIELD_fld_N1_S2_Mul_25_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_25_12", FIELD_fld_N1_S2_Mul_25_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_25_14", FIELD_fld_N1_S2_Mul_25_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_25_19", FIELD_fld_N1_S2_Mul_25_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_25_21", FIELD_fld_N1_S2_Mul_25_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_3_0", FIELD_fld_N1_S2_Mul_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_3_3", FIELD_fld_N1_S2_Mul_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_7_4", FIELD_fld_N1_S2_Mul_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_8_4", FIELD_fld_N1_S2_Mul_8_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_8_8", FIELD_fld_N1_S2_Mul_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_12_0", FIELD_fld_N2_S0_LdSt_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_12_10", FIELD_fld_N2_S0_LdSt_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_12_11", FIELD_fld_N2_S0_LdSt_12_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_12_12", FIELD_fld_N2_S0_LdSt_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_12_4", FIELD_fld_N2_S0_LdSt_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_12_8", FIELD_fld_N2_S0_LdSt_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_13_11", FIELD_fld_N2_S0_LdSt_13_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_15_15", FIELD_fld_N2_S0_LdSt_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_10", FIELD_fld_N2_S0_LdSt_29_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_11", FIELD_fld_N2_S0_LdSt_29_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_12", FIELD_fld_N2_S0_LdSt_29_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_13", FIELD_fld_N2_S0_LdSt_29_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_14", FIELD_fld_N2_S0_LdSt_29_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_15", FIELD_fld_N2_S0_LdSt_29_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_16", FIELD_fld_N2_S0_LdSt_29_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_17", FIELD_fld_N2_S0_LdSt_29_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_18", FIELD_fld_N2_S0_LdSt_29_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_20", FIELD_fld_N2_S0_LdSt_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_5", FIELD_fld_N2_S0_LdSt_29_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_8", FIELD_fld_N2_S0_LdSt_29_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_3_0", FIELD_fld_N2_S0_LdSt_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_4_0", FIELD_fld_N2_S0_LdSt_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_4_4", FIELD_fld_N2_S0_LdSt_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_7_4", FIELD_fld_N2_S0_LdSt_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_7_6", FIELD_fld_N2_S0_LdSt_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_8_0", FIELD_fld_N2_S0_LdSt_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_8_4", FIELD_fld_N2_S0_LdSt_8_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_9_5", FIELD_fld_N2_S0_LdSt_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_9_6", FIELD_fld_N2_S0_LdSt_9_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_12_10", FIELD_fld_N2_S1_Ld_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_12_2", FIELD_fld_N2_S1_Ld_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_12_4", FIELD_fld_N2_S1_Ld_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_12_8", FIELD_fld_N2_S1_Ld_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_1_0", FIELD_fld_N2_S1_Ld_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_10", FIELD_fld_N2_S1_Ld_26_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_11", FIELD_fld_N2_S1_Ld_26_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_12", FIELD_fld_N2_S1_Ld_26_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_13", FIELD_fld_N2_S1_Ld_26_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_15", FIELD_fld_N2_S1_Ld_26_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_16", FIELD_fld_N2_S1_Ld_26_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_17", FIELD_fld_N2_S1_Ld_26_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_2", FIELD_fld_N2_S1_Ld_26_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_8", FIELD_fld_N2_S1_Ld_26_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_9", FIELD_fld_N2_S1_Ld_26_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_3_0", FIELD_fld_N2_S1_Ld_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_3_2", FIELD_fld_N2_S1_Ld_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_4_0", FIELD_fld_N2_S1_Ld_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_4_3", FIELD_fld_N2_S1_Ld_4_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_4_4", FIELD_fld_N2_S1_Ld_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_7_0", FIELD_fld_N2_S1_Ld_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_7_2", FIELD_fld_N2_S1_Ld_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_7_4", FIELD_fld_N2_S1_Ld_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_7_6", FIELD_fld_N2_S1_Ld_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_7_7", FIELD_fld_N2_S1_Ld_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_12_0", FIELD_fld_N0_S0_LdSt_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_12_12", FIELD_fld_N0_S0_LdSt_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_12_2", FIELD_fld_N0_S0_LdSt_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_12_4", FIELD_fld_N0_S0_LdSt_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_12_8", FIELD_fld_N0_S0_LdSt_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_22_0", FIELD_fld_N0_S0_LdSt_22_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_22_12", FIELD_fld_N0_S0_LdSt_22_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_22_13", FIELD_fld_N0_S0_LdSt_22_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_22_15", FIELD_fld_N0_S0_LdSt_22_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_22_16", FIELD_fld_N0_S0_LdSt_22_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_22_17", FIELD_fld_N0_S0_LdSt_22_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_3_0", FIELD_fld_N0_S0_LdSt_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_7_4", FIELD_fld_N0_S0_LdSt_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_7_5", FIELD_fld_N0_S0_LdSt_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_7_6", FIELD_fld_N0_S0_LdSt_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S1_None_2_0", FIELD_fld_N0_S1_None_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S2_None_2_0", FIELD_fld_N0_S2_None_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_14_10", FIELD_fld_N0_S3_ALU_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_14_13", FIELD_fld_N0_S3_ALU_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_14_14", FIELD_fld_N0_S3_ALU_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_14_5", FIELD_fld_N0_S3_ALU_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_19_12", FIELD_fld_N0_S3_ALU_19_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_19_13", FIELD_fld_N0_S3_ALU_19_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_19_15", FIELD_fld_N0_S3_ALU_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_27_12", FIELD_fld_N0_S3_ALU_27_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_27_13", FIELD_fld_N0_S3_ALU_27_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_27_15", FIELD_fld_N0_S3_ALU_27_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_27_16", FIELD_fld_N0_S3_ALU_27_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_27_19", FIELD_fld_N0_S3_ALU_27_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_27_20", FIELD_fld_N0_S3_ALU_27_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_27_22", FIELD_fld_N0_S3_ALU_27_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_27_23", FIELD_fld_N0_S3_ALU_27_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_27_3", FIELD_fld_N0_S3_ALU_27_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_2_0", FIELD_fld_N0_S3_ALU_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_3_0", FIELD_fld_N0_S3_ALU_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_7_0", FIELD_fld_N0_S3_ALU_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_9_0", FIELD_fld_N0_S3_ALU_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_9_3", FIELD_fld_N0_S3_ALU_9_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_9_4", FIELD_fld_N0_S3_ALU_9_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_9_5", FIELD_fld_N0_S3_ALU_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_9_6", FIELD_fld_N0_S3_ALU_9_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_9_7", FIELD_fld_N0_S3_ALU_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_9_9", FIELD_fld_N0_S3_ALU_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_MTK_AndPOPC_c", FIELD_fld_MTK_AndPOPC_c, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_MTK_AndPOPC_inB", FIELD_fld_MTK_AndPOPC_inB, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_MTK_AndPOPC_inA", FIELD_fld_MTK_AndPOPC_inA, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_MTK_AndPOPC_oData", FIELD_fld_MTK_AndPOPC_oData, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S4_ALU_24_16", FIELD_fld_F11_S4_ALU_24_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S4_ALU_23_16", FIELD_fld_F3_S4_ALU_23_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_iq_tie2apb_inq0_pop_qdata", FIELD_fld_iq_tie2apb_inq0_pop_qdata, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_iq_tie2apb_inq0_is_ready_is_ready", FIELD_fld_iq_tie2apb_inq0_is_ready_is_ready, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_11_8", FIELD_fld_Inst_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_iq_tie2apb_inq0_nonblocking_peek_success", FIELD_fld_iq_tie2apb_inq0_nonblocking_peek_success, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_iq_tie2apb_inq0_nonblocking_peek_qdata", FIELD_fld_iq_tie2apb_inq0_nonblocking_peek_qdata, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_iq_tie2apb_inq0_nonblocking_pop_success", FIELD_fld_iq_tie2apb_inq0_nonblocking_pop_success, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_iq_tie2apb_inq0_nonblocking_pop_qdata", FIELD_fld_iq_tie2apb_inq0_nonblocking_pop_qdata, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_23_8", FIELD_fld_Inst_23_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_iq_tie2apb_inq0_blocking_peek_qdata", FIELD_fld_iq_tie2apb_inq0_blocking_peek_qdata, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_23_12", FIELD_fld_Inst_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_push_read_qaddr", FIELD_fld_oq_tie2apb_outq0_push_read_qaddr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_push_read_qdata", FIELD_fld_oq_tie2apb_outq0_push_read_qdata, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_push_write_qaddr", FIELD_fld_oq_tie2apb_outq0_push_write_qaddr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_push_write_qdata", FIELD_fld_oq_tie2apb_outq0_push_write_qdata, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_is_ready_is_ready", FIELD_fld_oq_tie2apb_outq0_is_ready_is_ready, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_3_0", FIELD_fld_Inst_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_23_16", FIELD_fld_Inst_23_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_nonblocking_push_read_success", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_read_success, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_nonblocking_push_read_qaddr", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_read_qaddr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_nonblocking_push_read_qdata", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_read_qdata, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_nonblocking_push_write_success", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_write_success, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_nonblocking_push_write_qaddr", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_write_qaddr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_nonblocking_push_write_qdata", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_write_qdata, -1, 0, 0, 0, 0, 0, 0 } +}; + +enum xtensa_operand_id { + OPERAND_soffsetx4, + OPERAND_uimm12x8, + OPERAND_simm4, + OPERAND_arr, + OPERAND_ars, + OPERAND__ars_invisible, + OPERAND_art, + OPERAND_ar0, + OPERAND_ar4, + OPERAND_ar8, + OPERAND_ar12, + OPERAND_ars_entry, + OPERAND_immrx4, + OPERAND_lsi4x4, + OPERAND_simm7, + OPERAND_uimm6, + OPERAND_ai4const, + OPERAND_b4const, + OPERAND_b4constu, + OPERAND_uimm8, + OPERAND_uimm8x2, + OPERAND_uimm8x4, + OPERAND_uimm4x16, + OPERAND_uimmrx4, + OPERAND_simm8, + OPERAND_simm8x256, + OPERAND_simm12b, + OPERAND_msalp32, + OPERAND_op2p1, + OPERAND_label8, + OPERAND_ulabel8, + OPERAND_label12, + OPERAND_soffset, + OPERAND_uimm16x4, + OPERAND_bbi, + OPERAND_imm16, + OPERAND_sae, + OPERAND_sas, + OPERAND_sargt, + OPERAND_s, + OPERAND_immt, + OPERAND_imms, + OPERAND_bt, + OPERAND_bs, + OPERAND_br, + OPERAND_bt2, + OPERAND_bs2, + OPERAND_br2, + OPERAND_bt4, + OPERAND_bs4, + OPERAND_br4, + OPERAND_bt8, + OPERAND_bs8, + OPERAND_br8, + OPERAND_bt16, + OPERAND_bs16, + OPERAND_br16, + OPERAND_brall, + OPERAND_tp7, + OPERAND_xt_wbr15_label, + OPERAND_xt_wbr18_label, + OPERAND_opnd_ivp_sem_vec_alu_vr, + OPERAND_opnd_ivp_sem_vec_alu_vt, + OPERAND_opnd_ivp_sem_vec_alu_vs, + OPERAND_opnd_ivp_sem_vec_alu_vbr, + OPERAND_opnd_ivp_sem_multiply_vr, + OPERAND_opnd_ivp_sem_multiply_vs, + OPERAND_opnd_ivp_sem_multiply_wvt, + OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr, + OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbs, + OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt, + OPERAND_opnd_ivp_sem_vec_alu_vbt, + OPERAND_opnd_ivp_sem_vec_histogram_arr, + OPERAND_opnd_ivp_sem_vec_histogram_vr, + OPERAND_opnd_ivp_sem_vec_histogram_vs, + OPERAND_opnd_ivp_sem_vec_histogram_vt, + OPERAND_opnd_ivp_sem_vec_histogram_vbr, + OPERAND_opnd_ivp_sem_vec_histogram_vbs, + OPERAND_opnd_ivp_sem_divide_lane_ctrl, + OPERAND_opnd_ivp_sem_divide_vr, + OPERAND_opnd_ivp_sem_divide_vt, + OPERAND_opnd_ivp_sem_divide_vu, + OPERAND_opnd_ivp_sem_divide_vs, + OPERAND_opnd_ivp_sem_vec_select_slct, + OPERAND_opnd_ivp_sem_vec_select_vr, + OPERAND_opnd_ivp_sem_vec_select_vs, + OPERAND_opnd_ivp_sem_vec_select_vt, + OPERAND_opnd_ivp_sem_vec_select_vu, + OPERAND_opnd_ivp_sem_vec_select_slct_h, + OPERAND_opnd_ivp_sem_vec_select_sr, + OPERAND_opnd_ivp_sem_vec_select_vbr, + OPERAND_opnd_ivp_sem_vec_alu_i_imm3, + OPERAND_opnd_ivp_sem_vec_rep_i32, + OPERAND_opnd_ivp_sem_vec_rep_vr, + OPERAND_opnd_ivp_sem_vec_rep_i, + OPERAND_opnd_ivp_sem_ld_st_uul, + OPERAND_opnd_ivp_sem_ld_st_vrul, + OPERAND_opnd_ivp_sem_ld_st_vrul2, + OPERAND_opnd_ivp_sem_ld_st_i_bimm6, + OPERAND_opnd_ivp_sem_ld_st_i_bimm4, + OPERAND_opnd_ivp_sem_ld_st_vbr, + OPERAND_opnd_ivp_sem_ld_st_i_bimm6b2n, + OPERAND_opnd_ivp_sem_ld_st_i_bimm4b2n, + OPERAND_opnd_ivp_sem_ld_st_i_bimm6bn_2, + OPERAND_opnd_ivp_sem_ld_st_i_bimm4bn_2, + OPERAND_opnd_ivp_sem_ld_st_i_bimm6bn, + OPERAND_opnd_ivp_sem_ld_st_i_bimm4bn, + OPERAND_opnd_ivp_sem_ld_st_i_bimm6x1, + OPERAND_opnd_ivp_sem_ld_st_vr, + OPERAND_opnd_ivp_sem_ld_st_i_bimm4x1, + OPERAND_opnd_ivp_sem_ld_st_i_bimm8x4, + OPERAND_opnd_ivp_sem_ld_st_i_bimm4x4, + OPERAND_opnd_ivp_sem_ld_st_i_bimm6x2, + OPERAND_opnd_ivp_sem_ld_st_i_bimm4x2, + OPERAND_opnd_ivp_sem_ld_st_vrr, + OPERAND_opnd_ivp_sem_ld_st_i_bimm6x4, + OPERAND_bbe_ltrx2nimm, + OPERAND_bbe_ltrxn_2imm, + OPERAND_bbe_ltrxnimm, + OPERAND_opnd_ivp_sem_ld_st_i_bimm8, + OPERAND_opnd_ivp_sem_ld_st_vbre, + OPERAND_opnd_ivp_sem_ld_st_i_bimmh8, + OPERAND_opnd_ivp_sem_ld_st_i_bimmh4, + OPERAND_opnd_ivp_sem_ld_st_i_bimmh6, + OPERAND_opnd_ivp_sem_ld_st_i_bimmb8, + OPERAND_opnd_ivp_sem_ld_st_i_bimmb4, + OPERAND_opnd_ivp_sem_ld_st_i_bimmb6, + OPERAND_opnd_ivp_sem_ld_st_valignr, + OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr, + OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs, + OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt, + OPERAND_opnd_ivp_sem_vec_mov_vt, + OPERAND_opnd_ivp_sem_vec_mov_wvr, + OPERAND_opnd_ivp_sem_vec_mov_arr, + OPERAND_opnd_ivp_sem_vec_mov_i_IMM_movint, + OPERAND_opnd_ivp_sem_vec_mov_immmovvi, + OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvr, + OPERAND_opnd_ivp_sem_multiply_arr, + OPERAND_opnd_ivp_sem_multiply_vp, + OPERAND_opnd_ivp_sem_multiply_vt, + OPERAND_opnd_ivp_sem_multiply_vbr, + OPERAND_opnd_ivp_sem_vec_shift_vr, + OPERAND_opnd_ivp_sem_vec_shift_vt, + OPERAND_opnd_ivp_sem_wvec_pack_vt, + OPERAND_opnd_ivp_sem_wvec_pack_wvr, + OPERAND_opnd_ivp_sem_wvec_pack_arr, + OPERAND_opnd_ivp_sem_vec_reduce_vr, + OPERAND_opnd_ivp_sem_vec_reduce_vt, + OPERAND_opnd_ivp_sem_vec_reduce_vbr, + OPERAND_opnd_ivp_sem_vec_reduce_vbt, + OPERAND_opnd_ivp_sem_vec_rep_i8, + OPERAND_opnd_ivp_sem_vec_rep_vt, + OPERAND_saimm4, + OPERAND_saimm6_31, + OPERAND_saimm5, + OPERAND_opnd_ivp_sem_vec_shift_vs, + OPERAND_opnd_ivp_sem_ld_st_uus, + OPERAND_opnd_ivp_sem_vec_select_isel, + OPERAND_opnd_ivp_sem_vec_select_ishfl, + OPERAND_opnd_ivp_sem_sqz_vbr, + OPERAND_opnd_ivp_sem_sqz_vt, + OPERAND_opnd_ivp_sem_unpack_wvec_mov_vt, + OPERAND_opnd_ivp_sem_vec_scatter_gather_ars, + OPERAND_opnd_ivp_sem_vec_scatter_gather_gt, + OPERAND_opnd_ivp_sem_vec_scatter_gather_vs, + OPERAND_opnd_ivp_sem_vec_scatter_gather_vbr, + OPERAND_opnd_ivp_sem_vec_scatter_gather_gs, + OPERAND_opnd_ivp_sem_vec_scatter_gather_vt, + OPERAND_opnd_ivp_sem_vec_scatter_gather_vr, + OPERAND_opnd_ivp_sem_vbool_alu_ltr_art, + OPERAND_imm1_2N, + OPERAND_opnd_ivp_sem_multiply_vq, + OPERAND_opnd_ivp_sem_vec_rep_arr, + OPERAND_bbe_selimm_S0, + OPERAND_opnd_ivp_sem_vec_specialized_seli_vr, + OPERAND_opnd_ivp_sem_vec_specialized_seli_vs, + OPERAND_opnd_ivp_sem_vec_specialized_seli_vt, + OPERAND_bbe_selimm_S2, + OPERAND_bbe_selimm_S4, + OPERAND_bbe_shflimm_S0, + OPERAND_bbe_shflimm_S2, + OPERAND_bbe_shflimm_S4, + OPERAND_opnd_MTK_AndPOPC_c, + OPERAND_opnd_MTK_AndPOPC_inB, + OPERAND_opnd_MTK_AndPOPC_inA, + OPERAND_opnd_MTK_AndPOPC_oData, + OPERAND_opnd_iq_tie2apb_inq0_pop_qdata, + OPERAND_opnd_iq_tie2apb_inq0_is_ready_is_ready, + OPERAND_opnd_iq_tie2apb_inq0_nonblocking_peek_success, + OPERAND_opnd_iq_tie2apb_inq0_nonblocking_peek_qdata, + OPERAND_opnd_iq_tie2apb_inq0_nonblocking_pop_success, + OPERAND_opnd_iq_tie2apb_inq0_nonblocking_pop_qdata, + OPERAND_opnd_iq_tie2apb_inq0_blocking_peek_qdata, + OPERAND_opnd_oq_tie2apb_outq0_push_read_qaddr, + OPERAND_opnd_oq_tie2apb_outq0_push_read_qdata, + OPERAND_opnd_oq_tie2apb_outq0_push_write_qaddr, + OPERAND_opnd_oq_tie2apb_outq0_push_write_qdata, + OPERAND_opnd_oq_tie2apb_outq0_is_ready_is_ready, + OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_read_success, + OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_read_qaddr, + OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_read_qdata, + OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_write_success, + OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_write_qaddr, + OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_write_qdata, + OPERAND_t, + OPERAND_bbi4, + OPERAND_imm12, + OPERAND_imm8, + OPERAND_imm12b, + OPERAND_m, + OPERAND_n, + OPERAND_offset, + OPERAND_op0, + OPERAND_op1, + OPERAND_op2, + OPERAND_r, + OPERAND_sa4, + OPERAND_sae4, + OPERAND_sal, + OPERAND_sas4, + OPERAND_sr, + OPERAND_st, + OPERAND_thi3, + OPERAND_imm4, + OPERAND_mn, + OPERAND_i, + OPERAND_imm6lo, + OPERAND_imm6hi, + OPERAND_imm7lo, + OPERAND_imm7hi, + OPERAND_z, + OPERAND_imm6, + OPERAND_imm7, + OPERAND_t2, + OPERAND_s2, + OPERAND_r2, + OPERAND_t4, + OPERAND_s4, + OPERAND_r4, + OPERAND_t8, + OPERAND_s8, + OPERAND_r8, + OPERAND_xt_wbr15_imm, + OPERAND_xt_wbr18_imm, + OPERAND_fld_F0_S0_LdSt_11_4, + OPERAND_fld_F0_S0_LdSt_11_8, + OPERAND_fld_F0_S0_LdSt_11_9, + OPERAND_fld_F0_S0_LdSt_12_0, + OPERAND_fld_F0_S0_LdSt_12_11, + OPERAND_fld_F0_S0_LdSt_12_12, + OPERAND_fld_F0_S0_LdSt_12_2, + OPERAND_fld_F0_S0_LdSt_12_4, + OPERAND_fld_F0_S0_LdSt_12_8, + OPERAND_fld_F0_S0_LdSt_13_9, + OPERAND_fld_F0_S0_LdSt_15_15, + OPERAND_fld_F0_S0_LdSt_33_11, + OPERAND_fld_F0_S0_LdSt_33_12, + OPERAND_fld_F0_S0_LdSt_33_13, + OPERAND_fld_F0_S0_LdSt_33_14, + OPERAND_fld_F0_S0_LdSt_33_15, + OPERAND_fld_F0_S0_LdSt_33_16, + OPERAND_fld_F0_S0_LdSt_33_17, + OPERAND_fld_F0_S0_LdSt_33_18, + OPERAND_fld_F0_S0_LdSt_33_19, + OPERAND_fld_F0_S0_LdSt_33_20, + OPERAND_fld_F0_S0_LdSt_33_27, + OPERAND_fld_F0_S0_LdSt_33_9, + OPERAND_fld_F0_S0_LdSt_3_0, + OPERAND_fld_F0_S0_LdSt_7_4, + OPERAND_fld_F0_S0_LdSt_7_5, + OPERAND_fld_F0_S0_LdSt_7_6, + OPERAND_fld_F0_S0_LdSt_7_7, + OPERAND_fld_F0_S0_LdSt_8_0, + OPERAND_fld_F0_S0_LdSt_8_4, + OPERAND_fld_F0_S0_LdSt_8_8, + OPERAND_fld_bbe_shflimm_S0, + OPERAND_fld_ivp_sem_ld_st_i_bimm4, + OPERAND_fld_ivp_sem_ld_st_i_bimm4b2n, + OPERAND_fld_ivp_sem_ld_st_i_bimm4bn, + OPERAND_fld_ivp_sem_ld_st_i_bimm4bn_2, + OPERAND_fld_ivp_sem_ld_st_i_bimm4x1, + OPERAND_fld_ivp_sem_ld_st_i_bimm4x2, + OPERAND_fld_ivp_sem_ld_st_i_bimm4x4, + OPERAND_fld_ivp_sem_ld_st_i_bimm6, + OPERAND_fld_ivp_sem_ld_st_i_bimm6b2n, + OPERAND_fld_ivp_sem_ld_st_i_bimm6bn, + OPERAND_fld_ivp_sem_ld_st_i_bimm6bn_2, + OPERAND_fld_ivp_sem_ld_st_i_bimm6x1, + OPERAND_fld_ivp_sem_ld_st_i_bimm6x2, + OPERAND_fld_ivp_sem_ld_st_i_bimm6x4, + OPERAND_fld_ivp_sem_ld_st_i_bimm8, + OPERAND_fld_ivp_sem_ld_st_i_bimm8x4, + OPERAND_fld_ivp_sem_ld_st_i_bimmb4, + OPERAND_fld_ivp_sem_ld_st_i_bimmb6, + OPERAND_fld_ivp_sem_ld_st_i_bimmb8, + OPERAND_fld_ivp_sem_ld_st_i_bimmh4, + OPERAND_fld_ivp_sem_ld_st_i_bimmh6, + OPERAND_fld_ivp_sem_ld_st_i_bimmh8, + OPERAND_fld_ivp_sem_ld_st_uul, + OPERAND_fld_ivp_sem_ld_st_uus, + OPERAND_fld_ivp_sem_ld_st_valignr, + OPERAND_fld_ivp_sem_ld_st_vbr, + OPERAND_fld_ivp_sem_ld_st_vbre, + OPERAND_fld_ivp_sem_ld_st_vr, + OPERAND_fld_ivp_sem_ld_st_vrr, + OPERAND_fld_ivp_sem_ld_st_vrul, + OPERAND_fld_ivp_sem_vec_alu_arr, + OPERAND_fld_ivp_sem_vec_alu_vbr, + OPERAND_fld_ivp_sem_vec_alu_vr, + OPERAND_fld_ivp_sem_vec_alu_vt, + OPERAND_fld_ivp_sem_vec_rep_i, + OPERAND_fld_ivp_sem_vec_rep_i32, + OPERAND_fld_ivp_sem_vec_rep_i8, + OPERAND_fld_ivp_sem_vec_rep_vr, + OPERAND_fld_ivp_sem_vec_rep_vt, + OPERAND_fld_ivp_sem_vec_scatter_gather_ars, + OPERAND_fld_ivp_sem_vec_scatter_gather_gt, + OPERAND_fld_ivp_sem_vec_scatter_gather_vbr, + OPERAND_fld_ivp_sem_vec_scatter_gather_vs, + OPERAND_fld_ivp_sem_vec_shift_vr, + OPERAND_fld_ivp_sem_vec_shift_vt, + OPERAND_fld_ivp_sem_vec_specialized_seli_vr, + OPERAND_fld_ivp_sem_vec_specialized_seli_vt, + OPERAND_fld_saimm4, + OPERAND_fld_saimm5, + OPERAND_fld_F0_S1_Ld_12_11, + OPERAND_fld_F0_S1_Ld_12_12, + OPERAND_fld_F0_S1_Ld_12_4, + OPERAND_fld_F0_S1_Ld_15_10, + OPERAND_fld_F0_S1_Ld_15_13, + OPERAND_fld_F0_S1_Ld_15_14, + OPERAND_fld_F0_S1_Ld_15_15, + OPERAND_fld_F0_S1_Ld_15_2, + OPERAND_fld_F0_S1_Ld_15_4, + OPERAND_fld_F0_S1_Ld_15_8, + OPERAND_fld_F0_S1_Ld_24_0, + OPERAND_fld_F0_S1_Ld_24_11, + OPERAND_fld_F0_S1_Ld_24_12, + OPERAND_fld_F0_S1_Ld_24_13, + OPERAND_fld_F0_S1_Ld_24_14, + OPERAND_fld_F0_S1_Ld_24_16, + OPERAND_fld_F0_S1_Ld_24_17, + OPERAND_fld_F0_S1_Ld_24_18, + OPERAND_fld_F0_S1_Ld_24_8, + OPERAND_fld_F0_S1_Ld_3_0, + OPERAND_fld_F0_S1_Ld_3_2, + OPERAND_fld_F0_S1_Ld_7_0, + OPERAND_fld_F0_S1_Ld_7_2, + OPERAND_fld_F0_S1_Ld_7_3, + OPERAND_fld_F0_S1_Ld_7_4, + OPERAND_fld_F0_S1_Ld_7_5, + OPERAND_fld_F0_S1_Ld_7_6, + OPERAND_fld_F0_S1_Ld_7_7, + OPERAND_fld_bbe_ltrx2nimm, + OPERAND_fld_bbe_ltrxn_2imm, + OPERAND_fld_bbe_ltrxnimm, + OPERAND_fld_imm1_2N, + OPERAND_fld_ivp_sem_sqz_vbr, + OPERAND_fld_ivp_sem_sqz_vt, + OPERAND_fld_ivp_sem_vbool_alu_ltr_art, + OPERAND_fld_ivp_sem_vbool_alu_ltr_vbr, + OPERAND_fld_ivp_sem_vbool_alu_ltr_vbs, + OPERAND_fld_ivp_sem_vbool_alu_ltr_vbt, + OPERAND_fld_ivp_sem_vec_mov_arr, + OPERAND_fld_ivp_sem_vec_mov_i_IMM_movint, + OPERAND_fld_ivp_sem_vec_mov_i_imm4, + OPERAND_fld_ivp_sem_vec_mov_immmovvi, + OPERAND_fld_ivp_sem_vec_mov_vbr, + OPERAND_fld_ivp_sem_vec_mov_vt, + OPERAND_fld_ivp_sem_vec_mov_wvr, + OPERAND_fld_ivp_sem_vec_scatter_gather_gs, + OPERAND_fld_ivp_sem_vec_scatter_gather_vt, + OPERAND_fld_ivp_sem_wvec_pack_arr, + OPERAND_fld_ivp_sem_wvec_pack_vt, + OPERAND_fld_ivp_sem_wvec_pack_wvr, + OPERAND_fld_F0_S2_Mul_11_8, + OPERAND_fld_F0_S2_Mul_13_12, + OPERAND_fld_F0_S2_Mul_18_12, + OPERAND_fld_F0_S2_Mul_18_14, + OPERAND_fld_F0_S2_Mul_18_9, + OPERAND_fld_F0_S2_Mul_1_0, + OPERAND_fld_F0_S2_Mul_26_12, + OPERAND_fld_F0_S2_Mul_26_13, + OPERAND_fld_F0_S2_Mul_26_14, + OPERAND_fld_F0_S2_Mul_26_2, + OPERAND_fld_F0_S2_Mul_26_20, + OPERAND_fld_F0_S2_Mul_26_21, + OPERAND_fld_F0_S2_Mul_3_0, + OPERAND_fld_F0_S2_Mul_3_3, + OPERAND_fld_F0_S2_Mul_4_4, + OPERAND_fld_F0_S2_Mul_7_4, + OPERAND_fld_F0_S2_Mul_7_5, + OPERAND_fld_ivp_sem_multiply_arr, + OPERAND_fld_ivp_sem_multiply_vp, + OPERAND_fld_ivp_sem_multiply_vr, + OPERAND_fld_ivp_sem_multiply_vs, + OPERAND_fld_ivp_sem_multiply_wvt, + OPERAND_fld_ivp_sem_unpack_wvec_mov_vr, + OPERAND_fld_ivp_sem_unpack_wvec_mov_vs, + OPERAND_fld_ivp_sem_unpack_wvec_mov_wvr, + OPERAND_fld_ivp_sem_unpack_wvec_mov_wvt, + OPERAND_fld_ivp_sem_vec_alu_vbt, + OPERAND_fld_ivp_sem_vec_alu_vs, + OPERAND_fld_F0_S3_ALU_0_0, + OPERAND_fld_F0_S3_ALU_14_10, + OPERAND_fld_F0_S3_ALU_14_11, + OPERAND_fld_F0_S3_ALU_14_13, + OPERAND_fld_F0_S3_ALU_14_14, + OPERAND_fld_F0_S3_ALU_14_8, + OPERAND_fld_F0_S3_ALU_24_10, + OPERAND_fld_F0_S3_ALU_24_13, + OPERAND_fld_F0_S3_ALU_24_19, + OPERAND_fld_F0_S3_ALU_24_20, + OPERAND_fld_F0_S3_ALU_33_10, + OPERAND_fld_F0_S3_ALU_33_13, + OPERAND_fld_F0_S3_ALU_33_18, + OPERAND_fld_F0_S3_ALU_33_19, + OPERAND_fld_F0_S3_ALU_33_20, + OPERAND_fld_F0_S3_ALU_33_25, + OPERAND_fld_F0_S3_ALU_33_26, + OPERAND_fld_F0_S3_ALU_33_27, + OPERAND_fld_F0_S3_ALU_33_28, + OPERAND_fld_F0_S3_ALU_33_9, + OPERAND_fld_F0_S3_ALU_3_0, + OPERAND_fld_F0_S3_ALU_3_1, + OPERAND_fld_F0_S3_ALU_3_2, + OPERAND_fld_F0_S3_ALU_3_3, + OPERAND_fld_F0_S3_ALU_7_3, + OPERAND_fld_F0_S3_ALU_7_4, + OPERAND_fld_F0_S3_ALU_7_7, + OPERAND_fld_F0_S3_ALU_8_0, + OPERAND_fld_F0_S3_ALU_8_8, + OPERAND_fld_F0_S3_ALU_9_0, + OPERAND_fld_F0_S3_ALU_9_7, + OPERAND_fld_F0_S3_ALU_9_8, + OPERAND_fld_fp_sem_hp_cnv_i_imm4, + OPERAND_fld_fp_sem_hp_cnv_vbr, + OPERAND_fld_fp_sem_hp_cnv_vr, + OPERAND_fld_fp_sem_hp_cnv_vs, + OPERAND_fld_fp_sem_hp_cnv_vt, + OPERAND_fld_ivp_sem_sp32cvt_i_imm5, + OPERAND_fld_ivp_sem_sp32cvt_vbr, + OPERAND_fld_ivp_sem_sp32cvt_vr, + OPERAND_fld_ivp_sem_sp32cvt_vt, + OPERAND_fld_ivp_sem_spmisc_vbr, + OPERAND_fld_ivp_sem_spmisc_vr, + OPERAND_fld_ivp_sem_spmisc_vs, + OPERAND_fld_ivp_sem_spmisc_vsM, + OPERAND_fld_ivp_sem_spmisc_vt, + OPERAND_fld_ivp_sem_vec_alu_i_imm3, + OPERAND_fld_ivp_sem_vec_reduce_vbr, + OPERAND_fld_ivp_sem_vec_reduce_vbt, + OPERAND_fld_ivp_sem_vec_reduce_vr, + OPERAND_fld_ivp_sem_vec_reduce_vt, + OPERAND_fld_ivp_sem_vec_rep_arr, + OPERAND_fld_ivp_sem_vec_select_isel, + OPERAND_fld_ivp_sem_vec_select_ishfl, + OPERAND_fld_ivp_sem_vec_select_slct, + OPERAND_fld_ivp_sem_vec_select_slct_h, + OPERAND_fld_ivp_sem_vec_select_sr, + OPERAND_fld_ivp_sem_vec_select_vbr, + OPERAND_fld_ivp_sem_vec_select_vr, + OPERAND_fld_ivp_sem_vec_select_vs, + OPERAND_fld_ivp_sem_vec_select_vt, + OPERAND_fld_ivp_sem_vec_select_vu, + OPERAND_fld_ivp_sem_vec_shift_vs, + OPERAND_fld_saimm6_31, + OPERAND_fld_F1_S0_LdStALU_12_0, + OPERAND_fld_F1_S0_LdStALU_12_12, + OPERAND_fld_F1_S0_LdStALU_12_2, + OPERAND_fld_F1_S0_LdStALU_12_4, + OPERAND_fld_F1_S0_LdStALU_12_8, + OPERAND_fld_F1_S0_LdStALU_14_10, + OPERAND_fld_F1_S0_LdStALU_14_12, + OPERAND_fld_F1_S0_LdStALU_14_14, + OPERAND_fld_F1_S0_LdStALU_15_15, + OPERAND_fld_F1_S0_LdStALU_30_12, + OPERAND_fld_F1_S0_LdStALU_30_13, + OPERAND_fld_F1_S0_LdStALU_30_14, + OPERAND_fld_F1_S0_LdStALU_30_15, + OPERAND_fld_F1_S0_LdStALU_30_16, + OPERAND_fld_F1_S0_LdStALU_30_17, + OPERAND_fld_F1_S0_LdStALU_30_18, + OPERAND_fld_F1_S0_LdStALU_30_19, + OPERAND_fld_F1_S0_LdStALU_30_20, + OPERAND_fld_F1_S0_LdStALU_30_6, + OPERAND_fld_F1_S0_LdStALU_30_8, + OPERAND_fld_F1_S0_LdStALU_30_9, + OPERAND_fld_F1_S0_LdStALU_3_0, + OPERAND_fld_F1_S0_LdStALU_5_0, + OPERAND_fld_F1_S0_LdStALU_5_4, + OPERAND_fld_F1_S0_LdStALU_7_4, + OPERAND_fld_F1_S0_LdStALU_7_5, + OPERAND_fld_F1_S0_LdStALU_7_7, + OPERAND_fld_F1_S0_LdStALU_9_9, + OPERAND_fld_bbe_selimm_S0, + OPERAND_fld_ivp_sem_vec_scatter_gather_vr, + OPERAND_fld_ivp_sem_vec_specialized_seli_vs, + OPERAND_fld_F1_S1_Ld_12_10, + OPERAND_fld_F1_S1_Ld_12_11, + OPERAND_fld_F1_S1_Ld_12_12, + OPERAND_fld_F1_S1_Ld_12_4, + OPERAND_fld_F1_S1_Ld_12_9, + OPERAND_fld_F1_S1_Ld_15_10, + OPERAND_fld_F1_S1_Ld_15_13, + OPERAND_fld_F1_S1_Ld_15_14, + OPERAND_fld_F1_S1_Ld_15_15, + OPERAND_fld_F1_S1_Ld_15_2, + OPERAND_fld_F1_S1_Ld_15_4, + OPERAND_fld_F1_S1_Ld_15_8, + OPERAND_fld_F1_S1_Ld_1_0, + OPERAND_fld_F1_S1_Ld_26_11, + OPERAND_fld_F1_S1_Ld_26_12, + OPERAND_fld_F1_S1_Ld_26_13, + OPERAND_fld_F1_S1_Ld_26_16, + OPERAND_fld_F1_S1_Ld_26_18, + OPERAND_fld_F1_S1_Ld_26_2, + OPERAND_fld_F1_S1_Ld_3_0, + OPERAND_fld_F1_S1_Ld_3_2, + OPERAND_fld_F1_S1_Ld_7_0, + OPERAND_fld_F1_S1_Ld_7_2, + OPERAND_fld_F1_S1_Ld_7_3, + OPERAND_fld_F1_S1_Ld_7_4, + OPERAND_fld_F1_S1_Ld_7_5, + OPERAND_fld_F1_S1_Ld_7_6, + OPERAND_fld_F1_S1_Ld_7_7, + OPERAND_fld_F1_S2_Mul_13_10, + OPERAND_fld_F1_S2_Mul_13_2, + OPERAND_fld_F1_S2_Mul_13_5, + OPERAND_fld_F1_S2_Mul_14_10, + OPERAND_fld_F1_S2_Mul_28_12, + OPERAND_fld_F1_S2_Mul_28_15, + OPERAND_fld_F1_S2_Mul_28_16, + OPERAND_fld_F1_S2_Mul_28_18, + OPERAND_fld_F1_S2_Mul_28_20, + OPERAND_fld_F1_S2_Mul_28_4, + OPERAND_fld_F1_S2_Mul_28_5, + OPERAND_fld_F1_S2_Mul_3_0, + OPERAND_fld_F1_S2_Mul_3_2, + OPERAND_fld_F1_S2_Mul_3_3, + OPERAND_fld_F1_S2_Mul_4_4, + OPERAND_fld_F1_S2_Mul_9_5, + OPERAND_fld_F1_S2_Mul_9_6, + OPERAND_fld_bbe_selimm_S2, + OPERAND_fld_bbe_shflimm_S2, + OPERAND_fld_fp_sem_hp_fma_vbr, + OPERAND_fld_fp_sem_hp_fma_vr, + OPERAND_fld_fp_sem_hp_fma_vs, + OPERAND_fld_fp_sem_hp_fma_vt, + OPERAND_fld_ivp_sem_multiply_vt, + OPERAND_fld_ivp_sem_spfma_vbr, + OPERAND_fld_ivp_sem_spfma_vr, + OPERAND_fld_ivp_sem_spfma_vs, + OPERAND_fld_ivp_sem_spfma_vt, + OPERAND_fld_ivp_sem_unpack_wvec_mov_vt, + OPERAND_fld_F1_S3_ALU_0_0, + OPERAND_fld_F1_S3_ALU_14_10, + OPERAND_fld_F1_S3_ALU_14_13, + OPERAND_fld_F1_S3_ALU_14_14, + OPERAND_fld_F1_S3_ALU_14_8, + OPERAND_fld_F1_S3_ALU_19_14, + OPERAND_fld_F1_S3_ALU_19_15, + OPERAND_fld_F1_S3_ALU_19_19, + OPERAND_fld_F1_S3_ALU_19_4, + OPERAND_fld_F1_S3_ALU_19_7, + OPERAND_fld_F1_S3_ALU_30_15, + OPERAND_fld_F1_S3_ALU_30_17, + OPERAND_fld_F1_S3_ALU_30_19, + OPERAND_fld_F1_S3_ALU_30_20, + OPERAND_fld_F1_S3_ALU_30_22, + OPERAND_fld_F1_S3_ALU_30_23, + OPERAND_fld_F1_S3_ALU_30_6, + OPERAND_fld_F1_S3_ALU_30_8, + OPERAND_fld_F1_S3_ALU_3_0, + OPERAND_fld_F1_S3_ALU_3_1, + OPERAND_fld_F1_S3_ALU_3_2, + OPERAND_fld_F1_S3_ALU_3_3, + OPERAND_fld_F1_S3_ALU_5_0, + OPERAND_fld_F1_S3_ALU_9_0, + OPERAND_fld_F1_S3_ALU_9_1, + OPERAND_fld_F1_S3_ALU_9_2, + OPERAND_fld_F1_S3_ALU_9_3, + OPERAND_fld_F1_S3_ALU_9_7, + OPERAND_fld_F1_S3_ALU_9_8, + OPERAND_fld_F1_S3_ALU_9_9, + OPERAND_fld_ivp_sem_vec_histogram_arr, + OPERAND_fld_ivp_sem_vec_histogram_vr, + OPERAND_fld_ivp_sem_vec_histogram_vs, + OPERAND_fld_ivp_sem_vec_histogram_vt, + OPERAND_fld_F2_S0_LdSt_12_0, + OPERAND_fld_F2_S0_LdSt_12_10, + OPERAND_fld_F2_S0_LdSt_12_2, + OPERAND_fld_F2_S0_LdSt_12_4, + OPERAND_fld_F2_S0_LdSt_12_8, + OPERAND_fld_F2_S0_LdSt_15_15, + OPERAND_fld_F2_S0_LdSt_28_11, + OPERAND_fld_F2_S0_LdSt_28_12, + OPERAND_fld_F2_S0_LdSt_28_13, + OPERAND_fld_F2_S0_LdSt_28_14, + OPERAND_fld_F2_S0_LdSt_28_15, + OPERAND_fld_F2_S0_LdSt_28_16, + OPERAND_fld_F2_S0_LdSt_28_17, + OPERAND_fld_F2_S0_LdSt_28_18, + OPERAND_fld_F2_S0_LdSt_28_20, + OPERAND_fld_F2_S0_LdSt_28_4, + OPERAND_fld_F2_S0_LdSt_28_8, + OPERAND_fld_F2_S0_LdSt_3_0, + OPERAND_fld_F2_S0_LdSt_3_2, + OPERAND_fld_F2_S0_LdSt_7_2, + OPERAND_fld_F2_S0_LdSt_7_4, + OPERAND_fld_F2_S1_Ld_12_10, + OPERAND_fld_F2_S1_Ld_12_11, + OPERAND_fld_F2_S1_Ld_12_4, + OPERAND_fld_F2_S1_Ld_12_9, + OPERAND_fld_F2_S1_Ld_15_10, + OPERAND_fld_F2_S1_Ld_15_13, + OPERAND_fld_F2_S1_Ld_15_14, + OPERAND_fld_F2_S1_Ld_15_15, + OPERAND_fld_F2_S1_Ld_15_2, + OPERAND_fld_F2_S1_Ld_15_4, + OPERAND_fld_F2_S1_Ld_15_8, + OPERAND_fld_F2_S1_Ld_1_0, + OPERAND_fld_F2_S1_Ld_26_11, + OPERAND_fld_F2_S1_Ld_26_12, + OPERAND_fld_F2_S1_Ld_26_13, + OPERAND_fld_F2_S1_Ld_26_16, + OPERAND_fld_F2_S1_Ld_26_18, + OPERAND_fld_F2_S1_Ld_26_2, + OPERAND_fld_F2_S1_Ld_3_0, + OPERAND_fld_F2_S1_Ld_3_2, + OPERAND_fld_F2_S1_Ld_7_0, + OPERAND_fld_F2_S1_Ld_7_2, + OPERAND_fld_F2_S1_Ld_7_3, + OPERAND_fld_F2_S1_Ld_7_4, + OPERAND_fld_F2_S1_Ld_7_6, + OPERAND_fld_F2_S1_Ld_7_7, + OPERAND_fld_F2_S2_Mul_14_10, + OPERAND_fld_F2_S2_Mul_14_11, + OPERAND_fld_F2_S2_Mul_14_5, + OPERAND_fld_F2_S2_Mul_19_10, + OPERAND_fld_F2_S2_Mul_19_15, + OPERAND_fld_F2_S2_Mul_19_7, + OPERAND_fld_F2_S2_Mul_30_10, + OPERAND_fld_F2_S2_Mul_30_12, + OPERAND_fld_F2_S2_Mul_30_15, + OPERAND_fld_F2_S2_Mul_30_18, + OPERAND_fld_F2_S2_Mul_30_19, + OPERAND_fld_F2_S2_Mul_30_20, + OPERAND_fld_F2_S2_Mul_30_21, + OPERAND_fld_F2_S2_Mul_30_6, + OPERAND_fld_F2_S2_Mul_3_0, + OPERAND_fld_F2_S2_Mul_4_0, + OPERAND_fld_F2_S2_Mul_4_3, + OPERAND_fld_F2_S2_Mul_5_0, + OPERAND_fld_ivp_sem_divide_lane_ctrl, + OPERAND_fld_ivp_sem_divide_vr, + OPERAND_fld_ivp_sem_divide_vs, + OPERAND_fld_ivp_sem_divide_vt, + OPERAND_fld_ivp_sem_divide_vu, + OPERAND_fld_ivp_sem_multiply_vbr, + OPERAND_fld_F2_S3_ALU_0_0, + OPERAND_fld_F2_S3_ALU_14_10, + OPERAND_fld_F2_S3_ALU_14_13, + OPERAND_fld_F2_S3_ALU_14_14, + OPERAND_fld_F2_S3_ALU_14_8, + OPERAND_fld_F2_S3_ALU_19_14, + OPERAND_fld_F2_S3_ALU_19_15, + OPERAND_fld_F2_S3_ALU_19_19, + OPERAND_fld_F2_S3_ALU_19_4, + OPERAND_fld_F2_S3_ALU_19_7, + OPERAND_fld_F2_S3_ALU_30_15, + OPERAND_fld_F2_S3_ALU_30_18, + OPERAND_fld_F2_S3_ALU_30_19, + OPERAND_fld_F2_S3_ALU_30_20, + OPERAND_fld_F2_S3_ALU_30_22, + OPERAND_fld_F2_S3_ALU_30_23, + OPERAND_fld_F2_S3_ALU_30_6, + OPERAND_fld_F2_S3_ALU_30_8, + OPERAND_fld_F2_S3_ALU_3_0, + OPERAND_fld_F2_S3_ALU_3_1, + OPERAND_fld_F2_S3_ALU_3_2, + OPERAND_fld_F2_S3_ALU_3_3, + OPERAND_fld_F2_S3_ALU_5_0, + OPERAND_fld_F2_S3_ALU_9_0, + OPERAND_fld_F2_S3_ALU_9_1, + OPERAND_fld_F2_S3_ALU_9_2, + OPERAND_fld_F2_S3_ALU_9_3, + OPERAND_fld_F2_S3_ALU_9_7, + OPERAND_fld_F2_S3_ALU_9_8, + OPERAND_fld_F2_S3_ALU_9_9, + OPERAND_fld_F3_S0_LdSt_0_0, + OPERAND_fld_F3_S0_LdSt_12_0, + OPERAND_fld_F3_S0_LdSt_12_11, + OPERAND_fld_F3_S0_LdSt_12_12, + OPERAND_fld_F3_S0_LdSt_12_4, + OPERAND_fld_F3_S0_LdSt_12_8, + OPERAND_fld_F3_S0_LdSt_13_9, + OPERAND_fld_F3_S0_LdSt_15_15, + OPERAND_fld_F3_S0_LdSt_25_1, + OPERAND_fld_F3_S0_LdSt_25_11, + OPERAND_fld_F3_S0_LdSt_25_12, + OPERAND_fld_F3_S0_LdSt_25_13, + OPERAND_fld_F3_S0_LdSt_25_14, + OPERAND_fld_F3_S0_LdSt_25_15, + OPERAND_fld_F3_S0_LdSt_25_16, + OPERAND_fld_F3_S0_LdSt_25_17, + OPERAND_fld_F3_S0_LdSt_25_18, + OPERAND_fld_F3_S0_LdSt_25_19, + OPERAND_fld_F3_S0_LdSt_25_20, + OPERAND_fld_F3_S0_LdSt_25_4, + OPERAND_fld_F3_S0_LdSt_25_8, + OPERAND_fld_F3_S0_LdSt_25_9, + OPERAND_fld_F3_S0_LdSt_3_0, + OPERAND_fld_F3_S0_LdSt_7_4, + OPERAND_fld_F3_S0_LdSt_7_5, + OPERAND_fld_F3_S0_LdSt_7_7, + OPERAND_fld_F3_S0_LdSt_8_0, + OPERAND_fld_F3_S1_Ld_12_11, + OPERAND_fld_F3_S1_Ld_12_2, + OPERAND_fld_F3_S1_Ld_12_4, + OPERAND_fld_F3_S1_Ld_12_8, + OPERAND_fld_F3_S1_Ld_21_0, + OPERAND_fld_F3_S1_Ld_21_10, + OPERAND_fld_F3_S1_Ld_21_11, + OPERAND_fld_F3_S1_Ld_21_12, + OPERAND_fld_F3_S1_Ld_21_13, + OPERAND_fld_F3_S1_Ld_21_15, + OPERAND_fld_F3_S1_Ld_21_16, + OPERAND_fld_F3_S1_Ld_21_17, + OPERAND_fld_F3_S1_Ld_21_8, + OPERAND_fld_F3_S1_Ld_21_9, + OPERAND_fld_F3_S1_Ld_3_0, + OPERAND_fld_F3_S1_Ld_3_2, + OPERAND_fld_F3_S1_Ld_4_0, + OPERAND_fld_F3_S1_Ld_4_3, + OPERAND_fld_F3_S1_Ld_4_4, + OPERAND_fld_F3_S1_Ld_7_0, + OPERAND_fld_F3_S1_Ld_7_2, + OPERAND_fld_F3_S1_Ld_7_4, + OPERAND_fld_F3_S1_Ld_7_7, + OPERAND_fld_F3_S2_Mul_11_8, + OPERAND_fld_F3_S2_Mul_13_12, + OPERAND_fld_F3_S2_Mul_13_7, + OPERAND_fld_F3_S2_Mul_21_0, + OPERAND_fld_F3_S2_Mul_21_12, + OPERAND_fld_F3_S2_Mul_21_13, + OPERAND_fld_F3_S2_Mul_21_14, + OPERAND_fld_F3_S2_Mul_21_15, + OPERAND_fld_F3_S2_Mul_21_16, + OPERAND_fld_F3_S2_Mul_3_0, + OPERAND_fld_F3_S2_Mul_3_3, + OPERAND_fld_F3_S2_Mul_4_0, + OPERAND_fld_F3_S2_Mul_7_4, + OPERAND_fld_F3_S2_Mul_7_5, + OPERAND_fld_F3_S3_ALU_13_9, + OPERAND_fld_F3_S3_ALU_18_12, + OPERAND_fld_F3_S3_ALU_18_13, + OPERAND_fld_F3_S3_ALU_18_14, + OPERAND_fld_F3_S3_ALU_18_18, + OPERAND_fld_F3_S3_ALU_18_3, + OPERAND_fld_F3_S3_ALU_18_7, + OPERAND_fld_F3_S3_ALU_18_8, + OPERAND_fld_F3_S3_ALU_28_12, + OPERAND_fld_F3_S3_ALU_28_13, + OPERAND_fld_F3_S3_ALU_28_14, + OPERAND_fld_F3_S3_ALU_28_18, + OPERAND_fld_F3_S3_ALU_28_19, + OPERAND_fld_F3_S3_ALU_28_20, + OPERAND_fld_F3_S3_ALU_28_21, + OPERAND_fld_F3_S3_ALU_28_22, + OPERAND_fld_F3_S3_ALU_28_25, + OPERAND_fld_F3_S3_ALU_28_4, + OPERAND_fld_F3_S3_ALU_28_8, + OPERAND_fld_F3_S3_ALU_28_9, + OPERAND_fld_F3_S3_ALU_3_0, + OPERAND_fld_F3_S3_ALU_3_2, + OPERAND_fld_F3_S3_ALU_3_3, + OPERAND_fld_F3_S3_ALU_7_3, + OPERAND_fld_F3_S3_ALU_7_6, + OPERAND_fld_F3_S3_ALU_7_7, + OPERAND_fld_F3_S3_ALU_8_0, + OPERAND_fld_ivp_sem_vec_histogram_vbr, + OPERAND_fld_ivp_sem_vec_histogram_vbs, + OPERAND_fld_F3_S4_ALU_14_10, + OPERAND_fld_F3_S4_ALU_23_0, + OPERAND_fld_F3_S4_ALU_23_15, + OPERAND_fld_F3_S4_ALU_23_18, + OPERAND_fld_F3_S4_ALU_23_20, + OPERAND_fld_F3_S4_ALU_9_5, + OPERAND_fld_F3_S4_ALU_9_6, + OPERAND_fld_bbe_selimm_S4, + OPERAND_fld_bbe_shflimm_S4, + OPERAND_fld_F4_S0_Ld_11_4, + OPERAND_fld_F4_S0_Ld_11_8, + OPERAND_fld_F4_S0_Ld_11_9, + OPERAND_fld_F4_S0_Ld_12_0, + OPERAND_fld_F4_S0_Ld_12_2, + OPERAND_fld_F4_S0_Ld_12_4, + OPERAND_fld_F4_S0_Ld_12_8, + OPERAND_fld_F4_S0_Ld_15_15, + OPERAND_fld_F4_S0_Ld_31_12, + OPERAND_fld_F4_S0_Ld_31_13, + OPERAND_fld_F4_S0_Ld_31_15, + OPERAND_fld_F4_S0_Ld_31_16, + OPERAND_fld_F4_S0_Ld_31_17, + OPERAND_fld_F4_S0_Ld_31_18, + OPERAND_fld_F4_S0_Ld_31_20, + OPERAND_fld_F4_S0_Ld_31_27, + OPERAND_fld_F4_S0_Ld_31_7, + OPERAND_fld_F4_S0_Ld_31_8, + OPERAND_fld_F4_S0_Ld_31_9, + OPERAND_fld_F4_S0_Ld_3_0, + OPERAND_fld_F4_S0_Ld_6_0, + OPERAND_fld_F4_S0_Ld_6_4, + OPERAND_fld_F4_S0_Ld_7_4, + OPERAND_fld_F4_S1_Ld_12_10, + OPERAND_fld_F4_S1_Ld_12_2, + OPERAND_fld_F4_S1_Ld_12_4, + OPERAND_fld_F4_S1_Ld_12_8, + OPERAND_fld_F4_S1_Ld_23_0, + OPERAND_fld_F4_S1_Ld_23_10, + OPERAND_fld_F4_S1_Ld_23_11, + OPERAND_fld_F4_S1_Ld_23_12, + OPERAND_fld_F4_S1_Ld_23_13, + OPERAND_fld_F4_S1_Ld_23_15, + OPERAND_fld_F4_S1_Ld_23_16, + OPERAND_fld_F4_S1_Ld_23_17, + OPERAND_fld_F4_S1_Ld_23_8, + OPERAND_fld_F4_S1_Ld_23_9, + OPERAND_fld_F4_S1_Ld_3_0, + OPERAND_fld_F4_S1_Ld_3_2, + OPERAND_fld_F4_S1_Ld_4_0, + OPERAND_fld_F4_S1_Ld_4_3, + OPERAND_fld_F4_S1_Ld_4_4, + OPERAND_fld_F4_S1_Ld_7_0, + OPERAND_fld_F4_S1_Ld_7_2, + OPERAND_fld_F4_S1_Ld_7_4, + OPERAND_fld_F4_S1_Ld_7_6, + OPERAND_fld_F4_S1_Ld_7_7, + OPERAND_fld_F4_S2_Mul_32_26, + OPERAND_fld_F4_S2_Mul_32_8, + OPERAND_fld_F4_S2_Mul_3_0, + OPERAND_fld_F4_S2_Mul_7_0, + OPERAND_fld_ivp_sem_multiply_vq, + OPERAND_fld_F4_S3_ALU_0_0, + OPERAND_fld_F4_S3_ALU_14_10, + OPERAND_fld_F4_S3_ALU_14_11, + OPERAND_fld_F4_S3_ALU_14_12, + OPERAND_fld_F4_S3_ALU_14_13, + OPERAND_fld_F4_S3_ALU_14_14, + OPERAND_fld_F4_S3_ALU_14_6, + OPERAND_fld_F4_S3_ALU_14_8, + OPERAND_fld_F4_S3_ALU_19_13, + OPERAND_fld_F4_S3_ALU_19_6, + OPERAND_fld_F4_S3_ALU_19_8, + OPERAND_fld_F4_S3_ALU_24_12, + OPERAND_fld_F4_S3_ALU_24_13, + OPERAND_fld_F4_S3_ALU_24_18, + OPERAND_fld_F4_S3_ALU_24_20, + OPERAND_fld_F4_S3_ALU_24_21, + OPERAND_fld_F4_S3_ALU_31_13, + OPERAND_fld_F4_S3_ALU_31_19, + OPERAND_fld_F4_S3_ALU_31_20, + OPERAND_fld_F4_S3_ALU_31_23, + OPERAND_fld_F4_S3_ALU_31_25, + OPERAND_fld_F4_S3_ALU_31_26, + OPERAND_fld_F4_S3_ALU_31_28, + OPERAND_fld_F4_S3_ALU_31_7, + OPERAND_fld_F4_S3_ALU_31_8, + OPERAND_fld_F4_S3_ALU_3_0, + OPERAND_fld_F4_S3_ALU_3_1, + OPERAND_fld_F4_S3_ALU_3_2, + OPERAND_fld_F4_S3_ALU_3_3, + OPERAND_fld_F4_S3_ALU_6_0, + OPERAND_fld_F4_S3_ALU_7_4, + OPERAND_fld_F4_S3_ALU_7_5, + OPERAND_fld_F4_S3_ALU_9_8, + OPERAND_fld_F5_S0_Base_11_0, + OPERAND_fld_F5_S0_Base_11_8, + OPERAND_fld_F5_S0_Base_11_9, + OPERAND_fld_F5_S0_Base_36_12, + OPERAND_fld_F5_S0_Base_36_13, + OPERAND_fld_F5_S0_Base_36_16, + OPERAND_fld_F5_S0_Base_36_17, + OPERAND_fld_F5_S0_Base_36_18, + OPERAND_fld_F5_S0_Base_36_20, + OPERAND_fld_F5_S0_Base_36_27, + OPERAND_fld_F5_S0_Base_3_0, + OPERAND_fld_F5_S0_Base_3_1, + OPERAND_fld_F5_S0_Base_7_4, + OPERAND_fld_F5_S1_Base_27_12, + OPERAND_fld_F5_S1_Base_27_13, + OPERAND_fld_F5_S1_Base_27_16, + OPERAND_fld_F5_S1_Base_27_17, + OPERAND_fld_F5_S1_Base_27_3, + OPERAND_fld_F5_S1_Base_2_0, + OPERAND_fld_F5_S1_Base_3_0, + OPERAND_fld_F5_S1_Base_7_4, + OPERAND_fld_F5_S2_Base_1_0, + OPERAND_fld_F5_S2_Base_26_12, + OPERAND_fld_F5_S2_Base_26_13, + OPERAND_fld_F5_S2_Base_26_16, + OPERAND_fld_F5_S2_Base_26_2, + OPERAND_fld_F5_S2_Base_26_8, + OPERAND_fld_F5_S2_Base_3_0, + OPERAND_fld_F5_S2_Base_7_4, + OPERAND_fld_F5_S3_Base_0_0, + OPERAND_fld_F5_S3_Base_25_1, + OPERAND_fld_F5_S3_Base_25_16, + OPERAND_fld_F5_S3_Base_25_8, + OPERAND_fld_F11_S0_Ld_1_0, + OPERAND_fld_F11_S0_Ld_23_0, + OPERAND_fld_F11_S0_Ld_23_12, + OPERAND_fld_F11_S0_Ld_23_13, + OPERAND_fld_F11_S0_Ld_23_16, + OPERAND_fld_F11_S0_Ld_23_17, + OPERAND_fld_F11_S0_Ld_23_20, + OPERAND_fld_F11_S0_Ld_23_4, + OPERAND_fld_F11_S0_Ld_3_0, + OPERAND_fld_F11_S0_Ld_7_4, + OPERAND_fld_F11_S1_ALU_12_10, + OPERAND_fld_F11_S1_ALU_12_11, + OPERAND_fld_F11_S1_ALU_12_12, + OPERAND_fld_F11_S1_ALU_12_3, + OPERAND_fld_F11_S1_ALU_12_4, + OPERAND_fld_F11_S1_ALU_12_9, + OPERAND_fld_F11_S1_ALU_15_13, + OPERAND_fld_F11_S1_ALU_15_14, + OPERAND_fld_F11_S1_ALU_15_15, + OPERAND_fld_F11_S1_ALU_15_2, + OPERAND_fld_F11_S1_ALU_22_0, + OPERAND_fld_F11_S1_ALU_22_12, + OPERAND_fld_F11_S1_ALU_22_13, + OPERAND_fld_F11_S1_ALU_22_14, + OPERAND_fld_F11_S1_ALU_22_16, + OPERAND_fld_F11_S1_ALU_22_18, + OPERAND_fld_F11_S1_ALU_3_0, + OPERAND_fld_F11_S1_ALU_7_4, + OPERAND_fld_ivp_sem_ld_st_vrul2, + OPERAND_fld_F11_S2_Mul_11_8, + OPERAND_fld_F11_S2_Mul_13_12, + OPERAND_fld_F11_S2_Mul_13_7, + OPERAND_fld_F11_S2_Mul_22_0, + OPERAND_fld_F11_S2_Mul_22_12, + OPERAND_fld_F11_S2_Mul_22_13, + OPERAND_fld_F11_S2_Mul_22_14, + OPERAND_fld_F11_S2_Mul_22_15, + OPERAND_fld_F11_S2_Mul_22_16, + OPERAND_fld_F11_S2_Mul_22_8, + OPERAND_fld_F11_S2_Mul_3_0, + OPERAND_fld_F11_S2_Mul_3_3, + OPERAND_fld_F11_S2_Mul_4_0, + OPERAND_fld_F11_S2_Mul_7_4, + OPERAND_fld_F11_S2_Mul_7_5, + OPERAND_fld_F11_S3_ALU_0_0, + OPERAND_fld_F11_S3_ALU_14_10, + OPERAND_fld_F11_S3_ALU_14_11, + OPERAND_fld_F11_S3_ALU_14_13, + OPERAND_fld_F11_S3_ALU_14_8, + OPERAND_fld_F11_S3_ALU_25_1, + OPERAND_fld_F11_S3_ALU_25_11, + OPERAND_fld_F11_S3_ALU_25_13, + OPERAND_fld_F11_S3_ALU_25_14, + OPERAND_fld_F11_S3_ALU_25_15, + OPERAND_fld_F11_S3_ALU_25_16, + OPERAND_fld_F11_S3_ALU_25_17, + OPERAND_fld_F11_S3_ALU_25_18, + OPERAND_fld_F11_S3_ALU_25_22, + OPERAND_fld_F11_S3_ALU_25_8, + OPERAND_fld_F11_S3_ALU_3_0, + OPERAND_fld_F11_S3_ALU_3_1, + OPERAND_fld_F11_S3_ALU_7_0, + OPERAND_fld_F11_S3_ALU_7_4, + OPERAND_fld_F11_S3_ALU_9_8, + OPERAND_fld_F11_S3_ALU_9_9, + OPERAND_fld_F11_S4_ALU_24_0, + OPERAND_fld_F11_S4_ALU_24_15, + OPERAND_fld_F11_S4_ALU_24_18, + OPERAND_fld_F11_S4_ALU_9_5, + OPERAND_fld_N1_S0_LdSt_12_0, + OPERAND_fld_N1_S0_LdSt_12_12, + OPERAND_fld_N1_S0_LdSt_12_2, + OPERAND_fld_N1_S0_LdSt_12_4, + OPERAND_fld_N1_S0_LdSt_12_8, + OPERAND_fld_N1_S0_LdSt_15_15, + OPERAND_fld_N1_S0_LdSt_1_0, + OPERAND_fld_N1_S0_LdSt_26_12, + OPERAND_fld_N1_S0_LdSt_26_13, + OPERAND_fld_N1_S0_LdSt_26_15, + OPERAND_fld_N1_S0_LdSt_26_16, + OPERAND_fld_N1_S0_LdSt_26_17, + OPERAND_fld_N1_S0_LdSt_26_18, + OPERAND_fld_N1_S0_LdSt_26_2, + OPERAND_fld_N1_S0_LdSt_26_20, + OPERAND_fld_N1_S0_LdSt_26_4, + OPERAND_fld_N1_S0_LdSt_26_8, + OPERAND_fld_N1_S0_LdSt_26_9, + OPERAND_fld_N1_S0_LdSt_3_0, + OPERAND_fld_N1_S0_LdSt_3_2, + OPERAND_fld_N1_S0_LdSt_7_2, + OPERAND_fld_N1_S0_LdSt_7_4, + OPERAND_fld_N1_S0_LdSt_7_5, + OPERAND_fld_N1_S0_LdSt_7_6, + OPERAND_fld_N1_S1_None_3_0, + OPERAND_fld_N1_S2_Mul_0_0, + OPERAND_fld_N1_S2_Mul_13_9, + OPERAND_fld_N1_S2_Mul_18_14, + OPERAND_fld_N1_S2_Mul_18_6, + OPERAND_fld_N1_S2_Mul_18_9, + OPERAND_fld_N1_S2_Mul_25_1, + OPERAND_fld_N1_S2_Mul_25_12, + OPERAND_fld_N1_S2_Mul_25_14, + OPERAND_fld_N1_S2_Mul_25_19, + OPERAND_fld_N1_S2_Mul_25_21, + OPERAND_fld_N1_S2_Mul_3_0, + OPERAND_fld_N1_S2_Mul_3_3, + OPERAND_fld_N1_S2_Mul_7_4, + OPERAND_fld_N1_S2_Mul_8_4, + OPERAND_fld_N1_S2_Mul_8_8, + OPERAND_fld_N2_S0_LdSt_12_0, + OPERAND_fld_N2_S0_LdSt_12_10, + OPERAND_fld_N2_S0_LdSt_12_11, + OPERAND_fld_N2_S0_LdSt_12_12, + OPERAND_fld_N2_S0_LdSt_12_4, + OPERAND_fld_N2_S0_LdSt_12_8, + OPERAND_fld_N2_S0_LdSt_13_11, + OPERAND_fld_N2_S0_LdSt_15_15, + OPERAND_fld_N2_S0_LdSt_29_10, + OPERAND_fld_N2_S0_LdSt_29_11, + OPERAND_fld_N2_S0_LdSt_29_12, + OPERAND_fld_N2_S0_LdSt_29_13, + OPERAND_fld_N2_S0_LdSt_29_14, + OPERAND_fld_N2_S0_LdSt_29_15, + OPERAND_fld_N2_S0_LdSt_29_16, + OPERAND_fld_N2_S0_LdSt_29_17, + OPERAND_fld_N2_S0_LdSt_29_18, + OPERAND_fld_N2_S0_LdSt_29_20, + OPERAND_fld_N2_S0_LdSt_29_5, + OPERAND_fld_N2_S0_LdSt_29_8, + OPERAND_fld_N2_S0_LdSt_3_0, + OPERAND_fld_N2_S0_LdSt_4_0, + OPERAND_fld_N2_S0_LdSt_4_4, + OPERAND_fld_N2_S0_LdSt_7_4, + OPERAND_fld_N2_S0_LdSt_7_6, + OPERAND_fld_N2_S0_LdSt_8_0, + OPERAND_fld_N2_S0_LdSt_8_4, + OPERAND_fld_N2_S0_LdSt_9_5, + OPERAND_fld_N2_S0_LdSt_9_6, + OPERAND_fld_N2_S1_Ld_12_10, + OPERAND_fld_N2_S1_Ld_12_2, + OPERAND_fld_N2_S1_Ld_12_4, + OPERAND_fld_N2_S1_Ld_12_8, + OPERAND_fld_N2_S1_Ld_1_0, + OPERAND_fld_N2_S1_Ld_26_10, + OPERAND_fld_N2_S1_Ld_26_11, + OPERAND_fld_N2_S1_Ld_26_12, + OPERAND_fld_N2_S1_Ld_26_13, + OPERAND_fld_N2_S1_Ld_26_15, + OPERAND_fld_N2_S1_Ld_26_16, + OPERAND_fld_N2_S1_Ld_26_17, + OPERAND_fld_N2_S1_Ld_26_2, + OPERAND_fld_N2_S1_Ld_26_8, + OPERAND_fld_N2_S1_Ld_26_9, + OPERAND_fld_N2_S1_Ld_3_0, + OPERAND_fld_N2_S1_Ld_3_2, + OPERAND_fld_N2_S1_Ld_4_0, + OPERAND_fld_N2_S1_Ld_4_3, + OPERAND_fld_N2_S1_Ld_4_4, + OPERAND_fld_N2_S1_Ld_7_0, + OPERAND_fld_N2_S1_Ld_7_2, + OPERAND_fld_N2_S1_Ld_7_4, + OPERAND_fld_N2_S1_Ld_7_6, + OPERAND_fld_N2_S1_Ld_7_7, + OPERAND_fld_N0_S0_LdSt_12_0, + OPERAND_fld_N0_S0_LdSt_12_12, + OPERAND_fld_N0_S0_LdSt_12_2, + OPERAND_fld_N0_S0_LdSt_12_4, + OPERAND_fld_N0_S0_LdSt_12_8, + OPERAND_fld_N0_S0_LdSt_22_0, + OPERAND_fld_N0_S0_LdSt_22_12, + OPERAND_fld_N0_S0_LdSt_22_13, + OPERAND_fld_N0_S0_LdSt_22_15, + OPERAND_fld_N0_S0_LdSt_22_16, + OPERAND_fld_N0_S0_LdSt_22_17, + OPERAND_fld_N0_S0_LdSt_3_0, + OPERAND_fld_N0_S0_LdSt_7_4, + OPERAND_fld_N0_S0_LdSt_7_5, + OPERAND_fld_N0_S0_LdSt_7_6, + OPERAND_fld_N0_S1_None_2_0, + OPERAND_fld_N0_S2_None_2_0, + OPERAND_fld_N0_S3_ALU_14_10, + OPERAND_fld_N0_S3_ALU_14_13, + OPERAND_fld_N0_S3_ALU_14_14, + OPERAND_fld_N0_S3_ALU_14_5, + OPERAND_fld_N0_S3_ALU_19_12, + OPERAND_fld_N0_S3_ALU_19_13, + OPERAND_fld_N0_S3_ALU_19_15, + OPERAND_fld_N0_S3_ALU_27_12, + OPERAND_fld_N0_S3_ALU_27_13, + OPERAND_fld_N0_S3_ALU_27_15, + OPERAND_fld_N0_S3_ALU_27_16, + OPERAND_fld_N0_S3_ALU_27_19, + OPERAND_fld_N0_S3_ALU_27_20, + OPERAND_fld_N0_S3_ALU_27_22, + OPERAND_fld_N0_S3_ALU_27_23, + OPERAND_fld_N0_S3_ALU_27_3, + OPERAND_fld_N0_S3_ALU_2_0, + OPERAND_fld_N0_S3_ALU_3_0, + OPERAND_fld_N0_S3_ALU_7_0, + OPERAND_fld_N0_S3_ALU_9_0, + OPERAND_fld_N0_S3_ALU_9_3, + OPERAND_fld_N0_S3_ALU_9_4, + OPERAND_fld_N0_S3_ALU_9_5, + OPERAND_fld_N0_S3_ALU_9_6, + OPERAND_fld_N0_S3_ALU_9_7, + OPERAND_fld_N0_S3_ALU_9_9, + OPERAND_fld_MTK_AndPOPC_c, + OPERAND_fld_MTK_AndPOPC_inB, + OPERAND_fld_MTK_AndPOPC_inA, + OPERAND_fld_MTK_AndPOPC_oData, + OPERAND_fld_F11_S4_ALU_24_16, + OPERAND_fld_F3_S4_ALU_23_16, + OPERAND_fld_iq_tie2apb_inq0_pop_qdata, + OPERAND_fld_iq_tie2apb_inq0_is_ready_is_ready, + OPERAND_fld_Inst_11_8, + OPERAND_fld_iq_tie2apb_inq0_nonblocking_peek_success, + OPERAND_fld_iq_tie2apb_inq0_nonblocking_peek_qdata, + OPERAND_fld_iq_tie2apb_inq0_nonblocking_pop_success, + OPERAND_fld_iq_tie2apb_inq0_nonblocking_pop_qdata, + OPERAND_fld_Inst_23_8, + OPERAND_fld_iq_tie2apb_inq0_blocking_peek_qdata, + OPERAND_fld_Inst_23_12, + OPERAND_fld_oq_tie2apb_outq0_push_read_qaddr, + OPERAND_fld_oq_tie2apb_outq0_push_read_qdata, + OPERAND_fld_oq_tie2apb_outq0_push_write_qaddr, + OPERAND_fld_oq_tie2apb_outq0_push_write_qdata, + OPERAND_fld_oq_tie2apb_outq0_is_ready_is_ready, + OPERAND_fld_Inst_3_0, + OPERAND_fld_Inst_23_16, + OPERAND_fld_oq_tie2apb_outq0_nonblocking_push_read_success, + OPERAND_fld_oq_tie2apb_outq0_nonblocking_push_read_qaddr, + OPERAND_fld_oq_tie2apb_outq0_nonblocking_push_read_qdata, + OPERAND_fld_oq_tie2apb_outq0_nonblocking_push_write_success, + OPERAND_fld_oq_tie2apb_outq0_nonblocking_push_write_qaddr, + OPERAND_fld_oq_tie2apb_outq0_nonblocking_push_write_qdata +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_IVP_REPNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_rep_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_i }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_REPNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_rep_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_i }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_REP2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_rep_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_REP2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELS2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_rep_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELS2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_REPN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_rep_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_REPN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELSN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_rep_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELSN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXT0IB_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' }, + { { OPERAND_imm1_2N }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXT0IB_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NOTB_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NOTB_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ANDB_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ANDB_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ORB_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ORB_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_XORB_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_XORB_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ANDNOTB_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ANDNOTB_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MB_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MB_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRN_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRNI_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_bbe_ltrxnimm }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRNI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LBN_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6bn }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LBN_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LBN_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4bn }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LBN_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SBN_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6bn }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SBN_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SBN_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4bn }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SBN_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX16_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX16_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX16_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX16_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX16_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX16_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX16_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX16_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVBRBV_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVBRBV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVBVBR_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_br }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVBVBR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_JOINB_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_JOINB_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRN_2_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRN_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRN_2I_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_bbe_ltrxn_2imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRN_2I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LBN_2_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6bn_2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LBN_2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LBN_2_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4bn_2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LBN_2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SBN_2_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6bn_2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SBN_2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SBN_2_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4bn_2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SBN_2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX16_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX16_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX16_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX16_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX16_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX16_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX16_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX16_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVA16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVV_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLINX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLINX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLSINX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLSINX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRAINX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRAINX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLINX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLINX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLANX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRANX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_XOR2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_XOR2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AND2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AND2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_OR2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_OR2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NOT2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NOT2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSGNNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSGNNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NSANX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NSANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NSAUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NSAUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LENX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LENX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EQNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EQNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEQNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEQNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LEUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LEUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RBMINNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RBMINNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RBMAXNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RBMAXNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOV2NX8T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOV2NX8T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKL_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKQ_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKQ_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSNX16PACKL_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSNX16PACKL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSNX16PACKQ_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSNX16PACKQ_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8T_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8T_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8T_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8T_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8T_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8T_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8T_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8T_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8T_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8T_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8T_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8T_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8T_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8T_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8T_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8T_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXUNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXUNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINUNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINUNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXUNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXUNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINUNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINUNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKLT_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKLT_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKQT_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKQT_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDSNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDSNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBSNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBSNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGSNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGSNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LALIGN_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LALIGN_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LALIGN_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LALIGN_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SALIGN_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SALIGN_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SALIGN_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SALIGN_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LA_PP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LA_PP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAPOS_FP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAPOS_FP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MALIGN_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_valignr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MALIGN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ZALIGN_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'o' } +}; + +static xtensa_arg_internal Iclass_IVP_ZALIGN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LA2NX8_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_LA2NX8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SA2NX8_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_SA2NX8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAV2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAV2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAV2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAV2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFLNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFLNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVPINT16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_i_IMM_movint }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVPINT16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVPA16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVPA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULNX16PACKP_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULNX16PACKP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKP_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSNX16PACKP_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSNX16PACKP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKPT_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKPT_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDMOD16U_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8S_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8S_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8U_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8U_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8U_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8U_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8U_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8U_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8U_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8U_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8U_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8U_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8ST_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8ST_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8ST_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8ST_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8ST_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8ST_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8ST_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8ST_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8UT_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8UT_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8UT_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8UT_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8UT_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8UT_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8UT_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8UT_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8UT_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8UT_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8UT_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8UT_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8UT_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8UT_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8UT_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8UT_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAVNX8S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAVNX8S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAVNX8U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAVNX8U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAVNX8U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAVNX8U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LANX8S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_LANX8S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LANX8U_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_LANX8U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SANX8U_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_SANX8U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRACTBL_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRACTBL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRACTBH_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRACTBH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVINT16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_i_IMM_movint }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVINT16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVQINT16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_i_IMM_movint }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVQINT16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVQA16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVQA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVINX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_immmovvi }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVINX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEQNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' } +}; + +static xtensa_arg_internal Iclass_IVP_SEQNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULNX16PACKL_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULNX16PACKL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULNX16PACKQ_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULNX16PACKQ_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAV16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAV16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAVU16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAVU16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRNX16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_i }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX8S_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX8S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX8S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX8S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX8S_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX8S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX8S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX8S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8S_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8S_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX8S_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX8S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX8S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX8S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX8S_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX8S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX8S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX8S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAVNX8S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAVNX8S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SANX8S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_SANX8S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8ST_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8ST_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8ST_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8ST_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8ST_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8ST_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8ST_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8ST_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVBA1_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVBA1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAB1_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAB1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NOTB1_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NOTB1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ANDNOTB1_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ANDNOTB1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ORNOTB1_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ORNOTB1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S2NX24LL_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S2NX24LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S2NX24LH_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S2NX24LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S2NX24HL_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S2NX24HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S2NX24HH_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S2NX24HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64SNX48LL_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64SNX48LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64SNX48LH_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64SNX48LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64SNX48HL_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64SNX48HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64SNX48HH_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64SNX48HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT16S2NX24L_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT16S2NX24L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT16S2NX24H_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT16S2NX24H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32SNX48L_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32SNX48L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32SNX48H_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32SNX48H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT16U2NX24H_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT16U2NX24H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32UNX48H_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32UNX48H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64UN_2X96H_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64UN_2X96H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT16U2NX24L_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT16U2NX24L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24U2NX16_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24U2NX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24S2NX16_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24S2NX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S24_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24U32_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24U32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24UNX32L_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24UNX32L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24UNX32H_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24UNX32H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32UNX48L_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32UNX48L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48UNX32L_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48UNX32L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48UNX32_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48UNX32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48SNX32L_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48SNX32L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48SNX32_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48SNX32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64S48_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64S48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48U64_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48U64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48UN_2X64L_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48UN_2X64L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48UN_2X64H_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48UN_2X64H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64UN_2X96L_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64UN_2X96L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT96UN_2X64_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT96UN_2X64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT96U64_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT96U64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64U96_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64U96_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LB2N_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6b2n }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LB2N_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LB2N_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4b2n }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LB2N_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SB2N_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6b2n }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SB2N_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SB2N_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4b2n }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SB2N_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTR2N_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTR2N_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTR2NI_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_bbe_ltrx2nimm }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTR2NI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16U_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16U_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16U_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16U_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16U_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16UT_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16UT_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16UT_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16UT_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16UT_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16UT_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16UT_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16UT_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16S_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16S_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16ST_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16ST_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16ST_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16ST_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16ST_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16ST_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16ST_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16ST_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16U_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16U_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16UT_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16UT_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16U_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16UT_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16UT_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16U_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16U_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16UT_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16UT_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16UT_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16UT_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16S_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16ST_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16ST_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16ST_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16ST_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16S_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16ST_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16ST_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16ST_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16ST_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAN_2X16S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_LAN_2X16S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAN_2X16U_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_LAN_2X16U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAN_2X16U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAN_2X16U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAN_2X16S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAN_2X16S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAN_2X16U_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_SAN_2X16U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAN_2X16S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_SAN_2X16S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAVN_2X16S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAVN_2X16S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAVN_2X16U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAVN_2X16U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAVN_2X16U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAVN_2X16U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAVN_2X16S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAVN_2X16S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X16S_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X16S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X16S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X16S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X16S_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X16S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X16S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X16S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X16S_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X16S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X16S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X16S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X16S_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X16S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X16S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X16S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X32_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X32_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X32_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X32_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X32_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X32_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X32_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X32_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X32_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X32_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X32_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X32_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X32_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X32_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X32_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X32_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RBMINUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RBMINUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RBMAXUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RBMAXUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAX2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAX2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMIN2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMIN2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXUN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXUN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINUN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINUN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDN_2X32T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDN_2X32T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBN_2X32T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBN_2X32T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADD2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADD2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUB2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUB2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEG2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEG2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MIN2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MIN2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAX2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAX2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LT2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LT2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LE2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LE2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EQ2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EQ2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEQ2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEQ2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LEU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LEU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADD2NX8T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADD2NX8T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUB2NX8T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUB2NX8T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELN_2X32T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELN_2X32T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFLN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFLN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLIN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm6_31 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLIN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLSIN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm6_31 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLSIN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRAIN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm6_31 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRAIN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLIN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm6_31 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLIN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLAN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLAN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRAN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRAN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLSN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLSN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRSN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRSN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXUN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXUN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINUN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINUN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDN_2X32T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDN_2X32T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABS2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABS2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSGNSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSGNSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRI2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRI2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRINX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRINX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRIN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm6_31 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRIN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINUN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINUN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXUN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXUN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSGNN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSGNN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NSAN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NSAN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NSAUN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NSAUN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LEN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LEN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EQN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EQN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEQN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEQN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTUN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTUN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LEUN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LEUN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAT2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAT2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUS2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUS2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULI2NX8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULI2NX8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAI2NX8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAI2NX8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSI2NX8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSI2NX8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAI2NX8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAI2NX8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULI2NR8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULI2NR8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAI2NR8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAI2NR8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSI2NR8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSI2NR8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAI2NR8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAI2NR8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSA2N8XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSA2N8XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUS2N8XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUS2N8XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULA2N8XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULA2N8XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MUL2N8XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MUL2N8XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DSEL2NX8I_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vu }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_slct }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DSEL2NX8I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DSEL2NX8I_H_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_slct_h }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DSEL2NX8I_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DSELNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vu }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DSELNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DSELNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DSELNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_INJBI2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_i_imm3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_INJBI2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTBI2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_i_imm3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTBI2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVA32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAV32_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAV32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVWW_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVWW_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LS2NX8_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LS2NX8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LS2NX8_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LS2NX8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LS2NX8_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LS2NX8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LS2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LS2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SS2NX8_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SS2NX8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SS2NX8_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SS2NX8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SS2NX8_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SS2NX8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SS2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SS2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LANX8S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LANX8S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LANX8U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LANX8U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LA2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LA2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSUBU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSUBU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSUB2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSUB2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVINT8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_i_IMM_movint }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVINT8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVA8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVA8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAVU8_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAVU8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLI2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLI2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRAI2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRAI2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLI2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLI2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKL2NX24_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKL2NX24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVR2NX24_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVR2NX24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRU2NX24_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRU2NX24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKLNX48_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKLNX48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKL2NX24_1_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKL2NX24_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVR2NX24_0_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVR2NX24_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVR2NX24_1_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVR2NX24_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRU2NX24_0_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRU2NX24_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRU2NX24_1_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRU2NX24_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNR2NX24_0_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNR2NX24_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNR2NX24_1_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNR2NX24_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKMNX48_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKMNX48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNX48_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNX48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKS2NX8_0_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKS2NX8_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKS2NX8_1_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKS2NX8_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKSNX16_L_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKSNX16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKSNX16_H_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKSNX16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8I_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_isel }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8I_S0_args[] = { + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vr }, 'i' }, + { { OPERAND_bbe_selimm_S0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8I_S0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8I_S2_args[] = { + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vr }, 'i' }, + { { OPERAND_bbe_selimm_S2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8I_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8I_S4_args[] = { + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vr }, 'i' }, + { { OPERAND_bbe_selimm_S4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8I_S4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8I_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_ishfl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8I_S0_args[] = { + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vr }, 'i' }, + { { OPERAND_bbe_shflimm_S0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8I_S0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8I_S2_args[] = { + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vr }, 'i' }, + { { OPERAND_bbe_shflimm_S2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8I_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8I_S4_args[] = { + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vr }, 'i' }, + { { OPERAND_bbe_shflimm_S4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8I_S4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SQZN_args[] = { + { { OPERAND_opnd_ivp_sem_sqz_vt }, 'o' }, + { { OPERAND_arr }, 'o' }, + { { OPERAND_opnd_ivp_sem_sqz_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SQZN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNSQZN_args[] = { + { { OPERAND_opnd_ivp_sem_sqz_vt }, 'o' }, + { { OPERAND_arr }, 'o' }, + { { OPERAND_opnd_ivp_sem_sqz_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNSQZN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MUL2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MUL2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDW2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDW2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWS2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWS2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUS2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUS2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16S_4STEP0_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16S_4STEP0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16S_4STEP_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16S_4STEP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16S_4STEPN_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16S_4STEPN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16U_4STEP0_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16U_4STEP0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16U_4STEP_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16U_4STEP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16U_4STEPN_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16U_4STEPN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16S_4STEP0_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16S_4STEP0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16S_4STEP_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16S_4STEP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16S_4STEPN_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16S_4STEPN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16U_4STEP0_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16U_4STEP0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16U_4STEP_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16U_4STEP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16U_4STEPN_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16U_4STEPN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16SQ_4STEP0_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16SQ_4STEP0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16Q_4STEP0_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16Q_4STEP0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUAN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUAN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUAN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUAN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUAHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUAHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUAHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUAHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUAN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUAN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUAN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUAN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUSHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUSHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSSHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSSHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUSHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUSHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUSN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUSN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSSN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSSN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUSN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUSN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUSN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUSN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSSN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSSN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUSN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUSN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKLN_2X96_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKLN_2X96_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKHN_2X64W_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKHN_2X64W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRN_2X64W_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRN_2X64W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNRN_2X64W_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNRN_2X64W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNX48_0_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNX48_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNX48_1_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNX48_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNRNX48_0_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNRNX48_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNRNX48_1_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNRNX48_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNRNX48_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNRNX48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNR2NX24_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNR2NX24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_L2A4NX8_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul2 }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_L2A4NX8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_L2AU2NX8_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_L2AU2NX8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_L2U2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_L2U2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGRU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGRU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADD2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADD2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADD2NX8T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADD2NX8T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDUNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDUNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDU2NX8T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDU2NX8T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRS2N_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRS2N_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRSN_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRSN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRSN_2_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRSN_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEQ2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' } +}; + +static xtensa_arg_internal Iclass_IVP_SEQ2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEQN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' } +}; + +static xtensa_arg_internal Iclass_IVP_SEQN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRN_2X32_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKU2NX8_0_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKU2NX8_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKU2NX8_1_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKU2NX8_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BADDNORMNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BADDNORMNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BSUBNORMNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BSUBNORMNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDSNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDSNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ORNOTB_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ORNOTB_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTR2NX8_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTR2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRVRN_2X32_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRVRN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAV8_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAV8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPN16XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPN16XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPAN16XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPAN16XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPN16XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPN16XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPAN16XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPAN16XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULP2N8XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULP2N8XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPA2N8XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPA2N8XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSP2N8XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSP2N8XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPA2N8XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPA2N8XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUPNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUPNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUPANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUPANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULP2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULP2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSP2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSP2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUP2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUP2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUPA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUPA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPI2NR8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPI2NR8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPAI2NR8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPAI2NR8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPI2NR8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPI2NR8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPAI2NR8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPAI2NR8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULQ2N8XR8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULQ2N8XR8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULQA2N8XR8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULQA2N8XR8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSQ2N8XR8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSQ2N8XR8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSQA2N8XR8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSQA2N8XR8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MUL4T2N8XR8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MUL4T2N8XR8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MUL4TA2N8XR8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MUL4TA2N8XR8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUS4T2N8XR8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUS4T2N8XR8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUS4TA2N8XR8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUS4TA2N8XR8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWUANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWUANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBW2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBW2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWUA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWUA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RANDB2N_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RANDB2N_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RORB2N_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RORB2N_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RANDBN_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RANDBN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RORBN_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RORBN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RANDBN_2_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RANDBN_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RORBN_2_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RORBN_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVG2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVG2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGR2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGR2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGRNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGRNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGRUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGRUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERANX8U_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERANX8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERANX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERAN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERAN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERANX8UT_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERANX8UT_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERANX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERANX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERAN_2X32T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERAN_2X32T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERDNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERDNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERDNX8S_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERDNX8S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERD2NX8_L_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERD2NX8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERD2NX8_H_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERD2NX8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVGATHERD_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVGATHERD_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERNX8U_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERNX8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTER2NX8_L_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTER2NX8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTER2NX8_H_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTER2NX8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERNX8UT_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERNX8UT_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTER2NX8T_L_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTER2NX8T_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTER2NX8T_H_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTER2NX8T_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERN_2X32T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERN_2X32T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTEQZ4NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_histogram_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_arr }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTEQZ4NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTEQ4NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_histogram_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_arr }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTEQ4NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTEQMZ4NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_histogram_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_arr }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTEQMZ4NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTEQM4NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_histogram_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_arr }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTEQM4NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTLEZ4NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_histogram_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_arr }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTLEZ4NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTLE4NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_histogram_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_arr }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTLE4NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTLEMZ4NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_histogram_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_arr }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTLEMZ4NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTLEM4NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_histogram_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_arr }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTLEM4NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSR2NX8_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSR2NX8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSR2NX8_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSR2NX8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSR2NX8_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSR2NX8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSR2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSR2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRNX16_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRNX16_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRNX16_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRNX16_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRNX16_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRNX16_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRNX16_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRNX16_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRN_2X32_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRN_2X32_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRN_2X32_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRN_2X32_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRN_2X32_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRN_2X32_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRN_2X32_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRN_2X32_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSUBNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSUBNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSUBUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSUBUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSSUBNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSSUBNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSRING }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { OPERAND_ars_entry }, 's' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm12x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { OPERAND_simm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ai4const }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_simm7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8x256 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_label12 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_const16_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_imm16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sae }, 'i' }, + { { OPERAND_op2p1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { OPERAND_soffset }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_uimm16x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_simm12b }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ex_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ex_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_getex_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_getex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clrex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimmrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { OPERAND_sas }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_msalp32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sargt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_stateArgs[] = { + { { STATE_MEMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_stateArgs[] = { + { { STATE_MEMCTL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_stateArgs[] = { + { { STATE_MEMCTL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpucfg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpucfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUNUMENTRIES }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpucfg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpucfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUNUMENTRIES }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_gserr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_gserr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_gserr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_gserr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_gserr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_gserr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul16_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32h_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { OPERAND_imms }, 'i' }, + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'i' }, + { { STATE_DBREAKC_SG0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_DBREAKC_SG0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_DBREAKC_SG0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_bs }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { + { { OPERAND_bs }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_brall }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_brall }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_brall }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cacheadrdis_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cacheadrdis_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CACHEADRDIS }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cacheadrdis_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cacheadrdis_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CACHEADRDIS }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cacheadrdis_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cacheadrdis_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CACHEADRDIS }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb0_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wptlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wptlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpuenb_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpuenb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpuenb_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpuenb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_mpuenb_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_mpuenb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { + { { STATE_ERACCESS }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_ERI_RAW_INTERLOCK }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = { + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { + { { STATE_ERACCESS }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_ERI_RAW_INTERLOCK }, 'o' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = { + INTERFACE_ERI_WR_In, + INTERFACE_ERI_WR_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_1_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_2_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_3_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_MTK_AndPOPC_args[] = { + { { OPERAND_opnd_MTK_AndPOPC_oData }, 'o' }, + { { OPERAND_opnd_MTK_AndPOPC_inA }, 'i' }, + { { OPERAND_opnd_MTK_AndPOPC_inB }, 'i' }, + { { OPERAND_opnd_MTK_AndPOPC_c }, 'i' } +}; + +static xtensa_arg_internal Iclass_MTK_AndPOPC_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iq_tie2apb_inq0_pop_args[] = { + { { OPERAND_opnd_iq_tie2apb_inq0_pop_qdata }, 'o' } +}; + +static xtensa_arg_internal Iclass_iq_tie2apb_inq0_pop_stateArgs[] = { + { { STATE_APB_PIPE }, 'm' } +}; + +static xtensa_interface Iclass_iq_tie2apb_inq0_pop_intfArgs[] = { + INTERFACE_iq_tie2apb_inq0 +}; + +static xtensa_arg_internal Iclass_iq_tie2apb_inq0_is_ready_args[] = { + { { OPERAND_opnd_iq_tie2apb_inq0_is_ready_is_ready }, 'o' } +}; + +static xtensa_interface Iclass_iq_tie2apb_inq0_is_ready_intfArgs[] = { + INTERFACE_iq_tie2apb_inq0_NOTRDY +}; + +static xtensa_arg_internal Iclass_iq_tie2apb_inq0_nonblocking_peek_args[] = { + { { OPERAND_opnd_iq_tie2apb_inq0_nonblocking_peek_qdata }, 'm' }, + { { OPERAND_opnd_iq_tie2apb_inq0_nonblocking_peek_success }, 'o' } +}; + +static xtensa_interface Iclass_iq_tie2apb_inq0_nonblocking_peek_intfArgs[] = { + INTERFACE_iq_tie2apb_inq0, + INTERFACE_iq_tie2apb_inq0_NOTRDY, + INTERFACE_iq_tie2apb_inq0_KILL +}; + +static xtensa_arg_internal Iclass_iq_tie2apb_inq0_nonblocking_pop_args[] = { + { { OPERAND_opnd_iq_tie2apb_inq0_nonblocking_pop_qdata }, 'm' }, + { { OPERAND_opnd_iq_tie2apb_inq0_nonblocking_pop_success }, 'o' } +}; + +static xtensa_arg_internal Iclass_iq_tie2apb_inq0_nonblocking_pop_stateArgs[] = { + { { STATE_APB_PIPE }, 'm' } +}; + +static xtensa_interface Iclass_iq_tie2apb_inq0_nonblocking_pop_intfArgs[] = { + INTERFACE_iq_tie2apb_inq0, + INTERFACE_iq_tie2apb_inq0_NOTRDY, + INTERFACE_iq_tie2apb_inq0_KILL +}; + +static xtensa_arg_internal Iclass_iq_tie2apb_inq0_blocking_peek_args[] = { + { { OPERAND_opnd_iq_tie2apb_inq0_blocking_peek_qdata }, 'o' } +}; + +static xtensa_interface Iclass_iq_tie2apb_inq0_blocking_peek_intfArgs[] = { + INTERFACE_iq_tie2apb_inq0, + INTERFACE_iq_tie2apb_inq0_KILL, + INTERFACE_iq_tie2apb_inq0_NOTRDY +}; + +static xtensa_arg_internal Iclass_oq_tie2apb_outq0_push_read_args[] = { + { { OPERAND_opnd_oq_tie2apb_outq0_push_read_qdata }, 'i' }, + { { OPERAND_opnd_oq_tie2apb_outq0_push_read_qaddr }, 'i' } +}; + +static xtensa_arg_internal Iclass_oq_tie2apb_outq0_push_read_stateArgs[] = { + { { STATE_APB_PIPE }, 'm' } +}; + +static xtensa_interface Iclass_oq_tie2apb_outq0_push_read_intfArgs[] = { + INTERFACE_oq_tie2apb_outq0 +}; + +static xtensa_arg_internal Iclass_oq_tie2apb_outq0_push_write_args[] = { + { { OPERAND_opnd_oq_tie2apb_outq0_push_write_qdata }, 'i' }, + { { OPERAND_opnd_oq_tie2apb_outq0_push_write_qaddr }, 'i' } +}; + +static xtensa_arg_internal Iclass_oq_tie2apb_outq0_push_write_stateArgs[] = { + { { STATE_APB_PIPE }, 'm' } +}; + +static xtensa_interface Iclass_oq_tie2apb_outq0_push_write_intfArgs[] = { + INTERFACE_oq_tie2apb_outq0 +}; + +static xtensa_arg_internal Iclass_oq_tie2apb_outq0_is_ready_args[] = { + { { OPERAND_opnd_oq_tie2apb_outq0_is_ready_is_ready }, 'o' } +}; + +static xtensa_interface Iclass_oq_tie2apb_outq0_is_ready_intfArgs[] = { + INTERFACE_oq_tie2apb_outq0_NOTRDY +}; + +static xtensa_arg_internal Iclass_oq_tie2apb_outq0_nonblocking_push_read_args[] = { + { { OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_read_qdata }, 'i' }, + { { OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_read_qaddr }, 'i' }, + { { OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_read_success }, 'o' } +}; + +static xtensa_arg_internal Iclass_oq_tie2apb_outq0_nonblocking_push_read_stateArgs[] = { + { { STATE_APB_PIPE }, 'm' } +}; + +static xtensa_interface Iclass_oq_tie2apb_outq0_nonblocking_push_read_intfArgs[] = { + INTERFACE_oq_tie2apb_outq0, + INTERFACE_oq_tie2apb_outq0_NOTRDY, + INTERFACE_oq_tie2apb_outq0_KILL +}; + +static xtensa_arg_internal Iclass_oq_tie2apb_outq0_nonblocking_push_write_args[] = { + { { OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_write_qdata }, 'i' }, + { { OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_write_qaddr }, 'i' }, + { { OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_write_success }, 'o' } +}; + +static xtensa_arg_internal Iclass_oq_tie2apb_outq0_nonblocking_push_write_stateArgs[] = { + { { STATE_APB_PIPE }, 'm' } +}; + +static xtensa_interface Iclass_oq_tie2apb_outq0_nonblocking_push_write_intfArgs[] = { + INTERFACE_oq_tie2apb_outq0, + INTERFACE_oq_tie2apb_outq0_NOTRDY, + INTERFACE_oq_tie2apb_outq0_KILL +}; + +static xtensa_arg_internal Iclass_rur_apb_pipe_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_apb_pipe_stateArgs[] = { + { { STATE_APB_PIPE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_apb_pipe_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_apb_pipe_stateArgs[] = { + { { STATE_APB_PIPE }, 'o' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 3, Iclass_IVP_REPNX16_args, + 1, Iclass_IVP_REPNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SELSNX16_args, + 1, Iclass_IVP_SELSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_REP2NX8_args, + 1, Iclass_IVP_REP2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SELS2NX8_args, + 1, Iclass_IVP_SELS2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_REPN_2X32_args, + 1, Iclass_IVP_REPN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SELSN_2X32_args, + 1, Iclass_IVP_SELSN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_EXT0IB_args, + 1, Iclass_IVP_EXT0IB_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NOTB_args, + 1, Iclass_IVP_NOTB_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ANDB_args, + 1, Iclass_IVP_ANDB_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ORB_args, + 1, Iclass_IVP_ORB_stateArgs, 0, 0 }, + { 3, Iclass_IVP_XORB_args, + 1, Iclass_IVP_XORB_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ANDNOTB_args, + 1, Iclass_IVP_ANDNOTB_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MB_args, + 1, Iclass_IVP_MB_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LTRN_args, + 1, Iclass_IVP_LTRN_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LTRNI_args, + 1, Iclass_IVP_LTRNI_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LBN_I_args, + 1, Iclass_IVP_LBN_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LBN_IP_args, + 1, Iclass_IVP_LBN_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SBN_I_args, + 1, Iclass_IVP_SBN_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SBN_IP_args, + 1, Iclass_IVP_SBN_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSNX16_I_args, + 1, Iclass_IVP_LSNX16_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSNX16_IP_args, + 1, Iclass_IVP_LSNX16_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSNX16_X_args, + 1, Iclass_IVP_LSNX16_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSNX16_XP_args, + 1, Iclass_IVP_LSNX16_XP_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVBRBV_args, + 1, Iclass_IVP_MOVBRBV_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVBVBR_args, + 1, Iclass_IVP_MOVBVBR_stateArgs, 0, 0 }, + { 3, Iclass_IVP_JOINB_args, + 1, Iclass_IVP_JOINB_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LTRN_2_args, + 1, Iclass_IVP_LTRN_2_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LTRN_2I_args, + 1, Iclass_IVP_LTRN_2I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LBN_2_I_args, + 1, Iclass_IVP_LBN_2_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LBN_2_IP_args, + 1, Iclass_IVP_LBN_2_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SBN_2_I_args, + 1, Iclass_IVP_SBN_2_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SBN_2_IP_args, + 1, Iclass_IVP_SBN_2_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LV2NX8_I_args, + 1, Iclass_IVP_LV2NX8_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LV2NX8_IP_args, + 1, Iclass_IVP_LV2NX8_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LV2NX8_X_args, + 1, Iclass_IVP_LV2NX8_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LV2NX8_XP_args, + 1, Iclass_IVP_LV2NX8_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SV2NX8_I_args, + 1, Iclass_IVP_SV2NX8_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SV2NX8_IP_args, + 1, Iclass_IVP_SV2NX8_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SV2NX8_X_args, + 1, Iclass_IVP_SV2NX8_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SV2NX8_XP_args, + 1, Iclass_IVP_SV2NX8_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSNX16_I_args, + 1, Iclass_IVP_SSNX16_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSNX16_IP_args, + 1, Iclass_IVP_SSNX16_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSNX16_X_args, + 1, Iclass_IVP_SSNX16_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSNX16_XP_args, + 1, Iclass_IVP_SSNX16_XP_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVVA16_args, + 1, Iclass_IVP_MOVVA16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVVV_args, + 1, Iclass_IVP_MOVVV_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLLINX16_args, + 1, Iclass_IVP_SLLINX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLSINX16_args, + 1, Iclass_IVP_SLSINX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRAINX16_args, + 1, Iclass_IVP_SRAINX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRLINX16_args, + 1, Iclass_IVP_SRLINX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLLNX16_args, + 1, Iclass_IVP_SLLNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRLNX16_args, + 1, Iclass_IVP_SRLNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLANX16_args, + 1, Iclass_IVP_SLANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRANX16_args, + 1, Iclass_IVP_SRANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLSNX16_args, + 1, Iclass_IVP_SLSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRSNX16_args, + 1, Iclass_IVP_SRSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_XOR2NX8_args, + 1, Iclass_IVP_XOR2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_AND2NX8_args, + 1, Iclass_IVP_AND2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_OR2NX8_args, + 1, Iclass_IVP_OR2NX8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NOT2NX8_args, + 1, Iclass_IVP_NOT2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDNX16_args, + 1, Iclass_IVP_ADDNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBNX16_args, + 1, Iclass_IVP_SUBNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NEGNX16_args, + 1, Iclass_IVP_NEGNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MINNX16_args, + 1, Iclass_IVP_MINNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MINUNX16_args, + 1, Iclass_IVP_MINUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MAXNX16_args, + 1, Iclass_IVP_MAXNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MAXUNX16_args, + 1, Iclass_IVP_MAXUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSGNNX16_args, + 1, Iclass_IVP_MULSGNNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NSANX16_args, + 1, Iclass_IVP_NSANX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NSAUNX16_args, + 1, Iclass_IVP_NSAUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LTNX16_args, + 1, Iclass_IVP_LTNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LENX16_args, + 1, Iclass_IVP_LENX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_EQNX16_args, + 1, Iclass_IVP_EQNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_NEQNX16_args, + 1, Iclass_IVP_NEQNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LTUNX16_args, + 1, Iclass_IVP_LTUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LEUNX16_args, + 1, Iclass_IVP_LEUNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RADDNX16_args, + 1, Iclass_IVP_RADDNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RMAXNX16_args, + 1, Iclass_IVP_RMAXNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RMINNX16_args, + 1, Iclass_IVP_RMINNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RMAXUNX16_args, + 1, Iclass_IVP_RMAXUNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RMINUNX16_args, + 1, Iclass_IVP_RMINUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RBMINNX16_args, + 1, Iclass_IVP_RBMINNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RBMAXNX16_args, + 1, Iclass_IVP_RBMAXNX16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMAXNX16_args, + 1, Iclass_IVP_BMAXNX16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMINNX16_args, + 1, Iclass_IVP_BMINNX16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MOV2NX8T_args, + 1, Iclass_IVP_MOV2NX8T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULANX16PACKL_args, + 1, Iclass_IVP_MULANX16PACKL_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULANX16PACKQ_args, + 1, Iclass_IVP_MULANX16PACKQ_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSNX16PACKL_args, + 1, Iclass_IVP_MULSNX16PACKL_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSNX16PACKQ_args, + 1, Iclass_IVP_MULSNX16PACKQ_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDSNX16_args, + 1, Iclass_IVP_ADDSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBSNX16_args, + 1, Iclass_IVP_SUBSNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NEGSNX16_args, + 1, Iclass_IVP_NEGSNX16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LV2NX8T_I_args, + 1, Iclass_IVP_LV2NX8T_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LV2NX8T_IP_args, + 1, Iclass_IVP_LV2NX8T_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LV2NX8T_X_args, + 1, Iclass_IVP_LV2NX8T_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LV2NX8T_XP_args, + 1, Iclass_IVP_LV2NX8T_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SV2NX8T_I_args, + 1, Iclass_IVP_SV2NX8T_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SV2NX8T_IP_args, + 1, Iclass_IVP_SV2NX8T_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SV2NX8T_X_args, + 1, Iclass_IVP_SV2NX8T_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SV2NX8T_XP_args, + 1, Iclass_IVP_SV2NX8T_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RADDNX16T_args, + 1, Iclass_IVP_RADDNX16T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RMAXNX16T_args, + 1, Iclass_IVP_RMAXNX16T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RMINNX16T_args, + 1, Iclass_IVP_RMINNX16T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RMAXUNX16T_args, + 1, Iclass_IVP_RMAXUNX16T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RMINUNX16T_args, + 1, Iclass_IVP_RMINUNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_ADDNX16T_args, + 1, Iclass_IVP_ADDNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SUBNX16T_args, + 1, Iclass_IVP_SUBNX16T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_NEGNX16T_args, + 1, Iclass_IVP_NEGNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MAXNX16T_args, + 1, Iclass_IVP_MAXNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MINNX16T_args, + 1, Iclass_IVP_MINNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MAXUNX16T_args, + 1, Iclass_IVP_MAXUNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MINUNX16T_args, + 1, Iclass_IVP_MINUNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULANX16PACKLT_args, + 1, Iclass_IVP_MULANX16PACKLT_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULANX16PACKQT_args, + 1, Iclass_IVP_MULANX16PACKQT_stateArgs, 0, 0 }, + { 4, Iclass_IVP_ADDSNX16T_args, + 1, Iclass_IVP_ADDSNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SUBSNX16T_args, + 1, Iclass_IVP_SUBSNX16T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_NEGSNX16T_args, + 1, Iclass_IVP_NEGSNX16T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LALIGN_I_args, + 1, Iclass_IVP_LALIGN_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LALIGN_IP_args, + 1, Iclass_IVP_LALIGN_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SALIGN_I_args, + 1, Iclass_IVP_SALIGN_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SALIGN_IP_args, + 1, Iclass_IVP_SALIGN_IP_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LA_PP_args, + 1, Iclass_IVP_LA_PP_stateArgs, 0, 0 }, + { 2, Iclass_IVP_SAPOS_FP_args, + 1, Iclass_IVP_SAPOS_FP_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MALIGN_args, + 1, Iclass_IVP_MALIGN_stateArgs, 0, 0 }, + { 1, Iclass_IVP_ZALIGN_args, + 1, Iclass_IVP_ZALIGN_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LA2NX8_IP_args, + 1, Iclass_IVP_LA2NX8_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SA2NX8_IP_args, + 1, Iclass_IVP_SA2NX8_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LAV2NX8_XP_args, + 1, Iclass_IVP_LAV2NX8_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SAV2NX8_XP_args, + 1, Iclass_IVP_SAV2NX8_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SELNX16_args, + 1, Iclass_IVP_SELNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SHFLNX16_args, + 1, Iclass_IVP_SHFLNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVPINT16_args, + 1, Iclass_IVP_MOVPINT16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVPA16_args, + 1, Iclass_IVP_MOVPA16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULNX16PACKP_args, + 1, Iclass_IVP_MULNX16PACKP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULANX16PACKP_args, + 1, Iclass_IVP_MULANX16PACKP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSNX16PACKP_args, + 1, Iclass_IVP_MULSNX16PACKP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULANX16PACKPT_args, + 1, Iclass_IVP_MULANX16PACKPT_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDMOD16U_args, + 0, 0, 0, 0 }, + { 3, Iclass_IVP_LVNX8S_I_args, + 1, Iclass_IVP_LVNX8S_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVNX8S_IP_args, + 1, Iclass_IVP_LVNX8S_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVNX8S_X_args, + 1, Iclass_IVP_LVNX8S_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVNX8S_XP_args, + 1, Iclass_IVP_LVNX8S_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVNX8U_I_args, + 1, Iclass_IVP_LVNX8U_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVNX8U_IP_args, + 1, Iclass_IVP_LVNX8U_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVNX8U_X_args, + 1, Iclass_IVP_LVNX8U_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVNX8U_XP_args, + 1, Iclass_IVP_LVNX8U_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVNX8U_I_args, + 1, Iclass_IVP_SVNX8U_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVNX8U_IP_args, + 1, Iclass_IVP_SVNX8U_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVNX8U_X_args, + 1, Iclass_IVP_SVNX8U_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVNX8U_XP_args, + 1, Iclass_IVP_SVNX8U_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVNX8ST_I_args, + 1, Iclass_IVP_LVNX8ST_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVNX8ST_IP_args, + 1, Iclass_IVP_LVNX8ST_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVNX8ST_X_args, + 1, Iclass_IVP_LVNX8ST_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVNX8ST_XP_args, + 1, Iclass_IVP_LVNX8ST_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVNX8UT_I_args, + 1, Iclass_IVP_LVNX8UT_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVNX8UT_IP_args, + 1, Iclass_IVP_LVNX8UT_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVNX8UT_X_args, + 1, Iclass_IVP_LVNX8UT_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVNX8UT_XP_args, + 1, Iclass_IVP_LVNX8UT_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVNX8UT_I_args, + 1, Iclass_IVP_SVNX8UT_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVNX8UT_IP_args, + 1, Iclass_IVP_SVNX8UT_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVNX8UT_X_args, + 1, Iclass_IVP_SVNX8UT_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVNX8UT_XP_args, + 1, Iclass_IVP_SVNX8UT_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LAVNX8S_XP_args, + 1, Iclass_IVP_LAVNX8S_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LAVNX8U_XP_args, + 1, Iclass_IVP_LAVNX8U_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SAVNX8U_XP_args, + 1, Iclass_IVP_SAVNX8U_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LANX8S_IP_args, + 1, Iclass_IVP_LANX8S_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LANX8U_IP_args, + 1, Iclass_IVP_LANX8U_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SANX8U_IP_args, + 1, Iclass_IVP_SANX8U_IP_stateArgs, 0, 0 }, + { 2, Iclass_IVP_EXTRACTBL_args, + 1, Iclass_IVP_EXTRACTBL_stateArgs, 0, 0 }, + { 2, Iclass_IVP_EXTRACTBH_args, + 1, Iclass_IVP_EXTRACTBH_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVVINT16_args, + 1, Iclass_IVP_MOVVINT16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVQINT16_args, + 1, Iclass_IVP_MOVQINT16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVQA16_args, + 1, Iclass_IVP_MOVQA16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVVINX16_args, + 1, Iclass_IVP_MOVVINX16_stateArgs, 0, 0 }, + { 1, Iclass_IVP_SEQNX16_args, + 1, Iclass_IVP_SEQNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULNX16PACKL_args, + 1, Iclass_IVP_MULNX16PACKL_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULNX16PACKQ_args, + 1, Iclass_IVP_MULNX16PACKQ_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVAV16_args, + 1, Iclass_IVP_MOVAV16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVAVU16_args, + 1, Iclass_IVP_MOVAVU16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_EXTRNX16_args, + 1, Iclass_IVP_EXTRNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSNX8S_I_args, + 1, Iclass_IVP_LSNX8S_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSNX8S_IP_args, + 1, Iclass_IVP_LSNX8S_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSNX8S_X_args, + 1, Iclass_IVP_LSNX8S_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSNX8S_XP_args, + 1, Iclass_IVP_LSNX8S_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVNX8S_I_args, + 1, Iclass_IVP_SVNX8S_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVNX8S_IP_args, + 1, Iclass_IVP_SVNX8S_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVNX8S_X_args, + 1, Iclass_IVP_SVNX8S_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVNX8S_XP_args, + 1, Iclass_IVP_SVNX8S_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSNX8S_I_args, + 1, Iclass_IVP_SSNX8S_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSNX8S_IP_args, + 1, Iclass_IVP_SSNX8S_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSNX8S_X_args, + 1, Iclass_IVP_SSNX8S_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSNX8S_XP_args, + 1, Iclass_IVP_SSNX8S_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SAVNX8S_XP_args, + 1, Iclass_IVP_SAVNX8S_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SANX8S_IP_args, + 1, Iclass_IVP_SANX8S_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVNX8ST_I_args, + 1, Iclass_IVP_SVNX8ST_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVNX8ST_IP_args, + 1, Iclass_IVP_SVNX8ST_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVNX8ST_X_args, + 1, Iclass_IVP_SVNX8ST_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVNX8ST_XP_args, + 1, Iclass_IVP_SVNX8ST_XP_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVBA1_args, + 1, Iclass_IVP_MOVBA1_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVAB1_args, + 1, Iclass_IVP_MOVAB1_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NOTB1_args, + 1, Iclass_IVP_NOTB1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ANDNOTB1_args, + 1, Iclass_IVP_ANDNOTB1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ORNOTB1_args, + 1, Iclass_IVP_ORNOTB1_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT32S2NX24LL_args, + 1, Iclass_IVP_CVT32S2NX24LL_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT32S2NX24LH_args, + 1, Iclass_IVP_CVT32S2NX24LH_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT32S2NX24HL_args, + 1, Iclass_IVP_CVT32S2NX24HL_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT32S2NX24HH_args, + 1, Iclass_IVP_CVT32S2NX24HH_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT64SNX48LL_args, + 1, Iclass_IVP_CVT64SNX48LL_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT64SNX48LH_args, + 1, Iclass_IVP_CVT64SNX48LH_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT64SNX48HL_args, + 1, Iclass_IVP_CVT64SNX48HL_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT64SNX48HH_args, + 1, Iclass_IVP_CVT64SNX48HH_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT16S2NX24L_args, + 1, Iclass_IVP_CVT16S2NX24L_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT16S2NX24H_args, + 1, Iclass_IVP_CVT16S2NX24H_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT32SNX48L_args, + 1, Iclass_IVP_CVT32SNX48L_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT32SNX48H_args, + 1, Iclass_IVP_CVT32SNX48H_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT16U2NX24H_args, + 1, Iclass_IVP_CVT16U2NX24H_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT32UNX48H_args, + 1, Iclass_IVP_CVT32UNX48H_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT64UN_2X96H_args, + 1, Iclass_IVP_CVT64UN_2X96H_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT16U2NX24L_args, + 1, Iclass_IVP_CVT16U2NX24L_stateArgs, 0, 0 }, + { 3, Iclass_IVP_CVT24U2NX16_args, + 1, Iclass_IVP_CVT24U2NX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_CVT24S2NX16_args, + 1, Iclass_IVP_CVT24S2NX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT32S24_args, + 1, Iclass_IVP_CVT32S24_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT24U32_args, + 1, Iclass_IVP_CVT24U32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_CVT24UNX32L_args, + 1, Iclass_IVP_CVT24UNX32L_stateArgs, 0, 0 }, + { 3, Iclass_IVP_CVT24UNX32H_args, + 1, Iclass_IVP_CVT24UNX32H_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT32UNX48L_args, + 1, Iclass_IVP_CVT32UNX48L_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT48UNX32L_args, + 1, Iclass_IVP_CVT48UNX32L_stateArgs, 0, 0 }, + { 3, Iclass_IVP_CVT48UNX32_args, + 1, Iclass_IVP_CVT48UNX32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT48SNX32L_args, + 1, Iclass_IVP_CVT48SNX32L_stateArgs, 0, 0 }, + { 3, Iclass_IVP_CVT48SNX32_args, + 1, Iclass_IVP_CVT48SNX32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT64S48_args, + 1, Iclass_IVP_CVT64S48_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT48U64_args, + 1, Iclass_IVP_CVT48U64_stateArgs, 0, 0 }, + { 3, Iclass_IVP_CVT48UN_2X64L_args, + 1, Iclass_IVP_CVT48UN_2X64L_stateArgs, 0, 0 }, + { 3, Iclass_IVP_CVT48UN_2X64H_args, + 1, Iclass_IVP_CVT48UN_2X64H_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT64UN_2X96L_args, + 1, Iclass_IVP_CVT64UN_2X96L_stateArgs, 0, 0 }, + { 3, Iclass_IVP_CVT96UN_2X64_args, + 1, Iclass_IVP_CVT96UN_2X64_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT96U64_args, + 1, Iclass_IVP_CVT96U64_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT64U96_args, + 1, Iclass_IVP_CVT64U96_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LB2N_I_args, + 1, Iclass_IVP_LB2N_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LB2N_IP_args, + 1, Iclass_IVP_LB2N_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SB2N_I_args, + 1, Iclass_IVP_SB2N_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SB2N_IP_args, + 1, Iclass_IVP_SB2N_IP_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LTR2N_args, + 1, Iclass_IVP_LTR2N_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LTR2NI_args, + 1, Iclass_IVP_LTR2NI_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVN_2X16U_I_args, + 1, Iclass_IVP_LVN_2X16U_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVN_2X16U_IP_args, + 1, Iclass_IVP_LVN_2X16U_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVN_2X16U_X_args, + 1, Iclass_IVP_LVN_2X16U_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVN_2X16U_XP_args, + 1, Iclass_IVP_LVN_2X16U_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVN_2X16UT_I_args, + 1, Iclass_IVP_LVN_2X16UT_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVN_2X16UT_IP_args, + 1, Iclass_IVP_LVN_2X16UT_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVN_2X16UT_X_args, + 1, Iclass_IVP_LVN_2X16UT_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVN_2X16UT_XP_args, + 1, Iclass_IVP_LVN_2X16UT_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVN_2X16S_I_args, + 1, Iclass_IVP_LVN_2X16S_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVN_2X16S_IP_args, + 1, Iclass_IVP_LVN_2X16S_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVN_2X16S_X_args, + 1, Iclass_IVP_LVN_2X16S_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVN_2X16S_XP_args, + 1, Iclass_IVP_LVN_2X16S_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVN_2X16ST_I_args, + 1, Iclass_IVP_LVN_2X16ST_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVN_2X16ST_IP_args, + 1, Iclass_IVP_LVN_2X16ST_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVN_2X16ST_X_args, + 1, Iclass_IVP_LVN_2X16ST_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVN_2X16ST_XP_args, + 1, Iclass_IVP_LVN_2X16ST_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVN_2X16U_I_args, + 1, Iclass_IVP_SVN_2X16U_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVN_2X16UT_I_args, + 1, Iclass_IVP_SVN_2X16UT_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVN_2X16U_IP_args, + 1, Iclass_IVP_SVN_2X16U_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVN_2X16UT_IP_args, + 1, Iclass_IVP_SVN_2X16UT_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVN_2X16U_X_args, + 1, Iclass_IVP_SVN_2X16U_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVN_2X16UT_X_args, + 1, Iclass_IVP_SVN_2X16UT_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVN_2X16U_XP_args, + 1, Iclass_IVP_SVN_2X16U_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVN_2X16UT_XP_args, + 1, Iclass_IVP_SVN_2X16UT_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVN_2X16S_I_args, + 1, Iclass_IVP_SVN_2X16S_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVN_2X16ST_I_args, + 1, Iclass_IVP_SVN_2X16ST_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVN_2X16S_IP_args, + 1, Iclass_IVP_SVN_2X16S_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVN_2X16ST_IP_args, + 1, Iclass_IVP_SVN_2X16ST_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVN_2X16S_X_args, + 1, Iclass_IVP_SVN_2X16S_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVN_2X16ST_X_args, + 1, Iclass_IVP_SVN_2X16ST_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVN_2X16S_XP_args, + 1, Iclass_IVP_SVN_2X16S_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVN_2X16ST_XP_args, + 1, Iclass_IVP_SVN_2X16ST_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LAN_2X16S_IP_args, + 1, Iclass_IVP_LAN_2X16S_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LAN_2X16U_IP_args, + 1, Iclass_IVP_LAN_2X16U_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LAN_2X16U_XP_args, + 1, Iclass_IVP_LAN_2X16U_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LAN_2X16S_XP_args, + 1, Iclass_IVP_LAN_2X16S_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SAN_2X16U_IP_args, + 1, Iclass_IVP_SAN_2X16U_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SAN_2X16S_IP_args, + 1, Iclass_IVP_SAN_2X16S_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LAVN_2X16S_XP_args, + 1, Iclass_IVP_LAVN_2X16S_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LAVN_2X16U_XP_args, + 1, Iclass_IVP_LAVN_2X16U_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SAVN_2X16U_XP_args, + 1, Iclass_IVP_SAVN_2X16U_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SAVN_2X16S_XP_args, + 1, Iclass_IVP_SAVN_2X16S_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSN_2X16S_I_args, + 1, Iclass_IVP_LSN_2X16S_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSN_2X16S_IP_args, + 1, Iclass_IVP_LSN_2X16S_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSN_2X16S_X_args, + 1, Iclass_IVP_LSN_2X16S_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSN_2X16S_XP_args, + 1, Iclass_IVP_LSN_2X16S_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSN_2X16S_I_args, + 1, Iclass_IVP_SSN_2X16S_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSN_2X16S_IP_args, + 1, Iclass_IVP_SSN_2X16S_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSN_2X16S_X_args, + 1, Iclass_IVP_SSN_2X16S_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSN_2X16S_XP_args, + 1, Iclass_IVP_SSN_2X16S_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSN_2X32_I_args, + 1, Iclass_IVP_LSN_2X32_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSN_2X32_IP_args, + 1, Iclass_IVP_LSN_2X32_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSN_2X32_X_args, + 1, Iclass_IVP_LSN_2X32_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSN_2X32_XP_args, + 1, Iclass_IVP_LSN_2X32_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSN_2X32_I_args, + 1, Iclass_IVP_SSN_2X32_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSN_2X32_IP_args, + 1, Iclass_IVP_SSN_2X32_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSN_2X32_X_args, + 1, Iclass_IVP_SSN_2X32_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSN_2X32_XP_args, + 1, Iclass_IVP_SSN_2X32_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMAXUNX16_args, + 1, Iclass_IVP_BMAXUNX16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMINUNX16_args, + 1, Iclass_IVP_BMINUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RBMINUNX16_args, + 1, Iclass_IVP_RBMINUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RBMAXUNX16_args, + 1, Iclass_IVP_RBMAXUNX16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMAX2NX8_args, + 1, Iclass_IVP_BMAX2NX8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMIN2NX8_args, + 1, Iclass_IVP_BMIN2NX8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMAXU2NX8_args, + 1, Iclass_IVP_BMAXU2NX8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMINU2NX8_args, + 1, Iclass_IVP_BMINU2NX8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMAXN_2X32_args, + 1, Iclass_IVP_BMAXN_2X32_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMINN_2X32_args, + 1, Iclass_IVP_BMINN_2X32_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMAXUN_2X32_args, + 1, Iclass_IVP_BMAXUN_2X32_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMINUN_2X32_args, + 1, Iclass_IVP_BMINUN_2X32_stateArgs, 0, 0 }, + { 4, Iclass_IVP_ADDN_2X32T_args, + 1, Iclass_IVP_ADDN_2X32T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SUBN_2X32T_args, + 1, Iclass_IVP_SUBN_2X32T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADD2NX8_args, + 1, Iclass_IVP_ADD2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUB2NX8_args, + 1, Iclass_IVP_SUB2NX8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NEG2NX8_args, + 1, Iclass_IVP_NEG2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MIN2NX8_args, + 1, Iclass_IVP_MIN2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MINU2NX8_args, + 1, Iclass_IVP_MINU2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MAX2NX8_args, + 1, Iclass_IVP_MAX2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MAXU2NX8_args, + 1, Iclass_IVP_MAXU2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LT2NX8_args, + 1, Iclass_IVP_LT2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LE2NX8_args, + 1, Iclass_IVP_LE2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_EQ2NX8_args, + 1, Iclass_IVP_EQ2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_NEQ2NX8_args, + 1, Iclass_IVP_NEQ2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LTU2NX8_args, + 1, Iclass_IVP_LTU2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LEU2NX8_args, + 1, Iclass_IVP_LEU2NX8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_ADD2NX8T_args, + 1, Iclass_IVP_ADD2NX8T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SUB2NX8T_args, + 1, Iclass_IVP_SUB2NX8T_stateArgs, 0, 0 }, + { 5, Iclass_IVP_SELNX16T_args, + 1, Iclass_IVP_SELNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SELN_2X32_args, + 1, Iclass_IVP_SELN_2X32_stateArgs, 0, 0 }, + { 5, Iclass_IVP_SELN_2X32T_args, + 1, Iclass_IVP_SELN_2X32T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SHFLN_2X32_args, + 1, Iclass_IVP_SHFLN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLLIN_2X32_args, + 1, Iclass_IVP_SLLIN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLSIN_2X32_args, + 1, Iclass_IVP_SLSIN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRAIN_2X32_args, + 1, Iclass_IVP_SRAIN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRLIN_2X32_args, + 1, Iclass_IVP_SRLIN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLLN_2X32_args, + 1, Iclass_IVP_SLLN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRLN_2X32_args, + 1, Iclass_IVP_SRLN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLAN_2X32_args, + 1, Iclass_IVP_SLAN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRAN_2X32_args, + 1, Iclass_IVP_SRAN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLSN_2X32_args, + 1, Iclass_IVP_SLSN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRSN_2X32_args, + 1, Iclass_IVP_SRSN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RADDN_2X32_args, + 1, Iclass_IVP_RADDN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RMAXN_2X32_args, + 1, Iclass_IVP_RMAXN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RMINN_2X32_args, + 1, Iclass_IVP_RMINN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RMAXUN_2X32_args, + 1, Iclass_IVP_RMAXUN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RMINUN_2X32_args, + 1, Iclass_IVP_RMINUN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RADDN_2X32T_args, + 1, Iclass_IVP_RADDN_2X32T_stateArgs, 0, 0 }, + { 2, Iclass_IVP_ABS2NX8_args, + 1, Iclass_IVP_ABS2NX8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_ABSN_2X32_args, + 1, Iclass_IVP_ABSN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSGNSNX16_args, + 1, Iclass_IVP_MULSGNSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ROTRI2NX8_args, + 1, Iclass_IVP_ROTRI2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ROTRINX16_args, + 1, Iclass_IVP_ROTRINX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ROTRIN_2X32_args, + 1, Iclass_IVP_ROTRIN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ROTRNX16_args, + 1, Iclass_IVP_ROTRNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ROTRN_2X32_args, + 1, Iclass_IVP_ROTRN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDN_2X32_args, + 1, Iclass_IVP_ADDN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBN_2X32_args, + 1, Iclass_IVP_SUBN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NEGN_2X32_args, + 1, Iclass_IVP_NEGN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MINN_2X32_args, + 1, Iclass_IVP_MINN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MINUN_2X32_args, + 1, Iclass_IVP_MINUN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MAXN_2X32_args, + 1, Iclass_IVP_MAXN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MAXUN_2X32_args, + 1, Iclass_IVP_MAXUN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSGNN_2X32_args, + 1, Iclass_IVP_MULSGNN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NSAN_2X32_args, + 1, Iclass_IVP_NSAN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NSAUN_2X32_args, + 1, Iclass_IVP_NSAUN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LTN_2X32_args, + 1, Iclass_IVP_LTN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LEN_2X32_args, + 1, Iclass_IVP_LEN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_EQN_2X32_args, + 1, Iclass_IVP_EQN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_NEQN_2X32_args, + 1, Iclass_IVP_NEQN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LTUN_2X32_args, + 1, Iclass_IVP_LTUN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LEUN_2X32_args, + 1, Iclass_IVP_LEUN_2X32_stateArgs, 0, 0 }, + { 5, Iclass_IVP_LAT2NX8_XP_args, + 1, Iclass_IVP_LAT2NX8_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUU2NX8_args, + 1, Iclass_IVP_MULUU2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUA2NX8_args, + 1, Iclass_IVP_MULUUA2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUS2NX8_args, + 1, Iclass_IVP_MULUS2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSA2NX8_args, + 1, Iclass_IVP_MULUSA2NX8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULI2NX8X16_args, + 1, Iclass_IVP_MULI2NX8X16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULAI2NX8X16_args, + 1, Iclass_IVP_MULAI2NX8X16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUSI2NX8X16_args, + 1, Iclass_IVP_MULUSI2NX8X16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUSAI2NX8X16_args, + 1, Iclass_IVP_MULUSAI2NX8X16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULI2NR8X16_args, + 1, Iclass_IVP_MULI2NR8X16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULAI2NR8X16_args, + 1, Iclass_IVP_MULAI2NR8X16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUSI2NR8X16_args, + 1, Iclass_IVP_MULUSI2NR8X16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUSAI2NR8X16_args, + 1, Iclass_IVP_MULUSAI2NR8X16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSA2N8XR16_args, + 1, Iclass_IVP_MULUSA2N8XR16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUS2N8XR16_args, + 1, Iclass_IVP_MULUS2N8XR16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULA2N8XR16_args, + 1, Iclass_IVP_MULA2N8XR16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MUL2N8XR16_args, + 1, Iclass_IVP_MUL2N8XR16_stateArgs, 0, 0 }, + { 5, Iclass_IVP_DSEL2NX8I_args, + 1, Iclass_IVP_DSEL2NX8I_stateArgs, 0, 0 }, + { 5, Iclass_IVP_DSEL2NX8I_H_args, + 1, Iclass_IVP_DSEL2NX8I_H_stateArgs, 0, 0 }, + { 5, Iclass_IVP_DSELNX16_args, + 1, Iclass_IVP_DSELNX16_stateArgs, 0, 0 }, + { 6, Iclass_IVP_DSELNX16T_args, + 1, Iclass_IVP_DSELNX16T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_INJBI2NX8_args, + 1, Iclass_IVP_INJBI2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_EXTBI2NX8_args, + 1, Iclass_IVP_EXTBI2NX8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVVA32_args, + 1, Iclass_IVP_MOVVA32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVAV32_args, + 1, Iclass_IVP_MOVAV32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVWW_args, + 1, Iclass_IVP_MOVWW_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LS2NX8_I_args, + 1, Iclass_IVP_LS2NX8_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LS2NX8_IP_args, + 1, Iclass_IVP_LS2NX8_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LS2NX8_X_args, + 1, Iclass_IVP_LS2NX8_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LS2NX8_XP_args, + 1, Iclass_IVP_LS2NX8_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SS2NX8_I_args, + 1, Iclass_IVP_SS2NX8_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SS2NX8_IP_args, + 1, Iclass_IVP_SS2NX8_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SS2NX8_X_args, + 1, Iclass_IVP_SS2NX8_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SS2NX8_XP_args, + 1, Iclass_IVP_SS2NX8_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LANX8S_XP_args, + 1, Iclass_IVP_LANX8S_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LANX8U_XP_args, + 1, Iclass_IVP_LANX8U_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LA2NX8_XP_args, + 1, Iclass_IVP_LA2NX8_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ABSSUBU2NX8_args, + 1, Iclass_IVP_ABSSUBU2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ABSSUB2NX8_args, + 1, Iclass_IVP_ABSSUB2NX8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVVINT8_args, + 1, Iclass_IVP_MOVVINT8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVVA8_args, + 1, Iclass_IVP_MOVVA8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVAVU8_args, + 1, Iclass_IVP_MOVAVU8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLLI2NX8_args, + 1, Iclass_IVP_SLLI2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRAI2NX8_args, + 1, Iclass_IVP_SRAI2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRLI2NX8_args, + 1, Iclass_IVP_SRLI2NX8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_PACKL2NX24_args, + 1, Iclass_IVP_PACKL2NX24_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVR2NX24_args, + 1, Iclass_IVP_PACKVR2NX24_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRU2NX24_args, + 1, Iclass_IVP_PACKVRU2NX24_stateArgs, 0, 0 }, + { 2, Iclass_IVP_PACKLNX48_args, + 1, Iclass_IVP_PACKLNX48_stateArgs, 0, 0 }, + { 2, Iclass_IVP_PACKL2NX24_1_args, + 1, Iclass_IVP_PACKL2NX24_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVR2NX24_0_args, + 1, Iclass_IVP_PACKVR2NX24_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVR2NX24_1_args, + 1, Iclass_IVP_PACKVR2NX24_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRU2NX24_0_args, + 1, Iclass_IVP_PACKVRU2NX24_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRU2NX24_1_args, + 1, Iclass_IVP_PACKVRU2NX24_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNR2NX24_0_args, + 1, Iclass_IVP_PACKVRNR2NX24_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNR2NX24_1_args, + 1, Iclass_IVP_PACKVRNR2NX24_1_stateArgs, 0, 0 }, + { 2, Iclass_IVP_PACKMNX48_args, + 1, Iclass_IVP_PACKMNX48_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNX48_args, + 1, Iclass_IVP_PACKVRNX48_stateArgs, 0, 0 }, + { 2, Iclass_IVP_UNPKS2NX8_0_args, + 1, Iclass_IVP_UNPKS2NX8_0_stateArgs, 0, 0 }, + { 2, Iclass_IVP_UNPKS2NX8_1_args, + 1, Iclass_IVP_UNPKS2NX8_1_stateArgs, 0, 0 }, + { 2, Iclass_IVP_UNPKSNX16_L_args, + 1, Iclass_IVP_UNPKSNX16_L_stateArgs, 0, 0 }, + { 2, Iclass_IVP_UNPKSNX16_H_args, + 1, Iclass_IVP_UNPKSNX16_H_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SEL2NX8I_args, + 1, Iclass_IVP_SEL2NX8I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SEL2NX8I_S0_args, + 1, Iclass_IVP_SEL2NX8I_S0_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SEL2NX8I_S2_args, + 1, Iclass_IVP_SEL2NX8I_S2_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SEL2NX8I_S4_args, + 1, Iclass_IVP_SEL2NX8I_S4_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SHFL2NX8I_args, + 1, Iclass_IVP_SHFL2NX8I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SHFL2NX8I_S0_args, + 1, Iclass_IVP_SHFL2NX8I_S0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SHFL2NX8I_S2_args, + 1, Iclass_IVP_SHFL2NX8I_S2_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SHFL2NX8I_S4_args, + 1, Iclass_IVP_SHFL2NX8I_S4_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SEL2NX8_args, + 1, Iclass_IVP_SEL2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SHFL2NX8_args, + 1, Iclass_IVP_SHFL2NX8_stateArgs, 0, 0 }, + { 5, Iclass_IVP_SEL2NX8T_args, + 1, Iclass_IVP_SEL2NX8T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SQZN_args, + 1, Iclass_IVP_SQZN_stateArgs, 0, 0 }, + { 3, Iclass_IVP_UNSQZN_args, + 1, Iclass_IVP_UNSQZN_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULNX16_args, + 1, Iclass_IVP_MULNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULANX16_args, + 1, Iclass_IVP_MULANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUNX16_args, + 1, Iclass_IVP_MULUUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUANX16_args, + 1, Iclass_IVP_MULUUANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSNX16_args, + 1, Iclass_IVP_MULUSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSANX16_args, + 1, Iclass_IVP_MULUSANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MUL2NX8_args, + 1, Iclass_IVP_MUL2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULA2NX8_args, + 1, Iclass_IVP_MULA2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDW2NX8_args, + 1, Iclass_IVP_ADDW2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWA2NX8_args, + 1, Iclass_IVP_ADDWA2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWS2NX8_args, + 1, Iclass_IVP_ADDWS2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWU2NX8_args, + 1, Iclass_IVP_ADDWU2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWUA2NX8_args, + 1, Iclass_IVP_ADDWUA2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWUS2NX8_args, + 1, Iclass_IVP_ADDWUS2NX8_stateArgs, 0, 0 }, + { 5, Iclass_IVP_DIVN_2X32X16S_4STEP0_args, + 1, Iclass_IVP_DIVN_2X32X16S_4STEP0_stateArgs, 0, 0 }, + { 4, Iclass_IVP_DIVN_2X32X16S_4STEP_args, + 1, Iclass_IVP_DIVN_2X32X16S_4STEP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_DIVN_2X32X16S_4STEPN_args, + 1, Iclass_IVP_DIVN_2X32X16S_4STEPN_stateArgs, 0, 0 }, + { 5, Iclass_IVP_DIVN_2X32X16U_4STEP0_args, + 1, Iclass_IVP_DIVN_2X32X16U_4STEP0_stateArgs, 0, 0 }, + { 4, Iclass_IVP_DIVN_2X32X16U_4STEP_args, + 1, Iclass_IVP_DIVN_2X32X16U_4STEP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_DIVN_2X32X16U_4STEPN_args, + 1, Iclass_IVP_DIVN_2X32X16U_4STEPN_stateArgs, 0, 0 }, + { 5, Iclass_IVP_DIVNX16S_4STEP0_args, + 1, Iclass_IVP_DIVNX16S_4STEP0_stateArgs, 0, 0 }, + { 4, Iclass_IVP_DIVNX16S_4STEP_args, + 1, Iclass_IVP_DIVNX16S_4STEP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_DIVNX16S_4STEPN_args, + 1, Iclass_IVP_DIVNX16S_4STEPN_stateArgs, 0, 0 }, + { 5, Iclass_IVP_DIVNX16U_4STEP0_args, + 1, Iclass_IVP_DIVNX16U_4STEP0_stateArgs, 0, 0 }, + { 4, Iclass_IVP_DIVNX16U_4STEP_args, + 1, Iclass_IVP_DIVNX16U_4STEP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_DIVNX16U_4STEPN_args, + 1, Iclass_IVP_DIVNX16U_4STEPN_stateArgs, 0, 0 }, + { 5, Iclass_IVP_DIVNX16SQ_4STEP0_args, + 1, Iclass_IVP_DIVNX16SQ_4STEP0_stateArgs, 0, 0 }, + { 5, Iclass_IVP_DIVNX16Q_4STEP0_args, + 1, Iclass_IVP_DIVNX16Q_4STEP0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSNX16_args, + 1, Iclass_IVP_MULSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUSNX16_args, + 1, Iclass_IVP_MULUUSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSSNX16_args, + 1, Iclass_IVP_MULUSSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULN_2X16X32_0_args, + 1, Iclass_IVP_MULN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUN_2X16X32_0_args, + 1, Iclass_IVP_MULUUN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSN_2X16X32_0_args, + 1, Iclass_IVP_MULUSN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSUN_2X16X32_0_args, + 1, Iclass_IVP_MULSUN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULN_2X16X32_1_args, + 1, Iclass_IVP_MULN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUN_2X16X32_1_args, + 1, Iclass_IVP_MULUUN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSN_2X16X32_1_args, + 1, Iclass_IVP_MULUSN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSUN_2X16X32_1_args, + 1, Iclass_IVP_MULSUN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULHN_2X16X32_1_args, + 1, Iclass_IVP_MULHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUHN_2X16X32_1_args, + 1, Iclass_IVP_MULUUHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSHN_2X16X32_1_args, + 1, Iclass_IVP_MULUSHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSUHN_2X16X32_1_args, + 1, Iclass_IVP_MULSUHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULAN_2X16X32_0_args, + 1, Iclass_IVP_MULAN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUAN_2X16X32_0_args, + 1, Iclass_IVP_MULUUAN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSAN_2X16X32_0_args, + 1, Iclass_IVP_MULUSAN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSUAN_2X16X32_0_args, + 1, Iclass_IVP_MULSUAN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULAHN_2X16X32_1_args, + 1, Iclass_IVP_MULAHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUAHN_2X16X32_1_args, + 1, Iclass_IVP_MULUUAHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSAHN_2X16X32_1_args, + 1, Iclass_IVP_MULUSAHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSUAHN_2X16X32_1_args, + 1, Iclass_IVP_MULSUAHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULAN_2X16X32_1_args, + 1, Iclass_IVP_MULAN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUAN_2X16X32_1_args, + 1, Iclass_IVP_MULUUAN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSAN_2X16X32_1_args, + 1, Iclass_IVP_MULUSAN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSUAN_2X16X32_1_args, + 1, Iclass_IVP_MULSUAN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSHN_2X16X32_1_args, + 1, Iclass_IVP_MULSHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUSHN_2X16X32_1_args, + 1, Iclass_IVP_MULUUSHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSSHN_2X16X32_1_args, + 1, Iclass_IVP_MULUSSHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSUSHN_2X16X32_1_args, + 1, Iclass_IVP_MULSUSHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSN_2X16X32_0_args, + 1, Iclass_IVP_MULSN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUSN_2X16X32_0_args, + 1, Iclass_IVP_MULUUSN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSSN_2X16X32_0_args, + 1, Iclass_IVP_MULUSSN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSUSN_2X16X32_0_args, + 1, Iclass_IVP_MULSUSN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSN_2X16X32_1_args, + 1, Iclass_IVP_MULSN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUSN_2X16X32_1_args, + 1, Iclass_IVP_MULUUSN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSSN_2X16X32_1_args, + 1, Iclass_IVP_MULUSSN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSUSN_2X16X32_1_args, + 1, Iclass_IVP_MULSUSN_2X16X32_1_stateArgs, 0, 0 }, + { 2, Iclass_IVP_PACKLN_2X96_args, + 1, Iclass_IVP_PACKLN_2X96_stateArgs, 0, 0 }, + { 2, Iclass_IVP_PACKHN_2X64W_args, + 1, Iclass_IVP_PACKHN_2X64W_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRN_2X64W_args, + 1, Iclass_IVP_PACKVRN_2X64W_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNRN_2X64W_args, + 1, Iclass_IVP_PACKVRNRN_2X64W_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNX48_0_args, + 1, Iclass_IVP_PACKVRNX48_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNX48_1_args, + 1, Iclass_IVP_PACKVRNX48_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNRNX48_0_args, + 1, Iclass_IVP_PACKVRNRNX48_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNRNX48_1_args, + 1, Iclass_IVP_PACKVRNRNX48_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNRNX48_args, + 1, Iclass_IVP_PACKVRNRNX48_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNR2NX24_args, + 1, Iclass_IVP_PACKVRNR2NX24_stateArgs, 0, 0 }, + { 4, Iclass_IVP_L2A4NX8_IP_args, + 1, Iclass_IVP_L2A4NX8_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_L2AU2NX8_IP_args, + 1, Iclass_IVP_L2AU2NX8_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_L2U2NX8_XP_args, + 1, Iclass_IVP_L2U2NX8_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_AVGU2NX8_args, + 1, Iclass_IVP_AVGU2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_AVGRU2NX8_args, + 1, Iclass_IVP_AVGRU2NX8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RADD2NX8_args, + 1, Iclass_IVP_RADD2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RADD2NX8T_args, + 1, Iclass_IVP_RADD2NX8T_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RADDUNX16_args, + 1, Iclass_IVP_RADDUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RADDUNX16T_args, + 1, Iclass_IVP_RADDUNX16T_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RADDU2NX8_args, + 1, Iclass_IVP_RADDU2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RADDU2NX8T_args, + 1, Iclass_IVP_RADDU2NX8T_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LTRS2N_args, + 1, Iclass_IVP_LTRS2N_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LTRSN_args, + 1, Iclass_IVP_LTRSN_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LTRSN_2_args, + 1, Iclass_IVP_LTRSN_2_stateArgs, 0, 0 }, + { 1, Iclass_IVP_SEQ2NX8_args, + 1, Iclass_IVP_SEQ2NX8_stateArgs, 0, 0 }, + { 1, Iclass_IVP_SEQN_2X32_args, + 1, Iclass_IVP_SEQN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_EXTRN_2X32_args, + 1, Iclass_IVP_EXTRN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_UNPKU2NX8_0_args, + 1, Iclass_IVP_UNPKU2NX8_0_stateArgs, 0, 0 }, + { 2, Iclass_IVP_UNPKU2NX8_1_args, + 1, Iclass_IVP_UNPKU2NX8_1_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BADDNORMNX16_args, + 1, Iclass_IVP_BADDNORMNX16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BSUBNORMNX16_args, + 1, Iclass_IVP_BSUBNORMNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RADDSNX16_args, + 1, Iclass_IVP_RADDSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RADDSNX16T_args, + 1, Iclass_IVP_RADDSNX16T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ORNOTB_args, + 1, Iclass_IVP_ORNOTB_stateArgs, 0, 0 }, + { 3, Iclass_IVP_EXTR2NX8_args, + 1, Iclass_IVP_EXTR2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_EXTRVRN_2X32_args, + 1, Iclass_IVP_EXTRVRN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVAV8_args, + 1, Iclass_IVP_MOVAV8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULPN16XR16_args, + 1, Iclass_IVP_MULPN16XR16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULPAN16XR16_args, + 1, Iclass_IVP_MULPAN16XR16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUSPN16XR16_args, + 1, Iclass_IVP_MULUSPN16XR16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUSPAN16XR16_args, + 1, Iclass_IVP_MULUSPAN16XR16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULP2N8XR16_args, + 1, Iclass_IVP_MULP2N8XR16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULPA2N8XR16_args, + 1, Iclass_IVP_MULPA2N8XR16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUSP2N8XR16_args, + 1, Iclass_IVP_MULUSP2N8XR16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUSPA2N8XR16_args, + 1, Iclass_IVP_MULUSPA2N8XR16_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULPNX16_args, + 1, Iclass_IVP_MULPNX16_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULPANX16_args, + 1, Iclass_IVP_MULPANX16_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULUSPNX16_args, + 1, Iclass_IVP_MULUSPNX16_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULUSPANX16_args, + 1, Iclass_IVP_MULUSPANX16_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULUUPNX16_args, + 1, Iclass_IVP_MULUUPNX16_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULUUPANX16_args, + 1, Iclass_IVP_MULUUPANX16_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULP2NX8_args, + 1, Iclass_IVP_MULP2NX8_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULPA2NX8_args, + 1, Iclass_IVP_MULPA2NX8_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULUSP2NX8_args, + 1, Iclass_IVP_MULUSP2NX8_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULUSPA2NX8_args, + 1, Iclass_IVP_MULUSPA2NX8_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULUUP2NX8_args, + 1, Iclass_IVP_MULUUP2NX8_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULUUPA2NX8_args, + 1, Iclass_IVP_MULUUPA2NX8_stateArgs, 0, 0 }, + { 6, Iclass_IVP_MULPI2NR8X16_args, + 1, Iclass_IVP_MULPI2NR8X16_stateArgs, 0, 0 }, + { 6, Iclass_IVP_MULPAI2NR8X16_args, + 1, Iclass_IVP_MULPAI2NR8X16_stateArgs, 0, 0 }, + { 6, Iclass_IVP_MULUSPI2NR8X16_args, + 1, Iclass_IVP_MULUSPI2NR8X16_stateArgs, 0, 0 }, + { 6, Iclass_IVP_MULUSPAI2NR8X16_args, + 1, Iclass_IVP_MULUSPAI2NR8X16_stateArgs, 0, 0 }, + { 6, Iclass_IVP_MULQ2N8XR8_args, + 1, Iclass_IVP_MULQ2N8XR8_stateArgs, 0, 0 }, + { 6, Iclass_IVP_MULQA2N8XR8_args, + 1, Iclass_IVP_MULQA2N8XR8_stateArgs, 0, 0 }, + { 6, Iclass_IVP_MULUSQ2N8XR8_args, + 1, Iclass_IVP_MULUSQ2N8XR8_stateArgs, 0, 0 }, + { 6, Iclass_IVP_MULUSQA2N8XR8_args, + 1, Iclass_IVP_MULUSQA2N8XR8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MUL4T2N8XR8_args, + 1, Iclass_IVP_MUL4T2N8XR8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MUL4TA2N8XR8_args, + 1, Iclass_IVP_MUL4TA2N8XR8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUS4T2N8XR8_args, + 1, Iclass_IVP_MULUS4T2N8XR8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUS4TA2N8XR8_args, + 1, Iclass_IVP_MULUS4TA2N8XR8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWNX16_args, + 1, Iclass_IVP_ADDWNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWANX16_args, + 1, Iclass_IVP_ADDWANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWSNX16_args, + 1, Iclass_IVP_ADDWSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWUNX16_args, + 1, Iclass_IVP_ADDWUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWUANX16_args, + 1, Iclass_IVP_ADDWUANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWUSNX16_args, + 1, Iclass_IVP_ADDWUSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBWNX16_args, + 1, Iclass_IVP_SUBWNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBWANX16_args, + 1, Iclass_IVP_SUBWANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBWUNX16_args, + 1, Iclass_IVP_SUBWUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBWUANX16_args, + 1, Iclass_IVP_SUBWUANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBW2NX8_args, + 1, Iclass_IVP_SUBW2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBWA2NX8_args, + 1, Iclass_IVP_SUBWA2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBWU2NX8_args, + 1, Iclass_IVP_SUBWU2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBWUA2NX8_args, + 1, Iclass_IVP_SUBWUA2NX8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RANDB2N_args, + 1, Iclass_IVP_RANDB2N_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RORB2N_args, + 1, Iclass_IVP_RORB2N_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RANDBN_args, + 1, Iclass_IVP_RANDBN_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RORBN_args, + 1, Iclass_IVP_RORBN_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RANDBN_2_args, + 1, Iclass_IVP_RANDBN_2_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RORBN_2_args, + 1, Iclass_IVP_RORBN_2_stateArgs, 0, 0 }, + { 3, Iclass_IVP_AVGNX16_args, + 1, Iclass_IVP_AVGNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_AVGUNX16_args, + 1, Iclass_IVP_AVGUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_AVG2NX8_args, + 1, Iclass_IVP_AVG2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_AVGR2NX8_args, + 1, Iclass_IVP_AVGR2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_AVGRNX16_args, + 1, Iclass_IVP_AVGRNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_AVGRUNX16_args, + 1, Iclass_IVP_AVGRUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_GATHERANX8U_args, + 1, Iclass_IVP_GATHERANX8U_stateArgs, 0, 0 }, + { 3, Iclass_IVP_GATHERANX16_args, + 1, Iclass_IVP_GATHERANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_GATHERAN_2X32_args, + 1, Iclass_IVP_GATHERAN_2X32_stateArgs, 0, 0 }, + { 4, Iclass_IVP_GATHERANX8UT_args, + 1, Iclass_IVP_GATHERANX8UT_stateArgs, 0, 0 }, + { 4, Iclass_IVP_GATHERANX16T_args, + 1, Iclass_IVP_GATHERANX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_GATHERAN_2X32T_args, + 1, Iclass_IVP_GATHERAN_2X32T_stateArgs, 0, 0 }, + { 2, Iclass_IVP_GATHERDNX16_args, + 1, Iclass_IVP_GATHERDNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_GATHERDNX8S_args, + 1, Iclass_IVP_GATHERDNX8S_stateArgs, 0, 0 }, + { 2, Iclass_IVP_GATHERD2NX8_L_args, + 1, Iclass_IVP_GATHERD2NX8_L_stateArgs, 0, 0 }, + { 2, Iclass_IVP_GATHERD2NX8_H_args, + 1, Iclass_IVP_GATHERD2NX8_H_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVGATHERD_args, + 1, Iclass_IVP_MOVGATHERD_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SCATTERNX8U_args, + 1, Iclass_IVP_SCATTERNX8U_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SCATTER2NX8_L_args, + 1, Iclass_IVP_SCATTER2NX8_L_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SCATTER2NX8_H_args, + 1, Iclass_IVP_SCATTER2NX8_H_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SCATTERNX16_args, + 1, Iclass_IVP_SCATTERNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SCATTERN_2X32_args, + 1, Iclass_IVP_SCATTERN_2X32_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SCATTERNX8UT_args, + 1, Iclass_IVP_SCATTERNX8UT_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SCATTER2NX8T_L_args, + 1, Iclass_IVP_SCATTER2NX8T_L_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SCATTER2NX8T_H_args, + 1, Iclass_IVP_SCATTER2NX8T_H_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SCATTERNX16T_args, + 1, Iclass_IVP_SCATTERNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SCATTERN_2X32T_args, + 1, Iclass_IVP_SCATTERN_2X32T_stateArgs, 0, 0 }, + { 0, 0 /* IVP_SCATTERW */, + 0, 0, 0, 0 }, + { 4, Iclass_IVP_COUNTEQZ4NX8_args, + 1, Iclass_IVP_COUNTEQZ4NX8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_COUNTEQ4NX8_args, + 1, Iclass_IVP_COUNTEQ4NX8_stateArgs, 0, 0 }, + { 6, Iclass_IVP_COUNTEQMZ4NX8_args, + 1, Iclass_IVP_COUNTEQMZ4NX8_stateArgs, 0, 0 }, + { 6, Iclass_IVP_COUNTEQM4NX8_args, + 1, Iclass_IVP_COUNTEQM4NX8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_COUNTLEZ4NX8_args, + 1, Iclass_IVP_COUNTLEZ4NX8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_COUNTLE4NX8_args, + 1, Iclass_IVP_COUNTLE4NX8_stateArgs, 0, 0 }, + { 6, Iclass_IVP_COUNTLEMZ4NX8_args, + 1, Iclass_IVP_COUNTLEMZ4NX8_stateArgs, 0, 0 }, + { 6, Iclass_IVP_COUNTLEM4NX8_args, + 1, Iclass_IVP_COUNTLEM4NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSR2NX8_I_args, + 1, Iclass_IVP_LSR2NX8_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSR2NX8_IP_args, + 1, Iclass_IVP_LSR2NX8_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSR2NX8_X_args, + 1, Iclass_IVP_LSR2NX8_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSR2NX8_XP_args, + 1, Iclass_IVP_LSR2NX8_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSRNX16_I_args, + 1, Iclass_IVP_LSRNX16_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSRNX16_IP_args, + 1, Iclass_IVP_LSRNX16_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSRNX16_X_args, + 1, Iclass_IVP_LSRNX16_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSRNX16_XP_args, + 1, Iclass_IVP_LSRNX16_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSRN_2X32_I_args, + 1, Iclass_IVP_LSRN_2X32_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSRN_2X32_IP_args, + 1, Iclass_IVP_LSRN_2X32_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSRN_2X32_X_args, + 1, Iclass_IVP_LSRN_2X32_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSRN_2X32_XP_args, + 1, Iclass_IVP_LSRN_2X32_XP_stateArgs, 0, 0 }, + { 2, Iclass_IVP_ABSNX16_args, + 1, Iclass_IVP_ABSNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_ABSSNX16_args, + 1, Iclass_IVP_ABSSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ABSSUBNX16_args, + 1, Iclass_IVP_ABSSUBNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ABSSUBUNX16_args, + 1, Iclass_IVP_ABSSUBUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ABSSSUBNX16_args, + 1, Iclass_IVP_ABSSSUBNX16_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_threadptr_args, + 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, + { 1, Iclass_wur_threadptr_args, + 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_const16_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32ex_args, + 1, Iclass_xt_iclass_l32ex_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_s32ex_args, + 1, Iclass_xt_iclass_s32ex_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_getex_args, + 1, Iclass_xt_iclass_getex_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_clrex */, + 1, Iclass_xt_iclass_clrex_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_simcall */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32nb_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_memctl_args, + 1, Iclass_xt_iclass_rsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_memctl_args, + 1, Iclass_xt_iclass_wsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_memctl_args, + 1, Iclass_xt_iclass_xsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid0_args, + 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_configid0_args, + 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid1_args, + 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_mpucfg_args, + 3, Iclass_xt_iclass_rsr_mpucfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mpucfg_args, + 3, Iclass_xt_iclass_wsr_mpucfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_gserr_args, + 3, Iclass_xt_iclass_rsr_gserr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_gserr_args, + 3, Iclass_xt_iclass_wsr_gserr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_gserr_args, + 3, Iclass_xt_iclass_xsr_gserr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_salt_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul16_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32h_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 15, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 4, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 5, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 5, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_lddr32_p_args, + 5, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sddr32_p_args, + 4, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_bbool1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbranch_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bmove_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_RSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_WSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_XSR_BR_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_lock_args, + 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cacheadrdis_args, + 4, Iclass_xt_iclass_wsr_cacheadrdis_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cacheadrdis_args, + 3, Iclass_xt_iclass_rsr_cacheadrdis_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cacheadrdis_args, + 4, Iclass_xt_iclass_xsr_cacheadrdis_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rptlb0_args, + 3, Iclass_xt_iclass_rptlb0_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rptlb_args, + 2, Iclass_xt_iclass_rptlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_wptlb_args, + 4, Iclass_xt_iclass_wptlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_mpuenb_args, + 3, Iclass_xt_iclass_rsr_mpuenb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mpuenb_args, + 4, Iclass_xt_iclass_wsr_mpuenb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_mpuenb_args, + 4, Iclass_xt_iclass_xsr_mpuenb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cpenable_args, + 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cpenable_args, + 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cpenable_args, + 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_clamp_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_atomctl_args, + 4, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_atomctl_args, + 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_atomctl_args, + 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_div_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eraccess_args, + 3, Iclass_xt_iclass_rsr_eraccess_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eraccess_args, + 3, Iclass_xt_iclass_wsr_eraccess_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eraccess_args, + 3, Iclass_xt_iclass_xsr_eraccess_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rer_args, + 4, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs }, + { 2, Iclass_xt_iclass_wer_args, + 4, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs }, + { 2, Iclass_xt_iclass_wb15_0_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_1_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_2_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_3_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_4_args, + 0, 0, 0, 0 }, + { 4, Iclass_MTK_AndPOPC_args, + 1, Iclass_MTK_AndPOPC_stateArgs, 0, 0 }, + { 1, Iclass_iq_tie2apb_inq0_pop_args, + 1, Iclass_iq_tie2apb_inq0_pop_stateArgs, 1, Iclass_iq_tie2apb_inq0_pop_intfArgs }, + { 1, Iclass_iq_tie2apb_inq0_is_ready_args, + 0, 0, 1, Iclass_iq_tie2apb_inq0_is_ready_intfArgs }, + { 2, Iclass_iq_tie2apb_inq0_nonblocking_peek_args, + 0, 0, 3, Iclass_iq_tie2apb_inq0_nonblocking_peek_intfArgs }, + { 2, Iclass_iq_tie2apb_inq0_nonblocking_pop_args, + 1, Iclass_iq_tie2apb_inq0_nonblocking_pop_stateArgs, 3, Iclass_iq_tie2apb_inq0_nonblocking_pop_intfArgs }, + { 1, Iclass_iq_tie2apb_inq0_blocking_peek_args, + 0, 0, 3, Iclass_iq_tie2apb_inq0_blocking_peek_intfArgs }, + { 2, Iclass_oq_tie2apb_outq0_push_read_args, + 1, Iclass_oq_tie2apb_outq0_push_read_stateArgs, 1, Iclass_oq_tie2apb_outq0_push_read_intfArgs }, + { 2, Iclass_oq_tie2apb_outq0_push_write_args, + 1, Iclass_oq_tie2apb_outq0_push_write_stateArgs, 1, Iclass_oq_tie2apb_outq0_push_write_intfArgs }, + { 1, Iclass_oq_tie2apb_outq0_is_ready_args, + 0, 0, 1, Iclass_oq_tie2apb_outq0_is_ready_intfArgs }, + { 3, Iclass_oq_tie2apb_outq0_nonblocking_push_read_args, + 1, Iclass_oq_tie2apb_outq0_nonblocking_push_read_stateArgs, 3, Iclass_oq_tie2apb_outq0_nonblocking_push_read_intfArgs }, + { 3, Iclass_oq_tie2apb_outq0_nonblocking_push_write_args, + 1, Iclass_oq_tie2apb_outq0_nonblocking_push_write_stateArgs, 3, Iclass_oq_tie2apb_outq0_nonblocking_push_write_intfArgs }, + { 1, Iclass_rur_apb_pipe_args, + 1, Iclass_rur_apb_pipe_stateArgs, 0, 0 }, + { 1, Iclass_wur_apb_pipe_args, + 1, Iclass_wur_apb_pipe_stateArgs, 0, 0 } +}; + +enum xtensa_iclass_id { + ICLASS_IVP_REPNX16, + ICLASS_IVP_SELSNX16, + ICLASS_IVP_REP2NX8, + ICLASS_IVP_SELS2NX8, + ICLASS_IVP_REPN_2X32, + ICLASS_IVP_SELSN_2X32, + ICLASS_IVP_EXT0IB, + ICLASS_IVP_NOTB, + ICLASS_IVP_ANDB, + ICLASS_IVP_ORB, + ICLASS_IVP_XORB, + ICLASS_IVP_ANDNOTB, + ICLASS_IVP_MB, + ICLASS_IVP_LTRN, + ICLASS_IVP_LTRNI, + ICLASS_IVP_LBN_I, + ICLASS_IVP_LBN_IP, + ICLASS_IVP_SBN_I, + ICLASS_IVP_SBN_IP, + ICLASS_IVP_LSNX16_I, + ICLASS_IVP_LSNX16_IP, + ICLASS_IVP_LSNX16_X, + ICLASS_IVP_LSNX16_XP, + ICLASS_IVP_MOVBRBV, + ICLASS_IVP_MOVBVBR, + ICLASS_IVP_JOINB, + ICLASS_IVP_LTRN_2, + ICLASS_IVP_LTRN_2I, + ICLASS_IVP_LBN_2_I, + ICLASS_IVP_LBN_2_IP, + ICLASS_IVP_SBN_2_I, + ICLASS_IVP_SBN_2_IP, + ICLASS_IVP_LV2NX8_I, + ICLASS_IVP_LV2NX8_IP, + ICLASS_IVP_LV2NX8_X, + ICLASS_IVP_LV2NX8_XP, + ICLASS_IVP_SV2NX8_I, + ICLASS_IVP_SV2NX8_IP, + ICLASS_IVP_SV2NX8_X, + ICLASS_IVP_SV2NX8_XP, + ICLASS_IVP_SSNX16_I, + ICLASS_IVP_SSNX16_IP, + ICLASS_IVP_SSNX16_X, + ICLASS_IVP_SSNX16_XP, + ICLASS_IVP_MOVVA16, + ICLASS_IVP_MOVVV, + ICLASS_IVP_SLLINX16, + ICLASS_IVP_SLSINX16, + ICLASS_IVP_SRAINX16, + ICLASS_IVP_SRLINX16, + ICLASS_IVP_SLLNX16, + ICLASS_IVP_SRLNX16, + ICLASS_IVP_SLANX16, + ICLASS_IVP_SRANX16, + ICLASS_IVP_SLSNX16, + ICLASS_IVP_SRSNX16, + ICLASS_IVP_XOR2NX8, + ICLASS_IVP_AND2NX8, + ICLASS_IVP_OR2NX8, + ICLASS_IVP_NOT2NX8, + ICLASS_IVP_ADDNX16, + ICLASS_IVP_SUBNX16, + ICLASS_IVP_NEGNX16, + ICLASS_IVP_MINNX16, + ICLASS_IVP_MINUNX16, + ICLASS_IVP_MAXNX16, + ICLASS_IVP_MAXUNX16, + ICLASS_IVP_MULSGNNX16, + ICLASS_IVP_NSANX16, + ICLASS_IVP_NSAUNX16, + ICLASS_IVP_LTNX16, + ICLASS_IVP_LENX16, + ICLASS_IVP_EQNX16, + ICLASS_IVP_NEQNX16, + ICLASS_IVP_LTUNX16, + ICLASS_IVP_LEUNX16, + ICLASS_IVP_RADDNX16, + ICLASS_IVP_RMAXNX16, + ICLASS_IVP_RMINNX16, + ICLASS_IVP_RMAXUNX16, + ICLASS_IVP_RMINUNX16, + ICLASS_IVP_RBMINNX16, + ICLASS_IVP_RBMAXNX16, + ICLASS_IVP_BMAXNX16, + ICLASS_IVP_BMINNX16, + ICLASS_IVP_MOV2NX8T, + ICLASS_IVP_MULANX16PACKL, + ICLASS_IVP_MULANX16PACKQ, + ICLASS_IVP_MULSNX16PACKL, + ICLASS_IVP_MULSNX16PACKQ, + ICLASS_IVP_ADDSNX16, + ICLASS_IVP_SUBSNX16, + ICLASS_IVP_NEGSNX16, + ICLASS_IVP_LV2NX8T_I, + ICLASS_IVP_LV2NX8T_IP, + ICLASS_IVP_LV2NX8T_X, + ICLASS_IVP_LV2NX8T_XP, + ICLASS_IVP_SV2NX8T_I, + ICLASS_IVP_SV2NX8T_IP, + ICLASS_IVP_SV2NX8T_X, + ICLASS_IVP_SV2NX8T_XP, + ICLASS_IVP_RADDNX16T, + ICLASS_IVP_RMAXNX16T, + ICLASS_IVP_RMINNX16T, + ICLASS_IVP_RMAXUNX16T, + ICLASS_IVP_RMINUNX16T, + ICLASS_IVP_ADDNX16T, + ICLASS_IVP_SUBNX16T, + ICLASS_IVP_NEGNX16T, + ICLASS_IVP_MAXNX16T, + ICLASS_IVP_MINNX16T, + ICLASS_IVP_MAXUNX16T, + ICLASS_IVP_MINUNX16T, + ICLASS_IVP_MULANX16PACKLT, + ICLASS_IVP_MULANX16PACKQT, + ICLASS_IVP_ADDSNX16T, + ICLASS_IVP_SUBSNX16T, + ICLASS_IVP_NEGSNX16T, + ICLASS_IVP_LALIGN_I, + ICLASS_IVP_LALIGN_IP, + ICLASS_IVP_SALIGN_I, + ICLASS_IVP_SALIGN_IP, + ICLASS_IVP_LA_PP, + ICLASS_IVP_SAPOS_FP, + ICLASS_IVP_MALIGN, + ICLASS_IVP_ZALIGN, + ICLASS_IVP_LA2NX8_IP, + ICLASS_IVP_SA2NX8_IP, + ICLASS_IVP_LAV2NX8_XP, + ICLASS_IVP_SAV2NX8_XP, + ICLASS_IVP_SELNX16, + ICLASS_IVP_SHFLNX16, + ICLASS_IVP_MOVPINT16, + ICLASS_IVP_MOVPA16, + ICLASS_IVP_MULNX16PACKP, + ICLASS_IVP_MULANX16PACKP, + ICLASS_IVP_MULSNX16PACKP, + ICLASS_IVP_MULANX16PACKPT, + ICLASS_IVP_ADDMOD16U, + ICLASS_IVP_LVNX8S_I, + ICLASS_IVP_LVNX8S_IP, + ICLASS_IVP_LVNX8S_X, + ICLASS_IVP_LVNX8S_XP, + ICLASS_IVP_LVNX8U_I, + ICLASS_IVP_LVNX8U_IP, + ICLASS_IVP_LVNX8U_X, + ICLASS_IVP_LVNX8U_XP, + ICLASS_IVP_SVNX8U_I, + ICLASS_IVP_SVNX8U_IP, + ICLASS_IVP_SVNX8U_X, + ICLASS_IVP_SVNX8U_XP, + ICLASS_IVP_LVNX8ST_I, + ICLASS_IVP_LVNX8ST_IP, + ICLASS_IVP_LVNX8ST_X, + ICLASS_IVP_LVNX8ST_XP, + ICLASS_IVP_LVNX8UT_I, + ICLASS_IVP_LVNX8UT_IP, + ICLASS_IVP_LVNX8UT_X, + ICLASS_IVP_LVNX8UT_XP, + ICLASS_IVP_SVNX8UT_I, + ICLASS_IVP_SVNX8UT_IP, + ICLASS_IVP_SVNX8UT_X, + ICLASS_IVP_SVNX8UT_XP, + ICLASS_IVP_LAVNX8S_XP, + ICLASS_IVP_LAVNX8U_XP, + ICLASS_IVP_SAVNX8U_XP, + ICLASS_IVP_LANX8S_IP, + ICLASS_IVP_LANX8U_IP, + ICLASS_IVP_SANX8U_IP, + ICLASS_IVP_EXTRACTBL, + ICLASS_IVP_EXTRACTBH, + ICLASS_IVP_MOVVINT16, + ICLASS_IVP_MOVQINT16, + ICLASS_IVP_MOVQA16, + ICLASS_IVP_MOVVINX16, + ICLASS_IVP_SEQNX16, + ICLASS_IVP_MULNX16PACKL, + ICLASS_IVP_MULNX16PACKQ, + ICLASS_IVP_MOVAV16, + ICLASS_IVP_MOVAVU16, + ICLASS_IVP_EXTRNX16, + ICLASS_IVP_LSNX8S_I, + ICLASS_IVP_LSNX8S_IP, + ICLASS_IVP_LSNX8S_X, + ICLASS_IVP_LSNX8S_XP, + ICLASS_IVP_SVNX8S_I, + ICLASS_IVP_SVNX8S_IP, + ICLASS_IVP_SVNX8S_X, + ICLASS_IVP_SVNX8S_XP, + ICLASS_IVP_SSNX8S_I, + ICLASS_IVP_SSNX8S_IP, + ICLASS_IVP_SSNX8S_X, + ICLASS_IVP_SSNX8S_XP, + ICLASS_IVP_SAVNX8S_XP, + ICLASS_IVP_SANX8S_IP, + ICLASS_IVP_SVNX8ST_I, + ICLASS_IVP_SVNX8ST_IP, + ICLASS_IVP_SVNX8ST_X, + ICLASS_IVP_SVNX8ST_XP, + ICLASS_IVP_MOVBA1, + ICLASS_IVP_MOVAB1, + ICLASS_IVP_NOTB1, + ICLASS_IVP_ANDNOTB1, + ICLASS_IVP_ORNOTB1, + ICLASS_IVP_CVT32S2NX24LL, + ICLASS_IVP_CVT32S2NX24LH, + ICLASS_IVP_CVT32S2NX24HL, + ICLASS_IVP_CVT32S2NX24HH, + ICLASS_IVP_CVT64SNX48LL, + ICLASS_IVP_CVT64SNX48LH, + ICLASS_IVP_CVT64SNX48HL, + ICLASS_IVP_CVT64SNX48HH, + ICLASS_IVP_CVT16S2NX24L, + ICLASS_IVP_CVT16S2NX24H, + ICLASS_IVP_CVT32SNX48L, + ICLASS_IVP_CVT32SNX48H, + ICLASS_IVP_CVT16U2NX24H, + ICLASS_IVP_CVT32UNX48H, + ICLASS_IVP_CVT64UN_2X96H, + ICLASS_IVP_CVT16U2NX24L, + ICLASS_IVP_CVT24U2NX16, + ICLASS_IVP_CVT24S2NX16, + ICLASS_IVP_CVT32S24, + ICLASS_IVP_CVT24U32, + ICLASS_IVP_CVT24UNX32L, + ICLASS_IVP_CVT24UNX32H, + ICLASS_IVP_CVT32UNX48L, + ICLASS_IVP_CVT48UNX32L, + ICLASS_IVP_CVT48UNX32, + ICLASS_IVP_CVT48SNX32L, + ICLASS_IVP_CVT48SNX32, + ICLASS_IVP_CVT64S48, + ICLASS_IVP_CVT48U64, + ICLASS_IVP_CVT48UN_2X64L, + ICLASS_IVP_CVT48UN_2X64H, + ICLASS_IVP_CVT64UN_2X96L, + ICLASS_IVP_CVT96UN_2X64, + ICLASS_IVP_CVT96U64, + ICLASS_IVP_CVT64U96, + ICLASS_IVP_LB2N_I, + ICLASS_IVP_LB2N_IP, + ICLASS_IVP_SB2N_I, + ICLASS_IVP_SB2N_IP, + ICLASS_IVP_LTR2N, + ICLASS_IVP_LTR2NI, + ICLASS_IVP_LVN_2X16U_I, + ICLASS_IVP_LVN_2X16U_IP, + ICLASS_IVP_LVN_2X16U_X, + ICLASS_IVP_LVN_2X16U_XP, + ICLASS_IVP_LVN_2X16UT_I, + ICLASS_IVP_LVN_2X16UT_IP, + ICLASS_IVP_LVN_2X16UT_X, + ICLASS_IVP_LVN_2X16UT_XP, + ICLASS_IVP_LVN_2X16S_I, + ICLASS_IVP_LVN_2X16S_IP, + ICLASS_IVP_LVN_2X16S_X, + ICLASS_IVP_LVN_2X16S_XP, + ICLASS_IVP_LVN_2X16ST_I, + ICLASS_IVP_LVN_2X16ST_IP, + ICLASS_IVP_LVN_2X16ST_X, + ICLASS_IVP_LVN_2X16ST_XP, + ICLASS_IVP_SVN_2X16U_I, + ICLASS_IVP_SVN_2X16UT_I, + ICLASS_IVP_SVN_2X16U_IP, + ICLASS_IVP_SVN_2X16UT_IP, + ICLASS_IVP_SVN_2X16U_X, + ICLASS_IVP_SVN_2X16UT_X, + ICLASS_IVP_SVN_2X16U_XP, + ICLASS_IVP_SVN_2X16UT_XP, + ICLASS_IVP_SVN_2X16S_I, + ICLASS_IVP_SVN_2X16ST_I, + ICLASS_IVP_SVN_2X16S_IP, + ICLASS_IVP_SVN_2X16ST_IP, + ICLASS_IVP_SVN_2X16S_X, + ICLASS_IVP_SVN_2X16ST_X, + ICLASS_IVP_SVN_2X16S_XP, + ICLASS_IVP_SVN_2X16ST_XP, + ICLASS_IVP_LAN_2X16S_IP, + ICLASS_IVP_LAN_2X16U_IP, + ICLASS_IVP_LAN_2X16U_XP, + ICLASS_IVP_LAN_2X16S_XP, + ICLASS_IVP_SAN_2X16U_IP, + ICLASS_IVP_SAN_2X16S_IP, + ICLASS_IVP_LAVN_2X16S_XP, + ICLASS_IVP_LAVN_2X16U_XP, + ICLASS_IVP_SAVN_2X16U_XP, + ICLASS_IVP_SAVN_2X16S_XP, + ICLASS_IVP_LSN_2X16S_I, + ICLASS_IVP_LSN_2X16S_IP, + ICLASS_IVP_LSN_2X16S_X, + ICLASS_IVP_LSN_2X16S_XP, + ICLASS_IVP_SSN_2X16S_I, + ICLASS_IVP_SSN_2X16S_IP, + ICLASS_IVP_SSN_2X16S_X, + ICLASS_IVP_SSN_2X16S_XP, + ICLASS_IVP_LSN_2X32_I, + ICLASS_IVP_LSN_2X32_IP, + ICLASS_IVP_LSN_2X32_X, + ICLASS_IVP_LSN_2X32_XP, + ICLASS_IVP_SSN_2X32_I, + ICLASS_IVP_SSN_2X32_IP, + ICLASS_IVP_SSN_2X32_X, + ICLASS_IVP_SSN_2X32_XP, + ICLASS_IVP_BMAXUNX16, + ICLASS_IVP_BMINUNX16, + ICLASS_IVP_RBMINUNX16, + ICLASS_IVP_RBMAXUNX16, + ICLASS_IVP_BMAX2NX8, + ICLASS_IVP_BMIN2NX8, + ICLASS_IVP_BMAXU2NX8, + ICLASS_IVP_BMINU2NX8, + ICLASS_IVP_BMAXN_2X32, + ICLASS_IVP_BMINN_2X32, + ICLASS_IVP_BMAXUN_2X32, + ICLASS_IVP_BMINUN_2X32, + ICLASS_IVP_ADDN_2X32T, + ICLASS_IVP_SUBN_2X32T, + ICLASS_IVP_ADD2NX8, + ICLASS_IVP_SUB2NX8, + ICLASS_IVP_NEG2NX8, + ICLASS_IVP_MIN2NX8, + ICLASS_IVP_MINU2NX8, + ICLASS_IVP_MAX2NX8, + ICLASS_IVP_MAXU2NX8, + ICLASS_IVP_LT2NX8, + ICLASS_IVP_LE2NX8, + ICLASS_IVP_EQ2NX8, + ICLASS_IVP_NEQ2NX8, + ICLASS_IVP_LTU2NX8, + ICLASS_IVP_LEU2NX8, + ICLASS_IVP_ADD2NX8T, + ICLASS_IVP_SUB2NX8T, + ICLASS_IVP_SELNX16T, + ICLASS_IVP_SELN_2X32, + ICLASS_IVP_SELN_2X32T, + ICLASS_IVP_SHFLN_2X32, + ICLASS_IVP_SLLIN_2X32, + ICLASS_IVP_SLSIN_2X32, + ICLASS_IVP_SRAIN_2X32, + ICLASS_IVP_SRLIN_2X32, + ICLASS_IVP_SLLN_2X32, + ICLASS_IVP_SRLN_2X32, + ICLASS_IVP_SLAN_2X32, + ICLASS_IVP_SRAN_2X32, + ICLASS_IVP_SLSN_2X32, + ICLASS_IVP_SRSN_2X32, + ICLASS_IVP_RADDN_2X32, + ICLASS_IVP_RMAXN_2X32, + ICLASS_IVP_RMINN_2X32, + ICLASS_IVP_RMAXUN_2X32, + ICLASS_IVP_RMINUN_2X32, + ICLASS_IVP_RADDN_2X32T, + ICLASS_IVP_ABS2NX8, + ICLASS_IVP_ABSN_2X32, + ICLASS_IVP_MULSGNSNX16, + ICLASS_IVP_ROTRI2NX8, + ICLASS_IVP_ROTRINX16, + ICLASS_IVP_ROTRIN_2X32, + ICLASS_IVP_ROTRNX16, + ICLASS_IVP_ROTRN_2X32, + ICLASS_IVP_ADDN_2X32, + ICLASS_IVP_SUBN_2X32, + ICLASS_IVP_NEGN_2X32, + ICLASS_IVP_MINN_2X32, + ICLASS_IVP_MINUN_2X32, + ICLASS_IVP_MAXN_2X32, + ICLASS_IVP_MAXUN_2X32, + ICLASS_IVP_MULSGNN_2X32, + ICLASS_IVP_NSAN_2X32, + ICLASS_IVP_NSAUN_2X32, + ICLASS_IVP_LTN_2X32, + ICLASS_IVP_LEN_2X32, + ICLASS_IVP_EQN_2X32, + ICLASS_IVP_NEQN_2X32, + ICLASS_IVP_LTUN_2X32, + ICLASS_IVP_LEUN_2X32, + ICLASS_IVP_LAT2NX8_XP, + ICLASS_IVP_MULUU2NX8, + ICLASS_IVP_MULUUA2NX8, + ICLASS_IVP_MULUS2NX8, + ICLASS_IVP_MULUSA2NX8, + ICLASS_IVP_MULI2NX8X16, + ICLASS_IVP_MULAI2NX8X16, + ICLASS_IVP_MULUSI2NX8X16, + ICLASS_IVP_MULUSAI2NX8X16, + ICLASS_IVP_MULI2NR8X16, + ICLASS_IVP_MULAI2NR8X16, + ICLASS_IVP_MULUSI2NR8X16, + ICLASS_IVP_MULUSAI2NR8X16, + ICLASS_IVP_MULUSA2N8XR16, + ICLASS_IVP_MULUS2N8XR16, + ICLASS_IVP_MULA2N8XR16, + ICLASS_IVP_MUL2N8XR16, + ICLASS_IVP_DSEL2NX8I, + ICLASS_IVP_DSEL2NX8I_H, + ICLASS_IVP_DSELNX16, + ICLASS_IVP_DSELNX16T, + ICLASS_IVP_INJBI2NX8, + ICLASS_IVP_EXTBI2NX8, + ICLASS_IVP_MOVVA32, + ICLASS_IVP_MOVAV32, + ICLASS_IVP_MOVWW, + ICLASS_IVP_LS2NX8_I, + ICLASS_IVP_LS2NX8_IP, + ICLASS_IVP_LS2NX8_X, + ICLASS_IVP_LS2NX8_XP, + ICLASS_IVP_SS2NX8_I, + ICLASS_IVP_SS2NX8_IP, + ICLASS_IVP_SS2NX8_X, + ICLASS_IVP_SS2NX8_XP, + ICLASS_IVP_LANX8S_XP, + ICLASS_IVP_LANX8U_XP, + ICLASS_IVP_LA2NX8_XP, + ICLASS_IVP_ABSSUBU2NX8, + ICLASS_IVP_ABSSUB2NX8, + ICLASS_IVP_MOVVINT8, + ICLASS_IVP_MOVVA8, + ICLASS_IVP_MOVAVU8, + ICLASS_IVP_SLLI2NX8, + ICLASS_IVP_SRAI2NX8, + ICLASS_IVP_SRLI2NX8, + ICLASS_IVP_PACKL2NX24, + ICLASS_IVP_PACKVR2NX24, + ICLASS_IVP_PACKVRU2NX24, + ICLASS_IVP_PACKLNX48, + ICLASS_IVP_PACKL2NX24_1, + ICLASS_IVP_PACKVR2NX24_0, + ICLASS_IVP_PACKVR2NX24_1, + ICLASS_IVP_PACKVRU2NX24_0, + ICLASS_IVP_PACKVRU2NX24_1, + ICLASS_IVP_PACKVRNR2NX24_0, + ICLASS_IVP_PACKVRNR2NX24_1, + ICLASS_IVP_PACKMNX48, + ICLASS_IVP_PACKVRNX48, + ICLASS_IVP_UNPKS2NX8_0, + ICLASS_IVP_UNPKS2NX8_1, + ICLASS_IVP_UNPKSNX16_L, + ICLASS_IVP_UNPKSNX16_H, + ICLASS_IVP_SEL2NX8I, + ICLASS_IVP_SEL2NX8I_S0, + ICLASS_IVP_SEL2NX8I_S2, + ICLASS_IVP_SEL2NX8I_S4, + ICLASS_IVP_SHFL2NX8I, + ICLASS_IVP_SHFL2NX8I_S0, + ICLASS_IVP_SHFL2NX8I_S2, + ICLASS_IVP_SHFL2NX8I_S4, + ICLASS_IVP_SEL2NX8, + ICLASS_IVP_SHFL2NX8, + ICLASS_IVP_SEL2NX8T, + ICLASS_IVP_SQZN, + ICLASS_IVP_UNSQZN, + ICLASS_IVP_MULNX16, + ICLASS_IVP_MULANX16, + ICLASS_IVP_MULUUNX16, + ICLASS_IVP_MULUUANX16, + ICLASS_IVP_MULUSNX16, + ICLASS_IVP_MULUSANX16, + ICLASS_IVP_MUL2NX8, + ICLASS_IVP_MULA2NX8, + ICLASS_IVP_ADDW2NX8, + ICLASS_IVP_ADDWA2NX8, + ICLASS_IVP_ADDWS2NX8, + ICLASS_IVP_ADDWU2NX8, + ICLASS_IVP_ADDWUA2NX8, + ICLASS_IVP_ADDWUS2NX8, + ICLASS_IVP_DIVN_2X32X16S_4STEP0, + ICLASS_IVP_DIVN_2X32X16S_4STEP, + ICLASS_IVP_DIVN_2X32X16S_4STEPN, + ICLASS_IVP_DIVN_2X32X16U_4STEP0, + ICLASS_IVP_DIVN_2X32X16U_4STEP, + ICLASS_IVP_DIVN_2X32X16U_4STEPN, + ICLASS_IVP_DIVNX16S_4STEP0, + ICLASS_IVP_DIVNX16S_4STEP, + ICLASS_IVP_DIVNX16S_4STEPN, + ICLASS_IVP_DIVNX16U_4STEP0, + ICLASS_IVP_DIVNX16U_4STEP, + ICLASS_IVP_DIVNX16U_4STEPN, + ICLASS_IVP_DIVNX16SQ_4STEP0, + ICLASS_IVP_DIVNX16Q_4STEP0, + ICLASS_IVP_MULSNX16, + ICLASS_IVP_MULUUSNX16, + ICLASS_IVP_MULUSSNX16, + ICLASS_IVP_MULN_2X16X32_0, + ICLASS_IVP_MULUUN_2X16X32_0, + ICLASS_IVP_MULUSN_2X16X32_0, + ICLASS_IVP_MULSUN_2X16X32_0, + ICLASS_IVP_MULN_2X16X32_1, + ICLASS_IVP_MULUUN_2X16X32_1, + ICLASS_IVP_MULUSN_2X16X32_1, + ICLASS_IVP_MULSUN_2X16X32_1, + ICLASS_IVP_MULHN_2X16X32_1, + ICLASS_IVP_MULUUHN_2X16X32_1, + ICLASS_IVP_MULUSHN_2X16X32_1, + ICLASS_IVP_MULSUHN_2X16X32_1, + ICLASS_IVP_MULAN_2X16X32_0, + ICLASS_IVP_MULUUAN_2X16X32_0, + ICLASS_IVP_MULUSAN_2X16X32_0, + ICLASS_IVP_MULSUAN_2X16X32_0, + ICLASS_IVP_MULAHN_2X16X32_1, + ICLASS_IVP_MULUUAHN_2X16X32_1, + ICLASS_IVP_MULUSAHN_2X16X32_1, + ICLASS_IVP_MULSUAHN_2X16X32_1, + ICLASS_IVP_MULAN_2X16X32_1, + ICLASS_IVP_MULUUAN_2X16X32_1, + ICLASS_IVP_MULUSAN_2X16X32_1, + ICLASS_IVP_MULSUAN_2X16X32_1, + ICLASS_IVP_MULSHN_2X16X32_1, + ICLASS_IVP_MULUUSHN_2X16X32_1, + ICLASS_IVP_MULUSSHN_2X16X32_1, + ICLASS_IVP_MULSUSHN_2X16X32_1, + ICLASS_IVP_MULSN_2X16X32_0, + ICLASS_IVP_MULUUSN_2X16X32_0, + ICLASS_IVP_MULUSSN_2X16X32_0, + ICLASS_IVP_MULSUSN_2X16X32_0, + ICLASS_IVP_MULSN_2X16X32_1, + ICLASS_IVP_MULUUSN_2X16X32_1, + ICLASS_IVP_MULUSSN_2X16X32_1, + ICLASS_IVP_MULSUSN_2X16X32_1, + ICLASS_IVP_PACKLN_2X96, + ICLASS_IVP_PACKHN_2X64W, + ICLASS_IVP_PACKVRN_2X64W, + ICLASS_IVP_PACKVRNRN_2X64W, + ICLASS_IVP_PACKVRNX48_0, + ICLASS_IVP_PACKVRNX48_1, + ICLASS_IVP_PACKVRNRNX48_0, + ICLASS_IVP_PACKVRNRNX48_1, + ICLASS_IVP_PACKVRNRNX48, + ICLASS_IVP_PACKVRNR2NX24, + ICLASS_IVP_L2A4NX8_IP, + ICLASS_IVP_L2AU2NX8_IP, + ICLASS_IVP_L2U2NX8_XP, + ICLASS_IVP_AVGU2NX8, + ICLASS_IVP_AVGRU2NX8, + ICLASS_IVP_RADD2NX8, + ICLASS_IVP_RADD2NX8T, + ICLASS_IVP_RADDUNX16, + ICLASS_IVP_RADDUNX16T, + ICLASS_IVP_RADDU2NX8, + ICLASS_IVP_RADDU2NX8T, + ICLASS_IVP_LTRS2N, + ICLASS_IVP_LTRSN, + ICLASS_IVP_LTRSN_2, + ICLASS_IVP_SEQ2NX8, + ICLASS_IVP_SEQN_2X32, + ICLASS_IVP_EXTRN_2X32, + ICLASS_IVP_UNPKU2NX8_0, + ICLASS_IVP_UNPKU2NX8_1, + ICLASS_IVP_BADDNORMNX16, + ICLASS_IVP_BSUBNORMNX16, + ICLASS_IVP_RADDSNX16, + ICLASS_IVP_RADDSNX16T, + ICLASS_IVP_ORNOTB, + ICLASS_IVP_EXTR2NX8, + ICLASS_IVP_EXTRVRN_2X32, + ICLASS_IVP_MOVAV8, + ICLASS_IVP_MULPN16XR16, + ICLASS_IVP_MULPAN16XR16, + ICLASS_IVP_MULUSPN16XR16, + ICLASS_IVP_MULUSPAN16XR16, + ICLASS_IVP_MULP2N8XR16, + ICLASS_IVP_MULPA2N8XR16, + ICLASS_IVP_MULUSP2N8XR16, + ICLASS_IVP_MULUSPA2N8XR16, + ICLASS_IVP_MULPNX16, + ICLASS_IVP_MULPANX16, + ICLASS_IVP_MULUSPNX16, + ICLASS_IVP_MULUSPANX16, + ICLASS_IVP_MULUUPNX16, + ICLASS_IVP_MULUUPANX16, + ICLASS_IVP_MULP2NX8, + ICLASS_IVP_MULPA2NX8, + ICLASS_IVP_MULUSP2NX8, + ICLASS_IVP_MULUSPA2NX8, + ICLASS_IVP_MULUUP2NX8, + ICLASS_IVP_MULUUPA2NX8, + ICLASS_IVP_MULPI2NR8X16, + ICLASS_IVP_MULPAI2NR8X16, + ICLASS_IVP_MULUSPI2NR8X16, + ICLASS_IVP_MULUSPAI2NR8X16, + ICLASS_IVP_MULQ2N8XR8, + ICLASS_IVP_MULQA2N8XR8, + ICLASS_IVP_MULUSQ2N8XR8, + ICLASS_IVP_MULUSQA2N8XR8, + ICLASS_IVP_MUL4T2N8XR8, + ICLASS_IVP_MUL4TA2N8XR8, + ICLASS_IVP_MULUS4T2N8XR8, + ICLASS_IVP_MULUS4TA2N8XR8, + ICLASS_IVP_ADDWNX16, + ICLASS_IVP_ADDWANX16, + ICLASS_IVP_ADDWSNX16, + ICLASS_IVP_ADDWUNX16, + ICLASS_IVP_ADDWUANX16, + ICLASS_IVP_ADDWUSNX16, + ICLASS_IVP_SUBWNX16, + ICLASS_IVP_SUBWANX16, + ICLASS_IVP_SUBWUNX16, + ICLASS_IVP_SUBWUANX16, + ICLASS_IVP_SUBW2NX8, + ICLASS_IVP_SUBWA2NX8, + ICLASS_IVP_SUBWU2NX8, + ICLASS_IVP_SUBWUA2NX8, + ICLASS_IVP_RANDB2N, + ICLASS_IVP_RORB2N, + ICLASS_IVP_RANDBN, + ICLASS_IVP_RORBN, + ICLASS_IVP_RANDBN_2, + ICLASS_IVP_RORBN_2, + ICLASS_IVP_AVGNX16, + ICLASS_IVP_AVGUNX16, + ICLASS_IVP_AVG2NX8, + ICLASS_IVP_AVGR2NX8, + ICLASS_IVP_AVGRNX16, + ICLASS_IVP_AVGRUNX16, + ICLASS_IVP_GATHERANX8U, + ICLASS_IVP_GATHERANX16, + ICLASS_IVP_GATHERAN_2X32, + ICLASS_IVP_GATHERANX8UT, + ICLASS_IVP_GATHERANX16T, + ICLASS_IVP_GATHERAN_2X32T, + ICLASS_IVP_GATHERDNX16, + ICLASS_IVP_GATHERDNX8S, + ICLASS_IVP_GATHERD2NX8_L, + ICLASS_IVP_GATHERD2NX8_H, + ICLASS_IVP_MOVGATHERD, + ICLASS_IVP_SCATTERNX8U, + ICLASS_IVP_SCATTER2NX8_L, + ICLASS_IVP_SCATTER2NX8_H, + ICLASS_IVP_SCATTERNX16, + ICLASS_IVP_SCATTERN_2X32, + ICLASS_IVP_SCATTERNX8UT, + ICLASS_IVP_SCATTER2NX8T_L, + ICLASS_IVP_SCATTER2NX8T_H, + ICLASS_IVP_SCATTERNX16T, + ICLASS_IVP_SCATTERN_2X32T, + ICLASS_IVP_SCATTERW, + ICLASS_IVP_COUNTEQZ4NX8, + ICLASS_IVP_COUNTEQ4NX8, + ICLASS_IVP_COUNTEQMZ4NX8, + ICLASS_IVP_COUNTEQM4NX8, + ICLASS_IVP_COUNTLEZ4NX8, + ICLASS_IVP_COUNTLE4NX8, + ICLASS_IVP_COUNTLEMZ4NX8, + ICLASS_IVP_COUNTLEM4NX8, + ICLASS_IVP_LSR2NX8_I, + ICLASS_IVP_LSR2NX8_IP, + ICLASS_IVP_LSR2NX8_X, + ICLASS_IVP_LSR2NX8_XP, + ICLASS_IVP_LSRNX16_I, + ICLASS_IVP_LSRNX16_IP, + ICLASS_IVP_LSRNX16_X, + ICLASS_IVP_LSRNX16_XP, + ICLASS_IVP_LSRN_2X32_I, + ICLASS_IVP_LSRN_2X32_IP, + ICLASS_IVP_LSRN_2X32_X, + ICLASS_IVP_LSRN_2X32_XP, + ICLASS_IVP_ABSNX16, + ICLASS_IVP_ABSSNX16, + ICLASS_IVP_ABSSUBNX16, + ICLASS_IVP_ABSSUBUNX16, + ICLASS_IVP_ABSSSUBNX16, + ICLASS_xt_iclass_excw, + ICLASS_xt_iclass_rfe, + ICLASS_xt_iclass_rfde, + ICLASS_xt_iclass_syscall, + ICLASS_xt_iclass_call12, + ICLASS_xt_iclass_call8, + ICLASS_xt_iclass_call4, + ICLASS_xt_iclass_callx12, + ICLASS_xt_iclass_callx8, + ICLASS_xt_iclass_callx4, + ICLASS_xt_iclass_entry, + ICLASS_xt_iclass_movsp, + ICLASS_xt_iclass_rotw, + ICLASS_xt_iclass_retw, + ICLASS_xt_iclass_rfwou, + ICLASS_xt_iclass_l32e, + ICLASS_xt_iclass_s32e, + ICLASS_xt_iclass_rsr_windowbase, + ICLASS_xt_iclass_wsr_windowbase, + ICLASS_xt_iclass_xsr_windowbase, + ICLASS_xt_iclass_rsr_windowstart, + ICLASS_xt_iclass_wsr_windowstart, + ICLASS_xt_iclass_xsr_windowstart, + ICLASS_xt_iclass_add_n, + ICLASS_xt_iclass_addi_n, + ICLASS_xt_iclass_bz6, + ICLASS_xt_iclass_ill_n, + ICLASS_xt_iclass_loadi4, + ICLASS_xt_iclass_mov_n, + ICLASS_xt_iclass_movi_n, + ICLASS_xt_iclass_nopn, + ICLASS_xt_iclass_retn, + ICLASS_xt_iclass_storei4, + ICLASS_rur_threadptr, + ICLASS_wur_threadptr, + ICLASS_xt_iclass_addi, + ICLASS_xt_iclass_addmi, + ICLASS_xt_iclass_addsub, + ICLASS_xt_iclass_bit, + ICLASS_xt_iclass_bsi8, + ICLASS_xt_iclass_bsi8b, + ICLASS_xt_iclass_bsi8u, + ICLASS_xt_iclass_bst8, + ICLASS_xt_iclass_bsz12, + ICLASS_xt_iclass_call0, + ICLASS_xt_iclass_callx0, + ICLASS_xt_iclass_const16, + ICLASS_xt_iclass_exti, + ICLASS_xt_iclass_ill, + ICLASS_xt_iclass_jump, + ICLASS_xt_iclass_jumpx, + ICLASS_xt_iclass_l16ui, + ICLASS_xt_iclass_l16si, + ICLASS_xt_iclass_l32i, + ICLASS_xt_iclass_l32r, + ICLASS_xt_iclass_l8i, + ICLASS_xt_iclass_loop, + ICLASS_xt_iclass_loopz, + ICLASS_xt_iclass_movi, + ICLASS_xt_iclass_movz, + ICLASS_xt_iclass_neg, + ICLASS_xt_iclass_nop, + ICLASS_xt_iclass_l32ex, + ICLASS_xt_iclass_s32ex, + ICLASS_xt_iclass_getex, + ICLASS_xt_iclass_clrex, + ICLASS_xt_iclass_return, + ICLASS_xt_iclass_simcall, + ICLASS_xt_iclass_s16i, + ICLASS_xt_iclass_s32i, + ICLASS_xt_iclass_s32nb, + ICLASS_xt_iclass_s8i, + ICLASS_xt_iclass_sar, + ICLASS_xt_iclass_sari, + ICLASS_xt_iclass_shifts, + ICLASS_xt_iclass_shiftst, + ICLASS_xt_iclass_shiftt, + ICLASS_xt_iclass_slli, + ICLASS_xt_iclass_srai, + ICLASS_xt_iclass_srli, + ICLASS_xt_iclass_memw, + ICLASS_xt_iclass_extw, + ICLASS_xt_iclass_isync, + ICLASS_xt_iclass_sync, + ICLASS_xt_iclass_rsil, + ICLASS_xt_iclass_rsr_lend, + ICLASS_xt_iclass_wsr_lend, + ICLASS_xt_iclass_xsr_lend, + ICLASS_xt_iclass_rsr_lcount, + ICLASS_xt_iclass_wsr_lcount, + ICLASS_xt_iclass_xsr_lcount, + ICLASS_xt_iclass_rsr_lbeg, + ICLASS_xt_iclass_wsr_lbeg, + ICLASS_xt_iclass_xsr_lbeg, + ICLASS_xt_iclass_rsr_sar, + ICLASS_xt_iclass_wsr_sar, + ICLASS_xt_iclass_xsr_sar, + ICLASS_xt_iclass_rsr_memctl, + ICLASS_xt_iclass_wsr_memctl, + ICLASS_xt_iclass_xsr_memctl, + ICLASS_xt_iclass_rsr_litbase, + ICLASS_xt_iclass_wsr_litbase, + ICLASS_xt_iclass_xsr_litbase, + ICLASS_xt_iclass_rsr_configid0, + ICLASS_xt_iclass_wsr_configid0, + ICLASS_xt_iclass_rsr_configid1, + ICLASS_xt_iclass_rsr_ps, + ICLASS_xt_iclass_wsr_ps, + ICLASS_xt_iclass_xsr_ps, + ICLASS_xt_iclass_rsr_epc1, + ICLASS_xt_iclass_wsr_epc1, + ICLASS_xt_iclass_xsr_epc1, + ICLASS_xt_iclass_rsr_excsave1, + ICLASS_xt_iclass_wsr_excsave1, + ICLASS_xt_iclass_xsr_excsave1, + ICLASS_xt_iclass_rsr_epc2, + ICLASS_xt_iclass_wsr_epc2, + ICLASS_xt_iclass_xsr_epc2, + ICLASS_xt_iclass_rsr_excsave2, + ICLASS_xt_iclass_wsr_excsave2, + ICLASS_xt_iclass_xsr_excsave2, + ICLASS_xt_iclass_rsr_epc3, + ICLASS_xt_iclass_wsr_epc3, + ICLASS_xt_iclass_xsr_epc3, + ICLASS_xt_iclass_rsr_excsave3, + ICLASS_xt_iclass_wsr_excsave3, + ICLASS_xt_iclass_xsr_excsave3, + ICLASS_xt_iclass_rsr_epc4, + ICLASS_xt_iclass_wsr_epc4, + ICLASS_xt_iclass_xsr_epc4, + ICLASS_xt_iclass_rsr_excsave4, + ICLASS_xt_iclass_wsr_excsave4, + ICLASS_xt_iclass_xsr_excsave4, + ICLASS_xt_iclass_rsr_eps2, + ICLASS_xt_iclass_wsr_eps2, + ICLASS_xt_iclass_xsr_eps2, + ICLASS_xt_iclass_rsr_eps3, + ICLASS_xt_iclass_wsr_eps3, + ICLASS_xt_iclass_xsr_eps3, + ICLASS_xt_iclass_rsr_eps4, + ICLASS_xt_iclass_wsr_eps4, + ICLASS_xt_iclass_xsr_eps4, + ICLASS_xt_iclass_rsr_excvaddr, + ICLASS_xt_iclass_wsr_excvaddr, + ICLASS_xt_iclass_xsr_excvaddr, + ICLASS_xt_iclass_rsr_depc, + ICLASS_xt_iclass_wsr_depc, + ICLASS_xt_iclass_xsr_depc, + ICLASS_xt_iclass_rsr_exccause, + ICLASS_xt_iclass_wsr_exccause, + ICLASS_xt_iclass_xsr_exccause, + ICLASS_xt_iclass_rsr_prid, + ICLASS_xt_iclass_rsr_vecbase, + ICLASS_xt_iclass_wsr_vecbase, + ICLASS_xt_iclass_xsr_vecbase, + ICLASS_xt_iclass_rsr_mpucfg, + ICLASS_xt_iclass_wsr_mpucfg, + ICLASS_xt_iclass_rsr_gserr, + ICLASS_xt_iclass_wsr_gserr, + ICLASS_xt_iclass_xsr_gserr, + ICLASS_xt_iclass_salt, + ICLASS_xt_mul16, + ICLASS_xt_mul32, + ICLASS_xt_mul32h, + ICLASS_xt_iclass_rfi, + ICLASS_xt_iclass_wait, + ICLASS_xt_iclass_rsr_interrupt, + ICLASS_xt_iclass_wsr_intset, + ICLASS_xt_iclass_wsr_intclear, + ICLASS_xt_iclass_rsr_intenable, + ICLASS_xt_iclass_wsr_intenable, + ICLASS_xt_iclass_xsr_intenable, + ICLASS_xt_iclass_break, + ICLASS_xt_iclass_break_n, + ICLASS_xt_iclass_rsr_dbreaka0, + ICLASS_xt_iclass_wsr_dbreaka0, + ICLASS_xt_iclass_xsr_dbreaka0, + ICLASS_xt_iclass_rsr_dbreakc0, + ICLASS_xt_iclass_wsr_dbreakc0, + ICLASS_xt_iclass_xsr_dbreakc0, + ICLASS_xt_iclass_rsr_ibreaka0, + ICLASS_xt_iclass_wsr_ibreaka0, + ICLASS_xt_iclass_xsr_ibreaka0, + ICLASS_xt_iclass_rsr_ibreakenable, + ICLASS_xt_iclass_wsr_ibreakenable, + ICLASS_xt_iclass_xsr_ibreakenable, + ICLASS_xt_iclass_rsr_debugcause, + ICLASS_xt_iclass_wsr_debugcause, + ICLASS_xt_iclass_xsr_debugcause, + ICLASS_xt_iclass_rsr_icount, + ICLASS_xt_iclass_wsr_icount, + ICLASS_xt_iclass_xsr_icount, + ICLASS_xt_iclass_rsr_icountlevel, + ICLASS_xt_iclass_wsr_icountlevel, + ICLASS_xt_iclass_xsr_icountlevel, + ICLASS_xt_iclass_rsr_ddr, + ICLASS_xt_iclass_wsr_ddr, + ICLASS_xt_iclass_xsr_ddr, + ICLASS_xt_iclass_lddr32_p, + ICLASS_xt_iclass_sddr32_p, + ICLASS_xt_iclass_rfdo, + ICLASS_xt_iclass_rfdd, + ICLASS_xt_iclass_wsr_mmid, + ICLASS_xt_iclass_bbool1, + ICLASS_xt_iclass_bbool4, + ICLASS_xt_iclass_bbool8, + ICLASS_xt_iclass_bbranch, + ICLASS_xt_iclass_bmove, + ICLASS_xt_iclass_RSR_BR, + ICLASS_xt_iclass_WSR_BR, + ICLASS_xt_iclass_XSR_BR, + ICLASS_xt_iclass_rsr_ccount, + ICLASS_xt_iclass_wsr_ccount, + ICLASS_xt_iclass_xsr_ccount, + ICLASS_xt_iclass_rsr_ccompare0, + ICLASS_xt_iclass_wsr_ccompare0, + ICLASS_xt_iclass_xsr_ccompare0, + ICLASS_xt_iclass_rsr_ccompare1, + ICLASS_xt_iclass_wsr_ccompare1, + ICLASS_xt_iclass_xsr_ccompare1, + ICLASS_xt_iclass_icache, + ICLASS_xt_iclass_icache_lock, + ICLASS_xt_iclass_icache_inv, + ICLASS_xt_iclass_licx, + ICLASS_xt_iclass_sicx, + ICLASS_xt_iclass_wsr_cacheadrdis, + ICLASS_xt_iclass_rsr_cacheadrdis, + ICLASS_xt_iclass_xsr_cacheadrdis, + ICLASS_xt_iclass_rptlb0, + ICLASS_xt_iclass_rptlb, + ICLASS_xt_iclass_wptlb, + ICLASS_xt_iclass_rsr_mpuenb, + ICLASS_xt_iclass_wsr_mpuenb, + ICLASS_xt_iclass_xsr_mpuenb, + ICLASS_xt_iclass_rsr_cpenable, + ICLASS_xt_iclass_wsr_cpenable, + ICLASS_xt_iclass_xsr_cpenable, + ICLASS_xt_iclass_clamp, + ICLASS_xt_iclass_minmax, + ICLASS_xt_iclass_nsa, + ICLASS_xt_iclass_sx, + ICLASS_xt_iclass_l32ai, + ICLASS_xt_iclass_s32ri, + ICLASS_xt_iclass_rsr_atomctl, + ICLASS_xt_iclass_wsr_atomctl, + ICLASS_xt_iclass_xsr_atomctl, + ICLASS_xt_iclass_div, + ICLASS_xt_iclass_rsr_eraccess, + ICLASS_xt_iclass_wsr_eraccess, + ICLASS_xt_iclass_xsr_eraccess, + ICLASS_xt_iclass_rer, + ICLASS_xt_iclass_wer, + ICLASS_xt_iclass_wb15_0, + ICLASS_xt_iclass_wb15_1, + ICLASS_xt_iclass_wb15_2, + ICLASS_xt_iclass_wb15_3, + ICLASS_xt_iclass_wb15_4, + ICLASS_MTK_AndPOPC, + ICLASS_iq_tie2apb_inq0_pop, + ICLASS_iq_tie2apb_inq0_is_ready, + ICLASS_iq_tie2apb_inq0_nonblocking_peek, + ICLASS_iq_tie2apb_inq0_nonblocking_pop, + ICLASS_iq_tie2apb_inq0_blocking_peek, + ICLASS_oq_tie2apb_outq0_push_read, + ICLASS_oq_tie2apb_outq0_push_write, + ICLASS_oq_tie2apb_outq0_is_ready, + ICLASS_oq_tie2apb_outq0_nonblocking_push_read, + ICLASS_oq_tie2apb_outq0_nonblocking_push_write, + ICLASS_rur_apb_pipe, + ICLASS_wur_apb_pipe +}; + + +/* Opcode encodings. */ + +static void +Opcode_ivp_repnx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8200070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_repnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30502020; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_repnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100020; +} + +static void +Opcode_ivp_repnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe60000; +} + +static void +Opcode_ivp_repnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000020; +} + +static void +Opcode_ivp_repnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c03400; +} + +static void +Opcode_ivp_repnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800320; +} + +static void +Opcode_ivp_repnx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800020; +} + +static void +Opcode_ivp_repnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400020; +} + +static void +Opcode_ivp_repnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c204020; +} + +static void +Opcode_ivp_repnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce0000; +} + +static void +Opcode_ivp_repnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800182; +} + +static void +Opcode_ivp_selsnx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_selsnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30502030; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_selsnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100030; +} + +static void +Opcode_ivp_selsnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe68000; +} + +static void +Opcode_ivp_selsnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000030; +} + +static void +Opcode_ivp_selsnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d03400; +} + +static void +Opcode_ivp_selsnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800330; +} + +static void +Opcode_ivp_selsnx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800030; +} + +static void +Opcode_ivp_selsnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400030; +} + +static void +Opcode_ivp_selsnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c204030; +} + +static void +Opcode_ivp_selsnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce8000; +} + +static void +Opcode_ivp_selsnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800183; +} + +static void +Opcode_ivp_rep2nx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rep2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30502000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rep2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ivp_rep2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_ivp_rep2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000000; +} + +static void +Opcode_ivp_rep2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c03800; +} + +static void +Opcode_ivp_rep2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800300; +} + +static void +Opcode_ivp_rep2nx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ivp_rep2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400000; +} + +static void +Opcode_ivp_rep2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c204000; +} + +static void +Opcode_ivp_rep2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae0000; +} + +static void +Opcode_ivp_rep2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800180; +} + +static void +Opcode_ivp_sels2nx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8100070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sels2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30502010; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sels2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100010; +} + +static void +Opcode_ivp_sels2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_ivp_sels2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000010; +} + +static void +Opcode_ivp_sels2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d03800; +} + +static void +Opcode_ivp_sels2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800310; +} + +static void +Opcode_ivp_sels2nx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800010; +} + +static void +Opcode_ivp_sels2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400010; +} + +static void +Opcode_ivp_sels2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c204010; +} + +static void +Opcode_ivp_sels2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf0000; +} + +static void +Opcode_ivp_sels2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800181; +} + +static void +Opcode_ivp_repn_2x32_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8300070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_repn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34502020; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_repn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180020; +} + +static void +Opcode_ivp_repn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe88000; +} + +static void +Opcode_ivp_repn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000024; +} + +static void +Opcode_ivp_repn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c84400; +} + +static void +Opcode_ivp_repn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800324; +} + +static void +Opcode_ivp_repn_2x32_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880020; +} + +static void +Opcode_ivp_repn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9500020; +} + +static void +Opcode_ivp_repn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c304020; +} + +static void +Opcode_ivp_repn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd18000; +} + +static void +Opcode_ivp_repn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001c2; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8340070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34502030; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180030; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80008; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000034; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04400; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800334; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880030; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9500030; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c304030; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd1c000; +} + +static void +Opcode_ivp_selsn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001c3; +} + +static void +Opcode_ivp_ext0ib_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1708c0; +} + +static void +Opcode_ivp_ext0ib_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ext0ib_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261840; +} + +static void +Opcode_ivp_ext0ib_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000100; +} + +static void +Opcode_ivp_ext0ib_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261800; +} + +static void +Opcode_ivp_ext0ib_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800000; +} + +static void +Opcode_ivp_ext0ib_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8808; +} + +static void +Opcode_ivp_ext0ib_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9810008; +} + +static void +Opcode_ivp_ext0ib_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0810; +} + +static void +Opcode_ivp_ext0ib_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd820e0; +} + +static void +Opcode_ivp_ext0ib_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6808; +} + +static void +Opcode_ivp_notb_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1708d3; +} + +static void +Opcode_ivp_notb_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0032; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_notb_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261851; +} + +static void +Opcode_ivp_notb_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30001b0; +} + +static void +Opcode_ivp_notb_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261813; +} + +static void +Opcode_ivp_notb_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000b0; +} + +static void +Opcode_ivp_notb_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1803; +} + +static void +Opcode_ivp_notb_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98100b8; +} + +static void +Opcode_ivp_notb_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8819; +} + +static void +Opcode_ivp_notb_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0160c2; +} + +static void +Opcode_ivp_notb_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0410; +} + +static void +Opcode_ivp_notb_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd828e2; +} + +static void +Opcode_ivp_notb_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3813; +} + +static void +Opcode_ivp_andb_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x171078; +} + +static void +Opcode_ivp_andb_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260840; +} + +static void +Opcode_ivp_andb_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260800; +} + +static void +Opcode_ivp_andb_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19f800; +} + +static void +Opcode_ivp_andb_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab800; +} + +static void +Opcode_ivp_andb_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cb810; +} + +static void +Opcode_ivp_orb_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1718c0; +} + +static void +Opcode_ivp_orb_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261848; +} + +static void +Opcode_ivp_orb_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261808; +} + +static void +Opcode_ivp_orb_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9808; +} + +static void +Opcode_ivp_orb_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab010; +} + +static void +Opcode_ivp_orb_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c7808; +} + +static void +Opcode_ivp_xorb_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1710c8; +} + +static void +Opcode_ivp_xorb_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261050; +} + +static void +Opcode_ivp_xorb_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261010; +} + +static void +Opcode_ivp_xorb_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9018; +} + +static void +Opcode_ivp_xorb_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa818; +} + +static void +Opcode_ivp_xorb_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c7018; +} + +static void +Opcode_ivp_andnotb_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x171878; +} + +static void +Opcode_ivp_andnotb_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260848; +} + +static void +Opcode_ivp_andnotb_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260808; +} + +static void +Opcode_ivp_andnotb_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19f808; +} + +static void +Opcode_ivp_andnotb_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab808; +} + +static void +Opcode_ivp_andnotb_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cb818; +} + +static void +Opcode_ivp_mb_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1708d2; +} + +static void +Opcode_ivp_mb_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0022; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mb_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261850; +} + +static void +Opcode_ivp_mb_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30001a0; +} + +static void +Opcode_ivp_mb_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261812; +} + +static void +Opcode_ivp_mb_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000a0; +} + +static void +Opcode_ivp_mb_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1003; +} + +static void +Opcode_ivp_mb_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98100a8; +} + +static void +Opcode_ivp_mb_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8019; +} + +static void +Opcode_ivp_mb_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c016082; +} + +static void +Opcode_ivp_mb_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0410; +} + +static void +Opcode_ivp_mb_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd828e0; +} + +static void +Opcode_ivp_mb_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800281; +} + +static void +Opcode_ivp_mb_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3013; +} + +static void +Opcode_ivp_ltrn_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1701e0; +} + +static void +Opcode_ivp_ltrn_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260760; +} + +static void +Opcode_ivp_ltrn_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260720; +} + +static void +Opcode_ivp_ltrn_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0710; +} + +static void +Opcode_ivp_ltrn_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae700; +} + +static void +Opcode_ivp_ltrn_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0110; +} + +static void +Opcode_ivp_ltrn_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc710; +} + +static void +Opcode_ivp_ltrni_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1718c8; +} + +static void +Opcode_ivp_ltrni_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260060; +} + +static void +Opcode_ivp_ltrni_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260020; +} + +static void +Opcode_ivp_ltrni_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0400; +} + +static void +Opcode_ivp_ltrni_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae000; +} + +static void +Opcode_ivp_ltrni_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c10; +} + +static void +Opcode_ivp_ltrni_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc010; +} + +static void +Opcode_ivp_lbn_i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170040; +} + +static void +Opcode_ivp_lbn_i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a000; +} + +static void +Opcode_ivp_lbn_i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a000; +} + +static void +Opcode_ivp_lbn_i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a000; +} + +static void +Opcode_ivp_lbn_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x171060; +} + +static void +Opcode_ivp_lbn_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19d000; +} + +static void +Opcode_ivp_lbn_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa000; +} + +static void +Opcode_ivp_lbn_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca010; +} + +static void +Opcode_ivp_sbn_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a20080; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sbn_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1120060; +} + +static void +Opcode_ivp_sbn_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0800; +} + +static void +Opcode_ivp_sbn_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e0020; +} + +static void +Opcode_ivp_sbn_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800080; +} + +static void +Opcode_ivp_sbn_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f1080; +} + +static void +Opcode_ivp_sbn_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a200e0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sbn_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100d0; +} + +static void +Opcode_ivp_sbn_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0e00; +} + +static void +Opcode_ivp_sbn_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8300d0; +} + +static void +Opcode_ivp_sbn_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000e0; +} + +static void +Opcode_ivp_sbn_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f10e0; +} + +static void +Opcode_ivp_lsnx16_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10860000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsnx16_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0000; +} + +static void +Opcode_ivp_lsnx16_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18e000; +} + +static void +Opcode_ivp_lsnx16_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18e000; +} + +static void +Opcode_ivp_lsnx16_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x960000; +} + +static void +Opcode_ivp_lsnx16_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10548000; +} + +static void +Opcode_ivp_lsnx16_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10972000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsnx16_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1392000; +} + +static void +Opcode_ivp_lsnx16_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_ivp_lsnx16_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_ivp_lsnx16_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa72000; +} + +static void +Opcode_ivp_lsnx16_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b0000; +} + +static void +Opcode_ivp_lsnx16_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108cc000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsnx16_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf4000; +} + +static void +Opcode_ivp_lsnx16_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fa000; +} + +static void +Opcode_ivp_lsnx16_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea000; +} + +static void +Opcode_ivp_lsnx16_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9cc000; +} + +static void +Opcode_ivp_lsnx16_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057c000; +} + +static void +Opcode_ivp_lsnx16_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108ce000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsnx16_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdfc000; +} + +static void +Opcode_ivp_lsnx16_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc000; +} + +static void +Opcode_ivp_lsnx16_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fa000; +} + +static void +Opcode_ivp_lsnx16_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ce000; +} + +static void +Opcode_ivp_lsnx16_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057e000; +} + +static void +Opcode_ivp_movbrbv_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a45000d; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movbrbv_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100500; +} + +static void +Opcode_ivp_movbrbv_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3900400; +} + +static void +Opcode_ivp_movbrbv_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9810108; +} + +static void +Opcode_ivp_movbrbv_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c016000; +} + +static void +Opcode_ivp_movbrbv_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcfc00d; +} + +static void +Opcode_ivp_movbrbv_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e88010; +} + +static void +Opcode_ivp_movbvbr_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x217c0c80; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movbvbr_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28f838c; +} + +static void +Opcode_ivp_movbvbr_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28f828c; +} + +static void +Opcode_ivp_movbvbr_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9882200; +} + +static void +Opcode_ivp_movbvbr_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606e0e; +} + +static void +Opcode_ivp_movbvbr_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0200; +} + +static void +Opcode_ivp_movbvbr_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800080; +} + +static void +Opcode_ivp_joinb_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1710c0; +} + +static void +Opcode_ivp_joinb_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261048; +} + +static void +Opcode_ivp_joinb_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261008; +} + +static void +Opcode_ivp_joinb_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9008; +} + +static void +Opcode_ivp_joinb_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa810; +} + +static void +Opcode_ivp_joinb_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c7008; +} + +static void +Opcode_ivp_ltrn_2_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1702e0; +} + +static void +Opcode_ivp_ltrn_2_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260860; +} + +static void +Opcode_ivp_ltrn_2_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260820; +} + +static void +Opcode_ivp_ltrn_2_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2400; +} + +static void +Opcode_ivp_ltrn_2_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae800; +} + +static void +Opcode_ivp_ltrn_2_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0210; +} + +static void +Opcode_ivp_ltrn_2_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc500; +} + +static void +Opcode_ivp_ltrn_2i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700d0; +} + +static void +Opcode_ivp_ltrn_2i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260460; +} + +static void +Opcode_ivp_ltrn_2i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260420; +} + +static void +Opcode_ivp_ltrn_2i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0410; +} + +static void +Opcode_ivp_ltrn_2i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae400; +} + +static void +Opcode_ivp_ltrn_2i_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0010; +} + +static void +Opcode_ivp_ltrn_2i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc410; +} + +static void +Opcode_ivp_lbn_2_i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x171000; +} + +static void +Opcode_ivp_lbn_2_i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_ivp_lbn_2_i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_ivp_lbn_2_i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_ivp_lbn_2_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x171050; +} + +static void +Opcode_ivp_lbn_2_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19b000; +} + +static void +Opcode_ivp_lbn_2_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193010; +} + +static void +Opcode_ivp_lbn_2_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9010; +} + +static void +Opcode_ivp_sbn_2_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a20040; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sbn_2_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1110060; +} + +static void +Opcode_ivp_sbn_2_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0400; +} + +static void +Opcode_ivp_sbn_2_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d0020; +} + +static void +Opcode_ivp_sbn_2_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800040; +} + +static void +Opcode_ivp_sbn_2_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f1040; +} + +static void +Opcode_ivp_sbn_2_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a200d0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sbn_2_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11110c0; +} + +static void +Opcode_ivp_sbn_2_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0d00; +} + +static void +Opcode_ivp_sbn_2_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8310c0; +} + +static void +Opcode_ivp_sbn_2_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000d0; +} + +static void +Opcode_ivp_sbn_2_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f10d0; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba0000; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0000; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0000; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1098e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x164000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138c000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22e000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22e000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8e000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105be000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e2000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa26000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108f8000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1452000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20a000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x208000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f8000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x152000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10598000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x152000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a8000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96c000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x172000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108fa000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x152000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145a000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20a000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9fa000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1059a000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7aa000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96e000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174000; +} + +static void +Opcode_ivp_sv2nx8_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sv2nx8_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc60000; +} + +static void +Opcode_ivp_sv2nx8_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0000; +} + +static void +Opcode_ivp_sv2nx8_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0000; +} + +static void +Opcode_ivp_sv2nx8_i_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ivp_sv2nx8_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_ivp_sv2nx8_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x520000; +} + +static void +Opcode_ivp_sv2nx8_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109b6000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sv2nx8_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139e000; +} + +static void +Opcode_ivp_sv2nx8_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x588000; +} + +static void +Opcode_ivp_sv2nx8_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab6000; +} + +static void +Opcode_ivp_sv2nx8_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4000; +} + +static void +Opcode_ivp_sv2nx8_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7ec000; +} + +static void +Opcode_ivp_sv2nx8_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_ivp_sv2nx8_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10942000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sv2nx8_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14f2000; +} + +static void +Opcode_ivp_sv2nx8_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x568000; +} + +static void +Opcode_ivp_sv2nx8_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa42000; +} + +static void +Opcode_ivp_sv2nx8_x_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c000; +} + +static void +Opcode_ivp_sv2nx8_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7cc000; +} + +static void +Opcode_ivp_sv2nx8_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_ivp_sv2nx8_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10946000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sv2nx8_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14fa000; +} + +static void +Opcode_ivp_sv2nx8_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56a000; +} + +static void +Opcode_ivp_sv2nx8_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa46000; +} + +static void +Opcode_ivp_sv2nx8_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18e000; +} + +static void +Opcode_ivp_sv2nx8_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7ce000; +} + +static void +Opcode_ivp_sv2nx8_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa12000; +} + +static void +Opcode_ivp_ssnx16_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10898000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssnx16_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1218000; +} + +static void +Opcode_ivp_ssnx16_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x520000; +} + +static void +Opcode_ivp_ssnx16_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x998000; +} + +static void +Opcode_ivp_ssnx16_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109a6000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssnx16_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13bc000; +} + +static void +Opcode_ivp_ssnx16_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ivp_ssnx16_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa6000; +} + +static void +Opcode_ivp_ssnx16_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10922000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssnx16_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14b2000; +} + +static void +Opcode_ivp_ssnx16_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x558000; +} + +static void +Opcode_ivp_ssnx16_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa22000; +} + +static void +Opcode_ivp_ssnx16_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10926000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssnx16_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14ba000; +} + +static void +Opcode_ivp_ssnx16_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x55a000; +} + +static void +Opcode_ivp_ssnx16_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa26000; +} + +static void +Opcode_ivp_movva16_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc006; +} + +static void +Opcode_ivp_movva16_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282004; +} + +static void +Opcode_ivp_movva16_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282004; +} + +static void +Opcode_ivp_movva16_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8004; +} + +static void +Opcode_ivp_movva16_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8004; +} + +static void +Opcode_ivp_movva16_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6006; +} + +static void +Opcode_ivp_movvv_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a300a0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movvv_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27500c0e; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movvv_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11080e0; +} + +static void +Opcode_ivp_movvv_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf70060; +} + +static void +Opcode_ivp_movvv_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330700e; +} + +static void +Opcode_ivp_movvv_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f60006; +} + +static void +Opcode_ivp_movvv_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f07208; +} + +static void +Opcode_ivp_movvv_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8340e0; +} + +static void +Opcode_ivp_movvv_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94801c9; +} + +static void +Opcode_ivp_movvv_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a80c0; +} + +static void +Opcode_ivp_movvv_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606c0a; +} + +static void +Opcode_ivp_movvv_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20204; +} + +static void +Opcode_ivp_movvv_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8080; +} + +static void +Opcode_ivp_movvv_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d20c0; +} + +static void +Opcode_ivp_movvv_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2707140; +} + +static void +Opcode_ivp_movvv_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220c0; +} + +static void +Opcode_ivp_movvv_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500009; +} + +static void +Opcode_ivp_movvv_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa602c0; +} + +static void +Opcode_ivp_sllinx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21500c08; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sllinx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe78000; +} + +static void +Opcode_ivp_sllinx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300400e; +} + +static void +Opcode_ivp_sllinx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c84000; +} + +static void +Opcode_ivp_sllinx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04208; +} + +static void +Opcode_ivp_sllinx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940008e; +} + +static void +Opcode_ivp_sllinx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606008; +} + +static void +Opcode_ivp_sllinx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00200; +} + +static void +Opcode_ivp_sllinx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2404140; +} + +static void +Opcode_ivp_slsinx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23500c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_slsinx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe70008; +} + +static void +Opcode_ivp_slsinx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x310000e; +} + +static void +Opcode_ivp_slsinx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04000; +} + +static void +Opcode_ivp_slsinx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00208; +} + +static void +Opcode_ivp_slsinx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940000f; +} + +static void +Opcode_ivp_slsinx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606400; +} + +static void +Opcode_ivp_slsinx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd08000; +} + +static void +Opcode_ivp_slsinx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500140; +} + +static void +Opcode_ivp_srainx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srainx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23500c08; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srainx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1378000; +} + +static void +Opcode_ivp_srainx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe78008; +} + +static void +Opcode_ivp_srainx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x310400e; +} + +static void +Opcode_ivp_srainx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d84000; +} + +static void +Opcode_ivp_srainx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04208; +} + +static void +Opcode_ivp_srainx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0000; +} + +static void +Opcode_ivp_srainx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940008f; +} + +static void +Opcode_ivp_srainx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606408; +} + +static void +Opcode_ivp_srainx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd08200; +} + +static void +Opcode_ivp_srainx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2504140; +} + +static void +Opcode_ivp_srlinx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108c4000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srlinx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25500c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srlinx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1378200; +} + +static void +Opcode_ivp_srlinx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ivp_srlinx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000e; +} + +static void +Opcode_ivp_srlinx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04400; +} + +static void +Opcode_ivp_srlinx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00208; +} + +static void +Opcode_ivp_srlinx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c4000; +} + +static void +Opcode_ivp_srlinx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9480008; +} + +static void +Opcode_ivp_srlinx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606800; +} + +static void +Opcode_ivp_srlinx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_ivp_srlinx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2600140; +} + +static void +Opcode_ivp_sllnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e503800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sllnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500008; +} + +static void +Opcode_ivp_sllnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0030e; +} + +static void +Opcode_ivp_sllnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9700005; +} + +static void +Opcode_ivp_sllnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e406c00; +} + +static void +Opcode_ivp_sllnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc78000; +} + +static void +Opcode_ivp_sllnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29003e0; +} + +static void +Opcode_ivp_srlnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srlnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360000a; +} + +static void +Opcode_ivp_srlnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00202; +} + +static void +Opcode_ivp_srlnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9780006; +} + +static void +Opcode_ivp_srlnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e507000; +} + +static void +Opcode_ivp_srlnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ivp_srlnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2600000; +} + +static void +Opcode_ivp_slanx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38503800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_slanx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200008; +} + +static void +Opcode_ivp_slanx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0030e; +} + +static void +Opcode_ivp_slanx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9700002; +} + +static void +Opcode_ivp_slanx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e406000; +} + +static void +Opcode_ivp_slanx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc60000; +} + +static void +Opcode_ivp_slanx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e003c0; +} + +static void +Opcode_ivp_sranx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sranx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000a; +} + +static void +Opcode_ivp_sranx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00200; +} + +static void +Opcode_ivp_sranx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9780003; +} + +static void +Opcode_ivp_sranx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e506400; +} + +static void +Opcode_ivp_sranx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca8000; +} + +static void +Opcode_ivp_sranx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f003e0; +} + +static void +Opcode_ivp_slsnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c503c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_slsnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000a; +} + +static void +Opcode_ivp_slsnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00200; +} + +static void +Opcode_ivp_slsnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9780000; +} + +static void +Opcode_ivp_slsnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e407800; +} + +static void +Opcode_ivp_slsnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90000; +} + +static void +Opcode_ivp_slsnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c003e0; +} + +static void +Opcode_ivp_srsnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srsnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000c; +} + +static void +Opcode_ivp_srsnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00204; +} + +static void +Opcode_ivp_srsnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400008; +} + +static void +Opcode_ivp_srsnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e507800; +} + +static void +Opcode_ivp_srsnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd0000; +} + +static void +Opcode_ivp_srsnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400020; +} + +static void +Opcode_ivp_xor2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38502000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_xor2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1360000; +} + +static void +Opcode_ivp_xor2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda0000; +} + +static void +Opcode_ivp_xor2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100304; +} + +static void +Opcode_ivp_xor2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000b; +} + +static void +Opcode_ivp_xor2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00308; +} + +static void +Opcode_ivp_xor2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f0000e; +} + +static void +Opcode_ivp_xor2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0000; +} + +static void +Opcode_ivp_xor2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e307000; +} + +static void +Opcode_ivp_xor2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ivp_xor2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0000; +} + +static void +Opcode_ivp_xor2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a003a0; +} + +static void +Opcode_ivp_and2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a402c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_and2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1278000; +} + +static void +Opcode_ivp_and2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc78000; +} + +static void +Opcode_ivp_and2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0020a; +} + +static void +Opcode_ivp_and2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00016; +} + +static void +Opcode_ivp_and2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0010a; +} + +static void +Opcode_ivp_and2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e8000b; +} + +static void +Opcode_ivp_and2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c8000; +} + +static void +Opcode_ivp_and2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e007400; +} + +static void +Opcode_ivp_and2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb58000; +} + +static void +Opcode_ivp_and2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c8000; +} + +static void +Opcode_ivp_and2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d00280; +} + +static void +Opcode_ivp_or2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e403800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_or2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338000; +} + +static void +Opcode_ivp_or2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd78000; +} + +static void +Opcode_ivp_or2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x310020a; +} + +static void +Opcode_ivp_or2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0001a; +} + +static void +Opcode_ivp_or2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0020c; +} + +static void +Opcode_ivp_or2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e8000d; +} + +static void +Opcode_ivp_or2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x578000; +} + +static void +Opcode_ivp_or2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e207c00; +} + +static void +Opcode_ivp_or2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc18000; +} + +static void +Opcode_ivp_or2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x478000; +} + +static void +Opcode_ivp_or2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d00380; +} + +static void +Opcode_ivp_not2nx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a34010; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_not2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30602c02; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_not2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500210; +} + +static void +Opcode_ivp_not2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf480c0; +} + +static void +Opcode_ivp_not2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801106; +} + +static void +Opcode_ivp_not2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f68010; +} + +static void +Opcode_ivp_not2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001106; +} + +static void +Opcode_ivp_not2nx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb08010; +} + +static void +Opcode_ivp_not2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9580023; +} + +static void +Opcode_ivp_not2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8160; +} + +static void +Opcode_ivp_not2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606d0c; +} + +static void +Opcode_ivp_not2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20308; +} + +static void +Opcode_ivp_not2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8120; +} + +static void +Opcode_ivp_not2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000f00; +} + +static void +Opcode_ivp_addnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c402800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_addnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1260000; +} + +static void +Opcode_ivp_addnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc60000; +} + +static void +Opcode_ivp_addnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0020a; +} + +static void +Opcode_ivp_addnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00005; +} + +static void +Opcode_ivp_addnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0010a; +} + +static void +Opcode_ivp_addnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d0000b; +} + +static void +Opcode_ivp_addnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0000; +} + +static void +Opcode_ivp_addnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e006800; +} + +static void +Opcode_ivp_addnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb40000; +} + +static void +Opcode_ivp_addnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0000; +} + +static void +Opcode_ivp_addnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00280; +} + +static void +Opcode_ivp_subnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a403c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_subnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1348000; +} + +static void +Opcode_ivp_subnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd88000; +} + +static void +Opcode_ivp_subnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x310020e; +} + +static void +Opcode_ivp_subnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0001a; +} + +static void +Opcode_ivp_subnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0020e; +} + +static void +Opcode_ivp_subnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e8000f; +} + +static void +Opcode_ivp_subnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x588000; +} + +static void +Opcode_ivp_subnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e306400; +} + +static void +Opcode_ivp_subnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc28000; +} + +static void +Opcode_ivp_subnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x488000; +} + +static void +Opcode_ivp_subnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f00380; +} + +static void +Opcode_ivp_negnx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a300c0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27500e0e; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11082c0; +} + +static void +Opcode_ivp_negnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40080; +} + +static void +Opcode_ivp_negnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330780e; +} + +static void +Opcode_ivp_negnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f60007; +} + +static void +Opcode_ivp_negnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f07a08; +} + +static void +Opcode_ivp_negnx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8380e0; +} + +static void +Opcode_ivp_negnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94801e9; +} + +static void +Opcode_ivp_negnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8100; +} + +static void +Opcode_ivp_negnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606e0a; +} + +static void +Opcode_ivp_negnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20206; +} + +static void +Opcode_ivp_negnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a80c0; +} + +static void +Opcode_ivp_negnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2707940; +} + +static void +Opcode_ivp_minnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a403000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_minnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f8000; +} + +static void +Opcode_ivp_minnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd28000; +} + +static void +Opcode_ivp_minnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0020e; +} + +static void +Opcode_ivp_minnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190001f; +} + +static void +Opcode_ivp_minnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00202; +} + +static void +Opcode_ivp_minnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d0000f; +} + +static void +Opcode_ivp_minnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x538000; +} + +static void +Opcode_ivp_minnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e107c00; +} + +static void +Opcode_ivp_minnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd8000; +} + +static void +Opcode_ivp_minnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x438000; +} + +static void +Opcode_ivp_minnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b002e0; +} + +static void +Opcode_ivp_minunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c403400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_minunx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1310000; +} + +static void +Opcode_ivp_minunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd50000; +} + +static void +Opcode_ivp_minunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100200; +} + +static void +Opcode_ivp_minunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00009; +} + +static void +Opcode_ivp_minunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00208; +} + +static void +Opcode_ivp_minunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e0000c; +} + +static void +Opcode_ivp_minunx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x550000; +} + +static void +Opcode_ivp_minunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e206800; +} + +static void +Opcode_ivp_minunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf0000; +} + +static void +Opcode_ivp_minunx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x450000; +} + +static void +Opcode_ivp_minunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800380; +} + +static void +Opcode_ivp_maxnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_maxnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c8000; +} + +static void +Opcode_ivp_maxnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd8000; +} + +static void +Opcode_ivp_maxnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290020c; +} + +static void +Opcode_ivp_maxnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190001a; +} + +static void +Opcode_ivp_maxnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290010e; +} + +static void +Opcode_ivp_maxnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000d; +} + +static void +Opcode_ivp_maxnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x508000; +} + +static void +Opcode_ivp_maxnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e106400; +} + +static void +Opcode_ivp_maxnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba8000; +} + +static void +Opcode_ivp_maxnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_ivp_maxnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29002c0; +} + +static void +Opcode_ivp_maxunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c401800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_maxunx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e0000; +} + +static void +Opcode_ivp_maxunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ivp_maxunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0020c; +} + +static void +Opcode_ivp_maxunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000d; +} + +static void +Opcode_ivp_maxunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0010e; +} + +static void +Opcode_ivp_maxunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c8000e; +} + +static void +Opcode_ivp_maxunx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x520000; +} + +static void +Opcode_ivp_maxunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e107000; +} + +static void +Opcode_ivp_maxunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc0000; +} + +static void +Opcode_ivp_maxunx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_ivp_maxunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e002c0; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38403800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1320000; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd60000; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100204; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00009; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0020a; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e0000e; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560000; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e207000; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x460000; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00380; +} + +static void +Opcode_ivp_nsanx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30603802; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_nsanx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380110c; +} + +static void +Opcode_ivp_nsanx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300110c; +} + +static void +Opcode_ivp_nsanx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9580026; +} + +static void +Opcode_ivp_nsanx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606e0c; +} + +static void +Opcode_ivp_nsanx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2020a; +} + +static void +Opcode_ivp_nsanx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000e20; +} + +static void +Opcode_ivp_nsaunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30602102; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_nsaunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801500; +} + +static void +Opcode_ivp_nsaunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001500; +} + +static void +Opcode_ivp_nsaunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9580030; +} + +static void +Opcode_ivp_nsaunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606c0e; +} + +static void +Opcode_ivp_nsaunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2020c; +} + +static void +Opcode_ivp_nsaunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000c40; +} + +static void +Opcode_ivp_ltnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x338000; +} + +static void +Opcode_ivp_ltnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b0400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ltnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400800; +} + +static void +Opcode_ivp_ltnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec1400; +} + +static void +Opcode_ivp_ltnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a0308; +} + +static void +Opcode_ivp_ltnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04808; +} + +static void +Opcode_ivp_ltnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a0208; +} + +static void +Opcode_ivp_ltnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000; +} + +static void +Opcode_ivp_ltnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9050008; +} + +static void +Opcode_ivp_ltnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c2800; +} + +static void +Opcode_ivp_ltnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c424000; +} + +static void +Opcode_ivp_ltnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000; +} + +static void +Opcode_ivp_ltnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd42800; +} + +static void +Opcode_ivp_ltnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3820000; +} + +static void +Opcode_ivp_ltnx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x738000; +} + +static void +Opcode_ivp_ltnx16_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x981800; +} + +static void +Opcode_ivp_lenx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x234008; +} + +static void +Opcode_ivp_lenx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305a9000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lenx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1481800; +} + +static void +Opcode_ivp_lenx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0800; +} + +static void +Opcode_ivp_lenx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0302; +} + +static void +Opcode_ivp_lenx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04c00; +} + +static void +Opcode_ivp_lenx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0202; +} + +static void +Opcode_ivp_lenx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0008; +} + +static void +Opcode_ivp_lenx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9904008; +} + +static void +Opcode_ivp_lenx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c1000; +} + +static void +Opcode_ivp_lenx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c415000; +} + +static void +Opcode_ivp_lenx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0008; +} + +static void +Opcode_ivp_lenx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd41000; +} + +static void +Opcode_ivp_lenx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3810020; +} + +static void +Opcode_ivp_lenx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x634008; +} + +static void +Opcode_ivp_lenx16_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x971000; +} + +static void +Opcode_ivp_eqnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b4000; +} + +static void +Opcode_ivp_eqnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305a8400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_eqnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c0400; +} + +static void +Opcode_ivp_eqnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec4000; +} + +static void +Opcode_ivp_eqnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a8306; +} + +static void +Opcode_ivp_eqnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04810; +} + +static void +Opcode_ivp_eqnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a8206; +} + +static void +Opcode_ivp_eqnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000; +} + +static void +Opcode_ivp_eqnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b84000; +} + +static void +Opcode_ivp_eqnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0400; +} + +static void +Opcode_ivp_eqnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c50d000; +} + +static void +Opcode_ivp_eqnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000; +} + +static void +Opcode_ivp_eqnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40400; +} + +static void +Opcode_ivp_eqnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3808060; +} + +static void +Opcode_ivp_eqnx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b4000; +} + +static void +Opcode_ivp_eqnx16_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970400; +} + +static void +Opcode_ivp_neqnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23c000; +} + +static void +Opcode_ivp_neqnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b1000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_neqnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c0800; +} + +static void +Opcode_ivp_neqnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec2000; +} + +static void +Opcode_ivp_neqnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b030a; +} + +static void +Opcode_ivp_neqnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05000; +} + +static void +Opcode_ivp_neqnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b020a; +} + +static void +Opcode_ivp_neqnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_ivp_neqnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90d8008; +} + +static void +Opcode_ivp_neqnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c4000; +} + +static void +Opcode_ivp_neqnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c435000; +} + +static void +Opcode_ivp_neqnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_ivp_neqnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd44000; +} + +static void +Opcode_ivp_neqnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3830020; +} + +static void +Opcode_ivp_neqnx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63c000; +} + +static void +Opcode_ivp_neqnx16_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a0000; +} + +static void +Opcode_ivp_ltunx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b8008; +} + +static void +Opcode_ivp_ltunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b8800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ltunx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1440c00; +} + +static void +Opcode_ivp_ltunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec5800; +} + +static void +Opcode_ivp_ltunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8308; +} + +static void +Opcode_ivp_ltunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04c18; +} + +static void +Opcode_ivp_ltunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8208; +} + +static void +Opcode_ivp_ltunx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4008; +} + +static void +Opcode_ivp_ltunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x905c008; +} + +static void +Opcode_ivp_ltunx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c3400; +} + +static void +Opcode_ivp_ltunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c43c000; +} + +static void +Opcode_ivp_ltunx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4008; +} + +static void +Opcode_ivp_ltunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd43400; +} + +static void +Opcode_ivp_ltunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3838000; +} + +static void +Opcode_ivp_ltunx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b8008; +} + +static void +Opcode_ivp_ltunx16_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x991400; +} + +static void +Opcode_ivp_leunx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b4008; +} + +static void +Opcode_ivp_leunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305a9c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_leunx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c1400; +} + +static void +Opcode_ivp_leunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec4c00; +} + +static void +Opcode_ivp_leunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8304; +} + +static void +Opcode_ivp_leunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04c10; +} + +static void +Opcode_ivp_leunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8204; +} + +static void +Opcode_ivp_leunx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc008; +} + +static void +Opcode_ivp_leunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a84008; +} + +static void +Opcode_ivp_leunx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c1c00; +} + +static void +Opcode_ivp_leunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c51c000; +} + +static void +Opcode_ivp_leunx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc008; +} + +static void +Opcode_ivp_leunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd41c00; +} + +static void +Opcode_ivp_leunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3818040; +} + +static void +Opcode_ivp_leunx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b4008; +} + +static void +Opcode_ivp_leunx16_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x971c00; +} + +static void +Opcode_ivp_raddnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502020; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000045; +} + +static void +Opcode_ivp_raddnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800345; +} + +static void +Opcode_ivp_raddnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c02800; +} + +static void +Opcode_ivp_raddnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607850; +} + +static void +Opcode_ivp_raddnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd880f0; +} + +static void +Opcode_ivp_raddnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c001b6; +} + +static void +Opcode_ivp_rmaxnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502430; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rmaxnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100055; +} + +static void +Opcode_ivp_rmaxnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900355; +} + +static void +Opcode_ivp_rmaxnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c82a00; +} + +static void +Opcode_ivp_rmaxnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607c60; +} + +static void +Opcode_ivp_rmaxnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb00f0; +} + +static void +Opcode_ivp_rmaxnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e001b7; +} + +static void +Opcode_ivp_rminnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502830; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rminnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200055; +} + +static void +Opcode_ivp_rminnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00355; +} + +static void +Opcode_ivp_rminnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d02a00; +} + +static void +Opcode_ivp_rminnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607861; +} + +static void +Opcode_ivp_rminnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30010; +} + +static void +Opcode_ivp_rminnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001c5; +} + +static void +Opcode_ivp_rmaxunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502431; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rmaxunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100075; +} + +static void +Opcode_ivp_rmaxunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900375; +} + +static void +Opcode_ivp_rmaxunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c82e00; +} + +static void +Opcode_ivp_rmaxunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607841; +} + +static void +Opcode_ivp_rmaxunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30000; +} + +static void +Opcode_ivp_rmaxunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f001b7; +} + +static void +Opcode_ivp_rminunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502831; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rminunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200075; +} + +static void +Opcode_ivp_rminunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00375; +} + +static void +Opcode_ivp_rminunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d02e00; +} + +static void +Opcode_ivp_rminunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607c41; +} + +static void +Opcode_ivp_rminunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30020; +} + +static void +Opcode_ivp_rminunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001c7; +} + +static void +Opcode_ivp_rbminnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800c01; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rbminnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000043; +} + +static void +Opcode_ivp_rbminnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800343; +} + +static void +Opcode_ivp_rbminnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9500408; +} + +static void +Opcode_ivp_rbminnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607080; +} + +static void +Opcode_ivp_rbminnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80080; +} + +static void +Opcode_ivp_rbminnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800197; +} + +static void +Opcode_ivp_rbmaxnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800ce0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rbmaxnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000062; +} + +static void +Opcode_ivp_rbmaxnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800362; +} + +static void +Opcode_ivp_rbmaxnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9500008; +} + +static void +Opcode_ivp_rbmaxnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607040; +} + +static void +Opcode_ivp_rbmaxnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80060; +} + +static void +Opcode_ivp_rbmaxnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800195; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800004; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00008; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800304; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8700000; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c302000; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_bmaxnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800340; +} + +static void +Opcode_ivp_bminnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20800c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bminnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780000; +} + +static void +Opcode_ivp_bminnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_bminnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800100; +} + +static void +Opcode_ivp_bminnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00008; +} + +static void +Opcode_ivp_bminnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800000; +} + +static void +Opcode_ivp_bminnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000000; +} + +static void +Opcode_ivp_bminnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ivp_bminnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c600000; +} + +static void +Opcode_ivp_bminnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ivp_bminnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_bminnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800380; +} + +static void +Opcode_ivp_mov2nx8t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38306000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mov2nx8t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ivp_mov2nx8t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880000; +} + +static void +Opcode_ivp_mov2nx8t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00200; +} + +static void +Opcode_ivp_mov2nx8t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300008; +} + +static void +Opcode_ivp_mov2nx8t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400300; +} + +static void +Opcode_ivp_mov2nx8t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00000; +} + +static void +Opcode_ivp_mov2nx8t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c702000; +} + +static void +Opcode_ivp_mov2nx8t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980000; +} + +static void +Opcode_ivp_mov2nx8t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800340; +} + +static void +Opcode_ivp_mulanx16packl_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0001d; +} + +static void +Opcode_ivp_mulanx16packl_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380008; +} + +static void +Opcode_ivp_mulanx16packq_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0001e; +} + +static void +Opcode_ivp_mulanx16packq_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000a; +} + +static void +Opcode_ivp_mulsnx16packl_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0001f; +} + +static void +Opcode_ivp_mulsnx16packl_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000e; +} + +static void +Opcode_ivp_mulsnx16packq_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0001f; +} + +static void +Opcode_ivp_mulsnx16packq_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400004; +} + +static void +Opcode_ivp_addsnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38402c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_addsnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1270000; +} + +static void +Opcode_ivp_addsnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc70000; +} + +static void +Opcode_ivp_addsnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0020a; +} + +static void +Opcode_ivp_addsnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00006; +} + +static void +Opcode_ivp_addsnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0010a; +} + +static void +Opcode_ivp_addsnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e0000b; +} + +static void +Opcode_ivp_addsnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ivp_addsnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e007000; +} + +static void +Opcode_ivp_addsnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb50000; +} + +static void +Opcode_ivp_addsnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ivp_addsnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c00280; +} + +static void +Opcode_ivp_subsnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e403c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_subsnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1358000; +} + +static void +Opcode_ivp_subsnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd98000; +} + +static void +Opcode_ivp_subsnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100302; +} + +static void +Opcode_ivp_subsnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0001b; +} + +static void +Opcode_ivp_subsnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900308; +} + +static void +Opcode_ivp_subsnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f0000d; +} + +static void +Opcode_ivp_subsnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x598000; +} + +static void +Opcode_ivp_subsnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e306c00; +} + +static void +Opcode_ivp_subsnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc38000; +} + +static void +Opcode_ivp_subsnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x498000; +} + +static void +Opcode_ivp_subsnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29003a0; +} + +static void +Opcode_ivp_negsnx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a34000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negsnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30602802; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negsnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500200; +} + +static void +Opcode_ivp_negsnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf400c0; +} + +static void +Opcode_ivp_negsnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801104; +} + +static void +Opcode_ivp_negsnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f68000; +} + +static void +Opcode_ivp_negsnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001104; +} + +static void +Opcode_ivp_negsnx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb08000; +} + +static void +Opcode_ivp_negsnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9580022; +} + +static void +Opcode_ivp_negsnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8140; +} + +static void +Opcode_ivp_negsnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606c0c; +} + +static void +Opcode_ivp_negsnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20208; +} + +static void +Opcode_ivp_negsnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8100; +} + +static void +Opcode_ivp_negsnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000e00; +} + +static void +Opcode_ivp_lv2nx8t_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10100000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lv2nx8t_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_lv2nx8t_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_lv2nx8t_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10100000; +} + +static void +Opcode_ivp_lv2nx8t_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_lv2nx8t_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_lv2nx8t_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10730000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lv2nx8t_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfb0000; +} + +static void +Opcode_ivp_lv2nx8t_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_ivp_lv2nx8t_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10490000; +} + +static void +Opcode_ivp_lv2nx8t_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ivp_lv2nx8t_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_ivp_lv2nx8t_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10580000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lv2nx8t_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ivp_lv2nx8t_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ivp_lv2nx8t_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10380000; +} + +static void +Opcode_ivp_lv2nx8t_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ivp_lv2nx8t_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0000; +} + +static void +Opcode_ivp_lv2nx8t_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10590000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lv2nx8t_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe10000; +} + +static void +Opcode_ivp_lv2nx8t_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_ivp_lv2nx8t_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10390000; +} + +static void +Opcode_ivp_lv2nx8t_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510000; +} + +static void +Opcode_ivp_lv2nx8t_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0000; +} + +static void +Opcode_ivp_sv2nx8t_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10240000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sv2nx8t_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ivp_sv2nx8t_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_sv2nx8t_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ivp_sv2nx8t_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ivp_sv2nx8t_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ivp_sv2nx8t_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sv2nx8t_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ivp_sv2nx8t_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_ivp_sv2nx8t_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780000; +} + +static void +Opcode_ivp_sv2nx8t_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0000; +} + +static void +Opcode_ivp_sv2nx8t_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880000; +} + +static void +Opcode_ivp_sv2nx8t_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10620000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sv2nx8t_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0000; +} + +static void +Opcode_ivp_sv2nx8t_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ivp_sv2nx8t_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620000; +} + +static void +Opcode_ivp_sv2nx8t_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0000; +} + +static void +Opcode_ivp_sv2nx8t_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740000; +} + +static void +Opcode_ivp_sv2nx8t_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10630000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sv2nx8t_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0000; +} + +static void +Opcode_ivp_sv2nx8t_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x390000; +} + +static void +Opcode_ivp_sv2nx8t_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_ivp_sv2nx8t_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0000; +} + +static void +Opcode_ivp_sv2nx8t_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750000; +} + +static void +Opcode_ivp_raddnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800c90; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000051; +} + +static void +Opcode_ivp_raddnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800351; +} + +static void +Opcode_ivp_raddnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01200; +} + +static void +Opcode_ivp_raddnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e304820; +} + +static void +Opcode_ivp_raddnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80010; +} + +static void +Opcode_ivp_raddnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800184; +} + +static void +Opcode_ivp_rmaxnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800c21; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rmaxnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000063; +} + +static void +Opcode_ivp_rmaxnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800363; +} + +static void +Opcode_ivp_rmaxnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01c00; +} + +static void +Opcode_ivp_rmaxnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6070c0; +} + +static void +Opcode_ivp_rmaxnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd800a0; +} + +static void +Opcode_ivp_rmaxnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001a5; +} + +static void +Opcode_ivp_rminnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800c41; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rminnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000044; +} + +static void +Opcode_ivp_rminnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800344; +} + +static void +Opcode_ivp_rminnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c02000; +} + +static void +Opcode_ivp_rminnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607800; +} + +static void +Opcode_ivp_rminnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd800c0; +} + +static void +Opcode_ivp_rminnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001a7; +} + +static void +Opcode_ivp_rmaxunx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800c31; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rmaxunx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000073; +} + +static void +Opcode_ivp_rmaxunx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800373; +} + +static void +Opcode_ivp_rmaxunx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01e00; +} + +static void +Opcode_ivp_rmaxunx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6070e0; +} + +static void +Opcode_ivp_rmaxunx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd800b0; +} + +static void +Opcode_ivp_rmaxunx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001a6; +} + +static void +Opcode_ivp_rminunx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800c51; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rminunx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000054; +} + +static void +Opcode_ivp_rminunx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800354; +} + +static void +Opcode_ivp_rminunx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c02200; +} + +static void +Opcode_ivp_rminunx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607820; +} + +static void +Opcode_ivp_rminunx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd800d0; +} + +static void +Opcode_ivp_rminunx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001b4; +} + +static void +Opcode_ivp_addnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36402000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_addnx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ivp_addnx16t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_addnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700000; +} + +static void +Opcode_ivp_addnx16t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00010; +} + +static void +Opcode_ivp_addnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300100; +} + +static void +Opcode_ivp_addnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8800001; +} + +static void +Opcode_ivp_addnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c201000; +} + +static void +Opcode_ivp_addnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ivp_addnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800220; +} + +static void +Opcode_ivp_subnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c306000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_subnx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa80000; +} + +static void +Opcode_ivp_subnx16t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ivp_subnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00200; +} + +static void +Opcode_ivp_subnx16t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ivp_subnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2600300; +} + +static void +Opcode_ivp_subnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00002; +} + +static void +Opcode_ivp_subnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c004000; +} + +static void +Opcode_ivp_subnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ivp_subnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800080; +} + +static void +Opcode_ivp_negnx16t_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a04000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30600002; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negnx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0220; +} + +static void +Opcode_ivp_negnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801000; +} + +static void +Opcode_ivp_negnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001000; +} + +static void +Opcode_ivp_negnx16t_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x808080; +} + +static void +Opcode_ivp_negnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c00101; +} + +static void +Opcode_ivp_negnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c604000; +} + +static void +Opcode_ivp_negnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ivp_negnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801100; +} + +static void +Opcode_ivp_maxnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34304000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_maxnx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ivp_maxnx16t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ivp_maxnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2600200; +} + +static void +Opcode_ivp_maxnx16t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000008; +} + +static void +Opcode_ivp_maxnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2600000; +} + +static void +Opcode_ivp_maxnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8800006; +} + +static void +Opcode_ivp_maxnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c502000; +} + +static void +Opcode_ivp_maxnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880000; +} + +static void +Opcode_ivp_maxnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800100; +} + +static void +Opcode_ivp_minnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30306000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_minnx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980000; +} + +static void +Opcode_ivp_minnx16t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780000; +} + +static void +Opcode_ivp_minnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800200; +} + +static void +Opcode_ivp_minnx16t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ivp_minnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400200; +} + +static void +Opcode_ivp_minnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880000c; +} + +static void +Opcode_ivp_minnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c602000; +} + +static void +Opcode_ivp_minnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ivp_minnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800240; +} + +static void +Opcode_ivp_maxunx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a304000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_maxunx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940000; +} + +static void +Opcode_ivp_maxunx16t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ivp_maxunx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500300; +} + +static void +Opcode_ivp_maxunx16t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100018; +} + +static void +Opcode_ivp_maxunx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500100; +} + +static void +Opcode_ivp_maxunx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8800009; +} + +static void +Opcode_ivp_maxunx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c503000; +} + +static void +Opcode_ivp_maxunx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000; +} + +static void +Opcode_ivp_maxunx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800160; +} + +static void +Opcode_ivp_minunx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36306000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_minunx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0000; +} + +static void +Opcode_ivp_minunx16t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840000; +} + +static void +Opcode_ivp_minunx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00200; +} + +static void +Opcode_ivp_minunx16t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200018; +} + +static void +Opcode_ivp_minunx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700200; +} + +static void +Opcode_ivp_minunx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880000f; +} + +static void +Opcode_ivp_minunx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c603000; +} + +static void +Opcode_ivp_minunx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940000; +} + +static void +Opcode_ivp_minunx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800320; +} + +static void +Opcode_ivp_mulanx16packlt_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500010; +} + +static void +Opcode_ivp_mulanx16packqt_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400018; +} + +static void +Opcode_ivp_addsnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36406000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_addsnx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ivp_addsnx16t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ivp_addsnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700100; +} + +static void +Opcode_ivp_addsnx16t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00010; +} + +static void +Opcode_ivp_addsnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300300; +} + +static void +Opcode_ivp_addsnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8800003; +} + +static void +Opcode_ivp_addsnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c301000; +} + +static void +Opcode_ivp_addsnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ivp_addsnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800260; +} + +static void +Opcode_ivp_subsnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38400000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_subsnx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_ivp_subsnx16t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980000; +} + +static void +Opcode_ivp_subsnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800300; +} + +static void +Opcode_ivp_subsnx16t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ivp_subsnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800200; +} + +static void +Opcode_ivp_subsnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00004; +} + +static void +Opcode_ivp_subsnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c104000; +} + +static void +Opcode_ivp_subsnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa80000; +} + +static void +Opcode_ivp_subsnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000c0; +} + +static void +Opcode_ivp_negsnx16t_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a08080; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negsnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30600302; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negsnx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100050; +} + +static void +Opcode_ivp_negsnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801c00; +} + +static void +Opcode_ivp_negsnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001c00; +} + +static void +Opcode_ivp_negsnx16t_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x814080; +} + +static void +Opcode_ivp_negsnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c00131; +} + +static void +Opcode_ivp_negsnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c604100; +} + +static void +Opcode_ivp_negsnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0100; +} + +static void +Opcode_ivp_negsnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801d00; +} + +static void +Opcode_ivp_lalign_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a40000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lalign_i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4000; +} + +static void +Opcode_ivp_lalign_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ivp_lalign_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_lalign_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ivp_lalign_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_lalign_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_ivp_lalign_i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198000; +} + +static void +Opcode_ivp_lalign_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600000; +} + +static void +Opcode_ivp_lalign_i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198000; +} + +static void +Opcode_ivp_lalign_i_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9000; +} + +static void +Opcode_ivp_lalign_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840000; +} + +static void +Opcode_ivp_lalign_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa80000; +} + +static void +Opcode_ivp_lalign_i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8000; +} + +static void +Opcode_ivp_lalign_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a40200; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lalign_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4400; +} + +static void +Opcode_ivp_lalign_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500400; +} + +static void +Opcode_ivp_lalign_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280400; +} + +static void +Opcode_ivp_lalign_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0f00; +} + +static void +Opcode_ivp_lalign_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280400; +} + +static void +Opcode_ivp_lalign_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d9800; +} + +static void +Opcode_ivp_lalign_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_ivp_lalign_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600100; +} + +static void +Opcode_ivp_lalign_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198400; +} + +static void +Opcode_ivp_lalign_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8000; +} + +static void +Opcode_ivp_lalign_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840200; +} + +static void +Opcode_ivp_lalign_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f8800; +} + +static void +Opcode_ivp_lalign_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8400; +} + +static void +Opcode_ivp_salign_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a40100; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_salign_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500100; +} + +static void +Opcode_ivp_salign_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_ivp_salign_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00100; +} + +static void +Opcode_ivp_salign_i_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9040; +} + +static void +Opcode_ivp_salign_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840100; +} + +static void +Opcode_ivp_salign_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa80400; +} + +static void +Opcode_ivp_salign_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a40300; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_salign_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500500; +} + +static void +Opcode_ivp_salign_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8f00; +} + +static void +Opcode_ivp_salign_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d9900; +} + +static void +Opcode_ivp_salign_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8100; +} + +static void +Opcode_ivp_salign_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840300; +} + +static void +Opcode_ivp_salign_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f8a00; +} + +static void +Opcode_ivp_la_pp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a200f0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_la_pp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4600; +} + +static void +Opcode_ivp_la_pp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500250; +} + +static void +Opcode_ivp_la_pp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280500; +} + +static void +Opcode_ivp_la_pp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600300; +} + +static void +Opcode_ivp_la_pp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280500; +} + +static void +Opcode_ivp_la_pp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8310d0; +} + +static void +Opcode_ivp_la_pp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0100; +} + +static void +Opcode_ivp_la_pp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f1070; +} + +static void +Opcode_ivp_la_pp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198500; +} + +static void +Opcode_ivp_la_pp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8200; +} + +static void +Opcode_ivp_la_pp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x850300; +} + +static void +Opcode_ivp_la_pp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa602e0; +} + +static void +Opcode_ivp_la_pp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8600; +} + +static void +Opcode_ivp_sapos_fp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a201f0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sapos_fp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500350; +} + +static void +Opcode_ivp_sapos_fp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600310; +} + +static void +Opcode_ivp_sapos_fp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8311d0; +} + +static void +Opcode_ivp_sapos_fp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8210; +} + +static void +Opcode_ivp_sapos_fp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x850310; +} + +static void +Opcode_ivp_sapos_fp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa606e0; +} + +static void +Opcode_ivp_malign_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a202f0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_malign_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4700; +} + +static void +Opcode_ivp_malign_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500650; +} + +static void +Opcode_ivp_malign_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280510; +} + +static void +Opcode_ivp_malign_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600330; +} + +static void +Opcode_ivp_malign_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280510; +} + +static void +Opcode_ivp_malign_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8318d0; +} + +static void +Opcode_ivp_malign_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0110; +} + +static void +Opcode_ivp_malign_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f1470; +} + +static void +Opcode_ivp_malign_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198510; +} + +static void +Opcode_ivp_malign_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b020; +} + +static void +Opcode_ivp_malign_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000; +} + +static void +Opcode_ivp_malign_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8220; +} + +static void +Opcode_ivp_malign_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x850320; +} + +static void +Opcode_ivp_malign_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f90f0; +} + +static void +Opcode_ivp_malign_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8700; +} + +static void +Opcode_ivp_zalign_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a202f4; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_zalign_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500654; +} + +static void +Opcode_ivp_zalign_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600334; +} + +static void +Opcode_ivp_zalign_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8318d1; +} + +static void +Opcode_ivp_zalign_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f1474; +} + +static void +Opcode_ivp_zalign_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b030; +} + +static void +Opcode_ivp_zalign_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8224; +} + +static void +Opcode_ivp_zalign_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x850324; +} + +static void +Opcode_ivp_zalign_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f90f1; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83b0070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce000; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1110090; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x284000; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x284000; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830090; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198010; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0030; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60000; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_ivp_sa2nx8_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83d8070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sa2nx8_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11180b0; +} + +static void +Opcode_ivp_sa2nx8_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0030; +} + +static void +Opcode_ivp_sa2nx8_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8380b0; +} + +static void +Opcode_ivp_sa2nx8_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0050; +} + +static void +Opcode_ivp_sa2nx8_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820050; +} + +static void +Opcode_ivp_sa2nx8_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60050; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10808000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x186000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1088000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x182000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x182000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x908000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10518000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x758000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x908000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ivp_sav2nx8_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10830000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sav2nx8_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0000; +} + +static void +Opcode_ivp_sav2nx8_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f0000; +} + +static void +Opcode_ivp_sav2nx8_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_ivp_sav2nx8_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ivp_sav2nx8_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780000; +} + +static void +Opcode_ivp_sav2nx8_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_ivp_selnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32400000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_selnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2100000; +} + +static void +Opcode_ivp_selnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2100000; +} + +static void +Opcode_ivp_selnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2100000; +} + +static void +Opcode_ivp_shflnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30600100; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_shflnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800400; +} + +static void +Opcode_ivp_shflnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000400; +} + +static void +Opcode_ivp_shflnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000400; +} + +static void +Opcode_ivp_movpint16_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea000; +} + +static void +Opcode_ivp_movpint16_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x252000; +} + +static void +Opcode_ivp_movpint16_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x252000; +} + +static void +Opcode_ivp_movpint16_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x194000; +} + +static void +Opcode_ivp_movpint16_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x194000; +} + +static void +Opcode_ivp_movpint16_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2000; +} + +static void +Opcode_ivp_movpa16_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc004; +} + +static void +Opcode_ivp_movpa16_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6004; +} + +static void +Opcode_ivp_mulnx16packp_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf0000; +} + +static void +Opcode_ivp_mulnx16packp_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0001e; +} + +static void +Opcode_ivp_mulnx16packp_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000c; +} + +static void +Opcode_ivp_mulanx16packp_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000e; +} + +static void +Opcode_ivp_mulanx16packp_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380009; +} + +static void +Opcode_ivp_mulsnx16packp_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000f; +} + +static void +Opcode_ivp_mulsnx16packp_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000f; +} + +static void +Opcode_ivp_mulanx16packpt_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400008; +} + +static void +Opcode_ivp_addmod16u_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cb000; +} + +static void +Opcode_ivp_addmod16u_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23f000; +} + +static void +Opcode_ivp_addmod16u_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d000; +} + +static void +Opcode_ivp_addmod16u_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10400000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc0000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10992000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x166000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1394000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa92000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16e000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c0000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16e000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e4000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa28000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18e000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108fc000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1462000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20e000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9fc000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x156000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1059c000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x156000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7ac000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x176000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108fe000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x156000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x146a000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20e000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9fe000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1059e000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7ae000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa02000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10420000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe0000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10996000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139c000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x232000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x232000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa96000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c2000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e6000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2a000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10902000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1472000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x212000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa02000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a0000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa04000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10906000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x147a000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x214000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x212000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa06000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a2000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c2000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa06000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c000; +} + +static void +Opcode_ivp_svnx8u_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8u_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca0000; +} + +static void +Opcode_ivp_svnx8u_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0000; +} + +static void +Opcode_ivp_svnx8u_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e0000; +} + +static void +Opcode_ivp_svnx8u_i_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ivp_svnx8u_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x460000; +} + +static void +Opcode_ivp_svnx8u_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560000; +} + +static void +Opcode_ivp_svnx8u_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109be000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8u_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ae000; +} + +static void +Opcode_ivp_svnx8u_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58c000; +} + +static void +Opcode_ivp_svnx8u_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabe000; +} + +static void +Opcode_ivp_svnx8u_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8000; +} + +static void +Opcode_ivp_svnx8u_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f0000; +} + +static void +Opcode_ivp_svnx8u_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa34000; +} + +static void +Opcode_ivp_svnx8u_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10952000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8u_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1390000; +} + +static void +Opcode_ivp_svnx8u_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x570000; +} + +static void +Opcode_ivp_svnx8u_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa52000; +} + +static void +Opcode_ivp_svnx8u_x_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x194000; +} + +static void +Opcode_ivp_svnx8u_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d4000; +} + +static void +Opcode_ivp_svnx8u_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa18000; +} + +static void +Opcode_ivp_svnx8u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10956000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1398000; +} + +static void +Opcode_ivp_svnx8u_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x572000; +} + +static void +Opcode_ivp_svnx8u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa56000; +} + +static void +Opcode_ivp_svnx8u_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x196000; +} + +static void +Opcode_ivp_svnx8u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d6000; +} + +static void +Opcode_ivp_svnx8u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1a000; +} + +static void +Opcode_ivp_lvnx8st_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10140000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8st_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ivp_lvnx8st_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_lvnx8st_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10140000; +} + +static void +Opcode_ivp_lvnx8st_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_lvnx8st_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ivp_lvnx8st_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8st_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ivp_lvnx8st_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740000; +} + +static void +Opcode_ivp_lvnx8st_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104a0000; +} + +static void +Opcode_ivp_lvnx8st_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690000; +} + +static void +Opcode_ivp_lvnx8st_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840000; +} + +static void +Opcode_ivp_lvnx8st_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8st_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20000; +} + +static void +Opcode_ivp_lvnx8st_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0000; +} + +static void +Opcode_ivp_lvnx8st_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103a0000; +} + +static void +Opcode_ivp_lvnx8st_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x520000; +} + +static void +Opcode_ivp_lvnx8st_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ivp_lvnx8st_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8st_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30000; +} + +static void +Opcode_ivp_lvnx8st_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0000; +} + +static void +Opcode_ivp_lvnx8st_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103b0000; +} + +static void +Opcode_ivp_lvnx8st_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_ivp_lvnx8st_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0000; +} + +static void +Opcode_ivp_lvnx8ut_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10180000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8ut_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_lvnx8ut_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_lvnx8ut_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10180000; +} + +static void +Opcode_ivp_lvnx8ut_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_lvnx8ut_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_lvnx8ut_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10750000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8ut_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfd0000; +} + +static void +Opcode_ivp_lvnx8ut_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750000; +} + +static void +Opcode_ivp_lvnx8ut_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104b0000; +} + +static void +Opcode_ivp_lvnx8ut_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0000; +} + +static void +Opcode_ivp_lvnx8ut_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x850000; +} + +static void +Opcode_ivp_lvnx8ut_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8ut_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40000; +} + +static void +Opcode_ivp_lvnx8ut_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ivp_lvnx8ut_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103c0000; +} + +static void +Opcode_ivp_lvnx8ut_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ivp_lvnx8ut_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_ivp_lvnx8ut_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8ut_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50000; +} + +static void +Opcode_ivp_lvnx8ut_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d0000; +} + +static void +Opcode_ivp_lvnx8ut_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103d0000; +} + +static void +Opcode_ivp_lvnx8ut_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x550000; +} + +static void +Opcode_ivp_lvnx8ut_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_ivp_svnx8ut_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8ut_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ivp_svnx8ut_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_svnx8ut_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ivp_svnx8ut_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ivp_svnx8ut_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ivp_svnx8ut_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8ut_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1020000; +} + +static void +Opcode_ivp_svnx8ut_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0000; +} + +static void +Opcode_ivp_svnx8ut_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0000; +} + +static void +Opcode_ivp_svnx8ut_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_ivp_svnx8ut_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a0000; +} + +static void +Opcode_ivp_svnx8ut_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10660000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8ut_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee0000; +} + +static void +Opcode_ivp_svnx8ut_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ivp_svnx8ut_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660000; +} + +static void +Opcode_ivp_svnx8ut_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e0000; +} + +static void +Opcode_ivp_svnx8ut_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780000; +} + +static void +Opcode_ivp_svnx8ut_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10670000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8ut_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xef0000; +} + +static void +Opcode_ivp_svnx8ut_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0000; +} + +static void +Opcode_ivp_svnx8ut_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x670000; +} + +static void +Opcode_ivp_svnx8ut_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f0000; +} + +static void +Opcode_ivp_svnx8ut_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x790000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10810000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x184000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x184000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10520000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x760000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10818000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1098000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x186000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x186000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x918000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10528000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x768000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x918000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_ivp_savnx8u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10840000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_savnx8u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ivp_savnx8u_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ivp_savnx8u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940000; +} + +static void +Opcode_ivp_savnx8u_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ivp_savnx8u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x790000; +} + +static void +Opcode_ivp_savnx8u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940000; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83b8070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce010; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1118090; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x286000; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x286000; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x838090; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198030; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f8030; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0020; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0010; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820010; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60010; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8020; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83c0070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce020; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100a0; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x284010; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x284010; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8300a0; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198050; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0040; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0040; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0020; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820020; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60020; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8040; +} + +static void +Opcode_ivp_sanx8u_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83e8070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sanx8u_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1108090; +} + +static void +Opcode_ivp_sanx8u_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0040; +} + +static void +Opcode_ivp_sanx8u_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x828090; +} + +static void +Opcode_ivp_sanx8u_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0070; +} + +static void +Opcode_ivp_sanx8u_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820070; +} + +static void +Opcode_ivp_sanx8u_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60070; +} + +static void +Opcode_ivp_extractbl_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1708d1; +} + +static void +Opcode_ivp_extractbl_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0012; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extractbl_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000190; +} + +static void +Opcode_ivp_extractbl_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261811; +} + +static void +Opcode_ivp_extractbl_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800090; +} + +static void +Opcode_ivp_extractbl_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1802; +} + +static void +Opcode_ivp_extractbl_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9810098; +} + +static void +Opcode_ivp_extractbl_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8809; +} + +static void +Opcode_ivp_extractbl_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c016042; +} + +static void +Opcode_ivp_extractbl_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800181; +} + +static void +Opcode_ivp_extractbl_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3803; +} + +static void +Opcode_ivp_extractbh_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1708d0; +} + +static void +Opcode_ivp_extractbh_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0002; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extractbh_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000180; +} + +static void +Opcode_ivp_extractbh_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261810; +} + +static void +Opcode_ivp_extractbh_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800080; +} + +static void +Opcode_ivp_extractbh_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1002; +} + +static void +Opcode_ivp_extractbh_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9810088; +} + +static void +Opcode_ivp_extractbh_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8009; +} + +static void +Opcode_ivp_extractbh_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c016002; +} + +static void +Opcode_ivp_extractbh_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800081; +} + +static void +Opcode_ivp_extractbh_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3003; +} + +static void +Opcode_ivp_movvint16_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea080; +} + +static void +Opcode_ivp_movvint16_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254000; +} + +static void +Opcode_ivp_movvint16_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254000; +} + +static void +Opcode_ivp_movvint16_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x196000; +} + +static void +Opcode_ivp_movvint16_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x196000; +} + +static void +Opcode_ivp_movvint16_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b4000; +} + +static void +Opcode_ivp_movqint16_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fa000; +} + +static void +Opcode_ivp_movqint16_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x252080; +} + +static void +Opcode_ivp_movqint16_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x252080; +} + +static void +Opcode_ivp_movqint16_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x194010; +} + +static void +Opcode_ivp_movqint16_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x194080; +} + +static void +Opcode_ivp_movqint16_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2080; +} + +static void +Opcode_ivp_movqa16_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc005; +} + +static void +Opcode_ivp_movqa16_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6005; +} + +static void +Opcode_ivp_movvinx16_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc000; +} + +static void +Opcode_ivp_movvinx16_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254080; +} + +static void +Opcode_ivp_movvinx16_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254080; +} + +static void +Opcode_ivp_movvinx16_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa000; +} + +static void +Opcode_ivp_movvinx16_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac000; +} + +static void +Opcode_ivp_movvinx16_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000; +} + +static void +Opcode_ivp_seqnx16_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1760de; +} + +static void +Opcode_ivp_seqnx16_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a05e; +} + +static void +Opcode_ivp_seqnx16_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2820de; +} + +static void +Opcode_ivp_seqnx16_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a0fa; +} + +static void +Opcode_ivp_seqnx16_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b60a5; +} + +static void +Opcode_ivp_seqnx16_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce0ad; +} + +static void +Opcode_ivp_mulnx16packl_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde8000; +} + +static void +Opcode_ivp_mulnx16packl_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000e; +} + +static void +Opcode_ivp_mulnx16packl_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000b; +} + +static void +Opcode_ivp_mulnx16packq_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf8000; +} + +static void +Opcode_ivp_mulnx16packq_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000f; +} + +static void +Opcode_ivp_mulnx16packq_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000d; +} + +static void +Opcode_ivp_movav16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d7800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movav16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a450001; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movav16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1459200; +} + +static void +Opcode_ivp_movav16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3038201; +} + +static void +Opcode_ivp_movav16_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54600c; +} + +static void +Opcode_ivp_movav16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28f820d; +} + +static void +Opcode_ivp_movav16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d9a00; +} + +static void +Opcode_ivp_movav16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980e008; +} + +static void +Opcode_ivp_movav16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c20e000; +} + +static void +Opcode_ivp_movav16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcfc001; +} + +static void +Opcode_ivp_movav16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3888010; +} + +static void +Opcode_ivp_movavu16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d7e00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movavu16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a450007; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movavu16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1459e00; +} + +static void +Opcode_ivp_movavu16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3038207; +} + +static void +Opcode_ivp_movavu16_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54600f; +} + +static void +Opcode_ivp_movavu16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2bf820d; +} + +static void +Opcode_ivp_movavu16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9dfa00; +} + +static void +Opcode_ivp_movavu16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980e00b; +} + +static void +Opcode_ivp_movavu16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c30e001; +} + +static void +Opcode_ivp_movavu16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcfc007; +} + +static void +Opcode_ivp_movavu16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b88010; +} + +static void +Opcode_ivp_extrnx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10900200; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extrnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x385a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extrnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400400; +} + +static void +Opcode_ivp_extrnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a8300; +} + +static void +Opcode_ivp_extrnx16_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x550000; +} + +static void +Opcode_ivp_extrnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a8200; +} + +static void +Opcode_ivp_extrnx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00200; +} + +static void +Opcode_ivp_extrnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a04000; +} + +static void +Opcode_ivp_extrnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c40c000; +} + +static void +Opcode_ivp_extrnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf0001; +} + +static void +Opcode_ivp_extrnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3808000; +} + +static void +Opcode_ivp_lsnx8s_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10868000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsnx8s_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e8000; +} + +static void +Opcode_ivp_lsnx8s_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ivp_lsnx8s_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ivp_lsnx8s_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x968000; +} + +static void +Opcode_ivp_lsnx8s_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10550000; +} + +static void +Opcode_ivp_lsnx8s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10976000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsnx8s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139a000; +} + +static void +Opcode_ivp_lsnx8s_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x222000; +} + +static void +Opcode_ivp_lsnx8s_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x222000; +} + +static void +Opcode_ivp_lsnx8s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa76000; +} + +static void +Opcode_ivp_lsnx8s_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b2000; +} + +static void +Opcode_ivp_lsnx8s_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsnx8s_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf6000; +} + +static void +Opcode_ivp_lsnx8s_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce000; +} + +static void +Opcode_ivp_lsnx8s_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc000; +} + +static void +Opcode_ivp_lsnx8s_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e0000; +} + +static void +Opcode_ivp_lsnx8s_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10580000; +} + +static void +Opcode_ivp_lsnx8s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108e2000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsnx8s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdfe000; +} + +static void +Opcode_ivp_lsnx8s_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc000; +} + +static void +Opcode_ivp_lsnx8s_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce000; +} + +static void +Opcode_ivp_lsnx8s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e2000; +} + +static void +Opcode_ivp_lsnx8s_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10582000; +} + +static void +Opcode_ivp_svnx8s_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8s_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ivp_svnx8s_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ivp_svnx8s_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ivp_svnx8s_i_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_svnx8s_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ivp_svnx8s_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ivp_svnx8s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109ba000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a6000; +} + +static void +Opcode_ivp_svnx8s_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58a000; +} + +static void +Opcode_ivp_svnx8s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaba000; +} + +static void +Opcode_ivp_svnx8s_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6000; +} + +static void +Opcode_ivp_svnx8s_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7ee000; +} + +static void +Opcode_ivp_svnx8s_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa32000; +} + +static void +Opcode_ivp_svnx8s_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1094a000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8s_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380000; +} + +static void +Opcode_ivp_svnx8s_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56c000; +} + +static void +Opcode_ivp_svnx8s_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4a000; +} + +static void +Opcode_ivp_svnx8s_x_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_ivp_svnx8s_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d0000; +} + +static void +Opcode_ivp_svnx8s_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa14000; +} + +static void +Opcode_ivp_svnx8s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1094e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1388000; +} + +static void +Opcode_ivp_svnx8s_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56e000; +} + +static void +Opcode_ivp_svnx8s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4e000; +} + +static void +Opcode_ivp_svnx8s_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192000; +} + +static void +Opcode_ivp_svnx8s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d2000; +} + +static void +Opcode_ivp_svnx8s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa16000; +} + +static void +Opcode_ivp_ssnx8s_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssnx8s_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1220000; +} + +static void +Opcode_ivp_ssnx8s_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x528000; +} + +static void +Opcode_ivp_ssnx8s_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a0000; +} + +static void +Opcode_ivp_ssnx8s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109aa000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssnx8s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1386000; +} + +static void +Opcode_ivp_ssnx8s_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x582000; +} + +static void +Opcode_ivp_ssnx8s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaaa000; +} + +static void +Opcode_ivp_ssnx8s_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1092a000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssnx8s_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c2000; +} + +static void +Opcode_ivp_ssnx8s_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x55c000; +} + +static void +Opcode_ivp_ssnx8s_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2a000; +} + +static void +Opcode_ivp_ssnx8s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1092e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssnx8s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14ca000; +} + +static void +Opcode_ivp_ssnx8s_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x55e000; +} + +static void +Opcode_ivp_ssnx8s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2e000; +} + +static void +Opcode_ivp_savnx8s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10838000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_savnx8s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b8000; +} + +static void +Opcode_ivp_savnx8s_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f8000; +} + +static void +Opcode_ivp_savnx8s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x938000; +} + +static void +Opcode_ivp_savnx8s_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_ivp_savnx8s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x788000; +} + +static void +Opcode_ivp_savnx8s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x938000; +} + +static void +Opcode_ivp_sanx8s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83e0070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sanx8s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1108080; +} + +static void +Opcode_ivp_sanx8s_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c8030; +} + +static void +Opcode_ivp_sanx8s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x828080; +} + +static void +Opcode_ivp_sanx8s_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0060; +} + +static void +Opcode_ivp_sanx8s_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820060; +} + +static void +Opcode_ivp_sanx8s_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60060; +} + +static void +Opcode_ivp_svnx8st_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8st_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ivp_svnx8st_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_svnx8st_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_svnx8st_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_svnx8st_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ivp_svnx8st_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10790000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8st_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1010000; +} + +static void +Opcode_ivp_svnx8st_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0000; +} + +static void +Opcode_ivp_svnx8st_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x790000; +} + +static void +Opcode_ivp_svnx8st_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_ivp_svnx8st_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x890000; +} + +static void +Opcode_ivp_svnx8st_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8st_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ivp_svnx8st_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0000; +} + +static void +Opcode_ivp_svnx8st_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ivp_svnx8st_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ivp_svnx8st_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x760000; +} + +static void +Opcode_ivp_svnx8st_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10650000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8st_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed0000; +} + +static void +Opcode_ivp_svnx8st_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0000; +} + +static void +Opcode_ivp_svnx8st_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650000; +} + +static void +Opcode_ivp_svnx8st_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d0000; +} + +static void +Opcode_ivp_svnx8st_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x770000; +} + +static void +Opcode_ivp_movba1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1706e0; +} + +static void +Opcode_ivp_movba1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260c60; +} + +static void +Opcode_ivp_movba1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260c20; +} + +static void +Opcode_ivp_movba1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2410; +} + +static void +Opcode_ivp_movba1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aec00; +} + +static void +Opcode_ivp_movba1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc810; +} + +static void +Opcode_ivp_movab1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dd040; +} + +static void +Opcode_ivp_movab1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x287020; +} + +static void +Opcode_ivp_movab1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x287020; +} + +static void +Opcode_ivp_movab1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab080; +} + +static void +Opcode_ivp_movab1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ad040; +} + +static void +Opcode_ivp_movab1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cd030; +} + +static void +Opcode_ivp_notb1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1710d0; +} + +static void +Opcode_ivp_notb1_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0042; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_notb1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261852; +} + +static void +Opcode_ivp_notb1_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30001c0; +} + +static void +Opcode_ivp_notb1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261814; +} + +static void +Opcode_ivp_notb1_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000c0; +} + +static void +Opcode_ivp_notb1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1012; +} + +static void +Opcode_ivp_notb1_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98100c8; +} + +static void +Opcode_ivp_notb1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a800a; +} + +static void +Opcode_ivp_notb1_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01e002; +} + +static void +Opcode_ivp_notb1_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0418; +} + +static void +Opcode_ivp_notb1_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd828e4; +} + +static void +Opcode_ivp_notb1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c7818; +} + +static void +Opcode_ivp_andnotb1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700c0; +} + +static void +Opcode_ivp_andnotb1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261040; +} + +static void +Opcode_ivp_andnotb1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261000; +} + +static void +Opcode_ivp_andnotb1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8008; +} + +static void +Opcode_ivp_andnotb1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa010; +} + +static void +Opcode_ivp_andnotb1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6008; +} + +static void +Opcode_ivp_ornotb1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1708c8; +} + +static void +Opcode_ivp_ornotb1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260850; +} + +static void +Opcode_ivp_ornotb1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260810; +} + +static void +Opcode_ivp_ornotb1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8818; +} + +static void +Opcode_ivp_ornotb1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa018; +} + +static void +Opcode_ivp_ornotb1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6818; +} + +static void +Opcode_ivp_cvt32s2nx24ll_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc070; +} + +static void +Opcode_ivp_cvt32s2nx24ll_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6020; +} + +static void +Opcode_ivp_cvt32s2nx24ll_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6020; +} + +static void +Opcode_ivp_cvt32s2nx24ll_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0c8; +} + +static void +Opcode_ivp_cvt32s2nx24ll_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac058; +} + +static void +Opcode_ivp_cvt32s2nx24ll_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2014; +} + +static void +Opcode_ivp_cvt32s2nx24lh_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc06c; +} + +static void +Opcode_ivp_cvt32s2nx24lh_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a602c; +} + +static void +Opcode_ivp_cvt32s2nx24lh_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a602c; +} + +static void +Opcode_ivp_cvt32s2nx24lh_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0e4; +} + +static void +Opcode_ivp_cvt32s2nx24lh_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac074; +} + +static void +Opcode_ivp_cvt32s2nx24lh_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d20e4; +} + +static void +Opcode_ivp_cvt32s2nx24hl_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc068; +} + +static void +Opcode_ivp_cvt32s2nx24hl_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6028; +} + +static void +Opcode_ivp_cvt32s2nx24hl_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6028; +} + +static void +Opcode_ivp_cvt32s2nx24hl_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0c4; +} + +static void +Opcode_ivp_cvt32s2nx24hl_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac054; +} + +static void +Opcode_ivp_cvt32s2nx24hl_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d20c4; +} + +static void +Opcode_ivp_cvt32s2nx24hh_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc064; +} + +static void +Opcode_ivp_cvt32s2nx24hh_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6024; +} + +static void +Opcode_ivp_cvt32s2nx24hh_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6024; +} + +static void +Opcode_ivp_cvt32s2nx24hh_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0e0; +} + +static void +Opcode_ivp_cvt32s2nx24hh_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac070; +} + +static void +Opcode_ivp_cvt32s2nx24hh_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d20a4; +} + +static void +Opcode_ivp_cvt64snx48ll_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a0d4; +} + +static void +Opcode_ivp_cvt64snx48ll_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80a4; +} + +static void +Opcode_ivp_cvt64snx48lh_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1780d4; +} + +static void +Opcode_ivp_cvt64snx48lh_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80a0; +} + +static void +Opcode_ivp_cvt64snx48hl_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1760d4; +} + +static void +Opcode_ivp_cvt64snx48hl_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d20f4; +} + +static void +Opcode_ivp_cvt64snx48hh_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1740d4; +} + +static void +Opcode_ivp_cvt64snx48hh_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d20d4; +} + +static void +Opcode_ivp_cvt16s2nx24l_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc054; +} + +static void +Opcode_ivp_cvt16s2nx24l_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x296024; +} + +static void +Opcode_ivp_cvt16s2nx24l_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x296024; +} + +static void +Opcode_ivp_cvt16s2nx24l_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0a4; +} + +static void +Opcode_ivp_cvt16s2nx24l_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac064; +} + +static void +Opcode_ivp_cvt16s2nx24l_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2024; +} + +static void +Opcode_ivp_cvt16s2nx24h_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc050; +} + +static void +Opcode_ivp_cvt16s2nx24h_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x296020; +} + +static void +Opcode_ivp_cvt16s2nx24h_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x296020; +} + +static void +Opcode_ivp_cvt16s2nx24h_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0a0; +} + +static void +Opcode_ivp_cvt16s2nx24h_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac060; +} + +static void +Opcode_ivp_cvt16s2nx24h_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2004; +} + +static void +Opcode_ivp_cvt32snx48l_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc078; +} + +static void +Opcode_ivp_cvt32snx48l_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6028; +} + +static void +Opcode_ivp_cvt32snx48l_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6028; +} + +static void +Opcode_ivp_cvt32snx48l_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0cc; +} + +static void +Opcode_ivp_cvt32snx48l_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac05c; +} + +static void +Opcode_ivp_cvt32snx48l_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2054; +} + +static void +Opcode_ivp_cvt32snx48h_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc074; +} + +static void +Opcode_ivp_cvt32snx48h_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6024; +} + +static void +Opcode_ivp_cvt32snx48h_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6024; +} + +static void +Opcode_ivp_cvt32snx48h_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0e8; +} + +static void +Opcode_ivp_cvt32snx48h_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac078; +} + +static void +Opcode_ivp_cvt32snx48h_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2034; +} + +static void +Opcode_ivp_cvt16u2nx24h_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc058; +} + +static void +Opcode_ivp_cvt16u2nx24h_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x296028; +} + +static void +Opcode_ivp_cvt16u2nx24h_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x296028; +} + +static void +Opcode_ivp_cvt16u2nx24h_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0a8; +} + +static void +Opcode_ivp_cvt16u2nx24h_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac068; +} + +static void +Opcode_ivp_cvt16u2nx24h_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2044; +} + +static void +Opcode_ivp_cvt32unx48h_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc07c; +} + +static void +Opcode_ivp_cvt32unx48h_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b602c; +} + +static void +Opcode_ivp_cvt32unx48h_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b602c; +} + +static void +Opcode_ivp_cvt32unx48h_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0ec; +} + +static void +Opcode_ivp_cvt32unx48h_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac07c; +} + +static void +Opcode_ivp_cvt32unx48h_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2074; +} + +static void +Opcode_ivp_cvt64un_2x96h_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e0d4; +} + +static void +Opcode_ivp_cvt64un_2x96h_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80ac; +} + +static void +Opcode_ivp_cvt16u2nx24l_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc05c; +} + +static void +Opcode_ivp_cvt16u2nx24l_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29602c; +} + +static void +Opcode_ivp_cvt16u2nx24l_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29602c; +} + +static void +Opcode_ivp_cvt16u2nx24l_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0ac; +} + +static void +Opcode_ivp_cvt16u2nx24l_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac06c; +} + +static void +Opcode_ivp_cvt16u2nx24l_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2064; +} + +static void +Opcode_ivp_cvt24u2nx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268000; +} + +static void +Opcode_ivp_cvt24u2nx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13400; +} + +static void +Opcode_ivp_cvt24u2nx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0600c; +} + +static void +Opcode_ivp_cvt24u2nx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_ivp_cvt24u2nx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_ivp_cvt24u2nx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x654001; +} + +static void +Opcode_ivp_cvt24s2nx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26400f; +} + +static void +Opcode_ivp_cvt24s2nx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03400; +} + +static void +Opcode_ivp_cvt24s2nx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c0b; +} + +static void +Opcode_ivp_cvt24s2nx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000f; +} + +static void +Opcode_ivp_cvt24s2nx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000f; +} + +static void +Opcode_ivp_cvt32s24_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc060; +} + +static void +Opcode_ivp_cvt32s24_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6020; +} + +static void +Opcode_ivp_cvt32s24_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6020; +} + +static void +Opcode_ivp_cvt32s24_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0c0; +} + +static void +Opcode_ivp_cvt32s24_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac050; +} + +static void +Opcode_ivp_cvt32s24_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2084; +} + +static void +Opcode_ivp_cvt24u32_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268008; +} + +static void +Opcode_ivp_cvt24u32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf500e0; +} + +static void +Opcode_ivp_cvt24u32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e68003; +} + +static void +Opcode_ivp_cvt24u32_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0008; +} + +static void +Opcode_ivp_cvt24u32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150008; +} + +static void +Opcode_ivp_cvt24u32_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65b000; +} + +static void +Opcode_ivp_cvt24unx32l_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268002; +} + +static void +Opcode_ivp_cvt24unx32l_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33400; +} + +static void +Opcode_ivp_cvt24unx32l_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0680c; +} + +static void +Opcode_ivp_cvt24unx32l_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0002; +} + +static void +Opcode_ivp_cvt24unx32l_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150002; +} + +static void +Opcode_ivp_cvt24unx32l_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x654003; +} + +static void +Opcode_ivp_cvt24unx32h_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268001; +} + +static void +Opcode_ivp_cvt24unx32h_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf23400; +} + +static void +Opcode_ivp_cvt24unx32h_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0640c; +} + +static void +Opcode_ivp_cvt24unx32h_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0001; +} + +static void +Opcode_ivp_cvt24unx32h_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150001; +} + +static void +Opcode_ivp_cvt24unx32h_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x654002; +} + +static void +Opcode_ivp_cvt32unx48l_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700d4; +} + +static void +Opcode_ivp_cvt32unx48l_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260058; +} + +static void +Opcode_ivp_cvt32unx48l_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28200c; +} + +static void +Opcode_ivp_cvt32unx48l_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980d0; +} + +static void +Opcode_ivp_cvt32unx48l_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00a0; +} + +static void +Opcode_ivp_cvt32unx48l_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2094; +} + +static void +Opcode_ivp_cvt48unx32l_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800b; +} + +static void +Opcode_ivp_cvt48unx32l_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf50ce0; +} + +static void +Opcode_ivp_cvt48unx32l_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e68c03; +} + +static void +Opcode_ivp_cvt48unx32l_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000b; +} + +static void +Opcode_ivp_cvt48unx32l_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150019; +} + +static void +Opcode_ivp_cvt48unx32l_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65b002; +} + +static void +Opcode_ivp_cvt48unx32_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268004; +} + +static void +Opcode_ivp_cvt48unx32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03c00; +} + +static void +Opcode_ivp_cvt48unx32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0700c; +} + +static void +Opcode_ivp_cvt48unx32_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0004; +} + +static void +Opcode_ivp_cvt48unx32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150004; +} + +static void +Opcode_ivp_cvt48unx32_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x654004; +} + +static void +Opcode_ivp_cvt48snx32l_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268009; +} + +static void +Opcode_ivp_cvt48snx32l_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf504e0; +} + +static void +Opcode_ivp_cvt48snx32l_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e68403; +} + +static void +Opcode_ivp_cvt48snx32l_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0009; +} + +static void +Opcode_ivp_cvt48snx32l_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150018; +} + +static void +Opcode_ivp_cvt48snx32_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268003; +} + +static void +Opcode_ivp_cvt48snx32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03800; +} + +static void +Opcode_ivp_cvt48snx32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c0c; +} + +static void +Opcode_ivp_cvt48snx32_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0003; +} + +static void +Opcode_ivp_cvt48snx32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150003; +} + +static void +Opcode_ivp_cvt64s48_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1720d4; +} + +static void +Opcode_ivp_cvt64s48_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262058; +} + +static void +Opcode_ivp_cvt64s48_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28201c; +} + +static void +Opcode_ivp_cvt64s48_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980f0; +} + +static void +Opcode_ivp_cvt64s48_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00a4; +} + +static void +Opcode_ivp_cvt64s48_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d20b4; +} + +static void +Opcode_ivp_cvt48u64_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800a; +} + +static void +Opcode_ivp_cvt48u64_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf508e0; +} + +static void +Opcode_ivp_cvt48u64_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e68803; +} + +static void +Opcode_ivp_cvt48u64_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000a; +} + +static void +Opcode_ivp_cvt48u64_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150009; +} + +static void +Opcode_ivp_cvt48u64_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65b001; +} + +static void +Opcode_ivp_cvt48un_2x64l_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268006; +} + +static void +Opcode_ivp_cvt48un_2x64l_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13c00; +} + +static void +Opcode_ivp_cvt48un_2x64l_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0780c; +} + +static void +Opcode_ivp_cvt48un_2x64l_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0006; +} + +static void +Opcode_ivp_cvt48un_2x64l_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150006; +} + +static void +Opcode_ivp_cvt48un_2x64l_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x654006; +} + +static void +Opcode_ivp_cvt48un_2x64h_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268005; +} + +static void +Opcode_ivp_cvt48un_2x64h_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13800; +} + +static void +Opcode_ivp_cvt48un_2x64h_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0740c; +} + +static void +Opcode_ivp_cvt48un_2x64h_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0005; +} + +static void +Opcode_ivp_cvt48un_2x64h_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150005; +} + +static void +Opcode_ivp_cvt48un_2x64h_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x654005; +} + +static void +Opcode_ivp_cvt64un_2x96l_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700d8; +} + +static void +Opcode_ivp_cvt64un_2x96l_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca0a0; +} + +static void +Opcode_ivp_cvt96un_2x64_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268007; +} + +static void +Opcode_ivp_cvt96un_2x64_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf23800; +} + +static void +Opcode_ivp_cvt96un_2x64_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c0c; +} + +static void +Opcode_ivp_cvt96un_2x64_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0007; +} + +static void +Opcode_ivp_cvt96un_2x64_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150007; +} + +static void +Opcode_ivp_cvt96un_2x64_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x654007; +} + +static void +Opcode_ivp_cvt96u64_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800c; +} + +static void +Opcode_ivp_cvt96u64_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf510e0; +} + +static void +Opcode_ivp_cvt96u64_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e69003; +} + +static void +Opcode_ivp_cvt96u64_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000c; +} + +static void +Opcode_ivp_cvt96u64_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000a; +} + +static void +Opcode_ivp_cvt96u64_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65b003; +} + +static void +Opcode_ivp_cvt64u96_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c0d4; +} + +static void +Opcode_ivp_cvt64u96_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264058; +} + +static void +Opcode_ivp_cvt64u96_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28202c; +} + +static void +Opcode_ivp_cvt64u96_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980d4; +} + +static void +Opcode_ivp_cvt64u96_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00a8; +} + +static void +Opcode_ivp_cvt64u96_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80a8; +} + +static void +Opcode_ivp_lb2n_i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ivp_lb2n_i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x166000; +} + +static void +Opcode_ivp_lb2n_i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x166000; +} + +static void +Opcode_ivp_lb2n_i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x186000; +} + +static void +Opcode_ivp_lb2n_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x171040; +} + +static void +Opcode_ivp_lb2n_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x199000; +} + +static void +Opcode_ivp_lb2n_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193000; +} + +static void +Opcode_ivp_lb2n_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8010; +} + +static void +Opcode_ivp_sb2n_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a20000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sb2n_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100060; +} + +static void +Opcode_ivp_sb2n_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0000; +} + +static void +Opcode_ivp_sb2n_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0020; +} + +static void +Opcode_ivp_sb2n_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ivp_sb2n_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f1000; +} + +static void +Opcode_ivp_sb2n_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a200c0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sb2n_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100c0; +} + +static void +Opcode_ivp_sb2n_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0c00; +} + +static void +Opcode_ivp_sb2n_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8300c0; +} + +static void +Opcode_ivp_sb2n_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000c0; +} + +static void +Opcode_ivp_sb2n_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f10c0; +} + +static void +Opcode_ivp_ltr2n_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700e0; +} + +static void +Opcode_ivp_ltr2n_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260660; +} + +static void +Opcode_ivp_ltr2n_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260620; +} + +static void +Opcode_ivp_ltr2n_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0610; +} + +static void +Opcode_ivp_ltr2n_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae600; +} + +static void +Opcode_ivp_ltr2n_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0010; +} + +static void +Opcode_ivp_ltr2n_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc610; +} + +static void +Opcode_ivp_ltr2ni_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x171070; +} + +static void +Opcode_ivp_ltr2ni_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260040; +} + +static void +Opcode_ivp_ltr2ni_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260000; +} + +static void +Opcode_ivp_ltr2ni_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19f000; +} + +static void +Opcode_ivp_ltr2ni_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab000; +} + +static void +Opcode_ivp_ltr2ni_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0010; +} + +static void +Opcode_ivp_ltr2ni_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cb010; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10460000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x460000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10320000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1099e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ac000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x236000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x236000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9e000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c6000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7ea000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2e000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x194000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10912000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1492000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21a000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x218000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa12000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x162000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a8000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x162000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c8000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0c000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x182000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10916000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x162000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x149a000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21c000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21a000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa16000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x164000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x164000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7ca000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0e000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x184000; +} + +static void +Opcode_ivp_lvn_2x16ut_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16ut_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ivp_lvn_2x16ut_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_lvn_2x16ut_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200000; +} + +static void +Opcode_ivp_lvn_2x16ut_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_lvn_2x16ut_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ivp_lvn_2x16ut_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10770000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16ut_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff0000; +} + +static void +Opcode_ivp_lvn_2x16ut_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x770000; +} + +static void +Opcode_ivp_lvn_2x16ut_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d0000; +} + +static void +Opcode_ivp_lvn_2x16ut_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ivp_lvn_2x16ut_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x870000; +} + +static void +Opcode_ivp_lvn_2x16ut_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16ut_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ivp_lvn_2x16ut_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ivp_lvn_2x16ut_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10400000; +} + +static void +Opcode_ivp_lvn_2x16ut_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ivp_lvn_2x16ut_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720000; +} + +static void +Opcode_ivp_lvn_2x16ut_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10610000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16ut_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe90000; +} + +static void +Opcode_ivp_lvn_2x16ut_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_ivp_lvn_2x16ut_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10410000; +} + +static void +Opcode_ivp_lvn_2x16ut_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_ivp_lvn_2x16ut_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10440000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e0000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1099a000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a4000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x234000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x234000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9a000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x172000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c4000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x172000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e8000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2c000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090a000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1482000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x216000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x214000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0a000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a4000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c4000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148a000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x218000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x216000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0e000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a6000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c6000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0a000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_lvn_2x16st_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16st_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ivp_lvn_2x16st_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ivp_lvn_2x16st_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101c0000; +} + +static void +Opcode_ivp_lvn_2x16st_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ivp_lvn_2x16st_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ivp_lvn_2x16st_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10760000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16st_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe0000; +} + +static void +Opcode_ivp_lvn_2x16st_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x760000; +} + +static void +Opcode_ivp_lvn_2x16st_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0000; +} + +static void +Opcode_ivp_lvn_2x16st_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0000; +} + +static void +Opcode_ivp_lvn_2x16st_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x860000; +} + +static void +Opcode_ivp_lvn_2x16st_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16st_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe60000; +} + +static void +Opcode_ivp_lvn_2x16st_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e0000; +} + +static void +Opcode_ivp_lvn_2x16st_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103e0000; +} + +static void +Opcode_ivp_lvn_2x16st_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560000; +} + +static void +Opcode_ivp_lvn_2x16st_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ivp_lvn_2x16st_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16st_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe70000; +} + +static void +Opcode_ivp_lvn_2x16st_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f0000; +} + +static void +Opcode_ivp_lvn_2x16st_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103f0000; +} + +static void +Opcode_ivp_lvn_2x16st_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x570000; +} + +static void +Opcode_ivp_lvn_2x16st_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x710000; +} + +static void +Opcode_ivp_svn_2x16u_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10520000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16u_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce0000; +} + +static void +Opcode_ivp_svn_2x16u_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000; +} + +static void +Opcode_ivp_svn_2x16u_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x520000; +} + +static void +Opcode_ivp_svn_2x16u_i_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ivp_svn_2x16u_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0000; +} + +static void +Opcode_ivp_svn_2x16u_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0000; +} + +static void +Opcode_ivp_svn_2x16ut_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16ut_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ivp_svn_2x16ut_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_svn_2x16ut_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ivp_svn_2x16ut_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ivp_svn_2x16ut_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ivp_svn_2x16u_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109c6000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16u_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13be000; +} + +static void +Opcode_ivp_svn_2x16u_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_ivp_svn_2x16u_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac6000; +} + +static void +Opcode_ivp_svn_2x16u_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac000; +} + +static void +Opcode_ivp_svn_2x16u_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f4000; +} + +static void +Opcode_ivp_svn_2x16u_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa38000; +} + +static void +Opcode_ivp_svn_2x16ut_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16ut_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ivp_svn_2x16ut_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d0000; +} + +static void +Opcode_ivp_svn_2x16ut_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0000; +} + +static void +Opcode_ivp_svn_2x16ut_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x710000; +} + +static void +Opcode_ivp_svn_2x16ut_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000; +} + +static void +Opcode_ivp_svn_2x16u_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10962000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16u_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b0000; +} + +static void +Opcode_ivp_svn_2x16u_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x578000; +} + +static void +Opcode_ivp_svn_2x16u_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa62000; +} + +static void +Opcode_ivp_svn_2x16u_x_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19c000; +} + +static void +Opcode_ivp_svn_2x16u_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7dc000; +} + +static void +Opcode_ivp_svn_2x16u_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa20000; +} + +static void +Opcode_ivp_svn_2x16ut_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16ut_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf20000; +} + +static void +Opcode_ivp_svn_2x16ut_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_svn_2x16ut_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0000; +} + +static void +Opcode_ivp_svn_2x16ut_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620000; +} + +static void +Opcode_ivp_svn_2x16ut_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0000; +} + +static void +Opcode_ivp_svn_2x16u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10966000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b8000; +} + +static void +Opcode_ivp_svn_2x16u_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57a000; +} + +static void +Opcode_ivp_svn_2x16u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa66000; +} + +static void +Opcode_ivp_svn_2x16u_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19e000; +} + +static void +Opcode_ivp_svn_2x16u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7de000; +} + +static void +Opcode_ivp_svn_2x16u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa22000; +} + +static void +Opcode_ivp_svn_2x16ut_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16ut_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30000; +} + +static void +Opcode_ivp_svn_2x16ut_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_ivp_svn_2x16ut_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0000; +} + +static void +Opcode_ivp_svn_2x16ut_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_ivp_svn_2x16ut_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d0000; +} + +static void +Opcode_ivp_svn_2x16s_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16s_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ivp_svn_2x16s_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ivp_svn_2x16s_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ivp_svn_2x16s_i_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_svn_2x16s_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ivp_svn_2x16s_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ivp_svn_2x16st_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16st_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_svn_2x16st_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ivp_svn_2x16st_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ivp_svn_2x16st_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ivp_svn_2x16st_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_svn_2x16s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109c2000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b6000; +} + +static void +Opcode_ivp_svn_2x16s_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58e000; +} + +static void +Opcode_ivp_svn_2x16s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac2000; +} + +static void +Opcode_ivp_svn_2x16s_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa000; +} + +static void +Opcode_ivp_svn_2x16s_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f2000; +} + +static void +Opcode_ivp_svn_2x16s_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa36000; +} + +static void +Opcode_ivp_svn_2x16st_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16st_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1030000; +} + +static void +Opcode_ivp_svn_2x16st_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ivp_svn_2x16st_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0000; +} + +static void +Opcode_ivp_svn_2x16st_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ivp_svn_2x16st_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b0000; +} + +static void +Opcode_ivp_svn_2x16s_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1095a000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16s_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a0000; +} + +static void +Opcode_ivp_svn_2x16s_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x574000; +} + +static void +Opcode_ivp_svn_2x16s_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5a000; +} + +static void +Opcode_ivp_svn_2x16s_x_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198000; +} + +static void +Opcode_ivp_svn_2x16s_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d8000; +} + +static void +Opcode_ivp_svn_2x16s_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1c000; +} + +static void +Opcode_ivp_svn_2x16st_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16st_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ivp_svn_2x16st_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0000; +} + +static void +Opcode_ivp_svn_2x16st_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ivp_svn_2x16st_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ivp_svn_2x16st_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0000; +} + +static void +Opcode_ivp_svn_2x16s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1095e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a8000; +} + +static void +Opcode_ivp_svn_2x16s_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x576000; +} + +static void +Opcode_ivp_svn_2x16s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5e000; +} + +static void +Opcode_ivp_svn_2x16s_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a000; +} + +static void +Opcode_ivp_svn_2x16s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7da000; +} + +static void +Opcode_ivp_svn_2x16s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1e000; +} + +static void +Opcode_ivp_svn_2x16st_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16st_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10000; +} + +static void +Opcode_ivp_svn_2x16st_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0000; +} + +static void +Opcode_ivp_svn_2x16st_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690000; +} + +static void +Opcode_ivp_svn_2x16st_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_ivp_svn_2x16st_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0000; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83c8070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce030; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100b0; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x286010; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x286010; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8300b0; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198070; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0050; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0060; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0030; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820030; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60030; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8060; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83d0070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce040; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11180a0; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x284020; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x284020; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8380a0; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198090; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0060; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0080; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0040; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820040; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60040; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8080; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10800000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x184000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10510000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107f8000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x182000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1078000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14e000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14e000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f8000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10508000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x748000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f8000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_ivp_san_2x16u_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83f8070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_san_2x16u_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11080b0; +} + +static void +Opcode_ivp_san_2x16u_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0060; +} + +static void +Opcode_ivp_san_2x16u_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280b0; +} + +static void +Opcode_ivp_san_2x16u_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0090; +} + +static void +Opcode_ivp_san_2x16u_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820090; +} + +static void +Opcode_ivp_san_2x16u_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60090; +} + +static void +Opcode_ivp_san_2x16s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83f0070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_san_2x16s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11080a0; +} + +static void +Opcode_ivp_san_2x16s_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0050; +} + +static void +Opcode_ivp_san_2x16s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280a0; +} + +static void +Opcode_ivp_san_2x16s_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0080; +} + +static void +Opcode_ivp_san_2x16s_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820080; +} + +static void +Opcode_ivp_san_2x16s_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60080; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10820000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x920000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10530000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x770000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x920000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10828000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18e000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a8000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x928000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10538000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x778000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x928000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_ivp_savn_2x16u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10850000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_savn_2x16u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0000; +} + +static void +Opcode_ivp_savn_2x16u_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510000; +} + +static void +Opcode_ivp_savn_2x16u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x950000; +} + +static void +Opcode_ivp_savn_2x16u_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_savn_2x16u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0000; +} + +static void +Opcode_ivp_savn_2x16u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x950000; +} + +static void +Opcode_ivp_savn_2x16s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10848000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_savn_2x16s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c8000; +} + +static void +Opcode_ivp_savn_2x16s_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x508000; +} + +static void +Opcode_ivp_savn_2x16s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x948000; +} + +static void +Opcode_ivp_savn_2x16s_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000; +} + +static void +Opcode_ivp_savn_2x16s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x798000; +} + +static void +Opcode_ivp_savn_2x16s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x948000; +} + +static void +Opcode_ivp_lsn_2x16s_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10870000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsn_2x16s_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0000; +} + +static void +Opcode_ivp_lsn_2x16s_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c2000; +} + +static void +Opcode_ivp_lsn_2x16s_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c2000; +} + +static void +Opcode_ivp_lsn_2x16s_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970000; +} + +static void +Opcode_ivp_lsn_2x16s_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10558000; +} + +static void +Opcode_ivp_lsn_2x16s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1097a000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsn_2x16s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a2000; +} + +static void +Opcode_ivp_lsn_2x16s_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x224000; +} + +static void +Opcode_ivp_lsn_2x16s_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x224000; +} + +static void +Opcode_ivp_lsn_2x16s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7a000; +} + +static void +Opcode_ivp_lsn_2x16s_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b4000; +} + +static void +Opcode_ivp_lsn_2x16s_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108e4000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsn_2x16s_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1402000; +} + +static void +Opcode_ivp_lsn_2x16s_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1de000; +} + +static void +Opcode_ivp_lsn_2x16s_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc000; +} + +static void +Opcode_ivp_lsn_2x16s_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e4000; +} + +static void +Opcode_ivp_lsn_2x16s_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10584000; +} + +static void +Opcode_ivp_lsn_2x16s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108e6000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsn_2x16s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140a000; +} + +static void +Opcode_ivp_lsn_2x16s_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec000; +} + +static void +Opcode_ivp_lsn_2x16s_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1de000; +} + +static void +Opcode_ivp_lsn_2x16s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e6000; +} + +static void +Opcode_ivp_lsn_2x16s_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10586000; +} + +static void +Opcode_ivp_ssn_2x16s_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108a8000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssn_2x16s_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1228000; +} + +static void +Opcode_ivp_ssn_2x16s_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_ivp_ssn_2x16s_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a8000; +} + +static void +Opcode_ivp_ssn_2x16s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109ae000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssn_2x16s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138e000; +} + +static void +Opcode_ivp_ssn_2x16s_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x584000; +} + +static void +Opcode_ivp_ssn_2x16s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaae000; +} + +static void +Opcode_ivp_ssn_2x16s_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10932000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssn_2x16s_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d2000; +} + +static void +Opcode_ivp_ssn_2x16s_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560000; +} + +static void +Opcode_ivp_ssn_2x16s_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa32000; +} + +static void +Opcode_ivp_ssn_2x16s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10936000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssn_2x16s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14da000; +} + +static void +Opcode_ivp_ssn_2x16s_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x562000; +} + +static void +Opcode_ivp_ssn_2x16s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa36000; +} + +static void +Opcode_ivp_lsn_2x32_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsn_2x32_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb80000; +} + +static void +Opcode_ivp_lsn_2x32_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_lsn_2x32_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_lsn_2x32_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ivp_lsn_2x32_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280000; +} + +static void +Opcode_ivp_lsn_2x32_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1097e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsn_2x32_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13aa000; +} + +static void +Opcode_ivp_lsn_2x32_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x226000; +} + +static void +Opcode_ivp_lsn_2x32_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x226000; +} + +static void +Opcode_ivp_lsn_2x32_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7e000; +} + +static void +Opcode_ivp_lsn_2x32_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b6000; +} + +static void +Opcode_ivp_lsn_2x32_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108e8000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsn_2x32_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1412000; +} + +static void +Opcode_ivp_lsn_2x32_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee000; +} + +static void +Opcode_ivp_lsn_2x32_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec000; +} + +static void +Opcode_ivp_lsn_2x32_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e8000; +} + +static void +Opcode_ivp_lsn_2x32_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10588000; +} + +static void +Opcode_ivp_lsn_2x32_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108ea000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsn_2x32_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x141a000; +} + +static void +Opcode_ivp_lsn_2x32_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fc000; +} + +static void +Opcode_ivp_lsn_2x32_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee000; +} + +static void +Opcode_ivp_lsn_2x32_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ea000; +} + +static void +Opcode_ivp_lsn_2x32_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058a000; +} + +static void +Opcode_ivp_ssn_2x32_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssn_2x32_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ivp_ssn_2x32_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_ssn_2x32_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ivp_ssn_2x32_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109b2000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssn_2x32_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1396000; +} + +static void +Opcode_ivp_ssn_2x32_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x586000; +} + +static void +Opcode_ivp_ssn_2x32_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab2000; +} + +static void +Opcode_ivp_ssn_2x32_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1093a000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssn_2x32_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14e2000; +} + +static void +Opcode_ivp_ssn_2x32_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x564000; +} + +static void +Opcode_ivp_ssn_2x32_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3a000; +} + +static void +Opcode_ivp_ssn_2x32_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1093e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssn_2x32_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14ea000; +} + +static void +Opcode_ivp_ssn_2x32_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x566000; +} + +static void +Opcode_ivp_ssn_2x32_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3e000; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20500c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000a; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00010; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180030a; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8680008; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c401000; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_bmaxunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18002a0; +} + +static void +Opcode_ivp_bminunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20b00c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bminunx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840000; +} + +static void +Opcode_ivp_bminunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ivp_bminunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800106; +} + +static void +Opcode_ivp_bminunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00018; +} + +static void +Opcode_ivp_bminunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800006; +} + +static void +Opcode_ivp_bminunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9180000; +} + +static void +Opcode_ivp_bminunx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ivp_bminunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c701000; +} + +static void +Opcode_ivp_bminunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0000; +} + +static void +Opcode_ivp_bminunx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ivp_bminunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18003e0; +} + +static void +Opcode_ivp_rbminunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800c11; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rbminunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000053; +} + +static void +Opcode_ivp_rbminunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800353; +} + +static void +Opcode_ivp_rbminunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9500608; +} + +static void +Opcode_ivp_rbminunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6070a0; +} + +static void +Opcode_ivp_rbminunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80090; +} + +static void +Opcode_ivp_rbminunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001a4; +} + +static void +Opcode_ivp_rbmaxunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800cf0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rbmaxunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000072; +} + +static void +Opcode_ivp_rbmaxunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800372; +} + +static void +Opcode_ivp_rbmaxunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9500208; +} + +static void +Opcode_ivp_rbmaxunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607060; +} + +static void +Opcode_ivp_rbmaxunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80070; +} + +static void +Opcode_ivp_rbmaxunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800196; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20100c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800002; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00018; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800302; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8680000; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c203000; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_bmax2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800320; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20700c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740000; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000e; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00010; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180030e; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8780008; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c501000; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ivp_bmin2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18002e0; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800008; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800308; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8600008; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c400000; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800280; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20a00c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800104; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00008; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800004; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9100000; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c700000; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780000; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_bminu2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18003c0; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20300c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800006; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00018; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800306; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8780000; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c303000; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800360; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20900c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0000; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800102; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00018; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800002; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9080000; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c601000; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740000; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ivp_bminn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18003a0; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20600c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000c; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180030c; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8700008; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c500000; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18002c0; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c00c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880000; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800108; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800008; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9200000; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c402000; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ivp_bminun_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800000; +} + +static void +Opcode_ivp_addn_2x32t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36404000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_addn_2x32t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ivp_addn_2x32t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_addn_2x32t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2600100; +} + +static void +Opcode_ivp_addn_2x32t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ivp_addn_2x32t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300200; +} + +static void +Opcode_ivp_addn_2x32t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8800002; +} + +static void +Opcode_ivp_addn_2x32t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c300000; +} + +static void +Opcode_ivp_addn_2x32t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ivp_addn_2x32t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800240; +} + +static void +Opcode_ivp_subn_2x32t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e306000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_subn_2x32t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac0000; +} + +static void +Opcode_ivp_subn_2x32t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940000; +} + +static void +Opcode_ivp_subn_2x32t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00200; +} + +static void +Opcode_ivp_subn_2x32t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400010; +} + +static void +Opcode_ivp_subn_2x32t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700300; +} + +static void +Opcode_ivp_subn_2x32t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00003; +} + +static void +Opcode_ivp_subn_2x32t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c005000; +} + +static void +Opcode_ivp_subn_2x32t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa40000; +} + +static void +Opcode_ivp_subn_2x32t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000a0; +} + +static void +Opcode_ivp_add2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a402800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_add2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1258000; +} + +static void +Opcode_ivp_add2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc58000; +} + +static void +Opcode_ivp_add2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290020a; +} + +static void +Opcode_ivp_add2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00015; +} + +static void +Opcode_ivp_add2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290010a; +} + +static void +Opcode_ivp_add2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c8000b; +} + +static void +Opcode_ivp_add2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8000; +} + +static void +Opcode_ivp_add2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e006400; +} + +static void +Opcode_ivp_add2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb38000; +} + +static void +Opcode_ivp_add2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a8000; +} + +static void +Opcode_ivp_add2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900280; +} + +static void +Opcode_ivp_sub2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38403c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sub2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340000; +} + +static void +Opcode_ivp_sub2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ivp_sub2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x310020c; +} + +static void +Opcode_ivp_sub2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000a; +} + +static void +Opcode_ivp_sub2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0020e; +} + +static void +Opcode_ivp_sub2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e8000e; +} + +static void +Opcode_ivp_sub2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ivp_sub2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e306000; +} + +static void +Opcode_ivp_sub2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_ivp_sub2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ivp_sub2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e00380; +} + +static void +Opcode_ivp_neg2nx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a300b0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_neg2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27500d0e; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_neg2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11080f0; +} + +static void +Opcode_ivp_neg2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf78060; +} + +static void +Opcode_ivp_neg2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330740e; +} + +static void +Opcode_ivp_neg2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f60016; +} + +static void +Opcode_ivp_neg2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f07608; +} + +static void +Opcode_ivp_neg2nx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8340f0; +} + +static void +Opcode_ivp_neg2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94801d9; +} + +static void +Opcode_ivp_neg2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a80e0; +} + +static void +Opcode_ivp_neg2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606d0a; +} + +static void +Opcode_ivp_neg2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20304; +} + +static void +Opcode_ivp_neg2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a80a0; +} + +static void +Opcode_ivp_neg2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2707540; +} + +static void +Opcode_ivp_min2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c401c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_min2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f0000; +} + +static void +Opcode_ivp_min2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_ivp_min2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280020e; +} + +static void +Opcode_ivp_min2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000e; +} + +static void +Opcode_ivp_min2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00200; +} + +static void +Opcode_ivp_min2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d0000c; +} + +static void +Opcode_ivp_min2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_ivp_min2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e107800; +} + +static void +Opcode_ivp_min2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd0000; +} + +static void +Opcode_ivp_min2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_ivp_min2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28002e0; +} + +static void +Opcode_ivp_minu2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a403400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_minu2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308000; +} + +static void +Opcode_ivp_minu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd48000; +} + +static void +Opcode_ivp_minu2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0020e; +} + +static void +Opcode_ivp_minu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00018; +} + +static void +Opcode_ivp_minu2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00206; +} + +static void +Opcode_ivp_minu2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d8000f; +} + +static void +Opcode_ivp_minu2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x548000; +} + +static void +Opcode_ivp_minu2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e206400; +} + +static void +Opcode_ivp_minu2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe8000; +} + +static void +Opcode_ivp_minu2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x448000; +} + +static void +Opcode_ivp_minu2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f002e0; +} + +static void +Opcode_ivp_max2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_max2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ivp_max2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ivp_max2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190030c; +} + +static void +Opcode_ivp_max2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900009; +} + +static void +Opcode_ivp_max2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0010c; +} + +static void +Opcode_ivp_max2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9380006; +} + +static void +Opcode_ivp_max2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ivp_max2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e106000; +} + +static void +Opcode_ivp_max2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba0000; +} + +static void +Opcode_ivp_max2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_max2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e002a0; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e401400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12d8000; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf8000; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0020c; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190001c; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0010e; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c8000d; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x518000; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e106c00; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb8000; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x418000; +} + +static void +Opcode_ivp_maxu2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d002c0; +} + +static void +Opcode_ivp_lt2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b8000; +} + +static void +Opcode_ivp_lt2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b8000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lt2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c1c00; +} + +static void +Opcode_ivp_lt2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec5000; +} + +static void +Opcode_ivp_lt2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8306; +} + +static void +Opcode_ivp_lt2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04818; +} + +static void +Opcode_ivp_lt2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8206; +} + +static void +Opcode_ivp_lt2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000; +} + +static void +Opcode_ivp_lt2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b84008; +} + +static void +Opcode_ivp_lt2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c2400; +} + +static void +Opcode_ivp_lt2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c51d000; +} + +static void +Opcode_ivp_lt2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000; +} + +static void +Opcode_ivp_lt2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd42400; +} + +static void +Opcode_ivp_lt2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3818060; +} + +static void +Opcode_ivp_lt2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b8000; +} + +static void +Opcode_ivp_lt2nx8_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x981400; +} + +static void +Opcode_ivp_le2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b4000; +} + +static void +Opcode_ivp_le2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305a8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_le2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1481400; +} + +static void +Opcode_ivp_le2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec4400; +} + +static void +Opcode_ivp_le2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8300; +} + +static void +Opcode_ivp_le2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04810; +} + +static void +Opcode_ivp_le2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8200; +} + +static void +Opcode_ivp_le2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000; +} + +static void +Opcode_ivp_le2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9884008; +} + +static void +Opcode_ivp_le2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0c00; +} + +static void +Opcode_ivp_le2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c41c000; +} + +static void +Opcode_ivp_le2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000; +} + +static void +Opcode_ivp_le2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40c00; +} + +static void +Opcode_ivp_le2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3818000; +} + +static void +Opcode_ivp_le2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b4000; +} + +static void +Opcode_ivp_le2nx8_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970c00; +} + +static void +Opcode_ivp_eq2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x234000; +} + +static void +Opcode_ivp_eq2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305a8000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_eq2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1480400; +} + +static void +Opcode_ivp_eq2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ivp_eq2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a8304; +} + +static void +Opcode_ivp_eq2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04800; +} + +static void +Opcode_ivp_eq2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a8204; +} + +static void +Opcode_ivp_eq2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_ivp_eq2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b04000; +} + +static void +Opcode_ivp_eq2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ivp_eq2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c50c000; +} + +static void +Opcode_ivp_eq2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_ivp_eq2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ivp_eq2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3808040; +} + +static void +Opcode_ivp_eq2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x634000; +} + +static void +Opcode_ivp_eq2nx8_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970000; +} + +static void +Opcode_ivp_neq2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b8008; +} + +static void +Opcode_ivp_neq2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_neq2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1480c00; +} + +static void +Opcode_ivp_neq2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec5c00; +} + +static void +Opcode_ivp_neq2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a830a; +} + +static void +Opcode_ivp_neq2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04c18; +} + +static void +Opcode_ivp_neq2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a820a; +} + +static void +Opcode_ivp_neq2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec008; +} + +static void +Opcode_ivp_neq2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90d4008; +} + +static void +Opcode_ivp_neq2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c3c00; +} + +static void +Opcode_ivp_neq2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c42d000; +} + +static void +Opcode_ivp_neq2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec008; +} + +static void +Opcode_ivp_neq2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd43c00; +} + +static void +Opcode_ivp_neq2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3828020; +} + +static void +Opcode_ivp_neq2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b8008; +} + +static void +Opcode_ivp_neq2nx8_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x991c00; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x238008; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b0800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1440800; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec1800; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0308; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04c08; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0208; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0008; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9058008; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c3000; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c434000; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0008; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd43000; +} + +static void +Opcode_ivp_ltu2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3830000; +} + +static void +Opcode_ivp_ltu2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x638008; +} + +static void +Opcode_ivp_ltu2nx8_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x991000; +} + +static void +Opcode_ivp_leu2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x334008; +} + +static void +Opcode_ivp_leu2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305a9800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_leu2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c1000; +} + +static void +Opcode_ivp_leu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0c00; +} + +static void +Opcode_ivp_leu2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0304; +} + +static void +Opcode_ivp_leu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04c00; +} + +static void +Opcode_ivp_leu2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0204; +} + +static void +Opcode_ivp_leu2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8008; +} + +static void +Opcode_ivp_leu2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a04008; +} + +static void +Opcode_ivp_leu2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c1800; +} + +static void +Opcode_ivp_leu2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c514000; +} + +static void +Opcode_ivp_leu2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8008; +} + +static void +Opcode_ivp_leu2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd41800; +} + +static void +Opcode_ivp_leu2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3810040; +} + +static void +Opcode_ivp_leu2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x734008; +} + +static void +Opcode_ivp_leu2nx8_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x971800; +} + +static void +Opcode_ivp_add2nx8t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36400000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_add2nx8t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ivp_add2nx8t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_add2nx8t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2600000; +} + +static void +Opcode_ivp_add2nx8t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ivp_add2nx8t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300000; +} + +static void +Opcode_ivp_add2nx8t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8800000; +} + +static void +Opcode_ivp_add2nx8t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c200000; +} + +static void +Opcode_ivp_add2nx8t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_add2nx8t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800200; +} + +static void +Opcode_ivp_sub2nx8t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a306000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sub2nx8t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa40000; +} + +static void +Opcode_ivp_sub2nx8t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000; +} + +static void +Opcode_ivp_sub2nx8t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00200; +} + +static void +Opcode_ivp_sub2nx8t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300018; +} + +static void +Opcode_ivp_sub2nx8t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500300; +} + +static void +Opcode_ivp_sub2nx8t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00001; +} + +static void +Opcode_ivp_sub2nx8t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c703000; +} + +static void +Opcode_ivp_sub2nx8t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0000; +} + +static void +Opcode_ivp_sub2nx8t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800360; +} + +static void +Opcode_ivp_selnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_selnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ivp_selnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ivp_selnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ivp_seln_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34400000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_seln_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200000; +} + +static void +Opcode_ivp_seln_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200000; +} + +static void +Opcode_ivp_seln_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200000; +} + +static void +Opcode_ivp_seln_2x32t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_seln_2x32t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ivp_seln_2x32t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ivp_seln_2x32t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ivp_shfln_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30600200; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_shfln_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800800; +} + +static void +Opcode_ivp_shfln_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000800; +} + +static void +Opcode_ivp_shfln_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000800; +} + +static void +Opcode_ivp_sllin_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c503800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sllin_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400008; +} + +static void +Opcode_ivp_sllin_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0030e; +} + +static void +Opcode_ivp_sllin_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9700004; +} + +static void +Opcode_ivp_sllin_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e406800; +} + +static void +Opcode_ivp_sllin_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc70000; +} + +static void +Opcode_ivp_sllin_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28003e0; +} + +static void +Opcode_ivp_slsin_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a503c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_slsin_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3700008; +} + +static void +Opcode_ivp_slsin_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0030e; +} + +static void +Opcode_ivp_slsin_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9700007; +} + +static void +Opcode_ivp_slsin_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e407400; +} + +static void +Opcode_ivp_slsin_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc88000; +} + +static void +Opcode_ivp_slsin_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b003e0; +} + +static void +Opcode_ivp_srain_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srain_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000a; +} + +static void +Opcode_ivp_srain_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00200; +} + +static void +Opcode_ivp_srain_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9780002; +} + +static void +Opcode_ivp_srain_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e506000; +} + +static void +Opcode_ivp_srain_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca0000; +} + +static void +Opcode_ivp_srain_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e003e0; +} + +static void +Opcode_ivp_srlin_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srlin_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350000a; +} + +static void +Opcode_ivp_srlin_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00202; +} + +static void +Opcode_ivp_srlin_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9780005; +} + +static void +Opcode_ivp_srlin_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e506c00; +} + +static void +Opcode_ivp_srlin_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb8000; +} + +static void +Opcode_ivp_srlin_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500000; +} + +static void +Opcode_ivp_slln_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38503c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_slln_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3600008; +} + +static void +Opcode_ivp_slln_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0030e; +} + +static void +Opcode_ivp_slln_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9700006; +} + +static void +Opcode_ivp_slln_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e407000; +} + +static void +Opcode_ivp_slln_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ivp_slln_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a003e0; +} + +static void +Opcode_ivp_srln_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srln_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370000a; +} + +static void +Opcode_ivp_srln_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00202; +} + +static void +Opcode_ivp_srln_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9780007; +} + +static void +Opcode_ivp_srln_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e507400; +} + +static void +Opcode_ivp_srln_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc8000; +} + +static void +Opcode_ivp_srln_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700000; +} + +static void +Opcode_ivp_slan_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a503800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_slan_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3300008; +} + +static void +Opcode_ivp_slan_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0030e; +} + +static void +Opcode_ivp_slan_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9700003; +} + +static void +Opcode_ivp_slan_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e406400; +} + +static void +Opcode_ivp_slan_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc68000; +} + +static void +Opcode_ivp_slan_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f003c0; +} + +static void +Opcode_ivp_sran_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sran_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000a; +} + +static void +Opcode_ivp_sran_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00202; +} + +static void +Opcode_ivp_sran_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9780004; +} + +static void +Opcode_ivp_sran_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e506800; +} + +static void +Opcode_ivp_sran_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb0000; +} + +static void +Opcode_ivp_sran_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400000; +} + +static void +Opcode_ivp_slsn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e503c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_slsn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x310000a; +} + +static void +Opcode_ivp_slsn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00200; +} + +static void +Opcode_ivp_slsn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9780001; +} + +static void +Opcode_ivp_slsn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e407c00; +} + +static void +Opcode_ivp_slsn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc98000; +} + +static void +Opcode_ivp_slsn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d003e0; +} + +static void +Opcode_ivp_srsn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srsn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x310000c; +} + +static void +Opcode_ivp_srsn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00204; +} + +static void +Opcode_ivp_srsn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400009; +} + +static void +Opcode_ivp_srsn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e507c00; +} + +static void +Opcode_ivp_srsn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd8000; +} + +static void +Opcode_ivp_srsn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500020; +} + +static void +Opcode_ivp_raddn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502030; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000055; +} + +static void +Opcode_ivp_raddn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800355; +} + +static void +Opcode_ivp_raddn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c02a00; +} + +static void +Opcode_ivp_raddn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607860; +} + +static void +Opcode_ivp_raddn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd900f0; +} + +static void +Opcode_ivp_raddn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c001b7; +} + +static void +Opcode_ivp_rmaxn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502421; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rmaxn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100065; +} + +static void +Opcode_ivp_rmaxn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900365; +} + +static void +Opcode_ivp_rmaxn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c82c00; +} + +static void +Opcode_ivp_rmaxn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607c70; +} + +static void +Opcode_ivp_rmaxn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb80f0; +} + +static void +Opcode_ivp_rmaxn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f001b6; +} + +static void +Opcode_ivp_rminn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502821; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rminn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200065; +} + +static void +Opcode_ivp_rminn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00365; +} + +static void +Opcode_ivp_rminn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d02c00; +} + +static void +Opcode_ivp_rminn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607871; +} + +static void +Opcode_ivp_rminn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd38010; +} + +static void +Opcode_ivp_rminn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001c6; +} + +static void +Opcode_ivp_rmaxun_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502820; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rmaxun_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200045; +} + +static void +Opcode_ivp_rmaxun_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00345; +} + +static void +Opcode_ivp_rmaxun_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d02800; +} + +static void +Opcode_ivp_rmaxun_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607851; +} + +static void +Opcode_ivp_rmaxun_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd38000; +} + +static void +Opcode_ivp_rmaxun_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001c4; +} + +static void +Opcode_ivp_rminun_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502c20; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rminun_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3300045; +} + +static void +Opcode_ivp_rminun_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b00345; +} + +static void +Opcode_ivp_rminun_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d82800; +} + +static void +Opcode_ivp_rminun_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607c51; +} + +static void +Opcode_ivp_rminun_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd38020; +} + +static void +Opcode_ivp_rminun_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001d4; +} + +static void +Opcode_ivp_raddn_2x32t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800ca0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddn_2x32t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000061; +} + +static void +Opcode_ivp_raddn_2x32t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800361; +} + +static void +Opcode_ivp_raddn_2x32t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01400; +} + +static void +Opcode_ivp_raddn_2x32t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e305020; +} + +static void +Opcode_ivp_raddn_2x32t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80020; +} + +static void +Opcode_ivp_raddn_2x32t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800185; +} + +static void +Opcode_ivp_abs2nx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a30040; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_abs2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27500c0a; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_abs2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11180e0; +} + +static void +Opcode_ivp_abs2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf50060; +} + +static void +Opcode_ivp_abs2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330500e; +} + +static void +Opcode_ivp_abs2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f60002; +} + +static void +Opcode_ivp_abs2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f05208; +} + +static void +Opcode_ivp_abs2nx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82c0c0; +} + +static void +Opcode_ivp_abs2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94800c9; +} + +static void +Opcode_ivp_abs2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8040; +} + +static void +Opcode_ivp_abs2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606c08; +} + +static void +Opcode_ivp_abs2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20200; +} + +static void +Opcode_ivp_abs2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8000; +} + +static void +Opcode_ivp_abs2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2705140; +} + +static void +Opcode_ivp_absn_2x32_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a30070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_absn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27500f0a; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_absn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11182f0; +} + +static void +Opcode_ivp_absn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf68040; +} + +static void +Opcode_ivp_absn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3305c0e; +} + +static void +Opcode_ivp_absn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f60013; +} + +static void +Opcode_ivp_absn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f05e08; +} + +static void +Opcode_ivp_absn_2x32_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82c0f0; +} + +static void +Opcode_ivp_absn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94800f9; +} + +static void +Opcode_ivp_absn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8080; +} + +static void +Opcode_ivp_absn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606e08; +} + +static void +Opcode_ivp_absn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20202; +} + +static void +Opcode_ivp_absn_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8040; +} + +static void +Opcode_ivp_absn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2705d40; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c403800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330000; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd70000; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100208; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000a; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0020c; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e8000c; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x570000; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e207800; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x470000; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c00380; +} + +static void +Opcode_ivp_rotri2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25500c08; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rotri2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe88008; +} + +static void +Opcode_ivp_rotri2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320400e; +} + +static void +Opcode_ivp_rotri2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d84400; +} + +static void +Opcode_ivp_rotri2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e04208; +} + +static void +Opcode_ivp_rotri2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9480088; +} + +static void +Opcode_ivp_rotri2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606808; +} + +static void +Opcode_ivp_rotri2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10200; +} + +static void +Opcode_ivp_rotri2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2604140; +} + +static void +Opcode_ivp_rotrinx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21500c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rotrinx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe70000; +} + +static void +Opcode_ivp_rotrinx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000e; +} + +static void +Opcode_ivp_rotrinx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04000; +} + +static void +Opcode_ivp_rotrinx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00208; +} + +static void +Opcode_ivp_rotrinx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940000e; +} + +static void +Opcode_ivp_rotrinx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606000; +} + +static void +Opcode_ivp_rotrinx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ivp_rotrinx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400140; +} + +static void +Opcode_ivp_rotrin_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a503400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rotrin_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0030e; +} + +static void +Opcode_ivp_rotrin_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0030c; +} + +static void +Opcode_ivp_rotrin_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9680007; +} + +static void +Opcode_ivp_rotrin_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e307400; +} + +static void +Opcode_ivp_rotrin_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc48000; +} + +static void +Opcode_ivp_rotrin_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b003c0; +} + +static void +Opcode_ivp_rotrnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c503400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rotrnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000008; +} + +static void +Opcode_ivp_rotrnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280030e; +} + +static void +Opcode_ivp_rotrnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9700000; +} + +static void +Opcode_ivp_rotrnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e307800; +} + +static void +Opcode_ivp_rotrnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc50000; +} + +static void +Opcode_ivp_rotrnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c003c0; +} + +static void +Opcode_ivp_rotrn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e503400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rotrn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100008; +} + +static void +Opcode_ivp_rotrn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290030e; +} + +static void +Opcode_ivp_rotrn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9700001; +} + +static void +Opcode_ivp_rotrn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e307c00; +} + +static void +Opcode_ivp_rotrn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc58000; +} + +static void +Opcode_ivp_rotrn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d003c0; +} + +static void +Opcode_ivp_addn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e402800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_addn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1268000; +} + +static void +Opcode_ivp_addn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc68000; +} + +static void +Opcode_ivp_addn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0020a; +} + +static void +Opcode_ivp_addn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00015; +} + +static void +Opcode_ivp_addn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0010a; +} + +static void +Opcode_ivp_addn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d8000b; +} + +static void +Opcode_ivp_addn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b8000; +} + +static void +Opcode_ivp_addn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e006c00; +} + +static void +Opcode_ivp_addn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb48000; +} + +static void +Opcode_ivp_addn_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b8000; +} + +static void +Opcode_ivp_addn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b00280; +} + +static void +Opcode_ivp_subn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c403c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_subn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1350000; +} + +static void +Opcode_ivp_subn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd90000; +} + +static void +Opcode_ivp_subn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100300; +} + +static void +Opcode_ivp_subn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000b; +} + +static void +Opcode_ivp_subn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800308; +} + +static void +Opcode_ivp_subn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f0000c; +} + +static void +Opcode_ivp_subn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_ivp_subn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e306800; +} + +static void +Opcode_ivp_subn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30000; +} + +static void +Opcode_ivp_subn_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_ivp_subn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28003a0; +} + +static void +Opcode_ivp_negn_2x32_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a300e0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30602002; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11082e0; +} + +static void +Opcode_ivp_negn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf400a0; +} + +static void +Opcode_ivp_negn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801100; +} + +static void +Opcode_ivp_negn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e68000; +} + +static void +Opcode_ivp_negn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001100; +} + +static void +Opcode_ivp_negn_2x32_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83c0e0; +} + +static void +Opcode_ivp_negn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9580020; +} + +static void +Opcode_ivp_negn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8120; +} + +static void +Opcode_ivp_negn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606f0a; +} + +static void +Opcode_ivp_negn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20306; +} + +static void +Opcode_ivp_negn_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a80e0; +} + +static void +Opcode_ivp_negn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000c00; +} + +static void +Opcode_ivp_minn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e403000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_minn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ivp_minn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd38000; +} + +static void +Opcode_ivp_minn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0020e; +} + +static void +Opcode_ivp_minn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00018; +} + +static void +Opcode_ivp_minn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00204; +} + +static void +Opcode_ivp_minn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d8000d; +} + +static void +Opcode_ivp_minn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ivp_minn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e206000; +} + +static void +Opcode_ivp_minn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe0000; +} + +static void +Opcode_ivp_minn_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ivp_minn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d002e0; +} + +static void +Opcode_ivp_minun_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e403400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_minun_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318000; +} + +static void +Opcode_ivp_minun_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd58000; +} + +static void +Opcode_ivp_minun_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100202; +} + +static void +Opcode_ivp_minun_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00019; +} + +static void +Opcode_ivp_minun_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00208; +} + +static void +Opcode_ivp_minun_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e0000d; +} + +static void +Opcode_ivp_minun_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x558000; +} + +static void +Opcode_ivp_minun_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e206c00; +} + +static void +Opcode_ivp_minun_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf8000; +} + +static void +Opcode_ivp_minun_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x458000; +} + +static void +Opcode_ivp_minun_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900380; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e401000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12d0000; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce8000; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0020c; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190001b; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0010e; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000f; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510000; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e106800; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb0000; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_ivp_maxn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b002c0; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e401800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e8000; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd08000; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0020c; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190001d; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0010e; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c8000f; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x528000; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e107400; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc8000; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x428000; +} + +static void +Opcode_ivp_maxun_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f002c0; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a403800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1328000; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd68000; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100206; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00019; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0020a; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e0000f; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x568000; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e207400; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc08000; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x468000; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b00380; +} + +static void +Opcode_ivp_nsan_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30603c02; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_nsan_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380110e; +} + +static void +Opcode_ivp_nsan_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300110e; +} + +static void +Opcode_ivp_nsan_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9580027; +} + +static void +Opcode_ivp_nsan_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606f0c; +} + +static void +Opcode_ivp_nsan_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2030a; +} + +static void +Opcode_ivp_nsan_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000f20; +} + +static void +Opcode_ivp_nsaun_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30602502; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_nsaun_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801502; +} + +static void +Opcode_ivp_nsaun_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001502; +} + +static void +Opcode_ivp_nsaun_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9580031; +} + +static void +Opcode_ivp_nsaun_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606d0e; +} + +static void +Opcode_ivp_nsaun_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2030c; +} + +static void +Opcode_ivp_nsaun_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000d40; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b8000; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b8400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400c00; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec5400; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a8308; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04818; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a8208; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9054008; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c2c00; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c42c000; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd42c00; +} + +static void +Opcode_ivp_ltn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3828000; +} + +static void +Opcode_ivp_ltn_2x32_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b8000; +} + +static void +Opcode_ivp_ltn_2x32_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x981c00; +} + +static void +Opcode_ivp_len_2x32_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b4008; +} + +static void +Opcode_ivp_len_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305a9400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_len_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1481c00; +} + +static void +Opcode_ivp_len_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec4800; +} + +static void +Opcode_ivp_len_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8302; +} + +static void +Opcode_ivp_len_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04c10; +} + +static void +Opcode_ivp_len_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8202; +} + +static void +Opcode_ivp_len_2x32_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4008; +} + +static void +Opcode_ivp_len_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9984008; +} + +static void +Opcode_ivp_len_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c1400; +} + +static void +Opcode_ivp_len_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c41d000; +} + +static void +Opcode_ivp_len_2x32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4008; +} + +static void +Opcode_ivp_len_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd41400; +} + +static void +Opcode_ivp_len_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3818020; +} + +static void +Opcode_ivp_len_2x32_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b4008; +} + +static void +Opcode_ivp_len_2x32_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x971400; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x334000; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305a8800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1481000; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0400; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0300; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04800; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0200; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9804008; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0800; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c414000; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40800; +} + +static void +Opcode_ivp_eqn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3810000; +} + +static void +Opcode_ivp_eqn_2x32_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x734000; +} + +static void +Opcode_ivp_eqn_2x32_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970800; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2bc000; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b9000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c0c00; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec6000; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b830a; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05010; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b820a; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90dc008; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c4400; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c43d000; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd44400; +} + +static void +Opcode_ivp_neqn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3838020; +} + +static void +Opcode_ivp_neqn_2x32_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6bc000; +} + +static void +Opcode_ivp_neqn_2x32_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a0400; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x338008; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1480800; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec1c00; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a030a; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04c08; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a020a; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8008; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90d0008; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c3800; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c425000; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8008; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd43800; +} + +static void +Opcode_ivp_ltun_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3820020; +} + +static void +Opcode_ivp_ltun_2x32_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x738008; +} + +static void +Opcode_ivp_ltun_2x32_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x991800; +} + +static void +Opcode_ivp_leun_2x32_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x238000; +} + +static void +Opcode_ivp_leun_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_leun_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c1800; +} + +static void +Opcode_ivp_leun_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec1000; +} + +static void +Opcode_ivp_leun_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0306; +} + +static void +Opcode_ivp_leun_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04808; +} + +static void +Opcode_ivp_leun_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0206; +} + +static void +Opcode_ivp_leun_2x32_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_ivp_leun_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b04008; +} + +static void +Opcode_ivp_leun_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c2000; +} + +static void +Opcode_ivp_leun_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c515000; +} + +static void +Opcode_ivp_leun_2x32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_ivp_leun_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd42000; +} + +static void +Opcode_ivp_leun_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3810060; +} + +static void +Opcode_ivp_leun_2x32_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x638000; +} + +static void +Opcode_ivp_leun_2x32_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x981000; +} + +static void +Opcode_ivp_lat2nx8_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_lat2nx8_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_lat2nx8_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_lat2nx8_xp_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_muluu2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260009; +} + +static void +Opcode_ivp_muluu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80005; +} + +static void +Opcode_ivp_muluu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06409; +} + +static void +Opcode_ivp_muluu2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180009; +} + +static void +Opcode_ivp_muluu2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130009; +} + +static void +Opcode_ivp_muluu2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650003; +} + +static void +Opcode_ivp_muluua2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26000a; +} + +static void +Opcode_ivp_muluua2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80006; +} + +static void +Opcode_ivp_muluua2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06809; +} + +static void +Opcode_ivp_muluua2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000a; +} + +static void +Opcode_ivp_muluua2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000a; +} + +static void +Opcode_ivp_muluua2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650004; +} + +static void +Opcode_ivp_mulus2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c00b; +} + +static void +Opcode_ivp_mulus2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0007; +} + +static void +Opcode_ivp_mulus2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c06; +} + +static void +Opcode_ivp_mulus2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000b; +} + +static void +Opcode_ivp_mulus2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000b; +} + +static void +Opcode_ivp_mulus2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c005; +} + +static void +Opcode_ivp_mulusa2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c00c; +} + +static void +Opcode_ivp_mulusa2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0008; +} + +static void +Opcode_ivp_mulusa2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07007; +} + +static void +Opcode_ivp_mulusa2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000c; +} + +static void +Opcode_ivp_mulusa2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000c; +} + +static void +Opcode_ivp_mulusa2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c006; +} + +static void +Opcode_ivp_muli2nx8x16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_ivp_muli2nx8x16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00001; +} + +static void +Opcode_ivp_muli2nx8x16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400001; +} + +static void +Opcode_ivp_mulai2nx8x16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_mulai2nx8x16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00000; +} + +static void +Opcode_ivp_mulai2nx8x16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_mulusi2nx8x16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_ivp_mulusi2nx8x16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00003; +} + +static void +Opcode_ivp_mulusi2nx8x16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400003; +} + +static void +Opcode_ivp_mulusai2nx8x16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_ivp_mulusai2nx8x16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00002; +} + +static void +Opcode_ivp_mulusai2nx8x16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400002; +} + +static void +Opcode_ivp_muli2nr8x16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400020; +} + +static void +Opcode_ivp_muli2nr8x16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e08000; +} + +static void +Opcode_ivp_muli2nr8x16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800200; +} + +static void +Opcode_ivp_mulai2nr8x16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_mulai2nr8x16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00000; +} + +static void +Opcode_ivp_mulai2nr8x16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ivp_mulusi2nr8x16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400060; +} + +static void +Opcode_ivp_mulusi2nr8x16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e18000; +} + +static void +Opcode_ivp_mulusi2nr8x16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800600; +} + +static void +Opcode_ivp_mulusai2nr8x16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400040; +} + +static void +Opcode_ivp_mulusai2nr8x16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e10000; +} + +static void +Opcode_ivp_mulusai2nr8x16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800400; +} + +static void +Opcode_ivp_mulusa2n8xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c300; +} + +static void +Opcode_ivp_mulusa2n8xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33810; +} + +static void +Opcode_ivp_mulusa2n8xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200060; +} + +static void +Opcode_ivp_mulusa2n8xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0060; +} + +static void +Opcode_ivp_mulusa2n8xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x161060; +} + +static void +Opcode_ivp_mulusa2n8xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65c030; +} + +static void +Opcode_ivp_mulus2n8xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c200; +} + +static void +Opcode_ivp_mulus2n8xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33800; +} + +static void +Opcode_ivp_mulus2n8xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200040; +} + +static void +Opcode_ivp_mulus2n8xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0040; +} + +static void +Opcode_ivp_mulus2n8xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x161040; +} + +static void +Opcode_ivp_mulus2n8xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65c020; +} + +static void +Opcode_ivp_mula2n8xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c100; +} + +static void +Opcode_ivp_mula2n8xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf23c10; +} + +static void +Opcode_ivp_mula2n8xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200020; +} + +static void +Opcode_ivp_mula2n8xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0020; +} + +static void +Opcode_ivp_mula2n8xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x161020; +} + +static void +Opcode_ivp_mula2n8xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65c010; +} + +static void +Opcode_ivp_mul2n8xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c000; +} + +static void +Opcode_ivp_mul2n8xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf23c00; +} + +static void +Opcode_ivp_mul2n8xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200000; +} + +static void +Opcode_ivp_mul2n8xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_ivp_mul2n8xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x161000; +} + +static void +Opcode_ivp_mul2n8xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65c000; +} + +static void +Opcode_ivp_dsel2nx8i_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_dsel2nx8i_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000000; +} + +static void +Opcode_ivp_dsel2nx8i_h_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_dsel2nx8i_h_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a004000; +} + +static void +Opcode_ivp_dselnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_dselnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000000; +} + +static void +Opcode_ivp_dselnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_dselnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_injbi2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a450000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_injbi2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3038200; +} + +static void +Opcode_ivp_injbi2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1958200; +} + +static void +Opcode_ivp_injbi2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c03000; +} + +static void +Opcode_ivp_injbi2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c444000; +} + +static void +Opcode_ivp_extbi2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x217c0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extbi2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28f830c; +} + +static void +Opcode_ivp_extbi2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28f820c; +} + +static void +Opcode_ivp_extbi2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980c008; +} + +static void +Opcode_ivp_extbi2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c444010; +} + +static void +Opcode_ivp_extbi2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd800e0; +} + +static void +Opcode_ivp_extbi2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3888000; +} + +static void +Opcode_ivp_movva32_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc007; +} + +static void +Opcode_ivp_movva32_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282005; +} + +static void +Opcode_ivp_movva32_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282005; +} + +static void +Opcode_ivp_movva32_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8005; +} + +static void +Opcode_ivp_movva32_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8005; +} + +static void +Opcode_ivp_movva32_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6007; +} + +static void +Opcode_ivp_movav32_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d7a00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movav32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a450003; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movav32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1459600; +} + +static void +Opcode_ivp_movav32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3038203; +} + +static void +Opcode_ivp_movav32_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54600d; +} + +static void +Opcode_ivp_movav32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29f820d; +} + +static void +Opcode_ivp_movav32_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9dba00; +} + +static void +Opcode_ivp_movav32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980e009; +} + +static void +Opcode_ivp_movav32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c30e000; +} + +static void +Opcode_ivp_movav32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcfc003; +} + +static void +Opcode_ivp_movav32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3988010; +} + +static void +Opcode_ivp_movww_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800d; +} + +static void +Opcode_ivp_movww_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf518e0; +} + +static void +Opcode_ivp_movww_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e69803; +} + +static void +Opcode_ivp_movww_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000e; +} + +static void +Opcode_ivp_movww_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15100b; +} + +static void +Opcode_ivp_movww_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65b004; +} + +static void +Opcode_ivp_ls2nx8_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10858000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ls2nx8_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d8000; +} + +static void +Opcode_ivp_ls2nx8_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c000; +} + +static void +Opcode_ivp_ls2nx8_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c000; +} + +static void +Opcode_ivp_ls2nx8_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x958000; +} + +static void +Opcode_ivp_ls2nx8_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10540000; +} + +static void +Opcode_ivp_ls2nx8_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1096e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ls2nx8_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138a000; +} + +static void +Opcode_ivp_ls2nx8_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21e000; +} + +static void +Opcode_ivp_ls2nx8_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21e000; +} + +static void +Opcode_ivp_ls2nx8_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6e000; +} + +static void +Opcode_ivp_ls2nx8_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae000; +} + +static void +Opcode_ivp_ls2nx8_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108c8000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ls2nx8_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdec000; +} + +static void +Opcode_ivp_ls2nx8_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1da000; +} + +static void +Opcode_ivp_ls2nx8_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca000; +} + +static void +Opcode_ivp_ls2nx8_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c8000; +} + +static void +Opcode_ivp_ls2nx8_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10578000; +} + +static void +Opcode_ivp_ls2nx8_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108ca000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ls2nx8_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdee000; +} + +static void +Opcode_ivp_ls2nx8_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea000; +} + +static void +Opcode_ivp_ls2nx8_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1da000; +} + +static void +Opcode_ivp_ls2nx8_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ca000; +} + +static void +Opcode_ivp_ls2nx8_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057a000; +} + +static void +Opcode_ivp_ss2nx8_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10890000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ss2nx8_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1210000; +} + +static void +Opcode_ivp_ss2nx8_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x518000; +} + +static void +Opcode_ivp_ss2nx8_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x990000; +} + +static void +Opcode_ivp_ss2nx8_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109a2000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ss2nx8_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b4000; +} + +static void +Opcode_ivp_ss2nx8_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57e000; +} + +static void +Opcode_ivp_ss2nx8_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa2000; +} + +static void +Opcode_ivp_ss2nx8_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1091a000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ss2nx8_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14a2000; +} + +static void +Opcode_ivp_ss2nx8_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x554000; +} + +static void +Opcode_ivp_ss2nx8_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1a000; +} + +static void +Opcode_ivp_ss2nx8_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1091e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ss2nx8_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14aa000; +} + +static void +Opcode_ivp_ss2nx8_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x556000; +} + +static void +Opcode_ivp_ss2nx8_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1e000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107e8000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1068000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14a000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14a000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e8000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f8000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x738000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e8000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107f0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f0000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f0000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e0000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f0000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e0000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e402400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1248000; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc48000; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f00208; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00014; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f00108; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9300007; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x498000; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e105c00; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb28000; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x398000; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f000e0; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a402400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1238000; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc38000; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d00208; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00014; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d00108; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9300005; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x488000; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e105800; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb18000; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x388000; +} + +static void +Opcode_ivp_abssub2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d000e0; +} + +static void +Opcode_ivp_movvint8_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fa080; +} + +static void +Opcode_ivp_movvint8_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x256000; +} + +static void +Opcode_ivp_movvint8_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x256000; +} + +static void +Opcode_ivp_movvint8_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x196010; +} + +static void +Opcode_ivp_movvint8_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x196080; +} + +static void +Opcode_ivp_movvint8_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b4080; +} + +static void +Opcode_ivp_movva8_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc008; +} + +static void +Opcode_ivp_movva8_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282006; +} + +static void +Opcode_ivp_movva8_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282006; +} + +static void +Opcode_ivp_movva8_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8006; +} + +static void +Opcode_ivp_movva8_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8006; +} + +static void +Opcode_ivp_movva8_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2000; +} + +static void +Opcode_ivp_movavu8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a50200; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movavu8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a450009; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movavu8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510400; +} + +static void +Opcode_ivp_movavu8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3038209; +} + +static void +Opcode_ivp_movavu8_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54800c; +} + +static void +Opcode_ivp_movavu8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2cf820d; +} + +static void +Opcode_ivp_movavu8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d7800; +} + +static void +Opcode_ivp_movavu8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980e00c; +} + +static void +Opcode_ivp_movavu8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c20e002; +} + +static void +Opcode_ivp_movavu8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcfc009; +} + +static void +Opcode_ivp_movavu8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c88010; +} + +static void +Opcode_ivp_slli2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25500c0c; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_slli2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8800c; +} + +static void +Opcode_ivp_slli2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320600e; +} + +static void +Opcode_ivp_slli2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc4400; +} + +static void +Opcode_ivp_slli2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e06208; +} + +static void +Opcode_ivp_slli2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94800c8; +} + +static void +Opcode_ivp_slli2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e60680c; +} + +static void +Opcode_ivp_slli2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10300; +} + +static void +Opcode_ivp_slli2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2606140; +} + +static void +Opcode_ivp_srai2nx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a10000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srai2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27500c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srai2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100080; +} + +static void +Opcode_ivp_srai2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe90000; +} + +static void +Opcode_ivp_srai2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000e; +} + +static void +Opcode_ivp_srai2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e80000; +} + +static void +Opcode_ivp_srai2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00208; +} + +static void +Opcode_ivp_srai2nx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820080; +} + +static void +Opcode_ivp_srai2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9480009; +} + +static void +Opcode_ivp_srai2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606c00; +} + +static void +Opcode_ivp_srai2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_ivp_srai2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700140; +} + +static void +Opcode_ivp_srli2nx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a10080; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srli2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27500c04; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srli2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100280; +} + +static void +Opcode_ivp_srli2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe98000; +} + +static void +Opcode_ivp_srli2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330200e; +} + +static void +Opcode_ivp_srli2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f80000; +} + +static void +Opcode_ivp_srli2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f02208; +} + +static void +Opcode_ivp_srli2nx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x824080; +} + +static void +Opcode_ivp_srli2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9480049; +} + +static void +Opcode_ivp_srli2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606c04; +} + +static void +Opcode_ivp_srli2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20100; +} + +static void +Opcode_ivp_srli2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2702140; +} + +static void +Opcode_ivp_packl2nx24_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1740d8; +} + +static void +Opcode_ivp_packl2nx24_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268058; +} + +static void +Opcode_ivp_packl2nx24_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28204c; +} + +static void +Opcode_ivp_packl2nx24_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980d8; +} + +static void +Opcode_ivp_packl2nx24_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b20a0; +} + +static void +Opcode_ivp_packl2nx24_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca0a8; +} + +static void +Opcode_ivp_packvr2nx24_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6000; +} + +static void +Opcode_ivp_packvr2nx24_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258000; +} + +static void +Opcode_ivp_packvr2nx24_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258000; +} + +static void +Opcode_ivp_packvr2nx24_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_ivp_packvr2nx24_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_ivp_packvr2nx24_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6000; +} + +static void +Opcode_ivp_packvru2nx24_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f6008; +} + +static void +Opcode_ivp_packvru2nx24_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e008; +} + +static void +Opcode_ivp_packvru2nx24_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e008; +} + +static void +Opcode_ivp_packvru2nx24_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6008; +} + +static void +Opcode_ivp_packvru2nx24_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6008; +} + +static void +Opcode_ivp_packvru2nx24_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4008; +} + +static void +Opcode_ivp_packlnx48_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1780d8; +} + +static void +Opcode_ivp_packlnx48_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c058; +} + +static void +Opcode_ivp_packlnx48_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28206c; +} + +static void +Opcode_ivp_packlnx48_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980dc; +} + +static void +Opcode_ivp_packlnx48_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b20a8; +} + +static void +Opcode_ivp_packlnx48_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc0a0; +} + +static void +Opcode_ivp_packl2nx24_1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1760d8; +} + +static void +Opcode_ivp_packl2nx24_1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a058; +} + +static void +Opcode_ivp_packl2nx24_1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28205c; +} + +static void +Opcode_ivp_packl2nx24_1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980f8; +} + +static void +Opcode_ivp_packl2nx24_1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b20a4; +} + +static void +Opcode_ivp_packl2nx24_1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca0ac; +} + +static void +Opcode_ivp_packvr2nx24_0_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6004; +} + +static void +Opcode_ivp_packvr2nx24_0_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258004; +} + +static void +Opcode_ivp_packvr2nx24_0_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258004; +} + +static void +Opcode_ivp_packvr2nx24_0_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0004; +} + +static void +Opcode_ivp_packvr2nx24_0_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0004; +} + +static void +Opcode_ivp_packvr2nx24_0_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6004; +} + +static void +Opcode_ivp_packvr2nx24_1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6008; +} + +static void +Opcode_ivp_packvr2nx24_1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a000; +} + +static void +Opcode_ivp_packvr2nx24_1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a000; +} + +static void +Opcode_ivp_packvr2nx24_1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0008; +} + +static void +Opcode_ivp_packvr2nx24_1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0008; +} + +static void +Opcode_ivp_packvr2nx24_1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6008; +} + +static void +Opcode_ivp_packvru2nx24_0_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f600c; +} + +static void +Opcode_ivp_packvru2nx24_0_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e00c; +} + +static void +Opcode_ivp_packvru2nx24_0_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e00c; +} + +static void +Opcode_ivp_packvru2nx24_0_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a600c; +} + +static void +Opcode_ivp_packvru2nx24_0_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a600c; +} + +static void +Opcode_ivp_packvru2nx24_0_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c400c; +} + +static void +Opcode_ivp_packvru2nx24_1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc000; +} + +static void +Opcode_ivp_packvru2nx24_1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282000; +} + +static void +Opcode_ivp_packvru2nx24_1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282000; +} + +static void +Opcode_ivp_packvru2nx24_1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8000; +} + +static void +Opcode_ivp_packvru2nx24_1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8000; +} + +static void +Opcode_ivp_packvru2nx24_1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6000; +} + +static void +Opcode_ivp_packvrnr2nx24_0_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6000; +} + +static void +Opcode_ivp_packvrnr2nx24_0_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c000; +} + +static void +Opcode_ivp_packvrnr2nx24_0_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c000; +} + +static void +Opcode_ivp_packvrnr2nx24_0_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2000; +} + +static void +Opcode_ivp_packvrnr2nx24_0_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2000; +} + +static void +Opcode_ivp_packvrnr2nx24_0_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ivp_packvrnr2nx24_1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6004; +} + +static void +Opcode_ivp_packvrnr2nx24_1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c004; +} + +static void +Opcode_ivp_packvrnr2nx24_1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c004; +} + +static void +Opcode_ivp_packvrnr2nx24_1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2004; +} + +static void +Opcode_ivp_packvrnr2nx24_1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2004; +} + +static void +Opcode_ivp_packvrnr2nx24_1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0004; +} + +static void +Opcode_ivp_packmnx48_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c0d8; +} + +static void +Opcode_ivp_packmnx48_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26005c; +} + +static void +Opcode_ivp_packmnx48_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28208c; +} + +static void +Opcode_ivp_packmnx48_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a0d0; +} + +static void +Opcode_ivp_packmnx48_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b40a0; +} + +static void +Opcode_ivp_packmnx48_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc0a8; +} + +static void +Opcode_ivp_packvrnx48_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6008; +} + +static void +Opcode_ivp_packvrnx48_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a008; +} + +static void +Opcode_ivp_packvrnx48_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a008; +} + +static void +Opcode_ivp_packvrnx48_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4008; +} + +static void +Opcode_ivp_packvrnx48_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4008; +} + +static void +Opcode_ivp_packvrnx48_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c2008; +} + +static void +Opcode_ivp_unpks2nx8_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf50080; +} + +static void +Opcode_ivp_unpks2nx8_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f68001; +} + +static void +Opcode_ivp_unpks2nx8_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf58080; +} + +static void +Opcode_ivp_unpks2nx8_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f68011; +} + +static void +Opcode_ivp_unpksnx16_l_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf580a0; +} + +static void +Opcode_ivp_unpksnx16_l_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e68012; +} + +static void +Opcode_ivp_unpksnx16_h_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf500a0; +} + +static void +Opcode_ivp_unpksnx16_h_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e68002; +} + +static void +Opcode_ivp_sel2nx8i_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sel2nx8i_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; +} + +static void +Opcode_ivp_sel2nx8i_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; +} + +static void +Opcode_ivp_sel2nx8i_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_ivp_sel2nx8i_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a005000; +} + +static void +Opcode_ivp_sel2nx8i_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_sel2nx8i_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; +} + +static void +Opcode_ivp_sel2nx8i_s0_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_sel2nx8i_s0_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_sel2nx8i_s2_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_sel2nx8i_s4_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_shfl2nx8i_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38402000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_shfl2nx8i_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800208; +} + +static void +Opcode_ivp_shfl2nx8i_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800108; +} + +static void +Opcode_ivp_shfl2nx8i_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9300000; +} + +static void +Opcode_ivp_shfl2nx8i_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c105000; +} + +static void +Opcode_ivp_shfl2nx8i_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac0000; +} + +static void +Opcode_ivp_shfl2nx8i_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000e0; +} + +static void +Opcode_ivp_shfl2nx8i_s0_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a30000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_shfl2nx8i_s0_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100e0; +} + +static void +Opcode_ivp_shfl2nx8i_s0_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280c0; +} + +static void +Opcode_ivp_shfl2nx8i_s0_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00c0; +} + +static void +Opcode_ivp_shfl2nx8i_s0_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8200c0; +} + +static void +Opcode_ivp_shfl2nx8i_s0_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa600c0; +} + +static void +Opcode_ivp_shfl2nx8i_s2_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40040; +} + +static void +Opcode_ivp_shfl2nx8i_s4_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8000; +} + +static void +Opcode_ivp_sel2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30400000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sel2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ivp_sel2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ivp_sel2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ivp_shfl2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30600000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_shfl2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800000; +} + +static void +Opcode_ivp_shfl2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000000; +} + +static void +Opcode_ivp_shfl2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000000; +} + +static void +Opcode_ivp_sel2nx8t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sel2nx8t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_sel2nx8t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_sel2nx8t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_sqzn_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700a0; +} + +static void +Opcode_ivp_sqzn_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260020; +} + +static void +Opcode_ivp_sqzn_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_ivp_sqzn_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191000; +} + +static void +Opcode_ivp_sqzn_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_ivp_unsqzn_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1710a0; +} + +static void +Opcode_ivp_unsqzn_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261020; +} + +static void +Opcode_ivp_unsqzn_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191000; +} + +static void +Opcode_ivp_unsqzn_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192000; +} + +static void +Opcode_ivp_unsqzn_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1000; +} + +static void +Opcode_ivp_mulnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25800b; +} + +static void +Opcode_ivp_mulnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0007; +} + +static void +Opcode_ivp_mulnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c02; +} + +static void +Opcode_ivp_mulnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000b; +} + +static void +Opcode_ivp_mulnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000b; +} + +static void +Opcode_ivp_mulnx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648005; +} + +static void +Opcode_ivp_mulanx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258007; +} + +static void +Opcode_ivp_mulanx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0003; +} + +static void +Opcode_ivp_mulanx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c01; +} + +static void +Opcode_ivp_mulanx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160007; +} + +static void +Opcode_ivp_mulanx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110007; +} + +static void +Opcode_ivp_mulanx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648001; +} + +static void +Opcode_ivp_muluunx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264000; +} + +static void +Opcode_ivp_muluunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000c; +} + +static void +Opcode_ivp_muluunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0600a; +} + +static void +Opcode_ivp_muluunx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_ivp_muluunx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_muluunx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65000a; +} + +static void +Opcode_ivp_muluuanx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26000c; +} + +static void +Opcode_ivp_muluuanx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80008; +} + +static void +Opcode_ivp_muluuanx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07009; +} + +static void +Opcode_ivp_muluuanx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000c; +} + +static void +Opcode_ivp_muluuanx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000c; +} + +static void +Opcode_ivp_muluuanx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650006; +} + +static void +Opcode_ivp_mulusnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260002; +} + +static void +Opcode_ivp_mulusnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000e; +} + +static void +Opcode_ivp_mulusnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06808; +} + +static void +Opcode_ivp_mulusnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180002; +} + +static void +Opcode_ivp_mulusnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130002; +} + +static void +Opcode_ivp_mulusnx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c00c; +} + +static void +Opcode_ivp_mulusanx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c00e; +} + +static void +Opcode_ivp_mulusanx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000a; +} + +static void +Opcode_ivp_mulusanx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07807; +} + +static void +Opcode_ivp_mulusanx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000e; +} + +static void +Opcode_ivp_mulusanx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000e; +} + +static void +Opcode_ivp_mulusanx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c008; +} + +static void +Opcode_ivp_mul2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258004; +} + +static void +Opcode_ivp_mul2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0000; +} + +static void +Opcode_ivp_mul2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07001; +} + +static void +Opcode_ivp_mul2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160004; +} + +static void +Opcode_ivp_mul2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110004; +} + +static void +Opcode_ivp_mul2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000e; +} + +static void +Opcode_ivp_mula2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258005; +} + +static void +Opcode_ivp_mula2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0001; +} + +static void +Opcode_ivp_mula2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07401; +} + +static void +Opcode_ivp_mula2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160005; +} + +static void +Opcode_ivp_mula2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110005; +} + +static void +Opcode_ivp_mula2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000f; +} + +static void +Opcode_ivp_addw2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250008; +} + +static void +Opcode_ivp_addw2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe90004; +} + +static void +Opcode_ivp_addw2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c00; +} + +static void +Opcode_ivp_addw2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140008; +} + +static void +Opcode_ivp_addw2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0008; +} + +static void +Opcode_ivp_addw2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640008; +} + +static void +Opcode_ivp_addwa2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250009; +} + +static void +Opcode_ivp_addwa2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe90005; +} + +static void +Opcode_ivp_addwa2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c01; +} + +static void +Opcode_ivp_addwa2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140009; +} + +static void +Opcode_ivp_addwa2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0009; +} + +static void +Opcode_ivp_addwa2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640009; +} + +static void +Opcode_ivp_addws2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000c; +} + +static void +Opcode_ivp_addws2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe90008; +} + +static void +Opcode_ivp_addws2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c04; +} + +static void +Opcode_ivp_addws2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000c; +} + +static void +Opcode_ivp_addws2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000c; +} + +static void +Opcode_ivp_addws2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000a; +} + +static void +Opcode_ivp_addwu2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000e; +} + +static void +Opcode_ivp_addwu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000a; +} + +static void +Opcode_ivp_addwu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c06; +} + +static void +Opcode_ivp_addwu2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000e; +} + +static void +Opcode_ivp_addwu2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000e; +} + +static void +Opcode_ivp_addwu2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000b; +} + +static void +Opcode_ivp_addwua2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000f; +} + +static void +Opcode_ivp_addwua2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000b; +} + +static void +Opcode_ivp_addwua2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c07; +} + +static void +Opcode_ivp_addwua2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000f; +} + +static void +Opcode_ivp_addwua2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000f; +} + +static void +Opcode_ivp_addwua2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000c; +} + +static void +Opcode_ivp_addwus2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258002; +} + +static void +Opcode_ivp_addwus2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000e; +} + +static void +Opcode_ivp_addwus2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07800; +} + +static void +Opcode_ivp_addwus2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160002; +} + +static void +Opcode_ivp_addwus2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110002; +} + +static void +Opcode_ivp_addwus2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000d; +} + +static void +Opcode_ivp_divn_2x32x16s_4step0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ivp_divn_2x32x16s_4step_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e40000; +} + +static void +Opcode_ivp_divn_2x32x16s_4stepn_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e48000; +} + +static void +Opcode_ivp_divn_2x32x16u_4step0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ivp_divn_2x32x16u_4step_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e50000; +} + +static void +Opcode_ivp_divn_2x32x16u_4stepn_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e58000; +} + +static void +Opcode_ivp_divnx16s_4step0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_divnx16s_4step_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e20000; +} + +static void +Opcode_ivp_divnx16s_4stepn_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e28000; +} + +static void +Opcode_ivp_divnx16u_4step0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ivp_divnx16u_4step_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e30000; +} + +static void +Opcode_ivp_divnx16u_4stepn_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e38000; +} + +static void +Opcode_ivp_divnx16sq_4step0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_divnx16q_4step0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_mulsnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25800f; +} + +static void +Opcode_ivp_mulsnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000b; +} + +static void +Opcode_ivp_mulsnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c03; +} + +static void +Opcode_ivp_mulsnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000f; +} + +static void +Opcode_ivp_mulsnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000f; +} + +static void +Opcode_ivp_mulsnx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648009; +} + +static void +Opcode_ivp_muluusnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264004; +} + +static void +Opcode_ivp_muluusnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90000; +} + +static void +Opcode_ivp_muluusnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0700a; +} + +static void +Opcode_ivp_muluusnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190004; +} + +static void +Opcode_ivp_muluusnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140004; +} + +static void +Opcode_ivp_muluusnx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65000e; +} + +static void +Opcode_ivp_mulussnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260006; +} + +static void +Opcode_ivp_mulussnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80002; +} + +static void +Opcode_ivp_mulussnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07808; +} + +static void +Opcode_ivp_mulussnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180006; +} + +static void +Opcode_ivp_mulussnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130006; +} + +static void +Opcode_ivp_mulussnx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650000; +} + +static void +Opcode_ivp_muln_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25800c; +} + +static void +Opcode_ivp_muln_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0008; +} + +static void +Opcode_ivp_muln_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07003; +} + +static void +Opcode_ivp_muln_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000c; +} + +static void +Opcode_ivp_muln_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000c; +} + +static void +Opcode_ivp_muln_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648006; +} + +static void +Opcode_ivp_muluun_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264001; +} + +static void +Opcode_ivp_muluun_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000d; +} + +static void +Opcode_ivp_muluun_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0640a; +} + +static void +Opcode_ivp_muluun_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190001; +} + +static void +Opcode_ivp_muluun_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140001; +} + +static void +Opcode_ivp_muluun_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65000b; +} + +static void +Opcode_ivp_mulusn_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260003; +} + +static void +Opcode_ivp_mulusn_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000f; +} + +static void +Opcode_ivp_mulusn_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c08; +} + +static void +Opcode_ivp_mulusn_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180003; +} + +static void +Opcode_ivp_mulusn_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130003; +} + +static void +Opcode_ivp_mulusn_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c00d; +} + +static void +Opcode_ivp_mulsun_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c006; +} + +static void +Opcode_ivp_mulsun_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0002; +} + +static void +Opcode_ivp_mulsun_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07805; +} + +static void +Opcode_ivp_mulsun_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170006; +} + +static void +Opcode_ivp_mulsun_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120006; +} + +static void +Opcode_ivp_mulsun_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c000; +} + +static void +Opcode_ivp_muln_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25800d; +} + +static void +Opcode_ivp_muln_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0009; +} + +static void +Opcode_ivp_muln_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07403; +} + +static void +Opcode_ivp_muln_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000d; +} + +static void +Opcode_ivp_muln_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000d; +} + +static void +Opcode_ivp_muln_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648007; +} + +static void +Opcode_ivp_muluun_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264002; +} + +static void +Opcode_ivp_muluun_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000e; +} + +static void +Opcode_ivp_muluun_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0680a; +} + +static void +Opcode_ivp_muluun_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190002; +} + +static void +Opcode_ivp_muluun_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140002; +} + +static void +Opcode_ivp_muluun_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65000c; +} + +static void +Opcode_ivp_mulusn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260004; +} + +static void +Opcode_ivp_mulusn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ivp_mulusn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07008; +} + +static void +Opcode_ivp_mulusn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180004; +} + +static void +Opcode_ivp_mulusn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130004; +} + +static void +Opcode_ivp_mulusn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c00e; +} + +static void +Opcode_ivp_mulsun_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c007; +} + +static void +Opcode_ivp_mulsun_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0003; +} + +static void +Opcode_ivp_mulsun_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c05; +} + +static void +Opcode_ivp_mulsun_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170007; +} + +static void +Opcode_ivp_mulsun_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120007; +} + +static void +Opcode_ivp_mulsun_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c001; +} + +static void +Opcode_ivp_mulhn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25800a; +} + +static void +Opcode_ivp_mulhn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0006; +} + +static void +Opcode_ivp_mulhn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07802; +} + +static void +Opcode_ivp_mulhn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000a; +} + +static void +Opcode_ivp_mulhn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000a; +} + +static void +Opcode_ivp_mulhn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648004; +} + +static void +Opcode_ivp_muluuhn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26000f; +} + +static void +Opcode_ivp_muluuhn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000b; +} + +static void +Opcode_ivp_muluuhn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c09; +} + +static void +Opcode_ivp_muluuhn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000f; +} + +static void +Opcode_ivp_muluuhn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000f; +} + +static void +Opcode_ivp_muluuhn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650009; +} + +static void +Opcode_ivp_mulushn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260001; +} + +static void +Opcode_ivp_mulushn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000d; +} + +static void +Opcode_ivp_mulushn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06408; +} + +static void +Opcode_ivp_mulushn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180001; +} + +static void +Opcode_ivp_mulushn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130001; +} + +static void +Opcode_ivp_mulushn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c00b; +} + +static void +Opcode_ivp_mulsuhn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c005; +} + +static void +Opcode_ivp_mulsuhn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0001; +} + +static void +Opcode_ivp_mulsuhn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07405; +} + +static void +Opcode_ivp_mulsuhn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170005; +} + +static void +Opcode_ivp_mulsuhn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120005; +} + +static void +Opcode_ivp_mulsuhn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64800f; +} + +static void +Opcode_ivp_mulan_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258008; +} + +static void +Opcode_ivp_mulan_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0004; +} + +static void +Opcode_ivp_mulan_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07002; +} + +static void +Opcode_ivp_mulan_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160008; +} + +static void +Opcode_ivp_mulan_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110008; +} + +static void +Opcode_ivp_mulan_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648002; +} + +static void +Opcode_ivp_muluuan_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26000d; +} + +static void +Opcode_ivp_muluuan_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80009; +} + +static void +Opcode_ivp_muluuan_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07409; +} + +static void +Opcode_ivp_muluuan_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000d; +} + +static void +Opcode_ivp_muluuan_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000d; +} + +static void +Opcode_ivp_muluuan_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650007; +} + +static void +Opcode_ivp_mulusan_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c00f; +} + +static void +Opcode_ivp_mulusan_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000b; +} + +static void +Opcode_ivp_mulusan_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c07; +} + +static void +Opcode_ivp_mulusan_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000f; +} + +static void +Opcode_ivp_mulusan_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000f; +} + +static void +Opcode_ivp_mulusan_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c009; +} + +static void +Opcode_ivp_mulsuan_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c003; +} + +static void +Opcode_ivp_mulsuan_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000f; +} + +static void +Opcode_ivp_mulsuan_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c04; +} + +static void +Opcode_ivp_mulsuan_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170003; +} + +static void +Opcode_ivp_mulsuan_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120003; +} + +static void +Opcode_ivp_mulsuan_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64800d; +} + +static void +Opcode_ivp_mulahn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258006; +} + +static void +Opcode_ivp_mulahn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0002; +} + +static void +Opcode_ivp_mulahn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07801; +} + +static void +Opcode_ivp_mulahn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160006; +} + +static void +Opcode_ivp_mulahn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110006; +} + +static void +Opcode_ivp_mulahn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648000; +} + +static void +Opcode_ivp_muluuahn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26000b; +} + +static void +Opcode_ivp_muluuahn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80007; +} + +static void +Opcode_ivp_muluuahn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c09; +} + +static void +Opcode_ivp_muluuahn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000b; +} + +static void +Opcode_ivp_muluuahn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000b; +} + +static void +Opcode_ivp_muluuahn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650005; +} + +static void +Opcode_ivp_mulusahn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c00d; +} + +static void +Opcode_ivp_mulusahn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0009; +} + +static void +Opcode_ivp_mulusahn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07407; +} + +static void +Opcode_ivp_mulusahn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000d; +} + +static void +Opcode_ivp_mulusahn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000d; +} + +static void +Opcode_ivp_mulusahn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c007; +} + +static void +Opcode_ivp_mulsuahn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c002; +} + +static void +Opcode_ivp_mulsuahn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000e; +} + +static void +Opcode_ivp_mulsuahn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07804; +} + +static void +Opcode_ivp_mulsuahn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170002; +} + +static void +Opcode_ivp_mulsuahn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120002; +} + +static void +Opcode_ivp_mulsuahn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64800c; +} + +static void +Opcode_ivp_mulan_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258009; +} + +static void +Opcode_ivp_mulan_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0005; +} + +static void +Opcode_ivp_mulan_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07402; +} + +static void +Opcode_ivp_mulan_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160009; +} + +static void +Opcode_ivp_mulan_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110009; +} + +static void +Opcode_ivp_mulan_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648003; +} + +static void +Opcode_ivp_muluuan_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26000e; +} + +static void +Opcode_ivp_muluuan_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000a; +} + +static void +Opcode_ivp_muluuan_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07809; +} + +static void +Opcode_ivp_muluuan_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000e; +} + +static void +Opcode_ivp_muluuan_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000e; +} + +static void +Opcode_ivp_muluuan_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650008; +} + +static void +Opcode_ivp_mulusan_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260000; +} + +static void +Opcode_ivp_mulusan_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000c; +} + +static void +Opcode_ivp_mulusan_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06008; +} + +static void +Opcode_ivp_mulusan_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_mulusan_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ivp_mulusan_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c00a; +} + +static void +Opcode_ivp_mulsuan_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c004; +} + +static void +Opcode_ivp_mulsuan_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0000; +} + +static void +Opcode_ivp_mulsuan_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07005; +} + +static void +Opcode_ivp_mulsuan_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170004; +} + +static void +Opcode_ivp_mulsuan_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120004; +} + +static void +Opcode_ivp_mulsuan_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64800e; +} + +static void +Opcode_ivp_mulshn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25800e; +} + +static void +Opcode_ivp_mulshn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000a; +} + +static void +Opcode_ivp_mulshn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07803; +} + +static void +Opcode_ivp_mulshn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000e; +} + +static void +Opcode_ivp_mulshn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000e; +} + +static void +Opcode_ivp_mulshn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648008; +} + +static void +Opcode_ivp_muluushn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264003; +} + +static void +Opcode_ivp_muluushn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000f; +} + +static void +Opcode_ivp_muluushn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c0a; +} + +static void +Opcode_ivp_muluushn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190003; +} + +static void +Opcode_ivp_muluushn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140003; +} + +static void +Opcode_ivp_muluushn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65000d; +} + +static void +Opcode_ivp_mulusshn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260005; +} + +static void +Opcode_ivp_mulusshn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80001; +} + +static void +Opcode_ivp_mulusshn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07408; +} + +static void +Opcode_ivp_mulusshn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180005; +} + +static void +Opcode_ivp_mulusshn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130005; +} + +static void +Opcode_ivp_mulusshn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c00f; +} + +static void +Opcode_ivp_mulsushn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c008; +} + +static void +Opcode_ivp_mulsushn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0004; +} + +static void +Opcode_ivp_mulsushn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07006; +} + +static void +Opcode_ivp_mulsushn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170008; +} + +static void +Opcode_ivp_mulsushn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120008; +} + +static void +Opcode_ivp_mulsushn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c002; +} + +static void +Opcode_ivp_mulsn_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c000; +} + +static void +Opcode_ivp_mulsn_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000c; +} + +static void +Opcode_ivp_mulsn_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07004; +} + +static void +Opcode_ivp_mulsn_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ivp_mulsn_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ivp_mulsn_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64800a; +} + +static void +Opcode_ivp_muluusn_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264005; +} + +static void +Opcode_ivp_muluusn_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90001; +} + +static void +Opcode_ivp_muluusn_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0740a; +} + +static void +Opcode_ivp_muluusn_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190005; +} + +static void +Opcode_ivp_muluusn_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140005; +} + +static void +Opcode_ivp_muluusn_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65000f; +} + +static void +Opcode_ivp_mulussn_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260007; +} + +static void +Opcode_ivp_mulussn_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80003; +} + +static void +Opcode_ivp_mulussn_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c08; +} + +static void +Opcode_ivp_mulussn_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180007; +} + +static void +Opcode_ivp_mulussn_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130007; +} + +static void +Opcode_ivp_mulussn_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650001; +} + +static void +Opcode_ivp_mulsusn_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c009; +} + +static void +Opcode_ivp_mulsusn_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0005; +} + +static void +Opcode_ivp_mulsusn_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07406; +} + +static void +Opcode_ivp_mulsusn_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170009; +} + +static void +Opcode_ivp_mulsusn_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120009; +} + +static void +Opcode_ivp_mulsusn_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c003; +} + +static void +Opcode_ivp_mulsn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c001; +} + +static void +Opcode_ivp_mulsn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000d; +} + +static void +Opcode_ivp_mulsn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07404; +} + +static void +Opcode_ivp_mulsn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170001; +} + +static void +Opcode_ivp_mulsn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120001; +} + +static void +Opcode_ivp_mulsn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64800b; +} + +static void +Opcode_ivp_muluusn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264006; +} + +static void +Opcode_ivp_muluusn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90002; +} + +static void +Opcode_ivp_muluusn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0780a; +} + +static void +Opcode_ivp_muluusn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190006; +} + +static void +Opcode_ivp_muluusn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140006; +} + +static void +Opcode_ivp_muluusn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x654000; +} + +static void +Opcode_ivp_mulussn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260008; +} + +static void +Opcode_ivp_mulussn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80004; +} + +static void +Opcode_ivp_mulussn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06009; +} + +static void +Opcode_ivp_mulussn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180008; +} + +static void +Opcode_ivp_mulussn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130008; +} + +static void +Opcode_ivp_mulussn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650002; +} + +static void +Opcode_ivp_mulsusn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c00a; +} + +static void +Opcode_ivp_mulsusn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0006; +} + +static void +Opcode_ivp_mulsusn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07806; +} + +static void +Opcode_ivp_mulsusn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000a; +} + +static void +Opcode_ivp_mulsusn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000a; +} + +static void +Opcode_ivp_mulsusn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c004; +} + +static void +Opcode_ivp_packln_2x96_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a0d8; +} + +static void +Opcode_ivp_packln_2x96_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e058; +} + +static void +Opcode_ivp_packln_2x96_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28207c; +} + +static void +Opcode_ivp_packln_2x96_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980fc; +} + +static void +Opcode_ivp_packln_2x96_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b20ac; +} + +static void +Opcode_ivp_packln_2x96_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc0a4; +} + +static void +Opcode_ivp_packhn_2x64w_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1720d8; +} + +static void +Opcode_ivp_packhn_2x64w_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x266058; +} + +static void +Opcode_ivp_packhn_2x64w_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28203c; +} + +static void +Opcode_ivp_packhn_2x64w_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980f4; +} + +static void +Opcode_ivp_packhn_2x64w_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00ac; +} + +static void +Opcode_ivp_packhn_2x64w_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca0a4; +} + +static void +Opcode_ivp_packvrn_2x64w_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f6004; +} + +static void +Opcode_ivp_packvrn_2x64w_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c00c; +} + +static void +Opcode_ivp_packvrn_2x64w_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c00c; +} + +static void +Opcode_ivp_packvrn_2x64w_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6004; +} + +static void +Opcode_ivp_packvrn_2x64w_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6004; +} + +static void +Opcode_ivp_packvrn_2x64w_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4004; +} + +static void +Opcode_ivp_packvrnrn_2x64w_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6004; +} + +static void +Opcode_ivp_packvrnrn_2x64w_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25800c; +} + +static void +Opcode_ivp_packvrnrn_2x64w_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25800c; +} + +static void +Opcode_ivp_packvrnrn_2x64w_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4004; +} + +static void +Opcode_ivp_packvrnrn_2x64w_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4004; +} + +static void +Opcode_ivp_packvrnrn_2x64w_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c2004; +} + +static void +Opcode_ivp_packvrnx48_0_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e600c; +} + +static void +Opcode_ivp_packvrnx48_0_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a00c; +} + +static void +Opcode_ivp_packvrnx48_0_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a00c; +} + +static void +Opcode_ivp_packvrnx48_0_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a400c; +} + +static void +Opcode_ivp_packvrnx48_0_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a400c; +} + +static void +Opcode_ivp_packvrnx48_0_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c200c; +} + +static void +Opcode_ivp_packvrnx48_1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f6000; +} + +static void +Opcode_ivp_packvrnx48_1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c008; +} + +static void +Opcode_ivp_packvrnx48_1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c008; +} + +static void +Opcode_ivp_packvrnx48_1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6000; +} + +static void +Opcode_ivp_packvrnx48_1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6000; +} + +static void +Opcode_ivp_packvrnx48_1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4000; +} + +static void +Opcode_ivp_packvrnrnx48_0_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d600c; +} + +static void +Opcode_ivp_packvrnrnx48_0_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e004; +} + +static void +Opcode_ivp_packvrnrnx48_0_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e004; +} + +static void +Opcode_ivp_packvrnrnx48_0_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a200c; +} + +static void +Opcode_ivp_packvrnrnx48_0_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a200c; +} + +static void +Opcode_ivp_packvrnrnx48_0_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000c; +} + +static void +Opcode_ivp_packvrnrnx48_1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6000; +} + +static void +Opcode_ivp_packvrnrnx48_1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258008; +} + +static void +Opcode_ivp_packvrnrnx48_1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258008; +} + +static void +Opcode_ivp_packvrnrnx48_1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4000; +} + +static void +Opcode_ivp_packvrnrnx48_1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4000; +} + +static void +Opcode_ivp_packvrnrnx48_1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c2000; +} + +static void +Opcode_ivp_packvrnrnx48_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6008; +} + +static void +Opcode_ivp_packvrnrnx48_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e000; +} + +static void +Opcode_ivp_packvrnrnx48_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e000; +} + +static void +Opcode_ivp_packvrnrnx48_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2008; +} + +static void +Opcode_ivp_packvrnrnx48_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2008; +} + +static void +Opcode_ivp_packvrnrnx48_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0008; +} + +static void +Opcode_ivp_packvrnr2nx24_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c600c; +} + +static void +Opcode_ivp_packvrnr2nx24_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a004; +} + +static void +Opcode_ivp_packvrnr2nx24_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a004; +} + +static void +Opcode_ivp_packvrnr2nx24_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000c; +} + +static void +Opcode_ivp_packvrnr2nx24_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000c; +} + +static void +Opcode_ivp_packvrnr2nx24_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b600c; +} + +static void +Opcode_ivp_l2a4nx8_ip_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000; +} + +static void +Opcode_ivp_l2au2nx8_ip_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ivp_l2u2nx8_xp_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ivp_avgu2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_avgu2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b0000; +} + +static void +Opcode_ivp_avgu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb0000; +} + +static void +Opcode_ivp_avgu2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900308; +} + +static void +Opcode_ivp_avgu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900008; +} + +static void +Opcode_ivp_avgu2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0010c; +} + +static void +Opcode_ivp_avgu2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9380004; +} + +static void +Opcode_ivp_avgu2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e007c00; +} + +static void +Opcode_ivp_avgu2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb90000; +} + +static void +Opcode_ivp_avgu2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c002a0; +} + +static void +Opcode_ivp_avgru2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_avgru2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a0000; +} + +static void +Opcode_ivp_avgru2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca0000; +} + +static void +Opcode_ivp_avgru2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900304; +} + +static void +Opcode_ivp_avgru2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00007; +} + +static void +Opcode_ivp_avgru2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0010c; +} + +static void +Opcode_ivp_avgru2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9380002; +} + +static void +Opcode_ivp_avgru2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e007800; +} + +static void +Opcode_ivp_avgru2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb80000; +} + +static void +Opcode_ivp_avgru2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a002a0; +} + +static void +Opcode_ivp_radd2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f800c71; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_radd2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3700074; +} + +static void +Opcode_ivp_radd2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f00374; +} + +static void +Opcode_ivp_radd2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f82600; +} + +static void +Opcode_ivp_radd2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607840; +} + +static void +Opcode_ivp_radd2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd800f0; +} + +static void +Opcode_ivp_radd2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b001b7; +} + +static void +Opcode_ivp_radd2nx8t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800c80; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_radd2nx8t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000041; +} + +static void +Opcode_ivp_radd2nx8t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800341; +} + +static void +Opcode_ivp_radd2nx8t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01000; +} + +static void +Opcode_ivp_radd2nx8t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e304020; +} + +static void +Opcode_ivp_radd2nx8t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ivp_radd2nx8t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001f3; +} + +static void +Opcode_ivp_raddunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502420; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100045; +} + +static void +Opcode_ivp_raddunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900345; +} + +static void +Opcode_ivp_raddunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c82800; +} + +static void +Opcode_ivp_raddunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607c50; +} + +static void +Opcode_ivp_raddunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda80f0; +} + +static void +Opcode_ivp_raddunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e001b6; +} + +static void +Opcode_ivp_raddunx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800cd0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddunx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000052; +} + +static void +Opcode_ivp_raddunx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800352; +} + +static void +Opcode_ivp_raddunx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01a00; +} + +static void +Opcode_ivp_raddunx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607020; +} + +static void +Opcode_ivp_raddunx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80050; +} + +static void +Opcode_ivp_raddunx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800194; +} + +static void +Opcode_ivp_raddu2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502031; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddu2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000075; +} + +static void +Opcode_ivp_raddu2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800375; +} + +static void +Opcode_ivp_raddu2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c02e00; +} + +static void +Opcode_ivp_raddu2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607c40; +} + +static void +Opcode_ivp_raddu2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda00f0; +} + +static void +Opcode_ivp_raddu2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d001b7; +} + +static void +Opcode_ivp_raddu2nx8t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800cc0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddu2nx8t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000042; +} + +static void +Opcode_ivp_raddu2nx8t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800342; +} + +static void +Opcode_ivp_raddu2nx8t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01800; +} + +static void +Opcode_ivp_raddu2nx8t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607000; +} + +static void +Opcode_ivp_raddu2nx8t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80040; +} + +static void +Opcode_ivp_raddu2nx8t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800187; +} + +static void +Opcode_ivp_ltrs2n_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1703e0; +} + +static void +Opcode_ivp_ltrs2n_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260960; +} + +static void +Opcode_ivp_ltrs2n_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260920; +} + +static void +Opcode_ivp_ltrs2n_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2500; +} + +static void +Opcode_ivp_ltrs2n_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae900; +} + +static void +Opcode_ivp_ltrs2n_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0210; +} + +static void +Opcode_ivp_ltrs2n_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be500; +} + +static void +Opcode_ivp_ltrsn_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1704e0; +} + +static void +Opcode_ivp_ltrsn_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260a60; +} + +static void +Opcode_ivp_ltrsn_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260a20; +} + +static void +Opcode_ivp_ltrsn_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2600; +} + +static void +Opcode_ivp_ltrsn_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aea00; +} + +static void +Opcode_ivp_ltrsn_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0310; +} + +static void +Opcode_ivp_ltrsn_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc510; +} + +static void +Opcode_ivp_ltrsn_2_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1705e0; +} + +static void +Opcode_ivp_ltrsn_2_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260b60; +} + +static void +Opcode_ivp_ltrsn_2_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260b20; +} + +static void +Opcode_ivp_ltrsn_2_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2700; +} + +static void +Opcode_ivp_ltrsn_2_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aeb00; +} + +static void +Opcode_ivp_ltrsn_2_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0310; +} + +static void +Opcode_ivp_ltrsn_2_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be510; +} + +static void +Opcode_ivp_seq2nx8_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1760dd; +} + +static void +Opcode_ivp_seq2nx8_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a05d; +} + +static void +Opcode_ivp_seq2nx8_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2820dd; +} + +static void +Opcode_ivp_seq2nx8_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a0f9; +} + +static void +Opcode_ivp_seq2nx8_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b60a4; +} + +static void +Opcode_ivp_seq2nx8_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce0ac; +} + +static void +Opcode_ivp_seqn_2x32_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1760df; +} + +static void +Opcode_ivp_seqn_2x32_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a05f; +} + +static void +Opcode_ivp_seqn_2x32_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2820df; +} + +static void +Opcode_ivp_seqn_2x32_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a0fb; +} + +static void +Opcode_ivp_seqn_2x32_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b60a6; +} + +static void +Opcode_ivp_seqn_2x32_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce0ae; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10980200; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a440000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1444000; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28f030c; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x594000; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28f020c; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa80200; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9808008; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00e000; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf8001; +} + +static void +Opcode_ivp_extrn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3880000; +} + +static void +Opcode_ivp_unpku2nx8_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf500c0; +} + +static void +Opcode_ivp_unpku2nx8_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f68002; +} + +static void +Opcode_ivp_unpku2nx8_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf580c0; +} + +static void +Opcode_ivp_unpku2nx8_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f68012; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800000; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00008; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800300; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8600000; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c202000; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_baddnormnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800300; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d00c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280010a; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000010; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000a; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9280000; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c403000; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840000; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800020; +} + +static void +Opcode_ivp_raddsnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502021; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddsnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000065; +} + +static void +Opcode_ivp_raddsnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800365; +} + +static void +Opcode_ivp_raddsnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c02c00; +} + +static void +Opcode_ivp_raddsnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607870; +} + +static void +Opcode_ivp_raddsnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd980f0; +} + +static void +Opcode_ivp_raddsnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d001b6; +} + +static void +Opcode_ivp_raddsnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800cb0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddsnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000071; +} + +static void +Opcode_ivp_raddsnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800371; +} + +static void +Opcode_ivp_raddsnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01600; +} + +static void +Opcode_ivp_raddsnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e305820; +} + +static void +Opcode_ivp_raddsnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80030; +} + +static void +Opcode_ivp_raddsnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800186; +} + +static void +Opcode_ivp_ornotb_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700c8; +} + +static void +Opcode_ivp_ornotb_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260050; +} + +static void +Opcode_ivp_ornotb_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260010; +} + +static void +Opcode_ivp_ornotb_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8018; +} + +static void +Opcode_ivp_ornotb_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab810; +} + +static void +Opcode_ivp_ornotb_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6018; +} + +static void +Opcode_ivp_extr2nx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10900000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extr2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extr2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ivp_extr2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a0300; +} + +static void +Opcode_ivp_extr2nx8_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x538000; +} + +static void +Opcode_ivp_extr2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a0200; +} + +static void +Opcode_ivp_extr2nx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ivp_extr2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9804000; +} + +static void +Opcode_ivp_extr2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c404000; +} + +static void +Opcode_ivp_extr2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf0000; +} + +static void +Opcode_ivp_extr2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800000; +} + +static void +Opcode_ivp_extrvrn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a448000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extrvrn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3030200; +} + +static void +Opcode_ivp_extrvrn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1950200; +} + +static void +Opcode_ivp_extrvrn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9802000; +} + +static void +Opcode_ivp_extrvrn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c10e000; +} + +static void +Opcode_ivp_extrvrn_2x32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104000; +} + +static void +Opcode_ivp_extrvrn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd28000; +} + +static void +Opcode_ivp_extrvrn_2x32_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x644000; +} + +static void +Opcode_ivp_movav8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d7c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movav8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a450005; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movav8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1459a00; +} + +static void +Opcode_ivp_movav8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3038205; +} + +static void +Opcode_ivp_movav8_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54600e; +} + +static void +Opcode_ivp_movav8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2af820d; +} + +static void +Opcode_ivp_movav8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9dda00; +} + +static void +Opcode_ivp_movav8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980e00a; +} + +static void +Opcode_ivp_movav8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c20e001; +} + +static void +Opcode_ivp_movav8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcfc005; +} + +static void +Opcode_ivp_movav8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a88010; +} + +static void +Opcode_ivp_mulpn16xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x214000; +} + +static void +Opcode_ivp_mulpn16xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb90000; +} + +static void +Opcode_ivp_mulpn16xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01400; +} + +static void +Opcode_ivp_mulpn16xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_ivp_mulpn16xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_ivp_mulpn16xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614000; +} + +static void +Opcode_ivp_mulpan16xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_ivp_mulpan16xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb80000; +} + +static void +Opcode_ivp_mulpan16xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01000; +} + +static void +Opcode_ivp_mulpan16xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_mulpan16xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_mulpan16xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_ivp_muluspn16xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22c000; +} + +static void +Opcode_ivp_muluspn16xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf0000; +} + +static void +Opcode_ivp_muluspn16xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c02c00; +} + +static void +Opcode_ivp_muluspn16xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_ivp_muluspn16xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_ivp_muluspn16xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62c000; +} + +static void +Opcode_ivp_muluspan16xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x228000; +} + +static void +Opcode_ivp_muluspan16xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe0000; +} + +static void +Opcode_ivp_muluspan16xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c02800; +} + +static void +Opcode_ivp_muluspan16xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ivp_muluspan16xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ivp_muluspan16xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x628000; +} + +static void +Opcode_ivp_mulp2n8xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x208000; +} + +static void +Opcode_ivp_mulp2n8xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb60000; +} + +static void +Opcode_ivp_mulp2n8xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00800; +} + +static void +Opcode_ivp_mulp2n8xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ivp_mulp2n8xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ivp_mulp2n8xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x608000; +} + +static void +Opcode_ivp_mulpa2n8xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c000; +} + +static void +Opcode_ivp_mulpa2n8xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb70000; +} + +static void +Opcode_ivp_mulpa2n8xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00c00; +} + +static void +Opcode_ivp_mulpa2n8xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_ivp_mulpa2n8xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_ivp_mulpa2n8xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60c000; +} + +static void +Opcode_ivp_mulusp2n8xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_ivp_mulusp2n8xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc0000; +} + +static void +Opcode_ivp_mulusp2n8xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c02000; +} + +static void +Opcode_ivp_mulusp2n8xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_mulusp2n8xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_mulusp2n8xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620000; +} + +static void +Opcode_ivp_muluspa2n8xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x224000; +} + +static void +Opcode_ivp_muluspa2n8xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd0000; +} + +static void +Opcode_ivp_muluspa2n8xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c02400; +} + +static void +Opcode_ivp_muluspa2n8xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_ivp_muluspa2n8xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_ivp_muluspa2n8xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x624000; +} + +static void +Opcode_ivp_mulpnx16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000003; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulpanx16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000002; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_muluspnx16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000007; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_muluspanx16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000006; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_muluupnx16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000b; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_muluupanx16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000a; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulp2nx8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulpa2nx8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000001; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulusp2nx8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000004; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_muluspa2nx8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000005; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_muluup2nx8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000008; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_muluupa2nx8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000009; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulpi2nr8x16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulpai2nr8x16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_muluspi2nr8x16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_muluspai2nr8x16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulq2n8xr8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulqa2n8xr8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulusq2n8xr8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulusqa2n8xr8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mul4t2n8xr8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_mul4t2n8xr8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb40000; +} + +static void +Opcode_ivp_mul4t2n8xr8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00000; +} + +static void +Opcode_ivp_mul4t2n8xr8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_mul4t2n8xr8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_mul4t2n8xr8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ivp_mul4ta2n8xr8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x204000; +} + +static void +Opcode_ivp_mul4ta2n8xr8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb50000; +} + +static void +Opcode_ivp_mul4ta2n8xr8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00400; +} + +static void +Opcode_ivp_mul4ta2n8xr8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ivp_mul4ta2n8xr8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ivp_mul4ta2n8xr8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x604000; +} + +static void +Opcode_ivp_mulus4t2n8xr8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x218000; +} + +static void +Opcode_ivp_mulus4t2n8xr8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba0000; +} + +static void +Opcode_ivp_mulus4t2n8xr8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01800; +} + +static void +Opcode_ivp_mulus4t2n8xr8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ivp_mulus4t2n8xr8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ivp_mulus4t2n8xr8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_ivp_mulus4ta2n8xr8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21c000; +} + +static void +Opcode_ivp_mulus4ta2n8xr8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb0000; +} + +static void +Opcode_ivp_mulus4ta2n8xr8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01c00; +} + +static void +Opcode_ivp_mulus4ta2n8xr8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_ivp_mulus4ta2n8xr8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_ivp_mulus4ta2n8xr8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_ivp_addwnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000b; +} + +static void +Opcode_ivp_addwnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe90007; +} + +static void +Opcode_ivp_addwnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c03; +} + +static void +Opcode_ivp_addwnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000b; +} + +static void +Opcode_ivp_addwnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000b; +} + +static void +Opcode_ivp_addwanx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000a; +} + +static void +Opcode_ivp_addwanx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe90006; +} + +static void +Opcode_ivp_addwanx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c02; +} + +static void +Opcode_ivp_addwanx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000a; +} + +static void +Opcode_ivp_addwanx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000a; +} + +static void +Opcode_ivp_addwsnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000d; +} + +static void +Opcode_ivp_addwsnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe90009; +} + +static void +Opcode_ivp_addwsnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c05; +} + +static void +Opcode_ivp_addwsnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000d; +} + +static void +Opcode_ivp_addwsnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000d; +} + +static void +Opcode_ivp_addwunx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258001; +} + +static void +Opcode_ivp_addwunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000d; +} + +static void +Opcode_ivp_addwunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07400; +} + +static void +Opcode_ivp_addwunx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160001; +} + +static void +Opcode_ivp_addwunx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110001; +} + +static void +Opcode_ivp_addwuanx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258000; +} + +static void +Opcode_ivp_addwuanx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000c; +} + +static void +Opcode_ivp_addwuanx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07000; +} + +static void +Opcode_ivp_addwuanx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ivp_addwuanx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ivp_addwusnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258003; +} + +static void +Opcode_ivp_addwusnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000f; +} + +static void +Opcode_ivp_addwusnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c00; +} + +static void +Opcode_ivp_addwusnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160003; +} + +static void +Opcode_ivp_addwusnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110003; +} + +static void +Opcode_ivp_subwnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26400a; +} + +static void +Opcode_ivp_subwnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90006; +} + +static void +Opcode_ivp_subwnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0680b; +} + +static void +Opcode_ivp_subwnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000a; +} + +static void +Opcode_ivp_subwnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000a; +} + +static void +Opcode_ivp_subwanx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264009; +} + +static void +Opcode_ivp_subwanx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90005; +} + +static void +Opcode_ivp_subwanx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0640b; +} + +static void +Opcode_ivp_subwanx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190009; +} + +static void +Opcode_ivp_subwanx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140009; +} + +static void +Opcode_ivp_subwunx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26400e; +} + +static void +Opcode_ivp_subwunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf9000a; +} + +static void +Opcode_ivp_subwunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0780b; +} + +static void +Opcode_ivp_subwunx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000e; +} + +static void +Opcode_ivp_subwunx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000e; +} + +static void +Opcode_ivp_subwuanx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26400d; +} + +static void +Opcode_ivp_subwuanx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90009; +} + +static void +Opcode_ivp_subwuanx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0740b; +} + +static void +Opcode_ivp_subwuanx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000d; +} + +static void +Opcode_ivp_subwuanx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000d; +} + +static void +Opcode_ivp_subw2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264007; +} + +static void +Opcode_ivp_subw2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90003; +} + +static void +Opcode_ivp_subw2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c0a; +} + +static void +Opcode_ivp_subw2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190007; +} + +static void +Opcode_ivp_subw2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140007; +} + +static void +Opcode_ivp_subwa2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264008; +} + +static void +Opcode_ivp_subwa2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90004; +} + +static void +Opcode_ivp_subwa2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0600b; +} + +static void +Opcode_ivp_subwa2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190008; +} + +static void +Opcode_ivp_subwa2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140008; +} + +static void +Opcode_ivp_subwu2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26400b; +} + +static void +Opcode_ivp_subwu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90007; +} + +static void +Opcode_ivp_subwu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c0b; +} + +static void +Opcode_ivp_subwu2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000b; +} + +static void +Opcode_ivp_subwu2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000b; +} + +static void +Opcode_ivp_subwua2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26400c; +} + +static void +Opcode_ivp_subwua2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90008; +} + +static void +Opcode_ivp_subwua2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0700b; +} + +static void +Opcode_ivp_subwua2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000c; +} + +static void +Opcode_ivp_subwua2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000c; +} + +static void +Opcode_ivp_randb2n_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1718d0; +} + +static void +Opcode_ivp_randb2n_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0052; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_randb2n_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261853; +} + +static void +Opcode_ivp_randb2n_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30001d0; +} + +static void +Opcode_ivp_randb2n_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261815; +} + +static void +Opcode_ivp_randb2n_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000d0; +} + +static void +Opcode_ivp_randb2n_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1812; +} + +static void +Opcode_ivp_randb2n_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98100d8; +} + +static void +Opcode_ivp_randb2n_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0418; +} + +static void +Opcode_ivp_randb2n_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd828e6; +} + +static void +Opcode_ivp_randb2n_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c7819; +} + +static void +Opcode_ivp_rorb2n_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1710d2; +} + +static void +Opcode_ivp_rorb2n_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0004; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rorb2n_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261856; +} + +static void +Opcode_ivp_rorb2n_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000101; +} + +static void +Opcode_ivp_rorb2n_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261020; +} + +static void +Opcode_ivp_rorb2n_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800001; +} + +static void +Opcode_ivp_rorb2n_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9818; +} + +static void +Opcode_ivp_rorb2n_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9810208; +} + +static void +Opcode_ivp_rorb2n_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0518; +} + +static void +Opcode_ivp_rorb2n_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd828ec; +} + +static void +Opcode_ivp_rorb2n_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c781c; +} + +static void +Opcode_ivp_randbn_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1710d1; +} + +static void +Opcode_ivp_randbn_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0062; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_randbn_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261854; +} + +static void +Opcode_ivp_randbn_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30001e0; +} + +static void +Opcode_ivp_randbn_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261816; +} + +static void +Opcode_ivp_randbn_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000e0; +} + +static void +Opcode_ivp_randbn_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1013; +} + +static void +Opcode_ivp_randbn_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98100e8; +} + +static void +Opcode_ivp_randbn_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0510; +} + +static void +Opcode_ivp_randbn_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd828e8; +} + +static void +Opcode_ivp_randbn_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c781a; +} + +static void +Opcode_ivp_rorbn_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1718d2; +} + +static void +Opcode_ivp_rorbn_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0006; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rorbn_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261857; +} + +static void +Opcode_ivp_rorbn_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000111; +} + +static void +Opcode_ivp_rorbn_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261820; +} + +static void +Opcode_ivp_rorbn_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800011; +} + +static void +Opcode_ivp_rorbn_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9819; +} + +static void +Opcode_ivp_rorbn_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9810218; +} + +static void +Opcode_ivp_rorbn_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0518; +} + +static void +Opcode_ivp_rorbn_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd828ee; +} + +static void +Opcode_ivp_rorbn_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c781d; +} + +static void +Opcode_ivp_randbn_2_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1718d1; +} + +static void +Opcode_ivp_randbn_2_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0072; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_randbn_2_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261855; +} + +static void +Opcode_ivp_randbn_2_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30001f0; +} + +static void +Opcode_ivp_randbn_2_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261817; +} + +static void +Opcode_ivp_randbn_2_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000f0; +} + +static void +Opcode_ivp_randbn_2_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1813; +} + +static void +Opcode_ivp_randbn_2_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98100f8; +} + +static void +Opcode_ivp_randbn_2_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0510; +} + +static void +Opcode_ivp_randbn_2_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd828ea; +} + +static void +Opcode_ivp_randbn_2_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c781b; +} + +static void +Opcode_ivp_rorbn_2_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1710d3; +} + +static void +Opcode_ivp_rorbn_2_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0014; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rorbn_2_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261060; +} + +static void +Opcode_ivp_rorbn_2_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000121; +} + +static void +Opcode_ivp_rorbn_2_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261021; +} + +static void +Opcode_ivp_rorbn_2_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800021; +} + +static void +Opcode_ivp_rorbn_2_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a981a; +} + +static void +Opcode_ivp_rorbn_2_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9810228; +} + +static void +Opcode_ivp_rorbn_2_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0610; +} + +static void +Opcode_ivp_rorbn_2_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd830e0; +} + +static void +Opcode_ivp_rorbn_2_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c781e; +} + +static void +Opcode_ivp_avgnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c402c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_avgnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1288000; +} + +static void +Opcode_ivp_avgnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc88000; +} + +static void +Opcode_ivp_avgnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0020a; +} + +static void +Opcode_ivp_avgnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00016; +} + +static void +Opcode_ivp_avgnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0010a; +} + +static void +Opcode_ivp_avgnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f8000b; +} + +static void +Opcode_ivp_avgnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d8000; +} + +static void +Opcode_ivp_avgnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb68000; +} + +static void +Opcode_ivp_avgnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d8000; +} + +static void +Opcode_ivp_avgnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f00280; +} + +static void +Opcode_ivp_avgunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_avgunx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b8000; +} + +static void +Opcode_ivp_avgunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb8000; +} + +static void +Opcode_ivp_avgunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190030a; +} + +static void +Opcode_ivp_avgunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900018; +} + +static void +Opcode_ivp_avgunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0010c; +} + +static void +Opcode_ivp_avgunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9380005; +} + +static void +Opcode_ivp_avgunx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f8000; +} + +static void +Opcode_ivp_avgunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb98000; +} + +static void +Opcode_ivp_avgunx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f8000; +} + +static void +Opcode_ivp_avgunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d002a0; +} + +static void +Opcode_ivp_avg2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ivp_avg2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ivp_avg2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0020a; +} + +static void +Opcode_ivp_avg2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00006; +} + +static void +Opcode_ivp_avg2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0010a; +} + +static void +Opcode_ivp_avg2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f0000b; +} + +static void +Opcode_ivp_avg2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d0000; +} + +static void +Opcode_ivp_avg2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb60000; +} + +static void +Opcode_ivp_avg2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0000; +} + +static void +Opcode_ivp_avg2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e00280; +} + +static void +Opcode_ivp_avgr2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1290000; +} + +static void +Opcode_ivp_avgr2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90000; +} + +static void +Opcode_ivp_avgr2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900300; +} + +static void +Opcode_ivp_avgr2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00007; +} + +static void +Opcode_ivp_avgr2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280010c; +} + +static void +Opcode_ivp_avgr2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9380000; +} + +static void +Opcode_ivp_avgr2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e0000; +} + +static void +Opcode_ivp_avgr2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb70000; +} + +static void +Opcode_ivp_avgr2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0000; +} + +static void +Opcode_ivp_avgr2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28002a0; +} + +static void +Opcode_ivp_avgrnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e402c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_avgrnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1298000; +} + +static void +Opcode_ivp_avgrnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc98000; +} + +static void +Opcode_ivp_avgrnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900302; +} + +static void +Opcode_ivp_avgrnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00017; +} + +static void +Opcode_ivp_avgrnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290010c; +} + +static void +Opcode_ivp_avgrnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9380001; +} + +static void +Opcode_ivp_avgrnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e8000; +} + +static void +Opcode_ivp_avgrnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb78000; +} + +static void +Opcode_ivp_avgrnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e8000; +} + +static void +Opcode_ivp_avgrnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29002a0; +} + +static void +Opcode_ivp_avgrunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_avgrunx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a8000; +} + +static void +Opcode_ivp_avgrunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca8000; +} + +static void +Opcode_ivp_avgrunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900306; +} + +static void +Opcode_ivp_avgrunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00017; +} + +static void +Opcode_ivp_avgrunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0010c; +} + +static void +Opcode_ivp_avgrunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9380003; +} + +static void +Opcode_ivp_avgrunx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f0000; +} + +static void +Opcode_ivp_avgrunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb88000; +} + +static void +Opcode_ivp_avgrunx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0000; +} + +static void +Opcode_ivp_avgrunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b002a0; +} + +static void +Opcode_ivp_gatheranx8u_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d3800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_gatheranx8u_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1449200; +} + +static void +Opcode_ivp_gatheranx8u_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54200c; +} + +static void +Opcode_ivp_gatheranx8u_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d3800; +} + +static void +Opcode_ivp_gatheranx8u_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b200c; +} + +static void +Opcode_ivp_gatheranx8u_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f2800; +} + +static void +Opcode_ivp_gatheranx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d1800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_gatheranx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1441200; +} + +static void +Opcode_ivp_gatheranx16_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54000c; +} + +static void +Opcode_ivp_gatheranx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d1800; +} + +static void +Opcode_ivp_gatheranx16_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b000c; +} + +static void +Opcode_ivp_gatheranx16_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f0800; +} + +static void +Opcode_ivp_gatheran_2x32_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d5800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_gatheran_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1451200; +} + +static void +Opcode_ivp_gatheran_2x32_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54400c; +} + +static void +Opcode_ivp_gatheran_2x32_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d5800; +} + +static void +Opcode_ivp_gatheran_2x32_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b400c; +} + +static void +Opcode_ivp_gatheran_2x32_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f4800; +} + +static void +Opcode_ivp_gatheranx8ut_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d0800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_gatheranx8ut_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1401200; +} + +static void +Opcode_ivp_gatheranx8ut_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540004; +} + +static void +Opcode_ivp_gatheranx8ut_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d0800; +} + +static void +Opcode_ivp_gatheranx8ut_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0004; +} + +static void +Opcode_ivp_gatheranx8ut_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980800; +} + +static void +Opcode_ivp_gatheranx16t_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_gatheranx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1401000; +} + +static void +Opcode_ivp_gatheranx16t_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ivp_gatheranx16t_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d0000; +} + +static void +Opcode_ivp_gatheranx16t_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0000; +} + +static void +Opcode_ivp_gatheranx16t_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980000; +} + +static void +Opcode_ivp_gatheran_2x32t_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d1000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_gatheran_2x32t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1441000; +} + +static void +Opcode_ivp_gatheran_2x32t_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540008; +} + +static void +Opcode_ivp_gatheran_2x32t_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d1000; +} + +static void +Opcode_ivp_gatheran_2x32t_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0008; +} + +static void +Opcode_ivp_gatheran_2x32t_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x982000; +} + +static void +Opcode_ivp_gatherdnx16_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1720dc; +} + +static void +Opcode_ivp_gatherdnx16_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26605c; +} + +static void +Opcode_ivp_gatherdnx16_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2820bc; +} + +static void +Opcode_ivp_gatherdnx16_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a0f4; +} + +static void +Opcode_ivp_gatherdnx16_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b40ac; +} + +static void +Opcode_ivp_gatherdnx16_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce0a4; +} + +static void +Opcode_ivp_gatherdnx8s_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1740dc; +} + +static void +Opcode_ivp_gatherdnx8s_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26805c; +} + +static void +Opcode_ivp_gatherdnx8s_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2820cc; +} + +static void +Opcode_ivp_gatherdnx8s_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a0d8; +} + +static void +Opcode_ivp_gatherdnx8s_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b60a0; +} + +static void +Opcode_ivp_gatherdnx8s_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce0a8; +} + +static void +Opcode_ivp_gatherd2nx8_l_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700dc; +} + +static void +Opcode_ivp_gatherd2nx8_l_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26405c; +} + +static void +Opcode_ivp_gatherd2nx8_l_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2820ac; +} + +static void +Opcode_ivp_gatherd2nx8_l_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a0d4; +} + +static void +Opcode_ivp_gatherd2nx8_l_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b40a8; +} + +static void +Opcode_ivp_gatherd2nx8_l_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce0a0; +} + +static void +Opcode_ivp_gatherd2nx8_h_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e0d8; +} + +static void +Opcode_ivp_gatherd2nx8_h_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26205c; +} + +static void +Opcode_ivp_gatherd2nx8_h_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28209c; +} + +static void +Opcode_ivp_gatherd2nx8_h_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a0f0; +} + +static void +Opcode_ivp_gatherd2nx8_h_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b40a4; +} + +static void +Opcode_ivp_gatherd2nx8_h_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc0ac; +} + +static void +Opcode_ivp_movgatherd_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a36050; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movgatherd_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11130d0; +} + +static void +Opcode_ivp_movgatherd_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54a00c; +} + +static void +Opcode_ivp_movgatherd_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0a050; +} + +static void +Opcode_ivp_movgatherd_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220f0; +} + +static void +Opcode_ivp_movgatherd_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f30f0; +} + +static void +Opcode_ivp_scatternx8u_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xddc000; +} + +static void +Opcode_ivp_scatternx8u_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x964000; +} + +static void +Opcode_ivp_scatter2nx8_l_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdcc000; +} + +static void +Opcode_ivp_scatter2nx8_l_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x95c000; +} + +static void +Opcode_ivp_scatter2nx8_h_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc4000; +} + +static void +Opcode_ivp_scatter2nx8_h_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x958000; +} + +static void +Opcode_ivp_scatternx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd4000; +} + +static void +Opcode_ivp_scatternx16_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x960000; +} + +static void +Opcode_ivp_scattern_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde4000; +} + +static void +Opcode_ivp_scattern_2x32_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x968000; +} + +static void +Opcode_ivp_scatternx8ut_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd84000; +} + +static void +Opcode_ivp_scatternx8ut_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ivp_scatter2nx8t_l_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd44000; +} + +static void +Opcode_ivp_scatter2nx8t_l_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ivp_scatter2nx8t_h_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ivp_scatter2nx8t_h_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e0000; +} + +static void +Opcode_ivp_scatternx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ivp_scatternx16t_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620000; +} + +static void +Opcode_ivp_scattern_2x32t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ivp_scattern_2x32t_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660000; +} + +static void +Opcode_ivp_scatterw_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a202f5; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_scatterw_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500655; +} + +static void +Opcode_ivp_scatterw_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600335; +} + +static void +Opcode_ivp_scatterw_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x831ad1; +} + +static void +Opcode_ivp_scatterw_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f1475; +} + +static void +Opcode_ivp_scatterw_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x850325; +} + +static void +Opcode_ivp_scatterw_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f92f1; +} + +static void +Opcode_ivp_counteqz4nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300200; +} + +static void +Opcode_ivp_counteqz4nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8480000; +} + +static void +Opcode_ivp_counteqz4nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000000; +} + +static void +Opcode_ivp_counteq4nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300000; +} + +static void +Opcode_ivp_counteq4nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8400000; +} + +static void +Opcode_ivp_counteq4nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000000; +} + +static void +Opcode_ivp_counteqmz4nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ivp_counteqmz4nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000000; +} + +static void +Opcode_ivp_counteqm4nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_counteqm4nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; +} + +static void +Opcode_ivp_countlez4nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500000; +} + +static void +Opcode_ivp_countlez4nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8580000; +} + +static void +Opcode_ivp_countlez4nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e100000; +} + +static void +Opcode_ivp_countle4nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400000; +} + +static void +Opcode_ivp_countle4nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8500000; +} + +static void +Opcode_ivp_countle4nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c100000; +} + +static void +Opcode_ivp_countlemz4nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; +} + +static void +Opcode_ivp_countlemz4nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000000; +} + +static void +Opcode_ivp_countlem4nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; +} + +static void +Opcode_ivp_countlem4nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; +} + +static void +Opcode_ivp_lsr2nx8_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10878000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsr2nx8_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f8000; +} + +static void +Opcode_ivp_lsr2nx8_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4000; +} + +static void +Opcode_ivp_lsr2nx8_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4000; +} + +static void +Opcode_ivp_lsr2nx8_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x978000; +} + +static void +Opcode_ivp_lsr2nx8_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10560000; +} + +static void +Opcode_ivp_lsr2nx8_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10982000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsr2nx8_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b2000; +} + +static void +Opcode_ivp_lsr2nx8_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x228000; +} + +static void +Opcode_ivp_lsr2nx8_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x228000; +} + +static void +Opcode_ivp_lsr2nx8_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa82000; +} + +static void +Opcode_ivp_lsr2nx8_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b8000; +} + +static void +Opcode_ivp_lsr2nx8_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108ec000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsr2nx8_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1422000; +} + +static void +Opcode_ivp_lsr2nx8_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fe000; +} + +static void +Opcode_ivp_lsr2nx8_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fc000; +} + +static void +Opcode_ivp_lsr2nx8_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ec000; +} + +static void +Opcode_ivp_lsr2nx8_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058c000; +} + +static void +Opcode_ivp_lsr2nx8_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108ee000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsr2nx8_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142a000; +} + +static void +Opcode_ivp_lsr2nx8_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_lsr2nx8_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fe000; +} + +static void +Opcode_ivp_lsr2nx8_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ee000; +} + +static void +Opcode_ivp_lsr2nx8_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058e000; +} + +static void +Opcode_ivp_lsrnx16_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10880000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsrnx16_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ivp_lsrnx16_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6000; +} + +static void +Opcode_ivp_lsrnx16_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6000; +} + +static void +Opcode_ivp_lsrnx16_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980000; +} + +static void +Opcode_ivp_lsrnx16_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10568000; +} + +static void +Opcode_ivp_lsrnx16_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10986000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsrnx16_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ba000; +} + +static void +Opcode_ivp_lsrnx16_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22a000; +} + +static void +Opcode_ivp_lsrnx16_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22a000; +} + +static void +Opcode_ivp_lsrnx16_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa86000; +} + +static void +Opcode_ivp_lsrnx16_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ba000; +} + +static void +Opcode_ivp_lsrnx16_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108f0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsrnx16_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1432000; +} + +static void +Opcode_ivp_lsrnx16_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x202000; +} + +static void +Opcode_ivp_lsrnx16_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_lsrnx16_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f0000; +} + +static void +Opcode_ivp_lsrnx16_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10590000; +} + +static void +Opcode_ivp_lsrnx16_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108f2000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsrnx16_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143a000; +} + +static void +Opcode_ivp_lsrnx16_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x204000; +} + +static void +Opcode_ivp_lsrnx16_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x202000; +} + +static void +Opcode_ivp_lsrnx16_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f2000; +} + +static void +Opcode_ivp_lsrnx16_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10592000; +} + +static void +Opcode_ivp_lsrn_2x32_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10888000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsrn_2x32_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1208000; +} + +static void +Opcode_ivp_lsrn_2x32_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_ivp_lsrn_2x32_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_ivp_lsrn_2x32_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x988000; +} + +static void +Opcode_ivp_lsrn_2x32_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10570000; +} + +static void +Opcode_ivp_lsrn_2x32_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1098a000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsrn_2x32_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1384000; +} + +static void +Opcode_ivp_lsrn_2x32_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22c000; +} + +static void +Opcode_ivp_lsrn_2x32_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22c000; +} + +static void +Opcode_ivp_lsrn_2x32_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8a000; +} + +static void +Opcode_ivp_lsrn_2x32_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105bc000; +} + +static void +Opcode_ivp_lsrn_2x32_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108f4000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsrn_2x32_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1442000; +} + +static void +Opcode_ivp_lsrn_2x32_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x206000; +} + +static void +Opcode_ivp_lsrn_2x32_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x204000; +} + +static void +Opcode_ivp_lsrn_2x32_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f4000; +} + +static void +Opcode_ivp_lsrn_2x32_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10594000; +} + +static void +Opcode_ivp_lsrn_2x32_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108f6000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsrn_2x32_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144a000; +} + +static void +Opcode_ivp_lsrn_2x32_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x208000; +} + +static void +Opcode_ivp_lsrn_2x32_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x206000; +} + +static void +Opcode_ivp_lsrn_2x32_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f6000; +} + +static void +Opcode_ivp_lsrn_2x32_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10596000; +} + +static void +Opcode_ivp_absnx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a30050; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_absnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27500d0a; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_absnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11180f0; +} + +static void +Opcode_ivp_absnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf58060; +} + +static void +Opcode_ivp_absnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330540e; +} + +static void +Opcode_ivp_absnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f60012; +} + +static void +Opcode_ivp_absnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f05608; +} + +static void +Opcode_ivp_absnx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82c0d0; +} + +static void +Opcode_ivp_absnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94800d9; +} + +static void +Opcode_ivp_absnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8060; +} + +static void +Opcode_ivp_absnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606d08; +} + +static void +Opcode_ivp_absnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20300; +} + +static void +Opcode_ivp_absnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8020; +} + +static void +Opcode_ivp_absnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2705540; +} + +static void +Opcode_ivp_abssnx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a30090; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_abssnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27500d0c; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_abssnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11080d0; +} + +static void +Opcode_ivp_abssnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf68060; +} + +static void +Opcode_ivp_abssnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330640e; +} + +static void +Opcode_ivp_abssnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f60014; +} + +static void +Opcode_ivp_abssnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f06608; +} + +static void +Opcode_ivp_abssnx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8300f0; +} + +static void +Opcode_ivp_abssnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9480199; +} + +static void +Opcode_ivp_abssnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a80a0; +} + +static void +Opcode_ivp_abssnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606f08; +} + +static void +Opcode_ivp_abssnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20302; +} + +static void +Opcode_ivp_abssnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8060; +} + +static void +Opcode_ivp_abssnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2706540; +} + +static void +Opcode_ivp_abssubnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c402400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_abssubnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_ivp_abssubnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ivp_abssubnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e00208; +} + +static void +Opcode_ivp_abssubnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00004; +} + +static void +Opcode_ivp_abssubnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e00108; +} + +static void +Opcode_ivp_abssubnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9300006; +} + +static void +Opcode_ivp_abssubnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_ivp_abssubnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c105c00; +} + +static void +Opcode_ivp_abssubnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb20000; +} + +static void +Opcode_ivp_abssubnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x390000; +} + +static void +Opcode_ivp_abssubnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e000e0; +} + +static void +Opcode_ivp_abssubunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38402800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_abssubunx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1250000; +} + +static void +Opcode_ivp_abssubunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc50000; +} + +static void +Opcode_ivp_abssubunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280020a; +} + +static void +Opcode_ivp_abssubunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00005; +} + +static void +Opcode_ivp_abssubunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280010a; +} + +static void +Opcode_ivp_abssubunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000b; +} + +static void +Opcode_ivp_abssubunx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0000; +} + +static void +Opcode_ivp_abssubunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e006000; +} + +static void +Opcode_ivp_abssubunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_ivp_abssubunx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0000; +} + +static void +Opcode_ivp_abssubunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800280; +} + +static void +Opcode_ivp_absssubnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38402400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_absssubnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1230000; +} + +static void +Opcode_ivp_absssubnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30000; +} + +static void +Opcode_ivp_absssubnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c00208; +} + +static void +Opcode_ivp_absssubnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00004; +} + +static void +Opcode_ivp_absssubnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c00108; +} + +static void +Opcode_ivp_absssubnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9300004; +} + +static void +Opcode_ivp_absssubnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ivp_absssubnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c105800; +} + +static void +Opcode_ivp_absssubnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_ivp_absssubnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ivp_absssubnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c000e0; +} + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01d; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134800; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614800; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34900; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134900; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614900; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf06d; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_l32i_n_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b3000; +} + +static void +Opcode_l32i_n_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80b000; +} + +static void +Opcode_l32i_n_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa42000; +} + +static void +Opcode_l32i_n_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae000; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_mov_n_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0100; + slotbuf[1] = 0; +} + +static void +Opcode_mov_n_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000500; +} + +static void +Opcode_mov_n_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800400; +} + +static void +Opcode_mov_n_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9882000; +} + +static void +Opcode_mov_n_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c40e000; +} + +static void +Opcode_mov_n_Slot_f5_s3_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_mov_n_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2a000; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03d; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00d; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_s32i_n_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf000; +} + +static void +Opcode_s32i_n_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x811000; +} + +static void +Opcode_s32i_n_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa50000; +} + +static void +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e70; +} + +static void +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e700; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addi_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10560000; + slotbuf[1] = 0; +} + +static void +Opcode_addi_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_addi_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_addi_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a400000; + slotbuf[1] = 0; +} + +static void +Opcode_addi_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_addi_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_addi_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_addi_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000200; +} + +static void +Opcode_addi_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360000; +} + +static void +Opcode_addi_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_addi_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c03000; +} + +static void +Opcode_addi_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900200; +} + +static void +Opcode_addi_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560000; +} + +static void +Opcode_addi_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_addi_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_addi_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9800000; +} + +static void +Opcode_addi_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10360000; +} + +static void +Opcode_addi_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_addi_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c006000; +} + +static void +Opcode_addi_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10160000; + slotbuf[1] = 0; +} + +static void +Opcode_addi_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_addi_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_addi_Slot_f5_s3_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_addi_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_addi_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_addi_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_addi_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_addi_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_addi_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300000; +} + +static void +Opcode_addi_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e0000; +} + +static void +Opcode_addi_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_addi_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_addi_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_addmi_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10570000; + slotbuf[1] = 0; +} + +static void +Opcode_addmi_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_addmi_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30000; +} + +static void +Opcode_addmi_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c000; +} + +static void +Opcode_addmi_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370000; +} + +static void +Opcode_addmi_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c000; +} + +static void +Opcode_addmi_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x570000; +} + +static void +Opcode_addmi_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_addmi_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10370000; +} + +static void +Opcode_addmi_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_addmi_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10170000; + slotbuf[1] = 0; +} + +static void +Opcode_addmi_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_addmi_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_addmi_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_addmi_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_addmi_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_addmi_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f0000; +} + +static void +Opcode_addmi_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690000; +} + +static void +Opcode_addmi_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_add_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109ce000; + slotbuf[1] = 0; +} + +static void +Opcode_add_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000; +} + +static void +Opcode_add_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d6000; +} + +static void +Opcode_add_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c8000; +} + +static void +Opcode_add_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23a000; +} + +static void +Opcode_add_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0000; +} + +static void +Opcode_add_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x596000; +} + +static void +Opcode_add_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23a000; +} + +static void +Opcode_add_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e81000; +} + +static void +Opcode_add_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xace000; +} + +static void +Opcode_add_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000; +} + +static void +Opcode_add_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x156000; +} + +static void +Opcode_add_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ca000; +} + +static void +Opcode_add_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000; +} + +static void +Opcode_add_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10204000; + slotbuf[1] = 0; +} + +static void +Opcode_add_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94000; +} + +static void +Opcode_add_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34000; +} + +static void +Opcode_add_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154000; +} + +static void +Opcode_add_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5000; +} + +static void +Opcode_add_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109000; +} + +static void +Opcode_add_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_add_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2310000; +} + +static void +Opcode_add_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x801000; +} + +static void +Opcode_add_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c4000; +} + +static void +Opcode_add_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3c000; +} + +static void +Opcode_add_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198000; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_sub_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a21000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d9000; +} + +static void +Opcode_sub_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d7000; +} + +static void +Opcode_sub_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1445000; +} + +static void +Opcode_sub_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24a000; +} + +static void +Opcode_sub_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa3000; +} + +static void +Opcode_sub_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b1000; +} + +static void +Opcode_sub_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24b000; +} + +static void +Opcode_sub_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e99000; +} + +static void +Opcode_sub_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xafa000; +} + +static void +Opcode_sub_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x189000; +} + +static void +Opcode_sub_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f000; +} + +static void +Opcode_sub_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e0000; +} + +static void +Opcode_sub_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x189000; +} + +static void +Opcode_sub_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1021a000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5000; +} + +static void +Opcode_sub_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46000; +} + +static void +Opcode_sub_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x165000; +} + +static void +Opcode_sub_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc000; +} + +static void +Opcode_sub_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107000; +} + +static void +Opcode_sub_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4000; +} + +static void +Opcode_sub_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2316000; +} + +static void +Opcode_sub_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x818000; +} + +static void +Opcode_sub_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x659000; +} + +static void +Opcode_sub_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa51000; +} + +static void +Opcode_sub_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8000; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addx2_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109cf000; + slotbuf[1] = 0; +} + +static void +Opcode_addx2_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e2000; +} + +static void +Opcode_addx2_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d7000; +} + +static void +Opcode_addx2_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c9000; +} + +static void +Opcode_addx2_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23b000; +} + +static void +Opcode_addx2_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa4000; +} + +static void +Opcode_addx2_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x597000; +} + +static void +Opcode_addx2_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23b000; +} + +static void +Opcode_addx2_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f81000; +} + +static void +Opcode_addx2_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xacf000; +} + +static void +Opcode_addx2_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000; +} + +static void +Opcode_addx2_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x157000; +} + +static void +Opcode_addx2_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105cb000; +} + +static void +Opcode_addx2_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000; +} + +static void +Opcode_addx2_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10205000; + slotbuf[1] = 0; +} + +static void +Opcode_addx2_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x95000; +} + +static void +Opcode_addx2_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35000; +} + +static void +Opcode_addx2_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x155000; +} + +static void +Opcode_addx2_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7000; +} + +static void +Opcode_addx2_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d000; +} + +static void +Opcode_addx2_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2000; +} + +static void +Opcode_addx2_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2311000; +} + +static void +Opcode_addx2_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x803000; +} + +static void +Opcode_addx2_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c5000; +} + +static void +Opcode_addx2_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3e000; +} + +static void +Opcode_addx2_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x199000; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_addx4_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a14000; + slotbuf[1] = 0; +} + +static void +Opcode_addx4_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1000; +} + +static void +Opcode_addx4_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x354000; +} + +static void +Opcode_addx4_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d0000; +} + +static void +Opcode_addx4_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23c000; +} + +static void +Opcode_addx4_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa1000; +} + +static void +Opcode_addx4_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x598000; +} + +static void +Opcode_addx4_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23c000; +} + +static void +Opcode_addx4_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e89000; +} + +static void +Opcode_addx4_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad2000; +} + +static void +Opcode_addx4_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000; +} + +static void +Opcode_addx4_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_addx4_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105cc000; +} + +static void +Opcode_addx4_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000; +} + +static void +Opcode_addx4_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10206000; + slotbuf[1] = 0; +} + +static void +Opcode_addx4_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96000; +} + +static void +Opcode_addx4_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_addx4_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x156000; +} + +static void +Opcode_addx4_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000; +} + +static void +Opcode_addx4_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102000; +} + +static void +Opcode_addx4_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b4000; +} + +static void +Opcode_addx4_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2312000; +} + +static void +Opcode_addx4_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x805000; +} + +static void +Opcode_addx4_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c6000; +} + +static void +Opcode_addx4_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3d000; +} + +static void +Opcode_addx4_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a000; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_addx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a16000; + slotbuf[1] = 0; +} + +static void +Opcode_addx8_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9000; +} + +static void +Opcode_addx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d4000; +} + +static void +Opcode_addx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d1000; +} + +static void +Opcode_addx8_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23d000; +} + +static void +Opcode_addx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa5000; +} + +static void +Opcode_addx8_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59a000; +} + +static void +Opcode_addx8_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23d000; +} + +static void +Opcode_addx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f89000; +} + +static void +Opcode_addx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad3000; +} + +static void +Opcode_addx8_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000; +} + +static void +Opcode_addx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c000; +} + +static void +Opcode_addx8_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ce000; +} + +static void +Opcode_addx8_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000; +} + +static void +Opcode_addx8_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10207000; + slotbuf[1] = 0; +} + +static void +Opcode_addx8_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x97000; +} + +static void +Opcode_addx8_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37000; +} + +static void +Opcode_addx8_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x157000; +} + +static void +Opcode_addx8_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000; +} + +static void +Opcode_addx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106000; +} + +static void +Opcode_addx8_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6000; +} + +static void +Opcode_addx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2313000; +} + +static void +Opcode_addx8_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x807000; +} + +static void +Opcode_addx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c7000; +} + +static void +Opcode_addx8_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3f000; +} + +static void +Opcode_addx8_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19b000; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_subx2_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a23000; + slotbuf[1] = 0; +} + +static void +Opcode_subx2_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1da000; +} + +static void +Opcode_subx2_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x255000; +} + +static void +Opcode_subx2_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1447000; +} + +static void +Opcode_subx2_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24b000; +} + +static void +Opcode_subx2_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa7000; +} + +static void +Opcode_subx2_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b3000; +} + +static void +Opcode_subx2_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24c000; +} + +static void +Opcode_subx2_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f99000; +} + +static void +Opcode_subx2_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xafb000; +} + +static void +Opcode_subx2_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a000; +} + +static void +Opcode_subx2_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000; +} + +static void +Opcode_subx2_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e2000; +} + +static void +Opcode_subx2_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a000; +} + +static void +Opcode_subx2_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1021b000; + slotbuf[1] = 0; +} + +static void +Opcode_subx2_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6000; +} + +static void +Opcode_subx2_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47000; +} + +static void +Opcode_subx2_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x166000; +} + +static void +Opcode_subx2_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe000; +} + +static void +Opcode_subx2_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b000; +} + +static void +Opcode_subx2_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6000; +} + +static void +Opcode_subx2_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2317000; +} + +static void +Opcode_subx2_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81a000; +} + +static void +Opcode_subx2_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d9000; +} + +static void +Opcode_subx2_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa53000; +} + +static void +Opcode_subx2_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9000; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_subx4_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a25000; + slotbuf[1] = 0; +} + +static void +Opcode_subx4_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1db000; +} + +static void +Opcode_subx4_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d5000; +} + +static void +Opcode_subx4_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144d000; +} + +static void +Opcode_subx4_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24c000; +} + +static void +Opcode_subx4_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa8000; +} + +static void +Opcode_subx4_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b5000; +} + +static void +Opcode_subx4_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24d000; +} + +static void +Opcode_subx4_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea1000; +} + +static void +Opcode_subx4_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xafe000; +} + +static void +Opcode_subx4_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b000; +} + +static void +Opcode_subx4_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x155000; +} + +static void +Opcode_subx4_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e4000; +} + +static void +Opcode_subx4_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b000; +} + +static void +Opcode_subx4_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1021c000; + slotbuf[1] = 0; +} + +static void +Opcode_subx4_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7000; +} + +static void +Opcode_subx4_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000; +} + +static void +Opcode_subx4_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x167000; +} + +static void +Opcode_subx4_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb1000; +} + +static void +Opcode_subx4_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f000; +} + +static void +Opcode_subx4_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c1000; +} + +static void +Opcode_subx4_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2318000; +} + +static void +Opcode_subx4_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81c000; +} + +static void +Opcode_subx4_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x759000; +} + +static void +Opcode_subx4_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa55000; +} + +static void +Opcode_subx4_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa000; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_subx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a27000; + slotbuf[1] = 0; +} + +static void +Opcode_subx8_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c1000; +} + +static void +Opcode_subx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x355000; +} + +static void +Opcode_subx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144f000; +} + +static void +Opcode_subx8_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24d000; +} + +static void +Opcode_subx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfac000; +} + +static void +Opcode_subx8_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b7000; +} + +static void +Opcode_subx8_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24e000; +} + +static void +Opcode_subx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fa1000; +} + +static void +Opcode_subx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaff000; +} + +static void +Opcode_subx8_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c000; +} + +static void +Opcode_subx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000; +} + +static void +Opcode_subx8_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e6000; +} + +static void +Opcode_subx8_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c000; +} + +static void +Opcode_subx8_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1021d000; + slotbuf[1] = 0; +} + +static void +Opcode_subx8_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000; +} + +static void +Opcode_subx8_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x49000; +} + +static void +Opcode_subx8_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_subx8_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3000; +} + +static void +Opcode_subx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_subx8_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c3000; +} + +static void +Opcode_subx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2319000; +} + +static void +Opcode_subx8_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81e000; +} + +static void +Opcode_subx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d9000; +} + +static void +Opcode_subx8_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa57000; +} + +static void +Opcode_subx8_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab000; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_and_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a15000; + slotbuf[1] = 0; +} + +static void +Opcode_and_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e3000; +} + +static void +Opcode_and_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x356000; +} + +static void +Opcode_and_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d8000; +} + +static void +Opcode_and_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23e000; +} + +static void +Opcode_and_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa2000; +} + +static void +Opcode_and_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59c000; +} + +static void +Opcode_and_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23e000; +} + +static void +Opcode_and_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e91000; +} + +static void +Opcode_and_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad6000; +} + +static void +Opcode_and_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c000; +} + +static void +Opcode_and_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000; +} + +static void +Opcode_and_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105cd000; +} + +static void +Opcode_and_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c000; +} + +static void +Opcode_and_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10208000; + slotbuf[1] = 0; +} + +static void +Opcode_and_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98000; +} + +static void +Opcode_and_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_and_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_and_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000; +} + +static void +Opcode_and_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a000; +} + +static void +Opcode_and_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1000; +} + +static void +Opcode_and_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2314000; +} + +static void +Opcode_and_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x809000; +} + +static void +Opcode_and_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x744000; +} + +static void +Opcode_and_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa40000; +} + +static void +Opcode_and_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19c000; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_or_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a1c000; + slotbuf[1] = 0; +} + +static void +Opcode_or_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2000; +} + +static void +Opcode_or_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d6000; +} + +static void +Opcode_or_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f0000; +} + +static void +Opcode_or_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x247000; +} + +static void +Opcode_or_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa6000; +} + +static void +Opcode_or_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0000; +} + +static void +Opcode_or_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x248000; +} + +static void +Opcode_or_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f91000; +} + +static void +Opcode_or_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf2000; +} + +static void +Opcode_or_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x186000; +} + +static void +Opcode_or_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e000; +} + +static void +Opcode_or_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d9000; +} + +static void +Opcode_or_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x186000; +} + +static void +Opcode_or_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10216000; + slotbuf[1] = 0; +} + +static void +Opcode_or_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1000; +} + +static void +Opcode_or_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41000; +} + +static void +Opcode_or_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x161000; +} + +static void +Opcode_or_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6000; +} + +static void +Opcode_or_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e000; +} + +static void +Opcode_or_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bd000; +} + +static void +Opcode_or_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2315000; +} + +static void +Opcode_or_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x816000; +} + +static void +Opcode_or_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d8000; +} + +static void +Opcode_or_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4f000; +} + +static void +Opcode_or_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a5000; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_xor_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a29000; + slotbuf[1] = 0; +} + +static void +Opcode_xor_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_xor_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d5000; +} + +static void +Opcode_xor_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1455000; +} + +static void +Opcode_xor_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24e000; +} + +static void +Opcode_xor_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa9000; +} + +static void +Opcode_xor_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b8000; +} + +static void +Opcode_xor_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24f000; +} + +static void +Opcode_xor_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea9000; +} + +static void +Opcode_xor_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa01000; +} + +static void +Opcode_xor_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18d000; +} + +static void +Opcode_xor_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d000; +} + +static void +Opcode_xor_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e1000; +} + +static void +Opcode_xor_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18d000; +} + +static void +Opcode_xor_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1021e000; + slotbuf[1] = 0; +} + +static void +Opcode_xor_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9000; +} + +static void +Opcode_xor_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a000; +} + +static void +Opcode_xor_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x169000; +} + +static void +Opcode_xor_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb5000; +} + +static void +Opcode_xor_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x164000; +} + +static void +Opcode_xor_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c5000; +} + +static void +Opcode_xor_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x231a000; +} + +static void +Opcode_xor_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x819000; +} + +static void +Opcode_xor_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65a000; +} + +static void +Opcode_xor_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa58000; +} + +static void +Opcode_xor_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac000; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6007; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe007; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1007; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9007; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa007; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2007; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb007; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3007; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc007; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5007; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd007; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_const16_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4; +} + +static void +Opcode_const16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0; +} + +static void +Opcode_const16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_const16_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_const16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_const16_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; +} + +static void +Opcode_const16_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0; +} + +static void +Opcode_const16_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_const16_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_const16_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_extui_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10540000; + slotbuf[1] = 0; +} + +static void +Opcode_extui_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_extui_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_extui_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_extui_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_extui_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_extui_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_extui_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_extui_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340000; +} + +static void +Opcode_extui_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_extui_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10140000; + slotbuf[1] = 0; +} + +static void +Opcode_extui_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_extui_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_extui_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_extui_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_extui_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_extui_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_extui_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_j_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10380000; + slotbuf[1] = 0; +} + +static void +Opcode_j_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb40000; +} + +static void +Opcode_j_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_j_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_j_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10240000; +} + +static void +Opcode_j_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10100000; + slotbuf[1] = 0; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_l16ui_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d0000; + slotbuf[1] = 0; +} + +static void +Opcode_l16ui_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf50000; +} + +static void +Opcode_l16ui_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_l16ui_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0000; +} + +static void +Opcode_l16ui_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10430000; +} + +static void +Opcode_l16ui_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10190000; + slotbuf[1] = 0; +} + +static void +Opcode_l16ui_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_l16ui_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650000; +} + +static void +Opcode_l16ui_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f0000; +} + +static void +Opcode_l16ui_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9002; +} + +static void +Opcode_l16si_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c0000; + slotbuf[1] = 0; +} + +static void +Opcode_l16si_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_l16si_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_l16si_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_l16si_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10420000; +} + +static void +Opcode_l16si_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10180000; + slotbuf[1] = 0; +} + +static void +Opcode_l16si_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_l16si_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_l16si_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e0000; +} + +static void +Opcode_l16si_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_l32i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e0000; + slotbuf[1] = 0; +} + +static void +Opcode_l32i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_l32i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf60000; +} + +static void +Opcode_l32i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_l32i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_l32i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_l32i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_l32i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_l32i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10440000; +} + +static void +Opcode_l32i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_l32i_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101a0000; + slotbuf[1] = 0; +} + +static void +Opcode_l32i_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_l8ui_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f0000; + slotbuf[1] = 0; +} + +static void +Opcode_l8ui_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf70000; +} + +static void +Opcode_l8ui_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x450000; +} + +static void +Opcode_l8ui_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_l8ui_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10450000; +} + +static void +Opcode_l8ui_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101b0000; + slotbuf[1] = 0; +} + +static void +Opcode_l8ui_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_l8ui_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660000; +} + +static void +Opcode_l8ui_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_l8ui_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8076; +} + +static void +Opcode_loop_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8380070; + slotbuf[1] = 0; +} + +static void +Opcode_loop_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1130060; +} + +static void +Opcode_loop_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_loop_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f0020; +} + +static void +Opcode_loop_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0000; +} + +static void +Opcode_loop_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230000; + slotbuf[1] = 0; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9076; +} + +static void +Opcode_loopnez_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a0070; + slotbuf[1] = 0; +} + +static void +Opcode_loopnez_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1110080; +} + +static void +Opcode_loopnez_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0020; +} + +static void +Opcode_loopnez_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830080; +} + +static void +Opcode_loopnez_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0020; +} + +static void +Opcode_loopnez_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230002; + slotbuf[1] = 0; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa076; +} + +static void +Opcode_loopgtz_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8390070; + slotbuf[1] = 0; +} + +static void +Opcode_loopgtz_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1130070; +} + +static void +Opcode_loopgtz_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0010; +} + +static void +Opcode_loopgtz_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f0030; +} + +static void +Opcode_loopgtz_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0010; +} + +static void +Opcode_loopgtz_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230001; + slotbuf[1] = 0; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_movi_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107d0000; + slotbuf[1] = 0; +} + +static void +Opcode_movi_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_movi_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050000; +} + +static void +Opcode_movi_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144000; +} + +static void +Opcode_movi_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e0000; +} + +static void +Opcode_movi_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144000; +} + +static void +Opcode_movi_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d0000; +} + +static void +Opcode_movi_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_movi_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0000; +} + +static void +Opcode_movi_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_movi_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101f0000; + slotbuf[1] = 0; +} + +static void +Opcode_movi_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_movi_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_movi_Slot_f5_s3_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_movi_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_movi_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c000; +} + +static void +Opcode_movi_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_movi_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720000; +} + +static void +Opcode_movi_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d0000; +} + +static void +Opcode_movi_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_moveqz_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109d7000; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d1000; +} + +static void +Opcode_moveqz_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145e000; +} + +static void +Opcode_moveqz_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x243000; +} + +static void +Opcode_moveqz_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59f000; +} + +static void +Opcode_moveqz_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x244000; +} + +static void +Opcode_moveqz_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xadf000; +} + +static void +Opcode_moveqz_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x182000; +} + +static void +Opcode_moveqz_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d6000; +} + +static void +Opcode_moveqz_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x182000; +} + +static void +Opcode_moveqz_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1020d000; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d000; +} + +static void +Opcode_moveqz_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_moveqz_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d000; +} + +static void +Opcode_moveqz_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf000; +} + +static void +Opcode_moveqz_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc000; +} + +static void +Opcode_moveqz_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7fc000; +} + +static void +Opcode_moveqz_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c6000; +} + +static void +Opcode_moveqz_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa45000; +} + +static void +Opcode_moveqz_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a1000; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_movnez_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109de000; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f3000; +} + +static void +Opcode_movnez_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1476000; +} + +static void +Opcode_movnez_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x246000; +} + +static void +Opcode_movnez_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a5000; +} + +static void +Opcode_movnez_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x247000; +} + +static void +Opcode_movnez_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae6000; +} + +static void +Opcode_movnez_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x185000; +} + +static void +Opcode_movnez_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d5000; +} + +static void +Opcode_movnez_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x185000; +} + +static void +Opcode_movnez_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10210000; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_movnez_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_movnez_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_movnez_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb4000; +} + +static void +Opcode_movnez_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb000; +} + +static void +Opcode_movnez_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7fb000; +} + +static void +Opcode_movnez_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x658000; +} + +static void +Opcode_movnez_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4a000; +} + +static void +Opcode_movnez_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4000; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_movltz_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109db000; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3000; +} + +static void +Opcode_movltz_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x146e000; +} + +static void +Opcode_movltz_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x245000; +} + +static void +Opcode_movltz_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a3000; +} + +static void +Opcode_movltz_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x246000; +} + +static void +Opcode_movltz_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae3000; +} + +static void +Opcode_movltz_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x184000; +} + +static void +Opcode_movltz_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d3000; +} + +static void +Opcode_movltz_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x184000; +} + +static void +Opcode_movltz_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1020f000; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f000; +} + +static void +Opcode_movltz_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_movltz_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f000; +} + +static void +Opcode_movltz_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb2000; +} + +static void +Opcode_movltz_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b9000; +} + +static void +Opcode_movltz_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f9000; +} + +static void +Opcode_movltz_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c7000; +} + +static void +Opcode_movltz_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa48000; +} + +static void +Opcode_movltz_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a3000; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_movgez_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109da000; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f1000; +} + +static void +Opcode_movgez_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1466000; +} + +static void +Opcode_movgez_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x244000; +} + +static void +Opcode_movgez_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a1000; +} + +static void +Opcode_movgez_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x245000; +} + +static void +Opcode_movgez_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae2000; +} + +static void +Opcode_movgez_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x183000; +} + +static void +Opcode_movgez_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d1000; +} + +static void +Opcode_movgez_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x183000; +} + +static void +Opcode_movgez_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1020e000; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e000; +} + +static void +Opcode_movgez_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_movgez_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e000; +} + +static void +Opcode_movgez_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_movgez_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be000; +} + +static void +Opcode_movgez_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7fe000; +} + +static void +Opcode_movgez_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x747000; +} + +static void +Opcode_movgez_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa47000; +} + +static void +Opcode_movgez_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2000; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_neg_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a38001; + slotbuf[1] = 0; +} + +static void +Opcode_neg_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc00a; +} + +static void +Opcode_neg_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1465001; +} + +static void +Opcode_neg_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54800f; +} + +static void +Opcode_neg_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0c001; +} + +static void +Opcode_neg_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e8001; +} + +static void +Opcode_neg_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10222010; + slotbuf[1] = 0; +} + +static void +Opcode_neg_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b000; +} + +static void +Opcode_neg_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b600d; +} + +static void +Opcode_neg_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa59001; +} + +static void +Opcode_neg_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2002; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_abs_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a38000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c010; +} + +static void +Opcode_abs_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1465000; +} + +static void +Opcode_abs_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54800e; +} + +static void +Opcode_abs_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0c000; +} + +static void +Opcode_abs_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e8000; +} + +static void +Opcode_abs_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8007; +} + +static void +Opcode_abs_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10222000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000; +} + +static void +Opcode_abs_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c000; +} + +static void +Opcode_abs_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b600c; +} + +static void +Opcode_abs_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa59000; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f0; +} + +static void +Opcode_nop_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a222f5; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4704; +} + +static void +Opcode_nop_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26820d; +} + +static void +Opcode_nop_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0016; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1502655; +} + +static void +Opcode_nop_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280514; +} + +static void +Opcode_nop_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf518e4; +} + +static void +Opcode_nop_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000131; +} + +static void +Opcode_nop_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x602335; +} + +static void +Opcode_nop_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280514; +} + +static void +Opcode_nop_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e69883; +} + +static void +Opcode_nop_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800031; +} + +static void +Opcode_nop_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x833ad1; +} + +static void +Opcode_nop_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0114; +} + +static void +Opcode_nop_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000f; +} + +static void +Opcode_nop_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9810238; +} + +static void +Opcode_nop_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8180; +} + +static void +Opcode_nop_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f3475; +} + +static void +Opcode_nop_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198514; +} + +static void +Opcode_nop_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000c; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01e042; +} + +static void +Opcode_nop_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10223205; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac030; +} + +static void +Opcode_nop_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d001; +} + +static void +Opcode_nop_Slot_f5_s3_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20100; +} + +static void +Opcode_nop_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b031; +} + +static void +Opcode_nop_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2004; +} + +static void +Opcode_nop_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15400b; +} + +static void +Opcode_nop_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd830e2; +} + +static void +Opcode_nop_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8140; +} + +static void +Opcode_nop_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x852325; +} + +static void +Opcode_nop_Slot_n1_s1_none_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_nop_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65b005; +} + +static void +Opcode_nop_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9fb2f1; +} + +static void +Opcode_nop_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8704; +} + +static void +Opcode_nop_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8225; +} + +static void +Opcode_nop_Slot_n0_s1_none_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_nop_Slot_n0_s2_none_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_nop_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800381; +} + +static void +Opcode_l32ex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf14000; +} + +static void +Opcode_s32ex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf15000; +} + +static void +Opcode_getex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40a000; +} + +static void +Opcode_clrex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3120; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002; +} + +static void +Opcode_s16i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700000; + slotbuf[1] = 0; +} + +static void +Opcode_s16i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_s16i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x460000; +} + +static void +Opcode_s16i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_s16i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10460000; +} + +static void +Opcode_s16i_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101c0000; + slotbuf[1] = 0; +} + +static void +Opcode_s16i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x670000; +} + +static void +Opcode_s16i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_s32i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10710000; + slotbuf[1] = 0; +} + +static void +Opcode_s32i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90000; +} + +static void +Opcode_s32i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x470000; +} + +static void +Opcode_s32i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x710000; +} + +static void +Opcode_s32i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10470000; +} + +static void +Opcode_s32i_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101d0000; + slotbuf[1] = 0; +} + +static void +Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_s8i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10720000; + slotbuf[1] = 0; +} + +static void +Opcode_s8i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0000; +} + +static void +Opcode_s8i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_s8i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720000; +} + +static void +Opcode_s8i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480000; +} + +static void +Opcode_s8i_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101e0000; + slotbuf[1] = 0; +} + +static void +Opcode_s8i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ssr_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a36c50; + slotbuf[1] = 0; +} + +static void +Opcode_ssr_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1113ad0; +} + +static void +Opcode_ssr_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x604320; +} + +static void +Opcode_ssr_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0ac50; +} + +static void +Opcode_ssr_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f1170; +} + +static void +Opcode_ssr_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10223204; + slotbuf[1] = 0; +} + +static void +Opcode_ssr_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000b; +} + +static void +Opcode_ssr_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8234e0; +} + +static void +Opcode_ssr_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f39f0; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401000; +} + +static void +Opcode_ssl_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a36b50; + slotbuf[1] = 0; +} + +static void +Opcode_ssl_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11137d0; +} + +static void +Opcode_ssl_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x602320; +} + +static void +Opcode_ssl_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0ab50; +} + +static void +Opcode_ssl_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f3370; +} + +static void +Opcode_ssl_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10223203; + slotbuf[1] = 0; +} + +static void +Opcode_ssl_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8233e0; +} + +static void +Opcode_ssl_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f3ef0; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402000; +} + +static void +Opcode_ssa8l_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a36a50; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8l_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11136d0; +} + +static void +Opcode_ssa8l_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600320; +} + +static void +Opcode_ssa8l_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0aa50; +} + +static void +Opcode_ssa8l_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f3270; +} + +static void +Opcode_ssa8l_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10223202; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8l_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8232e0; +} + +static void +Opcode_ssa8l_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f3cf0; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403000; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_ssai_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a36850; + slotbuf[1] = 0; +} + +static void +Opcode_ssai_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11132d0; +} + +static void +Opcode_ssai_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54a01c; +} + +static void +Opcode_ssai_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0a850; +} + +static void +Opcode_ssai_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f1270; +} + +static void +Opcode_ssai_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10223200; + slotbuf[1] = 0; +} + +static void +Opcode_ssai_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8230e0; +} + +static void +Opcode_ssai_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f38f0; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_sll_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a34050; + slotbuf[1] = 0; +} + +static void +Opcode_sll_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc040; +} + +static void +Opcode_sll_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350000; +} + +static void +Opcode_sll_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11110d0; +} + +static void +Opcode_sll_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x286020; +} + +static void +Opcode_sll_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0070; +} + +static void +Opcode_sll_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x286020; +} + +static void +Opcode_sll_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb08050; +} + +static void +Opcode_sll_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa080; +} + +static void +Opcode_sll_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1000; +} + +static void +Opcode_sll_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0070; +} + +static void +Opcode_sll_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac040; +} + +static void +Opcode_sll_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230003; + slotbuf[1] = 0; +} + +static void +Opcode_sll_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad000; +} + +static void +Opcode_sll_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d000; +} + +static void +Opcode_sll_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c000; +} + +static void +Opcode_sll_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0010; +} + +static void +Opcode_sll_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000; +} + +static void +Opcode_sll_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d20e0; +} + +static void +Opcode_sll_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220e0; +} + +static void +Opcode_sll_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75a000; +} + +static void +Opcode_sll_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f10f0; +} + +static void +Opcode_sll_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cd010; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_src_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a1f000; + slotbuf[1] = 0; +} + +static void +Opcode_src_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f9000; +} + +static void +Opcode_src_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b6000; +} + +static void +Opcode_src_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf7000; +} + +static void +Opcode_src_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105df000; +} + +static void +Opcode_src_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10219000; + slotbuf[1] = 0; +} + +static void +Opcode_src_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000; +} + +static void +Opcode_src_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103000; +} + +static void +Opcode_src_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x817000; +} + +static void +Opcode_src_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa56000; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_srl_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a38003; + slotbuf[1] = 0; +} + +static void +Opcode_srl_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cd00a; +} + +static void +Opcode_srl_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36c010; +} + +static void +Opcode_srl_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1465003; +} + +static void +Opcode_srl_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x251001; +} + +static void +Opcode_srl_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54900f; +} + +static void +Opcode_srl_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282009; +} + +static void +Opcode_srl_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0c003; +} + +static void +Opcode_srl_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1001; +} + +static void +Opcode_srl_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00a0; +} + +static void +Opcode_srl_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e8003; +} + +static void +Opcode_srl_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8008; +} + +static void +Opcode_srl_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10222030; + slotbuf[1] = 0; +} + +static void +Opcode_srl_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac020; +} + +static void +Opcode_srl_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b020; +} + +static void +Opcode_srl_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b010; +} + +static void +Opcode_srl_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb001; +} + +static void +Opcode_srl_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c040; +} + +static void +Opcode_srl_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca001; +} + +static void +Opcode_srl_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b600f; +} + +static void +Opcode_srl_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65c040; +} + +static void +Opcode_srl_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa59003; +} + +static void +Opcode_srl_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3002; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_sra_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a38002; + slotbuf[1] = 0; +} + +static void +Opcode_sra_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc00b; +} + +static void +Opcode_sra_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ec010; +} + +static void +Opcode_sra_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1465002; +} + +static void +Opcode_sra_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x251000; +} + +static void +Opcode_sra_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54900e; +} + +static void +Opcode_sra_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282008; +} + +static void +Opcode_sra_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0c002; +} + +static void +Opcode_sra_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1000; +} + +static void +Opcode_sra_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0080; +} + +static void +Opcode_sra_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e8002; +} + +static void +Opcode_sra_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9007; +} + +static void +Opcode_sra_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10222020; + slotbuf[1] = 0; +} + +static void +Opcode_sra_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac010; +} + +static void +Opcode_sra_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b010; +} + +static void +Opcode_sra_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b000; +} + +static void +Opcode_sra_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb000; +} + +static void +Opcode_sra_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c020; +} + +static void +Opcode_sra_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca000; +} + +static void +Opcode_sra_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b600e; +} + +static void +Opcode_sra_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa59002; +} + +static void +Opcode_sra_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2003; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_slli_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1096a000; + slotbuf[1] = 0; +} + +static void +Opcode_slli_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_slli_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x256000; +} + +static void +Opcode_slli_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1382000; +} + +static void +Opcode_slli_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca000; +} + +static void +Opcode_slli_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57c000; +} + +static void +Opcode_slli_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21c000; +} + +static void +Opcode_slli_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6a000; +} + +static void +Opcode_slli_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_slli_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x152000; +} + +static void +Opcode_slli_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ac000; +} + +static void +Opcode_slli_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_slli_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200000; + slotbuf[1] = 0; +} + +static void +Opcode_slli_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x92000; +} + +static void +Opcode_slli_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32000; +} + +static void +Opcode_slli_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x152000; +} + +static void +Opcode_slli_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000; +} + +static void +Opcode_slli_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_slli_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_slli_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e0000; +} + +static void +Opcode_slli_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa24000; +} + +static void +Opcode_slli_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_srai_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109ca000; + slotbuf[1] = 0; +} + +static void +Opcode_srai_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16e000; +} + +static void +Opcode_srai_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254000; +} + +static void +Opcode_srai_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c0000; +} + +static void +Opcode_srai_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x238000; +} + +static void +Opcode_srai_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x592000; +} + +static void +Opcode_srai_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x238000; +} + +static void +Opcode_srai_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaca000; +} + +static void +Opcode_srai_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x176000; +} + +static void +Opcode_srai_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_srai_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c8000; +} + +static void +Opcode_srai_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x176000; +} + +static void +Opcode_srai_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10202000; + slotbuf[1] = 0; +} + +static void +Opcode_srai_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_srai_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_srai_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_srai_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2000; +} + +static void +Opcode_srai_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_srai_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae000; +} + +static void +Opcode_srai_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f6000; +} + +static void +Opcode_srai_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3a000; +} + +static void +Opcode_srai_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x196000; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_srli_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a2f000; + slotbuf[1] = 0; +} + +static void +Opcode_srli_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca000; +} + +static void +Opcode_srli_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x357000; +} + +static void +Opcode_srli_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145f000; +} + +static void +Opcode_srli_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250000; +} + +static void +Opcode_srli_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5be000; +} + +static void +Opcode_srli_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x251000; +} + +static void +Opcode_srli_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0d000; +} + +static void +Opcode_srli_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18f000; +} + +static void +Opcode_srli_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000; +} + +static void +Opcode_srli_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e7000; +} + +static void +Opcode_srli_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_srli_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10221000; + slotbuf[1] = 0; +} + +static void +Opcode_srli_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000; +} + +static void +Opcode_srli_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x45000; +} + +static void +Opcode_srli_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x164000; +} + +static void +Opcode_srli_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9000; +} + +static void +Opcode_srli_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_srli_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_srli_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81f000; +} + +static void +Opcode_srli_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5e000; +} + +static void +Opcode_srli_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1af000; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d0; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2010; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610100; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610200; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610300; +} + +static void +Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36100; +} + +static void +Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136100; +} + +static void +Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616100; +} + +static void +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30500; +} + +static void +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130500; +} + +static void +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610500; +} + +static void +Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e600; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e600; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e600; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b100; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b100; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b100; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d100; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d100; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d100; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b200; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b200; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b200; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d200; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d200; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d200; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b300; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b300; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b300; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d300; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d300; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d300; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b400; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b400; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b400; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d400; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d400; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c200; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c200; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c300; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c300; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c300; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c400; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c400; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ee00; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee00; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ee00; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e800; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e800; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e800; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3eb00; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e700; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e700; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e700; +} + +static void +Opcode_rsr_mpucfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35c00; +} + +static void +Opcode_wsr_mpucfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135c00; +} + +static void +Opcode_rsr_gserr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37400; +} + +static void +Opcode_wsr_gserr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137400; +} + +static void +Opcode_xsr_gserr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x617400; +} + +static void +Opcode_salt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720000; +} + +static void +Opcode_salt_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a1e000; + slotbuf[1] = 0; +} + +static void +Opcode_salt_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f2000; +} + +static void +Opcode_salt_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f1000; +} + +static void +Opcode_salt_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x248000; +} + +static void +Opcode_salt_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b2000; +} + +static void +Opcode_salt_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x249000; +} + +static void +Opcode_salt_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf3000; +} + +static void +Opcode_salt_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187000; +} + +static void +Opcode_salt_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105db000; +} + +static void +Opcode_salt_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187000; +} + +static void +Opcode_salt_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10217000; + slotbuf[1] = 0; +} + +static void +Opcode_salt_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2000; +} + +static void +Opcode_salt_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000; +} + +static void +Opcode_salt_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x162000; +} + +static void +Opcode_salt_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb8000; +} + +static void +Opcode_salt_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_salt_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x813000; +} + +static void +Opcode_salt_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x758000; +} + +static void +Opcode_salt_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa52000; +} + +static void +Opcode_salt_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6000; +} + +static void +Opcode_saltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620000; +} + +static void +Opcode_saltu_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a1d000; + slotbuf[1] = 0; +} + +static void +Opcode_saltu_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8000; +} + +static void +Opcode_saltu_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f8000; +} + +static void +Opcode_saltu_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x249000; +} + +static void +Opcode_saltu_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b4000; +} + +static void +Opcode_saltu_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24a000; +} + +static void +Opcode_saltu_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf6000; +} + +static void +Opcode_saltu_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_saltu_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105dd000; +} + +static void +Opcode_saltu_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_saltu_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10218000; + slotbuf[1] = 0; +} + +static void +Opcode_saltu_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3000; +} + +static void +Opcode_saltu_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x43000; +} + +static void +Opcode_saltu_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x163000; +} + +static void +Opcode_saltu_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba000; +} + +static void +Opcode_saltu_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c2000; +} + +static void +Opcode_saltu_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x815000; +} + +static void +Opcode_saltu_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d8000; +} + +static void +Opcode_saltu_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa54000; +} + +static void +Opcode_saltu_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a7000; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_mul16u_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a18000; + slotbuf[1] = 0; +} + +static void +Opcode_mul16u_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0000; +} + +static void +Opcode_mul16u_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e0000; +} + +static void +Opcode_mul16u_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a9000; +} + +static void +Opcode_mul16u_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaea000; +} + +static void +Opcode_mul16u_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d8000; +} + +static void +Opcode_mul16u_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10212000; + slotbuf[1] = 0; +} + +static void +Opcode_mul16u_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7ff000; +} + +static void +Opcode_mul16u_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4e000; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_mul16s_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109df000; + slotbuf[1] = 0; +} + +static void +Opcode_mul16s_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000; +} + +static void +Opcode_mul16s_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x147e000; +} + +static void +Opcode_mul16s_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a7000; +} + +static void +Opcode_mul16s_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae7000; +} + +static void +Opcode_mul16s_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d7000; +} + +static void +Opcode_mul16s_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10211000; + slotbuf[1] = 0; +} + +static void +Opcode_mul16s_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7fd000; +} + +static void +Opcode_mul16s_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4c000; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_mull_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a1a000; + slotbuf[1] = 0; +} + +static void +Opcode_mull_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e1000; +} + +static void +Opcode_mull_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5ab000; +} + +static void +Opcode_mull_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaeb000; +} + +static void +Opcode_mull_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105da000; +} + +static void +Opcode_mull_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10213000; + slotbuf[1] = 0; +} + +static void +Opcode_mull_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_mull_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa49000; +} + +static void +Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa20000; +} + +static void +Opcode_muluh_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a1b000; + slotbuf[1] = 0; +} + +static void +Opcode_muluh_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e9000; +} + +static void +Opcode_muluh_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5af000; +} + +static void +Opcode_muluh_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaef000; +} + +static void +Opcode_muluh_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105de000; +} + +static void +Opcode_muluh_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10215000; + slotbuf[1] = 0; +} + +static void +Opcode_muluh_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x814000; +} + +static void +Opcode_muluh_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4d000; +} + +static void +Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb20000; +} + +static void +Opcode_mulsh_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a19000; + slotbuf[1] = 0; +} + +static void +Opcode_mulsh_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e8000; +} + +static void +Opcode_mulsh_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5ad000; +} + +static void +Opcode_mulsh_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaee000; +} + +static void +Opcode_mulsh_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105dc000; +} + +static void +Opcode_mulsh_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10214000; + slotbuf[1] = 0; +} + +static void +Opcode_mulsh_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x812000; +} + +static void +Opcode_mulsh_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4b000; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3010; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e200; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e200; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e300; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e400; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e400; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02d; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619000; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a000; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616000; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e900; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e900; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e900; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ec00; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec00; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ec00; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed00; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ed00; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ed00; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36800; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136800; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616800; +} + +static void +Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e0; +} + +static void +Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f0; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e000; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e010; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135900; +} + +static void +Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000; +} + +static void +Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76; +} + +static void +Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1076; +} + +static void +Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30000; +} + +static void +Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30000; +} + +static void +Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30400; +} + +static void +Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130400; +} + +static void +Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610400; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ea00; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea00; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ea00; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f000; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f100; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f100; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f100; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c2; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e2; +} + +static void +Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70d2; +} + +static void +Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270d2; +} + +static void +Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370d2; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f2; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10000; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf12000; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf11000; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13000; +} + +static void +Opcode_wsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136200; +} + +static void +Opcode_rsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36200; +} + +static void +Opcode_xsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616200; +} + +static void +Opcode_rptlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50b000; +} + +static void +Opcode_pptlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50d000; +} + +static void +Opcode_rptlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50f000; +} + +static void +Opcode_wptlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50e000; +} + +static void +Opcode_rsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35a00; +} + +static void +Opcode_wsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135a00; +} + +static void +Opcode_xsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615a00; +} + +static void +Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e000; +} + +static void +Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_clamps_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a2b000; + slotbuf[1] = 0; +} + +static void +Opcode_clamps_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1457000; +} + +static void +Opcode_clamps_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5ba000; +} + +static void +Opcode_clamps_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa05000; +} + +static void +Opcode_clamps_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e3000; +} + +static void +Opcode_clamps_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18e000; +} + +static void +Opcode_clamps_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1021f000; + slotbuf[1] = 0; +} + +static void +Opcode_clamps_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000; +} + +static void +Opcode_clamps_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81b000; +} + +static void +Opcode_clamps_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6da000; +} + +static void +Opcode_clamps_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5a000; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_min_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109d3000; + slotbuf[1] = 0; +} + +static void +Opcode_min_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f8000; +} + +static void +Opcode_min_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144e000; +} + +static void +Opcode_min_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x241000; +} + +static void +Opcode_min_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59b000; +} + +static void +Opcode_min_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x242000; +} + +static void +Opcode_min_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xadb000; +} + +static void +Opcode_min_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_min_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d2000; +} + +static void +Opcode_min_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_min_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1020b000; + slotbuf[1] = 0; +} + +static void +Opcode_min_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b000; +} + +static void +Opcode_min_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_min_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000; +} + +static void +Opcode_min_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab000; +} + +static void +Opcode_min_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8000; +} + +static void +Opcode_min_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f8000; +} + +static void +Opcode_min_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c5000; +} + +static void +Opcode_min_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa41000; +} + +static void +Opcode_min_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19f000; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_max_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a17000; + slotbuf[1] = 0; +} + +static void +Opcode_max_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e8000; +} + +static void +Opcode_max_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d9000; +} + +static void +Opcode_max_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23f000; +} + +static void +Opcode_max_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59e000; +} + +static void +Opcode_max_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_max_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad7000; +} + +static void +Opcode_max_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e000; +} + +static void +Opcode_max_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105cf000; +} + +static void +Opcode_max_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e000; +} + +static void +Opcode_max_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10209000; + slotbuf[1] = 0; +} + +static void +Opcode_max_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x99000; +} + +static void +Opcode_max_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_max_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000; +} + +static void +Opcode_max_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae000; +} + +static void +Opcode_max_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b5000; +} + +static void +Opcode_max_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80d000; +} + +static void +Opcode_max_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c4000; +} + +static void +Opcode_max_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa44000; +} + +static void +Opcode_max_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19d000; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_minu_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109d6000; + slotbuf[1] = 0; +} + +static void +Opcode_minu_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f9000; +} + +static void +Opcode_minu_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1456000; +} + +static void +Opcode_minu_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x242000; +} + +static void +Opcode_minu_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59d000; +} + +static void +Opcode_minu_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x243000; +} + +static void +Opcode_minu_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xade000; +} + +static void +Opcode_minu_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x181000; +} + +static void +Opcode_minu_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d4000; +} + +static void +Opcode_minu_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x181000; +} + +static void +Opcode_minu_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1020c000; + slotbuf[1] = 0; +} + +static void +Opcode_minu_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000; +} + +static void +Opcode_minu_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_minu_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c000; +} + +static void +Opcode_minu_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad000; +} + +static void +Opcode_minu_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba000; +} + +static void +Opcode_minu_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7fa000; +} + +static void +Opcode_minu_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x746000; +} + +static void +Opcode_minu_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa43000; +} + +static void +Opcode_minu_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_maxu_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109d2000; + slotbuf[1] = 0; +} + +static void +Opcode_maxu_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e9000; +} + +static void +Opcode_maxu_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1446000; +} + +static void +Opcode_maxu_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_maxu_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x599000; +} + +static void +Opcode_maxu_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x241000; +} + +static void +Opcode_maxu_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xada000; +} + +static void +Opcode_maxu_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f000; +} + +static void +Opcode_maxu_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d0000; +} + +static void +Opcode_maxu_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f000; +} + +static void +Opcode_maxu_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1020a000; + slotbuf[1] = 0; +} + +static void +Opcode_maxu_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a000; +} + +static void +Opcode_maxu_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_maxu_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000; +} + +static void +Opcode_maxu_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9000; +} + +static void +Opcode_maxu_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7000; +} + +static void +Opcode_maxu_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80f000; +} + +static void +Opcode_maxu_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x745000; +} + +static void +Opcode_maxu_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa46000; +} + +static void +Opcode_maxu_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19e000; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e000; +} + +static void +Opcode_nsa_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a54200; + slotbuf[1] = 0; +} + +static void +Opcode_nsa_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4500; +} + +static void +Opcode_nsa_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514400; +} + +static void +Opcode_nsa_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600200; +} + +static void +Opcode_nsa_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d7c00; +} + +static void +Opcode_nsa_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10610100; +} + +static void +Opcode_nsa_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10223000; + slotbuf[1] = 0; +} + +static void +Opcode_nsa_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c000; +} + +static void +Opcode_nsa_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x850200; +} + +static void +Opcode_nsa_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f8c00; +} + +static void +Opcode_nsa_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8500; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f000; +} + +static void +Opcode_nsau_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a56200; + slotbuf[1] = 0; +} + +static void +Opcode_nsau_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d4500; +} + +static void +Opcode_nsau_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516400; +} + +static void +Opcode_nsau_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x602200; +} + +static void +Opcode_nsau_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d7d00; +} + +static void +Opcode_nsau_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10612100; +} + +static void +Opcode_nsau_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10223100; + slotbuf[1] = 0; +} + +static void +Opcode_nsau_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c100; +} + +static void +Opcode_nsau_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x852200; +} + +static void +Opcode_nsau_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f8e00; +} + +static void +Opcode_nsau_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba500; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_sext_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a2d000; + slotbuf[1] = 0; +} + +static void +Opcode_sext_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c3000; +} + +static void +Opcode_sext_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145d000; +} + +static void +Opcode_sext_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24f000; +} + +static void +Opcode_sext_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5bc000; +} + +static void +Opcode_sext_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250000; +} + +static void +Opcode_sext_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa09000; +} + +static void +Opcode_sext_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18e000; +} + +static void +Opcode_sext_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e5000; +} + +static void +Opcode_sext_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18f000; +} + +static void +Opcode_sext_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10220000; + slotbuf[1] = 0; +} + +static void +Opcode_sext_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab000; +} + +static void +Opcode_sext_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a000; +} + +static void +Opcode_sext_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb7000; +} + +static void +Opcode_sext_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c7000; +} + +static void +Opcode_sext_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81d000; +} + +static void +Opcode_sext_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5c000; +} + +static void +Opcode_sext_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ad000; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb002; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36300; +} + +static void +Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136300; +} + +static void +Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616300; +} + +static void +Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20000; +} + +static void +Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf20000; +} + +static void +Opcode_rsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35f00; +} + +static void +Opcode_wsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135f00; +} + +static void +Opcode_xsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615f00; +} + +static void +Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x406000; +} + +static void +Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x407000; +} + +static void +Opcode_beqz_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000060; + slotbuf[1] = 0; +} + +static void +Opcode_beqz_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000060; +} + +static void +Opcode_beqz_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000006; + slotbuf[1] = 0; +} + +static void +Opcode_bnez_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000360; + slotbuf[1] = 0; +} + +static void +Opcode_bnez_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000360; +} + +static void +Opcode_bnez_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000306; + slotbuf[1] = 0; +} + +static void +Opcode_bgez_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000160; + slotbuf[1] = 0; +} + +static void +Opcode_bgez_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000160; +} + +static void +Opcode_bgez_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000106; + slotbuf[1] = 0; +} + +static void +Opcode_bltz_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000260; + slotbuf[1] = 0; +} + +static void +Opcode_bltz_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000260; +} + +static void +Opcode_bltz_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000206; + slotbuf[1] = 0; +} + +static void +Opcode_beqi_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0; +} + +static void +Opcode_beqi_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_beqi_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0; +} + +static void +Opcode_bnei_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000050; + slotbuf[1] = 0; +} + +static void +Opcode_bnei_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000050; +} + +static void +Opcode_bnei_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000005; + slotbuf[1] = 0; +} + +static void +Opcode_bgei_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000010; + slotbuf[1] = 0; +} + +static void +Opcode_bgei_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000010; +} + +static void +Opcode_bgei_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000001; + slotbuf[1] = 0; +} + +static void +Opcode_blti_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000030; + slotbuf[1] = 0; +} + +static void +Opcode_blti_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000030; +} + +static void +Opcode_blti_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000003; + slotbuf[1] = 0; +} + +static void +Opcode_bgeui_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; + slotbuf[1] = 0; +} + +static void +Opcode_bgeui_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; +} + +static void +Opcode_bgeui_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002; + slotbuf[1] = 0; +} + +static void +Opcode_bltui_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000040; + slotbuf[1] = 0; +} + +static void +Opcode_bltui_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000040; +} + +static void +Opcode_bltui_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000004; + slotbuf[1] = 0; +} + +static void +Opcode_bbci_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_bbci_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_bbci_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_bbsi_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; + slotbuf[1] = 0; +} + +static void +Opcode_bbsi_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_bbsi_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; + slotbuf[1] = 0; +} + +static void +Opcode_beq_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; + slotbuf[1] = 0; +} + +static void +Opcode_beq_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; +} + +static void +Opcode_beq_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; + slotbuf[1] = 0; +} + +static void +Opcode_bne_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00; + slotbuf[1] = 0; +} + +static void +Opcode_bne_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00; +} + +static void +Opcode_bne_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00; + slotbuf[1] = 0; +} + +static void +Opcode_bge_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00; + slotbuf[1] = 0; +} + +static void +Opcode_bge_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00; +} + +static void +Opcode_bge_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00; + slotbuf[1] = 0; +} + +static void +Opcode_blt_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00; + slotbuf[1] = 0; +} + +static void +Opcode_blt_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00; +} + +static void +Opcode_blt_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00; + slotbuf[1] = 0; +} + +static void +Opcode_bgeu_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900; + slotbuf[1] = 0; +} + +static void +Opcode_bgeu_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900; +} + +static void +Opcode_bgeu_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900; + slotbuf[1] = 0; +} + +static void +Opcode_bltu_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00; + slotbuf[1] = 0; +} + +static void +Opcode_bltu_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00; +} + +static void +Opcode_bltu_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00; + slotbuf[1] = 0; +} + +static void +Opcode_bany_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500; + slotbuf[1] = 0; +} + +static void +Opcode_bany_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500; +} + +static void +Opcode_bany_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500; + slotbuf[1] = 0; +} + +static void +Opcode_bnone_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00; + slotbuf[1] = 0; +} + +static void +Opcode_bnone_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00; +} + +static void +Opcode_bnone_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00; + slotbuf[1] = 0; +} + +static void +Opcode_ball_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; + slotbuf[1] = 0; +} + +static void +Opcode_ball_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; +} + +static void +Opcode_ball_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; + slotbuf[1] = 0; +} + +static void +Opcode_bnall_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00; + slotbuf[1] = 0; +} + +static void +Opcode_bnall_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00; +} + +static void +Opcode_bnall_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00; + slotbuf[1] = 0; +} + +static void +Opcode_bbc_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; + slotbuf[1] = 0; +} + +static void +Opcode_bbc_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; +} + +static void +Opcode_bbc_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; + slotbuf[1] = 0; +} + +static void +Opcode_bbs_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; + slotbuf[1] = 0; +} + +static void +Opcode_bbs_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; +} + +static void +Opcode_bbs_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; + slotbuf[1] = 0; +} + +static void +Opcode_mtk_andpopc_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_mtk_andpopc_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0000; +} + +static void +Opcode_iq_tie2apb_inq0_pop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x362200; +} + +static void +Opcode_iq_tie2apb_inq0_is_ready_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x362100; +} + +static void +Opcode_iq_tie2apb_inq0_nonblocking_peek_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260000; +} + +static void +Opcode_iq_tie2apb_inq0_nonblocking_pop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260100; +} + +static void +Opcode_iq_tie2apb_inq0_blocking_peek_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x362000; +} + +static void +Opcode_oq_tie2apb_outq0_push_read_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360000; +} + +static void +Opcode_oq_tie2apb_outq0_push_write_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x361000; +} + +static void +Opcode_oq_tie2apb_outq0_is_ready_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x362300; +} + +static void +Opcode_oq_tie2apb_outq0_nonblocking_push_read_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_oq_tie2apb_outq0_nonblocking_push_write_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_rur_apb_pipe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30000; +} + +static void +Opcode_wur_apb_pipe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30000; +} + +xtensa_opcode_encode_fn Opcode_ivp_repnx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_repnx16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_repnx16_Slot_f0_s3_alu_encode, Opcode_ivp_repnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_repnx16_Slot_f1_s2_mul_encode, Opcode_ivp_repnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_repnx16_Slot_f2_s2_mul_encode, Opcode_ivp_repnx16_Slot_f2_s3_alu_encode, Opcode_ivp_repnx16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_repnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_repnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_repnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_repnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_selsnx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_selsnx16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_selsnx16_Slot_f0_s3_alu_encode, Opcode_ivp_selsnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_selsnx16_Slot_f1_s2_mul_encode, Opcode_ivp_selsnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_selsnx16_Slot_f2_s2_mul_encode, Opcode_ivp_selsnx16_Slot_f2_s3_alu_encode, Opcode_ivp_selsnx16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_selsnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_selsnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_selsnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_selsnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rep2nx8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_rep2nx8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_rep2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_rep2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_rep2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_rep2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_rep2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_rep2nx8_Slot_f2_s3_alu_encode, Opcode_ivp_rep2nx8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_rep2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rep2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rep2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rep2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sels2nx8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sels2nx8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_sels2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_sels2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_sels2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_sels2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_sels2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_sels2nx8_Slot_f2_s3_alu_encode, Opcode_ivp_sels2nx8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_sels2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_sels2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sels2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sels2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_repn_2x32_encode_fns[] = { + 0, 0, 0, Opcode_ivp_repn_2x32_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_repn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_repn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_repn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_repn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_repn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_repn_2x32_Slot_f2_s3_alu_encode, Opcode_ivp_repn_2x32_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_repn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_repn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_repn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_repn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_selsn_2x32_encode_fns[] = { + 0, 0, 0, Opcode_ivp_selsn_2x32_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_selsn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_selsn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_selsn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_selsn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_selsn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_selsn_2x32_Slot_f2_s3_alu_encode, Opcode_ivp_selsn_2x32_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_selsn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_selsn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_selsn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_selsn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_ext0ib_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ext0ib_Slot_f0_s1_ld_encode, 0, Opcode_ivp_ext0ib_Slot_f0_s3_alu_encode, 0, Opcode_ivp_ext0ib_Slot_f1_s1_ld_encode, 0, Opcode_ivp_ext0ib_Slot_f1_s3_alu_encode, 0, Opcode_ivp_ext0ib_Slot_f2_s1_ld_encode, 0, Opcode_ivp_ext0ib_Slot_f2_s3_alu_encode, 0, Opcode_ivp_ext0ib_Slot_f3_s1_ld_encode, 0, Opcode_ivp_ext0ib_Slot_f3_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ext0ib_Slot_f11_s1_alu_encode, 0, Opcode_ivp_ext0ib_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_ext0ib_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_notb_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_notb_Slot_f0_s1_ld_encode, 0, Opcode_ivp_notb_Slot_f0_s3_alu_encode, 0, Opcode_ivp_notb_Slot_f1_s1_ld_encode, 0, Opcode_ivp_notb_Slot_f1_s3_alu_encode, 0, Opcode_ivp_notb_Slot_f2_s1_ld_encode, 0, Opcode_ivp_notb_Slot_f2_s3_alu_encode, 0, Opcode_ivp_notb_Slot_f3_s1_ld_encode, 0, Opcode_ivp_notb_Slot_f3_s3_alu_encode, 0, 0, Opcode_ivp_notb_Slot_f4_s1_ld_encode, 0, Opcode_ivp_notb_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_notb_Slot_f11_s1_alu_encode, 0, Opcode_ivp_notb_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_notb_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_andb_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_andb_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_andb_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_andb_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_andb_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_andb_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_andb_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_orb_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_orb_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_orb_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_orb_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_orb_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_orb_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_orb_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_xorb_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_xorb_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_xorb_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_xorb_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_xorb_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_xorb_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_xorb_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_andnotb_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_andnotb_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_andnotb_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_andnotb_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_andnotb_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_andnotb_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_andnotb_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mb_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_mb_Slot_f0_s1_ld_encode, 0, Opcode_ivp_mb_Slot_f0_s3_alu_encode, 0, Opcode_ivp_mb_Slot_f1_s1_ld_encode, 0, Opcode_ivp_mb_Slot_f1_s3_alu_encode, 0, Opcode_ivp_mb_Slot_f2_s1_ld_encode, 0, Opcode_ivp_mb_Slot_f2_s3_alu_encode, 0, Opcode_ivp_mb_Slot_f3_s1_ld_encode, 0, Opcode_ivp_mb_Slot_f3_s3_alu_encode, 0, 0, Opcode_ivp_mb_Slot_f4_s1_ld_encode, 0, Opcode_ivp_mb_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_mb_Slot_f11_s1_alu_encode, 0, Opcode_ivp_mb_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_mb_Slot_n2_s1_ld_encode, 0, 0, 0, Opcode_ivp_mb_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltrn_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ltrn_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrn_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrn_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrn_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ltrn_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrn_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrn_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltrni_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ltrni_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrni_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrni_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrni_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ltrni_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrni_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrni_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lbn_i_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_lbn_i_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lbn_i_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_lbn_i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lbn_i_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lbn_ip_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_lbn_ip_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lbn_ip_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_lbn_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lbn_ip_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sbn_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sbn_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sbn_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sbn_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sbn_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sbn_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sbn_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sbn_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sbn_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sbn_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sbn_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sbn_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sbn_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sbn_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsnx16_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsnx16_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsnx16_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsnx16_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsnx16_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsnx16_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsnx16_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsnx16_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsnx16_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsnx16_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsnx16_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsnx16_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsnx16_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsnx16_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsnx16_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsnx16_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsnx16_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsnx16_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsnx16_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsnx16_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsnx16_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsnx16_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsnx16_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsnx16_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsnx16_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsnx16_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsnx16_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsnx16_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movbrbv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_movbrbv_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_movbrbv_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_movbrbv_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_movbrbv_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_movbrbv_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movbrbv_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movbrbv_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_movbvbr_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_movbvbr_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_movbvbr_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_movbvbr_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_movbvbr_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_movbvbr_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movbvbr_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movbvbr_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_joinb_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_joinb_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_joinb_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_joinb_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_joinb_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_joinb_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_joinb_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltrn_2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ltrn_2_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrn_2_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrn_2_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrn_2_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ltrn_2_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrn_2_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrn_2_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltrn_2i_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ltrn_2i_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrn_2i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrn_2i_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrn_2i_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ltrn_2i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrn_2i_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrn_2i_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lbn_2_i_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_lbn_2_i_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lbn_2_i_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_lbn_2_i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lbn_2_i_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lbn_2_ip_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_lbn_2_ip_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lbn_2_ip_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_lbn_2_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lbn_2_ip_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sbn_2_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sbn_2_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sbn_2_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sbn_2_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sbn_2_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sbn_2_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sbn_2_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sbn_2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sbn_2_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sbn_2_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sbn_2_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sbn_2_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sbn_2_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sbn_2_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lv2nx8_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lv2nx8_i_Slot_f0_s0_ldst_encode, Opcode_ivp_lv2nx8_i_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lv2nx8_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lv2nx8_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lv2nx8_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lv2nx8_i_Slot_f3_s0_ldst_encode, Opcode_ivp_lv2nx8_i_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lv2nx8_i_Slot_f4_s0_ld_encode, Opcode_ivp_lv2nx8_i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lv2nx8_i_Slot_n2_s0_ldst_encode, Opcode_ivp_lv2nx8_i_Slot_n2_s1_ld_encode, Opcode_ivp_lv2nx8_i_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lv2nx8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lv2nx8_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lv2nx8_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lv2nx8_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lv2nx8_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lv2nx8_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lv2nx8_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lv2nx8_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lv2nx8_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lv2nx8_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lv2nx8_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lv2nx8_ip_Slot_n2_s1_ld_encode, Opcode_ivp_lv2nx8_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lv2nx8_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lv2nx8_x_Slot_f0_s0_ldst_encode, Opcode_ivp_lv2nx8_x_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lv2nx8_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lv2nx8_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lv2nx8_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lv2nx8_x_Slot_f3_s0_ldst_encode, Opcode_ivp_lv2nx8_x_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lv2nx8_x_Slot_f4_s0_ld_encode, Opcode_ivp_lv2nx8_x_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lv2nx8_x_Slot_n2_s0_ldst_encode, Opcode_ivp_lv2nx8_x_Slot_n2_s1_ld_encode, Opcode_ivp_lv2nx8_x_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lv2nx8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lv2nx8_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lv2nx8_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lv2nx8_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lv2nx8_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lv2nx8_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lv2nx8_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lv2nx8_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lv2nx8_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lv2nx8_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lv2nx8_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lv2nx8_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lv2nx8_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sv2nx8_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sv2nx8_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sv2nx8_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sv2nx8_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sv2nx8_i_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_sv2nx8_i_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sv2nx8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sv2nx8_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sv2nx8_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sv2nx8_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sv2nx8_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_sv2nx8_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sv2nx8_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sv2nx8_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sv2nx8_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sv2nx8_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sv2nx8_x_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_sv2nx8_x_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sv2nx8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sv2nx8_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sv2nx8_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sv2nx8_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sv2nx8_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_sv2nx8_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssnx16_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssnx16_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx16_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssnx16_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx16_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssnx16_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssnx16_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx16_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssnx16_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx16_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssnx16_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssnx16_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx16_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssnx16_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx16_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssnx16_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssnx16_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx16_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssnx16_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx16_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movva16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movva16_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movva16_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movva16_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movva16_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movva16_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movva16_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movvv_encode_fns[] = { + 0, 0, 0, Opcode_ivp_movvv_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_movvv_Slot_f0_s3_alu_encode, Opcode_ivp_movvv_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_movvv_Slot_f1_s2_mul_encode, Opcode_ivp_movvv_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_movvv_Slot_f2_s2_mul_encode, Opcode_ivp_movvv_Slot_f2_s3_alu_encode, Opcode_ivp_movvv_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_movvv_Slot_f3_s3_alu_encode, Opcode_ivp_movvv_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_movvv_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movvv_Slot_f11_s3_alu_encode, Opcode_ivp_movvv_Slot_f11_s4_alu_encode, Opcode_ivp_movvv_Slot_n1_s0_ldst_encode, 0, Opcode_ivp_movvv_Slot_n1_s2_mul_encode, Opcode_ivp_movvv_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_movvv_Slot_n0_s0_ldst_encode, 0, 0, Opcode_ivp_movvv_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sllinx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sllinx16_Slot_f0_s3_alu_encode, 0, 0, Opcode_ivp_sllinx16_Slot_f1_s2_mul_encode, Opcode_ivp_sllinx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_sllinx16_Slot_f2_s2_mul_encode, Opcode_ivp_sllinx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_sllinx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_sllinx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sllinx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sllinx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_slsinx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_slsinx16_Slot_f0_s3_alu_encode, 0, 0, Opcode_ivp_slsinx16_Slot_f1_s2_mul_encode, Opcode_ivp_slsinx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_slsinx16_Slot_f2_s2_mul_encode, Opcode_ivp_slsinx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsinx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_slsinx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slsinx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slsinx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srainx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_srainx16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_srainx16_Slot_f0_s3_alu_encode, Opcode_ivp_srainx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_srainx16_Slot_f1_s2_mul_encode, Opcode_ivp_srainx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_srainx16_Slot_f2_s2_mul_encode, Opcode_ivp_srainx16_Slot_f2_s3_alu_encode, Opcode_ivp_srainx16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_srainx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srainx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srainx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srainx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srlinx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_srlinx16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_srlinx16_Slot_f0_s3_alu_encode, Opcode_ivp_srlinx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_srlinx16_Slot_f1_s2_mul_encode, Opcode_ivp_srlinx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_srlinx16_Slot_f2_s2_mul_encode, Opcode_ivp_srlinx16_Slot_f2_s3_alu_encode, Opcode_ivp_srlinx16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_srlinx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srlinx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srlinx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srlinx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sllnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sllnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_sllnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_sllnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_sllnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_sllnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sllnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sllnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srlnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_srlnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_srlnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_srlnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_srlnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srlnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srlnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srlnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_slanx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_slanx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_slanx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_slanx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_slanx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_slanx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slanx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slanx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sranx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sranx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_sranx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_sranx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_sranx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_sranx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sranx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sranx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_slsnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_slsnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_slsnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slsnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slsnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srsnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_srsnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_srsnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_srsnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_srsnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srsnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srsnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srsnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_xor2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_xor2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_xor2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_xor2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_xor2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_xor2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_xor2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_xor2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_xor2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_xor2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_xor2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_xor2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_xor2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_and2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_and2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_and2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_and2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_and2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_and2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_and2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_and2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_and2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_and2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_and2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_and2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_and2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_or2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_or2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_or2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_or2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_or2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_or2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_or2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_or2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_or2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_or2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_or2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_or2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_or2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_not2nx8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_not2nx8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_not2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_not2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_not2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_not2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_not2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_not2nx8_Slot_f2_s3_alu_encode, Opcode_ivp_not2nx8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_not2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_not2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_not2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_not2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_not2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_not2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_addnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_addnx16_Slot_f0_s3_alu_encode, Opcode_ivp_addnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_addnx16_Slot_f1_s2_mul_encode, Opcode_ivp_addnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_addnx16_Slot_f2_s2_mul_encode, Opcode_ivp_addnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_addnx16_Slot_f3_s3_alu_encode, Opcode_ivp_addnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_addnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addnx16_Slot_f11_s3_alu_encode, Opcode_ivp_addnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_subnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_subnx16_Slot_f0_s3_alu_encode, Opcode_ivp_subnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_subnx16_Slot_f1_s2_mul_encode, Opcode_ivp_subnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_subnx16_Slot_f2_s2_mul_encode, Opcode_ivp_subnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_subnx16_Slot_f3_s3_alu_encode, Opcode_ivp_subnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_subnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subnx16_Slot_f11_s3_alu_encode, Opcode_ivp_subnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_negnx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_negnx16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_negnx16_Slot_f0_s3_alu_encode, Opcode_ivp_negnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_negnx16_Slot_f1_s2_mul_encode, Opcode_ivp_negnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_negnx16_Slot_f2_s2_mul_encode, Opcode_ivp_negnx16_Slot_f2_s3_alu_encode, Opcode_ivp_negnx16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_negnx16_Slot_f3_s3_alu_encode, Opcode_ivp_negnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_negnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negnx16_Slot_f11_s3_alu_encode, Opcode_ivp_negnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_minnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_minnx16_Slot_f0_s3_alu_encode, Opcode_ivp_minnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_minnx16_Slot_f1_s2_mul_encode, Opcode_ivp_minnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_minnx16_Slot_f2_s2_mul_encode, Opcode_ivp_minnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_minnx16_Slot_f3_s3_alu_encode, Opcode_ivp_minnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_minnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minnx16_Slot_f11_s3_alu_encode, Opcode_ivp_minnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_minunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_minunx16_Slot_f0_s3_alu_encode, Opcode_ivp_minunx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_minunx16_Slot_f1_s2_mul_encode, Opcode_ivp_minunx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_minunx16_Slot_f2_s2_mul_encode, Opcode_ivp_minunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_minunx16_Slot_f3_s3_alu_encode, Opcode_ivp_minunx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_minunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minunx16_Slot_f11_s3_alu_encode, Opcode_ivp_minunx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_maxnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_maxnx16_Slot_f0_s3_alu_encode, Opcode_ivp_maxnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_maxnx16_Slot_f1_s2_mul_encode, Opcode_ivp_maxnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_maxnx16_Slot_f2_s2_mul_encode, Opcode_ivp_maxnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_maxnx16_Slot_f3_s3_alu_encode, Opcode_ivp_maxnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_maxnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxnx16_Slot_f11_s3_alu_encode, Opcode_ivp_maxnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_maxunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_maxunx16_Slot_f0_s3_alu_encode, Opcode_ivp_maxunx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_maxunx16_Slot_f1_s2_mul_encode, Opcode_ivp_maxunx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_maxunx16_Slot_f2_s2_mul_encode, Opcode_ivp_maxunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_maxunx16_Slot_f3_s3_alu_encode, Opcode_ivp_maxunx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_maxunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxunx16_Slot_f11_s3_alu_encode, Opcode_ivp_maxunx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsgnnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsgnnx16_Slot_f0_s3_alu_encode, Opcode_ivp_mulsgnnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_mulsgnnx16_Slot_f1_s2_mul_encode, Opcode_ivp_mulsgnnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_mulsgnnx16_Slot_f2_s2_mul_encode, Opcode_ivp_mulsgnnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_mulsgnnx16_Slot_f3_s3_alu_encode, Opcode_ivp_mulsgnnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_mulsgnnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsgnnx16_Slot_f11_s3_alu_encode, Opcode_ivp_mulsgnnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsgnnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_nsanx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_nsanx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsanx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsanx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsanx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_nsanx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_nsanx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_nsanx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_nsaunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_nsaunx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsaunx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsaunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsaunx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_nsaunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_nsaunx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_nsaunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_ltnx16_Slot_f0_s2_mul_encode, Opcode_ivp_ltnx16_Slot_f0_s3_alu_encode, Opcode_ivp_ltnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_ltnx16_Slot_f1_s2_mul_encode, Opcode_ivp_ltnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_ltnx16_Slot_f2_s2_mul_encode, Opcode_ivp_ltnx16_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_ltnx16_Slot_f3_s2_mul_encode, Opcode_ivp_ltnx16_Slot_f3_s3_alu_encode, Opcode_ivp_ltnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_ltnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltnx16_Slot_f11_s2_mul_encode, Opcode_ivp_ltnx16_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_ltnx16_Slot_n1_s2_mul_encode, Opcode_ivp_ltnx16_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_ltnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_lenx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_lenx16_Slot_f0_s2_mul_encode, Opcode_ivp_lenx16_Slot_f0_s3_alu_encode, Opcode_ivp_lenx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_lenx16_Slot_f1_s2_mul_encode, Opcode_ivp_lenx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_lenx16_Slot_f2_s2_mul_encode, Opcode_ivp_lenx16_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_lenx16_Slot_f3_s2_mul_encode, Opcode_ivp_lenx16_Slot_f3_s3_alu_encode, Opcode_ivp_lenx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_lenx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_lenx16_Slot_f11_s2_mul_encode, Opcode_ivp_lenx16_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_lenx16_Slot_n1_s2_mul_encode, Opcode_ivp_lenx16_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lenx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_eqnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_eqnx16_Slot_f0_s2_mul_encode, Opcode_ivp_eqnx16_Slot_f0_s3_alu_encode, Opcode_ivp_eqnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_eqnx16_Slot_f1_s2_mul_encode, Opcode_ivp_eqnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_eqnx16_Slot_f2_s2_mul_encode, Opcode_ivp_eqnx16_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_eqnx16_Slot_f3_s2_mul_encode, Opcode_ivp_eqnx16_Slot_f3_s3_alu_encode, Opcode_ivp_eqnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_eqnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_eqnx16_Slot_f11_s2_mul_encode, Opcode_ivp_eqnx16_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_eqnx16_Slot_n1_s2_mul_encode, Opcode_ivp_eqnx16_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_eqnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_neqnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_neqnx16_Slot_f0_s2_mul_encode, Opcode_ivp_neqnx16_Slot_f0_s3_alu_encode, Opcode_ivp_neqnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_neqnx16_Slot_f1_s2_mul_encode, Opcode_ivp_neqnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_neqnx16_Slot_f2_s2_mul_encode, Opcode_ivp_neqnx16_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_neqnx16_Slot_f3_s2_mul_encode, Opcode_ivp_neqnx16_Slot_f3_s3_alu_encode, Opcode_ivp_neqnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_neqnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_neqnx16_Slot_f11_s2_mul_encode, Opcode_ivp_neqnx16_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_neqnx16_Slot_n1_s2_mul_encode, Opcode_ivp_neqnx16_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_neqnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltunx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_ltunx16_Slot_f0_s2_mul_encode, Opcode_ivp_ltunx16_Slot_f0_s3_alu_encode, Opcode_ivp_ltunx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_ltunx16_Slot_f1_s2_mul_encode, Opcode_ivp_ltunx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_ltunx16_Slot_f2_s2_mul_encode, Opcode_ivp_ltunx16_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_ltunx16_Slot_f3_s2_mul_encode, Opcode_ivp_ltunx16_Slot_f3_s3_alu_encode, Opcode_ivp_ltunx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_ltunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltunx16_Slot_f11_s2_mul_encode, Opcode_ivp_ltunx16_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_ltunx16_Slot_n1_s2_mul_encode, Opcode_ivp_ltunx16_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_ltunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_leunx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_leunx16_Slot_f0_s2_mul_encode, Opcode_ivp_leunx16_Slot_f0_s3_alu_encode, Opcode_ivp_leunx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_leunx16_Slot_f1_s2_mul_encode, Opcode_ivp_leunx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_leunx16_Slot_f2_s2_mul_encode, Opcode_ivp_leunx16_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_leunx16_Slot_f3_s2_mul_encode, Opcode_ivp_leunx16_Slot_f3_s3_alu_encode, Opcode_ivp_leunx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_leunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_leunx16_Slot_f11_s2_mul_encode, Opcode_ivp_leunx16_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_leunx16_Slot_n1_s2_mul_encode, Opcode_ivp_leunx16_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_leunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rmaxnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rmaxnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rminnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rminnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rminnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rmaxunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxunx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxunx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxunx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rmaxunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxunx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rminunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rminunx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminunx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminunx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rminunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminunx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rbminnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rbminnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbminnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbminnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbminnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rbminnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rbminnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rbminnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rbmaxnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rbmaxnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbmaxnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbmaxnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbmaxnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rbmaxnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rbmaxnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rbmaxnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bmaxnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxnx16_Slot_f0_s3_alu_encode, Opcode_ivp_bmaxnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bmaxnx16_Slot_f1_s2_mul_encode, Opcode_ivp_bmaxnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bmaxnx16_Slot_f2_s2_mul_encode, Opcode_ivp_bmaxnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bmaxnx16_Slot_f3_s3_alu_encode, Opcode_ivp_bmaxnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bmaxnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxnx16_Slot_f11_s3_alu_encode, Opcode_ivp_bmaxnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bminnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bminnx16_Slot_f0_s3_alu_encode, Opcode_ivp_bminnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bminnx16_Slot_f1_s2_mul_encode, Opcode_ivp_bminnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bminnx16_Slot_f2_s2_mul_encode, Opcode_ivp_bminnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bminnx16_Slot_f3_s3_alu_encode, Opcode_ivp_bminnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bminnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminnx16_Slot_f11_s3_alu_encode, Opcode_ivp_bminnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_mov2nx8t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_mov2nx8t_Slot_f0_s3_alu_encode, Opcode_ivp_mov2nx8t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_mov2nx8t_Slot_f1_s2_mul_encode, Opcode_ivp_mov2nx8t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_mov2nx8t_Slot_f2_s2_mul_encode, Opcode_ivp_mov2nx8t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_mov2nx8t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_mov2nx8t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mov2nx8t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mov2nx8t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulanx16packl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16packl_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16packl_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulanx16packq_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16packq_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16packq_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsnx16packl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsnx16packl_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsnx16packl_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsnx16packq_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsnx16packq_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsnx16packq_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addsnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_addsnx16_Slot_f0_s3_alu_encode, Opcode_ivp_addsnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_addsnx16_Slot_f1_s2_mul_encode, Opcode_ivp_addsnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_addsnx16_Slot_f2_s2_mul_encode, Opcode_ivp_addsnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_addsnx16_Slot_f3_s3_alu_encode, Opcode_ivp_addsnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_addsnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addsnx16_Slot_f11_s3_alu_encode, Opcode_ivp_addsnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addsnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_subsnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_subsnx16_Slot_f0_s3_alu_encode, Opcode_ivp_subsnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_subsnx16_Slot_f1_s2_mul_encode, Opcode_ivp_subsnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_subsnx16_Slot_f2_s2_mul_encode, Opcode_ivp_subsnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_subsnx16_Slot_f3_s3_alu_encode, Opcode_ivp_subsnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_subsnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subsnx16_Slot_f11_s3_alu_encode, Opcode_ivp_subsnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subsnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_negsnx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_negsnx16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_negsnx16_Slot_f0_s3_alu_encode, Opcode_ivp_negsnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_negsnx16_Slot_f1_s2_mul_encode, Opcode_ivp_negsnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_negsnx16_Slot_f2_s2_mul_encode, Opcode_ivp_negsnx16_Slot_f2_s3_alu_encode, Opcode_ivp_negsnx16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_negsnx16_Slot_f3_s3_alu_encode, Opcode_ivp_negsnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_negsnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negsnx16_Slot_f11_s3_alu_encode, Opcode_ivp_negsnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negsnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_lv2nx8t_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lv2nx8t_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lv2nx8t_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lv2nx8t_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lv2nx8t_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lv2nx8t_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lv2nx8t_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lv2nx8t_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lv2nx8t_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lv2nx8t_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lv2nx8t_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lv2nx8t_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lv2nx8t_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lv2nx8t_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lv2nx8t_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lv2nx8t_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sv2nx8t_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sv2nx8t_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sv2nx8t_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sv2nx8t_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sv2nx8t_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sv2nx8t_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sv2nx8t_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sv2nx8t_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sv2nx8t_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sv2nx8t_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sv2nx8t_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sv2nx8t_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sv2nx8t_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sv2nx8t_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sv2nx8t_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sv2nx8t_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddnx16t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddnx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rmaxnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxnx16t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxnx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rmaxnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rminnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rminnx16t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminnx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rminnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rmaxunx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxunx16t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxunx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxunx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxunx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rmaxunx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxunx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxunx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rminunx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rminunx16t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminunx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminunx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminunx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rminunx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminunx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminunx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_addnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_addnx16t_Slot_f0_s3_alu_encode, Opcode_ivp_addnx16t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_addnx16t_Slot_f1_s2_mul_encode, Opcode_ivp_addnx16t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_addnx16t_Slot_f2_s2_mul_encode, Opcode_ivp_addnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_addnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_addnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_subnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_subnx16t_Slot_f0_s3_alu_encode, Opcode_ivp_subnx16t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_subnx16t_Slot_f1_s2_mul_encode, Opcode_ivp_subnx16t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_subnx16t_Slot_f2_s2_mul_encode, Opcode_ivp_subnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_subnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_subnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_negnx16t_encode_fns[] = { + 0, 0, 0, Opcode_ivp_negnx16t_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_negnx16t_Slot_f0_s3_alu_encode, Opcode_ivp_negnx16t_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_negnx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_negnx16t_Slot_f2_s3_alu_encode, Opcode_ivp_negnx16t_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_negnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_negnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_maxnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_maxnx16t_Slot_f0_s3_alu_encode, Opcode_ivp_maxnx16t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_maxnx16t_Slot_f1_s2_mul_encode, Opcode_ivp_maxnx16t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_maxnx16t_Slot_f2_s2_mul_encode, Opcode_ivp_maxnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_maxnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_maxnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_minnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_minnx16t_Slot_f0_s3_alu_encode, Opcode_ivp_minnx16t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_minnx16t_Slot_f1_s2_mul_encode, Opcode_ivp_minnx16t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_minnx16t_Slot_f2_s2_mul_encode, Opcode_ivp_minnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_minnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_minnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_maxunx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_maxunx16t_Slot_f0_s3_alu_encode, Opcode_ivp_maxunx16t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_maxunx16t_Slot_f1_s2_mul_encode, Opcode_ivp_maxunx16t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_maxunx16t_Slot_f2_s2_mul_encode, Opcode_ivp_maxunx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_maxunx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_maxunx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxunx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxunx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_minunx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_minunx16t_Slot_f0_s3_alu_encode, Opcode_ivp_minunx16t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_minunx16t_Slot_f1_s2_mul_encode, Opcode_ivp_minunx16t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_minunx16t_Slot_f2_s2_mul_encode, Opcode_ivp_minunx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_minunx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_minunx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minunx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minunx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulanx16packlt_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16packlt_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulanx16packqt_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16packqt_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addsnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_addsnx16t_Slot_f0_s3_alu_encode, Opcode_ivp_addsnx16t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_addsnx16t_Slot_f1_s2_mul_encode, Opcode_ivp_addsnx16t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_addsnx16t_Slot_f2_s2_mul_encode, Opcode_ivp_addsnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_addsnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_addsnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addsnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addsnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_subsnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_subsnx16t_Slot_f0_s3_alu_encode, Opcode_ivp_subsnx16t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_subsnx16t_Slot_f1_s2_mul_encode, Opcode_ivp_subsnx16t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_subsnx16t_Slot_f2_s2_mul_encode, Opcode_ivp_subsnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_subsnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_subsnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subsnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subsnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_negsnx16t_encode_fns[] = { + 0, 0, 0, Opcode_ivp_negsnx16t_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_negsnx16t_Slot_f0_s3_alu_encode, Opcode_ivp_negsnx16t_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_negsnx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_negsnx16t_Slot_f2_s3_alu_encode, Opcode_ivp_negsnx16t_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_negsnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_negsnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negsnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negsnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_lalign_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lalign_i_Slot_f0_s0_ldst_encode, Opcode_ivp_lalign_i_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lalign_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lalign_i_Slot_f1_s1_ld_encode, 0, 0, Opcode_ivp_lalign_i_Slot_f2_s0_ldst_encode, Opcode_ivp_lalign_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lalign_i_Slot_f3_s0_ldst_encode, Opcode_ivp_lalign_i_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lalign_i_Slot_f4_s0_ld_encode, Opcode_ivp_lalign_i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lalign_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lalign_i_Slot_n2_s0_ldst_encode, Opcode_ivp_lalign_i_Slot_n2_s1_ld_encode, Opcode_ivp_lalign_i_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lalign_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lalign_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lalign_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lalign_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lalign_ip_Slot_f1_s1_ld_encode, 0, 0, Opcode_ivp_lalign_ip_Slot_f2_s0_ldst_encode, Opcode_ivp_lalign_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lalign_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lalign_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lalign_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lalign_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lalign_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lalign_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lalign_ip_Slot_n2_s1_ld_encode, Opcode_ivp_lalign_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_salign_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_salign_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_salign_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_salign_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_salign_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_salign_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_salign_i_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_salign_i_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_salign_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_salign_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_salign_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_salign_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_salign_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_salign_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_salign_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_salign_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_la_pp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_la_pp_Slot_f0_s0_ldst_encode, Opcode_ivp_la_pp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_la_pp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_la_pp_Slot_f1_s1_ld_encode, 0, 0, Opcode_ivp_la_pp_Slot_f2_s0_ldst_encode, Opcode_ivp_la_pp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_la_pp_Slot_f3_s0_ldst_encode, Opcode_ivp_la_pp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_la_pp_Slot_f4_s0_ld_encode, Opcode_ivp_la_pp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_la_pp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_la_pp_Slot_n2_s0_ldst_encode, Opcode_ivp_la_pp_Slot_n2_s1_ld_encode, Opcode_ivp_la_pp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sapos_fp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sapos_fp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sapos_fp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sapos_fp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sapos_fp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sapos_fp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sapos_fp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_sapos_fp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_malign_encode_fns[] = { + 0, 0, 0, Opcode_ivp_malign_Slot_f0_s0_ldst_encode, Opcode_ivp_malign_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_malign_Slot_f1_s0_ldstalu_encode, Opcode_ivp_malign_Slot_f1_s1_ld_encode, 0, 0, Opcode_ivp_malign_Slot_f2_s0_ldst_encode, Opcode_ivp_malign_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_malign_Slot_f3_s0_ldst_encode, Opcode_ivp_malign_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_malign_Slot_f4_s0_ld_encode, Opcode_ivp_malign_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_malign_Slot_f11_s0_ld_encode, Opcode_ivp_malign_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_ivp_malign_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_malign_Slot_n2_s0_ldst_encode, Opcode_ivp_malign_Slot_n2_s1_ld_encode, Opcode_ivp_malign_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_zalign_encode_fns[] = { + 0, 0, 0, Opcode_ivp_zalign_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_zalign_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_zalign_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_zalign_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_zalign_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_zalign_Slot_f11_s0_ld_encode, 0, 0, 0, 0, Opcode_ivp_zalign_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_zalign_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_zalign_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_la2nx8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_la2nx8_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_la2nx8_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_la2nx8_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_la2nx8_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_la2nx8_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_la2nx8_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_la2nx8_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_la2nx8_ip_Slot_f4_s0_ld_encode, Opcode_ivp_la2nx8_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_la2nx8_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_la2nx8_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_la2nx8_ip_Slot_n2_s1_ld_encode, Opcode_ivp_la2nx8_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sa2nx8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sa2nx8_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sa2nx8_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sa2nx8_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sa2nx8_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sa2nx8_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sa2nx8_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_sa2nx8_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lav2nx8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lav2nx8_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lav2nx8_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lav2nx8_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lav2nx8_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lav2nx8_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lav2nx8_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lav2nx8_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lav2nx8_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lav2nx8_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lav2nx8_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lav2nx8_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lav2nx8_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lav2nx8_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sav2nx8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sav2nx8_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sav2nx8_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sav2nx8_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sav2nx8_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sav2nx8_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sav2nx8_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_sav2nx8_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_selnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_selnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_selnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_selnx16_Slot_f2_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_selnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_shflnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_shflnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_shflnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_shflnx16_Slot_f2_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_shflnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_movpint16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movpint16_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movpint16_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movpint16_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movpint16_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movpint16_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movpint16_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movpa16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movpa16_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movpa16_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulnx16packp_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulnx16packp_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulnx16packp_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulnx16packp_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulanx16packp_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16packp_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16packp_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsnx16packp_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsnx16packp_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsnx16packp_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulanx16packpt_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16packpt_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addmod16u_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_addmod16u_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addmod16u_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_addmod16u_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_addmod16u_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8s_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8s_i_Slot_f0_s0_ldst_encode, Opcode_ivp_lvnx8s_i_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8s_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvnx8s_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8s_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8s_i_Slot_f3_s0_ldst_encode, Opcode_ivp_lvnx8s_i_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8s_i_Slot_f4_s0_ld_encode, Opcode_ivp_lvnx8s_i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8s_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8s_i_Slot_n2_s0_ldst_encode, Opcode_ivp_lvnx8s_i_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8s_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lvnx8s_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8s_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvnx8s_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8s_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8s_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lvnx8s_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8s_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lvnx8s_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8s_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8s_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lvnx8s_ip_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8s_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8s_x_Slot_f0_s0_ldst_encode, Opcode_ivp_lvnx8s_x_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8s_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvnx8s_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8s_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8s_x_Slot_f3_s0_ldst_encode, Opcode_ivp_lvnx8s_x_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8s_x_Slot_f4_s0_ld_encode, Opcode_ivp_lvnx8s_x_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8s_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8s_x_Slot_n2_s0_ldst_encode, Opcode_ivp_lvnx8s_x_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8s_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lvnx8s_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8s_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvnx8s_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8s_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8s_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lvnx8s_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8s_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lvnx8s_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8s_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lvnx8s_xp_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8u_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8u_i_Slot_f0_s0_ldst_encode, Opcode_ivp_lvnx8u_i_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8u_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvnx8u_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8u_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8u_i_Slot_f3_s0_ldst_encode, Opcode_ivp_lvnx8u_i_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8u_i_Slot_f4_s0_ld_encode, Opcode_ivp_lvnx8u_i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8u_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8u_i_Slot_n2_s0_ldst_encode, Opcode_ivp_lvnx8u_i_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8u_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lvnx8u_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8u_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvnx8u_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8u_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8u_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lvnx8u_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8u_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lvnx8u_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8u_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8u_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lvnx8u_ip_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8u_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8u_x_Slot_f0_s0_ldst_encode, Opcode_ivp_lvnx8u_x_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8u_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvnx8u_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8u_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8u_x_Slot_f3_s0_ldst_encode, Opcode_ivp_lvnx8u_x_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8u_x_Slot_f4_s0_ld_encode, Opcode_ivp_lvnx8u_x_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8u_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8u_x_Slot_n2_s0_ldst_encode, Opcode_ivp_lvnx8u_x_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8u_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lvnx8u_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8u_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvnx8u_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8u_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8u_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lvnx8u_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8u_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lvnx8u_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8u_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lvnx8u_xp_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8u_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8u_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8u_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8u_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8u_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8u_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8u_i_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svnx8u_i_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8u_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8u_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8u_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8u_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8u_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8u_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svnx8u_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8u_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8u_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8u_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8u_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8u_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8u_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8u_x_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svnx8u_x_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8u_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8u_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8u_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8u_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8u_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svnx8u_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8st_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8st_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvnx8st_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8st_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvnx8st_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8st_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8st_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8st_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8st_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvnx8st_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8st_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvnx8st_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8st_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8st_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8st_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8st_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvnx8st_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8st_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvnx8st_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8st_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8st_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8st_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8st_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvnx8st_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8st_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvnx8st_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8st_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8st_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8ut_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8ut_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvnx8ut_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8ut_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8ut_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8ut_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvnx8ut_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8ut_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8ut_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8ut_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvnx8ut_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8ut_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8ut_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8ut_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvnx8ut_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8ut_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8ut_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8ut_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8ut_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8ut_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8ut_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8ut_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8ut_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8ut_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8ut_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8ut_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8ut_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8ut_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8ut_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8ut_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8ut_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8ut_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8ut_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8ut_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8ut_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8ut_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8ut_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8ut_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8ut_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8ut_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8ut_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8ut_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8ut_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8ut_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lavnx8s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lavnx8s_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lavnx8s_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lavnx8s_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lavnx8s_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lavnx8s_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lavnx8s_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lavnx8s_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lavnx8s_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lavnx8s_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lavnx8s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lavnx8s_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lavnx8s_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lavnx8s_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lavnx8u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lavnx8u_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lavnx8u_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lavnx8u_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lavnx8u_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lavnx8u_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lavnx8u_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lavnx8u_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lavnx8u_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lavnx8u_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lavnx8u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lavnx8u_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lavnx8u_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lavnx8u_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_savnx8u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_savnx8u_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_savnx8u_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_savnx8u_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_savnx8u_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_savnx8u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_savnx8u_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_savnx8u_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lanx8s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lanx8s_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lanx8s_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lanx8s_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lanx8s_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lanx8s_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lanx8s_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lanx8s_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lanx8s_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lanx8s_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lanx8s_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lanx8s_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lanx8s_ip_Slot_n2_s1_ld_encode, Opcode_ivp_lanx8s_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lanx8u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lanx8u_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lanx8u_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lanx8u_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lanx8u_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lanx8u_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lanx8u_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lanx8u_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lanx8u_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lanx8u_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lanx8u_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lanx8u_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lanx8u_ip_Slot_n2_s1_ld_encode, Opcode_ivp_lanx8u_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sanx8u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sanx8u_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sanx8u_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sanx8u_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sanx8u_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sanx8u_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sanx8u_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_sanx8u_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_extractbl_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_extractbl_Slot_f0_s1_ld_encode, 0, Opcode_ivp_extractbl_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_extractbl_Slot_f1_s3_alu_encode, 0, Opcode_ivp_extractbl_Slot_f2_s1_ld_encode, 0, Opcode_ivp_extractbl_Slot_f2_s3_alu_encode, 0, Opcode_ivp_extractbl_Slot_f3_s1_ld_encode, 0, Opcode_ivp_extractbl_Slot_f3_s3_alu_encode, 0, 0, Opcode_ivp_extractbl_Slot_f4_s1_ld_encode, 0, Opcode_ivp_extractbl_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extractbl_Slot_n2_s1_ld_encode, 0, 0, 0, Opcode_ivp_extractbl_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_extractbh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_extractbh_Slot_f0_s1_ld_encode, 0, Opcode_ivp_extractbh_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_extractbh_Slot_f1_s3_alu_encode, 0, Opcode_ivp_extractbh_Slot_f2_s1_ld_encode, 0, Opcode_ivp_extractbh_Slot_f2_s3_alu_encode, 0, Opcode_ivp_extractbh_Slot_f3_s1_ld_encode, 0, Opcode_ivp_extractbh_Slot_f3_s3_alu_encode, 0, 0, Opcode_ivp_extractbh_Slot_f4_s1_ld_encode, 0, Opcode_ivp_extractbh_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extractbh_Slot_n2_s1_ld_encode, 0, 0, 0, Opcode_ivp_extractbh_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_movvint16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movvint16_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movvint16_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movvint16_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movvint16_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movvint16_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movvint16_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movqint16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movqint16_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movqint16_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movqint16_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movqint16_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movqint16_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movqint16_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movqa16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movqa16_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movqa16_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movvinx16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movvinx16_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movvinx16_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movvinx16_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movvinx16_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movvinx16_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movvinx16_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_seqnx16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_seqnx16_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_seqnx16_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_seqnx16_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_seqnx16_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_seqnx16_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_seqnx16_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulnx16packl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulnx16packl_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulnx16packl_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulnx16packl_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulnx16packq_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulnx16packq_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulnx16packq_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulnx16packq_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movav16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_movav16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_movav16_Slot_f0_s3_alu_encode, Opcode_ivp_movav16_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_movav16_Slot_f1_s3_alu_encode, Opcode_ivp_movav16_Slot_f2_s0_ldst_encode, 0, 0, Opcode_ivp_movav16_Slot_f2_s3_alu_encode, Opcode_ivp_movav16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_movav16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_movav16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movav16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movav16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_movavu16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_movavu16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_movavu16_Slot_f0_s3_alu_encode, Opcode_ivp_movavu16_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_movavu16_Slot_f1_s3_alu_encode, Opcode_ivp_movavu16_Slot_f2_s0_ldst_encode, 0, 0, Opcode_ivp_movavu16_Slot_f2_s3_alu_encode, Opcode_ivp_movavu16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_movavu16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_movavu16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movavu16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movavu16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_extrnx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_extrnx16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_extrnx16_Slot_f0_s3_alu_encode, Opcode_ivp_extrnx16_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_extrnx16_Slot_f1_s3_alu_encode, Opcode_ivp_extrnx16_Slot_f2_s0_ldst_encode, 0, 0, Opcode_ivp_extrnx16_Slot_f2_s3_alu_encode, Opcode_ivp_extrnx16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_extrnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_extrnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extrnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extrnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsnx8s_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsnx8s_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsnx8s_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsnx8s_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsnx8s_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsnx8s_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsnx8s_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsnx8s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsnx8s_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsnx8s_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsnx8s_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsnx8s_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsnx8s_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsnx8s_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsnx8s_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsnx8s_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsnx8s_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsnx8s_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsnx8s_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsnx8s_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsnx8s_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsnx8s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsnx8s_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsnx8s_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsnx8s_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsnx8s_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsnx8s_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsnx8s_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8s_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8s_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8s_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8s_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8s_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8s_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8s_i_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svnx8s_i_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8s_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8s_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8s_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8s_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8s_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8s_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svnx8s_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8s_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8s_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8s_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8s_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8s_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8s_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8s_x_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svnx8s_x_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8s_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8s_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8s_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8s_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8s_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svnx8s_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssnx8s_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssnx8s_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx8s_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssnx8s_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx8s_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssnx8s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssnx8s_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx8s_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssnx8s_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx8s_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssnx8s_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssnx8s_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx8s_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssnx8s_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx8s_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssnx8s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssnx8s_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx8s_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssnx8s_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx8s_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_savnx8s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_savnx8s_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_savnx8s_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_savnx8s_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_savnx8s_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_savnx8s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_savnx8s_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_savnx8s_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sanx8s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sanx8s_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sanx8s_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sanx8s_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sanx8s_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sanx8s_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sanx8s_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_sanx8s_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8st_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8st_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8st_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8st_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8st_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8st_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8st_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8st_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8st_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8st_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8st_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8st_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8st_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8st_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8st_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8st_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8st_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8st_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8st_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8st_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8st_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8st_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8st_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8st_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8st_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8st_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8st_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8st_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movba1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movba1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movba1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movba1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movba1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movba1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movba1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movab1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movab1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movab1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movab1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movab1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movab1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movab1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_notb1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_notb1_Slot_f0_s1_ld_encode, 0, Opcode_ivp_notb1_Slot_f0_s3_alu_encode, 0, Opcode_ivp_notb1_Slot_f1_s1_ld_encode, 0, Opcode_ivp_notb1_Slot_f1_s3_alu_encode, 0, Opcode_ivp_notb1_Slot_f2_s1_ld_encode, 0, Opcode_ivp_notb1_Slot_f2_s3_alu_encode, 0, Opcode_ivp_notb1_Slot_f3_s1_ld_encode, 0, Opcode_ivp_notb1_Slot_f3_s3_alu_encode, 0, 0, Opcode_ivp_notb1_Slot_f4_s1_ld_encode, 0, Opcode_ivp_notb1_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_notb1_Slot_f11_s1_alu_encode, 0, Opcode_ivp_notb1_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_notb1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_andnotb1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_andnotb1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_andnotb1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_andnotb1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_andnotb1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_andnotb1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_andnotb1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ornotb1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ornotb1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ornotb1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ornotb1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ornotb1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ornotb1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ornotb1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt32s2nx24ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24ll_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24ll_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24ll_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24ll_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24ll_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24ll_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt32s2nx24lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24lh_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24lh_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24lh_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24lh_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24lh_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24lh_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt32s2nx24hl_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24hl_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24hl_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24hl_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24hl_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24hl_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24hl_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt32s2nx24hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24hh_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24hh_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24hh_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24hh_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24hh_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24hh_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt64snx48ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt64snx48ll_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt64snx48ll_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt64snx48lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt64snx48lh_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt64snx48lh_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt64snx48hl_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt64snx48hl_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt64snx48hl_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt64snx48hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt64snx48hh_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt64snx48hh_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt16s2nx24l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt16s2nx24l_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16s2nx24l_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16s2nx24l_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16s2nx24l_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt16s2nx24l_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt16s2nx24l_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt16s2nx24h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt16s2nx24h_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16s2nx24h_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16s2nx24h_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16s2nx24h_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt16s2nx24h_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt16s2nx24h_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt32snx48l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt32snx48l_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32snx48l_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32snx48l_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32snx48l_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt32snx48l_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt32snx48l_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt32snx48h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt32snx48h_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32snx48h_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32snx48h_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32snx48h_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt32snx48h_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt32snx48h_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt16u2nx24h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt16u2nx24h_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16u2nx24h_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16u2nx24h_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16u2nx24h_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt16u2nx24h_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt16u2nx24h_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt32unx48h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt32unx48h_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32unx48h_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32unx48h_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32unx48h_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt32unx48h_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt32unx48h_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt64un_2x96h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt64un_2x96h_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt64un_2x96h_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt16u2nx24l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt16u2nx24l_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16u2nx24l_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16u2nx24l_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16u2nx24l_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt16u2nx24l_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt16u2nx24l_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt24u2nx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt24u2nx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24u2nx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24u2nx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24u2nx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt24u2nx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt24u2nx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt24s2nx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt24s2nx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24s2nx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24s2nx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24s2nx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt24s2nx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt32s24_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt32s24_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s24_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s24_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s24_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt32s24_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt32s24_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt24u32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt24u32_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24u32_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24u32_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24u32_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt24u32_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt24u32_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt24unx32l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt24unx32l_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24unx32l_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24unx32l_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24unx32l_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt24unx32l_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt24unx32l_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt24unx32h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt24unx32h_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24unx32h_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24unx32h_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24unx32h_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt24unx32h_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt24unx32h_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt32unx48l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt32unx48l_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32unx48l_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32unx48l_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32unx48l_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt32unx48l_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt32unx48l_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt48unx32l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt48unx32l_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48unx32l_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48unx32l_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48unx32l_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt48unx32l_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt48unx32l_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt48unx32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt48unx32_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48unx32_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48unx32_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48unx32_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt48unx32_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt48unx32_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt48snx32l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt48snx32l_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48snx32l_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48snx32l_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48snx32l_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt48snx32l_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt48snx32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt48snx32_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48snx32_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48snx32_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48snx32_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt48snx32_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt64s48_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt64s48_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt64s48_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt64s48_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt64s48_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt64s48_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt64s48_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt48u64_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt48u64_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48u64_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48u64_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48u64_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt48u64_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt48u64_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt48un_2x64l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt48un_2x64l_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48un_2x64l_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48un_2x64l_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48un_2x64l_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt48un_2x64l_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt48un_2x64l_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt48un_2x64h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt48un_2x64h_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48un_2x64h_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48un_2x64h_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48un_2x64h_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt48un_2x64h_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt48un_2x64h_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt64un_2x96l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt64un_2x96l_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt64un_2x96l_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt96un_2x64_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt96un_2x64_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt96un_2x64_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt96un_2x64_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt96un_2x64_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt96un_2x64_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt96un_2x64_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt96u64_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt96u64_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt96u64_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt96u64_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt96u64_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt96u64_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt96u64_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt64u96_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt64u96_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt64u96_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt64u96_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt64u96_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt64u96_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt64u96_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lb2n_i_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_lb2n_i_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lb2n_i_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_lb2n_i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lb2n_i_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lb2n_ip_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_lb2n_ip_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lb2n_ip_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_lb2n_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lb2n_ip_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sb2n_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sb2n_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sb2n_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sb2n_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sb2n_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sb2n_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sb2n_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sb2n_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sb2n_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sb2n_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sb2n_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sb2n_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sb2n_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sb2n_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltr2n_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ltr2n_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltr2n_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltr2n_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltr2n_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ltr2n_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltr2n_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltr2n_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltr2ni_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ltr2ni_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltr2ni_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltr2ni_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltr2ni_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ltr2ni_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltr2ni_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltr2ni_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16u_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16u_i_Slot_f0_s0_ldst_encode, Opcode_ivp_lvn_2x16u_i_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16u_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvn_2x16u_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16u_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16u_i_Slot_f3_s0_ldst_encode, Opcode_ivp_lvn_2x16u_i_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16u_i_Slot_f4_s0_ld_encode, Opcode_ivp_lvn_2x16u_i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16u_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16u_i_Slot_n2_s0_ldst_encode, Opcode_ivp_lvn_2x16u_i_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16u_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lvn_2x16u_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16u_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvn_2x16u_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16u_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16u_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lvn_2x16u_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16u_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lvn_2x16u_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16u_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16u_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lvn_2x16u_ip_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16u_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16u_x_Slot_f0_s0_ldst_encode, Opcode_ivp_lvn_2x16u_x_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16u_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvn_2x16u_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16u_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16u_x_Slot_f3_s0_ldst_encode, Opcode_ivp_lvn_2x16u_x_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16u_x_Slot_f4_s0_ld_encode, Opcode_ivp_lvn_2x16u_x_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16u_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16u_x_Slot_n2_s0_ldst_encode, Opcode_ivp_lvn_2x16u_x_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16u_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lvn_2x16u_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16u_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvn_2x16u_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16u_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16u_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lvn_2x16u_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16u_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lvn_2x16u_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16u_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lvn_2x16u_xp_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16ut_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16ut_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvn_2x16ut_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16ut_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16ut_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16ut_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvn_2x16ut_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16ut_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16ut_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16ut_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvn_2x16ut_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16ut_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16ut_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16ut_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvn_2x16ut_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16ut_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16s_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16s_i_Slot_f0_s0_ldst_encode, Opcode_ivp_lvn_2x16s_i_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16s_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvn_2x16s_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16s_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16s_i_Slot_f3_s0_ldst_encode, Opcode_ivp_lvn_2x16s_i_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16s_i_Slot_f4_s0_ld_encode, Opcode_ivp_lvn_2x16s_i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16s_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16s_i_Slot_n2_s0_ldst_encode, Opcode_ivp_lvn_2x16s_i_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16s_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lvn_2x16s_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16s_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvn_2x16s_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16s_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16s_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lvn_2x16s_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16s_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lvn_2x16s_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16s_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16s_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lvn_2x16s_ip_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16s_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16s_x_Slot_f0_s0_ldst_encode, Opcode_ivp_lvn_2x16s_x_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16s_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvn_2x16s_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16s_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16s_x_Slot_f3_s0_ldst_encode, Opcode_ivp_lvn_2x16s_x_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16s_x_Slot_f4_s0_ld_encode, Opcode_ivp_lvn_2x16s_x_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16s_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16s_x_Slot_n2_s0_ldst_encode, Opcode_ivp_lvn_2x16s_x_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16s_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lvn_2x16s_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16s_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvn_2x16s_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16s_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16s_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lvn_2x16s_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16s_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lvn_2x16s_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16s_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lvn_2x16s_xp_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16st_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16st_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvn_2x16st_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16st_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16st_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16st_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvn_2x16st_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16st_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16st_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16st_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvn_2x16st_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16st_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16st_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16st_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvn_2x16st_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16st_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16u_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16u_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16u_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16u_i_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svn_2x16u_i_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16ut_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16ut_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16ut_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16ut_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16u_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16u_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16u_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svn_2x16u_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16ut_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16ut_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16ut_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16ut_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16u_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16u_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16u_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16u_x_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svn_2x16u_x_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16ut_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16ut_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16ut_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16ut_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16u_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16u_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svn_2x16u_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16ut_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16ut_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16ut_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16ut_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16s_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16s_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16s_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16s_i_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svn_2x16s_i_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16st_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16st_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16st_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16st_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16s_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16s_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16s_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svn_2x16s_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16st_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16st_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16st_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16st_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16s_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16s_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16s_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16s_x_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svn_2x16s_x_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16st_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16st_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16st_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16st_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16s_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16s_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svn_2x16s_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16st_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16st_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16st_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16st_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lan_2x16s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lan_2x16s_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lan_2x16s_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lan_2x16s_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lan_2x16s_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lan_2x16s_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lan_2x16s_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lan_2x16s_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lan_2x16s_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lan_2x16s_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lan_2x16s_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lan_2x16s_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lan_2x16s_ip_Slot_n2_s1_ld_encode, Opcode_ivp_lan_2x16s_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lan_2x16u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lan_2x16u_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lan_2x16u_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lan_2x16u_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lan_2x16u_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lan_2x16u_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lan_2x16u_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lan_2x16u_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lan_2x16u_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lan_2x16u_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lan_2x16u_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lan_2x16u_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lan_2x16u_ip_Slot_n2_s1_ld_encode, Opcode_ivp_lan_2x16u_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lan_2x16u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lan_2x16u_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lan_2x16u_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lan_2x16u_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lan_2x16u_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lan_2x16u_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lan_2x16u_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lan_2x16u_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lan_2x16u_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lan_2x16u_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lan_2x16u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lan_2x16u_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lan_2x16u_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lan_2x16u_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lan_2x16s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lan_2x16s_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lan_2x16s_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lan_2x16s_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lan_2x16s_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lan_2x16s_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lan_2x16s_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lan_2x16s_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lan_2x16s_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lan_2x16s_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lan_2x16s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lan_2x16s_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lan_2x16s_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lan_2x16s_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_san_2x16u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_san_2x16u_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_san_2x16u_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_san_2x16u_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_san_2x16u_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_san_2x16u_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_san_2x16u_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_san_2x16u_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_san_2x16s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_san_2x16s_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_san_2x16s_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_san_2x16s_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_san_2x16s_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_san_2x16s_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_san_2x16s_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_san_2x16s_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lavn_2x16s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lavn_2x16s_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lavn_2x16s_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lavn_2x16s_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lavn_2x16s_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lavn_2x16s_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lavn_2x16s_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lavn_2x16s_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lavn_2x16s_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lavn_2x16s_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lavn_2x16s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lavn_2x16s_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lavn_2x16s_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lavn_2x16s_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lavn_2x16u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lavn_2x16u_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lavn_2x16u_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lavn_2x16u_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lavn_2x16u_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lavn_2x16u_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lavn_2x16u_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lavn_2x16u_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lavn_2x16u_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lavn_2x16u_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lavn_2x16u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lavn_2x16u_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lavn_2x16u_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lavn_2x16u_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_savn_2x16u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_savn_2x16u_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_savn_2x16u_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_savn_2x16u_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_savn_2x16u_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_savn_2x16u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_savn_2x16u_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_savn_2x16u_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_savn_2x16s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_savn_2x16s_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_savn_2x16s_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_savn_2x16s_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_savn_2x16s_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_savn_2x16s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_savn_2x16s_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_savn_2x16s_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsn_2x16s_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsn_2x16s_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsn_2x16s_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsn_2x16s_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsn_2x16s_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsn_2x16s_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsn_2x16s_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsn_2x16s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsn_2x16s_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsn_2x16s_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsn_2x16s_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsn_2x16s_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsn_2x16s_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsn_2x16s_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsn_2x16s_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsn_2x16s_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsn_2x16s_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsn_2x16s_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsn_2x16s_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsn_2x16s_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsn_2x16s_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsn_2x16s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsn_2x16s_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsn_2x16s_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsn_2x16s_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsn_2x16s_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsn_2x16s_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsn_2x16s_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssn_2x16s_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssn_2x16s_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssn_2x16s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssn_2x16s_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssn_2x16s_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssn_2x16s_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssn_2x16s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssn_2x16s_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsn_2x32_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsn_2x32_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsn_2x32_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsn_2x32_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsn_2x32_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsn_2x32_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsn_2x32_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsn_2x32_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsn_2x32_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsn_2x32_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsn_2x32_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsn_2x32_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsn_2x32_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsn_2x32_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsn_2x32_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsn_2x32_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsn_2x32_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsn_2x32_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsn_2x32_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsn_2x32_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsn_2x32_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsn_2x32_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsn_2x32_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsn_2x32_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsn_2x32_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsn_2x32_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsn_2x32_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsn_2x32_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssn_2x32_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssn_2x32_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssn_2x32_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssn_2x32_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssn_2x32_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssn_2x32_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssn_2x32_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssn_2x32_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_bmaxunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxunx16_Slot_f0_s3_alu_encode, Opcode_ivp_bmaxunx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bmaxunx16_Slot_f1_s2_mul_encode, Opcode_ivp_bmaxunx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bmaxunx16_Slot_f2_s2_mul_encode, Opcode_ivp_bmaxunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bmaxunx16_Slot_f3_s3_alu_encode, Opcode_ivp_bmaxunx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bmaxunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxunx16_Slot_f11_s3_alu_encode, Opcode_ivp_bmaxunx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bminunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bminunx16_Slot_f0_s3_alu_encode, Opcode_ivp_bminunx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bminunx16_Slot_f1_s2_mul_encode, Opcode_ivp_bminunx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bminunx16_Slot_f2_s2_mul_encode, Opcode_ivp_bminunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bminunx16_Slot_f3_s3_alu_encode, Opcode_ivp_bminunx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bminunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminunx16_Slot_f11_s3_alu_encode, Opcode_ivp_bminunx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rbminunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rbminunx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbminunx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbminunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbminunx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rbminunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rbminunx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rbminunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rbmaxunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rbmaxunx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbmaxunx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbmaxunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbmaxunx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rbmaxunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rbmaxunx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rbmaxunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bmax2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bmax2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_bmax2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bmax2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_bmax2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bmax2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_bmax2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bmax2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_bmax2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bmax2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmax2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_bmax2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmax2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bmin2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bmin2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_bmin2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bmin2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_bmin2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bmin2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_bmin2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bmin2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_bmin2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bmin2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmin2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_bmin2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmin2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bmaxu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxu2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_bmaxu2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bmaxu2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_bmaxu2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bmaxu2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_bmaxu2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bmaxu2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_bmaxu2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bmaxu2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxu2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_bmaxu2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxu2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bminu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bminu2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_bminu2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bminu2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_bminu2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bminu2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_bminu2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bminu2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_bminu2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bminu2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminu2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_bminu2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminu2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bmaxn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_bmaxn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bmaxn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_bmaxn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bmaxn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_bmaxn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bmaxn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_bmaxn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bmaxn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxn_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_bmaxn_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bminn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bminn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_bminn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bminn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_bminn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bminn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_bminn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bminn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_bminn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bminn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminn_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_bminn_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bmaxun_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxun_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_bmaxun_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bmaxun_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_bmaxun_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bmaxun_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_bmaxun_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bmaxun_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_bmaxun_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bmaxun_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxun_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_bmaxun_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxun_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bminun_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bminun_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_bminun_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bminun_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_bminun_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bminun_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_bminun_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bminun_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_bminun_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bminun_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminun_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_bminun_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminun_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_addn_2x32t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_addn_2x32t_Slot_f0_s3_alu_encode, Opcode_ivp_addn_2x32t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_addn_2x32t_Slot_f1_s2_mul_encode, Opcode_ivp_addn_2x32t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_addn_2x32t_Slot_f2_s2_mul_encode, Opcode_ivp_addn_2x32t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_addn_2x32t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_addn_2x32t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addn_2x32t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addn_2x32t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_subn_2x32t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_subn_2x32t_Slot_f0_s3_alu_encode, Opcode_ivp_subn_2x32t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_subn_2x32t_Slot_f1_s2_mul_encode, Opcode_ivp_subn_2x32t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_subn_2x32t_Slot_f2_s2_mul_encode, Opcode_ivp_subn_2x32t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_subn_2x32t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_subn_2x32t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subn_2x32t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subn_2x32t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_add2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_add2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_add2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_add2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_add2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_add2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_add2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_add2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_add2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_add2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_add2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_add2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_add2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sub2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sub2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_sub2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_sub2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_sub2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_sub2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_sub2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_sub2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_sub2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_sub2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sub2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_sub2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sub2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_neg2nx8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_neg2nx8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_neg2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_neg2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_neg2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_neg2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_neg2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_neg2nx8_Slot_f2_s3_alu_encode, Opcode_ivp_neg2nx8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_neg2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_neg2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_neg2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_neg2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_neg2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_neg2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_min2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_min2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_min2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_min2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_min2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_min2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_min2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_min2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_min2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_min2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_min2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_min2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_min2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_minu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_minu2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_minu2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_minu2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_minu2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_minu2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_minu2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_minu2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_minu2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_minu2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minu2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_minu2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minu2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_max2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_max2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_max2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_max2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_max2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_max2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_max2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_max2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_max2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_max2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_max2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_max2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_max2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_maxu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_maxu2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_maxu2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_maxu2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_maxu2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_maxu2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_maxu2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_maxu2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_maxu2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_maxu2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxu2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_maxu2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxu2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_lt2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_lt2nx8_Slot_f0_s2_mul_encode, Opcode_ivp_lt2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_lt2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_lt2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_lt2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_lt2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_lt2nx8_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_lt2nx8_Slot_f3_s2_mul_encode, Opcode_ivp_lt2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_lt2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_lt2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_lt2nx8_Slot_f11_s2_mul_encode, Opcode_ivp_lt2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_lt2nx8_Slot_n1_s2_mul_encode, Opcode_ivp_lt2nx8_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lt2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_le2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_le2nx8_Slot_f0_s2_mul_encode, Opcode_ivp_le2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_le2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_le2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_le2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_le2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_le2nx8_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_le2nx8_Slot_f3_s2_mul_encode, Opcode_ivp_le2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_le2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_le2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_le2nx8_Slot_f11_s2_mul_encode, Opcode_ivp_le2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_le2nx8_Slot_n1_s2_mul_encode, Opcode_ivp_le2nx8_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_le2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_eq2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_eq2nx8_Slot_f0_s2_mul_encode, Opcode_ivp_eq2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_eq2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_eq2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_eq2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_eq2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_eq2nx8_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_eq2nx8_Slot_f3_s2_mul_encode, Opcode_ivp_eq2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_eq2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_eq2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_eq2nx8_Slot_f11_s2_mul_encode, Opcode_ivp_eq2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_eq2nx8_Slot_n1_s2_mul_encode, Opcode_ivp_eq2nx8_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_eq2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_neq2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_neq2nx8_Slot_f0_s2_mul_encode, Opcode_ivp_neq2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_neq2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_neq2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_neq2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_neq2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_neq2nx8_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_neq2nx8_Slot_f3_s2_mul_encode, Opcode_ivp_neq2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_neq2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_neq2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_neq2nx8_Slot_f11_s2_mul_encode, Opcode_ivp_neq2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_neq2nx8_Slot_n1_s2_mul_encode, Opcode_ivp_neq2nx8_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_neq2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_ltu2nx8_Slot_f0_s2_mul_encode, Opcode_ivp_ltu2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_ltu2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_ltu2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_ltu2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_ltu2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_ltu2nx8_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_ltu2nx8_Slot_f3_s2_mul_encode, Opcode_ivp_ltu2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_ltu2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_ltu2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltu2nx8_Slot_f11_s2_mul_encode, Opcode_ivp_ltu2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_ltu2nx8_Slot_n1_s2_mul_encode, Opcode_ivp_ltu2nx8_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_ltu2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_leu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_leu2nx8_Slot_f0_s2_mul_encode, Opcode_ivp_leu2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_leu2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_leu2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_leu2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_leu2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_leu2nx8_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_leu2nx8_Slot_f3_s2_mul_encode, Opcode_ivp_leu2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_leu2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_leu2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_leu2nx8_Slot_f11_s2_mul_encode, Opcode_ivp_leu2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_leu2nx8_Slot_n1_s2_mul_encode, Opcode_ivp_leu2nx8_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_leu2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_add2nx8t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_add2nx8t_Slot_f0_s3_alu_encode, Opcode_ivp_add2nx8t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_add2nx8t_Slot_f1_s2_mul_encode, Opcode_ivp_add2nx8t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_add2nx8t_Slot_f2_s2_mul_encode, Opcode_ivp_add2nx8t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_add2nx8t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_add2nx8t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_add2nx8t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_add2nx8t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sub2nx8t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sub2nx8t_Slot_f0_s3_alu_encode, Opcode_ivp_sub2nx8t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_sub2nx8t_Slot_f1_s2_mul_encode, Opcode_ivp_sub2nx8t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_sub2nx8t_Slot_f2_s2_mul_encode, Opcode_ivp_sub2nx8t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_sub2nx8t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_sub2nx8t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sub2nx8t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sub2nx8t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_selnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_selnx16t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_selnx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_selnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_selnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_seln_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_seln_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_seln_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_seln_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_seln_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_seln_2x32t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_seln_2x32t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_seln_2x32t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_seln_2x32t_Slot_f2_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_seln_2x32t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_shfln_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_shfln_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_shfln_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_shfln_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_shfln_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sllin_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sllin_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_sllin_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_sllin_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_sllin_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_sllin_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sllin_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sllin_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_slsin_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_slsin_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsin_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsin_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsin_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_slsin_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slsin_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slsin_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srain_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_srain_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_srain_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_srain_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_srain_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srain_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srain_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srain_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srlin_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_srlin_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_srlin_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_srlin_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_srlin_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srlin_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srlin_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srlin_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_slln_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_slln_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_slln_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_slln_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_slln_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_slln_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slln_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slln_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srln_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_srln_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_srln_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_srln_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_srln_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srln_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srln_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srln_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_slan_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_slan_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_slan_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_slan_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_slan_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_slan_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slan_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slan_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sran_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sran_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_sran_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_sran_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_sran_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_sran_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sran_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sran_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_slsn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_slsn_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsn_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_slsn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slsn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slsn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srsn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_srsn_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_srsn_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_srsn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_srsn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srsn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srsn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srsn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddn_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddn_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rmaxn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxn_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxn_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rmaxn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rminn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rminn_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminn_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rminn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rmaxun_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxun_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxun_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxun_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxun_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rmaxun_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxun_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxun_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rminun_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rminun_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminun_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminun_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminun_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rminun_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminun_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminun_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddn_2x32t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddn_2x32t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddn_2x32t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddn_2x32t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddn_2x32t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddn_2x32t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddn_2x32t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddn_2x32t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_abs2nx8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_abs2nx8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_abs2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_abs2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_abs2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_abs2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_abs2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_abs2nx8_Slot_f2_s3_alu_encode, Opcode_ivp_abs2nx8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_abs2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_abs2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_abs2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abs2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_abs2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abs2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_absn_2x32_encode_fns[] = { + 0, 0, 0, Opcode_ivp_absn_2x32_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_absn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_absn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_absn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_absn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_absn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_absn_2x32_Slot_f2_s3_alu_encode, Opcode_ivp_absn_2x32_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_absn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_absn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_absn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_absn_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_absn_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_absn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsgnsnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsgnsnx16_Slot_f0_s3_alu_encode, Opcode_ivp_mulsgnsnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_mulsgnsnx16_Slot_f1_s2_mul_encode, Opcode_ivp_mulsgnsnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_mulsgnsnx16_Slot_f2_s2_mul_encode, Opcode_ivp_mulsgnsnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_mulsgnsnx16_Slot_f3_s3_alu_encode, Opcode_ivp_mulsgnsnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_mulsgnsnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsgnsnx16_Slot_f11_s3_alu_encode, Opcode_ivp_mulsgnsnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsgnsnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rotri2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rotri2nx8_Slot_f0_s3_alu_encode, 0, 0, Opcode_ivp_rotri2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_rotri2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_rotri2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_rotri2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotri2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rotri2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotri2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotri2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rotrinx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrinx16_Slot_f0_s3_alu_encode, 0, 0, Opcode_ivp_rotrinx16_Slot_f1_s2_mul_encode, Opcode_ivp_rotrinx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_rotrinx16_Slot_f2_s2_mul_encode, Opcode_ivp_rotrinx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrinx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rotrinx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrinx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrinx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rotrin_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrin_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrin_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrin_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrin_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rotrin_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrin_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrin_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rotrnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rotrnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rotrn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrn_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrn_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rotrn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_addn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_addn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_addn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_addn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_addn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_addn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_addn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_addn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_addn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_addn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addn_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_addn_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_subn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_subn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_subn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_subn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_subn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_subn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_subn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_subn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_subn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_subn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subn_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_subn_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_negn_2x32_encode_fns[] = { + 0, 0, 0, Opcode_ivp_negn_2x32_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_negn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_negn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_negn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_negn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_negn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_negn_2x32_Slot_f2_s3_alu_encode, Opcode_ivp_negn_2x32_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_negn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_negn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_negn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negn_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_negn_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_minn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_minn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_minn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_minn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_minn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_minn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_minn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_minn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_minn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_minn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minn_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_minn_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_minun_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_minun_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_minun_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_minun_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_minun_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_minun_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_minun_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_minun_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_minun_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_minun_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minun_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_minun_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minun_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_maxn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_maxn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_maxn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_maxn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_maxn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_maxn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_maxn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_maxn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_maxn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_maxn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxn_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_maxn_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_maxun_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_maxun_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_maxun_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_maxun_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_maxun_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_maxun_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_maxun_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_maxun_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_maxun_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_maxun_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxun_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_maxun_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxun_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsgnn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsgnn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_mulsgnn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_mulsgnn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_mulsgnn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_mulsgnn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_mulsgnn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_mulsgnn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_mulsgnn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_mulsgnn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsgnn_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_mulsgnn_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsgnn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_nsan_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_nsan_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsan_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsan_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsan_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_nsan_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_nsan_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_nsan_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_nsaun_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_nsaun_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsaun_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsaun_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsaun_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_nsaun_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_nsaun_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_nsaun_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_ltn_2x32_Slot_f0_s2_mul_encode, Opcode_ivp_ltn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_ltn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_ltn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_ltn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_ltn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_ltn_2x32_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_ltn_2x32_Slot_f3_s2_mul_encode, Opcode_ivp_ltn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_ltn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_ltn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltn_2x32_Slot_f11_s2_mul_encode, Opcode_ivp_ltn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_ltn_2x32_Slot_n1_s2_mul_encode, Opcode_ivp_ltn_2x32_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_ltn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_len_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_len_2x32_Slot_f0_s2_mul_encode, Opcode_ivp_len_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_len_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_len_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_len_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_len_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_len_2x32_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_len_2x32_Slot_f3_s2_mul_encode, Opcode_ivp_len_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_len_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_len_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_len_2x32_Slot_f11_s2_mul_encode, Opcode_ivp_len_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_len_2x32_Slot_n1_s2_mul_encode, Opcode_ivp_len_2x32_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_len_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_eqn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_eqn_2x32_Slot_f0_s2_mul_encode, Opcode_ivp_eqn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_eqn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_eqn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_eqn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_eqn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_eqn_2x32_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_eqn_2x32_Slot_f3_s2_mul_encode, Opcode_ivp_eqn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_eqn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_eqn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_eqn_2x32_Slot_f11_s2_mul_encode, Opcode_ivp_eqn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_eqn_2x32_Slot_n1_s2_mul_encode, Opcode_ivp_eqn_2x32_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_eqn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_neqn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_neqn_2x32_Slot_f0_s2_mul_encode, Opcode_ivp_neqn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_neqn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_neqn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_neqn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_neqn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_neqn_2x32_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_neqn_2x32_Slot_f3_s2_mul_encode, Opcode_ivp_neqn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_neqn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_neqn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_neqn_2x32_Slot_f11_s2_mul_encode, Opcode_ivp_neqn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_neqn_2x32_Slot_n1_s2_mul_encode, Opcode_ivp_neqn_2x32_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_neqn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltun_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_ltun_2x32_Slot_f0_s2_mul_encode, Opcode_ivp_ltun_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_ltun_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_ltun_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_ltun_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_ltun_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_ltun_2x32_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_ltun_2x32_Slot_f3_s2_mul_encode, Opcode_ivp_ltun_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_ltun_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_ltun_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltun_2x32_Slot_f11_s2_mul_encode, Opcode_ivp_ltun_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_ltun_2x32_Slot_n1_s2_mul_encode, Opcode_ivp_ltun_2x32_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_ltun_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_leun_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_leun_2x32_Slot_f0_s2_mul_encode, Opcode_ivp_leun_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_leun_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_leun_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_leun_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_leun_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_leun_2x32_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_leun_2x32_Slot_f3_s2_mul_encode, Opcode_ivp_leun_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_leun_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_leun_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_leun_2x32_Slot_f11_s2_mul_encode, Opcode_ivp_leun_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_leun_2x32_Slot_n1_s2_mul_encode, Opcode_ivp_leun_2x32_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_leun_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_lat2nx8_xp_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_lat2nx8_xp_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_lat2nx8_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lat2nx8_xp_Slot_f2_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lat2nx8_xp_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluu2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluu2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluu2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluu2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluu2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluu2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluua2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluua2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluua2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluua2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluua2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluua2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluua2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulus2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulus2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulus2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulus2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusa2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusa2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusa2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusa2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusa2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusa2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusa2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muli2nx8x16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muli2nx8x16_Slot_f0_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muli2nx8x16_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muli2nx8x16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulai2nx8x16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulai2nx8x16_Slot_f0_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulai2nx8x16_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulai2nx8x16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusi2nx8x16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusi2nx8x16_Slot_f0_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusi2nx8x16_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusi2nx8x16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusai2nx8x16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusai2nx8x16_Slot_f0_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusai2nx8x16_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusai2nx8x16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muli2nr8x16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muli2nr8x16_Slot_f0_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muli2nr8x16_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muli2nr8x16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulai2nr8x16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulai2nr8x16_Slot_f0_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulai2nr8x16_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulai2nr8x16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusi2nr8x16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusi2nr8x16_Slot_f0_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusi2nr8x16_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusi2nr8x16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusai2nr8x16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusai2nr8x16_Slot_f0_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusai2nr8x16_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusai2nr8x16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusa2n8xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusa2n8xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusa2n8xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusa2n8xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusa2n8xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusa2n8xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusa2n8xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulus2n8xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulus2n8xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus2n8xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus2n8xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus2n8xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulus2n8xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulus2n8xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mula2n8xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mula2n8xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mula2n8xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mula2n8xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mula2n8xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mula2n8xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mula2n8xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mul2n8xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mul2n8xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul2n8xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul2n8xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul2n8xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mul2n8xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mul2n8xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_dsel2nx8i_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_dsel2nx8i_Slot_f0_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_dsel2nx8i_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_dsel2nx8i_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_dsel2nx8i_h_Slot_f0_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_dsel2nx8i_h_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_dselnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_dselnx16_Slot_f0_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_dselnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_dselnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_dselnx16t_Slot_f0_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_dselnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_injbi2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_injbi2nx8_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_injbi2nx8_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_injbi2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_injbi2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_injbi2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_extbi2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_extbi2nx8_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_extbi2nx8_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_extbi2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_extbi2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_extbi2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extbi2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extbi2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_movva32_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movva32_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movva32_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movva32_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movva32_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movva32_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movva32_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movav32_encode_fns[] = { + 0, 0, 0, Opcode_ivp_movav32_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_movav32_Slot_f0_s3_alu_encode, Opcode_ivp_movav32_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_movav32_Slot_f1_s3_alu_encode, Opcode_ivp_movav32_Slot_f2_s0_ldst_encode, 0, 0, Opcode_ivp_movav32_Slot_f2_s3_alu_encode, Opcode_ivp_movav32_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_movav32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_movav32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movav32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movav32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_movww_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_movww_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_movww_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_movww_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_movww_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movww_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_movww_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ls2nx8_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ls2nx8_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ls2nx8_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_ls2nx8_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ls2nx8_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_ls2nx8_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_ls2nx8_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ls2nx8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ls2nx8_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ls2nx8_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_ls2nx8_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ls2nx8_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_ls2nx8_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_ls2nx8_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ls2nx8_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ls2nx8_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ls2nx8_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_ls2nx8_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ls2nx8_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_ls2nx8_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_ls2nx8_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ls2nx8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ls2nx8_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ls2nx8_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_ls2nx8_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ls2nx8_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_ls2nx8_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_ls2nx8_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ss2nx8_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ss2nx8_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ss2nx8_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ss2nx8_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ss2nx8_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ss2nx8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ss2nx8_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ss2nx8_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ss2nx8_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ss2nx8_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ss2nx8_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ss2nx8_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ss2nx8_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ss2nx8_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ss2nx8_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ss2nx8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ss2nx8_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ss2nx8_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ss2nx8_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ss2nx8_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lanx8s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lanx8s_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lanx8s_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lanx8s_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lanx8s_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lanx8s_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lanx8s_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lanx8s_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lanx8s_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lanx8s_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lanx8s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lanx8s_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lanx8s_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lanx8s_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lanx8u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lanx8u_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lanx8u_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lanx8u_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lanx8u_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lanx8u_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lanx8u_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lanx8u_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lanx8u_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lanx8u_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lanx8u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lanx8u_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lanx8u_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lanx8u_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_la2nx8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_la2nx8_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_la2nx8_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_la2nx8_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_la2nx8_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_la2nx8_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_la2nx8_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_la2nx8_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_la2nx8_xp_Slot_f4_s0_ld_encode, Opcode_ivp_la2nx8_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_la2nx8_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_la2nx8_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_la2nx8_xp_Slot_n2_s1_ld_encode, Opcode_ivp_la2nx8_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_abssubu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_abssubu2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_abssubu2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_abssubu2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_abssubu2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_abssubu2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_abssubu2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_abssubu2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_abssubu2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_abssubu2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssubu2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_abssubu2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssubu2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_abssub2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_abssub2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_abssub2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_abssub2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_abssub2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_abssub2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_abssub2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_abssub2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_abssub2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_abssub2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssub2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_abssub2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssub2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_movvint8_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movvint8_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movvint8_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movvint8_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movvint8_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movvint8_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movvint8_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movva8_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movva8_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movva8_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movva8_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movva8_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movva8_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movva8_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movavu8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_movavu8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_movavu8_Slot_f0_s3_alu_encode, Opcode_ivp_movavu8_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_movavu8_Slot_f1_s3_alu_encode, Opcode_ivp_movavu8_Slot_f2_s0_ldst_encode, 0, 0, Opcode_ivp_movavu8_Slot_f2_s3_alu_encode, Opcode_ivp_movavu8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_movavu8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_movavu8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movavu8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movavu8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_slli2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_slli2nx8_Slot_f0_s3_alu_encode, 0, 0, Opcode_ivp_slli2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_slli2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_slli2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_slli2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_slli2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_slli2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slli2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slli2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srai2nx8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_srai2nx8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_srai2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_srai2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_srai2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_srai2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_srai2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_srai2nx8_Slot_f2_s3_alu_encode, Opcode_ivp_srai2nx8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_srai2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srai2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srai2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srai2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srli2nx8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_srli2nx8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_srli2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_srli2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_srli2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_srli2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_srli2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_srli2nx8_Slot_f2_s3_alu_encode, Opcode_ivp_srli2nx8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_srli2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srli2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srli2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srli2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_packl2nx24_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packl2nx24_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packl2nx24_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packl2nx24_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packl2nx24_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packl2nx24_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packl2nx24_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvr2nx24_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvr2nx24_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvr2nx24_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvr2nx24_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvr2nx24_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvr2nx24_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvr2nx24_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvru2nx24_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvru2nx24_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvru2nx24_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvru2nx24_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvru2nx24_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvru2nx24_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvru2nx24_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packlnx48_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packlnx48_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packlnx48_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packlnx48_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packlnx48_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packlnx48_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packlnx48_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packl2nx24_1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packl2nx24_1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packl2nx24_1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packl2nx24_1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packl2nx24_1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packl2nx24_1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packl2nx24_1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvr2nx24_0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvr2nx24_0_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvr2nx24_0_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvr2nx24_0_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvr2nx24_0_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvr2nx24_0_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvr2nx24_0_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvr2nx24_1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvr2nx24_1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvr2nx24_1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvr2nx24_1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvr2nx24_1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvr2nx24_1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvr2nx24_1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvru2nx24_0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvru2nx24_0_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvru2nx24_0_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvru2nx24_0_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvru2nx24_0_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvru2nx24_0_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvru2nx24_0_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvru2nx24_1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvru2nx24_1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvru2nx24_1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvru2nx24_1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvru2nx24_1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvru2nx24_1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvru2nx24_1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnr2nx24_0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnr2nx24_0_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnr2nx24_0_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnr2nx24_0_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnr2nx24_0_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnr2nx24_0_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnr2nx24_0_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnr2nx24_1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnr2nx24_1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnr2nx24_1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnr2nx24_1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnr2nx24_1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnr2nx24_1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnr2nx24_1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packmnx48_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packmnx48_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packmnx48_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packmnx48_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packmnx48_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packmnx48_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packmnx48_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnx48_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnx48_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnx48_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnx48_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnx48_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnx48_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnx48_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_unpks2nx8_0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_unpks2nx8_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_unpks2nx8_0_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_unpks2nx8_1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_unpks2nx8_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_unpks2nx8_1_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_unpksnx16_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_unpksnx16_l_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_unpksnx16_l_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_unpksnx16_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_unpksnx16_h_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_unpksnx16_h_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sel2nx8i_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8i_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_sel2nx8i_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_sel2nx8i_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_sel2nx8i_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_sel2nx8i_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8i_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8i_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sel2nx8i_s0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8i_s0_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8i_s0_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sel2nx8i_s2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8i_s2_Slot_f1_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sel2nx8i_s4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8i_s4_Slot_f3_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_shfl2nx8i_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_shfl2nx8i_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_shfl2nx8i_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_shfl2nx8i_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_shfl2nx8i_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_shfl2nx8i_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_shfl2nx8i_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_shfl2nx8i_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_shfl2nx8i_s0_encode_fns[] = { + 0, 0, 0, Opcode_ivp_shfl2nx8i_s0_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_shfl2nx8i_s0_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_shfl2nx8i_s0_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_shfl2nx8i_s0_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_shfl2nx8i_s0_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_shfl2nx8i_s0_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_shfl2nx8i_s2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_shfl2nx8i_s2_Slot_f1_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_shfl2nx8i_s4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_shfl2nx8i_s4_Slot_f3_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sel2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_sel2nx8_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_sel2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_shfl2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_shfl2nx8_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_shfl2nx8_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_shfl2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_shfl2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sel2nx8t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_sel2nx8t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_sel2nx8t_Slot_f2_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sqzn_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_sqzn_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_sqzn_Slot_f1_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sqzn_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_sqzn_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sqzn_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_unsqzn_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_unsqzn_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_unsqzn_Slot_f1_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_unsqzn_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_unsqzn_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_unsqzn_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulnx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulnx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulnx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulnx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulnx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulnx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulanx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulanx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulanx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulanx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulanx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulanx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluunx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluunx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluunx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluunx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluunx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluunx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluunx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluuanx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluuanx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuanx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuanx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuanx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluuanx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluuanx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusnx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusnx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusnx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusnx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusnx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusnx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusanx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusanx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusanx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusanx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusanx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusanx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusanx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mul2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mul2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mul2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mul2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mula2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mula2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mula2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mula2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mula2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mula2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mula2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addw2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addw2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addw2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addw2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addw2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addw2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_addw2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwa2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwa2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwa2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwa2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwa2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwa2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_addwa2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addws2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addws2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addws2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addws2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addws2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addws2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_addws2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwu2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwu2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwu2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwu2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwu2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_addwu2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwua2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwua2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwua2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwua2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwua2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwua2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_addwua2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwus2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwus2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwus2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwus2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwus2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwus2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_addwus2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divn_2x32x16s_4step0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divn_2x32x16s_4step0_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divn_2x32x16s_4step_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divn_2x32x16s_4step_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divn_2x32x16s_4stepn_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divn_2x32x16s_4stepn_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divn_2x32x16u_4step0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divn_2x32x16u_4step0_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divn_2x32x16u_4step_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divn_2x32x16u_4step_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divn_2x32x16u_4stepn_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divn_2x32x16u_4stepn_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divnx16s_4step0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divnx16s_4step0_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divnx16s_4step_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divnx16s_4step_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divnx16s_4stepn_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divnx16s_4stepn_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divnx16u_4step0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divnx16u_4step0_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divnx16u_4step_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divnx16u_4step_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divnx16u_4stepn_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divnx16u_4stepn_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divnx16sq_4step0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divnx16sq_4step0_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divnx16q_4step0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divnx16q_4step0_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsnx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsnx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsnx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsnx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsnx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsnx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluusnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluusnx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluusnx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluusnx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluusnx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluusnx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluusnx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulussnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulussnx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulussnx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulussnx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulussnx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulussnx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulussnx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muln_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muln_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muln_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muln_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muln_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muln_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muln_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluun_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluun_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluun_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluun_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluun_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluun_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluun_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusn_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsun_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muln_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muln_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muln_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muln_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muln_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muln_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muln_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluun_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluun_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluun_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluun_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluun_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluun_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluun_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsun_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulhn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulhn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulhn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulhn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulhn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulhn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulhn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluuhn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluuhn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuhn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuhn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuhn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluuhn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluuhn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulushn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulushn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulushn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulushn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulushn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulushn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulushn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsuhn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsuhn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuhn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuhn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuhn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsuhn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsuhn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulan_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulan_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulan_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulan_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulan_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulan_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulan_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluuan_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusan_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsuan_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulahn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulahn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulahn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulahn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulahn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulahn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulahn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluuahn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluuahn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuahn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuahn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuahn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluuahn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluuahn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusahn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusahn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusahn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusahn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusahn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusahn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusahn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsuahn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsuahn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuahn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuahn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuahn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsuahn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsuahn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulan_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulan_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulan_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulan_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulan_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulan_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulan_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluuan_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusan_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsuan_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulshn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulshn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulshn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulshn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulshn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulshn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulshn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluushn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluushn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluushn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluushn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluushn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluushn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluushn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusshn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusshn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusshn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusshn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusshn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusshn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusshn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsushn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsushn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsushn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsushn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsushn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsushn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsushn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsn_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluusn_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulussn_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsusn_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluusn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulussn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsusn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packln_2x96_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packln_2x96_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packln_2x96_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packln_2x96_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packln_2x96_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packln_2x96_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packln_2x96_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packhn_2x64w_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packhn_2x64w_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packhn_2x64w_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packhn_2x64w_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packhn_2x64w_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packhn_2x64w_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packhn_2x64w_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrn_2x64w_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrn_2x64w_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrn_2x64w_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrn_2x64w_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrn_2x64w_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrn_2x64w_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrn_2x64w_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnrn_2x64w_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnrn_2x64w_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrn_2x64w_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrn_2x64w_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrn_2x64w_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnrn_2x64w_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnrn_2x64w_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnx48_0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnx48_0_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnx48_0_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnx48_0_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnx48_0_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnx48_0_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnx48_0_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnx48_1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnx48_1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnx48_1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnx48_1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnx48_1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnx48_1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnx48_1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnrnx48_0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnrnx48_0_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrnx48_0_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrnx48_0_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrnx48_0_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnrnx48_0_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnrnx48_0_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnrnx48_1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnrnx48_1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrnx48_1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrnx48_1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrnx48_1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnrnx48_1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnrnx48_1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnrnx48_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnrnx48_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrnx48_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrnx48_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrnx48_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnrnx48_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnrnx48_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnr2nx24_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnr2nx24_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnr2nx24_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnr2nx24_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnr2nx24_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnr2nx24_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnr2nx24_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_l2a4nx8_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_l2a4nx8_ip_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_l2au2nx8_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_l2au2nx8_ip_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_l2u2nx8_xp_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_l2u2nx8_xp_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_avgu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_avgu2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_avgu2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_avgu2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_avgu2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_avgu2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_avgu2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_avgu2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_avgu2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgu2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgu2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_avgru2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_avgru2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_avgru2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_avgru2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_avgru2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_avgru2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_avgru2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_avgru2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_avgru2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgru2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgru2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_radd2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_radd2nx8_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_radd2nx8_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_radd2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_radd2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_radd2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_radd2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_radd2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_radd2nx8t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_radd2nx8t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_radd2nx8t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_radd2nx8t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_radd2nx8t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_radd2nx8t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_radd2nx8t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_radd2nx8t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddunx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddunx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddunx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddunx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddunx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddunx16t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddunx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddunx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddunx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddunx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddunx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddunx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddu2nx8_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddu2nx8_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddu2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddu2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddu2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddu2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddu2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddu2nx8t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddu2nx8t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddu2nx8t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddu2nx8t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddu2nx8t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddu2nx8t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddu2nx8t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddu2nx8t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltrs2n_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ltrs2n_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrs2n_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrs2n_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrs2n_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ltrs2n_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrs2n_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrs2n_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltrsn_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ltrsn_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrsn_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrsn_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrsn_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ltrsn_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrsn_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrsn_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltrsn_2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ltrsn_2_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrsn_2_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrsn_2_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrsn_2_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ltrsn_2_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrsn_2_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrsn_2_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_seq2nx8_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_seq2nx8_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_seq2nx8_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_seq2nx8_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_seq2nx8_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_seq2nx8_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_seq2nx8_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_seqn_2x32_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_seqn_2x32_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_seqn_2x32_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_seqn_2x32_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_seqn_2x32_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_seqn_2x32_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_seqn_2x32_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_extrn_2x32_encode_fns[] = { + 0, 0, 0, Opcode_ivp_extrn_2x32_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_extrn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_extrn_2x32_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_extrn_2x32_Slot_f1_s3_alu_encode, Opcode_ivp_extrn_2x32_Slot_f2_s0_ldst_encode, 0, 0, Opcode_ivp_extrn_2x32_Slot_f2_s3_alu_encode, Opcode_ivp_extrn_2x32_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_extrn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_extrn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extrn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extrn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_unpku2nx8_0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_unpku2nx8_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_unpku2nx8_0_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_unpku2nx8_1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_unpku2nx8_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_unpku2nx8_1_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_baddnormnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_baddnormnx16_Slot_f0_s3_alu_encode, Opcode_ivp_baddnormnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_baddnormnx16_Slot_f1_s2_mul_encode, Opcode_ivp_baddnormnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_baddnormnx16_Slot_f2_s2_mul_encode, Opcode_ivp_baddnormnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_baddnormnx16_Slot_f3_s3_alu_encode, Opcode_ivp_baddnormnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_baddnormnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_baddnormnx16_Slot_f11_s3_alu_encode, Opcode_ivp_baddnormnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_baddnormnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bsubnormnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bsubnormnx16_Slot_f0_s3_alu_encode, Opcode_ivp_bsubnormnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bsubnormnx16_Slot_f1_s2_mul_encode, Opcode_ivp_bsubnormnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bsubnormnx16_Slot_f2_s2_mul_encode, Opcode_ivp_bsubnormnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bsubnormnx16_Slot_f3_s3_alu_encode, Opcode_ivp_bsubnormnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bsubnormnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bsubnormnx16_Slot_f11_s3_alu_encode, Opcode_ivp_bsubnormnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bsubnormnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddsnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddsnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddsnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddsnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddsnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddsnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddsnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddsnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddsnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddsnx16t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddsnx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddsnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddsnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddsnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddsnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddsnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_ornotb_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ornotb_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ornotb_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ornotb_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ornotb_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ornotb_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ornotb_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_extr2nx8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_extr2nx8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_extr2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_extr2nx8_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_extr2nx8_Slot_f1_s3_alu_encode, Opcode_ivp_extr2nx8_Slot_f2_s0_ldst_encode, 0, 0, Opcode_ivp_extr2nx8_Slot_f2_s3_alu_encode, Opcode_ivp_extr2nx8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_extr2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_extr2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extr2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extr2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_extrvrn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_extrvrn_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_extrvrn_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_extrvrn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_extrvrn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_extrvrn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_extrvrn_2x32_Slot_f11_s2_mul_encode, Opcode_ivp_extrvrn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_extrvrn_2x32_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movav8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_movav8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_movav8_Slot_f0_s3_alu_encode, Opcode_ivp_movav8_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_movav8_Slot_f1_s3_alu_encode, Opcode_ivp_movav8_Slot_f2_s0_ldst_encode, 0, 0, Opcode_ivp_movav8_Slot_f2_s3_alu_encode, Opcode_ivp_movav8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_movav8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_movav8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movav8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movav8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulpn16xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulpn16xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulpn16xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulpn16xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulpn16xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulpn16xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulpn16xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulpan16xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulpan16xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulpan16xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulpan16xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulpan16xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulpan16xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulpan16xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluspn16xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluspn16xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluspn16xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluspn16xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluspn16xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluspn16xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluspn16xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluspan16xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluspan16xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluspan16xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluspan16xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluspan16xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluspan16xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluspan16xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulp2n8xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulp2n8xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulp2n8xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulp2n8xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulp2n8xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulp2n8xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulp2n8xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulpa2n8xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulpa2n8xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulpa2n8xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulpa2n8xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulpa2n8xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulpa2n8xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulpa2n8xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusp2n8xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusp2n8xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusp2n8xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusp2n8xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusp2n8xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusp2n8xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusp2n8xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluspa2n8xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluspa2n8xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluspa2n8xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluspa2n8xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluspa2n8xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluspa2n8xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluspa2n8xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulpnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulpnx16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulpanx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulpanx16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluspnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluspnx16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluspanx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluspanx16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluupnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluupnx16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluupanx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluupanx16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulp2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulp2nx8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulpa2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulpa2nx8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusp2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusp2nx8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluspa2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluspa2nx8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluup2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluup2nx8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluupa2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluupa2nx8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulpi2nr8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulpi2nr8x16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulpai2nr8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulpai2nr8x16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluspi2nr8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluspi2nr8x16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluspai2nr8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluspai2nr8x16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulq2n8xr8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulq2n8xr8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulqa2n8xr8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulqa2n8xr8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusq2n8xr8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusq2n8xr8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusqa2n8xr8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusqa2n8xr8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mul4t2n8xr8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mul4t2n8xr8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul4t2n8xr8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul4t2n8xr8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul4t2n8xr8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mul4t2n8xr8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mul4t2n8xr8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mul4ta2n8xr8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mul4ta2n8xr8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul4ta2n8xr8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul4ta2n8xr8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul4ta2n8xr8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mul4ta2n8xr8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mul4ta2n8xr8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulus4t2n8xr8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulus4t2n8xr8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus4t2n8xr8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus4t2n8xr8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus4t2n8xr8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulus4t2n8xr8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulus4t2n8xr8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulus4ta2n8xr8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulus4ta2n8xr8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus4ta2n8xr8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus4ta2n8xr8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus4ta2n8xr8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulus4ta2n8xr8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulus4ta2n8xr8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwnx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwnx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwnx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwnx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwnx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwanx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwanx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwanx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwanx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwanx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwanx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwsnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwsnx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwsnx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwsnx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwsnx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwsnx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwunx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwunx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwunx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwunx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwunx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwunx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwuanx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwuanx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwuanx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwuanx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwuanx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwuanx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwusnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwusnx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwusnx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwusnx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwusnx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwusnx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_subwnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_subwnx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwnx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwnx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwnx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subwnx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_subwanx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_subwanx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwanx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwanx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwanx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subwanx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_subwunx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_subwunx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwunx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwunx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwunx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subwunx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_subwuanx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_subwuanx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwuanx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwuanx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwuanx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subwuanx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_subw2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_subw2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_subw2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_subw2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_subw2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subw2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_subwa2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_subwa2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwa2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwa2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwa2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subwa2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_subwu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_subwu2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwu2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwu2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwu2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subwu2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_subwua2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_subwua2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwua2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwua2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwua2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subwua2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_randb2n_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_randb2n_Slot_f0_s1_ld_encode, 0, Opcode_ivp_randb2n_Slot_f0_s3_alu_encode, 0, Opcode_ivp_randb2n_Slot_f1_s1_ld_encode, 0, Opcode_ivp_randb2n_Slot_f1_s3_alu_encode, 0, Opcode_ivp_randb2n_Slot_f2_s1_ld_encode, 0, Opcode_ivp_randb2n_Slot_f2_s3_alu_encode, 0, Opcode_ivp_randb2n_Slot_f3_s1_ld_encode, 0, Opcode_ivp_randb2n_Slot_f3_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_randb2n_Slot_f11_s1_alu_encode, 0, Opcode_ivp_randb2n_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_randb2n_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_rorb2n_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_rorb2n_Slot_f0_s1_ld_encode, 0, Opcode_ivp_rorb2n_Slot_f0_s3_alu_encode, 0, Opcode_ivp_rorb2n_Slot_f1_s1_ld_encode, 0, Opcode_ivp_rorb2n_Slot_f1_s3_alu_encode, 0, Opcode_ivp_rorb2n_Slot_f2_s1_ld_encode, 0, Opcode_ivp_rorb2n_Slot_f2_s3_alu_encode, 0, Opcode_ivp_rorb2n_Slot_f3_s1_ld_encode, 0, Opcode_ivp_rorb2n_Slot_f3_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rorb2n_Slot_f11_s1_alu_encode, 0, Opcode_ivp_rorb2n_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_rorb2n_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_randbn_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_randbn_Slot_f0_s1_ld_encode, 0, Opcode_ivp_randbn_Slot_f0_s3_alu_encode, 0, Opcode_ivp_randbn_Slot_f1_s1_ld_encode, 0, Opcode_ivp_randbn_Slot_f1_s3_alu_encode, 0, Opcode_ivp_randbn_Slot_f2_s1_ld_encode, 0, Opcode_ivp_randbn_Slot_f2_s3_alu_encode, 0, Opcode_ivp_randbn_Slot_f3_s1_ld_encode, 0, Opcode_ivp_randbn_Slot_f3_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_randbn_Slot_f11_s1_alu_encode, 0, Opcode_ivp_randbn_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_randbn_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_rorbn_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_rorbn_Slot_f0_s1_ld_encode, 0, Opcode_ivp_rorbn_Slot_f0_s3_alu_encode, 0, Opcode_ivp_rorbn_Slot_f1_s1_ld_encode, 0, Opcode_ivp_rorbn_Slot_f1_s3_alu_encode, 0, Opcode_ivp_rorbn_Slot_f2_s1_ld_encode, 0, Opcode_ivp_rorbn_Slot_f2_s3_alu_encode, 0, Opcode_ivp_rorbn_Slot_f3_s1_ld_encode, 0, Opcode_ivp_rorbn_Slot_f3_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rorbn_Slot_f11_s1_alu_encode, 0, Opcode_ivp_rorbn_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_rorbn_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_randbn_2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_randbn_2_Slot_f0_s1_ld_encode, 0, Opcode_ivp_randbn_2_Slot_f0_s3_alu_encode, 0, Opcode_ivp_randbn_2_Slot_f1_s1_ld_encode, 0, Opcode_ivp_randbn_2_Slot_f1_s3_alu_encode, 0, Opcode_ivp_randbn_2_Slot_f2_s1_ld_encode, 0, Opcode_ivp_randbn_2_Slot_f2_s3_alu_encode, 0, Opcode_ivp_randbn_2_Slot_f3_s1_ld_encode, 0, Opcode_ivp_randbn_2_Slot_f3_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_randbn_2_Slot_f11_s1_alu_encode, 0, Opcode_ivp_randbn_2_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_randbn_2_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_rorbn_2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_rorbn_2_Slot_f0_s1_ld_encode, 0, Opcode_ivp_rorbn_2_Slot_f0_s3_alu_encode, 0, Opcode_ivp_rorbn_2_Slot_f1_s1_ld_encode, 0, Opcode_ivp_rorbn_2_Slot_f1_s3_alu_encode, 0, Opcode_ivp_rorbn_2_Slot_f2_s1_ld_encode, 0, Opcode_ivp_rorbn_2_Slot_f2_s3_alu_encode, 0, Opcode_ivp_rorbn_2_Slot_f3_s1_ld_encode, 0, Opcode_ivp_rorbn_2_Slot_f3_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rorbn_2_Slot_f11_s1_alu_encode, 0, Opcode_ivp_rorbn_2_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_rorbn_2_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_avgnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_avgnx16_Slot_f0_s3_alu_encode, Opcode_ivp_avgnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_avgnx16_Slot_f1_s2_mul_encode, Opcode_ivp_avgnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_avgnx16_Slot_f2_s2_mul_encode, Opcode_ivp_avgnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_avgnx16_Slot_f3_s3_alu_encode, Opcode_ivp_avgnx16_Slot_f3_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgnx16_Slot_f11_s3_alu_encode, Opcode_ivp_avgnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_avgunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_avgunx16_Slot_f0_s3_alu_encode, Opcode_ivp_avgunx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_avgunx16_Slot_f1_s2_mul_encode, Opcode_ivp_avgunx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_avgunx16_Slot_f2_s2_mul_encode, Opcode_ivp_avgunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_avgunx16_Slot_f3_s3_alu_encode, Opcode_ivp_avgunx16_Slot_f3_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgunx16_Slot_f11_s3_alu_encode, Opcode_ivp_avgunx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_avg2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avg2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_avg2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_avg2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_avg2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_avg2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_avg2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_avg2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avg2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_avg2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avg2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_avgr2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgr2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_avgr2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_avgr2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_avgr2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_avgr2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_avgr2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_avgr2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgr2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_avgr2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgr2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_avgrnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_avgrnx16_Slot_f0_s3_alu_encode, Opcode_ivp_avgrnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_avgrnx16_Slot_f1_s2_mul_encode, Opcode_ivp_avgrnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_avgrnx16_Slot_f2_s2_mul_encode, Opcode_ivp_avgrnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_avgrnx16_Slot_f3_s3_alu_encode, Opcode_ivp_avgrnx16_Slot_f3_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgrnx16_Slot_f11_s3_alu_encode, Opcode_ivp_avgrnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgrnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_avgrunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_avgrunx16_Slot_f0_s3_alu_encode, Opcode_ivp_avgrunx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_avgrunx16_Slot_f1_s2_mul_encode, Opcode_ivp_avgrunx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_avgrunx16_Slot_f2_s2_mul_encode, Opcode_ivp_avgrunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_avgrunx16_Slot_f3_s3_alu_encode, Opcode_ivp_avgrunx16_Slot_f3_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgrunx16_Slot_f11_s3_alu_encode, Opcode_ivp_avgrunx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgrunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatheranx8u_encode_fns[] = { + 0, 0, 0, Opcode_ivp_gatheranx8u_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheranx8u_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_gatheranx8u_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheranx8u_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatheranx8u_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_gatheranx8u_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatheranx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_gatheranx16_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheranx16_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_gatheranx16_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheranx16_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatheranx16_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_gatheranx16_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatheran_2x32_encode_fns[] = { + 0, 0, 0, Opcode_ivp_gatheran_2x32_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheran_2x32_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_gatheran_2x32_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheran_2x32_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatheran_2x32_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_gatheran_2x32_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatheranx8ut_encode_fns[] = { + 0, 0, 0, Opcode_ivp_gatheranx8ut_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheranx8ut_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_gatheranx8ut_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheranx8ut_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatheranx8ut_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_gatheranx8ut_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatheranx16t_encode_fns[] = { + 0, 0, 0, Opcode_ivp_gatheranx16t_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheranx16t_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_gatheranx16t_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheranx16t_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatheranx16t_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_gatheranx16t_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatheran_2x32t_encode_fns[] = { + 0, 0, 0, Opcode_ivp_gatheran_2x32t_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheran_2x32t_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_gatheran_2x32t_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheran_2x32t_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatheran_2x32t_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_gatheran_2x32t_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatherdnx16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_gatherdnx16_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherdnx16_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherdnx16_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherdnx16_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_gatherdnx16_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatherdnx16_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatherdnx8s_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_gatherdnx8s_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherdnx8s_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherdnx8s_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherdnx8s_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_gatherdnx8s_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatherdnx8s_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatherd2nx8_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_gatherd2nx8_l_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherd2nx8_l_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherd2nx8_l_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherd2nx8_l_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_gatherd2nx8_l_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatherd2nx8_l_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatherd2nx8_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_gatherd2nx8_h_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherd2nx8_h_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherd2nx8_h_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherd2nx8_h_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_gatherd2nx8_h_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatherd2nx8_h_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movgatherd_encode_fns[] = { + 0, 0, 0, Opcode_ivp_movgatherd_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_movgatherd_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_movgatherd_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_movgatherd_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movgatherd_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_movgatherd_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scatternx8u_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatternx8u_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatternx8u_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scatter2nx8_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatter2nx8_l_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatter2nx8_l_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scatter2nx8_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatter2nx8_h_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatter2nx8_h_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scatternx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatternx16_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatternx16_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scattern_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scattern_2x32_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scattern_2x32_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scatternx8ut_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatternx8ut_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatternx8ut_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scatter2nx8t_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatter2nx8t_l_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatter2nx8t_l_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scatter2nx8t_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatter2nx8t_h_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatter2nx8t_h_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scatternx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatternx16t_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatternx16t_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scattern_2x32t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scattern_2x32t_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scattern_2x32t_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scatterw_encode_fns[] = { + 0, 0, 0, Opcode_ivp_scatterw_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_scatterw_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_scatterw_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_scatterw_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_scatterw_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatterw_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_scatterw_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_counteqz4nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_counteqz4nx8_Slot_f1_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_counteqz4nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_counteqz4nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_counteq4nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_counteq4nx8_Slot_f1_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_counteq4nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_counteq4nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_counteqmz4nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_counteqmz4nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_counteqmz4nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_counteqm4nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_counteqm4nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_counteqm4nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_countlez4nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_countlez4nx8_Slot_f1_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_countlez4nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_countlez4nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_countle4nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_countle4nx8_Slot_f1_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_countle4nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_countle4nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_countlemz4nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_countlemz4nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_countlemz4nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_countlem4nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_countlem4nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_countlem4nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsr2nx8_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsr2nx8_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsr2nx8_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsr2nx8_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsr2nx8_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsr2nx8_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsr2nx8_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsr2nx8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsr2nx8_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsr2nx8_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsr2nx8_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsr2nx8_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsr2nx8_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsr2nx8_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsr2nx8_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsr2nx8_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsr2nx8_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsr2nx8_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsr2nx8_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsr2nx8_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsr2nx8_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsr2nx8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsr2nx8_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsr2nx8_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsr2nx8_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsr2nx8_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsr2nx8_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsr2nx8_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsrnx16_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsrnx16_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsrnx16_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsrnx16_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsrnx16_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsrnx16_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsrnx16_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsrnx16_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsrnx16_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsrnx16_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsrnx16_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsrnx16_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsrnx16_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsrnx16_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsrnx16_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsrnx16_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsrnx16_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsrnx16_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsrnx16_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsrnx16_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsrnx16_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsrnx16_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsrnx16_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsrnx16_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsrnx16_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsrnx16_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsrnx16_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsrnx16_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsrn_2x32_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsrn_2x32_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsrn_2x32_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsrn_2x32_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsrn_2x32_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsrn_2x32_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsrn_2x32_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsrn_2x32_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsrn_2x32_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsrn_2x32_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsrn_2x32_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsrn_2x32_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsrn_2x32_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsrn_2x32_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsrn_2x32_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsrn_2x32_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsrn_2x32_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsrn_2x32_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsrn_2x32_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsrn_2x32_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsrn_2x32_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsrn_2x32_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsrn_2x32_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsrn_2x32_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsrn_2x32_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsrn_2x32_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsrn_2x32_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsrn_2x32_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_absnx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_absnx16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_absnx16_Slot_f0_s3_alu_encode, Opcode_ivp_absnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_absnx16_Slot_f1_s2_mul_encode, Opcode_ivp_absnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_absnx16_Slot_f2_s2_mul_encode, Opcode_ivp_absnx16_Slot_f2_s3_alu_encode, Opcode_ivp_absnx16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_absnx16_Slot_f3_s3_alu_encode, Opcode_ivp_absnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_absnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_absnx16_Slot_f11_s3_alu_encode, Opcode_ivp_absnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_absnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_abssnx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_abssnx16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_abssnx16_Slot_f0_s3_alu_encode, Opcode_ivp_abssnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_abssnx16_Slot_f1_s2_mul_encode, Opcode_ivp_abssnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_abssnx16_Slot_f2_s2_mul_encode, Opcode_ivp_abssnx16_Slot_f2_s3_alu_encode, Opcode_ivp_abssnx16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_abssnx16_Slot_f3_s3_alu_encode, Opcode_ivp_abssnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_abssnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssnx16_Slot_f11_s3_alu_encode, Opcode_ivp_abssnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_abssubnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_abssubnx16_Slot_f0_s3_alu_encode, Opcode_ivp_abssubnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_abssubnx16_Slot_f1_s2_mul_encode, Opcode_ivp_abssubnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_abssubnx16_Slot_f2_s2_mul_encode, Opcode_ivp_abssubnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_abssubnx16_Slot_f3_s3_alu_encode, Opcode_ivp_abssubnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_abssubnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssubnx16_Slot_f11_s3_alu_encode, Opcode_ivp_abssubnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssubnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_abssubunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_abssubunx16_Slot_f0_s3_alu_encode, Opcode_ivp_abssubunx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_abssubunx16_Slot_f1_s2_mul_encode, Opcode_ivp_abssubunx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_abssubunx16_Slot_f2_s2_mul_encode, Opcode_ivp_abssubunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_abssubunx16_Slot_f3_s3_alu_encode, Opcode_ivp_abssubunx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_abssubunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssubunx16_Slot_f11_s3_alu_encode, Opcode_ivp_abssubunx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssubunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_absssubnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_absssubnx16_Slot_f0_s3_alu_encode, Opcode_ivp_absssubnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_absssubnx16_Slot_f1_s2_mul_encode, Opcode_ivp_absssubnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_absssubnx16_Slot_f2_s2_mul_encode, Opcode_ivp_absssubnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_absssubnx16_Slot_f3_s3_alu_encode, Opcode_ivp_absssubnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_absssubnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_absssubnx16_Slot_f11_s3_alu_encode, Opcode_ivp_absssubnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_absssubnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l32i_n_Slot_n1_s0_ldst_encode, 0, 0, Opcode_l32i_n_Slot_n2_s0_ldst_encode, Opcode_l32i_n_Slot_n2_s1_ld_encode, Opcode_l32i_n_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0, 0, Opcode_mov_n_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_mov_n_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_mov_n_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_mov_n_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_mov_n_Slot_f4_s3_alu_encode, 0, 0, 0, Opcode_mov_n_Slot_f5_s3_base_encode, 0, 0, 0, Opcode_mov_n_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s32i_n_Slot_n1_s0_ldst_encode, 0, 0, Opcode_s32i_n_Slot_n2_s0_ldst_encode, 0, Opcode_s32i_n_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { + Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { + Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0, Opcode_addi_Slot_f0_s0_ldst_encode, Opcode_addi_Slot_f0_s1_ld_encode, Opcode_addi_Slot_f0_s2_mul_encode, Opcode_addi_Slot_f0_s3_alu_encode, Opcode_addi_Slot_f1_s0_ldstalu_encode, Opcode_addi_Slot_f1_s1_ld_encode, Opcode_addi_Slot_f1_s2_mul_encode, Opcode_addi_Slot_f1_s3_alu_encode, Opcode_addi_Slot_f2_s0_ldst_encode, Opcode_addi_Slot_f2_s1_ld_encode, Opcode_addi_Slot_f2_s2_mul_encode, Opcode_addi_Slot_f2_s3_alu_encode, Opcode_addi_Slot_f3_s0_ldst_encode, Opcode_addi_Slot_f3_s1_ld_encode, Opcode_addi_Slot_f3_s2_mul_encode, Opcode_addi_Slot_f3_s3_alu_encode, 0, Opcode_addi_Slot_f4_s0_ld_encode, Opcode_addi_Slot_f4_s1_ld_encode, 0, Opcode_addi_Slot_f4_s3_alu_encode, Opcode_addi_Slot_f5_s0_base_encode, Opcode_addi_Slot_f5_s1_base_encode, Opcode_addi_Slot_f5_s2_base_encode, Opcode_addi_Slot_f5_s3_base_encode, Opcode_addi_Slot_f11_s0_ld_encode, Opcode_addi_Slot_f11_s1_alu_encode, Opcode_addi_Slot_f11_s2_mul_encode, Opcode_addi_Slot_f11_s3_alu_encode, 0, Opcode_addi_Slot_n1_s0_ldst_encode, 0, Opcode_addi_Slot_n1_s2_mul_encode, Opcode_addi_Slot_n2_s0_ldst_encode, Opcode_addi_Slot_n2_s1_ld_encode, Opcode_addi_Slot_n0_s0_ldst_encode, 0, 0, Opcode_addi_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0, Opcode_addmi_Slot_f0_s0_ldst_encode, Opcode_addmi_Slot_f0_s1_ld_encode, 0, 0, Opcode_addmi_Slot_f1_s0_ldstalu_encode, Opcode_addmi_Slot_f1_s1_ld_encode, 0, 0, Opcode_addmi_Slot_f2_s0_ldst_encode, Opcode_addmi_Slot_f2_s1_ld_encode, 0, 0, Opcode_addmi_Slot_f3_s0_ldst_encode, Opcode_addmi_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_addmi_Slot_f4_s0_ld_encode, Opcode_addmi_Slot_f4_s1_ld_encode, 0, 0, Opcode_addmi_Slot_f5_s0_base_encode, Opcode_addmi_Slot_f5_s1_base_encode, Opcode_addmi_Slot_f5_s2_base_encode, 0, Opcode_addmi_Slot_f11_s0_ld_encode, Opcode_addmi_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_addmi_Slot_n1_s0_ldst_encode, 0, 0, Opcode_addmi_Slot_n2_s0_ldst_encode, Opcode_addmi_Slot_n2_s1_ld_encode, Opcode_addmi_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_f0_s0_ldst_encode, Opcode_add_Slot_f0_s1_ld_encode, Opcode_add_Slot_f0_s2_mul_encode, 0, Opcode_add_Slot_f1_s0_ldstalu_encode, Opcode_add_Slot_f1_s1_ld_encode, Opcode_add_Slot_f1_s2_mul_encode, 0, Opcode_add_Slot_f2_s0_ldst_encode, Opcode_add_Slot_f2_s1_ld_encode, Opcode_add_Slot_f2_s2_mul_encode, 0, Opcode_add_Slot_f3_s0_ldst_encode, Opcode_add_Slot_f3_s1_ld_encode, Opcode_add_Slot_f3_s2_mul_encode, 0, 0, Opcode_add_Slot_f4_s0_ld_encode, Opcode_add_Slot_f4_s1_ld_encode, 0, 0, Opcode_add_Slot_f5_s0_base_encode, Opcode_add_Slot_f5_s1_base_encode, Opcode_add_Slot_f5_s2_base_encode, 0, Opcode_add_Slot_f11_s0_ld_encode, Opcode_add_Slot_f11_s1_alu_encode, Opcode_add_Slot_f11_s2_mul_encode, 0, 0, Opcode_add_Slot_n1_s0_ldst_encode, 0, Opcode_add_Slot_n1_s2_mul_encode, Opcode_add_Slot_n2_s0_ldst_encode, Opcode_add_Slot_n2_s1_ld_encode, Opcode_add_Slot_n0_s0_ldst_encode, 0, 0, Opcode_add_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_f0_s0_ldst_encode, Opcode_sub_Slot_f0_s1_ld_encode, Opcode_sub_Slot_f0_s2_mul_encode, 0, Opcode_sub_Slot_f1_s0_ldstalu_encode, Opcode_sub_Slot_f1_s1_ld_encode, Opcode_sub_Slot_f1_s2_mul_encode, 0, Opcode_sub_Slot_f2_s0_ldst_encode, Opcode_sub_Slot_f2_s1_ld_encode, Opcode_sub_Slot_f2_s2_mul_encode, 0, Opcode_sub_Slot_f3_s0_ldst_encode, Opcode_sub_Slot_f3_s1_ld_encode, Opcode_sub_Slot_f3_s2_mul_encode, 0, 0, Opcode_sub_Slot_f4_s0_ld_encode, Opcode_sub_Slot_f4_s1_ld_encode, 0, 0, Opcode_sub_Slot_f5_s0_base_encode, Opcode_sub_Slot_f5_s1_base_encode, Opcode_sub_Slot_f5_s2_base_encode, 0, Opcode_sub_Slot_f11_s0_ld_encode, Opcode_sub_Slot_f11_s1_alu_encode, Opcode_sub_Slot_f11_s2_mul_encode, 0, 0, Opcode_sub_Slot_n1_s0_ldst_encode, 0, Opcode_sub_Slot_n1_s2_mul_encode, Opcode_sub_Slot_n2_s0_ldst_encode, Opcode_sub_Slot_n2_s1_ld_encode, Opcode_sub_Slot_n0_s0_ldst_encode, 0, 0, Opcode_sub_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0, Opcode_addx2_Slot_f0_s0_ldst_encode, Opcode_addx2_Slot_f0_s1_ld_encode, Opcode_addx2_Slot_f0_s2_mul_encode, 0, Opcode_addx2_Slot_f1_s0_ldstalu_encode, Opcode_addx2_Slot_f1_s1_ld_encode, Opcode_addx2_Slot_f1_s2_mul_encode, 0, Opcode_addx2_Slot_f2_s0_ldst_encode, Opcode_addx2_Slot_f2_s1_ld_encode, Opcode_addx2_Slot_f2_s2_mul_encode, 0, Opcode_addx2_Slot_f3_s0_ldst_encode, Opcode_addx2_Slot_f3_s1_ld_encode, Opcode_addx2_Slot_f3_s2_mul_encode, 0, 0, Opcode_addx2_Slot_f4_s0_ld_encode, Opcode_addx2_Slot_f4_s1_ld_encode, 0, 0, Opcode_addx2_Slot_f5_s0_base_encode, Opcode_addx2_Slot_f5_s1_base_encode, Opcode_addx2_Slot_f5_s2_base_encode, 0, Opcode_addx2_Slot_f11_s0_ld_encode, Opcode_addx2_Slot_f11_s1_alu_encode, Opcode_addx2_Slot_f11_s2_mul_encode, 0, 0, Opcode_addx2_Slot_n1_s0_ldst_encode, 0, Opcode_addx2_Slot_n1_s2_mul_encode, Opcode_addx2_Slot_n2_s0_ldst_encode, Opcode_addx2_Slot_n2_s1_ld_encode, Opcode_addx2_Slot_n0_s0_ldst_encode, 0, 0, Opcode_addx2_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0, Opcode_addx4_Slot_f0_s0_ldst_encode, Opcode_addx4_Slot_f0_s1_ld_encode, Opcode_addx4_Slot_f0_s2_mul_encode, 0, Opcode_addx4_Slot_f1_s0_ldstalu_encode, Opcode_addx4_Slot_f1_s1_ld_encode, Opcode_addx4_Slot_f1_s2_mul_encode, 0, Opcode_addx4_Slot_f2_s0_ldst_encode, Opcode_addx4_Slot_f2_s1_ld_encode, Opcode_addx4_Slot_f2_s2_mul_encode, 0, Opcode_addx4_Slot_f3_s0_ldst_encode, Opcode_addx4_Slot_f3_s1_ld_encode, Opcode_addx4_Slot_f3_s2_mul_encode, 0, 0, Opcode_addx4_Slot_f4_s0_ld_encode, Opcode_addx4_Slot_f4_s1_ld_encode, 0, 0, Opcode_addx4_Slot_f5_s0_base_encode, Opcode_addx4_Slot_f5_s1_base_encode, Opcode_addx4_Slot_f5_s2_base_encode, 0, Opcode_addx4_Slot_f11_s0_ld_encode, Opcode_addx4_Slot_f11_s1_alu_encode, Opcode_addx4_Slot_f11_s2_mul_encode, 0, 0, Opcode_addx4_Slot_n1_s0_ldst_encode, 0, Opcode_addx4_Slot_n1_s2_mul_encode, Opcode_addx4_Slot_n2_s0_ldst_encode, Opcode_addx4_Slot_n2_s1_ld_encode, Opcode_addx4_Slot_n0_s0_ldst_encode, 0, 0, Opcode_addx4_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0, Opcode_addx8_Slot_f0_s0_ldst_encode, Opcode_addx8_Slot_f0_s1_ld_encode, Opcode_addx8_Slot_f0_s2_mul_encode, 0, Opcode_addx8_Slot_f1_s0_ldstalu_encode, Opcode_addx8_Slot_f1_s1_ld_encode, Opcode_addx8_Slot_f1_s2_mul_encode, 0, Opcode_addx8_Slot_f2_s0_ldst_encode, Opcode_addx8_Slot_f2_s1_ld_encode, Opcode_addx8_Slot_f2_s2_mul_encode, 0, Opcode_addx8_Slot_f3_s0_ldst_encode, Opcode_addx8_Slot_f3_s1_ld_encode, Opcode_addx8_Slot_f3_s2_mul_encode, 0, 0, Opcode_addx8_Slot_f4_s0_ld_encode, Opcode_addx8_Slot_f4_s1_ld_encode, 0, 0, Opcode_addx8_Slot_f5_s0_base_encode, Opcode_addx8_Slot_f5_s1_base_encode, Opcode_addx8_Slot_f5_s2_base_encode, 0, Opcode_addx8_Slot_f11_s0_ld_encode, Opcode_addx8_Slot_f11_s1_alu_encode, Opcode_addx8_Slot_f11_s2_mul_encode, 0, 0, Opcode_addx8_Slot_n1_s0_ldst_encode, 0, Opcode_addx8_Slot_n1_s2_mul_encode, Opcode_addx8_Slot_n2_s0_ldst_encode, Opcode_addx8_Slot_n2_s1_ld_encode, Opcode_addx8_Slot_n0_s0_ldst_encode, 0, 0, Opcode_addx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0, Opcode_subx2_Slot_f0_s0_ldst_encode, Opcode_subx2_Slot_f0_s1_ld_encode, Opcode_subx2_Slot_f0_s2_mul_encode, 0, Opcode_subx2_Slot_f1_s0_ldstalu_encode, Opcode_subx2_Slot_f1_s1_ld_encode, Opcode_subx2_Slot_f1_s2_mul_encode, 0, Opcode_subx2_Slot_f2_s0_ldst_encode, Opcode_subx2_Slot_f2_s1_ld_encode, Opcode_subx2_Slot_f2_s2_mul_encode, 0, Opcode_subx2_Slot_f3_s0_ldst_encode, Opcode_subx2_Slot_f3_s1_ld_encode, Opcode_subx2_Slot_f3_s2_mul_encode, 0, 0, Opcode_subx2_Slot_f4_s0_ld_encode, Opcode_subx2_Slot_f4_s1_ld_encode, 0, 0, Opcode_subx2_Slot_f5_s0_base_encode, Opcode_subx2_Slot_f5_s1_base_encode, Opcode_subx2_Slot_f5_s2_base_encode, 0, Opcode_subx2_Slot_f11_s0_ld_encode, Opcode_subx2_Slot_f11_s1_alu_encode, Opcode_subx2_Slot_f11_s2_mul_encode, 0, 0, Opcode_subx2_Slot_n1_s0_ldst_encode, 0, Opcode_subx2_Slot_n1_s2_mul_encode, Opcode_subx2_Slot_n2_s0_ldst_encode, Opcode_subx2_Slot_n2_s1_ld_encode, Opcode_subx2_Slot_n0_s0_ldst_encode, 0, 0, Opcode_subx2_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0, Opcode_subx4_Slot_f0_s0_ldst_encode, Opcode_subx4_Slot_f0_s1_ld_encode, Opcode_subx4_Slot_f0_s2_mul_encode, 0, Opcode_subx4_Slot_f1_s0_ldstalu_encode, Opcode_subx4_Slot_f1_s1_ld_encode, Opcode_subx4_Slot_f1_s2_mul_encode, 0, Opcode_subx4_Slot_f2_s0_ldst_encode, Opcode_subx4_Slot_f2_s1_ld_encode, Opcode_subx4_Slot_f2_s2_mul_encode, 0, Opcode_subx4_Slot_f3_s0_ldst_encode, Opcode_subx4_Slot_f3_s1_ld_encode, Opcode_subx4_Slot_f3_s2_mul_encode, 0, 0, Opcode_subx4_Slot_f4_s0_ld_encode, Opcode_subx4_Slot_f4_s1_ld_encode, 0, 0, Opcode_subx4_Slot_f5_s0_base_encode, Opcode_subx4_Slot_f5_s1_base_encode, Opcode_subx4_Slot_f5_s2_base_encode, 0, Opcode_subx4_Slot_f11_s0_ld_encode, Opcode_subx4_Slot_f11_s1_alu_encode, Opcode_subx4_Slot_f11_s2_mul_encode, 0, 0, Opcode_subx4_Slot_n1_s0_ldst_encode, 0, Opcode_subx4_Slot_n1_s2_mul_encode, Opcode_subx4_Slot_n2_s0_ldst_encode, Opcode_subx4_Slot_n2_s1_ld_encode, Opcode_subx4_Slot_n0_s0_ldst_encode, 0, 0, Opcode_subx4_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0, Opcode_subx8_Slot_f0_s0_ldst_encode, Opcode_subx8_Slot_f0_s1_ld_encode, Opcode_subx8_Slot_f0_s2_mul_encode, 0, Opcode_subx8_Slot_f1_s0_ldstalu_encode, Opcode_subx8_Slot_f1_s1_ld_encode, Opcode_subx8_Slot_f1_s2_mul_encode, 0, Opcode_subx8_Slot_f2_s0_ldst_encode, Opcode_subx8_Slot_f2_s1_ld_encode, Opcode_subx8_Slot_f2_s2_mul_encode, 0, Opcode_subx8_Slot_f3_s0_ldst_encode, Opcode_subx8_Slot_f3_s1_ld_encode, Opcode_subx8_Slot_f3_s2_mul_encode, 0, 0, Opcode_subx8_Slot_f4_s0_ld_encode, Opcode_subx8_Slot_f4_s1_ld_encode, 0, 0, Opcode_subx8_Slot_f5_s0_base_encode, Opcode_subx8_Slot_f5_s1_base_encode, Opcode_subx8_Slot_f5_s2_base_encode, 0, Opcode_subx8_Slot_f11_s0_ld_encode, Opcode_subx8_Slot_f11_s1_alu_encode, Opcode_subx8_Slot_f11_s2_mul_encode, 0, 0, Opcode_subx8_Slot_n1_s0_ldst_encode, 0, Opcode_subx8_Slot_n1_s2_mul_encode, Opcode_subx8_Slot_n2_s0_ldst_encode, Opcode_subx8_Slot_n2_s1_ld_encode, Opcode_subx8_Slot_n0_s0_ldst_encode, 0, 0, Opcode_subx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_f0_s0_ldst_encode, Opcode_and_Slot_f0_s1_ld_encode, Opcode_and_Slot_f0_s2_mul_encode, 0, Opcode_and_Slot_f1_s0_ldstalu_encode, Opcode_and_Slot_f1_s1_ld_encode, Opcode_and_Slot_f1_s2_mul_encode, 0, Opcode_and_Slot_f2_s0_ldst_encode, Opcode_and_Slot_f2_s1_ld_encode, Opcode_and_Slot_f2_s2_mul_encode, 0, Opcode_and_Slot_f3_s0_ldst_encode, Opcode_and_Slot_f3_s1_ld_encode, Opcode_and_Slot_f3_s2_mul_encode, 0, 0, Opcode_and_Slot_f4_s0_ld_encode, Opcode_and_Slot_f4_s1_ld_encode, 0, 0, Opcode_and_Slot_f5_s0_base_encode, Opcode_and_Slot_f5_s1_base_encode, Opcode_and_Slot_f5_s2_base_encode, 0, Opcode_and_Slot_f11_s0_ld_encode, Opcode_and_Slot_f11_s1_alu_encode, Opcode_and_Slot_f11_s2_mul_encode, 0, 0, Opcode_and_Slot_n1_s0_ldst_encode, 0, Opcode_and_Slot_n1_s2_mul_encode, Opcode_and_Slot_n2_s0_ldst_encode, Opcode_and_Slot_n2_s1_ld_encode, Opcode_and_Slot_n0_s0_ldst_encode, 0, 0, Opcode_and_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_f0_s0_ldst_encode, Opcode_or_Slot_f0_s1_ld_encode, Opcode_or_Slot_f0_s2_mul_encode, 0, Opcode_or_Slot_f1_s0_ldstalu_encode, Opcode_or_Slot_f1_s1_ld_encode, Opcode_or_Slot_f1_s2_mul_encode, 0, Opcode_or_Slot_f2_s0_ldst_encode, Opcode_or_Slot_f2_s1_ld_encode, Opcode_or_Slot_f2_s2_mul_encode, 0, Opcode_or_Slot_f3_s0_ldst_encode, Opcode_or_Slot_f3_s1_ld_encode, Opcode_or_Slot_f3_s2_mul_encode, 0, 0, Opcode_or_Slot_f4_s0_ld_encode, Opcode_or_Slot_f4_s1_ld_encode, 0, 0, Opcode_or_Slot_f5_s0_base_encode, Opcode_or_Slot_f5_s1_base_encode, Opcode_or_Slot_f5_s2_base_encode, 0, Opcode_or_Slot_f11_s0_ld_encode, Opcode_or_Slot_f11_s1_alu_encode, Opcode_or_Slot_f11_s2_mul_encode, 0, 0, Opcode_or_Slot_n1_s0_ldst_encode, 0, Opcode_or_Slot_n1_s2_mul_encode, Opcode_or_Slot_n2_s0_ldst_encode, Opcode_or_Slot_n2_s1_ld_encode, Opcode_or_Slot_n0_s0_ldst_encode, 0, 0, Opcode_or_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_f0_s0_ldst_encode, Opcode_xor_Slot_f0_s1_ld_encode, Opcode_xor_Slot_f0_s2_mul_encode, 0, Opcode_xor_Slot_f1_s0_ldstalu_encode, Opcode_xor_Slot_f1_s1_ld_encode, Opcode_xor_Slot_f1_s2_mul_encode, 0, Opcode_xor_Slot_f2_s0_ldst_encode, Opcode_xor_Slot_f2_s1_ld_encode, Opcode_xor_Slot_f2_s2_mul_encode, 0, Opcode_xor_Slot_f3_s0_ldst_encode, Opcode_xor_Slot_f3_s1_ld_encode, Opcode_xor_Slot_f3_s2_mul_encode, 0, 0, Opcode_xor_Slot_f4_s0_ld_encode, Opcode_xor_Slot_f4_s1_ld_encode, 0, 0, Opcode_xor_Slot_f5_s0_base_encode, Opcode_xor_Slot_f5_s1_base_encode, Opcode_xor_Slot_f5_s2_base_encode, 0, Opcode_xor_Slot_f11_s0_ld_encode, Opcode_xor_Slot_f11_s1_alu_encode, Opcode_xor_Slot_f11_s2_mul_encode, 0, 0, Opcode_xor_Slot_n1_s0_ldst_encode, 0, Opcode_xor_Slot_n1_s2_mul_encode, Opcode_xor_Slot_n2_s0_ldst_encode, Opcode_xor_Slot_n2_s1_ld_encode, Opcode_xor_Slot_n0_s0_ldst_encode, 0, 0, Opcode_xor_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_const16_encode_fns[] = { + Opcode_const16_Slot_inst_encode, 0, 0, Opcode_const16_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_const16_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_const16_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_const16_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_const16_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_const16_Slot_f5_s0_base_encode, 0, 0, 0, Opcode_const16_Slot_f11_s0_ld_encode, 0, 0, 0, 0, Opcode_const16_Slot_n1_s0_ldst_encode, 0, 0, Opcode_const16_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_f0_s0_ldst_encode, Opcode_extui_Slot_f0_s1_ld_encode, 0, 0, Opcode_extui_Slot_f1_s0_ldstalu_encode, Opcode_extui_Slot_f1_s1_ld_encode, 0, 0, Opcode_extui_Slot_f2_s0_ldst_encode, Opcode_extui_Slot_f2_s1_ld_encode, 0, 0, Opcode_extui_Slot_f3_s0_ldst_encode, Opcode_extui_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_extui_Slot_f4_s0_ld_encode, Opcode_extui_Slot_f4_s1_ld_encode, 0, 0, Opcode_extui_Slot_f5_s0_base_encode, Opcode_extui_Slot_f5_s1_base_encode, 0, 0, Opcode_extui_Slot_f11_s0_ld_encode, Opcode_extui_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_extui_Slot_n1_s0_ldst_encode, 0, 0, Opcode_extui_Slot_n2_s0_ldst_encode, Opcode_extui_Slot_n2_s1_ld_encode, Opcode_extui_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0, Opcode_j_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_j_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_j_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_j_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_j_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_j_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0, Opcode_l16ui_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_l16ui_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_l16ui_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_l16ui_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_l16ui_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_l16ui_Slot_f5_s0_base_encode, Opcode_l16ui_Slot_f5_s1_base_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_l16ui_Slot_n1_s0_ldst_encode, 0, 0, Opcode_l16ui_Slot_n2_s0_ldst_encode, Opcode_l16ui_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0, Opcode_l16si_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_l16si_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_l16si_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_l16si_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_l16si_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_l16si_Slot_f5_s0_base_encode, Opcode_l16si_Slot_f5_s1_base_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_l16si_Slot_n1_s0_ldst_encode, 0, 0, Opcode_l16si_Slot_n2_s0_ldst_encode, Opcode_l16si_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0, Opcode_l32i_Slot_f0_s0_ldst_encode, Opcode_l32i_Slot_f0_s1_ld_encode, 0, 0, Opcode_l32i_Slot_f1_s0_ldstalu_encode, Opcode_l32i_Slot_f1_s1_ld_encode, 0, 0, Opcode_l32i_Slot_f2_s0_ldst_encode, Opcode_l32i_Slot_f2_s1_ld_encode, 0, 0, Opcode_l32i_Slot_f3_s0_ldst_encode, Opcode_l32i_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_l32i_Slot_f4_s0_ld_encode, Opcode_l32i_Slot_f4_s1_ld_encode, 0, 0, Opcode_l32i_Slot_f5_s0_base_encode, Opcode_l32i_Slot_f5_s1_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0, Opcode_l8ui_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_l8ui_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_l8ui_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_l8ui_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_l8ui_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_l8ui_Slot_f5_s0_base_encode, Opcode_l8ui_Slot_f5_s1_base_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_l8ui_Slot_n1_s0_ldst_encode, 0, 0, Opcode_l8ui_Slot_n2_s0_ldst_encode, Opcode_l8ui_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0, Opcode_loop_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_loop_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_loop_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_loop_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_loop_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_loop_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0, Opcode_loopnez_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_loopnez_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_loopnez_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_loopnez_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_loopnez_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_loopnez_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0, Opcode_loopgtz_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_loopgtz_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_loopgtz_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_loopgtz_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_loopgtz_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_loopgtz_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0, Opcode_movi_Slot_f0_s0_ldst_encode, Opcode_movi_Slot_f0_s1_ld_encode, 0, 0, Opcode_movi_Slot_f1_s0_ldstalu_encode, Opcode_movi_Slot_f1_s1_ld_encode, 0, 0, Opcode_movi_Slot_f2_s0_ldst_encode, Opcode_movi_Slot_f2_s1_ld_encode, 0, 0, Opcode_movi_Slot_f3_s0_ldst_encode, Opcode_movi_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_movi_Slot_f4_s0_ld_encode, Opcode_movi_Slot_f4_s1_ld_encode, 0, 0, Opcode_movi_Slot_f5_s0_base_encode, Opcode_movi_Slot_f5_s1_base_encode, Opcode_movi_Slot_f5_s2_base_encode, Opcode_movi_Slot_f5_s3_base_encode, Opcode_movi_Slot_f11_s0_ld_encode, Opcode_movi_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_movi_Slot_n1_s0_ldst_encode, 0, 0, Opcode_movi_Slot_n2_s0_ldst_encode, Opcode_movi_Slot_n2_s1_ld_encode, Opcode_movi_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_f0_s0_ldst_encode, Opcode_moveqz_Slot_f0_s1_ld_encode, 0, 0, Opcode_moveqz_Slot_f1_s0_ldstalu_encode, Opcode_moveqz_Slot_f1_s1_ld_encode, 0, 0, Opcode_moveqz_Slot_f2_s0_ldst_encode, Opcode_moveqz_Slot_f2_s1_ld_encode, 0, 0, Opcode_moveqz_Slot_f3_s0_ldst_encode, Opcode_moveqz_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_moveqz_Slot_f4_s0_ld_encode, Opcode_moveqz_Slot_f4_s1_ld_encode, 0, 0, Opcode_moveqz_Slot_f5_s0_base_encode, Opcode_moveqz_Slot_f5_s1_base_encode, Opcode_moveqz_Slot_f5_s2_base_encode, 0, Opcode_moveqz_Slot_f11_s0_ld_encode, Opcode_moveqz_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_moveqz_Slot_n1_s0_ldst_encode, 0, Opcode_moveqz_Slot_n1_s2_mul_encode, Opcode_moveqz_Slot_n2_s0_ldst_encode, Opcode_moveqz_Slot_n2_s1_ld_encode, Opcode_moveqz_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_f0_s0_ldst_encode, Opcode_movnez_Slot_f0_s1_ld_encode, 0, 0, Opcode_movnez_Slot_f1_s0_ldstalu_encode, Opcode_movnez_Slot_f1_s1_ld_encode, 0, 0, Opcode_movnez_Slot_f2_s0_ldst_encode, Opcode_movnez_Slot_f2_s1_ld_encode, 0, 0, Opcode_movnez_Slot_f3_s0_ldst_encode, Opcode_movnez_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_movnez_Slot_f4_s0_ld_encode, Opcode_movnez_Slot_f4_s1_ld_encode, 0, 0, Opcode_movnez_Slot_f5_s0_base_encode, Opcode_movnez_Slot_f5_s1_base_encode, Opcode_movnez_Slot_f5_s2_base_encode, 0, Opcode_movnez_Slot_f11_s0_ld_encode, Opcode_movnez_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_movnez_Slot_n1_s0_ldst_encode, 0, Opcode_movnez_Slot_n1_s2_mul_encode, Opcode_movnez_Slot_n2_s0_ldst_encode, Opcode_movnez_Slot_n2_s1_ld_encode, Opcode_movnez_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_f0_s0_ldst_encode, Opcode_movltz_Slot_f0_s1_ld_encode, 0, 0, Opcode_movltz_Slot_f1_s0_ldstalu_encode, Opcode_movltz_Slot_f1_s1_ld_encode, 0, 0, Opcode_movltz_Slot_f2_s0_ldst_encode, Opcode_movltz_Slot_f2_s1_ld_encode, 0, 0, Opcode_movltz_Slot_f3_s0_ldst_encode, Opcode_movltz_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_movltz_Slot_f4_s0_ld_encode, Opcode_movltz_Slot_f4_s1_ld_encode, 0, 0, Opcode_movltz_Slot_f5_s0_base_encode, Opcode_movltz_Slot_f5_s1_base_encode, Opcode_movltz_Slot_f5_s2_base_encode, 0, Opcode_movltz_Slot_f11_s0_ld_encode, Opcode_movltz_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_movltz_Slot_n1_s0_ldst_encode, 0, Opcode_movltz_Slot_n1_s2_mul_encode, Opcode_movltz_Slot_n2_s0_ldst_encode, Opcode_movltz_Slot_n2_s1_ld_encode, Opcode_movltz_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_f0_s0_ldst_encode, Opcode_movgez_Slot_f0_s1_ld_encode, 0, 0, Opcode_movgez_Slot_f1_s0_ldstalu_encode, Opcode_movgez_Slot_f1_s1_ld_encode, 0, 0, Opcode_movgez_Slot_f2_s0_ldst_encode, Opcode_movgez_Slot_f2_s1_ld_encode, 0, 0, Opcode_movgez_Slot_f3_s0_ldst_encode, Opcode_movgez_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_movgez_Slot_f4_s0_ld_encode, Opcode_movgez_Slot_f4_s1_ld_encode, 0, 0, Opcode_movgez_Slot_f5_s0_base_encode, Opcode_movgez_Slot_f5_s1_base_encode, Opcode_movgez_Slot_f5_s2_base_encode, 0, Opcode_movgez_Slot_f11_s0_ld_encode, Opcode_movgez_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_movgez_Slot_n1_s0_ldst_encode, 0, Opcode_movgez_Slot_n1_s2_mul_encode, Opcode_movgez_Slot_n2_s0_ldst_encode, Opcode_movgez_Slot_n2_s1_ld_encode, Opcode_movgez_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_f0_s0_ldst_encode, Opcode_neg_Slot_f0_s1_ld_encode, 0, 0, Opcode_neg_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_neg_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_neg_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_neg_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_neg_Slot_f5_s0_base_encode, 0, Opcode_neg_Slot_f5_s2_base_encode, 0, 0, 0, 0, 0, 0, Opcode_neg_Slot_n1_s0_ldst_encode, 0, 0, Opcode_neg_Slot_n2_s0_ldst_encode, Opcode_neg_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_f0_s0_ldst_encode, 0, Opcode_abs_Slot_f0_s2_mul_encode, 0, Opcode_abs_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_abs_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_abs_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_abs_Slot_f4_s0_ld_encode, Opcode_abs_Slot_f4_s1_ld_encode, 0, 0, Opcode_abs_Slot_f5_s0_base_encode, Opcode_abs_Slot_f5_s1_base_encode, 0, 0, 0, 0, Opcode_abs_Slot_f11_s2_mul_encode, 0, 0, Opcode_abs_Slot_n1_s0_ldst_encode, 0, 0, Opcode_abs_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_f0_s0_ldst_encode, Opcode_nop_Slot_f0_s1_ld_encode, Opcode_nop_Slot_f0_s2_mul_encode, Opcode_nop_Slot_f0_s3_alu_encode, Opcode_nop_Slot_f1_s0_ldstalu_encode, Opcode_nop_Slot_f1_s1_ld_encode, Opcode_nop_Slot_f1_s2_mul_encode, Opcode_nop_Slot_f1_s3_alu_encode, Opcode_nop_Slot_f2_s0_ldst_encode, Opcode_nop_Slot_f2_s1_ld_encode, Opcode_nop_Slot_f2_s2_mul_encode, Opcode_nop_Slot_f2_s3_alu_encode, Opcode_nop_Slot_f3_s0_ldst_encode, Opcode_nop_Slot_f3_s1_ld_encode, Opcode_nop_Slot_f3_s2_mul_encode, Opcode_nop_Slot_f3_s3_alu_encode, Opcode_nop_Slot_f3_s4_alu_encode, Opcode_nop_Slot_f4_s0_ld_encode, Opcode_nop_Slot_f4_s1_ld_encode, Opcode_nop_Slot_f4_s2_mul_encode, Opcode_nop_Slot_f4_s3_alu_encode, Opcode_nop_Slot_f5_s0_base_encode, Opcode_nop_Slot_f5_s1_base_encode, Opcode_nop_Slot_f5_s2_base_encode, Opcode_nop_Slot_f5_s3_base_encode, Opcode_nop_Slot_f11_s0_ld_encode, Opcode_nop_Slot_f11_s1_alu_encode, Opcode_nop_Slot_f11_s2_mul_encode, Opcode_nop_Slot_f11_s3_alu_encode, Opcode_nop_Slot_f11_s4_alu_encode, Opcode_nop_Slot_n1_s0_ldst_encode, Opcode_nop_Slot_n1_s1_none_encode, Opcode_nop_Slot_n1_s2_mul_encode, Opcode_nop_Slot_n2_s0_ldst_encode, Opcode_nop_Slot_n2_s1_ld_encode, Opcode_nop_Slot_n0_s0_ldst_encode, Opcode_nop_Slot_n0_s1_none_encode, Opcode_nop_Slot_n0_s2_none_encode, Opcode_nop_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_l32ex_encode_fns[] = { + Opcode_l32ex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s32ex_encode_fns[] = { + Opcode_s32ex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_getex_encode_fns[] = { + Opcode_getex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_clrex_encode_fns[] = { + Opcode_clrex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0, Opcode_s16i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_s16i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_s16i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_s16i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_s16i_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_s16i_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s16i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_s16i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0, Opcode_s32i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_s32i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_s32i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_s32i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_s32i_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_s32i_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { + Opcode_s32nb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0, Opcode_s8i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_s8i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_s8i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_s8i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_s8i_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_s8i_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s8i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0, Opcode_ssr_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ssr_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ssr_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ssr_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ssr_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_ssr_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, Opcode_ssr_Slot_f11_s2_mul_encode, 0, 0, Opcode_ssr_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ssr_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0, Opcode_ssl_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ssl_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ssl_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ssl_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ssl_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_ssl_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssl_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ssl_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0, Opcode_ssa8l_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ssa8l_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ssa8l_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ssa8l_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ssa8l_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_ssa8l_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssa8l_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ssa8l_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0, Opcode_ssai_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ssai_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ssai_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ssai_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ssai_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_ssai_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssai_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ssai_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_f0_s0_ldst_encode, Opcode_sll_Slot_f0_s1_ld_encode, Opcode_sll_Slot_f0_s2_mul_encode, 0, Opcode_sll_Slot_f1_s0_ldstalu_encode, Opcode_sll_Slot_f1_s1_ld_encode, 0, 0, Opcode_sll_Slot_f2_s0_ldst_encode, Opcode_sll_Slot_f2_s1_ld_encode, 0, 0, Opcode_sll_Slot_f3_s0_ldst_encode, Opcode_sll_Slot_f3_s1_ld_encode, Opcode_sll_Slot_f3_s2_mul_encode, 0, 0, Opcode_sll_Slot_f4_s0_ld_encode, Opcode_sll_Slot_f4_s1_ld_encode, 0, 0, Opcode_sll_Slot_f5_s0_base_encode, Opcode_sll_Slot_f5_s1_base_encode, Opcode_sll_Slot_f5_s2_base_encode, 0, Opcode_sll_Slot_f11_s0_ld_encode, Opcode_sll_Slot_f11_s1_alu_encode, Opcode_sll_Slot_f11_s2_mul_encode, 0, 0, Opcode_sll_Slot_n1_s0_ldst_encode, 0, Opcode_sll_Slot_n1_s2_mul_encode, Opcode_sll_Slot_n2_s0_ldst_encode, Opcode_sll_Slot_n2_s1_ld_encode, Opcode_sll_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0, Opcode_src_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_src_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_src_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_src_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_src_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_src_Slot_f5_s0_base_encode, 0, Opcode_src_Slot_f5_s2_base_encode, 0, 0, 0, Opcode_src_Slot_f11_s2_mul_encode, 0, 0, Opcode_src_Slot_n1_s0_ldst_encode, 0, 0, Opcode_src_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0, Opcode_srl_Slot_f0_s0_ldst_encode, Opcode_srl_Slot_f0_s1_ld_encode, Opcode_srl_Slot_f0_s2_mul_encode, 0, Opcode_srl_Slot_f1_s0_ldstalu_encode, Opcode_srl_Slot_f1_s1_ld_encode, 0, 0, Opcode_srl_Slot_f2_s0_ldst_encode, Opcode_srl_Slot_f2_s1_ld_encode, 0, 0, Opcode_srl_Slot_f3_s0_ldst_encode, Opcode_srl_Slot_f3_s1_ld_encode, Opcode_srl_Slot_f3_s2_mul_encode, 0, 0, Opcode_srl_Slot_f4_s0_ld_encode, Opcode_srl_Slot_f4_s1_ld_encode, 0, 0, Opcode_srl_Slot_f5_s0_base_encode, Opcode_srl_Slot_f5_s1_base_encode, Opcode_srl_Slot_f5_s2_base_encode, 0, Opcode_srl_Slot_f11_s0_ld_encode, Opcode_srl_Slot_f11_s1_alu_encode, Opcode_srl_Slot_f11_s2_mul_encode, 0, 0, Opcode_srl_Slot_n1_s0_ldst_encode, 0, Opcode_srl_Slot_n1_s2_mul_encode, Opcode_srl_Slot_n2_s0_ldst_encode, Opcode_srl_Slot_n2_s1_ld_encode, Opcode_srl_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_f0_s0_ldst_encode, Opcode_sra_Slot_f0_s1_ld_encode, Opcode_sra_Slot_f0_s2_mul_encode, 0, Opcode_sra_Slot_f1_s0_ldstalu_encode, Opcode_sra_Slot_f1_s1_ld_encode, 0, 0, Opcode_sra_Slot_f2_s0_ldst_encode, Opcode_sra_Slot_f2_s1_ld_encode, 0, 0, Opcode_sra_Slot_f3_s0_ldst_encode, Opcode_sra_Slot_f3_s1_ld_encode, Opcode_sra_Slot_f3_s2_mul_encode, 0, 0, Opcode_sra_Slot_f4_s0_ld_encode, Opcode_sra_Slot_f4_s1_ld_encode, 0, 0, Opcode_sra_Slot_f5_s0_base_encode, Opcode_sra_Slot_f5_s1_base_encode, Opcode_sra_Slot_f5_s2_base_encode, 0, Opcode_sra_Slot_f11_s0_ld_encode, Opcode_sra_Slot_f11_s1_alu_encode, Opcode_sra_Slot_f11_s2_mul_encode, 0, 0, Opcode_sra_Slot_n1_s0_ldst_encode, 0, 0, Opcode_sra_Slot_n2_s0_ldst_encode, Opcode_sra_Slot_n2_s1_ld_encode, Opcode_sra_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0, Opcode_slli_Slot_f0_s0_ldst_encode, Opcode_slli_Slot_f0_s1_ld_encode, Opcode_slli_Slot_f0_s2_mul_encode, 0, Opcode_slli_Slot_f1_s0_ldstalu_encode, Opcode_slli_Slot_f1_s1_ld_encode, 0, 0, Opcode_slli_Slot_f2_s0_ldst_encode, Opcode_slli_Slot_f2_s1_ld_encode, 0, 0, Opcode_slli_Slot_f3_s0_ldst_encode, Opcode_slli_Slot_f3_s1_ld_encode, Opcode_slli_Slot_f3_s2_mul_encode, 0, 0, Opcode_slli_Slot_f4_s0_ld_encode, Opcode_slli_Slot_f4_s1_ld_encode, 0, 0, Opcode_slli_Slot_f5_s0_base_encode, Opcode_slli_Slot_f5_s1_base_encode, Opcode_slli_Slot_f5_s2_base_encode, 0, Opcode_slli_Slot_f11_s0_ld_encode, Opcode_slli_Slot_f11_s1_alu_encode, Opcode_slli_Slot_f11_s2_mul_encode, 0, 0, Opcode_slli_Slot_n1_s0_ldst_encode, 0, 0, Opcode_slli_Slot_n2_s0_ldst_encode, Opcode_slli_Slot_n2_s1_ld_encode, Opcode_slli_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0, Opcode_srai_Slot_f0_s0_ldst_encode, Opcode_srai_Slot_f0_s1_ld_encode, Opcode_srai_Slot_f0_s2_mul_encode, 0, Opcode_srai_Slot_f1_s0_ldstalu_encode, Opcode_srai_Slot_f1_s1_ld_encode, 0, 0, Opcode_srai_Slot_f2_s0_ldst_encode, Opcode_srai_Slot_f2_s1_ld_encode, 0, 0, Opcode_srai_Slot_f3_s0_ldst_encode, Opcode_srai_Slot_f3_s1_ld_encode, Opcode_srai_Slot_f3_s2_mul_encode, 0, 0, Opcode_srai_Slot_f4_s0_ld_encode, Opcode_srai_Slot_f4_s1_ld_encode, 0, 0, Opcode_srai_Slot_f5_s0_base_encode, Opcode_srai_Slot_f5_s1_base_encode, Opcode_srai_Slot_f5_s2_base_encode, 0, Opcode_srai_Slot_f11_s0_ld_encode, Opcode_srai_Slot_f11_s1_alu_encode, Opcode_srai_Slot_f11_s2_mul_encode, 0, 0, Opcode_srai_Slot_n1_s0_ldst_encode, 0, 0, Opcode_srai_Slot_n2_s0_ldst_encode, Opcode_srai_Slot_n2_s1_ld_encode, Opcode_srai_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0, Opcode_srli_Slot_f0_s0_ldst_encode, Opcode_srli_Slot_f0_s1_ld_encode, Opcode_srli_Slot_f0_s2_mul_encode, 0, Opcode_srli_Slot_f1_s0_ldstalu_encode, Opcode_srli_Slot_f1_s1_ld_encode, 0, 0, Opcode_srli_Slot_f2_s0_ldst_encode, Opcode_srli_Slot_f2_s1_ld_encode, 0, 0, Opcode_srli_Slot_f3_s0_ldst_encode, Opcode_srli_Slot_f3_s1_ld_encode, Opcode_srli_Slot_f3_s2_mul_encode, 0, 0, Opcode_srli_Slot_f4_s0_ld_encode, Opcode_srli_Slot_f4_s1_ld_encode, 0, 0, Opcode_srli_Slot_f5_s0_base_encode, Opcode_srli_Slot_f5_s1_base_encode, Opcode_srli_Slot_f5_s2_base_encode, 0, Opcode_srli_Slot_f11_s0_ld_encode, Opcode_srli_Slot_f11_s1_alu_encode, Opcode_srli_Slot_f11_s2_mul_encode, 0, 0, Opcode_srli_Slot_n1_s0_ldst_encode, 0, 0, Opcode_srli_Slot_n2_s0_ldst_encode, Opcode_srli_Slot_n2_s1_ld_encode, Opcode_srli_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { + Opcode_rsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { + Opcode_wsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { + Opcode_xsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { + Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { + Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { + Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { + Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { + Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { + Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_mpucfg_encode_fns[] = { + Opcode_rsr_mpucfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_mpucfg_encode_fns[] = { + Opcode_wsr_mpucfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_gserr_encode_fns[] = { + Opcode_rsr_gserr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_gserr_encode_fns[] = { + Opcode_wsr_gserr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_gserr_encode_fns[] = { + Opcode_xsr_gserr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_salt_encode_fns[] = { + Opcode_salt_Slot_inst_encode, 0, 0, Opcode_salt_Slot_f0_s0_ldst_encode, Opcode_salt_Slot_f0_s1_ld_encode, 0, 0, Opcode_salt_Slot_f1_s0_ldstalu_encode, Opcode_salt_Slot_f1_s1_ld_encode, 0, 0, Opcode_salt_Slot_f2_s0_ldst_encode, Opcode_salt_Slot_f2_s1_ld_encode, 0, 0, Opcode_salt_Slot_f3_s0_ldst_encode, Opcode_salt_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_salt_Slot_f4_s0_ld_encode, Opcode_salt_Slot_f4_s1_ld_encode, 0, 0, Opcode_salt_Slot_f5_s0_base_encode, Opcode_salt_Slot_f5_s1_base_encode, Opcode_salt_Slot_f5_s2_base_encode, 0, Opcode_salt_Slot_f11_s0_ld_encode, Opcode_salt_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_salt_Slot_n1_s0_ldst_encode, 0, Opcode_salt_Slot_n1_s2_mul_encode, Opcode_salt_Slot_n2_s0_ldst_encode, Opcode_salt_Slot_n2_s1_ld_encode, Opcode_salt_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_saltu_encode_fns[] = { + Opcode_saltu_Slot_inst_encode, 0, 0, Opcode_saltu_Slot_f0_s0_ldst_encode, Opcode_saltu_Slot_f0_s1_ld_encode, 0, 0, Opcode_saltu_Slot_f1_s0_ldstalu_encode, Opcode_saltu_Slot_f1_s1_ld_encode, 0, 0, Opcode_saltu_Slot_f2_s0_ldst_encode, Opcode_saltu_Slot_f2_s1_ld_encode, 0, 0, Opcode_saltu_Slot_f3_s0_ldst_encode, Opcode_saltu_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_saltu_Slot_f4_s0_ld_encode, Opcode_saltu_Slot_f4_s1_ld_encode, 0, 0, Opcode_saltu_Slot_f5_s0_base_encode, Opcode_saltu_Slot_f5_s1_base_encode, Opcode_saltu_Slot_f5_s2_base_encode, 0, Opcode_saltu_Slot_f11_s0_ld_encode, Opcode_saltu_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_saltu_Slot_n1_s0_ldst_encode, 0, Opcode_saltu_Slot_n1_s2_mul_encode, Opcode_saltu_Slot_n2_s0_ldst_encode, Opcode_saltu_Slot_n2_s1_ld_encode, Opcode_saltu_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0, Opcode_mul16u_Slot_f0_s0_ldst_encode, Opcode_mul16u_Slot_f0_s1_ld_encode, 0, 0, Opcode_mul16u_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_mul16u_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_mul16u_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_mul16u_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_mul16u_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul16u_Slot_n1_s0_ldst_encode, 0, 0, Opcode_mul16u_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0, Opcode_mul16s_Slot_f0_s0_ldst_encode, Opcode_mul16s_Slot_f0_s1_ld_encode, 0, 0, Opcode_mul16s_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_mul16s_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_mul16s_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_mul16s_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_mul16s_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul16s_Slot_n1_s0_ldst_encode, 0, 0, Opcode_mul16s_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0, Opcode_mull_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_mull_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_mull_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_mull_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_mull_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_mull_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mull_Slot_n1_s0_ldst_encode, 0, 0, Opcode_mull_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = { + Opcode_muluh_Slot_inst_encode, 0, 0, Opcode_muluh_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_muluh_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_muluh_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_muluh_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_muluh_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_muluh_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_muluh_Slot_n1_s0_ldst_encode, 0, 0, Opcode_muluh_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = { + Opcode_mulsh_Slot_inst_encode, 0, 0, Opcode_mulsh_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_mulsh_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_mulsh_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_mulsh_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_mulsh_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_mulsh_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulsh_Slot_n1_s0_ldst_encode, 0, 0, Opcode_mulsh_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { + Opcode_lddr32_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { + Opcode_sddr32_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { + Opcode_andb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { + Opcode_andbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { + Opcode_orb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { + Opcode_orbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { + Opcode_xorb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { + Opcode_any4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { + Opcode_all4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { + Opcode_any8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { + Opcode_all8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { + Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { + Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { + Opcode_movf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { + Opcode_movt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { + Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { + Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { + Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { + Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { + Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { + Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_cacheadrdis_encode_fns[] = { + Opcode_wsr_cacheadrdis_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_cacheadrdis_encode_fns[] = { + Opcode_rsr_cacheadrdis_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_cacheadrdis_encode_fns[] = { + Opcode_xsr_cacheadrdis_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rptlb0_encode_fns[] = { + Opcode_rptlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_pptlb_encode_fns[] = { + Opcode_pptlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rptlb1_encode_fns[] = { + Opcode_rptlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wptlb_encode_fns[] = { + Opcode_wptlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_mpuenb_encode_fns[] = { + Opcode_rsr_mpuenb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_mpuenb_encode_fns[] = { + Opcode_wsr_mpuenb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_mpuenb_encode_fns[] = { + Opcode_xsr_mpuenb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { + Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { + Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { + Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { + Opcode_clamps_Slot_inst_encode, 0, 0, Opcode_clamps_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_clamps_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_clamps_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_clamps_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_clamps_Slot_f4_s0_ld_encode, Opcode_clamps_Slot_f4_s1_ld_encode, 0, 0, Opcode_clamps_Slot_f5_s0_base_encode, Opcode_clamps_Slot_f5_s1_base_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_clamps_Slot_n1_s0_ldst_encode, 0, Opcode_clamps_Slot_n1_s2_mul_encode, Opcode_clamps_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0, Opcode_min_Slot_f0_s0_ldst_encode, Opcode_min_Slot_f0_s1_ld_encode, 0, 0, Opcode_min_Slot_f1_s0_ldstalu_encode, Opcode_min_Slot_f1_s1_ld_encode, 0, 0, Opcode_min_Slot_f2_s0_ldst_encode, Opcode_min_Slot_f2_s1_ld_encode, 0, 0, Opcode_min_Slot_f3_s0_ldst_encode, Opcode_min_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_min_Slot_f4_s0_ld_encode, Opcode_min_Slot_f4_s1_ld_encode, 0, 0, Opcode_min_Slot_f5_s0_base_encode, Opcode_min_Slot_f5_s1_base_encode, Opcode_min_Slot_f5_s2_base_encode, 0, Opcode_min_Slot_f11_s0_ld_encode, Opcode_min_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_min_Slot_n1_s0_ldst_encode, 0, Opcode_min_Slot_n1_s2_mul_encode, Opcode_min_Slot_n2_s0_ldst_encode, Opcode_min_Slot_n2_s1_ld_encode, Opcode_min_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0, Opcode_max_Slot_f0_s0_ldst_encode, Opcode_max_Slot_f0_s1_ld_encode, 0, 0, Opcode_max_Slot_f1_s0_ldstalu_encode, Opcode_max_Slot_f1_s1_ld_encode, 0, 0, Opcode_max_Slot_f2_s0_ldst_encode, Opcode_max_Slot_f2_s1_ld_encode, 0, 0, Opcode_max_Slot_f3_s0_ldst_encode, Opcode_max_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_max_Slot_f4_s0_ld_encode, Opcode_max_Slot_f4_s1_ld_encode, 0, 0, Opcode_max_Slot_f5_s0_base_encode, Opcode_max_Slot_f5_s1_base_encode, Opcode_max_Slot_f5_s2_base_encode, 0, Opcode_max_Slot_f11_s0_ld_encode, Opcode_max_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_max_Slot_n1_s0_ldst_encode, 0, Opcode_max_Slot_n1_s2_mul_encode, Opcode_max_Slot_n2_s0_ldst_encode, Opcode_max_Slot_n2_s1_ld_encode, Opcode_max_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0, Opcode_minu_Slot_f0_s0_ldst_encode, Opcode_minu_Slot_f0_s1_ld_encode, 0, 0, Opcode_minu_Slot_f1_s0_ldstalu_encode, Opcode_minu_Slot_f1_s1_ld_encode, 0, 0, Opcode_minu_Slot_f2_s0_ldst_encode, Opcode_minu_Slot_f2_s1_ld_encode, 0, 0, Opcode_minu_Slot_f3_s0_ldst_encode, Opcode_minu_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_minu_Slot_f4_s0_ld_encode, Opcode_minu_Slot_f4_s1_ld_encode, 0, 0, Opcode_minu_Slot_f5_s0_base_encode, Opcode_minu_Slot_f5_s1_base_encode, Opcode_minu_Slot_f5_s2_base_encode, 0, Opcode_minu_Slot_f11_s0_ld_encode, Opcode_minu_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_minu_Slot_n1_s0_ldst_encode, 0, Opcode_minu_Slot_n1_s2_mul_encode, Opcode_minu_Slot_n2_s0_ldst_encode, Opcode_minu_Slot_n2_s1_ld_encode, Opcode_minu_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0, Opcode_maxu_Slot_f0_s0_ldst_encode, Opcode_maxu_Slot_f0_s1_ld_encode, 0, 0, Opcode_maxu_Slot_f1_s0_ldstalu_encode, Opcode_maxu_Slot_f1_s1_ld_encode, 0, 0, Opcode_maxu_Slot_f2_s0_ldst_encode, Opcode_maxu_Slot_f2_s1_ld_encode, 0, 0, Opcode_maxu_Slot_f3_s0_ldst_encode, Opcode_maxu_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_maxu_Slot_f4_s0_ld_encode, Opcode_maxu_Slot_f4_s1_ld_encode, 0, 0, Opcode_maxu_Slot_f5_s0_base_encode, Opcode_maxu_Slot_f5_s1_base_encode, Opcode_maxu_Slot_f5_s2_base_encode, 0, Opcode_maxu_Slot_f11_s0_ld_encode, Opcode_maxu_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_maxu_Slot_n1_s0_ldst_encode, 0, Opcode_maxu_Slot_n1_s2_mul_encode, Opcode_maxu_Slot_n2_s0_ldst_encode, Opcode_maxu_Slot_n2_s1_ld_encode, Opcode_maxu_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0, Opcode_nsa_Slot_f0_s0_ldst_encode, Opcode_nsa_Slot_f0_s1_ld_encode, 0, 0, Opcode_nsa_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_nsa_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_nsa_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_nsa_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_nsa_Slot_f5_s0_base_encode, 0, Opcode_nsa_Slot_f5_s2_base_encode, 0, 0, 0, 0, 0, 0, Opcode_nsa_Slot_n1_s0_ldst_encode, 0, 0, Opcode_nsa_Slot_n2_s0_ldst_encode, Opcode_nsa_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0, Opcode_nsau_Slot_f0_s0_ldst_encode, Opcode_nsau_Slot_f0_s1_ld_encode, 0, 0, Opcode_nsau_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_nsau_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_nsau_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_nsau_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_nsau_Slot_f5_s0_base_encode, 0, Opcode_nsau_Slot_f5_s2_base_encode, 0, 0, 0, 0, 0, 0, Opcode_nsau_Slot_n1_s0_ldst_encode, 0, 0, Opcode_nsau_Slot_n2_s0_ldst_encode, Opcode_nsau_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0, Opcode_sext_Slot_f0_s0_ldst_encode, Opcode_sext_Slot_f0_s1_ld_encode, 0, 0, Opcode_sext_Slot_f1_s0_ldstalu_encode, Opcode_sext_Slot_f1_s1_ld_encode, 0, 0, Opcode_sext_Slot_f2_s0_ldst_encode, Opcode_sext_Slot_f2_s1_ld_encode, 0, 0, Opcode_sext_Slot_f3_s0_ldst_encode, Opcode_sext_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_sext_Slot_f4_s0_ld_encode, Opcode_sext_Slot_f4_s1_ld_encode, 0, 0, Opcode_sext_Slot_f5_s0_base_encode, Opcode_sext_Slot_f5_s1_base_encode, 0, 0, Opcode_sext_Slot_f11_s0_ld_encode, Opcode_sext_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_sext_Slot_n1_s0_ldst_encode, 0, 0, Opcode_sext_Slot_n2_s0_ldst_encode, Opcode_sext_Slot_n2_s1_ld_encode, Opcode_sext_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { + Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { + Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { + Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { + Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { + Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { + Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { + Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_eraccess_encode_fns[] = { + Opcode_rsr_eraccess_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_eraccess_encode_fns[] = { + Opcode_wsr_eraccess_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_eraccess_encode_fns[] = { + Opcode_xsr_eraccess_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { + Opcode_rer_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { + Opcode_wer_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_beqz_w15_encode_fns[] = { + 0, 0, 0, Opcode_beqz_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_beqz_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnez_w15_encode_fns[] = { + 0, 0, 0, Opcode_bnez_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bnez_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgez_w15_encode_fns[] = { + 0, 0, 0, Opcode_bgez_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bgez_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bltz_w15_encode_fns[] = { + 0, 0, 0, Opcode_bltz_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bltz_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_beqi_w15_encode_fns[] = { + 0, 0, 0, Opcode_beqi_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_beqi_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnei_w15_encode_fns[] = { + 0, 0, 0, Opcode_bnei_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bnei_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgei_w15_encode_fns[] = { + 0, 0, 0, Opcode_bgei_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bgei_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_blti_w15_encode_fns[] = { + 0, 0, 0, Opcode_blti_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_blti_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_blti_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgeui_w15_encode_fns[] = { + 0, 0, 0, Opcode_bgeui_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bgeui_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bltui_w15_encode_fns[] = { + 0, 0, 0, Opcode_bltui_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bltui_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbci_w15_encode_fns[] = { + 0, 0, 0, Opcode_bbci_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bbci_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbsi_w15_encode_fns[] = { + 0, 0, 0, Opcode_bbsi_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bbsi_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_beq_w15_encode_fns[] = { + 0, 0, 0, Opcode_beq_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_beq_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_beq_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bne_w15_encode_fns[] = { + 0, 0, 0, Opcode_bne_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bne_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bne_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bge_w15_encode_fns[] = { + 0, 0, 0, Opcode_bge_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bge_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bge_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_blt_w15_encode_fns[] = { + 0, 0, 0, Opcode_blt_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_blt_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_blt_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgeu_w15_encode_fns[] = { + 0, 0, 0, Opcode_bgeu_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bgeu_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bltu_w15_encode_fns[] = { + 0, 0, 0, Opcode_bltu_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bltu_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bany_w15_encode_fns[] = { + 0, 0, 0, Opcode_bany_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bany_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bany_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnone_w15_encode_fns[] = { + 0, 0, 0, Opcode_bnone_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bnone_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ball_w15_encode_fns[] = { + 0, 0, 0, Opcode_ball_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ball_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_ball_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnall_w15_encode_fns[] = { + 0, 0, 0, Opcode_bnall_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bnall_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbc_w15_encode_fns[] = { + 0, 0, 0, Opcode_bbc_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bbc_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbs_w15_encode_fns[] = { + 0, 0, 0, Opcode_bbs_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bbs_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_mtk_andpopc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mtk_andpopc_Slot_f3_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mtk_andpopc_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_iq_tie2apb_inq0_pop_encode_fns[] = { + Opcode_iq_tie2apb_inq0_pop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_iq_tie2apb_inq0_is_ready_encode_fns[] = { + Opcode_iq_tie2apb_inq0_is_ready_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_iq_tie2apb_inq0_nonblocking_peek_encode_fns[] = { + Opcode_iq_tie2apb_inq0_nonblocking_peek_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_iq_tie2apb_inq0_nonblocking_pop_encode_fns[] = { + Opcode_iq_tie2apb_inq0_nonblocking_pop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_iq_tie2apb_inq0_blocking_peek_encode_fns[] = { + Opcode_iq_tie2apb_inq0_blocking_peek_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_oq_tie2apb_outq0_push_read_encode_fns[] = { + Opcode_oq_tie2apb_outq0_push_read_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_oq_tie2apb_outq0_push_write_encode_fns[] = { + Opcode_oq_tie2apb_outq0_push_write_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_oq_tie2apb_outq0_is_ready_encode_fns[] = { + Opcode_oq_tie2apb_outq0_is_ready_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_oq_tie2apb_outq0_nonblocking_push_read_encode_fns[] = { + Opcode_oq_tie2apb_outq0_nonblocking_push_read_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_oq_tie2apb_outq0_nonblocking_push_write_encode_fns[] = { + Opcode_oq_tie2apb_outq0_nonblocking_push_write_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rur_apb_pipe_encode_fns[] = { + Opcode_rur_apb_pipe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wur_apb_pipe_encode_fns[] = { + Opcode_wur_apb_pipe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +int num_bypass_groups() { + return 0; +} + +int num_bypass_group_chunks() { + return 0; +} + +uint32 *bypass_entry(int i) { + return 0; +} + + +/* Opcode table. */ + +static xtensa_opcode_internal opcodes[] = { + { "ivp_repnx16", ICLASS_IVP_REPNX16, + 0, + Opcode_ivp_repnx16_encode_fns, 0, 0 }, + { "ivp_selsnx16", ICLASS_IVP_SELSNX16, + 0, + Opcode_ivp_selsnx16_encode_fns, 0, 0 }, + { "ivp_rep2nx8", ICLASS_IVP_REP2NX8, + 0, + Opcode_ivp_rep2nx8_encode_fns, 0, 0 }, + { "ivp_sels2nx8", ICLASS_IVP_SELS2NX8, + 0, + Opcode_ivp_sels2nx8_encode_fns, 0, 0 }, + { "ivp_repn_2x32", ICLASS_IVP_REPN_2X32, + 0, + Opcode_ivp_repn_2x32_encode_fns, 0, 0 }, + { "ivp_selsn_2x32", ICLASS_IVP_SELSN_2X32, + 0, + Opcode_ivp_selsn_2x32_encode_fns, 0, 0 }, + { "ivp_ext0ib", ICLASS_IVP_EXT0IB, + 0, + Opcode_ivp_ext0ib_encode_fns, 0, 0 }, + { "ivp_notb", ICLASS_IVP_NOTB, + 0, + Opcode_ivp_notb_encode_fns, 0, 0 }, + { "ivp_andb", ICLASS_IVP_ANDB, + 0, + Opcode_ivp_andb_encode_fns, 0, 0 }, + { "ivp_orb", ICLASS_IVP_ORB, + 0, + Opcode_ivp_orb_encode_fns, 0, 0 }, + { "ivp_xorb", ICLASS_IVP_XORB, + 0, + Opcode_ivp_xorb_encode_fns, 0, 0 }, + { "ivp_andnotb", ICLASS_IVP_ANDNOTB, + 0, + Opcode_ivp_andnotb_encode_fns, 0, 0 }, + { "ivp_mb", ICLASS_IVP_MB, + 0, + Opcode_ivp_mb_encode_fns, 0, 0 }, + { "ivp_ltrn", ICLASS_IVP_LTRN, + 0, + Opcode_ivp_ltrn_encode_fns, 0, 0 }, + { "ivp_ltrni", ICLASS_IVP_LTRNI, + 0, + Opcode_ivp_ltrni_encode_fns, 0, 0 }, + { "ivp_lbn_i", ICLASS_IVP_LBN_I, + 0, + Opcode_ivp_lbn_i_encode_fns, 0, 0 }, + { "ivp_lbn_ip", ICLASS_IVP_LBN_IP, + 0, + Opcode_ivp_lbn_ip_encode_fns, 0, 0 }, + { "ivp_sbn_i", ICLASS_IVP_SBN_I, + 0, + Opcode_ivp_sbn_i_encode_fns, 0, 0 }, + { "ivp_sbn_ip", ICLASS_IVP_SBN_IP, + 0, + Opcode_ivp_sbn_ip_encode_fns, 0, 0 }, + { "ivp_lsnx16_i", ICLASS_IVP_LSNX16_I, + 0, + Opcode_ivp_lsnx16_i_encode_fns, 0, 0 }, + { "ivp_lsnx16_ip", ICLASS_IVP_LSNX16_IP, + 0, + Opcode_ivp_lsnx16_ip_encode_fns, 0, 0 }, + { "ivp_lsnx16_x", ICLASS_IVP_LSNX16_X, + 0, + Opcode_ivp_lsnx16_x_encode_fns, 0, 0 }, + { "ivp_lsnx16_xp", ICLASS_IVP_LSNX16_XP, + 0, + Opcode_ivp_lsnx16_xp_encode_fns, 0, 0 }, + { "ivp_movbrbv", ICLASS_IVP_MOVBRBV, + 0, + Opcode_ivp_movbrbv_encode_fns, 0, 0 }, + { "ivp_movbvbr", ICLASS_IVP_MOVBVBR, + 0, + Opcode_ivp_movbvbr_encode_fns, 0, 0 }, + { "ivp_joinb", ICLASS_IVP_JOINB, + 0, + Opcode_ivp_joinb_encode_fns, 0, 0 }, + { "ivp_ltrn_2", ICLASS_IVP_LTRN_2, + 0, + Opcode_ivp_ltrn_2_encode_fns, 0, 0 }, + { "ivp_ltrn_2i", ICLASS_IVP_LTRN_2I, + 0, + Opcode_ivp_ltrn_2i_encode_fns, 0, 0 }, + { "ivp_lbn_2_i", ICLASS_IVP_LBN_2_I, + 0, + Opcode_ivp_lbn_2_i_encode_fns, 0, 0 }, + { "ivp_lbn_2_ip", ICLASS_IVP_LBN_2_IP, + 0, + Opcode_ivp_lbn_2_ip_encode_fns, 0, 0 }, + { "ivp_sbn_2_i", ICLASS_IVP_SBN_2_I, + 0, + Opcode_ivp_sbn_2_i_encode_fns, 0, 0 }, + { "ivp_sbn_2_ip", ICLASS_IVP_SBN_2_IP, + 0, + Opcode_ivp_sbn_2_ip_encode_fns, 0, 0 }, + { "ivp_lv2nx8_i", ICLASS_IVP_LV2NX8_I, + 0, + Opcode_ivp_lv2nx8_i_encode_fns, 0, 0 }, + { "ivp_lv2nx8_ip", ICLASS_IVP_LV2NX8_IP, + 0, + Opcode_ivp_lv2nx8_ip_encode_fns, 0, 0 }, + { "ivp_lv2nx8_x", ICLASS_IVP_LV2NX8_X, + 0, + Opcode_ivp_lv2nx8_x_encode_fns, 0, 0 }, + { "ivp_lv2nx8_xp", ICLASS_IVP_LV2NX8_XP, + 0, + Opcode_ivp_lv2nx8_xp_encode_fns, 0, 0 }, + { "ivp_sv2nx8_i", ICLASS_IVP_SV2NX8_I, + 0, + Opcode_ivp_sv2nx8_i_encode_fns, 0, 0 }, + { "ivp_sv2nx8_ip", ICLASS_IVP_SV2NX8_IP, + 0, + Opcode_ivp_sv2nx8_ip_encode_fns, 0, 0 }, + { "ivp_sv2nx8_x", ICLASS_IVP_SV2NX8_X, + 0, + Opcode_ivp_sv2nx8_x_encode_fns, 0, 0 }, + { "ivp_sv2nx8_xp", ICLASS_IVP_SV2NX8_XP, + 0, + Opcode_ivp_sv2nx8_xp_encode_fns, 0, 0 }, + { "ivp_ssnx16_i", ICLASS_IVP_SSNX16_I, + 0, + Opcode_ivp_ssnx16_i_encode_fns, 0, 0 }, + { "ivp_ssnx16_ip", ICLASS_IVP_SSNX16_IP, + 0, + Opcode_ivp_ssnx16_ip_encode_fns, 0, 0 }, + { "ivp_ssnx16_x", ICLASS_IVP_SSNX16_X, + 0, + Opcode_ivp_ssnx16_x_encode_fns, 0, 0 }, + { "ivp_ssnx16_xp", ICLASS_IVP_SSNX16_XP, + 0, + Opcode_ivp_ssnx16_xp_encode_fns, 0, 0 }, + { "ivp_movva16", ICLASS_IVP_MOVVA16, + 0, + Opcode_ivp_movva16_encode_fns, 0, 0 }, + { "ivp_movvv", ICLASS_IVP_MOVVV, + 0, + Opcode_ivp_movvv_encode_fns, 0, 0 }, + { "ivp_sllinx16", ICLASS_IVP_SLLINX16, + 0, + Opcode_ivp_sllinx16_encode_fns, 0, 0 }, + { "ivp_slsinx16", ICLASS_IVP_SLSINX16, + 0, + Opcode_ivp_slsinx16_encode_fns, 0, 0 }, + { "ivp_srainx16", ICLASS_IVP_SRAINX16, + 0, + Opcode_ivp_srainx16_encode_fns, 0, 0 }, + { "ivp_srlinx16", ICLASS_IVP_SRLINX16, + 0, + Opcode_ivp_srlinx16_encode_fns, 0, 0 }, + { "ivp_sllnx16", ICLASS_IVP_SLLNX16, + 0, + Opcode_ivp_sllnx16_encode_fns, 0, 0 }, + { "ivp_srlnx16", ICLASS_IVP_SRLNX16, + 0, + Opcode_ivp_srlnx16_encode_fns, 0, 0 }, + { "ivp_slanx16", ICLASS_IVP_SLANX16, + 0, + Opcode_ivp_slanx16_encode_fns, 0, 0 }, + { "ivp_sranx16", ICLASS_IVP_SRANX16, + 0, + Opcode_ivp_sranx16_encode_fns, 0, 0 }, + { "ivp_slsnx16", ICLASS_IVP_SLSNX16, + 0, + Opcode_ivp_slsnx16_encode_fns, 0, 0 }, + { "ivp_srsnx16", ICLASS_IVP_SRSNX16, + 0, + Opcode_ivp_srsnx16_encode_fns, 0, 0 }, + { "ivp_xor2nx8", ICLASS_IVP_XOR2NX8, + 0, + Opcode_ivp_xor2nx8_encode_fns, 0, 0 }, + { "ivp_and2nx8", ICLASS_IVP_AND2NX8, + 0, + Opcode_ivp_and2nx8_encode_fns, 0, 0 }, + { "ivp_or2nx8", ICLASS_IVP_OR2NX8, + 0, + Opcode_ivp_or2nx8_encode_fns, 0, 0 }, + { "ivp_not2nx8", ICLASS_IVP_NOT2NX8, + 0, + Opcode_ivp_not2nx8_encode_fns, 0, 0 }, + { "ivp_addnx16", ICLASS_IVP_ADDNX16, + 0, + Opcode_ivp_addnx16_encode_fns, 0, 0 }, + { "ivp_subnx16", ICLASS_IVP_SUBNX16, + 0, + Opcode_ivp_subnx16_encode_fns, 0, 0 }, + { "ivp_negnx16", ICLASS_IVP_NEGNX16, + 0, + Opcode_ivp_negnx16_encode_fns, 0, 0 }, + { "ivp_minnx16", ICLASS_IVP_MINNX16, + 0, + Opcode_ivp_minnx16_encode_fns, 0, 0 }, + { "ivp_minunx16", ICLASS_IVP_MINUNX16, + 0, + Opcode_ivp_minunx16_encode_fns, 0, 0 }, + { "ivp_maxnx16", ICLASS_IVP_MAXNX16, + 0, + Opcode_ivp_maxnx16_encode_fns, 0, 0 }, + { "ivp_maxunx16", ICLASS_IVP_MAXUNX16, + 0, + Opcode_ivp_maxunx16_encode_fns, 0, 0 }, + { "ivp_mulsgnnx16", ICLASS_IVP_MULSGNNX16, + 0, + Opcode_ivp_mulsgnnx16_encode_fns, 0, 0 }, + { "ivp_nsanx16", ICLASS_IVP_NSANX16, + 0, + Opcode_ivp_nsanx16_encode_fns, 0, 0 }, + { "ivp_nsaunx16", ICLASS_IVP_NSAUNX16, + 0, + Opcode_ivp_nsaunx16_encode_fns, 0, 0 }, + { "ivp_ltnx16", ICLASS_IVP_LTNX16, + 0, + Opcode_ivp_ltnx16_encode_fns, 0, 0 }, + { "ivp_lenx16", ICLASS_IVP_LENX16, + 0, + Opcode_ivp_lenx16_encode_fns, 0, 0 }, + { "ivp_eqnx16", ICLASS_IVP_EQNX16, + 0, + Opcode_ivp_eqnx16_encode_fns, 0, 0 }, + { "ivp_neqnx16", ICLASS_IVP_NEQNX16, + 0, + Opcode_ivp_neqnx16_encode_fns, 0, 0 }, + { "ivp_ltunx16", ICLASS_IVP_LTUNX16, + 0, + Opcode_ivp_ltunx16_encode_fns, 0, 0 }, + { "ivp_leunx16", ICLASS_IVP_LEUNX16, + 0, + Opcode_ivp_leunx16_encode_fns, 0, 0 }, + { "ivp_raddnx16", ICLASS_IVP_RADDNX16, + 0, + Opcode_ivp_raddnx16_encode_fns, 0, 0 }, + { "ivp_rmaxnx16", ICLASS_IVP_RMAXNX16, + 0, + Opcode_ivp_rmaxnx16_encode_fns, 0, 0 }, + { "ivp_rminnx16", ICLASS_IVP_RMINNX16, + 0, + Opcode_ivp_rminnx16_encode_fns, 0, 0 }, + { "ivp_rmaxunx16", ICLASS_IVP_RMAXUNX16, + 0, + Opcode_ivp_rmaxunx16_encode_fns, 0, 0 }, + { "ivp_rminunx16", ICLASS_IVP_RMINUNX16, + 0, + Opcode_ivp_rminunx16_encode_fns, 0, 0 }, + { "ivp_rbminnx16", ICLASS_IVP_RBMINNX16, + 0, + Opcode_ivp_rbminnx16_encode_fns, 0, 0 }, + { "ivp_rbmaxnx16", ICLASS_IVP_RBMAXNX16, + 0, + Opcode_ivp_rbmaxnx16_encode_fns, 0, 0 }, + { "ivp_bmaxnx16", ICLASS_IVP_BMAXNX16, + 0, + Opcode_ivp_bmaxnx16_encode_fns, 0, 0 }, + { "ivp_bminnx16", ICLASS_IVP_BMINNX16, + 0, + Opcode_ivp_bminnx16_encode_fns, 0, 0 }, + { "ivp_mov2nx8t", ICLASS_IVP_MOV2NX8T, + 0, + Opcode_ivp_mov2nx8t_encode_fns, 0, 0 }, + { "ivp_mulanx16packl", ICLASS_IVP_MULANX16PACKL, + 0, + Opcode_ivp_mulanx16packl_encode_fns, 0, 0 }, + { "ivp_mulanx16packq", ICLASS_IVP_MULANX16PACKQ, + 0, + Opcode_ivp_mulanx16packq_encode_fns, 0, 0 }, + { "ivp_mulsnx16packl", ICLASS_IVP_MULSNX16PACKL, + 0, + Opcode_ivp_mulsnx16packl_encode_fns, 0, 0 }, + { "ivp_mulsnx16packq", ICLASS_IVP_MULSNX16PACKQ, + 0, + Opcode_ivp_mulsnx16packq_encode_fns, 0, 0 }, + { "ivp_addsnx16", ICLASS_IVP_ADDSNX16, + 0, + Opcode_ivp_addsnx16_encode_fns, 0, 0 }, + { "ivp_subsnx16", ICLASS_IVP_SUBSNX16, + 0, + Opcode_ivp_subsnx16_encode_fns, 0, 0 }, + { "ivp_negsnx16", ICLASS_IVP_NEGSNX16, + 0, + Opcode_ivp_negsnx16_encode_fns, 0, 0 }, + { "ivp_lv2nx8t_i", ICLASS_IVP_LV2NX8T_I, + 0, + Opcode_ivp_lv2nx8t_i_encode_fns, 0, 0 }, + { "ivp_lv2nx8t_ip", ICLASS_IVP_LV2NX8T_IP, + 0, + Opcode_ivp_lv2nx8t_ip_encode_fns, 0, 0 }, + { "ivp_lv2nx8t_x", ICLASS_IVP_LV2NX8T_X, + 0, + Opcode_ivp_lv2nx8t_x_encode_fns, 0, 0 }, + { "ivp_lv2nx8t_xp", ICLASS_IVP_LV2NX8T_XP, + 0, + Opcode_ivp_lv2nx8t_xp_encode_fns, 0, 0 }, + { "ivp_sv2nx8t_i", ICLASS_IVP_SV2NX8T_I, + 0, + Opcode_ivp_sv2nx8t_i_encode_fns, 0, 0 }, + { "ivp_sv2nx8t_ip", ICLASS_IVP_SV2NX8T_IP, + 0, + Opcode_ivp_sv2nx8t_ip_encode_fns, 0, 0 }, + { "ivp_sv2nx8t_x", ICLASS_IVP_SV2NX8T_X, + 0, + Opcode_ivp_sv2nx8t_x_encode_fns, 0, 0 }, + { "ivp_sv2nx8t_xp", ICLASS_IVP_SV2NX8T_XP, + 0, + Opcode_ivp_sv2nx8t_xp_encode_fns, 0, 0 }, + { "ivp_raddnx16t", ICLASS_IVP_RADDNX16T, + 0, + Opcode_ivp_raddnx16t_encode_fns, 0, 0 }, + { "ivp_rmaxnx16t", ICLASS_IVP_RMAXNX16T, + 0, + Opcode_ivp_rmaxnx16t_encode_fns, 0, 0 }, + { "ivp_rminnx16t", ICLASS_IVP_RMINNX16T, + 0, + Opcode_ivp_rminnx16t_encode_fns, 0, 0 }, + { "ivp_rmaxunx16t", ICLASS_IVP_RMAXUNX16T, + 0, + Opcode_ivp_rmaxunx16t_encode_fns, 0, 0 }, + { "ivp_rminunx16t", ICLASS_IVP_RMINUNX16T, + 0, + Opcode_ivp_rminunx16t_encode_fns, 0, 0 }, + { "ivp_addnx16t", ICLASS_IVP_ADDNX16T, + 0, + Opcode_ivp_addnx16t_encode_fns, 0, 0 }, + { "ivp_subnx16t", ICLASS_IVP_SUBNX16T, + 0, + Opcode_ivp_subnx16t_encode_fns, 0, 0 }, + { "ivp_negnx16t", ICLASS_IVP_NEGNX16T, + 0, + Opcode_ivp_negnx16t_encode_fns, 0, 0 }, + { "ivp_maxnx16t", ICLASS_IVP_MAXNX16T, + 0, + Opcode_ivp_maxnx16t_encode_fns, 0, 0 }, + { "ivp_minnx16t", ICLASS_IVP_MINNX16T, + 0, + Opcode_ivp_minnx16t_encode_fns, 0, 0 }, + { "ivp_maxunx16t", ICLASS_IVP_MAXUNX16T, + 0, + Opcode_ivp_maxunx16t_encode_fns, 0, 0 }, + { "ivp_minunx16t", ICLASS_IVP_MINUNX16T, + 0, + Opcode_ivp_minunx16t_encode_fns, 0, 0 }, + { "ivp_mulanx16packlt", ICLASS_IVP_MULANX16PACKLT, + 0, + Opcode_ivp_mulanx16packlt_encode_fns, 0, 0 }, + { "ivp_mulanx16packqt", ICLASS_IVP_MULANX16PACKQT, + 0, + Opcode_ivp_mulanx16packqt_encode_fns, 0, 0 }, + { "ivp_addsnx16t", ICLASS_IVP_ADDSNX16T, + 0, + Opcode_ivp_addsnx16t_encode_fns, 0, 0 }, + { "ivp_subsnx16t", ICLASS_IVP_SUBSNX16T, + 0, + Opcode_ivp_subsnx16t_encode_fns, 0, 0 }, + { "ivp_negsnx16t", ICLASS_IVP_NEGSNX16T, + 0, + Opcode_ivp_negsnx16t_encode_fns, 0, 0 }, + { "ivp_lalign_i", ICLASS_IVP_LALIGN_I, + 0, + Opcode_ivp_lalign_i_encode_fns, 0, 0 }, + { "ivp_lalign_ip", ICLASS_IVP_LALIGN_IP, + 0, + Opcode_ivp_lalign_ip_encode_fns, 0, 0 }, + { "ivp_salign_i", ICLASS_IVP_SALIGN_I, + 0, + Opcode_ivp_salign_i_encode_fns, 0, 0 }, + { "ivp_salign_ip", ICLASS_IVP_SALIGN_IP, + 0, + Opcode_ivp_salign_ip_encode_fns, 0, 0 }, + { "ivp_la_pp", ICLASS_IVP_LA_PP, + 0, + Opcode_ivp_la_pp_encode_fns, 0, 0 }, + { "ivp_sapos_fp", ICLASS_IVP_SAPOS_FP, + 0, + Opcode_ivp_sapos_fp_encode_fns, 0, 0 }, + { "ivp_malign", ICLASS_IVP_MALIGN, + 0, + Opcode_ivp_malign_encode_fns, 0, 0 }, + { "ivp_zalign", ICLASS_IVP_ZALIGN, + 0, + Opcode_ivp_zalign_encode_fns, 0, 0 }, + { "ivp_la2nx8_ip", ICLASS_IVP_LA2NX8_IP, + 0, + Opcode_ivp_la2nx8_ip_encode_fns, 0, 0 }, + { "ivp_sa2nx8_ip", ICLASS_IVP_SA2NX8_IP, + 0, + Opcode_ivp_sa2nx8_ip_encode_fns, 0, 0 }, + { "ivp_lav2nx8_xp", ICLASS_IVP_LAV2NX8_XP, + 0, + Opcode_ivp_lav2nx8_xp_encode_fns, 0, 0 }, + { "ivp_sav2nx8_xp", ICLASS_IVP_SAV2NX8_XP, + 0, + Opcode_ivp_sav2nx8_xp_encode_fns, 0, 0 }, + { "ivp_selnx16", ICLASS_IVP_SELNX16, + 0, + Opcode_ivp_selnx16_encode_fns, 0, 0 }, + { "ivp_shflnx16", ICLASS_IVP_SHFLNX16, + 0, + Opcode_ivp_shflnx16_encode_fns, 0, 0 }, + { "ivp_movpint16", ICLASS_IVP_MOVPINT16, + 0, + Opcode_ivp_movpint16_encode_fns, 0, 0 }, + { "ivp_movpa16", ICLASS_IVP_MOVPA16, + 0, + Opcode_ivp_movpa16_encode_fns, 0, 0 }, + { "ivp_mulnx16packp", ICLASS_IVP_MULNX16PACKP, + 0, + Opcode_ivp_mulnx16packp_encode_fns, 0, 0 }, + { "ivp_mulanx16packp", ICLASS_IVP_MULANX16PACKP, + 0, + Opcode_ivp_mulanx16packp_encode_fns, 0, 0 }, + { "ivp_mulsnx16packp", ICLASS_IVP_MULSNX16PACKP, + 0, + Opcode_ivp_mulsnx16packp_encode_fns, 0, 0 }, + { "ivp_mulanx16packpt", ICLASS_IVP_MULANX16PACKPT, + 0, + Opcode_ivp_mulanx16packpt_encode_fns, 0, 0 }, + { "ivp_addmod16u", ICLASS_IVP_ADDMOD16U, + 0, + Opcode_ivp_addmod16u_encode_fns, 0, 0 }, + { "ivp_lvnx8s_i", ICLASS_IVP_LVNX8S_I, + 0, + Opcode_ivp_lvnx8s_i_encode_fns, 0, 0 }, + { "ivp_lvnx8s_ip", ICLASS_IVP_LVNX8S_IP, + 0, + Opcode_ivp_lvnx8s_ip_encode_fns, 0, 0 }, + { "ivp_lvnx8s_x", ICLASS_IVP_LVNX8S_X, + 0, + Opcode_ivp_lvnx8s_x_encode_fns, 0, 0 }, + { "ivp_lvnx8s_xp", ICLASS_IVP_LVNX8S_XP, + 0, + Opcode_ivp_lvnx8s_xp_encode_fns, 0, 0 }, + { "ivp_lvnx8u_i", ICLASS_IVP_LVNX8U_I, + 0, + Opcode_ivp_lvnx8u_i_encode_fns, 0, 0 }, + { "ivp_lvnx8u_ip", ICLASS_IVP_LVNX8U_IP, + 0, + Opcode_ivp_lvnx8u_ip_encode_fns, 0, 0 }, + { "ivp_lvnx8u_x", ICLASS_IVP_LVNX8U_X, + 0, + Opcode_ivp_lvnx8u_x_encode_fns, 0, 0 }, + { "ivp_lvnx8u_xp", ICLASS_IVP_LVNX8U_XP, + 0, + Opcode_ivp_lvnx8u_xp_encode_fns, 0, 0 }, + { "ivp_svnx8u_i", ICLASS_IVP_SVNX8U_I, + 0, + Opcode_ivp_svnx8u_i_encode_fns, 0, 0 }, + { "ivp_svnx8u_ip", ICLASS_IVP_SVNX8U_IP, + 0, + Opcode_ivp_svnx8u_ip_encode_fns, 0, 0 }, + { "ivp_svnx8u_x", ICLASS_IVP_SVNX8U_X, + 0, + Opcode_ivp_svnx8u_x_encode_fns, 0, 0 }, + { "ivp_svnx8u_xp", ICLASS_IVP_SVNX8U_XP, + 0, + Opcode_ivp_svnx8u_xp_encode_fns, 0, 0 }, + { "ivp_lvnx8st_i", ICLASS_IVP_LVNX8ST_I, + 0, + Opcode_ivp_lvnx8st_i_encode_fns, 0, 0 }, + { "ivp_lvnx8st_ip", ICLASS_IVP_LVNX8ST_IP, + 0, + Opcode_ivp_lvnx8st_ip_encode_fns, 0, 0 }, + { "ivp_lvnx8st_x", ICLASS_IVP_LVNX8ST_X, + 0, + Opcode_ivp_lvnx8st_x_encode_fns, 0, 0 }, + { "ivp_lvnx8st_xp", ICLASS_IVP_LVNX8ST_XP, + 0, + Opcode_ivp_lvnx8st_xp_encode_fns, 0, 0 }, + { "ivp_lvnx8ut_i", ICLASS_IVP_LVNX8UT_I, + 0, + Opcode_ivp_lvnx8ut_i_encode_fns, 0, 0 }, + { "ivp_lvnx8ut_ip", ICLASS_IVP_LVNX8UT_IP, + 0, + Opcode_ivp_lvnx8ut_ip_encode_fns, 0, 0 }, + { "ivp_lvnx8ut_x", ICLASS_IVP_LVNX8UT_X, + 0, + Opcode_ivp_lvnx8ut_x_encode_fns, 0, 0 }, + { "ivp_lvnx8ut_xp", ICLASS_IVP_LVNX8UT_XP, + 0, + Opcode_ivp_lvnx8ut_xp_encode_fns, 0, 0 }, + { "ivp_svnx8ut_i", ICLASS_IVP_SVNX8UT_I, + 0, + Opcode_ivp_svnx8ut_i_encode_fns, 0, 0 }, + { "ivp_svnx8ut_ip", ICLASS_IVP_SVNX8UT_IP, + 0, + Opcode_ivp_svnx8ut_ip_encode_fns, 0, 0 }, + { "ivp_svnx8ut_x", ICLASS_IVP_SVNX8UT_X, + 0, + Opcode_ivp_svnx8ut_x_encode_fns, 0, 0 }, + { "ivp_svnx8ut_xp", ICLASS_IVP_SVNX8UT_XP, + 0, + Opcode_ivp_svnx8ut_xp_encode_fns, 0, 0 }, + { "ivp_lavnx8s_xp", ICLASS_IVP_LAVNX8S_XP, + 0, + Opcode_ivp_lavnx8s_xp_encode_fns, 0, 0 }, + { "ivp_lavnx8u_xp", ICLASS_IVP_LAVNX8U_XP, + 0, + Opcode_ivp_lavnx8u_xp_encode_fns, 0, 0 }, + { "ivp_savnx8u_xp", ICLASS_IVP_SAVNX8U_XP, + 0, + Opcode_ivp_savnx8u_xp_encode_fns, 0, 0 }, + { "ivp_lanx8s_ip", ICLASS_IVP_LANX8S_IP, + 0, + Opcode_ivp_lanx8s_ip_encode_fns, 0, 0 }, + { "ivp_lanx8u_ip", ICLASS_IVP_LANX8U_IP, + 0, + Opcode_ivp_lanx8u_ip_encode_fns, 0, 0 }, + { "ivp_sanx8u_ip", ICLASS_IVP_SANX8U_IP, + 0, + Opcode_ivp_sanx8u_ip_encode_fns, 0, 0 }, + { "ivp_extractbl", ICLASS_IVP_EXTRACTBL, + 0, + Opcode_ivp_extractbl_encode_fns, 0, 0 }, + { "ivp_extractbh", ICLASS_IVP_EXTRACTBH, + 0, + Opcode_ivp_extractbh_encode_fns, 0, 0 }, + { "ivp_movvint16", ICLASS_IVP_MOVVINT16, + 0, + Opcode_ivp_movvint16_encode_fns, 0, 0 }, + { "ivp_movqint16", ICLASS_IVP_MOVQINT16, + 0, + Opcode_ivp_movqint16_encode_fns, 0, 0 }, + { "ivp_movqa16", ICLASS_IVP_MOVQA16, + 0, + Opcode_ivp_movqa16_encode_fns, 0, 0 }, + { "ivp_movvinx16", ICLASS_IVP_MOVVINX16, + 0, + Opcode_ivp_movvinx16_encode_fns, 0, 0 }, + { "ivp_seqnx16", ICLASS_IVP_SEQNX16, + 0, + Opcode_ivp_seqnx16_encode_fns, 0, 0 }, + { "ivp_mulnx16packl", ICLASS_IVP_MULNX16PACKL, + 0, + Opcode_ivp_mulnx16packl_encode_fns, 0, 0 }, + { "ivp_mulnx16packq", ICLASS_IVP_MULNX16PACKQ, + 0, + Opcode_ivp_mulnx16packq_encode_fns, 0, 0 }, + { "ivp_movav16", ICLASS_IVP_MOVAV16, + 0, + Opcode_ivp_movav16_encode_fns, 0, 0 }, + { "ivp_movavu16", ICLASS_IVP_MOVAVU16, + 0, + Opcode_ivp_movavu16_encode_fns, 0, 0 }, + { "ivp_extrnx16", ICLASS_IVP_EXTRNX16, + 0, + Opcode_ivp_extrnx16_encode_fns, 0, 0 }, + { "ivp_lsnx8s_i", ICLASS_IVP_LSNX8S_I, + 0, + Opcode_ivp_lsnx8s_i_encode_fns, 0, 0 }, + { "ivp_lsnx8s_ip", ICLASS_IVP_LSNX8S_IP, + 0, + Opcode_ivp_lsnx8s_ip_encode_fns, 0, 0 }, + { "ivp_lsnx8s_x", ICLASS_IVP_LSNX8S_X, + 0, + Opcode_ivp_lsnx8s_x_encode_fns, 0, 0 }, + { "ivp_lsnx8s_xp", ICLASS_IVP_LSNX8S_XP, + 0, + Opcode_ivp_lsnx8s_xp_encode_fns, 0, 0 }, + { "ivp_svnx8s_i", ICLASS_IVP_SVNX8S_I, + 0, + Opcode_ivp_svnx8s_i_encode_fns, 0, 0 }, + { "ivp_svnx8s_ip", ICLASS_IVP_SVNX8S_IP, + 0, + Opcode_ivp_svnx8s_ip_encode_fns, 0, 0 }, + { "ivp_svnx8s_x", ICLASS_IVP_SVNX8S_X, + 0, + Opcode_ivp_svnx8s_x_encode_fns, 0, 0 }, + { "ivp_svnx8s_xp", ICLASS_IVP_SVNX8S_XP, + 0, + Opcode_ivp_svnx8s_xp_encode_fns, 0, 0 }, + { "ivp_ssnx8s_i", ICLASS_IVP_SSNX8S_I, + 0, + Opcode_ivp_ssnx8s_i_encode_fns, 0, 0 }, + { "ivp_ssnx8s_ip", ICLASS_IVP_SSNX8S_IP, + 0, + Opcode_ivp_ssnx8s_ip_encode_fns, 0, 0 }, + { "ivp_ssnx8s_x", ICLASS_IVP_SSNX8S_X, + 0, + Opcode_ivp_ssnx8s_x_encode_fns, 0, 0 }, + { "ivp_ssnx8s_xp", ICLASS_IVP_SSNX8S_XP, + 0, + Opcode_ivp_ssnx8s_xp_encode_fns, 0, 0 }, + { "ivp_savnx8s_xp", ICLASS_IVP_SAVNX8S_XP, + 0, + Opcode_ivp_savnx8s_xp_encode_fns, 0, 0 }, + { "ivp_sanx8s_ip", ICLASS_IVP_SANX8S_IP, + 0, + Opcode_ivp_sanx8s_ip_encode_fns, 0, 0 }, + { "ivp_svnx8st_i", ICLASS_IVP_SVNX8ST_I, + 0, + Opcode_ivp_svnx8st_i_encode_fns, 0, 0 }, + { "ivp_svnx8st_ip", ICLASS_IVP_SVNX8ST_IP, + 0, + Opcode_ivp_svnx8st_ip_encode_fns, 0, 0 }, + { "ivp_svnx8st_x", ICLASS_IVP_SVNX8ST_X, + 0, + Opcode_ivp_svnx8st_x_encode_fns, 0, 0 }, + { "ivp_svnx8st_xp", ICLASS_IVP_SVNX8ST_XP, + 0, + Opcode_ivp_svnx8st_xp_encode_fns, 0, 0 }, + { "ivp_movba1", ICLASS_IVP_MOVBA1, + 0, + Opcode_ivp_movba1_encode_fns, 0, 0 }, + { "ivp_movab1", ICLASS_IVP_MOVAB1, + 0, + Opcode_ivp_movab1_encode_fns, 0, 0 }, + { "ivp_notb1", ICLASS_IVP_NOTB1, + 0, + Opcode_ivp_notb1_encode_fns, 0, 0 }, + { "ivp_andnotb1", ICLASS_IVP_ANDNOTB1, + 0, + Opcode_ivp_andnotb1_encode_fns, 0, 0 }, + { "ivp_ornotb1", ICLASS_IVP_ORNOTB1, + 0, + Opcode_ivp_ornotb1_encode_fns, 0, 0 }, + { "ivp_cvt32s2nx24ll", ICLASS_IVP_CVT32S2NX24LL, + 0, + Opcode_ivp_cvt32s2nx24ll_encode_fns, 0, 0 }, + { "ivp_cvt32s2nx24lh", ICLASS_IVP_CVT32S2NX24LH, + 0, + Opcode_ivp_cvt32s2nx24lh_encode_fns, 0, 0 }, + { "ivp_cvt32s2nx24hl", ICLASS_IVP_CVT32S2NX24HL, + 0, + Opcode_ivp_cvt32s2nx24hl_encode_fns, 0, 0 }, + { "ivp_cvt32s2nx24hh", ICLASS_IVP_CVT32S2NX24HH, + 0, + Opcode_ivp_cvt32s2nx24hh_encode_fns, 0, 0 }, + { "ivp_cvt64snx48ll", ICLASS_IVP_CVT64SNX48LL, + 0, + Opcode_ivp_cvt64snx48ll_encode_fns, 0, 0 }, + { "ivp_cvt64snx48lh", ICLASS_IVP_CVT64SNX48LH, + 0, + Opcode_ivp_cvt64snx48lh_encode_fns, 0, 0 }, + { "ivp_cvt64snx48hl", ICLASS_IVP_CVT64SNX48HL, + 0, + Opcode_ivp_cvt64snx48hl_encode_fns, 0, 0 }, + { "ivp_cvt64snx48hh", ICLASS_IVP_CVT64SNX48HH, + 0, + Opcode_ivp_cvt64snx48hh_encode_fns, 0, 0 }, + { "ivp_cvt16s2nx24l", ICLASS_IVP_CVT16S2NX24L, + 0, + Opcode_ivp_cvt16s2nx24l_encode_fns, 0, 0 }, + { "ivp_cvt16s2nx24h", ICLASS_IVP_CVT16S2NX24H, + 0, + Opcode_ivp_cvt16s2nx24h_encode_fns, 0, 0 }, + { "ivp_cvt32snx48l", ICLASS_IVP_CVT32SNX48L, + 0, + Opcode_ivp_cvt32snx48l_encode_fns, 0, 0 }, + { "ivp_cvt32snx48h", ICLASS_IVP_CVT32SNX48H, + 0, + Opcode_ivp_cvt32snx48h_encode_fns, 0, 0 }, + { "ivp_cvt16u2nx24h", ICLASS_IVP_CVT16U2NX24H, + 0, + Opcode_ivp_cvt16u2nx24h_encode_fns, 0, 0 }, + { "ivp_cvt32unx48h", ICLASS_IVP_CVT32UNX48H, + 0, + Opcode_ivp_cvt32unx48h_encode_fns, 0, 0 }, + { "ivp_cvt64un_2x96h", ICLASS_IVP_CVT64UN_2X96H, + 0, + Opcode_ivp_cvt64un_2x96h_encode_fns, 0, 0 }, + { "ivp_cvt16u2nx24l", ICLASS_IVP_CVT16U2NX24L, + 0, + Opcode_ivp_cvt16u2nx24l_encode_fns, 0, 0 }, + { "ivp_cvt24u2nx16", ICLASS_IVP_CVT24U2NX16, + 0, + Opcode_ivp_cvt24u2nx16_encode_fns, 0, 0 }, + { "ivp_cvt24s2nx16", ICLASS_IVP_CVT24S2NX16, + 0, + Opcode_ivp_cvt24s2nx16_encode_fns, 0, 0 }, + { "ivp_cvt32s24", ICLASS_IVP_CVT32S24, + 0, + Opcode_ivp_cvt32s24_encode_fns, 0, 0 }, + { "ivp_cvt24u32", ICLASS_IVP_CVT24U32, + 0, + Opcode_ivp_cvt24u32_encode_fns, 0, 0 }, + { "ivp_cvt24unx32l", ICLASS_IVP_CVT24UNX32L, + 0, + Opcode_ivp_cvt24unx32l_encode_fns, 0, 0 }, + { "ivp_cvt24unx32h", ICLASS_IVP_CVT24UNX32H, + 0, + Opcode_ivp_cvt24unx32h_encode_fns, 0, 0 }, + { "ivp_cvt32unx48l", ICLASS_IVP_CVT32UNX48L, + 0, + Opcode_ivp_cvt32unx48l_encode_fns, 0, 0 }, + { "ivp_cvt48unx32l", ICLASS_IVP_CVT48UNX32L, + 0, + Opcode_ivp_cvt48unx32l_encode_fns, 0, 0 }, + { "ivp_cvt48unx32", ICLASS_IVP_CVT48UNX32, + 0, + Opcode_ivp_cvt48unx32_encode_fns, 0, 0 }, + { "ivp_cvt48snx32l", ICLASS_IVP_CVT48SNX32L, + 0, + Opcode_ivp_cvt48snx32l_encode_fns, 0, 0 }, + { "ivp_cvt48snx32", ICLASS_IVP_CVT48SNX32, + 0, + Opcode_ivp_cvt48snx32_encode_fns, 0, 0 }, + { "ivp_cvt64s48", ICLASS_IVP_CVT64S48, + 0, + Opcode_ivp_cvt64s48_encode_fns, 0, 0 }, + { "ivp_cvt48u64", ICLASS_IVP_CVT48U64, + 0, + Opcode_ivp_cvt48u64_encode_fns, 0, 0 }, + { "ivp_cvt48un_2x64l", ICLASS_IVP_CVT48UN_2X64L, + 0, + Opcode_ivp_cvt48un_2x64l_encode_fns, 0, 0 }, + { "ivp_cvt48un_2x64h", ICLASS_IVP_CVT48UN_2X64H, + 0, + Opcode_ivp_cvt48un_2x64h_encode_fns, 0, 0 }, + { "ivp_cvt64un_2x96l", ICLASS_IVP_CVT64UN_2X96L, + 0, + Opcode_ivp_cvt64un_2x96l_encode_fns, 0, 0 }, + { "ivp_cvt96un_2x64", ICLASS_IVP_CVT96UN_2X64, + 0, + Opcode_ivp_cvt96un_2x64_encode_fns, 0, 0 }, + { "ivp_cvt96u64", ICLASS_IVP_CVT96U64, + 0, + Opcode_ivp_cvt96u64_encode_fns, 0, 0 }, + { "ivp_cvt64u96", ICLASS_IVP_CVT64U96, + 0, + Opcode_ivp_cvt64u96_encode_fns, 0, 0 }, + { "ivp_lb2n_i", ICLASS_IVP_LB2N_I, + 0, + Opcode_ivp_lb2n_i_encode_fns, 0, 0 }, + { "ivp_lb2n_ip", ICLASS_IVP_LB2N_IP, + 0, + Opcode_ivp_lb2n_ip_encode_fns, 0, 0 }, + { "ivp_sb2n_i", ICLASS_IVP_SB2N_I, + 0, + Opcode_ivp_sb2n_i_encode_fns, 0, 0 }, + { "ivp_sb2n_ip", ICLASS_IVP_SB2N_IP, + 0, + Opcode_ivp_sb2n_ip_encode_fns, 0, 0 }, + { "ivp_ltr2n", ICLASS_IVP_LTR2N, + 0, + Opcode_ivp_ltr2n_encode_fns, 0, 0 }, + { "ivp_ltr2ni", ICLASS_IVP_LTR2NI, + 0, + Opcode_ivp_ltr2ni_encode_fns, 0, 0 }, + { "ivp_lvn_2x16u_i", ICLASS_IVP_LVN_2X16U_I, + 0, + Opcode_ivp_lvn_2x16u_i_encode_fns, 0, 0 }, + { "ivp_lvn_2x16u_ip", ICLASS_IVP_LVN_2X16U_IP, + 0, + Opcode_ivp_lvn_2x16u_ip_encode_fns, 0, 0 }, + { "ivp_lvn_2x16u_x", ICLASS_IVP_LVN_2X16U_X, + 0, + Opcode_ivp_lvn_2x16u_x_encode_fns, 0, 0 }, + { "ivp_lvn_2x16u_xp", ICLASS_IVP_LVN_2X16U_XP, + 0, + Opcode_ivp_lvn_2x16u_xp_encode_fns, 0, 0 }, + { "ivp_lvn_2x16ut_i", ICLASS_IVP_LVN_2X16UT_I, + 0, + Opcode_ivp_lvn_2x16ut_i_encode_fns, 0, 0 }, + { "ivp_lvn_2x16ut_ip", ICLASS_IVP_LVN_2X16UT_IP, + 0, + Opcode_ivp_lvn_2x16ut_ip_encode_fns, 0, 0 }, + { "ivp_lvn_2x16ut_x", ICLASS_IVP_LVN_2X16UT_X, + 0, + Opcode_ivp_lvn_2x16ut_x_encode_fns, 0, 0 }, + { "ivp_lvn_2x16ut_xp", ICLASS_IVP_LVN_2X16UT_XP, + 0, + Opcode_ivp_lvn_2x16ut_xp_encode_fns, 0, 0 }, + { "ivp_lvn_2x16s_i", ICLASS_IVP_LVN_2X16S_I, + 0, + Opcode_ivp_lvn_2x16s_i_encode_fns, 0, 0 }, + { "ivp_lvn_2x16s_ip", ICLASS_IVP_LVN_2X16S_IP, + 0, + Opcode_ivp_lvn_2x16s_ip_encode_fns, 0, 0 }, + { "ivp_lvn_2x16s_x", ICLASS_IVP_LVN_2X16S_X, + 0, + Opcode_ivp_lvn_2x16s_x_encode_fns, 0, 0 }, + { "ivp_lvn_2x16s_xp", ICLASS_IVP_LVN_2X16S_XP, + 0, + Opcode_ivp_lvn_2x16s_xp_encode_fns, 0, 0 }, + { "ivp_lvn_2x16st_i", ICLASS_IVP_LVN_2X16ST_I, + 0, + Opcode_ivp_lvn_2x16st_i_encode_fns, 0, 0 }, + { "ivp_lvn_2x16st_ip", ICLASS_IVP_LVN_2X16ST_IP, + 0, + Opcode_ivp_lvn_2x16st_ip_encode_fns, 0, 0 }, + { "ivp_lvn_2x16st_x", ICLASS_IVP_LVN_2X16ST_X, + 0, + Opcode_ivp_lvn_2x16st_x_encode_fns, 0, 0 }, + { "ivp_lvn_2x16st_xp", ICLASS_IVP_LVN_2X16ST_XP, + 0, + Opcode_ivp_lvn_2x16st_xp_encode_fns, 0, 0 }, + { "ivp_svn_2x16u_i", ICLASS_IVP_SVN_2X16U_I, + 0, + Opcode_ivp_svn_2x16u_i_encode_fns, 0, 0 }, + { "ivp_svn_2x16ut_i", ICLASS_IVP_SVN_2X16UT_I, + 0, + Opcode_ivp_svn_2x16ut_i_encode_fns, 0, 0 }, + { "ivp_svn_2x16u_ip", ICLASS_IVP_SVN_2X16U_IP, + 0, + Opcode_ivp_svn_2x16u_ip_encode_fns, 0, 0 }, + { "ivp_svn_2x16ut_ip", ICLASS_IVP_SVN_2X16UT_IP, + 0, + Opcode_ivp_svn_2x16ut_ip_encode_fns, 0, 0 }, + { "ivp_svn_2x16u_x", ICLASS_IVP_SVN_2X16U_X, + 0, + Opcode_ivp_svn_2x16u_x_encode_fns, 0, 0 }, + { "ivp_svn_2x16ut_x", ICLASS_IVP_SVN_2X16UT_X, + 0, + Opcode_ivp_svn_2x16ut_x_encode_fns, 0, 0 }, + { "ivp_svn_2x16u_xp", ICLASS_IVP_SVN_2X16U_XP, + 0, + Opcode_ivp_svn_2x16u_xp_encode_fns, 0, 0 }, + { "ivp_svn_2x16ut_xp", ICLASS_IVP_SVN_2X16UT_XP, + 0, + Opcode_ivp_svn_2x16ut_xp_encode_fns, 0, 0 }, + { "ivp_svn_2x16s_i", ICLASS_IVP_SVN_2X16S_I, + 0, + Opcode_ivp_svn_2x16s_i_encode_fns, 0, 0 }, + { "ivp_svn_2x16st_i", ICLASS_IVP_SVN_2X16ST_I, + 0, + Opcode_ivp_svn_2x16st_i_encode_fns, 0, 0 }, + { "ivp_svn_2x16s_ip", ICLASS_IVP_SVN_2X16S_IP, + 0, + Opcode_ivp_svn_2x16s_ip_encode_fns, 0, 0 }, + { "ivp_svn_2x16st_ip", ICLASS_IVP_SVN_2X16ST_IP, + 0, + Opcode_ivp_svn_2x16st_ip_encode_fns, 0, 0 }, + { "ivp_svn_2x16s_x", ICLASS_IVP_SVN_2X16S_X, + 0, + Opcode_ivp_svn_2x16s_x_encode_fns, 0, 0 }, + { "ivp_svn_2x16st_x", ICLASS_IVP_SVN_2X16ST_X, + 0, + Opcode_ivp_svn_2x16st_x_encode_fns, 0, 0 }, + { "ivp_svn_2x16s_xp", ICLASS_IVP_SVN_2X16S_XP, + 0, + Opcode_ivp_svn_2x16s_xp_encode_fns, 0, 0 }, + { "ivp_svn_2x16st_xp", ICLASS_IVP_SVN_2X16ST_XP, + 0, + Opcode_ivp_svn_2x16st_xp_encode_fns, 0, 0 }, + { "ivp_lan_2x16s_ip", ICLASS_IVP_LAN_2X16S_IP, + 0, + Opcode_ivp_lan_2x16s_ip_encode_fns, 0, 0 }, + { "ivp_lan_2x16u_ip", ICLASS_IVP_LAN_2X16U_IP, + 0, + Opcode_ivp_lan_2x16u_ip_encode_fns, 0, 0 }, + { "ivp_lan_2x16u_xp", ICLASS_IVP_LAN_2X16U_XP, + 0, + Opcode_ivp_lan_2x16u_xp_encode_fns, 0, 0 }, + { "ivp_lan_2x16s_xp", ICLASS_IVP_LAN_2X16S_XP, + 0, + Opcode_ivp_lan_2x16s_xp_encode_fns, 0, 0 }, + { "ivp_san_2x16u_ip", ICLASS_IVP_SAN_2X16U_IP, + 0, + Opcode_ivp_san_2x16u_ip_encode_fns, 0, 0 }, + { "ivp_san_2x16s_ip", ICLASS_IVP_SAN_2X16S_IP, + 0, + Opcode_ivp_san_2x16s_ip_encode_fns, 0, 0 }, + { "ivp_lavn_2x16s_xp", ICLASS_IVP_LAVN_2X16S_XP, + 0, + Opcode_ivp_lavn_2x16s_xp_encode_fns, 0, 0 }, + { "ivp_lavn_2x16u_xp", ICLASS_IVP_LAVN_2X16U_XP, + 0, + Opcode_ivp_lavn_2x16u_xp_encode_fns, 0, 0 }, + { "ivp_savn_2x16u_xp", ICLASS_IVP_SAVN_2X16U_XP, + 0, + Opcode_ivp_savn_2x16u_xp_encode_fns, 0, 0 }, + { "ivp_savn_2x16s_xp", ICLASS_IVP_SAVN_2X16S_XP, + 0, + Opcode_ivp_savn_2x16s_xp_encode_fns, 0, 0 }, + { "ivp_lsn_2x16s_i", ICLASS_IVP_LSN_2X16S_I, + 0, + Opcode_ivp_lsn_2x16s_i_encode_fns, 0, 0 }, + { "ivp_lsn_2x16s_ip", ICLASS_IVP_LSN_2X16S_IP, + 0, + Opcode_ivp_lsn_2x16s_ip_encode_fns, 0, 0 }, + { "ivp_lsn_2x16s_x", ICLASS_IVP_LSN_2X16S_X, + 0, + Opcode_ivp_lsn_2x16s_x_encode_fns, 0, 0 }, + { "ivp_lsn_2x16s_xp", ICLASS_IVP_LSN_2X16S_XP, + 0, + Opcode_ivp_lsn_2x16s_xp_encode_fns, 0, 0 }, + { "ivp_ssn_2x16s_i", ICLASS_IVP_SSN_2X16S_I, + 0, + Opcode_ivp_ssn_2x16s_i_encode_fns, 0, 0 }, + { "ivp_ssn_2x16s_ip", ICLASS_IVP_SSN_2X16S_IP, + 0, + Opcode_ivp_ssn_2x16s_ip_encode_fns, 0, 0 }, + { "ivp_ssn_2x16s_x", ICLASS_IVP_SSN_2X16S_X, + 0, + Opcode_ivp_ssn_2x16s_x_encode_fns, 0, 0 }, + { "ivp_ssn_2x16s_xp", ICLASS_IVP_SSN_2X16S_XP, + 0, + Opcode_ivp_ssn_2x16s_xp_encode_fns, 0, 0 }, + { "ivp_lsn_2x32_i", ICLASS_IVP_LSN_2X32_I, + 0, + Opcode_ivp_lsn_2x32_i_encode_fns, 0, 0 }, + { "ivp_lsn_2x32_ip", ICLASS_IVP_LSN_2X32_IP, + 0, + Opcode_ivp_lsn_2x32_ip_encode_fns, 0, 0 }, + { "ivp_lsn_2x32_x", ICLASS_IVP_LSN_2X32_X, + 0, + Opcode_ivp_lsn_2x32_x_encode_fns, 0, 0 }, + { "ivp_lsn_2x32_xp", ICLASS_IVP_LSN_2X32_XP, + 0, + Opcode_ivp_lsn_2x32_xp_encode_fns, 0, 0 }, + { "ivp_ssn_2x32_i", ICLASS_IVP_SSN_2X32_I, + 0, + Opcode_ivp_ssn_2x32_i_encode_fns, 0, 0 }, + { "ivp_ssn_2x32_ip", ICLASS_IVP_SSN_2X32_IP, + 0, + Opcode_ivp_ssn_2x32_ip_encode_fns, 0, 0 }, + { "ivp_ssn_2x32_x", ICLASS_IVP_SSN_2X32_X, + 0, + Opcode_ivp_ssn_2x32_x_encode_fns, 0, 0 }, + { "ivp_ssn_2x32_xp", ICLASS_IVP_SSN_2X32_XP, + 0, + Opcode_ivp_ssn_2x32_xp_encode_fns, 0, 0 }, + { "ivp_bmaxunx16", ICLASS_IVP_BMAXUNX16, + 0, + Opcode_ivp_bmaxunx16_encode_fns, 0, 0 }, + { "ivp_bminunx16", ICLASS_IVP_BMINUNX16, + 0, + Opcode_ivp_bminunx16_encode_fns, 0, 0 }, + { "ivp_rbminunx16", ICLASS_IVP_RBMINUNX16, + 0, + Opcode_ivp_rbminunx16_encode_fns, 0, 0 }, + { "ivp_rbmaxunx16", ICLASS_IVP_RBMAXUNX16, + 0, + Opcode_ivp_rbmaxunx16_encode_fns, 0, 0 }, + { "ivp_bmax2nx8", ICLASS_IVP_BMAX2NX8, + 0, + Opcode_ivp_bmax2nx8_encode_fns, 0, 0 }, + { "ivp_bmin2nx8", ICLASS_IVP_BMIN2NX8, + 0, + Opcode_ivp_bmin2nx8_encode_fns, 0, 0 }, + { "ivp_bmaxu2nx8", ICLASS_IVP_BMAXU2NX8, + 0, + Opcode_ivp_bmaxu2nx8_encode_fns, 0, 0 }, + { "ivp_bminu2nx8", ICLASS_IVP_BMINU2NX8, + 0, + Opcode_ivp_bminu2nx8_encode_fns, 0, 0 }, + { "ivp_bmaxn_2x32", ICLASS_IVP_BMAXN_2X32, + 0, + Opcode_ivp_bmaxn_2x32_encode_fns, 0, 0 }, + { "ivp_bminn_2x32", ICLASS_IVP_BMINN_2X32, + 0, + Opcode_ivp_bminn_2x32_encode_fns, 0, 0 }, + { "ivp_bmaxun_2x32", ICLASS_IVP_BMAXUN_2X32, + 0, + Opcode_ivp_bmaxun_2x32_encode_fns, 0, 0 }, + { "ivp_bminun_2x32", ICLASS_IVP_BMINUN_2X32, + 0, + Opcode_ivp_bminun_2x32_encode_fns, 0, 0 }, + { "ivp_addn_2x32t", ICLASS_IVP_ADDN_2X32T, + 0, + Opcode_ivp_addn_2x32t_encode_fns, 0, 0 }, + { "ivp_subn_2x32t", ICLASS_IVP_SUBN_2X32T, + 0, + Opcode_ivp_subn_2x32t_encode_fns, 0, 0 }, + { "ivp_add2nx8", ICLASS_IVP_ADD2NX8, + 0, + Opcode_ivp_add2nx8_encode_fns, 0, 0 }, + { "ivp_sub2nx8", ICLASS_IVP_SUB2NX8, + 0, + Opcode_ivp_sub2nx8_encode_fns, 0, 0 }, + { "ivp_neg2nx8", ICLASS_IVP_NEG2NX8, + 0, + Opcode_ivp_neg2nx8_encode_fns, 0, 0 }, + { "ivp_min2nx8", ICLASS_IVP_MIN2NX8, + 0, + Opcode_ivp_min2nx8_encode_fns, 0, 0 }, + { "ivp_minu2nx8", ICLASS_IVP_MINU2NX8, + 0, + Opcode_ivp_minu2nx8_encode_fns, 0, 0 }, + { "ivp_max2nx8", ICLASS_IVP_MAX2NX8, + 0, + Opcode_ivp_max2nx8_encode_fns, 0, 0 }, + { "ivp_maxu2nx8", ICLASS_IVP_MAXU2NX8, + 0, + Opcode_ivp_maxu2nx8_encode_fns, 0, 0 }, + { "ivp_lt2nx8", ICLASS_IVP_LT2NX8, + 0, + Opcode_ivp_lt2nx8_encode_fns, 0, 0 }, + { "ivp_le2nx8", ICLASS_IVP_LE2NX8, + 0, + Opcode_ivp_le2nx8_encode_fns, 0, 0 }, + { "ivp_eq2nx8", ICLASS_IVP_EQ2NX8, + 0, + Opcode_ivp_eq2nx8_encode_fns, 0, 0 }, + { "ivp_neq2nx8", ICLASS_IVP_NEQ2NX8, + 0, + Opcode_ivp_neq2nx8_encode_fns, 0, 0 }, + { "ivp_ltu2nx8", ICLASS_IVP_LTU2NX8, + 0, + Opcode_ivp_ltu2nx8_encode_fns, 0, 0 }, + { "ivp_leu2nx8", ICLASS_IVP_LEU2NX8, + 0, + Opcode_ivp_leu2nx8_encode_fns, 0, 0 }, + { "ivp_add2nx8t", ICLASS_IVP_ADD2NX8T, + 0, + Opcode_ivp_add2nx8t_encode_fns, 0, 0 }, + { "ivp_sub2nx8t", ICLASS_IVP_SUB2NX8T, + 0, + Opcode_ivp_sub2nx8t_encode_fns, 0, 0 }, + { "ivp_selnx16t", ICLASS_IVP_SELNX16T, + 0, + Opcode_ivp_selnx16t_encode_fns, 0, 0 }, + { "ivp_seln_2x32", ICLASS_IVP_SELN_2X32, + 0, + Opcode_ivp_seln_2x32_encode_fns, 0, 0 }, + { "ivp_seln_2x32t", ICLASS_IVP_SELN_2X32T, + 0, + Opcode_ivp_seln_2x32t_encode_fns, 0, 0 }, + { "ivp_shfln_2x32", ICLASS_IVP_SHFLN_2X32, + 0, + Opcode_ivp_shfln_2x32_encode_fns, 0, 0 }, + { "ivp_sllin_2x32", ICLASS_IVP_SLLIN_2X32, + 0, + Opcode_ivp_sllin_2x32_encode_fns, 0, 0 }, + { "ivp_slsin_2x32", ICLASS_IVP_SLSIN_2X32, + 0, + Opcode_ivp_slsin_2x32_encode_fns, 0, 0 }, + { "ivp_srain_2x32", ICLASS_IVP_SRAIN_2X32, + 0, + Opcode_ivp_srain_2x32_encode_fns, 0, 0 }, + { "ivp_srlin_2x32", ICLASS_IVP_SRLIN_2X32, + 0, + Opcode_ivp_srlin_2x32_encode_fns, 0, 0 }, + { "ivp_slln_2x32", ICLASS_IVP_SLLN_2X32, + 0, + Opcode_ivp_slln_2x32_encode_fns, 0, 0 }, + { "ivp_srln_2x32", ICLASS_IVP_SRLN_2X32, + 0, + Opcode_ivp_srln_2x32_encode_fns, 0, 0 }, + { "ivp_slan_2x32", ICLASS_IVP_SLAN_2X32, + 0, + Opcode_ivp_slan_2x32_encode_fns, 0, 0 }, + { "ivp_sran_2x32", ICLASS_IVP_SRAN_2X32, + 0, + Opcode_ivp_sran_2x32_encode_fns, 0, 0 }, + { "ivp_slsn_2x32", ICLASS_IVP_SLSN_2X32, + 0, + Opcode_ivp_slsn_2x32_encode_fns, 0, 0 }, + { "ivp_srsn_2x32", ICLASS_IVP_SRSN_2X32, + 0, + Opcode_ivp_srsn_2x32_encode_fns, 0, 0 }, + { "ivp_raddn_2x32", ICLASS_IVP_RADDN_2X32, + 0, + Opcode_ivp_raddn_2x32_encode_fns, 0, 0 }, + { "ivp_rmaxn_2x32", ICLASS_IVP_RMAXN_2X32, + 0, + Opcode_ivp_rmaxn_2x32_encode_fns, 0, 0 }, + { "ivp_rminn_2x32", ICLASS_IVP_RMINN_2X32, + 0, + Opcode_ivp_rminn_2x32_encode_fns, 0, 0 }, + { "ivp_rmaxun_2x32", ICLASS_IVP_RMAXUN_2X32, + 0, + Opcode_ivp_rmaxun_2x32_encode_fns, 0, 0 }, + { "ivp_rminun_2x32", ICLASS_IVP_RMINUN_2X32, + 0, + Opcode_ivp_rminun_2x32_encode_fns, 0, 0 }, + { "ivp_raddn_2x32t", ICLASS_IVP_RADDN_2X32T, + 0, + Opcode_ivp_raddn_2x32t_encode_fns, 0, 0 }, + { "ivp_abs2nx8", ICLASS_IVP_ABS2NX8, + 0, + Opcode_ivp_abs2nx8_encode_fns, 0, 0 }, + { "ivp_absn_2x32", ICLASS_IVP_ABSN_2X32, + 0, + Opcode_ivp_absn_2x32_encode_fns, 0, 0 }, + { "ivp_mulsgnsnx16", ICLASS_IVP_MULSGNSNX16, + 0, + Opcode_ivp_mulsgnsnx16_encode_fns, 0, 0 }, + { "ivp_rotri2nx8", ICLASS_IVP_ROTRI2NX8, + 0, + Opcode_ivp_rotri2nx8_encode_fns, 0, 0 }, + { "ivp_rotrinx16", ICLASS_IVP_ROTRINX16, + 0, + Opcode_ivp_rotrinx16_encode_fns, 0, 0 }, + { "ivp_rotrin_2x32", ICLASS_IVP_ROTRIN_2X32, + 0, + Opcode_ivp_rotrin_2x32_encode_fns, 0, 0 }, + { "ivp_rotrnx16", ICLASS_IVP_ROTRNX16, + 0, + Opcode_ivp_rotrnx16_encode_fns, 0, 0 }, + { "ivp_rotrn_2x32", ICLASS_IVP_ROTRN_2X32, + 0, + Opcode_ivp_rotrn_2x32_encode_fns, 0, 0 }, + { "ivp_addn_2x32", ICLASS_IVP_ADDN_2X32, + 0, + Opcode_ivp_addn_2x32_encode_fns, 0, 0 }, + { "ivp_subn_2x32", ICLASS_IVP_SUBN_2X32, + 0, + Opcode_ivp_subn_2x32_encode_fns, 0, 0 }, + { "ivp_negn_2x32", ICLASS_IVP_NEGN_2X32, + 0, + Opcode_ivp_negn_2x32_encode_fns, 0, 0 }, + { "ivp_minn_2x32", ICLASS_IVP_MINN_2X32, + 0, + Opcode_ivp_minn_2x32_encode_fns, 0, 0 }, + { "ivp_minun_2x32", ICLASS_IVP_MINUN_2X32, + 0, + Opcode_ivp_minun_2x32_encode_fns, 0, 0 }, + { "ivp_maxn_2x32", ICLASS_IVP_MAXN_2X32, + 0, + Opcode_ivp_maxn_2x32_encode_fns, 0, 0 }, + { "ivp_maxun_2x32", ICLASS_IVP_MAXUN_2X32, + 0, + Opcode_ivp_maxun_2x32_encode_fns, 0, 0 }, + { "ivp_mulsgnn_2x32", ICLASS_IVP_MULSGNN_2X32, + 0, + Opcode_ivp_mulsgnn_2x32_encode_fns, 0, 0 }, + { "ivp_nsan_2x32", ICLASS_IVP_NSAN_2X32, + 0, + Opcode_ivp_nsan_2x32_encode_fns, 0, 0 }, + { "ivp_nsaun_2x32", ICLASS_IVP_NSAUN_2X32, + 0, + Opcode_ivp_nsaun_2x32_encode_fns, 0, 0 }, + { "ivp_ltn_2x32", ICLASS_IVP_LTN_2X32, + 0, + Opcode_ivp_ltn_2x32_encode_fns, 0, 0 }, + { "ivp_len_2x32", ICLASS_IVP_LEN_2X32, + 0, + Opcode_ivp_len_2x32_encode_fns, 0, 0 }, + { "ivp_eqn_2x32", ICLASS_IVP_EQN_2X32, + 0, + Opcode_ivp_eqn_2x32_encode_fns, 0, 0 }, + { "ivp_neqn_2x32", ICLASS_IVP_NEQN_2X32, + 0, + Opcode_ivp_neqn_2x32_encode_fns, 0, 0 }, + { "ivp_ltun_2x32", ICLASS_IVP_LTUN_2X32, + 0, + Opcode_ivp_ltun_2x32_encode_fns, 0, 0 }, + { "ivp_leun_2x32", ICLASS_IVP_LEUN_2X32, + 0, + Opcode_ivp_leun_2x32_encode_fns, 0, 0 }, + { "ivp_lat2nx8_xp", ICLASS_IVP_LAT2NX8_XP, + 0, + Opcode_ivp_lat2nx8_xp_encode_fns, 0, 0 }, + { "ivp_muluu2nx8", ICLASS_IVP_MULUU2NX8, + 0, + Opcode_ivp_muluu2nx8_encode_fns, 0, 0 }, + { "ivp_muluua2nx8", ICLASS_IVP_MULUUA2NX8, + 0, + Opcode_ivp_muluua2nx8_encode_fns, 0, 0 }, + { "ivp_mulus2nx8", ICLASS_IVP_MULUS2NX8, + 0, + Opcode_ivp_mulus2nx8_encode_fns, 0, 0 }, + { "ivp_mulusa2nx8", ICLASS_IVP_MULUSA2NX8, + 0, + Opcode_ivp_mulusa2nx8_encode_fns, 0, 0 }, + { "ivp_muli2nx8x16", ICLASS_IVP_MULI2NX8X16, + 0, + Opcode_ivp_muli2nx8x16_encode_fns, 0, 0 }, + { "ivp_mulai2nx8x16", ICLASS_IVP_MULAI2NX8X16, + 0, + Opcode_ivp_mulai2nx8x16_encode_fns, 0, 0 }, + { "ivp_mulusi2nx8x16", ICLASS_IVP_MULUSI2NX8X16, + 0, + Opcode_ivp_mulusi2nx8x16_encode_fns, 0, 0 }, + { "ivp_mulusai2nx8x16", ICLASS_IVP_MULUSAI2NX8X16, + 0, + Opcode_ivp_mulusai2nx8x16_encode_fns, 0, 0 }, + { "ivp_muli2nr8x16", ICLASS_IVP_MULI2NR8X16, + 0, + Opcode_ivp_muli2nr8x16_encode_fns, 0, 0 }, + { "ivp_mulai2nr8x16", ICLASS_IVP_MULAI2NR8X16, + 0, + Opcode_ivp_mulai2nr8x16_encode_fns, 0, 0 }, + { "ivp_mulusi2nr8x16", ICLASS_IVP_MULUSI2NR8X16, + 0, + Opcode_ivp_mulusi2nr8x16_encode_fns, 0, 0 }, + { "ivp_mulusai2nr8x16", ICLASS_IVP_MULUSAI2NR8X16, + 0, + Opcode_ivp_mulusai2nr8x16_encode_fns, 0, 0 }, + { "ivp_mulusa2n8xr16", ICLASS_IVP_MULUSA2N8XR16, + 0, + Opcode_ivp_mulusa2n8xr16_encode_fns, 0, 0 }, + { "ivp_mulus2n8xr16", ICLASS_IVP_MULUS2N8XR16, + 0, + Opcode_ivp_mulus2n8xr16_encode_fns, 0, 0 }, + { "ivp_mula2n8xr16", ICLASS_IVP_MULA2N8XR16, + 0, + Opcode_ivp_mula2n8xr16_encode_fns, 0, 0 }, + { "ivp_mul2n8xr16", ICLASS_IVP_MUL2N8XR16, + 0, + Opcode_ivp_mul2n8xr16_encode_fns, 0, 0 }, + { "ivp_dsel2nx8i", ICLASS_IVP_DSEL2NX8I, + 0, + Opcode_ivp_dsel2nx8i_encode_fns, 0, 0 }, + { "ivp_dsel2nx8i_h", ICLASS_IVP_DSEL2NX8I_H, + 0, + Opcode_ivp_dsel2nx8i_h_encode_fns, 0, 0 }, + { "ivp_dselnx16", ICLASS_IVP_DSELNX16, + 0, + Opcode_ivp_dselnx16_encode_fns, 0, 0 }, + { "ivp_dselnx16t", ICLASS_IVP_DSELNX16T, + 0, + Opcode_ivp_dselnx16t_encode_fns, 0, 0 }, + { "ivp_injbi2nx8", ICLASS_IVP_INJBI2NX8, + 0, + Opcode_ivp_injbi2nx8_encode_fns, 0, 0 }, + { "ivp_extbi2nx8", ICLASS_IVP_EXTBI2NX8, + 0, + Opcode_ivp_extbi2nx8_encode_fns, 0, 0 }, + { "ivp_movva32", ICLASS_IVP_MOVVA32, + 0, + Opcode_ivp_movva32_encode_fns, 0, 0 }, + { "ivp_movav32", ICLASS_IVP_MOVAV32, + 0, + Opcode_ivp_movav32_encode_fns, 0, 0 }, + { "ivp_movww", ICLASS_IVP_MOVWW, + 0, + Opcode_ivp_movww_encode_fns, 0, 0 }, + { "ivp_ls2nx8_i", ICLASS_IVP_LS2NX8_I, + 0, + Opcode_ivp_ls2nx8_i_encode_fns, 0, 0 }, + { "ivp_ls2nx8_ip", ICLASS_IVP_LS2NX8_IP, + 0, + Opcode_ivp_ls2nx8_ip_encode_fns, 0, 0 }, + { "ivp_ls2nx8_x", ICLASS_IVP_LS2NX8_X, + 0, + Opcode_ivp_ls2nx8_x_encode_fns, 0, 0 }, + { "ivp_ls2nx8_xp", ICLASS_IVP_LS2NX8_XP, + 0, + Opcode_ivp_ls2nx8_xp_encode_fns, 0, 0 }, + { "ivp_ss2nx8_i", ICLASS_IVP_SS2NX8_I, + 0, + Opcode_ivp_ss2nx8_i_encode_fns, 0, 0 }, + { "ivp_ss2nx8_ip", ICLASS_IVP_SS2NX8_IP, + 0, + Opcode_ivp_ss2nx8_ip_encode_fns, 0, 0 }, + { "ivp_ss2nx8_x", ICLASS_IVP_SS2NX8_X, + 0, + Opcode_ivp_ss2nx8_x_encode_fns, 0, 0 }, + { "ivp_ss2nx8_xp", ICLASS_IVP_SS2NX8_XP, + 0, + Opcode_ivp_ss2nx8_xp_encode_fns, 0, 0 }, + { "ivp_lanx8s_xp", ICLASS_IVP_LANX8S_XP, + 0, + Opcode_ivp_lanx8s_xp_encode_fns, 0, 0 }, + { "ivp_lanx8u_xp", ICLASS_IVP_LANX8U_XP, + 0, + Opcode_ivp_lanx8u_xp_encode_fns, 0, 0 }, + { "ivp_la2nx8_xp", ICLASS_IVP_LA2NX8_XP, + 0, + Opcode_ivp_la2nx8_xp_encode_fns, 0, 0 }, + { "ivp_abssubu2nx8", ICLASS_IVP_ABSSUBU2NX8, + 0, + Opcode_ivp_abssubu2nx8_encode_fns, 0, 0 }, + { "ivp_abssub2nx8", ICLASS_IVP_ABSSUB2NX8, + 0, + Opcode_ivp_abssub2nx8_encode_fns, 0, 0 }, + { "ivp_movvint8", ICLASS_IVP_MOVVINT8, + 0, + Opcode_ivp_movvint8_encode_fns, 0, 0 }, + { "ivp_movva8", ICLASS_IVP_MOVVA8, + 0, + Opcode_ivp_movva8_encode_fns, 0, 0 }, + { "ivp_movavu8", ICLASS_IVP_MOVAVU8, + 0, + Opcode_ivp_movavu8_encode_fns, 0, 0 }, + { "ivp_slli2nx8", ICLASS_IVP_SLLI2NX8, + 0, + Opcode_ivp_slli2nx8_encode_fns, 0, 0 }, + { "ivp_srai2nx8", ICLASS_IVP_SRAI2NX8, + 0, + Opcode_ivp_srai2nx8_encode_fns, 0, 0 }, + { "ivp_srli2nx8", ICLASS_IVP_SRLI2NX8, + 0, + Opcode_ivp_srli2nx8_encode_fns, 0, 0 }, + { "ivp_packl2nx24", ICLASS_IVP_PACKL2NX24, + 0, + Opcode_ivp_packl2nx24_encode_fns, 0, 0 }, + { "ivp_packvr2nx24", ICLASS_IVP_PACKVR2NX24, + 0, + Opcode_ivp_packvr2nx24_encode_fns, 0, 0 }, + { "ivp_packvru2nx24", ICLASS_IVP_PACKVRU2NX24, + 0, + Opcode_ivp_packvru2nx24_encode_fns, 0, 0 }, + { "ivp_packlnx48", ICLASS_IVP_PACKLNX48, + 0, + Opcode_ivp_packlnx48_encode_fns, 0, 0 }, + { "ivp_packl2nx24_1", ICLASS_IVP_PACKL2NX24_1, + 0, + Opcode_ivp_packl2nx24_1_encode_fns, 0, 0 }, + { "ivp_packvr2nx24_0", ICLASS_IVP_PACKVR2NX24_0, + 0, + Opcode_ivp_packvr2nx24_0_encode_fns, 0, 0 }, + { "ivp_packvr2nx24_1", ICLASS_IVP_PACKVR2NX24_1, + 0, + Opcode_ivp_packvr2nx24_1_encode_fns, 0, 0 }, + { "ivp_packvru2nx24_0", ICLASS_IVP_PACKVRU2NX24_0, + 0, + Opcode_ivp_packvru2nx24_0_encode_fns, 0, 0 }, + { "ivp_packvru2nx24_1", ICLASS_IVP_PACKVRU2NX24_1, + 0, + Opcode_ivp_packvru2nx24_1_encode_fns, 0, 0 }, + { "ivp_packvrnr2nx24_0", ICLASS_IVP_PACKVRNR2NX24_0, + 0, + Opcode_ivp_packvrnr2nx24_0_encode_fns, 0, 0 }, + { "ivp_packvrnr2nx24_1", ICLASS_IVP_PACKVRNR2NX24_1, + 0, + Opcode_ivp_packvrnr2nx24_1_encode_fns, 0, 0 }, + { "ivp_packmnx48", ICLASS_IVP_PACKMNX48, + 0, + Opcode_ivp_packmnx48_encode_fns, 0, 0 }, + { "ivp_packvrnx48", ICLASS_IVP_PACKVRNX48, + 0, + Opcode_ivp_packvrnx48_encode_fns, 0, 0 }, + { "ivp_unpks2nx8_0", ICLASS_IVP_UNPKS2NX8_0, + 0, + Opcode_ivp_unpks2nx8_0_encode_fns, 0, 0 }, + { "ivp_unpks2nx8_1", ICLASS_IVP_UNPKS2NX8_1, + 0, + Opcode_ivp_unpks2nx8_1_encode_fns, 0, 0 }, + { "ivp_unpksnx16_l", ICLASS_IVP_UNPKSNX16_L, + 0, + Opcode_ivp_unpksnx16_l_encode_fns, 0, 0 }, + { "ivp_unpksnx16_h", ICLASS_IVP_UNPKSNX16_H, + 0, + Opcode_ivp_unpksnx16_h_encode_fns, 0, 0 }, + { "ivp_sel2nx8i", ICLASS_IVP_SEL2NX8I, + 0, + Opcode_ivp_sel2nx8i_encode_fns, 0, 0 }, + { "ivp_sel2nx8i_s0", ICLASS_IVP_SEL2NX8I_S0, + 0, + Opcode_ivp_sel2nx8i_s0_encode_fns, 0, 0 }, + { "ivp_sel2nx8i_s2", ICLASS_IVP_SEL2NX8I_S2, + 0, + Opcode_ivp_sel2nx8i_s2_encode_fns, 0, 0 }, + { "ivp_sel2nx8i_s4", ICLASS_IVP_SEL2NX8I_S4, + 0, + Opcode_ivp_sel2nx8i_s4_encode_fns, 0, 0 }, + { "ivp_shfl2nx8i", ICLASS_IVP_SHFL2NX8I, + 0, + Opcode_ivp_shfl2nx8i_encode_fns, 0, 0 }, + { "ivp_shfl2nx8i_s0", ICLASS_IVP_SHFL2NX8I_S0, + 0, + Opcode_ivp_shfl2nx8i_s0_encode_fns, 0, 0 }, + { "ivp_shfl2nx8i_s2", ICLASS_IVP_SHFL2NX8I_S2, + 0, + Opcode_ivp_shfl2nx8i_s2_encode_fns, 0, 0 }, + { "ivp_shfl2nx8i_s4", ICLASS_IVP_SHFL2NX8I_S4, + 0, + Opcode_ivp_shfl2nx8i_s4_encode_fns, 0, 0 }, + { "ivp_sel2nx8", ICLASS_IVP_SEL2NX8, + 0, + Opcode_ivp_sel2nx8_encode_fns, 0, 0 }, + { "ivp_shfl2nx8", ICLASS_IVP_SHFL2NX8, + 0, + Opcode_ivp_shfl2nx8_encode_fns, 0, 0 }, + { "ivp_sel2nx8t", ICLASS_IVP_SEL2NX8T, + 0, + Opcode_ivp_sel2nx8t_encode_fns, 0, 0 }, + { "ivp_sqzn", ICLASS_IVP_SQZN, + 0, + Opcode_ivp_sqzn_encode_fns, 0, 0 }, + { "ivp_unsqzn", ICLASS_IVP_UNSQZN, + 0, + Opcode_ivp_unsqzn_encode_fns, 0, 0 }, + { "ivp_mulnx16", ICLASS_IVP_MULNX16, + 0, + Opcode_ivp_mulnx16_encode_fns, 0, 0 }, + { "ivp_mulanx16", ICLASS_IVP_MULANX16, + 0, + Opcode_ivp_mulanx16_encode_fns, 0, 0 }, + { "ivp_muluunx16", ICLASS_IVP_MULUUNX16, + 0, + Opcode_ivp_muluunx16_encode_fns, 0, 0 }, + { "ivp_muluuanx16", ICLASS_IVP_MULUUANX16, + 0, + Opcode_ivp_muluuanx16_encode_fns, 0, 0 }, + { "ivp_mulusnx16", ICLASS_IVP_MULUSNX16, + 0, + Opcode_ivp_mulusnx16_encode_fns, 0, 0 }, + { "ivp_mulusanx16", ICLASS_IVP_MULUSANX16, + 0, + Opcode_ivp_mulusanx16_encode_fns, 0, 0 }, + { "ivp_mul2nx8", ICLASS_IVP_MUL2NX8, + 0, + Opcode_ivp_mul2nx8_encode_fns, 0, 0 }, + { "ivp_mula2nx8", ICLASS_IVP_MULA2NX8, + 0, + Opcode_ivp_mula2nx8_encode_fns, 0, 0 }, + { "ivp_addw2nx8", ICLASS_IVP_ADDW2NX8, + 0, + Opcode_ivp_addw2nx8_encode_fns, 0, 0 }, + { "ivp_addwa2nx8", ICLASS_IVP_ADDWA2NX8, + 0, + Opcode_ivp_addwa2nx8_encode_fns, 0, 0 }, + { "ivp_addws2nx8", ICLASS_IVP_ADDWS2NX8, + 0, + Opcode_ivp_addws2nx8_encode_fns, 0, 0 }, + { "ivp_addwu2nx8", ICLASS_IVP_ADDWU2NX8, + 0, + Opcode_ivp_addwu2nx8_encode_fns, 0, 0 }, + { "ivp_addwua2nx8", ICLASS_IVP_ADDWUA2NX8, + 0, + Opcode_ivp_addwua2nx8_encode_fns, 0, 0 }, + { "ivp_addwus2nx8", ICLASS_IVP_ADDWUS2NX8, + 0, + Opcode_ivp_addwus2nx8_encode_fns, 0, 0 }, + { "ivp_divn_2x32x16s_4step0", ICLASS_IVP_DIVN_2X32X16S_4STEP0, + 0, + Opcode_ivp_divn_2x32x16s_4step0_encode_fns, 0, 0 }, + { "ivp_divn_2x32x16s_4step", ICLASS_IVP_DIVN_2X32X16S_4STEP, + 0, + Opcode_ivp_divn_2x32x16s_4step_encode_fns, 0, 0 }, + { "ivp_divn_2x32x16s_4stepn", ICLASS_IVP_DIVN_2X32X16S_4STEPN, + 0, + Opcode_ivp_divn_2x32x16s_4stepn_encode_fns, 0, 0 }, + { "ivp_divn_2x32x16u_4step0", ICLASS_IVP_DIVN_2X32X16U_4STEP0, + 0, + Opcode_ivp_divn_2x32x16u_4step0_encode_fns, 0, 0 }, + { "ivp_divn_2x32x16u_4step", ICLASS_IVP_DIVN_2X32X16U_4STEP, + 0, + Opcode_ivp_divn_2x32x16u_4step_encode_fns, 0, 0 }, + { "ivp_divn_2x32x16u_4stepn", ICLASS_IVP_DIVN_2X32X16U_4STEPN, + 0, + Opcode_ivp_divn_2x32x16u_4stepn_encode_fns, 0, 0 }, + { "ivp_divnx16s_4step0", ICLASS_IVP_DIVNX16S_4STEP0, + 0, + Opcode_ivp_divnx16s_4step0_encode_fns, 0, 0 }, + { "ivp_divnx16s_4step", ICLASS_IVP_DIVNX16S_4STEP, + 0, + Opcode_ivp_divnx16s_4step_encode_fns, 0, 0 }, + { "ivp_divnx16s_4stepn", ICLASS_IVP_DIVNX16S_4STEPN, + 0, + Opcode_ivp_divnx16s_4stepn_encode_fns, 0, 0 }, + { "ivp_divnx16u_4step0", ICLASS_IVP_DIVNX16U_4STEP0, + 0, + Opcode_ivp_divnx16u_4step0_encode_fns, 0, 0 }, + { "ivp_divnx16u_4step", ICLASS_IVP_DIVNX16U_4STEP, + 0, + Opcode_ivp_divnx16u_4step_encode_fns, 0, 0 }, + { "ivp_divnx16u_4stepn", ICLASS_IVP_DIVNX16U_4STEPN, + 0, + Opcode_ivp_divnx16u_4stepn_encode_fns, 0, 0 }, + { "ivp_divnx16sq_4step0", ICLASS_IVP_DIVNX16SQ_4STEP0, + 0, + Opcode_ivp_divnx16sq_4step0_encode_fns, 0, 0 }, + { "ivp_divnx16q_4step0", ICLASS_IVP_DIVNX16Q_4STEP0, + 0, + Opcode_ivp_divnx16q_4step0_encode_fns, 0, 0 }, + { "ivp_mulsnx16", ICLASS_IVP_MULSNX16, + 0, + Opcode_ivp_mulsnx16_encode_fns, 0, 0 }, + { "ivp_muluusnx16", ICLASS_IVP_MULUUSNX16, + 0, + Opcode_ivp_muluusnx16_encode_fns, 0, 0 }, + { "ivp_mulussnx16", ICLASS_IVP_MULUSSNX16, + 0, + Opcode_ivp_mulussnx16_encode_fns, 0, 0 }, + { "ivp_muln_2x16x32_0", ICLASS_IVP_MULN_2X16X32_0, + 0, + Opcode_ivp_muln_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_muluun_2x16x32_0", ICLASS_IVP_MULUUN_2X16X32_0, + 0, + Opcode_ivp_muluun_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_mulusn_2x16x32_0", ICLASS_IVP_MULUSN_2X16X32_0, + 0, + Opcode_ivp_mulusn_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_mulsun_2x16x32_0", ICLASS_IVP_MULSUN_2X16X32_0, + 0, + Opcode_ivp_mulsun_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_muln_2x16x32_1", ICLASS_IVP_MULN_2X16X32_1, + 0, + Opcode_ivp_muln_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_muluun_2x16x32_1", ICLASS_IVP_MULUUN_2X16X32_1, + 0, + Opcode_ivp_muluun_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulusn_2x16x32_1", ICLASS_IVP_MULUSN_2X16X32_1, + 0, + Opcode_ivp_mulusn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulsun_2x16x32_1", ICLASS_IVP_MULSUN_2X16X32_1, + 0, + Opcode_ivp_mulsun_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulhn_2x16x32_1", ICLASS_IVP_MULHN_2X16X32_1, + 0, + Opcode_ivp_mulhn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_muluuhn_2x16x32_1", ICLASS_IVP_MULUUHN_2X16X32_1, + 0, + Opcode_ivp_muluuhn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulushn_2x16x32_1", ICLASS_IVP_MULUSHN_2X16X32_1, + 0, + Opcode_ivp_mulushn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulsuhn_2x16x32_1", ICLASS_IVP_MULSUHN_2X16X32_1, + 0, + Opcode_ivp_mulsuhn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulan_2x16x32_0", ICLASS_IVP_MULAN_2X16X32_0, + 0, + Opcode_ivp_mulan_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_muluuan_2x16x32_0", ICLASS_IVP_MULUUAN_2X16X32_0, + 0, + Opcode_ivp_muluuan_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_mulusan_2x16x32_0", ICLASS_IVP_MULUSAN_2X16X32_0, + 0, + Opcode_ivp_mulusan_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_mulsuan_2x16x32_0", ICLASS_IVP_MULSUAN_2X16X32_0, + 0, + Opcode_ivp_mulsuan_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_mulahn_2x16x32_1", ICLASS_IVP_MULAHN_2X16X32_1, + 0, + Opcode_ivp_mulahn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_muluuahn_2x16x32_1", ICLASS_IVP_MULUUAHN_2X16X32_1, + 0, + Opcode_ivp_muluuahn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulusahn_2x16x32_1", ICLASS_IVP_MULUSAHN_2X16X32_1, + 0, + Opcode_ivp_mulusahn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulsuahn_2x16x32_1", ICLASS_IVP_MULSUAHN_2X16X32_1, + 0, + Opcode_ivp_mulsuahn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulan_2x16x32_1", ICLASS_IVP_MULAN_2X16X32_1, + 0, + Opcode_ivp_mulan_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_muluuan_2x16x32_1", ICLASS_IVP_MULUUAN_2X16X32_1, + 0, + Opcode_ivp_muluuan_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulusan_2x16x32_1", ICLASS_IVP_MULUSAN_2X16X32_1, + 0, + Opcode_ivp_mulusan_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulsuan_2x16x32_1", ICLASS_IVP_MULSUAN_2X16X32_1, + 0, + Opcode_ivp_mulsuan_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulshn_2x16x32_1", ICLASS_IVP_MULSHN_2X16X32_1, + 0, + Opcode_ivp_mulshn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_muluushn_2x16x32_1", ICLASS_IVP_MULUUSHN_2X16X32_1, + 0, + Opcode_ivp_muluushn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulusshn_2x16x32_1", ICLASS_IVP_MULUSSHN_2X16X32_1, + 0, + Opcode_ivp_mulusshn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulsushn_2x16x32_1", ICLASS_IVP_MULSUSHN_2X16X32_1, + 0, + Opcode_ivp_mulsushn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulsn_2x16x32_0", ICLASS_IVP_MULSN_2X16X32_0, + 0, + Opcode_ivp_mulsn_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_muluusn_2x16x32_0", ICLASS_IVP_MULUUSN_2X16X32_0, + 0, + Opcode_ivp_muluusn_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_mulussn_2x16x32_0", ICLASS_IVP_MULUSSN_2X16X32_0, + 0, + Opcode_ivp_mulussn_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_mulsusn_2x16x32_0", ICLASS_IVP_MULSUSN_2X16X32_0, + 0, + Opcode_ivp_mulsusn_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_mulsn_2x16x32_1", ICLASS_IVP_MULSN_2X16X32_1, + 0, + Opcode_ivp_mulsn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_muluusn_2x16x32_1", ICLASS_IVP_MULUUSN_2X16X32_1, + 0, + Opcode_ivp_muluusn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulussn_2x16x32_1", ICLASS_IVP_MULUSSN_2X16X32_1, + 0, + Opcode_ivp_mulussn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulsusn_2x16x32_1", ICLASS_IVP_MULSUSN_2X16X32_1, + 0, + Opcode_ivp_mulsusn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_packln_2x96", ICLASS_IVP_PACKLN_2X96, + 0, + Opcode_ivp_packln_2x96_encode_fns, 0, 0 }, + { "ivp_packhn_2x64w", ICLASS_IVP_PACKHN_2X64W, + 0, + Opcode_ivp_packhn_2x64w_encode_fns, 0, 0 }, + { "ivp_packvrn_2x64w", ICLASS_IVP_PACKVRN_2X64W, + 0, + Opcode_ivp_packvrn_2x64w_encode_fns, 0, 0 }, + { "ivp_packvrnrn_2x64w", ICLASS_IVP_PACKVRNRN_2X64W, + 0, + Opcode_ivp_packvrnrn_2x64w_encode_fns, 0, 0 }, + { "ivp_packvrnx48_0", ICLASS_IVP_PACKVRNX48_0, + 0, + Opcode_ivp_packvrnx48_0_encode_fns, 0, 0 }, + { "ivp_packvrnx48_1", ICLASS_IVP_PACKVRNX48_1, + 0, + Opcode_ivp_packvrnx48_1_encode_fns, 0, 0 }, + { "ivp_packvrnrnx48_0", ICLASS_IVP_PACKVRNRNX48_0, + 0, + Opcode_ivp_packvrnrnx48_0_encode_fns, 0, 0 }, + { "ivp_packvrnrnx48_1", ICLASS_IVP_PACKVRNRNX48_1, + 0, + Opcode_ivp_packvrnrnx48_1_encode_fns, 0, 0 }, + { "ivp_packvrnrnx48", ICLASS_IVP_PACKVRNRNX48, + 0, + Opcode_ivp_packvrnrnx48_encode_fns, 0, 0 }, + { "ivp_packvrnr2nx24", ICLASS_IVP_PACKVRNR2NX24, + 0, + Opcode_ivp_packvrnr2nx24_encode_fns, 0, 0 }, + { "ivp_l2a4nx8_ip", ICLASS_IVP_L2A4NX8_IP, + 0, + Opcode_ivp_l2a4nx8_ip_encode_fns, 0, 0 }, + { "ivp_l2au2nx8_ip", ICLASS_IVP_L2AU2NX8_IP, + 0, + Opcode_ivp_l2au2nx8_ip_encode_fns, 0, 0 }, + { "ivp_l2u2nx8_xp", ICLASS_IVP_L2U2NX8_XP, + 0, + Opcode_ivp_l2u2nx8_xp_encode_fns, 0, 0 }, + { "ivp_avgu2nx8", ICLASS_IVP_AVGU2NX8, + 0, + Opcode_ivp_avgu2nx8_encode_fns, 0, 0 }, + { "ivp_avgru2nx8", ICLASS_IVP_AVGRU2NX8, + 0, + Opcode_ivp_avgru2nx8_encode_fns, 0, 0 }, + { "ivp_radd2nx8", ICLASS_IVP_RADD2NX8, + 0, + Opcode_ivp_radd2nx8_encode_fns, 0, 0 }, + { "ivp_radd2nx8t", ICLASS_IVP_RADD2NX8T, + 0, + Opcode_ivp_radd2nx8t_encode_fns, 0, 0 }, + { "ivp_raddunx16", ICLASS_IVP_RADDUNX16, + 0, + Opcode_ivp_raddunx16_encode_fns, 0, 0 }, + { "ivp_raddunx16t", ICLASS_IVP_RADDUNX16T, + 0, + Opcode_ivp_raddunx16t_encode_fns, 0, 0 }, + { "ivp_raddu2nx8", ICLASS_IVP_RADDU2NX8, + 0, + Opcode_ivp_raddu2nx8_encode_fns, 0, 0 }, + { "ivp_raddu2nx8t", ICLASS_IVP_RADDU2NX8T, + 0, + Opcode_ivp_raddu2nx8t_encode_fns, 0, 0 }, + { "ivp_ltrs2n", ICLASS_IVP_LTRS2N, + 0, + Opcode_ivp_ltrs2n_encode_fns, 0, 0 }, + { "ivp_ltrsn", ICLASS_IVP_LTRSN, + 0, + Opcode_ivp_ltrsn_encode_fns, 0, 0 }, + { "ivp_ltrsn_2", ICLASS_IVP_LTRSN_2, + 0, + Opcode_ivp_ltrsn_2_encode_fns, 0, 0 }, + { "ivp_seq2nx8", ICLASS_IVP_SEQ2NX8, + 0, + Opcode_ivp_seq2nx8_encode_fns, 0, 0 }, + { "ivp_seqn_2x32", ICLASS_IVP_SEQN_2X32, + 0, + Opcode_ivp_seqn_2x32_encode_fns, 0, 0 }, + { "ivp_extrn_2x32", ICLASS_IVP_EXTRN_2X32, + 0, + Opcode_ivp_extrn_2x32_encode_fns, 0, 0 }, + { "ivp_unpku2nx8_0", ICLASS_IVP_UNPKU2NX8_0, + 0, + Opcode_ivp_unpku2nx8_0_encode_fns, 0, 0 }, + { "ivp_unpku2nx8_1", ICLASS_IVP_UNPKU2NX8_1, + 0, + Opcode_ivp_unpku2nx8_1_encode_fns, 0, 0 }, + { "ivp_baddnormnx16", ICLASS_IVP_BADDNORMNX16, + 0, + Opcode_ivp_baddnormnx16_encode_fns, 0, 0 }, + { "ivp_bsubnormnx16", ICLASS_IVP_BSUBNORMNX16, + 0, + Opcode_ivp_bsubnormnx16_encode_fns, 0, 0 }, + { "ivp_raddsnx16", ICLASS_IVP_RADDSNX16, + 0, + Opcode_ivp_raddsnx16_encode_fns, 0, 0 }, + { "ivp_raddsnx16t", ICLASS_IVP_RADDSNX16T, + 0, + Opcode_ivp_raddsnx16t_encode_fns, 0, 0 }, + { "ivp_ornotb", ICLASS_IVP_ORNOTB, + 0, + Opcode_ivp_ornotb_encode_fns, 0, 0 }, + { "ivp_extr2nx8", ICLASS_IVP_EXTR2NX8, + 0, + Opcode_ivp_extr2nx8_encode_fns, 0, 0 }, + { "ivp_extrvrn_2x32", ICLASS_IVP_EXTRVRN_2X32, + 0, + Opcode_ivp_extrvrn_2x32_encode_fns, 0, 0 }, + { "ivp_movav8", ICLASS_IVP_MOVAV8, + 0, + Opcode_ivp_movav8_encode_fns, 0, 0 }, + { "ivp_mulpn16xr16", ICLASS_IVP_MULPN16XR16, + 0, + Opcode_ivp_mulpn16xr16_encode_fns, 0, 0 }, + { "ivp_mulpan16xr16", ICLASS_IVP_MULPAN16XR16, + 0, + Opcode_ivp_mulpan16xr16_encode_fns, 0, 0 }, + { "ivp_muluspn16xr16", ICLASS_IVP_MULUSPN16XR16, + 0, + Opcode_ivp_muluspn16xr16_encode_fns, 0, 0 }, + { "ivp_muluspan16xr16", ICLASS_IVP_MULUSPAN16XR16, + 0, + Opcode_ivp_muluspan16xr16_encode_fns, 0, 0 }, + { "ivp_mulp2n8xr16", ICLASS_IVP_MULP2N8XR16, + 0, + Opcode_ivp_mulp2n8xr16_encode_fns, 0, 0 }, + { "ivp_mulpa2n8xr16", ICLASS_IVP_MULPA2N8XR16, + 0, + Opcode_ivp_mulpa2n8xr16_encode_fns, 0, 0 }, + { "ivp_mulusp2n8xr16", ICLASS_IVP_MULUSP2N8XR16, + 0, + Opcode_ivp_mulusp2n8xr16_encode_fns, 0, 0 }, + { "ivp_muluspa2n8xr16", ICLASS_IVP_MULUSPA2N8XR16, + 0, + Opcode_ivp_muluspa2n8xr16_encode_fns, 0, 0 }, + { "ivp_mulpnx16", ICLASS_IVP_MULPNX16, + 0, + Opcode_ivp_mulpnx16_encode_fns, 0, 0 }, + { "ivp_mulpanx16", ICLASS_IVP_MULPANX16, + 0, + Opcode_ivp_mulpanx16_encode_fns, 0, 0 }, + { "ivp_muluspnx16", ICLASS_IVP_MULUSPNX16, + 0, + Opcode_ivp_muluspnx16_encode_fns, 0, 0 }, + { "ivp_muluspanx16", ICLASS_IVP_MULUSPANX16, + 0, + Opcode_ivp_muluspanx16_encode_fns, 0, 0 }, + { "ivp_muluupnx16", ICLASS_IVP_MULUUPNX16, + 0, + Opcode_ivp_muluupnx16_encode_fns, 0, 0 }, + { "ivp_muluupanx16", ICLASS_IVP_MULUUPANX16, + 0, + Opcode_ivp_muluupanx16_encode_fns, 0, 0 }, + { "ivp_mulp2nx8", ICLASS_IVP_MULP2NX8, + 0, + Opcode_ivp_mulp2nx8_encode_fns, 0, 0 }, + { "ivp_mulpa2nx8", ICLASS_IVP_MULPA2NX8, + 0, + Opcode_ivp_mulpa2nx8_encode_fns, 0, 0 }, + { "ivp_mulusp2nx8", ICLASS_IVP_MULUSP2NX8, + 0, + Opcode_ivp_mulusp2nx8_encode_fns, 0, 0 }, + { "ivp_muluspa2nx8", ICLASS_IVP_MULUSPA2NX8, + 0, + Opcode_ivp_muluspa2nx8_encode_fns, 0, 0 }, + { "ivp_muluup2nx8", ICLASS_IVP_MULUUP2NX8, + 0, + Opcode_ivp_muluup2nx8_encode_fns, 0, 0 }, + { "ivp_muluupa2nx8", ICLASS_IVP_MULUUPA2NX8, + 0, + Opcode_ivp_muluupa2nx8_encode_fns, 0, 0 }, + { "ivp_mulpi2nr8x16", ICLASS_IVP_MULPI2NR8X16, + 0, + Opcode_ivp_mulpi2nr8x16_encode_fns, 0, 0 }, + { "ivp_mulpai2nr8x16", ICLASS_IVP_MULPAI2NR8X16, + 0, + Opcode_ivp_mulpai2nr8x16_encode_fns, 0, 0 }, + { "ivp_muluspi2nr8x16", ICLASS_IVP_MULUSPI2NR8X16, + 0, + Opcode_ivp_muluspi2nr8x16_encode_fns, 0, 0 }, + { "ivp_muluspai2nr8x16", ICLASS_IVP_MULUSPAI2NR8X16, + 0, + Opcode_ivp_muluspai2nr8x16_encode_fns, 0, 0 }, + { "ivp_mulq2n8xr8", ICLASS_IVP_MULQ2N8XR8, + 0, + Opcode_ivp_mulq2n8xr8_encode_fns, 0, 0 }, + { "ivp_mulqa2n8xr8", ICLASS_IVP_MULQA2N8XR8, + 0, + Opcode_ivp_mulqa2n8xr8_encode_fns, 0, 0 }, + { "ivp_mulusq2n8xr8", ICLASS_IVP_MULUSQ2N8XR8, + 0, + Opcode_ivp_mulusq2n8xr8_encode_fns, 0, 0 }, + { "ivp_mulusqa2n8xr8", ICLASS_IVP_MULUSQA2N8XR8, + 0, + Opcode_ivp_mulusqa2n8xr8_encode_fns, 0, 0 }, + { "ivp_mul4t2n8xr8", ICLASS_IVP_MUL4T2N8XR8, + 0, + Opcode_ivp_mul4t2n8xr8_encode_fns, 0, 0 }, + { "ivp_mul4ta2n8xr8", ICLASS_IVP_MUL4TA2N8XR8, + 0, + Opcode_ivp_mul4ta2n8xr8_encode_fns, 0, 0 }, + { "ivp_mulus4t2n8xr8", ICLASS_IVP_MULUS4T2N8XR8, + 0, + Opcode_ivp_mulus4t2n8xr8_encode_fns, 0, 0 }, + { "ivp_mulus4ta2n8xr8", ICLASS_IVP_MULUS4TA2N8XR8, + 0, + Opcode_ivp_mulus4ta2n8xr8_encode_fns, 0, 0 }, + { "ivp_addwnx16", ICLASS_IVP_ADDWNX16, + 0, + Opcode_ivp_addwnx16_encode_fns, 0, 0 }, + { "ivp_addwanx16", ICLASS_IVP_ADDWANX16, + 0, + Opcode_ivp_addwanx16_encode_fns, 0, 0 }, + { "ivp_addwsnx16", ICLASS_IVP_ADDWSNX16, + 0, + Opcode_ivp_addwsnx16_encode_fns, 0, 0 }, + { "ivp_addwunx16", ICLASS_IVP_ADDWUNX16, + 0, + Opcode_ivp_addwunx16_encode_fns, 0, 0 }, + { "ivp_addwuanx16", ICLASS_IVP_ADDWUANX16, + 0, + Opcode_ivp_addwuanx16_encode_fns, 0, 0 }, + { "ivp_addwusnx16", ICLASS_IVP_ADDWUSNX16, + 0, + Opcode_ivp_addwusnx16_encode_fns, 0, 0 }, + { "ivp_subwnx16", ICLASS_IVP_SUBWNX16, + 0, + Opcode_ivp_subwnx16_encode_fns, 0, 0 }, + { "ivp_subwanx16", ICLASS_IVP_SUBWANX16, + 0, + Opcode_ivp_subwanx16_encode_fns, 0, 0 }, + { "ivp_subwunx16", ICLASS_IVP_SUBWUNX16, + 0, + Opcode_ivp_subwunx16_encode_fns, 0, 0 }, + { "ivp_subwuanx16", ICLASS_IVP_SUBWUANX16, + 0, + Opcode_ivp_subwuanx16_encode_fns, 0, 0 }, + { "ivp_subw2nx8", ICLASS_IVP_SUBW2NX8, + 0, + Opcode_ivp_subw2nx8_encode_fns, 0, 0 }, + { "ivp_subwa2nx8", ICLASS_IVP_SUBWA2NX8, + 0, + Opcode_ivp_subwa2nx8_encode_fns, 0, 0 }, + { "ivp_subwu2nx8", ICLASS_IVP_SUBWU2NX8, + 0, + Opcode_ivp_subwu2nx8_encode_fns, 0, 0 }, + { "ivp_subwua2nx8", ICLASS_IVP_SUBWUA2NX8, + 0, + Opcode_ivp_subwua2nx8_encode_fns, 0, 0 }, + { "ivp_randb2n", ICLASS_IVP_RANDB2N, + 0, + Opcode_ivp_randb2n_encode_fns, 0, 0 }, + { "ivp_rorb2n", ICLASS_IVP_RORB2N, + 0, + Opcode_ivp_rorb2n_encode_fns, 0, 0 }, + { "ivp_randbn", ICLASS_IVP_RANDBN, + 0, + Opcode_ivp_randbn_encode_fns, 0, 0 }, + { "ivp_rorbn", ICLASS_IVP_RORBN, + 0, + Opcode_ivp_rorbn_encode_fns, 0, 0 }, + { "ivp_randbn_2", ICLASS_IVP_RANDBN_2, + 0, + Opcode_ivp_randbn_2_encode_fns, 0, 0 }, + { "ivp_rorbn_2", ICLASS_IVP_RORBN_2, + 0, + Opcode_ivp_rorbn_2_encode_fns, 0, 0 }, + { "ivp_avgnx16", ICLASS_IVP_AVGNX16, + 0, + Opcode_ivp_avgnx16_encode_fns, 0, 0 }, + { "ivp_avgunx16", ICLASS_IVP_AVGUNX16, + 0, + Opcode_ivp_avgunx16_encode_fns, 0, 0 }, + { "ivp_avg2nx8", ICLASS_IVP_AVG2NX8, + 0, + Opcode_ivp_avg2nx8_encode_fns, 0, 0 }, + { "ivp_avgr2nx8", ICLASS_IVP_AVGR2NX8, + 0, + Opcode_ivp_avgr2nx8_encode_fns, 0, 0 }, + { "ivp_avgrnx16", ICLASS_IVP_AVGRNX16, + 0, + Opcode_ivp_avgrnx16_encode_fns, 0, 0 }, + { "ivp_avgrunx16", ICLASS_IVP_AVGRUNX16, + 0, + Opcode_ivp_avgrunx16_encode_fns, 0, 0 }, + { "ivp_gatheranx8u", ICLASS_IVP_GATHERANX8U, + 0, + Opcode_ivp_gatheranx8u_encode_fns, 0, 0 }, + { "ivp_gatheranx16", ICLASS_IVP_GATHERANX16, + 0, + Opcode_ivp_gatheranx16_encode_fns, 0, 0 }, + { "ivp_gatheran_2x32", ICLASS_IVP_GATHERAN_2X32, + 0, + Opcode_ivp_gatheran_2x32_encode_fns, 0, 0 }, + { "ivp_gatheranx8ut", ICLASS_IVP_GATHERANX8UT, + 0, + Opcode_ivp_gatheranx8ut_encode_fns, 0, 0 }, + { "ivp_gatheranx16t", ICLASS_IVP_GATHERANX16T, + 0, + Opcode_ivp_gatheranx16t_encode_fns, 0, 0 }, + { "ivp_gatheran_2x32t", ICLASS_IVP_GATHERAN_2X32T, + 0, + Opcode_ivp_gatheran_2x32t_encode_fns, 0, 0 }, + { "ivp_gatherdnx16", ICLASS_IVP_GATHERDNX16, + 0, + Opcode_ivp_gatherdnx16_encode_fns, 0, 0 }, + { "ivp_gatherdnx8s", ICLASS_IVP_GATHERDNX8S, + 0, + Opcode_ivp_gatherdnx8s_encode_fns, 0, 0 }, + { "ivp_gatherd2nx8_l", ICLASS_IVP_GATHERD2NX8_L, + 0, + Opcode_ivp_gatherd2nx8_l_encode_fns, 0, 0 }, + { "ivp_gatherd2nx8_h", ICLASS_IVP_GATHERD2NX8_H, + 0, + Opcode_ivp_gatherd2nx8_h_encode_fns, 0, 0 }, + { "ivp_movgatherd", ICLASS_IVP_MOVGATHERD, + 0, + Opcode_ivp_movgatherd_encode_fns, 0, 0 }, + { "ivp_scatternx8u", ICLASS_IVP_SCATTERNX8U, + 0, + Opcode_ivp_scatternx8u_encode_fns, 0, 0 }, + { "ivp_scatter2nx8_l", ICLASS_IVP_SCATTER2NX8_L, + 0, + Opcode_ivp_scatter2nx8_l_encode_fns, 0, 0 }, + { "ivp_scatter2nx8_h", ICLASS_IVP_SCATTER2NX8_H, + 0, + Opcode_ivp_scatter2nx8_h_encode_fns, 0, 0 }, + { "ivp_scatternx16", ICLASS_IVP_SCATTERNX16, + 0, + Opcode_ivp_scatternx16_encode_fns, 0, 0 }, + { "ivp_scattern_2x32", ICLASS_IVP_SCATTERN_2X32, + 0, + Opcode_ivp_scattern_2x32_encode_fns, 0, 0 }, + { "ivp_scatternx8ut", ICLASS_IVP_SCATTERNX8UT, + 0, + Opcode_ivp_scatternx8ut_encode_fns, 0, 0 }, + { "ivp_scatter2nx8t_l", ICLASS_IVP_SCATTER2NX8T_L, + 0, + Opcode_ivp_scatter2nx8t_l_encode_fns, 0, 0 }, + { "ivp_scatter2nx8t_h", ICLASS_IVP_SCATTER2NX8T_H, + 0, + Opcode_ivp_scatter2nx8t_h_encode_fns, 0, 0 }, + { "ivp_scatternx16t", ICLASS_IVP_SCATTERNX16T, + 0, + Opcode_ivp_scatternx16t_encode_fns, 0, 0 }, + { "ivp_scattern_2x32t", ICLASS_IVP_SCATTERN_2X32T, + 0, + Opcode_ivp_scattern_2x32t_encode_fns, 0, 0 }, + { "ivp_scatterw", ICLASS_IVP_SCATTERW, + 0, + Opcode_ivp_scatterw_encode_fns, 0, 0 }, + { "ivp_counteqz4nx8", ICLASS_IVP_COUNTEQZ4NX8, + 0, + Opcode_ivp_counteqz4nx8_encode_fns, 0, 0 }, + { "ivp_counteq4nx8", ICLASS_IVP_COUNTEQ4NX8, + 0, + Opcode_ivp_counteq4nx8_encode_fns, 0, 0 }, + { "ivp_counteqmz4nx8", ICLASS_IVP_COUNTEQMZ4NX8, + 0, + Opcode_ivp_counteqmz4nx8_encode_fns, 0, 0 }, + { "ivp_counteqm4nx8", ICLASS_IVP_COUNTEQM4NX8, + 0, + Opcode_ivp_counteqm4nx8_encode_fns, 0, 0 }, + { "ivp_countlez4nx8", ICLASS_IVP_COUNTLEZ4NX8, + 0, + Opcode_ivp_countlez4nx8_encode_fns, 0, 0 }, + { "ivp_countle4nx8", ICLASS_IVP_COUNTLE4NX8, + 0, + Opcode_ivp_countle4nx8_encode_fns, 0, 0 }, + { "ivp_countlemz4nx8", ICLASS_IVP_COUNTLEMZ4NX8, + 0, + Opcode_ivp_countlemz4nx8_encode_fns, 0, 0 }, + { "ivp_countlem4nx8", ICLASS_IVP_COUNTLEM4NX8, + 0, + Opcode_ivp_countlem4nx8_encode_fns, 0, 0 }, + { "ivp_lsr2nx8_i", ICLASS_IVP_LSR2NX8_I, + 0, + Opcode_ivp_lsr2nx8_i_encode_fns, 0, 0 }, + { "ivp_lsr2nx8_ip", ICLASS_IVP_LSR2NX8_IP, + 0, + Opcode_ivp_lsr2nx8_ip_encode_fns, 0, 0 }, + { "ivp_lsr2nx8_x", ICLASS_IVP_LSR2NX8_X, + 0, + Opcode_ivp_lsr2nx8_x_encode_fns, 0, 0 }, + { "ivp_lsr2nx8_xp", ICLASS_IVP_LSR2NX8_XP, + 0, + Opcode_ivp_lsr2nx8_xp_encode_fns, 0, 0 }, + { "ivp_lsrnx16_i", ICLASS_IVP_LSRNX16_I, + 0, + Opcode_ivp_lsrnx16_i_encode_fns, 0, 0 }, + { "ivp_lsrnx16_ip", ICLASS_IVP_LSRNX16_IP, + 0, + Opcode_ivp_lsrnx16_ip_encode_fns, 0, 0 }, + { "ivp_lsrnx16_x", ICLASS_IVP_LSRNX16_X, + 0, + Opcode_ivp_lsrnx16_x_encode_fns, 0, 0 }, + { "ivp_lsrnx16_xp", ICLASS_IVP_LSRNX16_XP, + 0, + Opcode_ivp_lsrnx16_xp_encode_fns, 0, 0 }, + { "ivp_lsrn_2x32_i", ICLASS_IVP_LSRN_2X32_I, + 0, + Opcode_ivp_lsrn_2x32_i_encode_fns, 0, 0 }, + { "ivp_lsrn_2x32_ip", ICLASS_IVP_LSRN_2X32_IP, + 0, + Opcode_ivp_lsrn_2x32_ip_encode_fns, 0, 0 }, + { "ivp_lsrn_2x32_x", ICLASS_IVP_LSRN_2X32_X, + 0, + Opcode_ivp_lsrn_2x32_x_encode_fns, 0, 0 }, + { "ivp_lsrn_2x32_xp", ICLASS_IVP_LSRN_2X32_XP, + 0, + Opcode_ivp_lsrn_2x32_xp_encode_fns, 0, 0 }, + { "ivp_absnx16", ICLASS_IVP_ABSNX16, + 0, + Opcode_ivp_absnx16_encode_fns, 0, 0 }, + { "ivp_abssnx16", ICLASS_IVP_ABSSNX16, + 0, + Opcode_ivp_abssnx16_encode_fns, 0, 0 }, + { "ivp_abssubnx16", ICLASS_IVP_ABSSUBNX16, + 0, + Opcode_ivp_abssubnx16_encode_fns, 0, 0 }, + { "ivp_abssubunx16", ICLASS_IVP_ABSSUBUNX16, + 0, + Opcode_ivp_abssubunx16_encode_fns, 0, 0 }, + { "ivp_absssubnx16", ICLASS_IVP_ABSSSUBNX16, + 0, + Opcode_ivp_absssubnx16_encode_fns, 0, 0 }, + { "excw", ICLASS_xt_iclass_excw, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", ICLASS_xt_iclass_rfe, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", ICLASS_xt_iclass_rfde, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", ICLASS_xt_iclass_syscall, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "call12", ICLASS_xt_iclass_call12, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", ICLASS_xt_iclass_call8, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", ICLASS_xt_iclass_call4, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", ICLASS_xt_iclass_callx12, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", ICLASS_xt_iclass_callx8, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", ICLASS_xt_iclass_callx4, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", ICLASS_xt_iclass_entry, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", ICLASS_xt_iclass_movsp, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", ICLASS_xt_iclass_rotw, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", ICLASS_xt_iclass_l32e, + 0, + Opcode_l32e_encode_fns, 0, 0 }, + { "s32e", ICLASS_xt_iclass_s32e, + 0, + Opcode_s32e_encode_fns, 0, 0 }, + { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", ICLASS_xt_iclass_add_n, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", ICLASS_xt_iclass_addi_n, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", ICLASS_xt_iclass_ill_n, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", ICLASS_xt_iclass_loadi4, + 0, + Opcode_l32i_n_encode_fns, 0, 0 }, + { "mov.n", ICLASS_xt_iclass_mov_n, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", ICLASS_xt_iclass_movi_n, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", ICLASS_xt_iclass_nopn, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", ICLASS_xt_iclass_retn, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", ICLASS_xt_iclass_storei4, + 0, + Opcode_s32i_n_encode_fns, 0, 0 }, + { "rur.threadptr", ICLASS_rur_threadptr, + 0, + Opcode_rur_threadptr_encode_fns, 0, 0 }, + { "wur.threadptr", ICLASS_wur_threadptr, + 0, + Opcode_wur_threadptr_encode_fns, 0, 0 }, + { "addi", ICLASS_xt_iclass_addi, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", ICLASS_xt_iclass_addmi, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", ICLASS_xt_iclass_addsub, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "sub", ICLASS_xt_iclass_addsub, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "addx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "subx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", ICLASS_xt_iclass_bit, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", ICLASS_xt_iclass_bit, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", ICLASS_xt_iclass_bit, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bnei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bgei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bbci", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "beq", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bne", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bge", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "blt", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bgeu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "bltu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bany", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bnone", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "ball", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bnall", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bbc", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beqz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bnez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "bgez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "call0", ICLASS_xt_iclass_call0, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", ICLASS_xt_iclass_callx0, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "const16", ICLASS_xt_iclass_const16, + 0, + Opcode_const16_encode_fns, 0, 0 }, + { "extui", ICLASS_xt_iclass_exti, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", ICLASS_xt_iclass_ill, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", ICLASS_xt_iclass_jump, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", ICLASS_xt_iclass_jumpx, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", ICLASS_xt_iclass_l16ui, + 0, + Opcode_l16ui_encode_fns, 0, 0 }, + { "l16si", ICLASS_xt_iclass_l16si, + 0, + Opcode_l16si_encode_fns, 0, 0 }, + { "l32i", ICLASS_xt_iclass_l32i, + 0, + Opcode_l32i_encode_fns, 0, 0 }, + { "l32r", ICLASS_xt_iclass_l32r, + 0, + Opcode_l32r_encode_fns, 0, 0 }, + { "l8ui", ICLASS_xt_iclass_l8i, + 0, + Opcode_l8ui_encode_fns, 0, 0 }, + { "loop", ICLASS_xt_iclass_loop, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopnez", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "loopgtz", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "movi", ICLASS_xt_iclass_movi, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", ICLASS_xt_iclass_movz, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movnez", ICLASS_xt_iclass_movz, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "movltz", ICLASS_xt_iclass_movz, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movgez", ICLASS_xt_iclass_movz, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "neg", ICLASS_xt_iclass_neg, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "abs", ICLASS_xt_iclass_neg, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "nop", ICLASS_xt_iclass_nop, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "l32ex", ICLASS_xt_iclass_l32ex, + 0, + Opcode_l32ex_encode_fns, 0, 0 }, + { "s32ex", ICLASS_xt_iclass_s32ex, + 0, + Opcode_s32ex_encode_fns, 0, 0 }, + { "getex", ICLASS_xt_iclass_getex, + 0, + Opcode_getex_encode_fns, 0, 0 }, + { "clrex", ICLASS_xt_iclass_clrex, + 0, + Opcode_clrex_encode_fns, 0, 0 }, + { "ret", ICLASS_xt_iclass_return, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "simcall", ICLASS_xt_iclass_simcall, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "s16i", ICLASS_xt_iclass_s16i, + 0, + Opcode_s16i_encode_fns, 0, 0 }, + { "s32i", ICLASS_xt_iclass_s32i, + 0, + Opcode_s32i_encode_fns, 0, 0 }, + { "s32nb", ICLASS_xt_iclass_s32nb, + 0, + Opcode_s32nb_encode_fns, 0, 0 }, + { "s8i", ICLASS_xt_iclass_s8i, + 0, + Opcode_s8i_encode_fns, 0, 0 }, + { "ssr", ICLASS_xt_iclass_sar, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssl", ICLASS_xt_iclass_sar, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssa8l", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssa8b", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssai", ICLASS_xt_iclass_sari, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", ICLASS_xt_iclass_shifts, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", ICLASS_xt_iclass_shiftst, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "srl", ICLASS_xt_iclass_shiftt, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "sra", ICLASS_xt_iclass_shiftt, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "slli", ICLASS_xt_iclass_slli, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", ICLASS_xt_iclass_srai, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", ICLASS_xt_iclass_srli, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", ICLASS_xt_iclass_memw, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", ICLASS_xt_iclass_extw, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", ICLASS_xt_iclass_isync, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "rsync", ICLASS_xt_iclass_sync, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "esync", ICLASS_xt_iclass_sync, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "dsync", ICLASS_xt_iclass_sync, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "rsil", ICLASS_xt_iclass_rsil, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", ICLASS_xt_iclass_rsr_lend, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", ICLASS_xt_iclass_wsr_lend, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", ICLASS_xt_iclass_xsr_lend, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", ICLASS_xt_iclass_rsr_sar, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", ICLASS_xt_iclass_wsr_sar, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", ICLASS_xt_iclass_xsr_sar, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, + 0, + Opcode_rsr_memctl_encode_fns, 0, 0 }, + { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, + 0, + Opcode_wsr_memctl_encode_fns, 0, 0 }, + { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, + 0, + Opcode_xsr_memctl_encode_fns, 0, 0 }, + { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, + 0, + Opcode_rsr_litbase_encode_fns, 0, 0 }, + { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, + 0, + Opcode_wsr_litbase_encode_fns, 0, 0 }, + { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, + 0, + Opcode_xsr_litbase_encode_fns, 0, 0 }, + { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, + 0, + Opcode_rsr_configid0_encode_fns, 0, 0 }, + { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, + 0, + Opcode_wsr_configid0_encode_fns, 0, 0 }, + { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, + 0, + Opcode_rsr_configid1_encode_fns, 0, 0 }, + { "rsr.ps", ICLASS_xt_iclass_rsr_ps, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", ICLASS_xt_iclass_wsr_ps, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", ICLASS_xt_iclass_xsr_ps, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", ICLASS_xt_iclass_rsr_depc, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", ICLASS_xt_iclass_wsr_depc, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", ICLASS_xt_iclass_xsr_depc, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.prid", ICLASS_xt_iclass_rsr_prid, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "rsr.mpucfg", ICLASS_xt_iclass_rsr_mpucfg, + 0, + Opcode_rsr_mpucfg_encode_fns, 0, 0 }, + { "wsr.mpucfg", ICLASS_xt_iclass_wsr_mpucfg, + 0, + Opcode_wsr_mpucfg_encode_fns, 0, 0 }, + { "rsr.gserr", ICLASS_xt_iclass_rsr_gserr, + 0, + Opcode_rsr_gserr_encode_fns, 0, 0 }, + { "wsr.gserr", ICLASS_xt_iclass_wsr_gserr, + 0, + Opcode_wsr_gserr_encode_fns, 0, 0 }, + { "xsr.gserr", ICLASS_xt_iclass_xsr_gserr, + 0, + Opcode_xsr_gserr_encode_fns, 0, 0 }, + { "salt", ICLASS_xt_iclass_salt, + 0, + Opcode_salt_encode_fns, 0, 0 }, + { "saltu", ICLASS_xt_iclass_salt, + 0, + Opcode_saltu_encode_fns, 0, 0 }, + { "mul16u", ICLASS_xt_mul16, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mul16s", ICLASS_xt_mul16, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "mull", ICLASS_xt_mul32, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "muluh", ICLASS_xt_mul32h, + 0, + Opcode_muluh_encode_fns, 0, 0 }, + { "mulsh", ICLASS_xt_mul32h, + 0, + Opcode_mulsh_encode_fns, 0, 0 }, + { "rfi", ICLASS_xt_iclass_rfi, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", ICLASS_xt_iclass_wait, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", ICLASS_xt_iclass_wsr_intset, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", ICLASS_xt_iclass_break, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", ICLASS_xt_iclass_break_n, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", ICLASS_xt_iclass_rsr_icount, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", ICLASS_xt_iclass_wsr_icount, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", ICLASS_xt_iclass_xsr_icount, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "lddr32.p", ICLASS_xt_iclass_lddr32_p, + 0, + Opcode_lddr32_p_encode_fns, 0, 0 }, + { "sddr32.p", ICLASS_xt_iclass_sddr32_p, + 0, + Opcode_sddr32_p_encode_fns, 0, 0 }, + { "rfdo", ICLASS_xt_iclass_rfdo, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", ICLASS_xt_iclass_rfdd, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "andb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andb_encode_fns, 0, 0 }, + { "andbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andbc_encode_fns, 0, 0 }, + { "orb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orb_encode_fns, 0, 0 }, + { "orbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orbc_encode_fns, 0, 0 }, + { "xorb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_xorb_encode_fns, 0, 0 }, + { "any4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_any4_encode_fns, 0, 0 }, + { "all4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_all4_encode_fns, 0, 0 }, + { "any8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_any8_encode_fns, 0, 0 }, + { "all8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_all8_encode_fns, 0, 0 }, + { "bf", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bf_encode_fns, 0, 0 }, + { "bt", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bt_encode_fns, 0, 0 }, + { "movf", ICLASS_xt_iclass_bmove, + 0, + Opcode_movf_encode_fns, 0, 0 }, + { "movt", ICLASS_xt_iclass_bmove, + 0, + Opcode_movt_encode_fns, 0, 0 }, + { "rsr.br", ICLASS_xt_iclass_RSR_BR, + 0, + Opcode_rsr_br_encode_fns, 0, 0 }, + { "wsr.br", ICLASS_xt_iclass_WSR_BR, + 0, + Opcode_wsr_br_encode_fns, 0, 0 }, + { "xsr.br", ICLASS_xt_iclass_XSR_BR, + 0, + Opcode_xsr_br_encode_fns, 0, 0 }, + { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "ipf", ICLASS_xt_iclass_icache, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihi", ICLASS_xt_iclass_icache, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "ipfl", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ipfl_encode_fns, 0, 0 }, + { "ihu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ihu_encode_fns, 0, 0 }, + { "iiu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_iiu_encode_fns, 0, 0 }, + { "iii", ICLASS_xt_iclass_icache_inv, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", ICLASS_xt_iclass_licx, + 0, + Opcode_lict_encode_fns, 0, 0 }, + { "licw", ICLASS_xt_iclass_licx, + 0, + Opcode_licw_encode_fns, 0, 0 }, + { "sict", ICLASS_xt_iclass_sicx, + 0, + Opcode_sict_encode_fns, 0, 0 }, + { "sicw", ICLASS_xt_iclass_sicx, + 0, + Opcode_sicw_encode_fns, 0, 0 }, + { "wsr.cacheadrdis", ICLASS_xt_iclass_wsr_cacheadrdis, + 0, + Opcode_wsr_cacheadrdis_encode_fns, 0, 0 }, + { "rsr.cacheadrdis", ICLASS_xt_iclass_rsr_cacheadrdis, + 0, + Opcode_rsr_cacheadrdis_encode_fns, 0, 0 }, + { "xsr.cacheadrdis", ICLASS_xt_iclass_xsr_cacheadrdis, + 0, + Opcode_xsr_cacheadrdis_encode_fns, 0, 0 }, + { "rptlb0", ICLASS_xt_iclass_rptlb0, + 0, + Opcode_rptlb0_encode_fns, 0, 0 }, + { "pptlb", ICLASS_xt_iclass_rptlb, + 0, + Opcode_pptlb_encode_fns, 0, 0 }, + { "rptlb1", ICLASS_xt_iclass_rptlb, + 0, + Opcode_rptlb1_encode_fns, 0, 0 }, + { "wptlb", ICLASS_xt_iclass_wptlb, + 0, + Opcode_wptlb_encode_fns, 0, 0 }, + { "rsr.mpuenb", ICLASS_xt_iclass_rsr_mpuenb, + 0, + Opcode_rsr_mpuenb_encode_fns, 0, 0 }, + { "wsr.mpuenb", ICLASS_xt_iclass_wsr_mpuenb, + 0, + Opcode_wsr_mpuenb_encode_fns, 0, 0 }, + { "xsr.mpuenb", ICLASS_xt_iclass_xsr_mpuenb, + 0, + Opcode_xsr_mpuenb_encode_fns, 0, 0 }, + { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, + 0, + Opcode_rsr_cpenable_encode_fns, 0, 0 }, + { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, + 0, + Opcode_wsr_cpenable_encode_fns, 0, 0 }, + { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, + 0, + Opcode_xsr_cpenable_encode_fns, 0, 0 }, + { "clamps", ICLASS_xt_iclass_clamp, + 0, + Opcode_clamps_encode_fns, 0, 0 }, + { "min", ICLASS_xt_iclass_minmax, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "max", ICLASS_xt_iclass_minmax, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "minu", ICLASS_xt_iclass_minmax, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "maxu", ICLASS_xt_iclass_minmax, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "nsa", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", ICLASS_xt_iclass_sx, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", ICLASS_xt_iclass_l32ai, + 0, + Opcode_l32ai_encode_fns, 0, 0 }, + { "s32ri", ICLASS_xt_iclass_s32ri, + 0, + Opcode_s32ri_encode_fns, 0, 0 }, + { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, + 0, + Opcode_rsr_atomctl_encode_fns, 0, 0 }, + { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, + 0, + Opcode_wsr_atomctl_encode_fns, 0, 0 }, + { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, + 0, + Opcode_xsr_atomctl_encode_fns, 0, 0 }, + { "quou", ICLASS_xt_iclass_div, + 0, + Opcode_quou_encode_fns, 0, 0 }, + { "quos", ICLASS_xt_iclass_div, + 0, + Opcode_quos_encode_fns, 0, 0 }, + { "remu", ICLASS_xt_iclass_div, + 0, + Opcode_remu_encode_fns, 0, 0 }, + { "rems", ICLASS_xt_iclass_div, + 0, + Opcode_rems_encode_fns, 0, 0 }, + { "rsr.eraccess", ICLASS_xt_iclass_rsr_eraccess, + 0, + Opcode_rsr_eraccess_encode_fns, 0, 0 }, + { "wsr.eraccess", ICLASS_xt_iclass_wsr_eraccess, + 0, + Opcode_wsr_eraccess_encode_fns, 0, 0 }, + { "xsr.eraccess", ICLASS_xt_iclass_xsr_eraccess, + 0, + Opcode_xsr_eraccess_encode_fns, 0, 0 }, + { "rer", ICLASS_xt_iclass_rer, + 0, + Opcode_rer_encode_fns, 0, 0 }, + { "wer", ICLASS_xt_iclass_wer, + 0, + Opcode_wer_encode_fns, 0, 0 }, + { "beqz.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_w15_encode_fns, 0, 0 }, + { "bnez.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_w15_encode_fns, 0, 0 }, + { "bgez.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_w15_encode_fns, 0, 0 }, + { "bltz.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_w15_encode_fns, 0, 0 }, + { "beqi.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_w15_encode_fns, 0, 0 }, + { "bnei.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_w15_encode_fns, 0, 0 }, + { "bgei.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_w15_encode_fns, 0, 0 }, + { "blti.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_w15_encode_fns, 0, 0 }, + { "bgeui.w15", ICLASS_xt_iclass_wb15_2, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_w15_encode_fns, 0, 0 }, + { "bltui.w15", ICLASS_xt_iclass_wb15_2, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_w15_encode_fns, 0, 0 }, + { "bbci.w15", ICLASS_xt_iclass_wb15_3, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_w15_encode_fns, 0, 0 }, + { "bbsi.w15", ICLASS_xt_iclass_wb15_3, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_w15_encode_fns, 0, 0 }, + { "beq.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_w15_encode_fns, 0, 0 }, + { "bne.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_w15_encode_fns, 0, 0 }, + { "bge.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_w15_encode_fns, 0, 0 }, + { "blt.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_w15_encode_fns, 0, 0 }, + { "bgeu.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_w15_encode_fns, 0, 0 }, + { "bltu.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_w15_encode_fns, 0, 0 }, + { "bany.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_w15_encode_fns, 0, 0 }, + { "bnone.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_w15_encode_fns, 0, 0 }, + { "ball.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_w15_encode_fns, 0, 0 }, + { "bnall.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_w15_encode_fns, 0, 0 }, + { "bbc.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_w15_encode_fns, 0, 0 }, + { "bbs.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_w15_encode_fns, 0, 0 }, + { "mtk_andpopc", ICLASS_MTK_AndPOPC, + 0, + Opcode_mtk_andpopc_encode_fns, 0, 0 }, + { "iq_tie2apb_inq0_pop", ICLASS_iq_tie2apb_inq0_pop, + 0, + Opcode_iq_tie2apb_inq0_pop_encode_fns, 0, 0 }, + { "iq_tie2apb_inq0_is_ready", ICLASS_iq_tie2apb_inq0_is_ready, + 0, + Opcode_iq_tie2apb_inq0_is_ready_encode_fns, 0, 0 }, + { "iq_tie2apb_inq0_nonblocking_peek", ICLASS_iq_tie2apb_inq0_nonblocking_peek, + 0, + Opcode_iq_tie2apb_inq0_nonblocking_peek_encode_fns, 0, 0 }, + { "iq_tie2apb_inq0_nonblocking_pop", ICLASS_iq_tie2apb_inq0_nonblocking_pop, + 0, + Opcode_iq_tie2apb_inq0_nonblocking_pop_encode_fns, 0, 0 }, + { "iq_tie2apb_inq0_blocking_peek", ICLASS_iq_tie2apb_inq0_blocking_peek, + 0, + Opcode_iq_tie2apb_inq0_blocking_peek_encode_fns, 0, 0 }, + { "oq_tie2apb_outq0_push_read", ICLASS_oq_tie2apb_outq0_push_read, + 0, + Opcode_oq_tie2apb_outq0_push_read_encode_fns, 0, 0 }, + { "oq_tie2apb_outq0_push_write", ICLASS_oq_tie2apb_outq0_push_write, + 0, + Opcode_oq_tie2apb_outq0_push_write_encode_fns, 0, 0 }, + { "oq_tie2apb_outq0_is_ready", ICLASS_oq_tie2apb_outq0_is_ready, + 0, + Opcode_oq_tie2apb_outq0_is_ready_encode_fns, 0, 0 }, + { "oq_tie2apb_outq0_nonblocking_push_read", ICLASS_oq_tie2apb_outq0_nonblocking_push_read, + 0, + Opcode_oq_tie2apb_outq0_nonblocking_push_read_encode_fns, 0, 0 }, + { "oq_tie2apb_outq0_nonblocking_push_write", ICLASS_oq_tie2apb_outq0_nonblocking_push_write, + 0, + Opcode_oq_tie2apb_outq0_nonblocking_push_write_encode_fns, 0, 0 }, + { "rur.apb_pipe", ICLASS_rur_apb_pipe, + 0, + Opcode_rur_apb_pipe_encode_fns, 0, 0 }, + { "wur.apb_pipe", ICLASS_wur_apb_pipe, + 0, + Opcode_wur_apb_pipe_encode_fns, 0, 0 } +}; + +enum xtensa_opcode_id { + OPCODE_IVP_REPNX16, + OPCODE_IVP_SELSNX16, + OPCODE_IVP_REP2NX8, + OPCODE_IVP_SELS2NX8, + OPCODE_IVP_REPN_2X32, + OPCODE_IVP_SELSN_2X32, + OPCODE_IVP_EXT0IB, + OPCODE_IVP_NOTB, + OPCODE_IVP_ANDB, + OPCODE_IVP_ORB, + OPCODE_IVP_XORB, + OPCODE_IVP_ANDNOTB, + OPCODE_IVP_MB, + OPCODE_IVP_LTRN, + OPCODE_IVP_LTRNI, + OPCODE_IVP_LBN_I, + OPCODE_IVP_LBN_IP, + OPCODE_IVP_SBN_I, + OPCODE_IVP_SBN_IP, + OPCODE_IVP_LSNX16_I, + OPCODE_IVP_LSNX16_IP, + OPCODE_IVP_LSNX16_X, + OPCODE_IVP_LSNX16_XP, + OPCODE_IVP_MOVBRBV, + OPCODE_IVP_MOVBVBR, + OPCODE_IVP_JOINB, + OPCODE_IVP_LTRN_2, + OPCODE_IVP_LTRN_2I, + OPCODE_IVP_LBN_2_I, + OPCODE_IVP_LBN_2_IP, + OPCODE_IVP_SBN_2_I, + OPCODE_IVP_SBN_2_IP, + OPCODE_IVP_LV2NX8_I, + OPCODE_IVP_LV2NX8_IP, + OPCODE_IVP_LV2NX8_X, + OPCODE_IVP_LV2NX8_XP, + OPCODE_IVP_SV2NX8_I, + OPCODE_IVP_SV2NX8_IP, + OPCODE_IVP_SV2NX8_X, + OPCODE_IVP_SV2NX8_XP, + OPCODE_IVP_SSNX16_I, + OPCODE_IVP_SSNX16_IP, + OPCODE_IVP_SSNX16_X, + OPCODE_IVP_SSNX16_XP, + OPCODE_IVP_MOVVA16, + OPCODE_IVP_MOVVV, + OPCODE_IVP_SLLINX16, + OPCODE_IVP_SLSINX16, + OPCODE_IVP_SRAINX16, + OPCODE_IVP_SRLINX16, + OPCODE_IVP_SLLNX16, + OPCODE_IVP_SRLNX16, + OPCODE_IVP_SLANX16, + OPCODE_IVP_SRANX16, + OPCODE_IVP_SLSNX16, + OPCODE_IVP_SRSNX16, + OPCODE_IVP_XOR2NX8, + OPCODE_IVP_AND2NX8, + OPCODE_IVP_OR2NX8, + OPCODE_IVP_NOT2NX8, + OPCODE_IVP_ADDNX16, + OPCODE_IVP_SUBNX16, + OPCODE_IVP_NEGNX16, + OPCODE_IVP_MINNX16, + OPCODE_IVP_MINUNX16, + OPCODE_IVP_MAXNX16, + OPCODE_IVP_MAXUNX16, + OPCODE_IVP_MULSGNNX16, + OPCODE_IVP_NSANX16, + OPCODE_IVP_NSAUNX16, + OPCODE_IVP_LTNX16, + OPCODE_IVP_LENX16, + OPCODE_IVP_EQNX16, + OPCODE_IVP_NEQNX16, + OPCODE_IVP_LTUNX16, + OPCODE_IVP_LEUNX16, + OPCODE_IVP_RADDNX16, + OPCODE_IVP_RMAXNX16, + OPCODE_IVP_RMINNX16, + OPCODE_IVP_RMAXUNX16, + OPCODE_IVP_RMINUNX16, + OPCODE_IVP_RBMINNX16, + OPCODE_IVP_RBMAXNX16, + OPCODE_IVP_BMAXNX16, + OPCODE_IVP_BMINNX16, + OPCODE_IVP_MOV2NX8T, + OPCODE_IVP_MULANX16PACKL, + OPCODE_IVP_MULANX16PACKQ, + OPCODE_IVP_MULSNX16PACKL, + OPCODE_IVP_MULSNX16PACKQ, + OPCODE_IVP_ADDSNX16, + OPCODE_IVP_SUBSNX16, + OPCODE_IVP_NEGSNX16, + OPCODE_IVP_LV2NX8T_I, + OPCODE_IVP_LV2NX8T_IP, + OPCODE_IVP_LV2NX8T_X, + OPCODE_IVP_LV2NX8T_XP, + OPCODE_IVP_SV2NX8T_I, + OPCODE_IVP_SV2NX8T_IP, + OPCODE_IVP_SV2NX8T_X, + OPCODE_IVP_SV2NX8T_XP, + OPCODE_IVP_RADDNX16T, + OPCODE_IVP_RMAXNX16T, + OPCODE_IVP_RMINNX16T, + OPCODE_IVP_RMAXUNX16T, + OPCODE_IVP_RMINUNX16T, + OPCODE_IVP_ADDNX16T, + OPCODE_IVP_SUBNX16T, + OPCODE_IVP_NEGNX16T, + OPCODE_IVP_MAXNX16T, + OPCODE_IVP_MINNX16T, + OPCODE_IVP_MAXUNX16T, + OPCODE_IVP_MINUNX16T, + OPCODE_IVP_MULANX16PACKLT, + OPCODE_IVP_MULANX16PACKQT, + OPCODE_IVP_ADDSNX16T, + OPCODE_IVP_SUBSNX16T, + OPCODE_IVP_NEGSNX16T, + OPCODE_IVP_LALIGN_I, + OPCODE_IVP_LALIGN_IP, + OPCODE_IVP_SALIGN_I, + OPCODE_IVP_SALIGN_IP, + OPCODE_IVP_LA_PP, + OPCODE_IVP_SAPOS_FP, + OPCODE_IVP_MALIGN, + OPCODE_IVP_ZALIGN, + OPCODE_IVP_LA2NX8_IP, + OPCODE_IVP_SA2NX8_IP, + OPCODE_IVP_LAV2NX8_XP, + OPCODE_IVP_SAV2NX8_XP, + OPCODE_IVP_SELNX16, + OPCODE_IVP_SHFLNX16, + OPCODE_IVP_MOVPINT16, + OPCODE_IVP_MOVPA16, + OPCODE_IVP_MULNX16PACKP, + OPCODE_IVP_MULANX16PACKP, + OPCODE_IVP_MULSNX16PACKP, + OPCODE_IVP_MULANX16PACKPT, + OPCODE_IVP_ADDMOD16U, + OPCODE_IVP_LVNX8S_I, + OPCODE_IVP_LVNX8S_IP, + OPCODE_IVP_LVNX8S_X, + OPCODE_IVP_LVNX8S_XP, + OPCODE_IVP_LVNX8U_I, + OPCODE_IVP_LVNX8U_IP, + OPCODE_IVP_LVNX8U_X, + OPCODE_IVP_LVNX8U_XP, + OPCODE_IVP_SVNX8U_I, + OPCODE_IVP_SVNX8U_IP, + OPCODE_IVP_SVNX8U_X, + OPCODE_IVP_SVNX8U_XP, + OPCODE_IVP_LVNX8ST_I, + OPCODE_IVP_LVNX8ST_IP, + OPCODE_IVP_LVNX8ST_X, + OPCODE_IVP_LVNX8ST_XP, + OPCODE_IVP_LVNX8UT_I, + OPCODE_IVP_LVNX8UT_IP, + OPCODE_IVP_LVNX8UT_X, + OPCODE_IVP_LVNX8UT_XP, + OPCODE_IVP_SVNX8UT_I, + OPCODE_IVP_SVNX8UT_IP, + OPCODE_IVP_SVNX8UT_X, + OPCODE_IVP_SVNX8UT_XP, + OPCODE_IVP_LAVNX8S_XP, + OPCODE_IVP_LAVNX8U_XP, + OPCODE_IVP_SAVNX8U_XP, + OPCODE_IVP_LANX8S_IP, + OPCODE_IVP_LANX8U_IP, + OPCODE_IVP_SANX8U_IP, + OPCODE_IVP_EXTRACTBL, + OPCODE_IVP_EXTRACTBH, + OPCODE_IVP_MOVVINT16, + OPCODE_IVP_MOVQINT16, + OPCODE_IVP_MOVQA16, + OPCODE_IVP_MOVVINX16, + OPCODE_IVP_SEQNX16, + OPCODE_IVP_MULNX16PACKL, + OPCODE_IVP_MULNX16PACKQ, + OPCODE_IVP_MOVAV16, + OPCODE_IVP_MOVAVU16, + OPCODE_IVP_EXTRNX16, + OPCODE_IVP_LSNX8S_I, + OPCODE_IVP_LSNX8S_IP, + OPCODE_IVP_LSNX8S_X, + OPCODE_IVP_LSNX8S_XP, + OPCODE_IVP_SVNX8S_I, + OPCODE_IVP_SVNX8S_IP, + OPCODE_IVP_SVNX8S_X, + OPCODE_IVP_SVNX8S_XP, + OPCODE_IVP_SSNX8S_I, + OPCODE_IVP_SSNX8S_IP, + OPCODE_IVP_SSNX8S_X, + OPCODE_IVP_SSNX8S_XP, + OPCODE_IVP_SAVNX8S_XP, + OPCODE_IVP_SANX8S_IP, + OPCODE_IVP_SVNX8ST_I, + OPCODE_IVP_SVNX8ST_IP, + OPCODE_IVP_SVNX8ST_X, + OPCODE_IVP_SVNX8ST_XP, + OPCODE_IVP_MOVBA1, + OPCODE_IVP_MOVAB1, + OPCODE_IVP_NOTB1, + OPCODE_IVP_ANDNOTB1, + OPCODE_IVP_ORNOTB1, + OPCODE_IVP_CVT32S2NX24LL, + OPCODE_IVP_CVT32S2NX24LH, + OPCODE_IVP_CVT32S2NX24HL, + OPCODE_IVP_CVT32S2NX24HH, + OPCODE_IVP_CVT64SNX48LL, + OPCODE_IVP_CVT64SNX48LH, + OPCODE_IVP_CVT64SNX48HL, + OPCODE_IVP_CVT64SNX48HH, + OPCODE_IVP_CVT16S2NX24L, + OPCODE_IVP_CVT16S2NX24H, + OPCODE_IVP_CVT32SNX48L, + OPCODE_IVP_CVT32SNX48H, + OPCODE_IVP_CVT16U2NX24H, + OPCODE_IVP_CVT32UNX48H, + OPCODE_IVP_CVT64UN_2X96H, + OPCODE_IVP_CVT16U2NX24L, + OPCODE_IVP_CVT24U2NX16, + OPCODE_IVP_CVT24S2NX16, + OPCODE_IVP_CVT32S24, + OPCODE_IVP_CVT24U32, + OPCODE_IVP_CVT24UNX32L, + OPCODE_IVP_CVT24UNX32H, + OPCODE_IVP_CVT32UNX48L, + OPCODE_IVP_CVT48UNX32L, + OPCODE_IVP_CVT48UNX32, + OPCODE_IVP_CVT48SNX32L, + OPCODE_IVP_CVT48SNX32, + OPCODE_IVP_CVT64S48, + OPCODE_IVP_CVT48U64, + OPCODE_IVP_CVT48UN_2X64L, + OPCODE_IVP_CVT48UN_2X64H, + OPCODE_IVP_CVT64UN_2X96L, + OPCODE_IVP_CVT96UN_2X64, + OPCODE_IVP_CVT96U64, + OPCODE_IVP_CVT64U96, + OPCODE_IVP_LB2N_I, + OPCODE_IVP_LB2N_IP, + OPCODE_IVP_SB2N_I, + OPCODE_IVP_SB2N_IP, + OPCODE_IVP_LTR2N, + OPCODE_IVP_LTR2NI, + OPCODE_IVP_LVN_2X16U_I, + OPCODE_IVP_LVN_2X16U_IP, + OPCODE_IVP_LVN_2X16U_X, + OPCODE_IVP_LVN_2X16U_XP, + OPCODE_IVP_LVN_2X16UT_I, + OPCODE_IVP_LVN_2X16UT_IP, + OPCODE_IVP_LVN_2X16UT_X, + OPCODE_IVP_LVN_2X16UT_XP, + OPCODE_IVP_LVN_2X16S_I, + OPCODE_IVP_LVN_2X16S_IP, + OPCODE_IVP_LVN_2X16S_X, + OPCODE_IVP_LVN_2X16S_XP, + OPCODE_IVP_LVN_2X16ST_I, + OPCODE_IVP_LVN_2X16ST_IP, + OPCODE_IVP_LVN_2X16ST_X, + OPCODE_IVP_LVN_2X16ST_XP, + OPCODE_IVP_SVN_2X16U_I, + OPCODE_IVP_SVN_2X16UT_I, + OPCODE_IVP_SVN_2X16U_IP, + OPCODE_IVP_SVN_2X16UT_IP, + OPCODE_IVP_SVN_2X16U_X, + OPCODE_IVP_SVN_2X16UT_X, + OPCODE_IVP_SVN_2X16U_XP, + OPCODE_IVP_SVN_2X16UT_XP, + OPCODE_IVP_SVN_2X16S_I, + OPCODE_IVP_SVN_2X16ST_I, + OPCODE_IVP_SVN_2X16S_IP, + OPCODE_IVP_SVN_2X16ST_IP, + OPCODE_IVP_SVN_2X16S_X, + OPCODE_IVP_SVN_2X16ST_X, + OPCODE_IVP_SVN_2X16S_XP, + OPCODE_IVP_SVN_2X16ST_XP, + OPCODE_IVP_LAN_2X16S_IP, + OPCODE_IVP_LAN_2X16U_IP, + OPCODE_IVP_LAN_2X16U_XP, + OPCODE_IVP_LAN_2X16S_XP, + OPCODE_IVP_SAN_2X16U_IP, + OPCODE_IVP_SAN_2X16S_IP, + OPCODE_IVP_LAVN_2X16S_XP, + OPCODE_IVP_LAVN_2X16U_XP, + OPCODE_IVP_SAVN_2X16U_XP, + OPCODE_IVP_SAVN_2X16S_XP, + OPCODE_IVP_LSN_2X16S_I, + OPCODE_IVP_LSN_2X16S_IP, + OPCODE_IVP_LSN_2X16S_X, + OPCODE_IVP_LSN_2X16S_XP, + OPCODE_IVP_SSN_2X16S_I, + OPCODE_IVP_SSN_2X16S_IP, + OPCODE_IVP_SSN_2X16S_X, + OPCODE_IVP_SSN_2X16S_XP, + OPCODE_IVP_LSN_2X32_I, + OPCODE_IVP_LSN_2X32_IP, + OPCODE_IVP_LSN_2X32_X, + OPCODE_IVP_LSN_2X32_XP, + OPCODE_IVP_SSN_2X32_I, + OPCODE_IVP_SSN_2X32_IP, + OPCODE_IVP_SSN_2X32_X, + OPCODE_IVP_SSN_2X32_XP, + OPCODE_IVP_BMAXUNX16, + OPCODE_IVP_BMINUNX16, + OPCODE_IVP_RBMINUNX16, + OPCODE_IVP_RBMAXUNX16, + OPCODE_IVP_BMAX2NX8, + OPCODE_IVP_BMIN2NX8, + OPCODE_IVP_BMAXU2NX8, + OPCODE_IVP_BMINU2NX8, + OPCODE_IVP_BMAXN_2X32, + OPCODE_IVP_BMINN_2X32, + OPCODE_IVP_BMAXUN_2X32, + OPCODE_IVP_BMINUN_2X32, + OPCODE_IVP_ADDN_2X32T, + OPCODE_IVP_SUBN_2X32T, + OPCODE_IVP_ADD2NX8, + OPCODE_IVP_SUB2NX8, + OPCODE_IVP_NEG2NX8, + OPCODE_IVP_MIN2NX8, + OPCODE_IVP_MINU2NX8, + OPCODE_IVP_MAX2NX8, + OPCODE_IVP_MAXU2NX8, + OPCODE_IVP_LT2NX8, + OPCODE_IVP_LE2NX8, + OPCODE_IVP_EQ2NX8, + OPCODE_IVP_NEQ2NX8, + OPCODE_IVP_LTU2NX8, + OPCODE_IVP_LEU2NX8, + OPCODE_IVP_ADD2NX8T, + OPCODE_IVP_SUB2NX8T, + OPCODE_IVP_SELNX16T, + OPCODE_IVP_SELN_2X32, + OPCODE_IVP_SELN_2X32T, + OPCODE_IVP_SHFLN_2X32, + OPCODE_IVP_SLLIN_2X32, + OPCODE_IVP_SLSIN_2X32, + OPCODE_IVP_SRAIN_2X32, + OPCODE_IVP_SRLIN_2X32, + OPCODE_IVP_SLLN_2X32, + OPCODE_IVP_SRLN_2X32, + OPCODE_IVP_SLAN_2X32, + OPCODE_IVP_SRAN_2X32, + OPCODE_IVP_SLSN_2X32, + OPCODE_IVP_SRSN_2X32, + OPCODE_IVP_RADDN_2X32, + OPCODE_IVP_RMAXN_2X32, + OPCODE_IVP_RMINN_2X32, + OPCODE_IVP_RMAXUN_2X32, + OPCODE_IVP_RMINUN_2X32, + OPCODE_IVP_RADDN_2X32T, + OPCODE_IVP_ABS2NX8, + OPCODE_IVP_ABSN_2X32, + OPCODE_IVP_MULSGNSNX16, + OPCODE_IVP_ROTRI2NX8, + OPCODE_IVP_ROTRINX16, + OPCODE_IVP_ROTRIN_2X32, + OPCODE_IVP_ROTRNX16, + OPCODE_IVP_ROTRN_2X32, + OPCODE_IVP_ADDN_2X32, + OPCODE_IVP_SUBN_2X32, + OPCODE_IVP_NEGN_2X32, + OPCODE_IVP_MINN_2X32, + OPCODE_IVP_MINUN_2X32, + OPCODE_IVP_MAXN_2X32, + OPCODE_IVP_MAXUN_2X32, + OPCODE_IVP_MULSGNN_2X32, + OPCODE_IVP_NSAN_2X32, + OPCODE_IVP_NSAUN_2X32, + OPCODE_IVP_LTN_2X32, + OPCODE_IVP_LEN_2X32, + OPCODE_IVP_EQN_2X32, + OPCODE_IVP_NEQN_2X32, + OPCODE_IVP_LTUN_2X32, + OPCODE_IVP_LEUN_2X32, + OPCODE_IVP_LAT2NX8_XP, + OPCODE_IVP_MULUU2NX8, + OPCODE_IVP_MULUUA2NX8, + OPCODE_IVP_MULUS2NX8, + OPCODE_IVP_MULUSA2NX8, + OPCODE_IVP_MULI2NX8X16, + OPCODE_IVP_MULAI2NX8X16, + OPCODE_IVP_MULUSI2NX8X16, + OPCODE_IVP_MULUSAI2NX8X16, + OPCODE_IVP_MULI2NR8X16, + OPCODE_IVP_MULAI2NR8X16, + OPCODE_IVP_MULUSI2NR8X16, + OPCODE_IVP_MULUSAI2NR8X16, + OPCODE_IVP_MULUSA2N8XR16, + OPCODE_IVP_MULUS2N8XR16, + OPCODE_IVP_MULA2N8XR16, + OPCODE_IVP_MUL2N8XR16, + OPCODE_IVP_DSEL2NX8I, + OPCODE_IVP_DSEL2NX8I_H, + OPCODE_IVP_DSELNX16, + OPCODE_IVP_DSELNX16T, + OPCODE_IVP_INJBI2NX8, + OPCODE_IVP_EXTBI2NX8, + OPCODE_IVP_MOVVA32, + OPCODE_IVP_MOVAV32, + OPCODE_IVP_MOVWW, + OPCODE_IVP_LS2NX8_I, + OPCODE_IVP_LS2NX8_IP, + OPCODE_IVP_LS2NX8_X, + OPCODE_IVP_LS2NX8_XP, + OPCODE_IVP_SS2NX8_I, + OPCODE_IVP_SS2NX8_IP, + OPCODE_IVP_SS2NX8_X, + OPCODE_IVP_SS2NX8_XP, + OPCODE_IVP_LANX8S_XP, + OPCODE_IVP_LANX8U_XP, + OPCODE_IVP_LA2NX8_XP, + OPCODE_IVP_ABSSUBU2NX8, + OPCODE_IVP_ABSSUB2NX8, + OPCODE_IVP_MOVVINT8, + OPCODE_IVP_MOVVA8, + OPCODE_IVP_MOVAVU8, + OPCODE_IVP_SLLI2NX8, + OPCODE_IVP_SRAI2NX8, + OPCODE_IVP_SRLI2NX8, + OPCODE_IVP_PACKL2NX24, + OPCODE_IVP_PACKVR2NX24, + OPCODE_IVP_PACKVRU2NX24, + OPCODE_IVP_PACKLNX48, + OPCODE_IVP_PACKL2NX24_1, + OPCODE_IVP_PACKVR2NX24_0, + OPCODE_IVP_PACKVR2NX24_1, + OPCODE_IVP_PACKVRU2NX24_0, + OPCODE_IVP_PACKVRU2NX24_1, + OPCODE_IVP_PACKVRNR2NX24_0, + OPCODE_IVP_PACKVRNR2NX24_1, + OPCODE_IVP_PACKMNX48, + OPCODE_IVP_PACKVRNX48, + OPCODE_IVP_UNPKS2NX8_0, + OPCODE_IVP_UNPKS2NX8_1, + OPCODE_IVP_UNPKSNX16_L, + OPCODE_IVP_UNPKSNX16_H, + OPCODE_IVP_SEL2NX8I, + OPCODE_IVP_SEL2NX8I_S0, + OPCODE_IVP_SEL2NX8I_S2, + OPCODE_IVP_SEL2NX8I_S4, + OPCODE_IVP_SHFL2NX8I, + OPCODE_IVP_SHFL2NX8I_S0, + OPCODE_IVP_SHFL2NX8I_S2, + OPCODE_IVP_SHFL2NX8I_S4, + OPCODE_IVP_SEL2NX8, + OPCODE_IVP_SHFL2NX8, + OPCODE_IVP_SEL2NX8T, + OPCODE_IVP_SQZN, + OPCODE_IVP_UNSQZN, + OPCODE_IVP_MULNX16, + OPCODE_IVP_MULANX16, + OPCODE_IVP_MULUUNX16, + OPCODE_IVP_MULUUANX16, + OPCODE_IVP_MULUSNX16, + OPCODE_IVP_MULUSANX16, + OPCODE_IVP_MUL2NX8, + OPCODE_IVP_MULA2NX8, + OPCODE_IVP_ADDW2NX8, + OPCODE_IVP_ADDWA2NX8, + OPCODE_IVP_ADDWS2NX8, + OPCODE_IVP_ADDWU2NX8, + OPCODE_IVP_ADDWUA2NX8, + OPCODE_IVP_ADDWUS2NX8, + OPCODE_IVP_DIVN_2X32X16S_4STEP0, + OPCODE_IVP_DIVN_2X32X16S_4STEP, + OPCODE_IVP_DIVN_2X32X16S_4STEPN, + OPCODE_IVP_DIVN_2X32X16U_4STEP0, + OPCODE_IVP_DIVN_2X32X16U_4STEP, + OPCODE_IVP_DIVN_2X32X16U_4STEPN, + OPCODE_IVP_DIVNX16S_4STEP0, + OPCODE_IVP_DIVNX16S_4STEP, + OPCODE_IVP_DIVNX16S_4STEPN, + OPCODE_IVP_DIVNX16U_4STEP0, + OPCODE_IVP_DIVNX16U_4STEP, + OPCODE_IVP_DIVNX16U_4STEPN, + OPCODE_IVP_DIVNX16SQ_4STEP0, + OPCODE_IVP_DIVNX16Q_4STEP0, + OPCODE_IVP_MULSNX16, + OPCODE_IVP_MULUUSNX16, + OPCODE_IVP_MULUSSNX16, + OPCODE_IVP_MULN_2X16X32_0, + OPCODE_IVP_MULUUN_2X16X32_0, + OPCODE_IVP_MULUSN_2X16X32_0, + OPCODE_IVP_MULSUN_2X16X32_0, + OPCODE_IVP_MULN_2X16X32_1, + OPCODE_IVP_MULUUN_2X16X32_1, + OPCODE_IVP_MULUSN_2X16X32_1, + OPCODE_IVP_MULSUN_2X16X32_1, + OPCODE_IVP_MULHN_2X16X32_1, + OPCODE_IVP_MULUUHN_2X16X32_1, + OPCODE_IVP_MULUSHN_2X16X32_1, + OPCODE_IVP_MULSUHN_2X16X32_1, + OPCODE_IVP_MULAN_2X16X32_0, + OPCODE_IVP_MULUUAN_2X16X32_0, + OPCODE_IVP_MULUSAN_2X16X32_0, + OPCODE_IVP_MULSUAN_2X16X32_0, + OPCODE_IVP_MULAHN_2X16X32_1, + OPCODE_IVP_MULUUAHN_2X16X32_1, + OPCODE_IVP_MULUSAHN_2X16X32_1, + OPCODE_IVP_MULSUAHN_2X16X32_1, + OPCODE_IVP_MULAN_2X16X32_1, + OPCODE_IVP_MULUUAN_2X16X32_1, + OPCODE_IVP_MULUSAN_2X16X32_1, + OPCODE_IVP_MULSUAN_2X16X32_1, + OPCODE_IVP_MULSHN_2X16X32_1, + OPCODE_IVP_MULUUSHN_2X16X32_1, + OPCODE_IVP_MULUSSHN_2X16X32_1, + OPCODE_IVP_MULSUSHN_2X16X32_1, + OPCODE_IVP_MULSN_2X16X32_0, + OPCODE_IVP_MULUUSN_2X16X32_0, + OPCODE_IVP_MULUSSN_2X16X32_0, + OPCODE_IVP_MULSUSN_2X16X32_0, + OPCODE_IVP_MULSN_2X16X32_1, + OPCODE_IVP_MULUUSN_2X16X32_1, + OPCODE_IVP_MULUSSN_2X16X32_1, + OPCODE_IVP_MULSUSN_2X16X32_1, + OPCODE_IVP_PACKLN_2X96, + OPCODE_IVP_PACKHN_2X64W, + OPCODE_IVP_PACKVRN_2X64W, + OPCODE_IVP_PACKVRNRN_2X64W, + OPCODE_IVP_PACKVRNX48_0, + OPCODE_IVP_PACKVRNX48_1, + OPCODE_IVP_PACKVRNRNX48_0, + OPCODE_IVP_PACKVRNRNX48_1, + OPCODE_IVP_PACKVRNRNX48, + OPCODE_IVP_PACKVRNR2NX24, + OPCODE_IVP_L2A4NX8_IP, + OPCODE_IVP_L2AU2NX8_IP, + OPCODE_IVP_L2U2NX8_XP, + OPCODE_IVP_AVGU2NX8, + OPCODE_IVP_AVGRU2NX8, + OPCODE_IVP_RADD2NX8, + OPCODE_IVP_RADD2NX8T, + OPCODE_IVP_RADDUNX16, + OPCODE_IVP_RADDUNX16T, + OPCODE_IVP_RADDU2NX8, + OPCODE_IVP_RADDU2NX8T, + OPCODE_IVP_LTRS2N, + OPCODE_IVP_LTRSN, + OPCODE_IVP_LTRSN_2, + OPCODE_IVP_SEQ2NX8, + OPCODE_IVP_SEQN_2X32, + OPCODE_IVP_EXTRN_2X32, + OPCODE_IVP_UNPKU2NX8_0, + OPCODE_IVP_UNPKU2NX8_1, + OPCODE_IVP_BADDNORMNX16, + OPCODE_IVP_BSUBNORMNX16, + OPCODE_IVP_RADDSNX16, + OPCODE_IVP_RADDSNX16T, + OPCODE_IVP_ORNOTB, + OPCODE_IVP_EXTR2NX8, + OPCODE_IVP_EXTRVRN_2X32, + OPCODE_IVP_MOVAV8, + OPCODE_IVP_MULPN16XR16, + OPCODE_IVP_MULPAN16XR16, + OPCODE_IVP_MULUSPN16XR16, + OPCODE_IVP_MULUSPAN16XR16, + OPCODE_IVP_MULP2N8XR16, + OPCODE_IVP_MULPA2N8XR16, + OPCODE_IVP_MULUSP2N8XR16, + OPCODE_IVP_MULUSPA2N8XR16, + OPCODE_IVP_MULPNX16, + OPCODE_IVP_MULPANX16, + OPCODE_IVP_MULUSPNX16, + OPCODE_IVP_MULUSPANX16, + OPCODE_IVP_MULUUPNX16, + OPCODE_IVP_MULUUPANX16, + OPCODE_IVP_MULP2NX8, + OPCODE_IVP_MULPA2NX8, + OPCODE_IVP_MULUSP2NX8, + OPCODE_IVP_MULUSPA2NX8, + OPCODE_IVP_MULUUP2NX8, + OPCODE_IVP_MULUUPA2NX8, + OPCODE_IVP_MULPI2NR8X16, + OPCODE_IVP_MULPAI2NR8X16, + OPCODE_IVP_MULUSPI2NR8X16, + OPCODE_IVP_MULUSPAI2NR8X16, + OPCODE_IVP_MULQ2N8XR8, + OPCODE_IVP_MULQA2N8XR8, + OPCODE_IVP_MULUSQ2N8XR8, + OPCODE_IVP_MULUSQA2N8XR8, + OPCODE_IVP_MUL4T2N8XR8, + OPCODE_IVP_MUL4TA2N8XR8, + OPCODE_IVP_MULUS4T2N8XR8, + OPCODE_IVP_MULUS4TA2N8XR8, + OPCODE_IVP_ADDWNX16, + OPCODE_IVP_ADDWANX16, + OPCODE_IVP_ADDWSNX16, + OPCODE_IVP_ADDWUNX16, + OPCODE_IVP_ADDWUANX16, + OPCODE_IVP_ADDWUSNX16, + OPCODE_IVP_SUBWNX16, + OPCODE_IVP_SUBWANX16, + OPCODE_IVP_SUBWUNX16, + OPCODE_IVP_SUBWUANX16, + OPCODE_IVP_SUBW2NX8, + OPCODE_IVP_SUBWA2NX8, + OPCODE_IVP_SUBWU2NX8, + OPCODE_IVP_SUBWUA2NX8, + OPCODE_IVP_RANDB2N, + OPCODE_IVP_RORB2N, + OPCODE_IVP_RANDBN, + OPCODE_IVP_RORBN, + OPCODE_IVP_RANDBN_2, + OPCODE_IVP_RORBN_2, + OPCODE_IVP_AVGNX16, + OPCODE_IVP_AVGUNX16, + OPCODE_IVP_AVG2NX8, + OPCODE_IVP_AVGR2NX8, + OPCODE_IVP_AVGRNX16, + OPCODE_IVP_AVGRUNX16, + OPCODE_IVP_GATHERANX8U, + OPCODE_IVP_GATHERANX16, + OPCODE_IVP_GATHERAN_2X32, + OPCODE_IVP_GATHERANX8UT, + OPCODE_IVP_GATHERANX16T, + OPCODE_IVP_GATHERAN_2X32T, + OPCODE_IVP_GATHERDNX16, + OPCODE_IVP_GATHERDNX8S, + OPCODE_IVP_GATHERD2NX8_L, + OPCODE_IVP_GATHERD2NX8_H, + OPCODE_IVP_MOVGATHERD, + OPCODE_IVP_SCATTERNX8U, + OPCODE_IVP_SCATTER2NX8_L, + OPCODE_IVP_SCATTER2NX8_H, + OPCODE_IVP_SCATTERNX16, + OPCODE_IVP_SCATTERN_2X32, + OPCODE_IVP_SCATTERNX8UT, + OPCODE_IVP_SCATTER2NX8T_L, + OPCODE_IVP_SCATTER2NX8T_H, + OPCODE_IVP_SCATTERNX16T, + OPCODE_IVP_SCATTERN_2X32T, + OPCODE_IVP_SCATTERW, + OPCODE_IVP_COUNTEQZ4NX8, + OPCODE_IVP_COUNTEQ4NX8, + OPCODE_IVP_COUNTEQMZ4NX8, + OPCODE_IVP_COUNTEQM4NX8, + OPCODE_IVP_COUNTLEZ4NX8, + OPCODE_IVP_COUNTLE4NX8, + OPCODE_IVP_COUNTLEMZ4NX8, + OPCODE_IVP_COUNTLEM4NX8, + OPCODE_IVP_LSR2NX8_I, + OPCODE_IVP_LSR2NX8_IP, + OPCODE_IVP_LSR2NX8_X, + OPCODE_IVP_LSR2NX8_XP, + OPCODE_IVP_LSRNX16_I, + OPCODE_IVP_LSRNX16_IP, + OPCODE_IVP_LSRNX16_X, + OPCODE_IVP_LSRNX16_XP, + OPCODE_IVP_LSRN_2X32_I, + OPCODE_IVP_LSRN_2X32_IP, + OPCODE_IVP_LSRN_2X32_X, + OPCODE_IVP_LSRN_2X32_XP, + OPCODE_IVP_ABSNX16, + OPCODE_IVP_ABSSNX16, + OPCODE_IVP_ABSSUBNX16, + OPCODE_IVP_ABSSUBUNX16, + OPCODE_IVP_ABSSSUBNX16, + OPCODE_EXCW, + OPCODE_RFE, + OPCODE_RFDE, + OPCODE_SYSCALL, + OPCODE_CALL12, + OPCODE_CALL8, + OPCODE_CALL4, + OPCODE_CALLX12, + OPCODE_CALLX8, + OPCODE_CALLX4, + OPCODE_ENTRY, + OPCODE_MOVSP, + OPCODE_ROTW, + OPCODE_RETW, + OPCODE_RETW_N, + OPCODE_RFWO, + OPCODE_RFWU, + OPCODE_L32E, + OPCODE_S32E, + OPCODE_RSR_WINDOWBASE, + OPCODE_WSR_WINDOWBASE, + OPCODE_XSR_WINDOWBASE, + OPCODE_RSR_WINDOWSTART, + OPCODE_WSR_WINDOWSTART, + OPCODE_XSR_WINDOWSTART, + OPCODE_ADD_N, + OPCODE_ADDI_N, + OPCODE_BEQZ_N, + OPCODE_BNEZ_N, + OPCODE_ILL_N, + OPCODE_L32I_N, + OPCODE_MOV_N, + OPCODE_MOVI_N, + OPCODE_NOP_N, + OPCODE_RET_N, + OPCODE_S32I_N, + OPCODE_RUR_THREADPTR, + OPCODE_WUR_THREADPTR, + OPCODE_ADDI, + OPCODE_ADDMI, + OPCODE_ADD, + OPCODE_SUB, + OPCODE_ADDX2, + OPCODE_ADDX4, + OPCODE_ADDX8, + OPCODE_SUBX2, + OPCODE_SUBX4, + OPCODE_SUBX8, + OPCODE_AND, + OPCODE_OR, + OPCODE_XOR, + OPCODE_BEQI, + OPCODE_BNEI, + OPCODE_BGEI, + OPCODE_BLTI, + OPCODE_BBCI, + OPCODE_BBSI, + OPCODE_BGEUI, + OPCODE_BLTUI, + OPCODE_BEQ, + OPCODE_BNE, + OPCODE_BGE, + OPCODE_BLT, + OPCODE_BGEU, + OPCODE_BLTU, + OPCODE_BANY, + OPCODE_BNONE, + OPCODE_BALL, + OPCODE_BNALL, + OPCODE_BBC, + OPCODE_BBS, + OPCODE_BEQZ, + OPCODE_BNEZ, + OPCODE_BGEZ, + OPCODE_BLTZ, + OPCODE_CALL0, + OPCODE_CALLX0, + OPCODE_CONST16, + OPCODE_EXTUI, + OPCODE_ILL, + OPCODE_J, + OPCODE_JX, + OPCODE_L16UI, + OPCODE_L16SI, + OPCODE_L32I, + OPCODE_L32R, + OPCODE_L8UI, + OPCODE_LOOP, + OPCODE_LOOPNEZ, + OPCODE_LOOPGTZ, + OPCODE_MOVI, + OPCODE_MOVEQZ, + OPCODE_MOVNEZ, + OPCODE_MOVLTZ, + OPCODE_MOVGEZ, + OPCODE_NEG, + OPCODE_ABS, + OPCODE_NOP, + OPCODE_L32EX, + OPCODE_S32EX, + OPCODE_GETEX, + OPCODE_CLREX, + OPCODE_RET, + OPCODE_SIMCALL, + OPCODE_S16I, + OPCODE_S32I, + OPCODE_S32NB, + OPCODE_S8I, + OPCODE_SSR, + OPCODE_SSL, + OPCODE_SSA8L, + OPCODE_SSA8B, + OPCODE_SSAI, + OPCODE_SLL, + OPCODE_SRC, + OPCODE_SRL, + OPCODE_SRA, + OPCODE_SLLI, + OPCODE_SRAI, + OPCODE_SRLI, + OPCODE_MEMW, + OPCODE_EXTW, + OPCODE_ISYNC, + OPCODE_RSYNC, + OPCODE_ESYNC, + OPCODE_DSYNC, + OPCODE_RSIL, + OPCODE_RSR_LEND, + OPCODE_WSR_LEND, + OPCODE_XSR_LEND, + OPCODE_RSR_LCOUNT, + OPCODE_WSR_LCOUNT, + OPCODE_XSR_LCOUNT, + OPCODE_RSR_LBEG, + OPCODE_WSR_LBEG, + OPCODE_XSR_LBEG, + OPCODE_RSR_SAR, + OPCODE_WSR_SAR, + OPCODE_XSR_SAR, + OPCODE_RSR_MEMCTL, + OPCODE_WSR_MEMCTL, + OPCODE_XSR_MEMCTL, + OPCODE_RSR_LITBASE, + OPCODE_WSR_LITBASE, + OPCODE_XSR_LITBASE, + OPCODE_RSR_CONFIGID0, + OPCODE_WSR_CONFIGID0, + OPCODE_RSR_CONFIGID1, + OPCODE_RSR_PS, + OPCODE_WSR_PS, + OPCODE_XSR_PS, + OPCODE_RSR_EPC1, + OPCODE_WSR_EPC1, + OPCODE_XSR_EPC1, + OPCODE_RSR_EXCSAVE1, + OPCODE_WSR_EXCSAVE1, + OPCODE_XSR_EXCSAVE1, + OPCODE_RSR_EPC2, + OPCODE_WSR_EPC2, + OPCODE_XSR_EPC2, + OPCODE_RSR_EXCSAVE2, + OPCODE_WSR_EXCSAVE2, + OPCODE_XSR_EXCSAVE2, + OPCODE_RSR_EPC3, + OPCODE_WSR_EPC3, + OPCODE_XSR_EPC3, + OPCODE_RSR_EXCSAVE3, + OPCODE_WSR_EXCSAVE3, + OPCODE_XSR_EXCSAVE3, + OPCODE_RSR_EPC4, + OPCODE_WSR_EPC4, + OPCODE_XSR_EPC4, + OPCODE_RSR_EXCSAVE4, + OPCODE_WSR_EXCSAVE4, + OPCODE_XSR_EXCSAVE4, + OPCODE_RSR_EPS2, + OPCODE_WSR_EPS2, + OPCODE_XSR_EPS2, + OPCODE_RSR_EPS3, + OPCODE_WSR_EPS3, + OPCODE_XSR_EPS3, + OPCODE_RSR_EPS4, + OPCODE_WSR_EPS4, + OPCODE_XSR_EPS4, + OPCODE_RSR_EXCVADDR, + OPCODE_WSR_EXCVADDR, + OPCODE_XSR_EXCVADDR, + OPCODE_RSR_DEPC, + OPCODE_WSR_DEPC, + OPCODE_XSR_DEPC, + OPCODE_RSR_EXCCAUSE, + OPCODE_WSR_EXCCAUSE, + OPCODE_XSR_EXCCAUSE, + OPCODE_RSR_PRID, + OPCODE_RSR_VECBASE, + OPCODE_WSR_VECBASE, + OPCODE_XSR_VECBASE, + OPCODE_RSR_MPUCFG, + OPCODE_WSR_MPUCFG, + OPCODE_RSR_GSERR, + OPCODE_WSR_GSERR, + OPCODE_XSR_GSERR, + OPCODE_SALT, + OPCODE_SALTU, + OPCODE_MUL16U, + OPCODE_MUL16S, + OPCODE_MULL, + OPCODE_MULUH, + OPCODE_MULSH, + OPCODE_RFI, + OPCODE_WAITI, + OPCODE_RSR_INTERRUPT, + OPCODE_WSR_INTSET, + OPCODE_WSR_INTCLEAR, + OPCODE_RSR_INTENABLE, + OPCODE_WSR_INTENABLE, + OPCODE_XSR_INTENABLE, + OPCODE_BREAK, + OPCODE_BREAK_N, + OPCODE_RSR_DBREAKA0, + OPCODE_WSR_DBREAKA0, + OPCODE_XSR_DBREAKA0, + OPCODE_RSR_DBREAKC0, + OPCODE_WSR_DBREAKC0, + OPCODE_XSR_DBREAKC0, + OPCODE_RSR_IBREAKA0, + OPCODE_WSR_IBREAKA0, + OPCODE_XSR_IBREAKA0, + OPCODE_RSR_IBREAKENABLE, + OPCODE_WSR_IBREAKENABLE, + OPCODE_XSR_IBREAKENABLE, + OPCODE_RSR_DEBUGCAUSE, + OPCODE_WSR_DEBUGCAUSE, + OPCODE_XSR_DEBUGCAUSE, + OPCODE_RSR_ICOUNT, + OPCODE_WSR_ICOUNT, + OPCODE_XSR_ICOUNT, + OPCODE_RSR_ICOUNTLEVEL, + OPCODE_WSR_ICOUNTLEVEL, + OPCODE_XSR_ICOUNTLEVEL, + OPCODE_RSR_DDR, + OPCODE_WSR_DDR, + OPCODE_XSR_DDR, + OPCODE_LDDR32_P, + OPCODE_SDDR32_P, + OPCODE_RFDO, + OPCODE_RFDD, + OPCODE_WSR_MMID, + OPCODE_ANDB, + OPCODE_ANDBC, + OPCODE_ORB, + OPCODE_ORBC, + OPCODE_XORB, + OPCODE_ANY4, + OPCODE_ALL4, + OPCODE_ANY8, + OPCODE_ALL8, + OPCODE_BF, + OPCODE_BT, + OPCODE_MOVF, + OPCODE_MOVT, + OPCODE_RSR_BR, + OPCODE_WSR_BR, + OPCODE_XSR_BR, + OPCODE_RSR_CCOUNT, + OPCODE_WSR_CCOUNT, + OPCODE_XSR_CCOUNT, + OPCODE_RSR_CCOMPARE0, + OPCODE_WSR_CCOMPARE0, + OPCODE_XSR_CCOMPARE0, + OPCODE_RSR_CCOMPARE1, + OPCODE_WSR_CCOMPARE1, + OPCODE_XSR_CCOMPARE1, + OPCODE_IPF, + OPCODE_IHI, + OPCODE_IPFL, + OPCODE_IHU, + OPCODE_IIU, + OPCODE_III, + OPCODE_LICT, + OPCODE_LICW, + OPCODE_SICT, + OPCODE_SICW, + OPCODE_WSR_CACHEADRDIS, + OPCODE_RSR_CACHEADRDIS, + OPCODE_XSR_CACHEADRDIS, + OPCODE_RPTLB0, + OPCODE_PPTLB, + OPCODE_RPTLB1, + OPCODE_WPTLB, + OPCODE_RSR_MPUENB, + OPCODE_WSR_MPUENB, + OPCODE_XSR_MPUENB, + OPCODE_RSR_CPENABLE, + OPCODE_WSR_CPENABLE, + OPCODE_XSR_CPENABLE, + OPCODE_CLAMPS, + OPCODE_MIN, + OPCODE_MAX, + OPCODE_MINU, + OPCODE_MAXU, + OPCODE_NSA, + OPCODE_NSAU, + OPCODE_SEXT, + OPCODE_L32AI, + OPCODE_S32RI, + OPCODE_RSR_ATOMCTL, + OPCODE_WSR_ATOMCTL, + OPCODE_XSR_ATOMCTL, + OPCODE_QUOU, + OPCODE_QUOS, + OPCODE_REMU, + OPCODE_REMS, + OPCODE_RSR_ERACCESS, + OPCODE_WSR_ERACCESS, + OPCODE_XSR_ERACCESS, + OPCODE_RER, + OPCODE_WER, + OPCODE_BEQZ_W15, + OPCODE_BNEZ_W15, + OPCODE_BGEZ_W15, + OPCODE_BLTZ_W15, + OPCODE_BEQI_W15, + OPCODE_BNEI_W15, + OPCODE_BGEI_W15, + OPCODE_BLTI_W15, + OPCODE_BGEUI_W15, + OPCODE_BLTUI_W15, + OPCODE_BBCI_W15, + OPCODE_BBSI_W15, + OPCODE_BEQ_W15, + OPCODE_BNE_W15, + OPCODE_BGE_W15, + OPCODE_BLT_W15, + OPCODE_BGEU_W15, + OPCODE_BLTU_W15, + OPCODE_BANY_W15, + OPCODE_BNONE_W15, + OPCODE_BALL_W15, + OPCODE_BNALL_W15, + OPCODE_BBC_W15, + OPCODE_BBS_W15, + OPCODE_MTK_AndPOPC, + OPCODE_iq_tie2apb_inq0_pop, + OPCODE_iq_tie2apb_inq0_is_ready, + OPCODE_iq_tie2apb_inq0_nonblocking_peek, + OPCODE_iq_tie2apb_inq0_nonblocking_pop, + OPCODE_iq_tie2apb_inq0_blocking_peek, + OPCODE_oq_tie2apb_outq0_push_read, + OPCODE_oq_tie2apb_outq0_push_write, + OPCODE_oq_tie2apb_outq0_is_ready, + OPCODE_oq_tie2apb_outq0_nonblocking_push_read, + OPCODE_oq_tie2apb_outq0_nonblocking_push_write, + OPCODE_RUR_APB_PIPE, + OPCODE_WUR_APB_PIPE +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_f0_s0_ldst_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f0_s0_ldst_33_11_Slot_f0_s0_ldst_get (insn) == 135587) + return OPCODE_IVP_GATHERANX16; + if (Field_fld_f0_s0_ldst_33_11_Slot_f0_s0_ldst_get (insn) == 135591) + return OPCODE_IVP_GATHERANX8U; + if (Field_fld_f0_s0_ldst_33_11_Slot_f0_s0_ldst_get (insn) == 135595) + return OPCODE_IVP_GATHERAN_2X32; + if (Field_fld_f0_s0_ldst_33_11_Slot_f0_s0_ldst_get (insn) == 136300 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 5) + return OPCODE_IVP_MOVGATHERD; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68046) + return OPCODE_ADD; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68047) + return OPCODE_ADDX2; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68050) + return OPCODE_MAXU; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68051) + return OPCODE_MIN; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68054) + return OPCODE_MINU; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68055) + return OPCODE_MOVEQZ; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68058) + return OPCODE_MOVGEZ; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68059) + return OPCODE_MOVLTZ; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68062) + return OPCODE_MOVNEZ; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68063) + return OPCODE_MUL16S; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68116) + return OPCODE_ADDX4; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68117) + return OPCODE_AND; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68118) + return OPCODE_ADDX8; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68119) + return OPCODE_MAX; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68120) + return OPCODE_MUL16U; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68121) + return OPCODE_MULSH; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68122) + return OPCODE_MULL; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68123) + return OPCODE_MULUH; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68124) + return OPCODE_OR; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68125) + return OPCODE_SALTU; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68126) + return OPCODE_SALT; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68127) + return OPCODE_SRC; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68129) + return OPCODE_SUB; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68131) + return OPCODE_SUBX2; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68133) + return OPCODE_SUBX4; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68135) + return OPCODE_SUBX8; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68137) + return OPCODE_XOR; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68139) + return OPCODE_CLAMPS; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68141) + return OPCODE_SEXT; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68143) + return OPCODE_SRLI; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68148 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 5) + return OPCODE_SLL; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68152 && + Field_fld_f0_s0_ldst_3_0_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68152 && + Field_fld_f0_s0_ldst_3_0_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68152 && + Field_fld_f0_s0_ldst_3_0_Slot_f0_s0_ldst_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68152 && + Field_fld_f0_s0_ldst_3_0_Slot_f0_s0_ldst_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33892) + return OPCODE_IVP_LS2NX8_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33893) + return OPCODE_IVP_LS2NX8_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33894) + return OPCODE_IVP_LSNX16_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33895) + return OPCODE_IVP_LSNX16_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33904) + return OPCODE_IVP_LSNX8S_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33905) + return OPCODE_IVP_LSNX8S_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33906) + return OPCODE_IVP_LSN_2X16S_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33907) + return OPCODE_IVP_LSN_2X16S_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33908) + return OPCODE_IVP_LSN_2X32_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33909) + return OPCODE_IVP_LSN_2X32_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33910) + return OPCODE_IVP_LSR2NX8_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33911) + return OPCODE_IVP_LSR2NX8_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33912) + return OPCODE_IVP_LSRNX16_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33913) + return OPCODE_IVP_LSRNX16_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33914) + return OPCODE_IVP_LSRN_2X32_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33915) + return OPCODE_IVP_LSRN_2X32_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33916) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33917) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33918) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33919) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33921) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33923) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33925) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33927) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33929) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33931) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33933) + return OPCODE_IVP_SS2NX8_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33935) + return OPCODE_IVP_SS2NX8_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33937) + return OPCODE_IVP_SSNX16_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33939) + return OPCODE_IVP_SSNX16_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33941) + return OPCODE_IVP_SSNX8S_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33943) + return OPCODE_IVP_SSNX8S_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33945) + return OPCODE_IVP_SSN_2X16S_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33947) + return OPCODE_IVP_SSN_2X16S_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33949) + return OPCODE_IVP_SSN_2X32_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33951) + return OPCODE_IVP_SSN_2X32_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33953) + return OPCODE_IVP_SV2NX8_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33955) + return OPCODE_IVP_SV2NX8_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33957) + return OPCODE_IVP_SVNX8S_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33959) + return OPCODE_IVP_SVNX8S_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33961) + return OPCODE_IVP_SVNX8U_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33963) + return OPCODE_IVP_SVNX8U_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33965) + return OPCODE_IVP_SVN_2X16S_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33967) + return OPCODE_IVP_SVN_2X16S_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33969) + return OPCODE_IVP_SVN_2X16U_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33971) + return OPCODE_IVP_SVN_2X16U_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33973) + return OPCODE_SLLI; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33975) + return OPCODE_IVP_LS2NX8_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33977) + return OPCODE_IVP_LSNX16_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33979) + return OPCODE_IVP_LSNX8S_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33981) + return OPCODE_IVP_LSN_2X16S_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33983) + return OPCODE_IVP_LSN_2X32_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33985) + return OPCODE_IVP_LSR2NX8_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33987) + return OPCODE_IVP_LSRNX16_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33989) + return OPCODE_IVP_LSRN_2X32_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33991) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33993) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33995) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33997) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33999) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34001) + return OPCODE_IVP_SS2NX8_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34003) + return OPCODE_IVP_SSNX16_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34005) + return OPCODE_IVP_SSNX8S_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34007) + return OPCODE_IVP_SSN_2X16S_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34009) + return OPCODE_IVP_SSN_2X32_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34011) + return OPCODE_IVP_SV2NX8_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34013) + return OPCODE_IVP_SVNX8S_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34015) + return OPCODE_IVP_SVNX8U_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34017) + return OPCODE_IVP_SVN_2X16S_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34019) + return OPCODE_IVP_SVN_2X16U_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34021) + return OPCODE_SRAI; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 16944) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 16945) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17025 && + Field_fld_f0_s0_ldst_7_7_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17026 && + Field_fld_f0_s0_ldst_7_7_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17028 && + Field_fld_f0_s0_ldst_7_7_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17028 && + Field_fld_f0_s0_ldst_7_7_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17036 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 10) + return OPCODE_IVP_MOVVV; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17036 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 12) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17036 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 11) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17036 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 4) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17036 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17036 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 14) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17036 && + Field_fld_f0_s0_ldst_7_5_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_SHFL2NX8I_S0; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17036 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 5) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17036 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 9) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17037 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17037 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4214 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4215 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4216 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4217 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4218 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4219 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SA2NX8_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4220 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SANX8S_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4221 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SANX8U_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4222 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SAN_2X16S_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4223 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SAN_2X16U_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8444) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8445) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8446) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8447) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8448) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8449) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8450) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8451) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8452) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8453) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8454) + return OPCODE_IVP_SAV2NX8_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8455) + return OPCODE_IVP_SAVNX8S_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8456) + return OPCODE_IVP_SAVNX8U_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8457) + return OPCODE_IVP_SAVN_2X16S_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8458) + return OPCODE_IVP_SAVN_2X16U_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8459) + return OPCODE_IVP_LS2NX8_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8460) + return OPCODE_IVP_LSNX16_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8461) + return OPCODE_IVP_LSNX8S_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8462) + return OPCODE_IVP_LSN_2X16S_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8463) + return OPCODE_IVP_LSR2NX8_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8464) + return OPCODE_IVP_LSRNX16_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8465) + return OPCODE_IVP_LSRN_2X32_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8466) + return OPCODE_IVP_SS2NX8_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8467) + return OPCODE_IVP_SSNX16_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8468) + return OPCODE_IVP_SSNX8S_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8469) + return OPCODE_IVP_SSN_2X16S_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8516 && + Field_fld_f0_s0_ldst_12_4_Slot_f0_s0_ldst_get (insn) == 15) + return OPCODE_IVP_LA_PP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8516 && + Field_fld_f0_s0_ldst_12_4_Slot_f0_s0_ldst_get (insn) == 31) + return OPCODE_IVP_SAPOS_FP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8516 && + Field_fld_f0_s0_ldst_12_2_Slot_f0_s0_ldst_get (insn) == 188) + return OPCODE_IVP_MALIGN; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8516 && + Field_fld_f0_s0_ldst_12_0_Slot_f0_s0_ldst_get (insn) == 756) + return OPCODE_IVP_ZALIGN; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8520 && + Field_fld_f0_s0_ldst_12_8_Slot_f0_s0_ldst_get (insn) == 2) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8520 && + Field_fld_f0_s0_ldst_12_8_Slot_f0_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SALIGN_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 2104 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_LOOP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 2105 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_LOOPGTZ; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 2106 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_LOOPNEZ; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4182) + return OPCODE_ADDI; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4183) + return OPCODE_ADDMI; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4184) + return OPCODE_IVP_LV2NX8T_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4185) + return OPCODE_IVP_LV2NX8T_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4186) + return OPCODE_IVP_LVNX8ST_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4187) + return OPCODE_IVP_LVNX8ST_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4188) + return OPCODE_IVP_LVNX8UT_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4189) + return OPCODE_IVP_LVNX8UT_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4190) + return OPCODE_IVP_LVN_2X16ST_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4191) + return OPCODE_IVP_LVN_2X16ST_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4192) + return OPCODE_IVP_LVN_2X16UT_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4193) + return OPCODE_IVP_LVN_2X16UT_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4194) + return OPCODE_IVP_SV2NX8T_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4195) + return OPCODE_IVP_SV2NX8T_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4196) + return OPCODE_IVP_SVNX8ST_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4197) + return OPCODE_IVP_SVNX8ST_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4198) + return OPCODE_IVP_SVNX8UT_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4199) + return OPCODE_IVP_SVNX8UT_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4200) + return OPCODE_IVP_SVN_2X16ST_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4201) + return OPCODE_IVP_SVN_2X16ST_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4202) + return OPCODE_IVP_SVN_2X16UT_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4203) + return OPCODE_IVP_SVN_2X16UT_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4204) + return OPCODE_L16SI; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4205) + return OPCODE_L16UI; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4206) + return OPCODE_L32I; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4207) + return OPCODE_L8UI; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4208) + return OPCODE_S16I; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4209) + return OPCODE_S32I; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4210) + return OPCODE_S8I; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4211) + return OPCODE_IVP_LV2NX8T_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4212) + return OPCODE_IVP_LVNX8ST_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4213) + return OPCODE_IVP_LVNX8UT_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4214) + return OPCODE_IVP_LVN_2X16ST_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4215) + return OPCODE_IVP_LVN_2X16UT_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4216) + return OPCODE_IVP_SV2NX8T_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4217) + return OPCODE_IVP_SVNX8ST_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4218) + return OPCODE_IVP_SVNX8UT_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4219) + return OPCODE_IVP_SVN_2X16ST_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4220) + return OPCODE_IVP_SVN_2X16UT_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4221) + return OPCODE_MOVI; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4237 && + Field_fld_f0_s0_ldst_12_11_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_GATHERANX8UT; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4237 && + Field_fld_f0_s0_ldst_12_11_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_GATHERANX16T; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4237 && + Field_fld_f0_s0_ldst_12_11_Slot_f0_s0_ldst_get (insn) == 2) + return OPCODE_IVP_GATHERAN_2X32T; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4258 && + Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_7_6_Slot_f0_s0_ldst_get (insn) == 2) + return OPCODE_IVP_SBN_I; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4258 && + Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 14) + return OPCODE_IVP_SBN_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4258 && + Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_7_6_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SBN_2_I; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4258 && + Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 13) + return OPCODE_IVP_SBN_2_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4258 && + Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_7_6_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_SB2N_I; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4258 && + Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 12) + return OPCODE_IVP_SB2N_IP; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2078) + return OPCODE_IVP_LSN_2X32_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2079) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2080) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2081) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2082) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2083) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2084) + return OPCODE_IVP_SSN_2X32_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2085) + return OPCODE_IVP_SV2NX8_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2086) + return OPCODE_IVP_SVNX8S_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2087) + return OPCODE_IVP_SVNX8U_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2088) + return OPCODE_IVP_SVN_2X16S_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2089) + return OPCODE_IVP_SVN_2X16U_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2090) + return OPCODE_EXTUI; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 524 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 525 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1028) + return OPCODE_IVP_LV2NX8T_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1029) + return OPCODE_IVP_LVNX8ST_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1030) + return OPCODE_IVP_LVNX8UT_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1031) + return OPCODE_IVP_LVN_2X16ST_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1032) + return OPCODE_IVP_LVN_2X16UT_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1033) + return OPCODE_IVP_SV2NX8T_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1034) + return OPCODE_IVP_SVNX8ST_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1035) + return OPCODE_IVP_SVNX8UT_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1036) + return OPCODE_IVP_SVN_2X16ST_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1037) + return OPCODE_IVP_SVN_2X16UT_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1038) + return OPCODE_J; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1062 && + Field_fld_f0_s0_ldst_13_9_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1065 && + Field_fld_f0_s0_ldst_15_15_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_12_8_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1065 && + Field_fld_f0_s0_ldst_15_15_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_12_8_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SALIGN_I; + if (Field_fld_f0_s0_ldst_33_19_Slot_f0_s0_ldst_get (insn) == 260 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_REPNX16; + if (Field_fld_f0_s0_ldst_33_19_Slot_f0_s0_ldst_get (insn) == 261 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f0_s0_ldst_33_19_Slot_f0_s0_ldst_get (insn) == 530 && + Field_fld_f0_s0_ldst_13_9_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f0_s0_ldst_33_20_Slot_f0_s0_ldst_get (insn) == 128 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f0_s0_ldst_33_20_Slot_f0_s0_ldst_get (insn) == 129 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f0_s0_ldst_33_20_Slot_f0_s0_ldst_get (insn) == 256) + return OPCODE_CONST16; + if (Field_fld_f0_s0_ldst_33_20_Slot_f0_s0_ldst_get (insn) == 265 && + Field_fld_f0_s0_ldst_13_9_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_9_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_9_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_BBSI_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 8) + return OPCODE_BEQ_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 14) + return OPCODE_BNE_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 10) + return OPCODE_BGE_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 12) + return OPCODE_BLT_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 9) + return OPCODE_BGEU_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 11) + return OPCODE_BLTU_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 5) + return OPCODE_BANY_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 4) + return OPCODE_BALL_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 13) + return OPCODE_BNALL_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 6) + return OPCODE_BBC_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_BBS_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_11_4_Slot_f0_s0_ldst_get (insn) == 6) + return OPCODE_BEQZ_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_11_4_Slot_f0_s0_ldst_get (insn) == 54) + return OPCODE_BNEZ_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_11_4_Slot_f0_s0_ldst_get (insn) == 22) + return OPCODE_BGEZ_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_11_4_Slot_f0_s0_ldst_get (insn) == 38) + return OPCODE_BLTZ_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 5) + return OPCODE_BNEI_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_BGEI_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 3) + return OPCODE_BLTI_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 2) + return OPCODE_BGEUI_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 4) + return OPCODE_BLTUI_W15; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 542396) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 542397) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 542398) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 542399) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 545025 && + Field_fld_f0_s0_ldst_8_0_Slot_f0_s0_ldst_get (insn) == 245) + return OPCODE_IVP_SCATTERW; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 545041 && + Field_fld_f0_s0_ldst_8_0_Slot_f0_s0_ldst_get (insn) == 245) + return OPCODE_NOP; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 545204 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 5) + return OPCODE_SSAI; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 545205 && + Field_fld_f0_s0_ldst_8_4_Slot_f0_s0_ldst_get (insn) == 21) + return OPCODE_SSL; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 545205 && + Field_fld_f0_s0_ldst_8_4_Slot_f0_s0_ldst_get (insn) == 5) + return OPCODE_SSA8L; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 545206 && + Field_fld_f0_s0_ldst_8_4_Slot_f0_s0_ldst_get (insn) == 5) + return OPCODE_SSR; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 545409) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 545441 && + Field_fld_f0_s0_ldst_8_8_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_NSA; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 545457 && + Field_fld_f0_s0_ldst_8_8_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_NSAU; + return XTENSA_UNDEFINED; +} + +static int +Slot_f0_s3_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (insn) == 119328) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (insn) == 119332) + return OPCODE_IVP_EXTRVRN_2X32; + if (Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (insn) == 119336 && + Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_get (insn) == 13) + return OPCODE_IVP_MOVBRBV; + if (Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (insn) == 119336 && + Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (insn) == 119336 && + Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_get (insn) == 7) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (insn) == 119336 && + Field_fld_f0_s3_alu_7_7_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_INJBI2NX8; + if (Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (insn) == 119336 && + Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (insn) == 119336 && + Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_get (insn) == 9) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (insn) == 119336 && + Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_get (insn) == 5) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f0_s3_alu_33_18_Slot_f0_s3_alu_get (insn) == 3728 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 532 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SRAIN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 533 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_3_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SLLINX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 533 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_3_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_ROTRINX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 564 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SRANX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 565 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_3_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SLSINX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 565 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_3_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 596 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SRAN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 597 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_3_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 597 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_2_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_ROTRI2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 597 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_2_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SLLI2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 628 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SRLIN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 629 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 12 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 7) + return OPCODE_IVP_MOVVV; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 629 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 14 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 7) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 629 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 13 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 7) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 629 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 12 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 5) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 629 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 15 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 5) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 629 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_2_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 629 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_2_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 629 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 13 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 5) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 629 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 13 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 6) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 660 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SRLNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 692 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SRLN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 724 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SRSNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 756 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SRSN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 760 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 7 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RADD2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 771 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_MINNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 772) + return OPCODE_IVP_SEL2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 44 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 56 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NSANX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 33 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NSAUNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 40 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_get (insn) == 1 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SHFLNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SHFLN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 32 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 60 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NSAN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 37 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NSAUN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SHFL2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 804) + return OPCODE_IVP_SELNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 835 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 836) + return OPCODE_IVP_SELN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 837 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 1 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 837 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 1 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 867 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 868 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 868 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 868 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 868 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 8 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 9 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 10 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 9 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMAXUNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 10 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMINUNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 8 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 9 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMAXN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 10 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMINN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 10 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXUN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 11 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINUN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 9 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDUNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 8 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RADDU2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 8 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RADDSNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 899 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 900 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 14) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 900 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 11) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 900 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 900 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 15) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 900 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 10) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 900 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 9) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 901 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 14) + return OPCODE_IVP_SLANX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 901 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 8) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 901 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 15) + return OPCODE_IVP_SLLN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 931 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 931 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 932 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 11) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 932 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 15) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 932 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 12) + return OPCODE_IVP_MINNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 932 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 10) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 932 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 13) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 932 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 14) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 932 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 9) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 933 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 15) + return OPCODE_IVP_SLSIN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 933 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 14) + return OPCODE_IVP_SLAN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 933 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 13) + return OPCODE_IVP_ROTRIN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 963 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 10) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 13) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 7) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 14) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 15) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 11) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 9) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 965 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 15) + return OPCODE_IVP_SLSNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 965 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 14) + return OPCODE_IVP_SLLIN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 965 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 13) + return OPCODE_IVP_ROTRNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 995 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 14) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 15) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 5) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 10) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 12) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 13) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 4) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 9) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 11) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 997 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 14) + return OPCODE_IVP_SLLNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 997 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 15) + return OPCODE_IVP_SLSN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 997 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 13) + return OPCODE_IVP_ROTRN_2X32; + if (Field_fld_f0_s3_alu_33_25_Slot_f0_s3_alu_get (insn) == 8) + return OPCODE_IVP_DSELNX16; + if (Field_fld_f0_s3_alu_33_26_Slot_f0_s3_alu_get (insn) == 12 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 5 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 1 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_REPNX16; + if (Field_fld_f0_s3_alu_33_26_Slot_f0_s3_alu_get (insn) == 12 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 5 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 1 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f0_s3_alu_33_26_Slot_f0_s3_alu_get (insn) == 14 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 720) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f0_s3_alu_33_27_Slot_f0_s3_alu_get (insn) == 4 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_DSEL2NX8I_H; + if (Field_fld_f0_s3_alu_33_27_Slot_f0_s3_alu_get (insn) == 6 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 5 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 1 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f0_s3_alu_33_27_Slot_f0_s3_alu_get (insn) == 6 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 5 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 1 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f0_s3_alu_33_27_Slot_f0_s3_alu_get (insn) == 6 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 720) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f0_s3_alu_33_27_Slot_f0_s3_alu_get (insn) == 7 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 4 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 8) + return OPCODE_IVP_SHFL2NX8I; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_DSELNX16T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 24323 && + Field_fld_f0_s3_alu_7_3_Slot_f0_s3_alu_get (insn) == 16 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_MOVBVBR; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RBMINNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 14 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RBMAXNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 8 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 9 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDNX16T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMAXNX16T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 4 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMINNX16T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMAXUNX16T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 5 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMINUNX16T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 5 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 11 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 1 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RBMINUNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 15 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RBMAXUNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 1 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 7 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 4 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 10 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 9 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 6 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 12 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 10 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDN_2X32T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_14_11_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_DSEL2NX8I; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 24323 && + Field_fld_f0_s3_alu_7_7_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTBI2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 8 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADD2NX8T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 13 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDUNX16T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 12 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDU2NX8T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 13 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 11 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDSNX16T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_7_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 50) + return OPCODE_IVP_NOTB; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 34) + return OPCODE_IVP_MB; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5825) + return OPCODE_IVP_LTNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5796) + return OPCODE_IVP_LENX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5793) + return OPCODE_IVP_EQNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5828) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5858) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5799) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 18) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 66) + return OPCODE_IVP_NOTB1; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5856) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5795) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5792) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5859) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5826) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5798) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SELNX16T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_SELN_2X32T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5857) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5797) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5794) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5860) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5827) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5824) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_14_14_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8I; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 82) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 4) + return OPCODE_IVP_RORB2N; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 98) + return OPCODE_IVP_RANDBN; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 6) + return OPCODE_IVP_RORBN; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 114) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 20) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f0_s3_alu_33_9_Slot_f0_s3_alu_get (insn) == 1584640 && + Field_fld_f0_s3_alu_8_8_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_MOV_N; + if (Field_fld_f0_s3_alu_33_9_Slot_f0_s3_alu_get (insn) == 1584640 && + Field_fld_f0_s3_alu_8_0_Slot_f0_s3_alu_get (insn) == 22) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_f1_s0_ldstalu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 4369 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 13) + return OPCODE_SLL; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 4371 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 13) + return OPCODE_IVP_MOVGATHERD; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5064) + return OPCODE_ADD; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5065) + return OPCODE_ADDX2; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5072) + return OPCODE_ADDX4; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5073) + return OPCODE_ADDX8; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5080) + return OPCODE_AND; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5081) + return OPCODE_MAX; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5088) + return OPCODE_MUL16U; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5089) + return OPCODE_MULL; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5096) + return OPCODE_MULSH; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5097) + return OPCODE_MULUH; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5104) + return OPCODE_OR; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5105) + return OPCODE_SALT; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5112) + return OPCODE_SALTU; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5113) + return OPCODE_SRC; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5185 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_GATHERANX16; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5189) + return OPCODE_SUB; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5190) + return OPCODE_MAXU; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5191) + return OPCODE_SUBX2; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5193 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_GATHERANX8U; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5197) + return OPCODE_SUBX4; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5198) + return OPCODE_MIN; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5199) + return OPCODE_SUBX8; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5201 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_GATHERAN_2X32; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5205) + return OPCODE_XOR; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5206) + return OPCODE_MINU; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5207) + return OPCODE_CLAMPS; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5213) + return OPCODE_SEXT; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5214) + return OPCODE_MOVEQZ; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5215) + return OPCODE_SRLI; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5221 && + Field_fld_f1_s0_ldstalu_3_0_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5221 && + Field_fld_f1_s0_ldstalu_3_0_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5221 && + Field_fld_f1_s0_ldstalu_3_0_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5221 && + Field_fld_f1_s0_ldstalu_3_0_Slot_f1_s0_ldstalu_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5222) + return OPCODE_MOVGEZ; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5230) + return OPCODE_MOVLTZ; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5238) + return OPCODE_MOVNEZ; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5246) + return OPCODE_MUL16S; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 1782) + return OPCODE_IVP_LS2NX8_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 1783) + return OPCODE_IVP_LS2NX8_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 1786) + return OPCODE_IVP_LSNX16_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 1787) + return OPCODE_IVP_LSNX8S_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 1790) + return OPCODE_IVP_LSNX16_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 1791) + return OPCODE_IVP_LSNX8S_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2496) + return OPCODE_IVP_SVNX8S_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2497) + return OPCODE_SLLI; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2498) + return OPCODE_IVP_LSRN_2X32_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2499) + return OPCODE_IVP_SSNX8S_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2500) + return OPCODE_IVP_SVNX8S_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2501) + return OPCODE_IVP_LS2NX8_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2502) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2503) + return OPCODE_IVP_SSN_2X16S_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2504) + return OPCODE_IVP_SVNX8U_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2505) + return OPCODE_IVP_LSNX16_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2506) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2507) + return OPCODE_IVP_SSN_2X32_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2508) + return OPCODE_IVP_SVNX8U_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2509) + return OPCODE_IVP_LSNX8S_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2510) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2511) + return OPCODE_IVP_SV2NX8_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2512) + return OPCODE_IVP_SVN_2X16S_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2513) + return OPCODE_IVP_LSN_2X16S_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2514) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2515) + return OPCODE_IVP_SVNX8S_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2516) + return OPCODE_IVP_SVN_2X16S_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2517) + return OPCODE_IVP_LSN_2X32_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2518) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2519) + return OPCODE_IVP_SVNX8U_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2520) + return OPCODE_IVP_SVN_2X16U_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2521) + return OPCODE_IVP_LSR2NX8_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2522) + return OPCODE_IVP_SS2NX8_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2523) + return OPCODE_IVP_SVN_2X16S_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2524) + return OPCODE_IVP_SVN_2X16U_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2525) + return OPCODE_IVP_LSRNX16_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2526) + return OPCODE_IVP_SSNX16_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2527) + return OPCODE_IVP_SVN_2X16U_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2528) + return OPCODE_SRAI; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2561) + return OPCODE_IVP_LSN_2X16S_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2565) + return OPCODE_IVP_LSN_2X16S_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2569) + return OPCODE_IVP_LSN_2X32_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2573) + return OPCODE_IVP_LSN_2X32_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2577) + return OPCODE_IVP_LSR2NX8_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2581) + return OPCODE_IVP_LSR2NX8_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2585) + return OPCODE_IVP_LSRNX16_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2589) + return OPCODE_IVP_LSRNX16_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2593) + return OPCODE_IVP_LSRN_2X32_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2597) + return OPCODE_IVP_LSRN_2X32_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2601) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2605) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2609) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2613) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2617) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2621) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2625) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2629) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2633) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2637) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2641) + return OPCODE_IVP_SS2NX8_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2645) + return OPCODE_IVP_SS2NX8_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2649) + return OPCODE_IVP_SSNX16_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2653) + return OPCODE_IVP_SSNX16_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2657) + return OPCODE_IVP_SSNX8S_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2661) + return OPCODE_IVP_SSNX8S_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2665) + return OPCODE_IVP_SSN_2X16S_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2669) + return OPCODE_IVP_SSN_2X16S_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2673) + return OPCODE_IVP_SSN_2X32_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2677) + return OPCODE_IVP_SSN_2X32_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2681) + return OPCODE_IVP_SV2NX8_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2685) + return OPCODE_IVP_SV2NX8_XP; + if (Field_fld_f1_s0_ldstalu_30_14_Slot_f1_s0_ldstalu_get (insn) == 881) + return OPCODE_IVP_SCATTER2NX8_H; + if (Field_fld_f1_s0_ldstalu_30_14_Slot_f1_s0_ldstalu_get (insn) == 883) + return OPCODE_IVP_SCATTER2NX8_L; + if (Field_fld_f1_s0_ldstalu_30_14_Slot_f1_s0_ldstalu_get (insn) == 885) + return OPCODE_IVP_SCATTERNX16; + if (Field_fld_f1_s0_ldstalu_30_14_Slot_f1_s0_ldstalu_get (insn) == 887) + return OPCODE_IVP_SCATTERNX8U; + if (Field_fld_f1_s0_ldstalu_30_14_Slot_f1_s0_ldstalu_get (insn) == 889) + return OPCODE_IVP_SCATTERN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 524) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 525) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 526) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 527) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 528) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 529) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 530) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 531) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 532) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 533) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 534) + return OPCODE_IVP_SAV2NX8_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 535) + return OPCODE_IVP_SAVNX8S_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 536) + return OPCODE_IVP_SAVNX8U_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 537) + return OPCODE_IVP_SAVN_2X16S_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 538) + return OPCODE_IVP_SAVN_2X16U_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 539) + return OPCODE_IVP_LS2NX8_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 540) + return OPCODE_IVP_LSNX16_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 541) + return OPCODE_IVP_LSNX8S_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 542) + return OPCODE_IVP_LSN_2X16S_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 543) + return OPCODE_IVP_LSR2NX8_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 544 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_7_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 544 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_7_7_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 545 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 14) + return OPCODE_IVP_MOVVV; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 545 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 12) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 545 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 9) + return OPCODE_IVP_SANX8U_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 545 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 8) + return OPCODE_IVP_SANX8S_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 545 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 11) + return OPCODE_IVP_SAN_2X16U_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 545 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 10) + return OPCODE_IVP_SAN_2X16S_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 545 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 15) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 545 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 14) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 545 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 13) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 546 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 9) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 546 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 10) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 546 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 11) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 546 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_5_Slot_f1_s0_ldstalu_get (insn) == 7) + return OPCODE_IVP_SHFL2NX8I_S0; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 547 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 11) + return OPCODE_IVP_SA2NX8_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 547 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 9) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 547 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 10) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 547 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 14) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 547 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 15) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 547 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 15) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 576) + return OPCODE_IVP_LSRNX16_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 577) + return OPCODE_IVP_LSRN_2X32_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 578) + return OPCODE_IVP_SS2NX8_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 579) + return OPCODE_IVP_SSNX16_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 580) + return OPCODE_IVP_SSNX8S_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 581) + return OPCODE_IVP_SSN_2X16S_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 582) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 583) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 584) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 585) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 586) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 587) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 588) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 589) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 590) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 591) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 592) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 593) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 594) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 595) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 596) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 597) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 598) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 599) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 600) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 601) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 602) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 603) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 604) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 605) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 606) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 607) + return OPCODE_IVP_MINNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 608) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 609) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 610) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 611) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 612) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 613) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 614) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 615) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 616) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 617) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 618) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 619) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 620) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 623 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 623 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 672 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 672 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 672 && + Field_fld_f1_s0_ldstalu_12_8_Slot_f1_s0_ldstalu_get (insn) == 4) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 672 && + Field_fld_f1_s0_ldstalu_12_8_Slot_f1_s0_ldstalu_get (insn) == 5) + return OPCODE_IVP_SALIGN_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 672 && + Field_fld_f1_s0_ldstalu_12_4_Slot_f1_s0_ldstalu_get (insn) == 37) + return OPCODE_IVP_LA_PP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 672 && + Field_fld_f1_s0_ldstalu_12_4_Slot_f1_s0_ldstalu_get (insn) == 53) + return OPCODE_IVP_SAPOS_FP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 672 && + Field_fld_f1_s0_ldstalu_12_2_Slot_f1_s0_ldstalu_get (insn) == 404) + return OPCODE_IVP_MALIGN; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 672 && + Field_fld_f1_s0_ldstalu_12_0_Slot_f1_s0_ldstalu_get (insn) == 1620) + return OPCODE_IVP_ZALIGN; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 210) + return OPCODE_ADDI; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 211) + return OPCODE_ADDMI; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 224) + return OPCODE_IVP_LV2NX8T_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 225) + return OPCODE_IVP_LV2NX8T_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 226) + return OPCODE_IVP_LVNX8ST_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 227) + return OPCODE_IVP_LVNX8ST_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 228) + return OPCODE_IVP_LVNX8UT_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 229) + return OPCODE_IVP_LVNX8UT_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 230) + return OPCODE_IVP_LVN_2X16ST_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 231) + return OPCODE_IVP_LVN_2X16ST_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 232) + return OPCODE_IVP_LVN_2X16UT_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 233) + return OPCODE_IVP_LVN_2X16UT_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 234) + return OPCODE_IVP_SV2NX8T_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 235) + return OPCODE_IVP_SV2NX8T_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 236) + return OPCODE_IVP_SVNX8ST_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 237) + return OPCODE_IVP_SVNX8ST_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 238) + return OPCODE_IVP_SVNX8UT_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 239) + return OPCODE_IVP_SVNX8UT_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 240) + return OPCODE_IVP_SVN_2X16ST_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 241) + return OPCODE_IVP_SVN_2X16ST_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 242) + return OPCODE_IVP_SVN_2X16UT_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 243) + return OPCODE_IVP_SVN_2X16UT_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 244) + return OPCODE_L16SI; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 245) + return OPCODE_L16UI; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 246) + return OPCODE_L32I; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 247) + return OPCODE_L8UI; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 248) + return OPCODE_S16I; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 249) + return OPCODE_S32I; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 250) + return OPCODE_S8I; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 251) + return OPCODE_IVP_LV2NX8T_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 252) + return OPCODE_IVP_LVNX8ST_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 253) + return OPCODE_IVP_LVNX8UT_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 254) + return OPCODE_IVP_LVN_2X16ST_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 255) + return OPCODE_IVP_LVN_2X16UT_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 256) + return OPCODE_IVP_SV2NX8T_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 257) + return OPCODE_IVP_SVNX8ST_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 258) + return OPCODE_IVP_SVNX8UT_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 259) + return OPCODE_IVP_SVN_2X16ST_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 260) + return OPCODE_IVP_SVN_2X16UT_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 261) + return OPCODE_MOVI; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 272 && + Field_fld_f1_s0_ldstalu_7_5_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_IVP_SB2N_I; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 273 && + Field_fld_f1_s0_ldstalu_12_12_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 13) + return OPCODE_IVP_SBN_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 273 && + Field_fld_f1_s0_ldstalu_7_5_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_IVP_SBN_2_I; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 273 && + Field_fld_f1_s0_ldstalu_12_12_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 12) + return OPCODE_IVP_SBN_2_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 273 && + Field_fld_f1_s0_ldstalu_12_12_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 12) + return OPCODE_IVP_SB2N_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 273 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 8) + return OPCODE_LOOPNEZ; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 274 && + Field_fld_f1_s0_ldstalu_7_5_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_IVP_SBN_I; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 275 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 6) + return OPCODE_LOOP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 275 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 7) + return OPCODE_LOOPGTZ; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 92) + return OPCODE_IVP_LSN_2X32_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 93) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 94) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 95) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 96) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 97) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 98) + return OPCODE_IVP_SSN_2X32_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 99) + return OPCODE_IVP_SV2NX8_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 100) + return OPCODE_IVP_SVNX8S_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 101) + return OPCODE_IVP_SVNX8U_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 102) + return OPCODE_IVP_SVN_2X16S_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 103) + return OPCODE_IVP_SVN_2X16U_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 104) + return OPCODE_EXTUI; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 8) + return OPCODE_IVP_LV2NX8T_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 9) + return OPCODE_IVP_LVNX8ST_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 10) + return OPCODE_IVP_LVNX8UT_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 11) + return OPCODE_IVP_LVN_2X16ST_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 12) + return OPCODE_IVP_LVN_2X16UT_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 13) + return OPCODE_IVP_SV2NX8T_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 14) + return OPCODE_IVP_SVNX8ST_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 15) + return OPCODE_IVP_SVNX8UT_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 16) + return OPCODE_IVP_SVN_2X16ST_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 17) + return OPCODE_IVP_SVN_2X16UT_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 18) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 19) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 20) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 21) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 22) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 23) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 24) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 25) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 26) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 27) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 28) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 29) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 30) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 31) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 32) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 33) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 34) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 35) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 36) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 37) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 38) + return OPCODE_IVP_MINNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 39) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 40) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 41) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 42) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 43) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 44) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 45) + return OPCODE_J; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 53 && + Field_fld_f1_s0_ldstalu_14_14_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_SCATTER2NX8T_L; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 53 && + Field_fld_f1_s0_ldstalu_14_14_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_SCATTER2NX8T_H; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 54 && + Field_fld_f1_s0_ldstalu_14_14_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_SCATTERNX8UT; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 54 && + Field_fld_f1_s0_ldstalu_14_14_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_SCATTERNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 55 && + Field_fld_f1_s0_ldstalu_14_14_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_SCATTERN_2X32T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 68 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 5) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 70 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 2) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 70 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 71 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 2) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 80 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 2) + return OPCODE_IVP_LTNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 80 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 80 && + Field_fld_f1_s0_ldstalu_14_12_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_GATHERANX8UT; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 80 && + Field_fld_f1_s0_ldstalu_14_12_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_GATHERANX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 81 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 81 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 2) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 81 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 16) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 81 && + Field_fld_f1_s0_ldstalu_14_12_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_GATHERAN_2X32T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 82 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 6) + return OPCODE_IVP_LENX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 82 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 5) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 82 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 82 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 82 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 7) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 82 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 4) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 82 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 2) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 83 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_EQNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 83 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 2) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 83 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 5) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 83 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 7) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 83 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 4) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 83 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 83 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 6) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 84 && + Field_fld_f1_s0_ldstalu_15_15_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_12_8_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 84 && + Field_fld_f1_s0_ldstalu_15_15_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_12_8_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_SALIGN_I; + if (Field_fld_f1_s0_ldstalu_30_19_Slot_f1_s0_ldstalu_get (insn) == 34 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 2) + return OPCODE_IVP_REPNX16; + if (Field_fld_f1_s0_ldstalu_30_19_Slot_f1_s0_ldstalu_get (insn) == 34 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f1_s0_ldstalu_30_19_Slot_f1_s0_ldstalu_get (insn) == 40 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f1_s0_ldstalu_30_20_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_CONST16; + if (Field_fld_f1_s0_ldstalu_30_20_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_SEL2NX8I_S0; + if (Field_fld_f1_s0_ldstalu_30_20_Slot_f1_s0_ldstalu_get (insn) == 17 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f1_s0_ldstalu_30_20_Slot_f1_s0_ldstalu_get (insn) == 17 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f1_s0_ldstalu_30_20_Slot_f1_s0_ldstalu_get (insn) == 20 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f1_s0_ldstalu_30_6_Slot_f1_s0_ldstalu_get (insn) == 279771 && + Field_fld_f1_s0_ldstalu_5_4_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_SSA8L; + if (Field_fld_f1_s0_ldstalu_30_6_Slot_f1_s0_ldstalu_get (insn) == 279775 && + Field_fld_f1_s0_ldstalu_5_4_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_SSL; + if (Field_fld_f1_s0_ldstalu_30_6_Slot_f1_s0_ldstalu_get (insn) == 279787 && + Field_fld_f1_s0_ldstalu_5_4_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_SSR; + if (Field_fld_f1_s0_ldstalu_30_6_Slot_f1_s0_ldstalu_get (insn) == 344089 && + Field_fld_f1_s0_ldstalu_5_0_Slot_f1_s0_ldstalu_get (insn) == 21) + return OPCODE_IVP_SCATTERW; + if (Field_fld_f1_s0_ldstalu_30_6_Slot_f1_s0_ldstalu_get (insn) == 344217 && + Field_fld_f1_s0_ldstalu_5_0_Slot_f1_s0_ldstalu_get (insn) == 21) + return OPCODE_NOP; + if (Field_fld_f1_s0_ldstalu_30_8_Slot_f1_s0_ldstalu_get (insn) == 86340) + return OPCODE_NSA; + if (Field_fld_f1_s0_ldstalu_30_8_Slot_f1_s0_ldstalu_get (insn) == 86372) + return OPCODE_NSAU; + if (Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_get (insn) == 34969 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 13) + return OPCODE_SSAI; + if (Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_get (insn) == 41673) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_get (insn) == 41675) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_get (insn) == 41677) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_get (insn) == 41679) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_get (insn) == 43138) + return OPCODE_IVP_MOVAVU8; + return XTENSA_UNDEFINED; +} + +static int +Slot_f1_s2_mul_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4000) + return OPCODE_ADD; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4001) + return OPCODE_ADDX4; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4002) + return OPCODE_AND; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4003) + return OPCODE_SUB; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4004) + return OPCODE_ADDX2; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4005) + return OPCODE_ADDX8; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4006) + return OPCODE_OR; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4007) + return OPCODE_SUBX2; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4008) + return OPCODE_SUBX4; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4009) + return OPCODE_XOR; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4012) + return OPCODE_SUBX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 390) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 391) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 392) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 393) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 394) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 395) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 396) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 397) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 398) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 399) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 400) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 401) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 402) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 403) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 404) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 405) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 406) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 407) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 408) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 411) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 413) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 415) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 416) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 417) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 418) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 421) + return OPCODE_IVP_MINNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 423) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 425) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 426) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 427) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 428) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 429) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 430) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 431) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 432) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 433) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 434) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 435) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 436) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 445) + return OPCODE_IVP_MULNX16PACKL; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 446) + return OPCODE_IVP_MULNX16PACKP; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 447) + return OPCODE_IVP_MULNX16PACKQ; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 460) + return OPCODE_IVP_REPNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 461) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 462 && + Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_SLSINX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 462 && + Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_ROTRINX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 463 && + Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_SLLINX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 463 && + Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 464 && + Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 464 && + Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 465 && + Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 465 && + Field_fld_f1_s2_mul_3_2_Slot_f1_s2_mul_get (insn) == 2) + return OPCODE_IVP_ROTRI2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 465 && + Field_fld_f1_s2_mul_3_2_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_SLLI2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 466 && + Field_fld_f1_s2_mul_3_2_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 467 && + Field_fld_f1_s2_mul_3_2_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 488 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 488 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 488 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 488 && + Field_fld_f1_s2_mul_9_6_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_SHFL2NX8I_S2; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 489 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 490 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 490 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_UNPKS2NX8_0; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 490 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_UNPKSNX16_H; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 490 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_UNPKU2NX8_0; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 491 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_UNPKS2NX8_1; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 491 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_UNPKSNX16_L; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 491 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_UNPKU2NX8_1; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 491 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 493 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 2) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 493 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 494 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MOVVV; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 495 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 180) + return OPCODE_IVP_MUL4T2N8XR8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 181) + return OPCODE_IVP_MUL4TA2N8XR8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 182) + return OPCODE_IVP_MULP2N8XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 183) + return OPCODE_IVP_MULPA2N8XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 184) + return OPCODE_IVP_MULPAN16XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 185) + return OPCODE_IVP_MULPN16XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 186) + return OPCODE_IVP_MULUS4T2N8XR8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 187) + return OPCODE_IVP_MULUS4TA2N8XR8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 188) + return OPCODE_IVP_MULUSP2N8XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 189) + return OPCODE_IVP_MULUSPA2N8XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 190) + return OPCODE_IVP_MULUSPAN16XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 191) + return OPCODE_IVP_MULUSPN16XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 192) + return OPCODE_ADDI; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 193) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 194) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_ADDW2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_ADDWA2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 8) + return OPCODE_IVP_ADDWS2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 10) + return OPCODE_IVP_ADDWU2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 11) + return OPCODE_IVP_ADDWUA2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 14) + return OPCODE_IVP_ADDWUS2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 7) + return OPCODE_IVP_ADDWNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_ADDWANX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 9) + return OPCODE_IVP_ADDWSNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 13) + return OPCODE_IVP_ADDWUNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 12) + return OPCODE_IVP_ADDWUANX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 15) + return OPCODE_IVP_ADDWUSNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULANX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULA2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULSNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULAN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULSUAN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULAHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULSUAHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULAN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULSHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULSN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULSN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUS2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSA2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUSNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUSANX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUSN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULSUN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULSUN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUSHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULSUHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUSAN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUSAHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUSAN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULSUAN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSUSHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULSUSN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULSUSN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 240 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 13) + return OPCODE_IVP_CVT24S2NX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 240 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 15) + return OPCODE_IVP_CVT48UNX32; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 240 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 14) + return OPCODE_IVP_CVT48SNX32; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 241 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 13) + return OPCODE_IVP_CVT24U2NX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 241 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 15) + return OPCODE_IVP_CVT48UN_2X64L; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 241 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 14) + return OPCODE_IVP_CVT48UN_2X64H; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 242 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 13) + return OPCODE_IVP_CVT24UNX32H; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 242 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 14) + return OPCODE_IVP_CVT96UN_2X64; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 242 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 15 && + Field_fld_f1_s2_mul_4_4_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULA2N8XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 242 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 15 && + Field_fld_f1_s2_mul_4_4_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL2N8XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 243 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 13) + return OPCODE_IVP_CVT24UNX32L; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 243 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 14 && + Field_fld_f1_s2_mul_4_4_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUSA2N8XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 243 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 14 && + Field_fld_f1_s2_mul_4_4_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUS2N8XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 245 && + Field_fld_f1_s2_mul_13_5_Slot_f1_s2_mul_get (insn) == 7) + return OPCODE_IVP_CVT24U32; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 245 && + Field_fld_f1_s2_mul_13_5_Slot_f1_s2_mul_get (insn) == 103) + return OPCODE_IVP_CVT48UNX32L; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 245 && + Field_fld_f1_s2_mul_13_5_Slot_f1_s2_mul_get (insn) == 39) + return OPCODE_IVP_CVT48SNX32L; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 245 && + Field_fld_f1_s2_mul_13_5_Slot_f1_s2_mul_get (insn) == 71) + return OPCODE_IVP_CVT48U64; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 245 && + Field_fld_f1_s2_mul_13_5_Slot_f1_s2_mul_get (insn) == 135) + return OPCODE_IVP_CVT96U64; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 245 && + Field_fld_f1_s2_mul_13_2_Slot_f1_s2_mul_get (insn) == 1592) + return OPCODE_IVP_MOVWW; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUU2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUUA2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUUNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUUANX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSSNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUUN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUUN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUSN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUUHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUUAN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUUAHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUAN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUUSHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUSSHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSSN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUSSN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUUSNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUUSN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUUSN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_SUBWNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_SUBWANX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 10) + return OPCODE_IVP_SUBWUNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 9) + return OPCODE_IVP_SUBWUANX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_SUBW2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_SUBWA2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 7) + return OPCODE_IVP_SUBWU2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 8) + return OPCODE_IVP_SUBWUA2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 7) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 8) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 9) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 10) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 11) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 12) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 13) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 14) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 15) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 16) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 17) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 18) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 19) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 20) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 21) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 24) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 27) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 30) + return OPCODE_IVP_MINNX16T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 33) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 34) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 35) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 36) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 37) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 38) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_LTNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 2) + return OPCODE_IVP_LENX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 16) + return OPCODE_IVP_EQNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 8) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 22) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 19) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 20) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 17) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 23) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 21) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 18) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 24) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 7) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f1_s2_mul_28_20_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_SEL2NX8I_S2; + if (Field_fld_f1_s2_mul_28_4_Slot_f1_s2_mul_get (insn) == 1003918 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_f1_s3_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_get (insn) == 1542 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_EXTRVRN_2X32; + if (Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_get (insn) == 1543 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_get (insn) == 1543 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_get (insn) == 1543 && + Field_fld_f1_s3_alu_9_7_Slot_f1_s3_alu_get (insn) == 4 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_INJBI2NX8; + if (Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_get (insn) == 1543 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_get (insn) == 1543 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_get (insn) == 9) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_get (insn) == 1543 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f1_s3_alu_30_17_Slot_f1_s3_alu_get (insn) == 384 && + Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_ADDI; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 24 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_MINNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 24 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 25 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 25 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 25 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 25 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 25 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 25 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 25 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 27 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 27 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_ROTRIN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 28 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 29 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 30 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 31 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 32) + return OPCODE_IVP_SEL2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 33) + return OPCODE_IVP_SELNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 34) + return OPCODE_IVP_SELN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 35 && + Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_COUNTEQZ4NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 35 && + Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_COUNTEQ4NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 36 && + Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_COUNTLE4NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 37 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 37 && + Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_COUNTLEZ4NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 38 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 38 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 38 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 39 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 39 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 40 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 40 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 41 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 41 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 42 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 43 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_MINNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 43 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 43 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 44 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 44 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 45 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 45 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 45 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 45 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 46 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 46 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 46 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 47 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 47 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 47 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 47 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 48 && + Field_fld_f1_s3_alu_14_14_Slot_f1_s3_alu_get (insn) == 1 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLLINX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 48 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_SLSNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 48 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_SRSNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 48 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 69) + return OPCODE_IVP_RADDNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 48 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 85) + return OPCODE_IVP_RADDN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 48 && + Field_fld_f1_s3_alu_14_14_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_ROTRINX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 48 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_ROTRNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 48 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 117) + return OPCODE_IVP_RADDU2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 48 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 101) + return OPCODE_IVP_RADDSNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_14_14_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLSINX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_14_14_Slot_f1_s3_alu_get (insn) == 1 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 85) + return OPCODE_IVP_RMAXNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 117) + return OPCODE_IVP_RMAXUNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_SLSN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_SRSN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 101) + return OPCODE_IVP_RMAXN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_ROTRN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 69) + return OPCODE_IVP_RADDUNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 50 && + Field_fld_f1_s3_alu_14_14_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 50 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLANX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 50 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 85) + return OPCODE_IVP_RMINNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 50 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 117) + return OPCODE_IVP_RMINUNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 50 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_SRAIN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 50 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 101) + return OPCODE_IVP_RMINN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 50 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 69) + return OPCODE_IVP_RMAXUN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 50 && + Field_fld_f1_s3_alu_14_13_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_ROTRI2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 50 && + Field_fld_f1_s3_alu_14_13_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLLI2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 112 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_MOVVV; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_SRANX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 120 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 116 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLAN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 69) + return OPCODE_IVP_RMINUN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 80 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 92 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_14_13_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_14_13_Slot_f1_s3_alu_get (insn) == 1 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 84 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 100 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 52 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLLIN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 52 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_SRAN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 53 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLLNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 53 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_SRLIN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 54 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_SRLNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 54 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLLN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 55 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLSIN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 55 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_SRLN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 55 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 116) + return OPCODE_IVP_RADD2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 17 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 17 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_NSANX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 21 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_NSAUNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 17 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 16) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 28) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_10_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_SHFLNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_10_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_SHFLN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 17 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 17 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_NSAN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 21 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_NSAUN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_10_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_SHFL2NX8; + if (Field_fld_f1_s3_alu_30_22_Slot_f1_s3_alu_get (insn) == 10 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_SHFL2NX8I; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_SELNX16T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_SELN_2X32T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8I; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_14_Slot_f1_s3_alu_get (insn) == 62 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 908) + return OPCODE_IVP_MOVBVBR; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 20 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_LTNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 22 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_LENX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 21 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_EQNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 22 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 23 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 23 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 1 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 21 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_2_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 1 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 1 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 1 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 1 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 23 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 23 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 21 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 21 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 22 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 22 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 21 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 23 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 22 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 23 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 20 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 22 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 31 && + Field_fld_f1_s3_alu_9_7_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_get (insn) == 12) + return OPCODE_IVP_EXTBI2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 30 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 1 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 20 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_3_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_2_Slot_f1_s3_alu_get (insn) == 8) + return OPCODE_IVP_REPNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_2_Slot_f1_s3_alu_get (insn) == 12) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_3_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_3_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_1_Slot_f1_s3_alu_get (insn) == 18) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_1_Slot_f1_s3_alu_get (insn) == 26) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_7_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 27 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_NOTB; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 26 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_MB; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 67) + return OPCODE_IVP_RBMINNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 98) + return OPCODE_IVP_RBMAXNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 81) + return OPCODE_IVP_RADDNX16T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 99) + return OPCODE_IVP_RMAXNX16T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 68) + return OPCODE_IVP_RMINNX16T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 115) + return OPCODE_IVP_RMAXUNX16T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 84) + return OPCODE_IVP_RMINUNX16T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 25 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 24 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 28 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_NOTB1; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 83) + return OPCODE_IVP_RBMINUNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 114) + return OPCODE_IVP_RBMAXUNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 97) + return OPCODE_IVP_RADDN_2X32T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 65) + return OPCODE_IVP_RADD2NX8T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 82) + return OPCODE_IVP_RADDUNX16T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 66) + return OPCODE_IVP_RADDU2NX8T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 113) + return OPCODE_IVP_RADDSNX16T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 29 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 16 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_RORB2N; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 30 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_RANDBN; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 17 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_RORBN; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 31 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 18 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f1_s3_alu_30_6_Slot_f1_s3_alu_get (insn) == 786436 && + Field_fld_f1_s3_alu_5_0_Slot_f1_s3_alu_get (insn) == 49) + return OPCODE_NOP; + if (Field_fld_f1_s3_alu_30_8_Slot_f1_s3_alu_get (insn) == 196613) + return OPCODE_MOV_N; + if (Field_fld_f1_s3_alu_30_8_Slot_f1_s3_alu_get (insn) == 200709 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_MOVBRBV; + return XTENSA_UNDEFINED; +} + +static int +Slot_f2_s2_mul_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 7809) + return OPCODE_ADD; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 7817) + return OPCODE_ADDX4; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 7825) + return OPCODE_AND; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 7833) + return OPCODE_SUB; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 7841) + return OPCODE_SUBX4; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 7849) + return OPCODE_XOR; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 8065) + return OPCODE_ADDX2; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 8073) + return OPCODE_ADDX8; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 8081) + return OPCODE_OR; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 8089) + return OPCODE_SUBX2; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 8097) + return OPCODE_SUBX8; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 973 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 973 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 18) + return OPCODE_IVP_UNPKSNX16_L; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 973 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_UNPKSNX16_H; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1004 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_MOVVV; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1004 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1004 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 22) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1004 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1004 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 19) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1004 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 18) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1004 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 20) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1005 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 16) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1005 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1005 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_UNPKS2NX8_0; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1005 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 17) + return OPCODE_IVP_UNPKS2NX8_1; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1005 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_UNPKU2NX8_0; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1005 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 18) + return OPCODE_IVP_UNPKU2NX8_1; + if (Field_fld_f2_s2_mul_30_18_Slot_f2_s2_mul_get (insn) == 118 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 17) + return OPCODE_IVP_ROTRI2NX8; + if (Field_fld_f2_s2_mul_30_18_Slot_f2_s2_mul_get (insn) == 119 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 17) + return OPCODE_IVP_SLLI2NX8; + if (Field_fld_f2_s2_mul_30_18_Slot_f2_s2_mul_get (insn) == 122 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f2_s2_mul_30_18_Slot_f2_s2_mul_get (insn) == 126 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_get (insn) == 56 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 17) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_get (insn) == 56 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 16) + return OPCODE_IVP_ROTRINX16; + if (Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_get (insn) == 57 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 17) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_get (insn) == 57 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 16) + return OPCODE_IVP_SLLINX16; + if (Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_get (insn) == 58 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 17) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_get (insn) == 58 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 16) + return OPCODE_IVP_SLSINX16; + if (Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_get (insn) == 59 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 16) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 12 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 12 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 12 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 12 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 13 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 13 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 13 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 13 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 16 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 16 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 16 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 17 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 18 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_MINNX16T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 20 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 20 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULANX16PACKQT; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 20 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULANX16PACKPT; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 20 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 21 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULANX16PACKLT; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 21 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 31) + return OPCODE_IVP_MINNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 26) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 13) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 14) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 28) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 27) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 29) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 24) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 22) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 26) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 30) + return OPCODE_IVP_MULANX16PACKQ; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 31) + return OPCODE_IVP_MULSNX16PACKL; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 27) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULANX16PACKP; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULNX16PACKQ; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 21) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 24) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 25) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 20) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 23) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 26) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 29) + return OPCODE_IVP_MULANX16PACKL; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 31) + return OPCODE_IVP_MULSNX16PACKQ; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 30) + return OPCODE_IVP_MULNX16PACKP; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULSNX16PACKP; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULNX16PACKL; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 24) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 21) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 25) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 20) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 22) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 23) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 13) + return OPCODE_IVP_REPNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_11_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_LENX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 18 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_EQNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 20 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 18 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 18 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 20 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 18 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 13) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_11_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 18 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 18 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 18 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 18 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_DIVNX16Q_4STEP0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_DIVNX16SQ_4STEP0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_DIVNX16S_4STEP0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_DIVNX16U_4STEP0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_DIVN_2X32X16S_4STEP0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_DIVN_2X32X16U_4STEP0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 13 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULI2NX8X16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 13 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULAI2NX8X16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 13 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSI2NX8X16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 13 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSAI2NX8X16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 24 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT24U2NX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_CVT24S2NX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT24UNX32L; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT24UNX32H; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT48UNX32; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT48SNX32; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT48UN_2X64L; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT48UN_2X64H; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT96UN_2X64; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUU2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUUA2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUS2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSA2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULANX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 24 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUUANX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSANX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MUL2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULA2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADDW2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_ADDWA2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_ADDWS2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_ADDWU2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_ADDWUA2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADDWUS2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULSNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUSNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSSNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULSUN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULSUN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUUHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULSUHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULAN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUUAN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSAN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSUAN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULAHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUUAHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSAHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSUAHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULAN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUUAN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 24 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSAN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULSUAN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULSHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUSHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSSHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULSUSHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUSN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSSN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULSUSN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUSN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 24 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUSSN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULSUSN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULPN16XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULPAN16XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUSPN16XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUSPAN16XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULP2N8XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULPA2N8XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSP2N8XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUSPA2N8XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL4T2N8XR8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MUL4TA2N8XR8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUS4T2N8XR8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUS4TA2N8XR8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_ADDWNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_ADDWANX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_ADDWSNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADDWUNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADDWUANX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADDWUSNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWANX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWUNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWUANX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_SUBW2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 24 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWA2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWU2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWUA2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 12) + return OPCODE_ADDI; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_10_Slot_f2_s2_mul_get (insn) == 416 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT24U32; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_10_Slot_f2_s2_mul_get (insn) == 419 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT48UNX32L; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_10_Slot_f2_s2_mul_get (insn) == 417 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT48SNX32L; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_10_Slot_f2_s2_mul_get (insn) == 418 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT48U64; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_10_Slot_f2_s2_mul_get (insn) == 420 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT96U64; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULI2NR8X16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULAI2NR8X16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSI2NR8X16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSAI2NR8X16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_7_Slot_f2_s2_mul_get (insn) == 3376 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MOVWW; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_DIVN_2X32X16S_4STEP; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_DIVN_2X32X16S_4STEPN; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_DIVN_2X32X16U_4STEP; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_DIVN_2X32X16U_4STEPN; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_DIVNX16S_4STEP; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_DIVNX16S_4STEPN; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_DIVNX16U_4STEP; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_DIVNX16U_4STEPN; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 17 && + Field_fld_f2_s2_mul_14_5_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSA2N8XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 17 && + Field_fld_f2_s2_mul_14_5_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUS2N8XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 17 && + Field_fld_f2_s2_mul_14_5_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULA2N8XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 17 && + Field_fld_f2_s2_mul_14_5_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL2N8XR16; + if (Field_fld_f2_s2_mul_30_6_Slot_f2_s2_mul_get (insn) == 498274 && + Field_fld_f2_s2_mul_5_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_f2_s3_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_get (insn) == 810 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_EXTRVRN_2X32; + if (Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_get (insn) == 811 && + Field_fld_f2_s3_alu_9_7_Slot_f2_s3_alu_get (insn) == 4 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_INJBI2NX8; + if (Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_get (insn) == 1311 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_get (insn) == 13) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_get (insn) == 1343 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_get (insn) == 13) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_get (insn) == 1375 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_get (insn) == 13) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_get (insn) == 1407 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_get (insn) == 13) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_get (insn) == 1439 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_get (insn) == 13) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_f2_s3_alu_30_18_Slot_f2_s3_alu_get (insn) == 100 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 24 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 26 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 26 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 26 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 26 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 26 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 27 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 27 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 27 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_MINNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 27 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 27 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 27 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 27 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 28 && + Field_fld_f2_s3_alu_14_14_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLLINX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 28 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_SLSNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 28 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_SRSNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 28 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRAN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 28 && + Field_fld_f2_s3_alu_14_14_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ROTRINX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 29 && + Field_fld_f2_s3_alu_14_14_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLSINX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 29 && + Field_fld_f2_s3_alu_14_14_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 29 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRLIN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 29 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_SLSN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 29 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_SRSN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 30 && + Field_fld_f2_s3_alu_14_14_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 30 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRLNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 30 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRAIN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 30 && + Field_fld_f2_s3_alu_14_13_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ROTRI2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 30 && + Field_fld_f2_s3_alu_14_13_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLLI2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 114 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_MOVVV; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRANX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 122 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 118 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRLN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 82 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 94 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_14_13_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_14_13_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 86 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 102 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 32) + return OPCODE_IVP_SEL2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 33) + return OPCODE_IVP_SELNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 34) + return OPCODE_IVP_SELN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 35 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 35 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 35 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 35 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 36 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 36 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_MINNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 37 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 37 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 38 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 38 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 39 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 39 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 40 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 837) + return OPCODE_IVP_RADDNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 40 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 853) + return OPCODE_IVP_RADDN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 40 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_ROTRNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 40 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 40 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 885) + return OPCODE_IVP_RADDU2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 40 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 869) + return OPCODE_IVP_RADDSNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 40 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 40 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 41 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 41 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 853) + return OPCODE_IVP_RMAXNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 41 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 885) + return OPCODE_IVP_RMAXUNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 41 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 41 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 41 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 869) + return OPCODE_IVP_RMAXN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 41 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_ROTRN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 41 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 837) + return OPCODE_IVP_RADDUNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 41 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 42 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLANX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 42 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 42 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 42 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 853) + return OPCODE_IVP_RMINNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 42 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 885) + return OPCODE_IVP_RMINUNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 42 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 869) + return OPCODE_IVP_RMINN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 42 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 837) + return OPCODE_IVP_RMAXUN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 42 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 43 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLAN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 43 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 837) + return OPCODE_IVP_RMINUN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 43 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 43 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 43 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 44 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 44 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLLIN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 44 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 44 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 45 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLLNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 45 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 45 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 45 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 45 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 46 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 46 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 46 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLLN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 46 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 46 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 47 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLSIN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 47 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_ROTRIN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 47 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 47 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 47 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 884) + return OPCODE_IVP_RADD2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 47 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 17 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 17 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_NSANX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 21 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_NSAUNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 17 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 16) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 28) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_10_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_SHFLNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_10_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_SHFLN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 17 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 17 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_NSAN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 21 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_NSAUN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_10_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_SHFL2NX8; + if (Field_fld_f2_s3_alu_30_22_Slot_f2_s3_alu_get (insn) == 10 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SHFL2NX8I; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_SELNX16T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_SELN_2X32T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_9_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8I; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_2_Slot_f2_s3_alu_get (insn) == 200) + return OPCODE_IVP_REPNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_2_Slot_f2_s3_alu_get (insn) == 204) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_3_Slot_f2_s3_alu_get (insn) == 96) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_3_Slot_f2_s3_alu_get (insn) == 98) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_1_Slot_f2_s3_alu_get (insn) == 402) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_1_Slot_f2_s3_alu_get (insn) == 410) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_14_Slot_f2_s3_alu_get (insn) == 62 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 652) + return OPCODE_IVP_MOVBVBR; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 20 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_LTNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 22 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_LENX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 21 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_EQNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 22 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 23 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 23 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 835) + return OPCODE_IVP_RBMINNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 866) + return OPCODE_IVP_RBMAXNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 849) + return OPCODE_IVP_RADDNX16T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 867) + return OPCODE_IVP_RMAXNX16T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 836) + return OPCODE_IVP_RMINNX16T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 883) + return OPCODE_IVP_RMAXUNX16T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 852) + return OPCODE_IVP_RMINUNX16T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 21 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_2_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 851) + return OPCODE_IVP_RBMINUNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 882) + return OPCODE_IVP_RBMAXUNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 23 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 23 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 21 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 21 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 22 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 22 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 865) + return OPCODE_IVP_RADDN_2X32T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 21 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 23 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 22 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 23 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 20 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 22 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_9_7_Slot_f2_s3_alu_get (insn) == 4 && + Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_get (insn) == 12) + return OPCODE_IVP_EXTBI2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 833) + return OPCODE_IVP_RADD2NX8T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 850) + return OPCODE_IVP_RADDUNX16T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 834) + return OPCODE_IVP_RADDU2NX8T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 30 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 881) + return OPCODE_IVP_RADDSNX16T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 20 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_3_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_7_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 11 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_NOTB; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 10 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_MB; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 9 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 8 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 12 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_NOTB1; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 13 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_RORB2N; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 14 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_RANDBN; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_RORBN; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 15 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f2_s3_alu_30_6_Slot_f2_s3_alu_get (insn) == 917504 && + Field_fld_f2_s3_alu_5_0_Slot_f2_s3_alu_get (insn) == 49) + return OPCODE_NOP; + if (Field_fld_f2_s3_alu_30_8_Slot_f2_s3_alu_get (insn) == 229380) + return OPCODE_MOV_N; + if (Field_fld_f2_s3_alu_30_8_Slot_f2_s3_alu_get (insn) == 233476 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_MOVBRBV; + return XTENSA_UNDEFINED; +} + +static int +Slot_f3_s0_ldst_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f3_s0_ldst_25_1_Slot_f3_s0_ldst_get (insn) == 4296040 && + Field_fld_f3_s0_ldst_0_0_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SCATTERW; + if (Field_fld_f3_s0_ldst_25_1_Slot_f3_s0_ldst_get (insn) == 4300136 && + Field_fld_f3_s0_ldst_0_0_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_f3_s0_ldst_25_11_Slot_f3_s0_ldst_get (insn) == 5027) + return OPCODE_IVP_GATHERANX16; + if (Field_fld_f3_s0_ldst_25_11_Slot_f3_s0_ldst_get (insn) == 5031) + return OPCODE_IVP_GATHERANX8U; + if (Field_fld_f3_s0_ldst_25_11_Slot_f3_s0_ldst_get (insn) == 5035) + return OPCODE_IVP_GATHERAN_2X32; + if (Field_fld_f3_s0_ldst_25_11_Slot_f3_s0_ldst_get (insn) == 5652 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 5) + return OPCODE_IVP_MOVGATHERD; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2561) + return OPCODE_XOR; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2565) + return OPCODE_CLAMPS; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2569) + return OPCODE_SEXT; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2573) + return OPCODE_SRLI; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2766) + return OPCODE_ADD; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2767) + return OPCODE_ADDX2; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2770) + return OPCODE_ADDX4; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2771) + return OPCODE_ADDX8; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2774) + return OPCODE_AND; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2775) + return OPCODE_MAX; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2778) + return OPCODE_MAXU; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2779) + return OPCODE_MIN; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2782) + return OPCODE_MINU; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2783) + return OPCODE_MOVEQZ; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2786) + return OPCODE_MOVGEZ; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2787) + return OPCODE_MOVLTZ; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2790) + return OPCODE_MOVNEZ; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2791) + return OPCODE_MUL16S; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2794) + return OPCODE_MUL16U; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2795) + return OPCODE_MULL; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2798) + return OPCODE_MULSH; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2799) + return OPCODE_MULUH; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2802) + return OPCODE_OR; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2803) + return OPCODE_SALT; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2806) + return OPCODE_SALTU; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2807) + return OPCODE_SRC; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2810) + return OPCODE_SUB; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2811) + return OPCODE_SUBX2; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2814) + return OPCODE_SUBX4; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2815) + return OPCODE_SUBX8; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2824 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 5) + return OPCODE_SLL; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2828 && + Field_fld_f3_s0_ldst_3_0_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2828 && + Field_fld_f3_s0_ldst_3_0_Slot_f3_s0_ldst_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2828 && + Field_fld_f3_s0_ldst_3_0_Slot_f3_s0_ldst_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2828 && + Field_fld_f3_s0_ldst_3_0_Slot_f3_s0_ldst_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1252) + return OPCODE_IVP_LS2NX8_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1253) + return OPCODE_IVP_LS2NX8_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1254) + return OPCODE_IVP_LSNX16_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1255) + return OPCODE_IVP_LSNX16_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1264) + return OPCODE_IVP_LSNX8S_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1265) + return OPCODE_IVP_LSNX8S_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1266) + return OPCODE_IVP_LSN_2X16S_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1267) + return OPCODE_IVP_LSN_2X16S_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1268) + return OPCODE_IVP_LSN_2X32_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1269) + return OPCODE_IVP_LSN_2X32_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1270) + return OPCODE_IVP_LSR2NX8_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1271) + return OPCODE_IVP_LSR2NX8_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1272) + return OPCODE_IVP_LSRNX16_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1273) + return OPCODE_IVP_LSRNX16_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1274) + return OPCODE_IVP_LSRN_2X32_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1275) + return OPCODE_IVP_LSRN_2X32_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1276) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1277) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1278) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1279) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1281) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1283) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1285) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1287) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1289) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1291) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1293) + return OPCODE_IVP_SS2NX8_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1295) + return OPCODE_IVP_SS2NX8_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1297) + return OPCODE_IVP_SSNX16_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1299) + return OPCODE_IVP_SSNX16_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1301) + return OPCODE_IVP_SSNX8S_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1303) + return OPCODE_IVP_SSNX8S_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1305) + return OPCODE_IVP_SSN_2X16S_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1307) + return OPCODE_IVP_SSN_2X16S_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1309) + return OPCODE_IVP_SSN_2X32_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1311) + return OPCODE_IVP_SSN_2X32_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1313) + return OPCODE_IVP_SV2NX8_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1315) + return OPCODE_IVP_SV2NX8_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1317) + return OPCODE_IVP_SVNX8S_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1319) + return OPCODE_IVP_SVNX8S_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1321) + return OPCODE_IVP_SVNX8U_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1323) + return OPCODE_IVP_SVNX8U_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1325) + return OPCODE_IVP_SVN_2X16S_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1327) + return OPCODE_IVP_SVN_2X16S_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1329) + return OPCODE_IVP_SVN_2X16U_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1331) + return OPCODE_IVP_SVN_2X16U_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1333) + return OPCODE_SLLI; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1335) + return OPCODE_IVP_LS2NX8_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1337) + return OPCODE_IVP_LSNX16_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1339) + return OPCODE_IVP_LSNX8S_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1341) + return OPCODE_IVP_LSN_2X16S_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1343) + return OPCODE_IVP_LSN_2X32_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1345) + return OPCODE_IVP_LSR2NX8_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1347) + return OPCODE_IVP_LSRNX16_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1349) + return OPCODE_IVP_LSRN_2X32_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1351) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1353) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1355) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1357) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1359) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1361) + return OPCODE_IVP_SS2NX8_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1363) + return OPCODE_IVP_SSNX16_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1365) + return OPCODE_IVP_SSNX8S_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1367) + return OPCODE_IVP_SSN_2X16S_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1369) + return OPCODE_IVP_SSN_2X32_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1371) + return OPCODE_IVP_SV2NX8_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1373) + return OPCODE_IVP_SVNX8S_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1375) + return OPCODE_IVP_SVNX8U_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1377) + return OPCODE_IVP_SVN_2X16S_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1379) + return OPCODE_IVP_SVN_2X16U_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1381) + return OPCODE_SRAI; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 514 && + Field_fld_f3_s0_ldst_7_7_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 517 && + Field_fld_f3_s0_ldst_7_7_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 520 && + Field_fld_f3_s0_ldst_7_7_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 521 && + Field_fld_f3_s0_ldst_7_7_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 522 && + Field_fld_f3_s0_ldst_7_5_Slot_f3_s0_ldst_get (insn) == 6) + return OPCODE_IVP_SHFL2NX8I_S0; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 523 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 12) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 523 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 15) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 523 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 13) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 524 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 15) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 525 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 14) + return OPCODE_IVP_MOVVV; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 525 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 15) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 526 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 14) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 527 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 14) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 624) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 625) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 706 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 706 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 0) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 252) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 253) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 254) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 255) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 261 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 9) + return OPCODE_IVP_SANX8U_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 261 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 8) + return OPCODE_IVP_SANX8S_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 261 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 11) + return OPCODE_IVP_SAN_2X16U_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 261 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 10) + return OPCODE_IVP_SAN_2X16S_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 262 && + Field_fld_f3_s0_ldst_12_4_Slot_f3_s0_ldst_get (insn) == 269) + return OPCODE_IVP_LA_PP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 262 && + Field_fld_f3_s0_ldst_12_4_Slot_f3_s0_ldst_get (insn) == 285) + return OPCODE_IVP_SAPOS_FP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 262 && + Field_fld_f3_s0_ldst_12_11_Slot_f3_s0_ldst_get (insn) == 3 && + Field_fld_f3_s0_ldst_8_0_Slot_f3_s0_ldst_get (insn) == 208) + return OPCODE_IVP_MALIGN; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 262 && + Field_fld_f3_s0_ldst_12_0_Slot_f3_s0_ldst_get (insn) == 6353) + return OPCODE_IVP_ZALIGN; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 262 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 9) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 262 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 10) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 262 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 11) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 263 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 11) + return OPCODE_IVP_SA2NX8_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 263 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 9) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 263 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 10) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 288) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 289) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 290) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 291) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 292) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 293) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 294) + return OPCODE_IVP_SAV2NX8_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 295) + return OPCODE_IVP_SAVNX8S_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 296) + return OPCODE_IVP_SAVNX8U_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 297) + return OPCODE_IVP_SAVN_2X16S_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 298) + return OPCODE_IVP_SAVN_2X16U_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 299) + return OPCODE_IVP_LS2NX8_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 300) + return OPCODE_IVP_LSNX16_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 301) + return OPCODE_IVP_LSNX8S_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 302) + return OPCODE_IVP_LSN_2X16S_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 303) + return OPCODE_IVP_LSR2NX8_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 304) + return OPCODE_IVP_LSRNX16_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 305) + return OPCODE_IVP_LSRN_2X32_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 306) + return OPCODE_IVP_SS2NX8_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 307) + return OPCODE_IVP_SSNX16_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 308) + return OPCODE_IVP_SSNX8S_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 309) + return OPCODE_IVP_SSN_2X16S_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 315 && + Field_fld_f3_s0_ldst_12_8_Slot_f3_s0_ldst_get (insn) == 24) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 315 && + Field_fld_f3_s0_ldst_12_8_Slot_f3_s0_ldst_get (insn) == 25) + return OPCODE_IVP_SALIGN_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 86) + return OPCODE_ADDI; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 87) + return OPCODE_ADDMI; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 88) + return OPCODE_IVP_LV2NX8T_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 89) + return OPCODE_IVP_LV2NX8T_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 90) + return OPCODE_IVP_LVNX8ST_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 91) + return OPCODE_IVP_LVNX8ST_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 92) + return OPCODE_IVP_LVNX8UT_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 93) + return OPCODE_IVP_LVNX8UT_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 94) + return OPCODE_IVP_LVN_2X16ST_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 95) + return OPCODE_IVP_LVN_2X16ST_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 96) + return OPCODE_IVP_LVN_2X16UT_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 97) + return OPCODE_IVP_LVN_2X16UT_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 98) + return OPCODE_IVP_SV2NX8T_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 99) + return OPCODE_IVP_SV2NX8T_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 100) + return OPCODE_IVP_SVNX8ST_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 101) + return OPCODE_IVP_SVNX8ST_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 102) + return OPCODE_IVP_SVNX8UT_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 103) + return OPCODE_IVP_SVNX8UT_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 104) + return OPCODE_IVP_SVN_2X16ST_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 105) + return OPCODE_IVP_SVN_2X16ST_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 106) + return OPCODE_IVP_SVN_2X16UT_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 107) + return OPCODE_IVP_SVN_2X16UT_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 108) + return OPCODE_L16SI; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 109) + return OPCODE_L16UI; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 110) + return OPCODE_L32I; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 111) + return OPCODE_L8UI; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 112) + return OPCODE_S16I; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 113) + return OPCODE_S32I; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 114) + return OPCODE_S8I; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 115) + return OPCODE_IVP_LV2NX8T_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 116) + return OPCODE_IVP_LVNX8ST_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 117) + return OPCODE_IVP_LVNX8UT_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 118) + return OPCODE_IVP_LVN_2X16ST_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 119) + return OPCODE_IVP_LVN_2X16UT_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 120) + return OPCODE_IVP_SV2NX8T_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 121) + return OPCODE_IVP_SVNX8ST_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 122) + return OPCODE_IVP_SVNX8UT_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 123) + return OPCODE_IVP_SVN_2X16ST_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 124) + return OPCODE_IVP_SVN_2X16UT_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 125) + return OPCODE_MOVI; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 131 && + Field_fld_f3_s0_ldst_12_12_Slot_f3_s0_ldst_get (insn) == 0 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 13) + return OPCODE_IVP_SBN_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 131 && + Field_fld_f3_s0_ldst_12_12_Slot_f3_s0_ldst_get (insn) == 1 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 12) + return OPCODE_IVP_SBN_2_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 131 && + Field_fld_f3_s0_ldst_12_12_Slot_f3_s0_ldst_get (insn) == 0 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 12) + return OPCODE_IVP_SB2N_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 131 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 8) + return OPCODE_LOOPNEZ; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 140 && + Field_fld_f3_s0_ldst_7_5_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SB2N_I; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 141 && + Field_fld_f3_s0_ldst_7_5_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SBN_2_I; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 142 && + Field_fld_f3_s0_ldst_7_5_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SBN_I; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 143 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 2) + return OPCODE_LOOP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 143 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 3) + return OPCODE_LOOPGTZ; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 157 && + Field_fld_f3_s0_ldst_12_11_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_GATHERANX8UT; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 157 && + Field_fld_f3_s0_ldst_12_11_Slot_f3_s0_ldst_get (insn) == 0) + return OPCODE_IVP_GATHERANX16T; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 157 && + Field_fld_f3_s0_ldst_12_11_Slot_f3_s0_ldst_get (insn) == 2) + return OPCODE_IVP_GATHERAN_2X32T; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 30) + return OPCODE_IVP_LSN_2X32_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 31) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 32) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 33) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 34) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 35) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 36) + return OPCODE_IVP_SSN_2X32_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 37) + return OPCODE_IVP_SV2NX8_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 38) + return OPCODE_IVP_SVNX8S_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 39) + return OPCODE_IVP_SVNX8U_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 40) + return OPCODE_IVP_SVN_2X16S_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 41) + return OPCODE_IVP_SVN_2X16U_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 42) + return OPCODE_EXTUI; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 4) + return OPCODE_IVP_LV2NX8T_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 5) + return OPCODE_IVP_LVNX8ST_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 6) + return OPCODE_IVP_LVNX8UT_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 7) + return OPCODE_IVP_LVN_2X16ST_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 8) + return OPCODE_IVP_LVN_2X16UT_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 9) + return OPCODE_IVP_SV2NX8T_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 10) + return OPCODE_IVP_SVNX8ST_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 11) + return OPCODE_IVP_SVNX8UT_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 12) + return OPCODE_IVP_SVN_2X16ST_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 13) + return OPCODE_IVP_SVN_2X16UT_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 14) + return OPCODE_J; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 34 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 2) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 34 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 42 && + Field_fld_f3_s0_ldst_13_9_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 44 && + Field_fld_f3_s0_ldst_15_15_Slot_f3_s0_ldst_get (insn) == 0 && + Field_fld_f3_s0_ldst_12_8_Slot_f3_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 44 && + Field_fld_f3_s0_ldst_15_15_Slot_f3_s0_ldst_get (insn) == 0 && + Field_fld_f3_s0_ldst_12_8_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SALIGN_I; + if (Field_fld_f3_s0_ldst_25_19_Slot_f3_s0_ldst_get (insn) == 16 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 2) + return OPCODE_IVP_REPNX16; + if (Field_fld_f3_s0_ldst_25_19_Slot_f3_s0_ldst_get (insn) == 16 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f3_s0_ldst_25_19_Slot_f3_s0_ldst_get (insn) == 20 && + Field_fld_f3_s0_ldst_13_9_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f3_s0_ldst_25_20_Slot_f3_s0_ldst_get (insn) == 0) + return OPCODE_CONST16; + if (Field_fld_f3_s0_ldst_25_20_Slot_f3_s0_ldst_get (insn) == 8 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 0) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f3_s0_ldst_25_20_Slot_f3_s0_ldst_get (insn) == 8 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f3_s0_ldst_25_20_Slot_f3_s0_ldst_get (insn) == 10 && + Field_fld_f3_s0_ldst_13_9_Slot_f3_s0_ldst_get (insn) == 0) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f3_s0_ldst_25_4_Slot_f3_s0_ldst_get (insn) == 723621) + return OPCODE_SSA8L; + if (Field_fld_f3_s0_ldst_25_4_Slot_f3_s0_ldst_get (insn) == 723637) + return OPCODE_SSL; + if (Field_fld_f3_s0_ldst_25_4_Slot_f3_s0_ldst_get (insn) == 723653) + return OPCODE_SSR; + if (Field_fld_f3_s0_ldst_25_8_Slot_f3_s0_ldst_get (insn) == 40316) + return OPCODE_NSA; + if (Field_fld_f3_s0_ldst_25_8_Slot_f3_s0_ldst_get (insn) == 40317) + return OPCODE_NSAU; + if (Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_get (insn) == 20156) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_get (insn) == 20173) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_get (insn) == 20189) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_get (insn) == 20205) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_get (insn) == 20221) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_get (insn) == 22612 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 5) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_f3_s3_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f3_s3_alu_28_12_Slot_f3_s3_alu_get (insn) == 38924 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_EXTBI2NX8; + if (Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_get (insn) == 19457) + return OPCODE_IVP_EXTRVRN_2X32; + if (Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_get (insn) == 19463 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 8) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_get (insn) == 19463 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 11) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_get (insn) == 19463 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 9) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_get (insn) == 19463 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 12) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_get (insn) == 19463 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 10) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9236 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LTNX16; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9237 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9238 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9239 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9268 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9269 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9270 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9271 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9729 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9730 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9761 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9793 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LENX16; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9825 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9857 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9889 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9921 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9921 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9953 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_EQNX16; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9953 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 264) + return OPCODE_IVP_COUNTEQ4NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 265) + return OPCODE_IVP_COUNTEQZ4NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 266) + return OPCODE_IVP_COUNTLE4NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 267) + return OPCODE_IVP_COUNTLEZ4NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 268 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 268 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 269 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 269 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 270 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 270 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 271 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 271 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 280 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 13) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 280 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 15) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 280 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 11) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 281 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 14) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 281 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 11) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 281 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 13) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 281 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 15) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 282 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 11) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 282 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 15) + return OPCODE_IVP_MINNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 282 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 12) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 283 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 15) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 283 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 11) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 283 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 13) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 284 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 12) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 284 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 14) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 284 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 11) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 284 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 13) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 284 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 15) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 285 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 11) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 285 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 13) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 285 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 15) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 285 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 14) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 285 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 12) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 286 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 14) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 286 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 13) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 286 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 12) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 286 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 11) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 287 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 11) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 288 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 289 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 290 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 291 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 292 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 293 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 294 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 7) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 294 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 5) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 294 && + Field_fld_f3_s3_alu_3_2_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_SHFL2NX8I; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 294 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 6) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 294 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 295 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 295 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 4) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 295 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 2) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 295 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 5) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 295 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 295 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 295 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 3) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 296 && + Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_get (insn) == 1 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 14) + return OPCODE_IVP_SLLINX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 296 && + Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_get (insn) == 0 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 15) + return OPCODE_IVP_SLSINX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 296 && + Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_get (insn) == 1 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 15) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 296 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 8) + return OPCODE_IVP_SRSNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 296 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 9) + return OPCODE_IVP_SRSN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 296 && + Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_get (insn) == 0 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 14) + return OPCODE_IVP_ROTRINX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 457) + return OPCODE_IVP_MOVVV; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_get (insn) == 0 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 8) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 489) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 473) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 201) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 249) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_7_6_Slot_f3_s3_alu_get (insn) == 2 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 8) + return OPCODE_IVP_ROTRI2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_7_6_Slot_f3_s3_alu_get (insn) == 3 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 8) + return OPCODE_IVP_SLLI2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_7_6_Slot_f3_s3_alu_get (insn) == 0 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 9) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_7_6_Slot_f3_s3_alu_get (insn) == 1 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 9) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 217) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 409) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 298 && + Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_get (insn) == 4) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 298 && + Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_get (insn) == 6) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 298 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 2 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_RBMINNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 298 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 0 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_RBMAXNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 298 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 3 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_RBMINUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 298 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 1 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_RBMAXUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 299 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 35) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 299 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 38) + return OPCODE_IVP_NSANX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 299 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 48) + return OPCODE_IVP_NSAUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 299 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 34) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 299 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 32) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 299 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 39) + return OPCODE_IVP_NSAN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 299 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 49) + return OPCODE_IVP_NSAUN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 301 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 7) + return OPCODE_IVP_ROTRIN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 302 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 5) + return OPCODE_IVP_SLLNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 302 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 2) + return OPCODE_IVP_SLANX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 302 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLLIN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 302 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLSIN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 302 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 6) + return OPCODE_IVP_SLLN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 302 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 3) + return OPCODE_IVP_SLAN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 302 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_ROTRNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 302 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_ROTRN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 303 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 6) + return OPCODE_IVP_SRLNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 303 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 3) + return OPCODE_IVP_SRANX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 303 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_SLSNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 303 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 2) + return OPCODE_IVP_SRAIN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 303 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 5) + return OPCODE_IVP_SRLIN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 303 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 7) + return OPCODE_IVP_SRLN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 303 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 4) + return OPCODE_IVP_SRAN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 303 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_SLSN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 312 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 20 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 312 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 21 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 312 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 23 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDU2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 312 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 22 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDSNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 313 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 21 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 313 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 23 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 313 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 22 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 313 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 20 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 314 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 21 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 314 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 23 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 314 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 22 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 314 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 20 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXUN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 315 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 20 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINUN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 319 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 19 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADD2NX8; + if (Field_fld_f3_s3_alu_28_20_Slot_f3_s3_alu_get (insn) == 148 && + Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_get (insn) == 4) + return OPCODE_IVP_REPNX16; + if (Field_fld_f3_s3_alu_28_20_Slot_f3_s3_alu_get (insn) == 148 && + Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_get (insn) == 6) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f3_s3_alu_28_20_Slot_f3_s3_alu_get (insn) == 154 && + Field_fld_f3_s3_alu_18_14_Slot_f3_s3_alu_get (insn) == 1 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f3_s3_alu_28_21_Slot_f3_s3_alu_get (insn) == 74 && + Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f3_s3_alu_28_21_Slot_f3_s3_alu_get (insn) == 74 && + Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_get (insn) == 2) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f3_s3_alu_28_21_Slot_f3_s3_alu_get (insn) == 76 && + Field_fld_f3_s3_alu_18_14_Slot_f3_s3_alu_get (insn) == 1 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 32) + return OPCODE_IVP_SEL2NX8I; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 34 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 34 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 34 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 12) + return OPCODE_IVP_MINNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 34 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 9) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 34 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 15) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 34 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 3) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 34 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 2) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 34 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 35 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 35 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 2) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 35 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 4) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 35 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 3) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 35 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_7_Slot_f3_s3_alu_get (insn) == 512 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8215) + return OPCODE_IVP_NOTB; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8213) + return OPCODE_IVP_MB; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_8_Slot_f3_s3_alu_get (insn) == 257 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 8) + return OPCODE_IVP_MOVBRBV; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8211) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8209) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8217) + return OPCODE_IVP_NOTB1; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8219) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8257) + return OPCODE_IVP_RORB2N; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8221) + return OPCODE_IVP_RANDBN; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8259) + return OPCODE_IVP_RORBN; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8223) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8261) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_13_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 9 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 14 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 16 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 15 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXUNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 17 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINUNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 257) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 305) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 10 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDN_2X32T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_18_12_Slot_f3_s3_alu_get (insn) == 3 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_INJBI2NX8; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 8 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADD2NX8T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 13 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDUNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 12 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDU2NX8T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 11 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDSNX16T; + if (Field_fld_f3_s3_alu_28_25_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_COUNTEQM4NX8; + if (Field_fld_f3_s3_alu_28_25_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_COUNTEQMZ4NX8; + if (Field_fld_f3_s3_alu_28_25_Slot_f3_s3_alu_get (insn) == 2) + return OPCODE_IVP_COUNTLEM4NX8; + if (Field_fld_f3_s3_alu_28_25_Slot_f3_s3_alu_get (insn) == 3) + return OPCODE_IVP_COUNTLEMZ4NX8; + if (Field_fld_f3_s3_alu_28_4_Slot_f3_s3_alu_get (insn) == 9965603 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 8) + return OPCODE_NOP; + if (Field_fld_f3_s3_alu_28_8_Slot_f3_s3_alu_get (insn) == 624672) + return OPCODE_MOV_N; + if (Field_fld_f3_s3_alu_28_9_Slot_f3_s3_alu_get (insn) == 312337 && + Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_get (insn) == 0 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_MOVBVBR; + return XTENSA_UNDEFINED; +} + +static int +Slot_f4_s3_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_get (insn) == 57351) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_get (insn) == 57479) + return OPCODE_IVP_EXTRVRN_2X32; + if (Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_get (insn) == 57607 && + Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_get (insn) == 57607 && + Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_get (insn) == 57607 && + Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_get (insn) == 57735 && + Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_get (insn) == 57735 && + Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f4_s3_alu_31_19_Slot_f4_s3_alu_get (insn) == 972 && + Field_fld_f4_s3_alu_14_6_Slot_f4_s3_alu_get (insn) == 440 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 7) + return OPCODE_IVP_MOVBVBR; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 448 && + Field_fld_f4_s3_alu_14_14_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_COUNTEQ4NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 449 && + Field_fld_f4_s3_alu_14_14_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_COUNTLE4NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 449 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 23) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 449 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 22) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 451 && + Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 451 && + Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 480 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 29) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 480 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 26) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 480 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 28) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 480 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 25) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 480 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 27) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 480 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 480 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 480 && + Field_fld_f4_s3_alu_14_14_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_COUNTEQZ4NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 480 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 24) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31) + return OPCODE_IVP_MINNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 25) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 28) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 24) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 27) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 26) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 29) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 23) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 22) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_14_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_COUNTLEZ4NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 482 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 482 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 26) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 482 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 28) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 482 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 25) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 482 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 482 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 24) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 482 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 27) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 482 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 29) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 28) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 25) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 27) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 9 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RADDNX16T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 24) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 10 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RADDN_2X32T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 29) + return OPCODE_IVP_ROTRIN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30) + return OPCODE_IVP_ROTRNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31) + return OPCODE_IVP_ROTRN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 26) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 8 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RADD2NX8T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 11 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RADDSNX16T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 484 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 27) + return OPCODE_IVP_SLLNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 484 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 24) + return OPCODE_IVP_SLANX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 484 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30) + return OPCODE_IVP_SLSNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 484 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 26) + return OPCODE_IVP_SLLIN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 484 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 29) + return OPCODE_IVP_SLSIN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 484 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 28) + return OPCODE_IVP_SLLN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 484 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 25) + return OPCODE_IVP_SLAN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 484 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31) + return OPCODE_IVP_SLSN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 485 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 28) + return OPCODE_IVP_SRLNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 485 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 25) + return OPCODE_IVP_SRANX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 485 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30) + return OPCODE_IVP_SRSNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 485 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 24) + return OPCODE_IVP_SRAIN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 485 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 27) + return OPCODE_IVP_SRLIN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 485 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 29) + return OPCODE_IVP_SRLN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 485 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 26) + return OPCODE_IVP_SRAN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 485 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31) + return OPCODE_IVP_SRSN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 108 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 5) + return OPCODE_IVP_MOVVV; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 24 && + Field_fld_f4_s3_alu_3_3_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_SLLINX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 25 && + Field_fld_f4_s3_alu_3_3_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_SLSINX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 25 && + Field_fld_f4_s3_alu_3_3_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 26 && + Field_fld_f4_s3_alu_3_3_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 109 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 6) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 110 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 5) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 110 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 6) + return OPCODE_IVP_NSANX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 108 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 7) + return OPCODE_IVP_NSAUNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 5 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 6 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 6 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMINNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMAXUNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMINUNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 14 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 4) + return OPCODE_IVP_RBMINNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 14 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_RBMAXNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 108 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 6) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 14 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 6) + return OPCODE_IVP_RMAXNX16T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 15 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINNX16T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 14 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 7) + return OPCODE_IVP_RMAXUNX16T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 15 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMINUNX16T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 14 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 5) + return OPCODE_IVP_RBMINUNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 14 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_RBMAXUNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 109 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 5) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 6 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMINN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 5 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMAXUN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 5 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMINUN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 108 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 110 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 26 && + Field_fld_f4_s3_alu_3_2_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_ROTRI2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 24 && + Field_fld_f4_s3_alu_3_3_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_ROTRINX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 111 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 5) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 111 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 6) + return OPCODE_IVP_NSAN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 109 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 7) + return OPCODE_IVP_NSAUN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 26 && + Field_fld_f4_s3_alu_3_2_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_SLLI2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 27 && + Field_fld_f4_s3_alu_3_2_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 27 && + Field_fld_f4_s3_alu_3_2_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADD2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 5 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDUNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 14 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RADDUNX16T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDU2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 14 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDU2NX8T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDSNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 109 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 111 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_get (insn) == 56 && + Field_fld_f4_s3_alu_19_6_Slot_f4_s3_alu_get (insn) == 1411 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_NOTB; + if (Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_get (insn) == 56 && + Field_fld_f4_s3_alu_19_6_Slot_f4_s3_alu_get (insn) == 1410 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_MB; + if (Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_get (insn) == 56 && + Field_fld_f4_s3_alu_19_8_Slot_f4_s3_alu_get (insn) == 352 && + Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_MOVBRBV; + if (Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_get (insn) == 56 && + Field_fld_f4_s3_alu_19_6_Slot_f4_s3_alu_get (insn) == 1409 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_get (insn) == 56 && + Field_fld_f4_s3_alu_19_6_Slot_f4_s3_alu_get (insn) == 1408 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_get (insn) == 56 && + Field_fld_f4_s3_alu_19_6_Slot_f4_s3_alu_get (insn) == 1920 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_NOTB1; + if (Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_get (insn) == 56 && + Field_fld_f4_s3_alu_19_13_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_ADDI; + if (Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get (insn) == 8) + return OPCODE_IVP_COUNTEQM4NX8; + if (Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get (insn) == 9) + return OPCODE_IVP_COUNTEQMZ4NX8; + if (Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get (insn) == 10) + return OPCODE_IVP_COUNTLEM4NX8; + if (Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get (insn) == 11) + return OPCODE_IVP_COUNTLEMZ4NX8; + if (Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get (insn) == 12) + return OPCODE_IVP_DSELNX16; + if (Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get (insn) == 13 && + Field_fld_f4_s3_alu_14_14_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_DSEL2NX8I; + if (Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get (insn) == 13 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 4) + return OPCODE_IVP_DSEL2NX8I_H; + if (Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get (insn) == 13 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 5) + return OPCODE_IVP_SEL2NX8I; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_REPNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_21_Slot_f4_s3_alu_get (insn) == 1 && + Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_21_Slot_f4_s3_alu_get (insn) == 1 && + Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1060) + return OPCODE_IVP_LTNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1045) + return OPCODE_IVP_LENX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1293) + return OPCODE_IVP_EQNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1077) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1084) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1308) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 3 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 6 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 0 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 4) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 6 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_9_8_Slot_f4_s3_alu_get (insn) == 0 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 5 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 6 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_MINNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 5 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 6 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 3 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 1 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 4) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 6 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_9_8_Slot_f4_s3_alu_get (insn) == 1 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_13_Slot_f4_s3_alu_get (insn) == 518) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 5 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 3 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 6 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 5 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 3 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 0 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 5) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1309) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1052) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1292) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1069) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1076) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1300) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1068) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1053) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1044) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1085) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1061) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1301) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_18_Slot_f4_s3_alu_get (insn) == 17 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 0 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_INJBI2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_18_Slot_f4_s3_alu_get (insn) == 17 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 1 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTBI2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 1 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 10) + return OPCODE_IVP_SHFL2NX8I; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_21_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_19_13_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f4_s3_alu_31_28_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_DSELNX16T; + if (Field_fld_f4_s3_alu_31_7_Slot_f4_s3_alu_get (insn) == 3670976 && + Field_fld_f4_s3_alu_6_0_Slot_f4_s3_alu_get (insn) == 66) + return OPCODE_NOP; + if (Field_fld_f4_s3_alu_31_8_Slot_f4_s3_alu_get (insn) == 1851616) + return OPCODE_MOV_N; + return XTENSA_UNDEFINED; +} + +static int +Slot_f11_s3_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f11_s3_alu_25_1_Slot_f11_s3_alu_get (insn) == 7084145 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_NOP; + if (Field_fld_f11_s3_alu_25_11_Slot_f11_s3_alu_get (insn) == 6648 && + Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_get (insn) == 13) + return OPCODE_IVP_MOVBRBV; + if (Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_get (insn) == 1662 && + Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_get (insn) == 1662 && + Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_get (insn) == 7) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_get (insn) == 1662 && + Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_get (insn) == 3) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_get (insn) == 1662 && + Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_get (insn) == 9) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_get (insn) == 1662 && + Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_get (insn) == 5) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_get (insn) == 1684) + return OPCODE_IVP_EXTRVRN_2X32; + if (Field_fld_f11_s3_alu_25_14_Slot_f11_s3_alu_get (insn) == 830 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 1) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f11_s3_alu_25_14_Slot_f11_s3_alu_get (insn) == 838) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f11_s3_alu_25_14_Slot_f11_s3_alu_get (insn) == 839) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 354) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 355) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 356) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 357) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 358) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 359) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 360) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 361) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 362) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 363) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 364) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 365) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 366) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 367) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 368) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 369) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 370) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 371) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 372) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 373) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 374) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 375) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 376) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 377) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 378) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 379) + return OPCODE_IVP_MINNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 380) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 381) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 382) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 383) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 384) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 385) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 386) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 387) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 388) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 389) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 390) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 391) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 392) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 393) + return OPCODE_IVP_ROTRIN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 394) + return OPCODE_IVP_ROTRNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 395) + return OPCODE_IVP_ROTRN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 396) + return OPCODE_IVP_SLANX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 397) + return OPCODE_IVP_SLAN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 398) + return OPCODE_IVP_SLLIN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 399) + return OPCODE_IVP_SLLNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 400) + return OPCODE_IVP_SLLN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 401) + return OPCODE_IVP_SLSIN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 402) + return OPCODE_IVP_SLSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 403) + return OPCODE_IVP_SLSN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 404) + return OPCODE_IVP_SRAIN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 405) + return OPCODE_IVP_SRANX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 406) + return OPCODE_IVP_SRAN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 407) + return OPCODE_IVP_SRLIN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 408) + return OPCODE_IVP_SRLNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 409) + return OPCODE_IVP_SRLN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 410) + return OPCODE_IVP_SRSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 411) + return OPCODE_IVP_SRSN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 412) + return OPCODE_IVP_REPNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 413) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 414 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 1) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 416 && + Field_fld_f11_s3_alu_9_9_Slot_f11_s3_alu_get (insn) == 1) + return OPCODE_IVP_SLLINX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 416 && + Field_fld_f11_s3_alu_9_9_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_ROTRINX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 417 && + Field_fld_f11_s3_alu_9_9_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_SLSINX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 417 && + Field_fld_f11_s3_alu_9_9_Slot_f11_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 418 && + Field_fld_f11_s3_alu_9_9_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 418 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 2) + return OPCODE_IVP_ROTRI2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 418 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 3) + return OPCODE_IVP_SLLI2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 2) + return OPCODE_IVP_MOVVV; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 3 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 4) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 3) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 5) + return OPCODE_IVP_NSANX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 6) + return OPCODE_IVP_NSAUNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 4) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 3 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 2) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 1) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 3 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 3) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 3 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 5) + return OPCODE_IVP_NSAN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 3 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 6) + return OPCODE_IVP_NSAUN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 3 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 3 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 1) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 422 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 1 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 422 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 0 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXUNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 422 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINUNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 423 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 1 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 423 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 0 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXUN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 423 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINUN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 432 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 15 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADD2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 433 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 15 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 434 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 15 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 435 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 15 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 436 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 15 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDU2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 437 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 15 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDUNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 438 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 15 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 439 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 15 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXN_2X32; + if (Field_fld_f11_s3_alu_25_16_Slot_f11_s3_alu_get (insn) == 174) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f11_s3_alu_25_16_Slot_f11_s3_alu_get (insn) == 175) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f11_s3_alu_25_16_Slot_f11_s3_alu_get (insn) == 176) + return OPCODE_ADDI; + if (Field_fld_f11_s3_alu_25_16_Slot_f11_s3_alu_get (insn) == 207 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f11_s3_alu_25_17_Slot_f11_s3_alu_get (insn) == 86) + return OPCODE_IVP_SHFL2NX8I; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 16) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 17) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 18) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 19) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 20) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 21) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 22) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 23) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 24) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 25) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 26) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 27) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 28) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 29) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 30) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 31) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 32) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 33) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 34) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 35) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 36) + return OPCODE_IVP_MINNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 37) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 38) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 39) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 40) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 41) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 42) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 10) + return OPCODE_IVP_LTNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 4) + return OPCODE_IVP_LENX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 1) + return OPCODE_IVP_EQNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 16) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 13) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 7) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 9) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 3) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 15) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 12) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 6) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 11) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 5) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 2) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 17) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 14) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 8) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 4 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 14 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 5 && + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (insn) == 226) + return OPCODE_IVP_NOTB; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 5 && + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (insn) == 224) + return OPCODE_IVP_MB; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 8 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RBMINNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 6 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RBMAXNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 1 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 10 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 12 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 11 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXUNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 13 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINUNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 5 && + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (insn) == 228) + return OPCODE_IVP_NOTB1; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 9 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RBMINUNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 7 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RBMAXUNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDN_2X32T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_13_Slot_f11_s3_alu_get (insn) == 0 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 14 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTBI2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 0 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADD2NX8T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 5 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDUNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 4 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDU2NX8T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 3 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDSNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 5 && + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (insn) == 230) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 5 && + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (insn) == 236) + return OPCODE_IVP_RORB2N; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 5 && + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (insn) == 232) + return OPCODE_IVP_RANDBN; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 5 && + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (insn) == 238) + return OPCODE_IVP_RORBN; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 5 && + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (insn) == 234) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 6 && + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (insn) == 224) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 55 && + Field_fld_f11_s3_alu_14_8_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_MOVBVBR; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 55 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 0 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 55 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 1 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_f11_s3_alu_25_22_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8I; + if (Field_fld_f11_s3_alu_25_8_Slot_f11_s3_alu_get (insn) == 53920) + return OPCODE_MOV_N; + return XTENSA_UNDEFINED; +} + +static int +Slot_n0_s3_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8976) + return OPCODE_ADD; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8977) + return OPCODE_ADDX2; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8978) + return OPCODE_ADDX4; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8979) + return OPCODE_ADDX8; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8980) + return OPCODE_AND; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8981) + return OPCODE_OR; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8982) + return OPCODE_SUB; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8983) + return OPCODE_SUBX2; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8984) + return OPCODE_SUBX4; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8985) + return OPCODE_SUBX8; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8986) + return OPCODE_XOR; + if (Field_fld_n0_s3_alu_27_13_Slot_n0_s3_alu_get (insn) == 8004 && + Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVBRBV; + if (Field_fld_n0_s3_alu_27_15_Slot_n0_s3_alu_get (insn) == 1809 && + Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAV16; + if (Field_fld_n0_s3_alu_27_15_Slot_n0_s3_alu_get (insn) == 1841 && + Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAV32; + if (Field_fld_n0_s3_alu_27_15_Slot_n0_s3_alu_get (insn) == 1873 && + Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAV8; + if (Field_fld_n0_s3_alu_27_15_Slot_n0_s3_alu_get (insn) == 1905 && + Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_n0_s3_alu_27_15_Slot_n0_s3_alu_get (insn) == 1937 && + Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_n0_s3_alu_27_16_Slot_n0_s3_alu_get (insn) == 560) + return OPCODE_ADDI; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 32) + return OPCODE_IVP_SEL2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 33) + return OPCODE_IVP_SELNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 34) + return OPCODE_IVP_SELN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 36 && + Field_fld_n0_s3_alu_14_14_Slot_n0_s3_alu_get (insn) == 1 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 10) + return OPCODE_IVP_SLLINX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 36 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRSNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 36 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRAN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 36 && + Field_fld_n0_s3_alu_14_14_Slot_n0_s3_alu_get (insn) == 0 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 10) + return OPCODE_IVP_ROTRINX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 37 && + Field_fld_n0_s3_alu_14_14_Slot_n0_s3_alu_get (insn) == 0 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 10) + return OPCODE_IVP_SLSINX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 37 && + Field_fld_n0_s3_alu_14_14_Slot_n0_s3_alu_get (insn) == 1 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 10) + return OPCODE_IVP_SRAINX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 37 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRLIN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 37 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRSN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 38 && + Field_fld_n0_s3_alu_14_14_Slot_n0_s3_alu_get (insn) == 0 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 10) + return OPCODE_IVP_SRLINX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 38 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRLNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 38 && + Field_fld_n0_s3_alu_14_13_Slot_n0_s3_alu_get (insn) == 2 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 10) + return OPCODE_IVP_ROTRI2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 38 && + Field_fld_n0_s3_alu_14_13_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 10) + return OPCODE_IVP_SLLI2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 906) + return OPCODE_IVP_MOVVV; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 970) + return OPCODE_IVP_NEGNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 938) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRLN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 650) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 746) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_14_13_Slot_n0_s3_alu_get (insn) == 0 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 10) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_14_13_Slot_n0_s3_alu_get (insn) == 1 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 10) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 682) + return OPCODE_IVP_ABSNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 810) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 28) + return OPCODE_IVP_MINUNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 453) + return OPCODE_IVP_RMINNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 455) + return OPCODE_IVP_RMINUNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 23) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 31) + return OPCODE_IVP_SLLIN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 454) + return OPCODE_IVP_RMINN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 452) + return OPCODE_IVP_RMAXUN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 468) + return OPCODE_IVP_RMINUN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 29) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 21) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 20) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 41 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 31) + return OPCODE_IVP_SLLNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 41 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 22) + return OPCODE_IVP_MAXNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 41 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 29) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 41 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 20) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 41 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 28) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 41 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 21) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 42 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 29) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 42 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 20) + return OPCODE_IVP_ADDNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 42 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 28) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 42 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 31) + return OPCODE_IVP_SLLN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 42 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 21) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 43 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 23) + return OPCODE_IVP_MINNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 43 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 31) + return OPCODE_IVP_SLSIN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 43 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 30) + return OPCODE_IVP_ROTRIN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 43 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 20) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 43 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 22) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 43 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 28) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 43 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 439) + return OPCODE_IVP_RADD2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 43 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 21) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 44 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 31) + return OPCODE_IVP_SLSNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 44 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 438) + return OPCODE_IVP_RADDNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 44 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 20) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 44 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 439) + return OPCODE_IVP_RADDN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 44 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 28) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 44 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 30) + return OPCODE_IVP_ROTRNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 44 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 21) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 44 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 7) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 20) + return OPCODE_IVP_AND2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 28) + return OPCODE_IVP_OR2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 22) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 31) + return OPCODE_IVP_SLSN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 30) + return OPCODE_IVP_ROTRN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 23) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 7) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 439) + return OPCODE_IVP_RADDU2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 438) + return OPCODE_IVP_RADDSNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 21) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 46 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 30) + return OPCODE_IVP_SLANX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 46 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 22) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 46 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 439) + return OPCODE_IVP_RMAXNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 46 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 28) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 46 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 21) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 46 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 31) + return OPCODE_IVP_SRAIN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 46 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 438) + return OPCODE_IVP_RADDUNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 46 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 20) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 46 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 7) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 47 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 31) + return OPCODE_IVP_SRANX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 47 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 28) + return OPCODE_IVP_SUBNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 47 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 439) + return OPCODE_IVP_RMAXUNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 47 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 23) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 47 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 30) + return OPCODE_IVP_SLAN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 47 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 438) + return OPCODE_IVP_RMAXN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 47 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 22) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 47 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 7) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 47 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 20) + return OPCODE_IVP_AVGNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 120) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 113) + return OPCODE_IVP_NSANX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 98) + return OPCODE_IVP_NSAUNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 112) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_10_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SHFLNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_10_Slot_n0_s3_alu_get (insn) == 2) + return OPCODE_IVP_SHFLN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 96) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 121) + return OPCODE_IVP_NSAN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 106) + return OPCODE_IVP_NSAUN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_10_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SHFL2NX8; + if (Field_fld_n0_s3_alu_27_22_Slot_n0_s3_alu_get (insn) == 10 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 7) + return OPCODE_IVP_SHFL2NX8I; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SELNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 2) + return OPCODE_IVP_SELN_2X32T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 26) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 28) + return OPCODE_IVP_BMINNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 17) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 19) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 21) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 31) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 25) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 23) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 20) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 30) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 27) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 29) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 22) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 18) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 16) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_9_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8I; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 24) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_6_Slot_n0_s3_alu_get (insn) == 6 && + Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_get (insn) == 2) + return OPCODE_IVP_REPNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_6_Slot_n0_s3_alu_get (insn) == 6 && + Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SELSNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_7_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_REP2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_7_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 14 && + Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_get (insn) == 2) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 14 && + Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 407) + return OPCODE_IVP_RBMINNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 405) + return OPCODE_IVP_RBMAXNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 26) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 388) + return OPCODE_IVP_RADDNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 421) + return OPCODE_IVP_RMAXNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 423) + return OPCODE_IVP_RMINNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 422) + return OPCODE_IVP_RMAXUNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 436) + return OPCODE_IVP_RMINUNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 4) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 8) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 18) + return OPCODE_IVP_MINNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 11) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 25) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 6) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 420) + return OPCODE_IVP_RBMINUNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 406) + return OPCODE_IVP_RBMAXUNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 5) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 27) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 389) + return OPCODE_IVP_RADDN_2X32T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 499) + return OPCODE_IVP_RADD2NX8T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 404) + return OPCODE_IVP_RADDUNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 391) + return OPCODE_IVP_RADDU2NX8T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 390) + return OPCODE_IVP_RADDSNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_13_Slot_n0_s3_alu_get (insn) == 0 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 641) + return OPCODE_IVP_MB; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_12_Slot_n0_s3_alu_get (insn) == 0 && + Field_fld_n0_s3_alu_7_0_Slot_n0_s3_alu_get (insn) == 128) + return OPCODE_IVP_MOVBVBR; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 4 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_LTNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 2 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_LENX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 1 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 3) + return OPCODE_IVP_EQNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 6 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEQNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_LTUNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 2) + return OPCODE_IVP_LEUNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 136) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 232) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_13_Slot_n0_s3_alu_get (insn) == 0 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 385) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_13_Slot_n0_s3_alu_get (insn) == 0 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 129) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 1 && + Field_fld_n0_s3_alu_9_6_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 3) + return OPCODE_IVP_LT2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_LE2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 1 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 2) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 6 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 2 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 2) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 2 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 4 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 2 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 3) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 17 && + Field_fld_n0_s3_alu_9_3_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTBI2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 16 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 0 && + Field_fld_n0_s3_alu_9_7_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_n0_s3_alu_27_3_Slot_n0_s3_alu_get (insn) == 7340144 && + Field_fld_n0_s3_alu_2_0_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_f0_s1_ld_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f0_s1_ld_24_0_Slot_f0_s1_ld_get (insn) == 1853188) + return OPCODE_NOP; + if (Field_fld_f0_s1_ld_24_11_Slot_f0_s1_ld_get (insn) == 954 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 4) + return OPCODE_IVP_MOVAB1; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 449) + return OPCODE_SUBX8; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 451) + return OPCODE_SEXT; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 456) + return OPCODE_XOR; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 457) + return OPCODE_ADDX8; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 458) + return OPCODE_SRLI; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 459) + return OPCODE_IVP_ADDMOD16U; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 460 && + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get (insn) == 10) + return OPCODE_NEG; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 460 && + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get (insn) == 11) + return OPCODE_SRA; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 461 && + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get (insn) == 10) + return OPCODE_SRL; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 464) + return OPCODE_MUL16S; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 465) + return OPCODE_MOVEQZ; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 466) + return OPCODE_OR; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 467) + return OPCODE_MOVLTZ; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 472) + return OPCODE_SALTU; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 473) + return OPCODE_SUB; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 474) + return OPCODE_SUBX2; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 475) + return OPCODE_SUBX4; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 476 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 4) + return OPCODE_SLL; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 480) + return OPCODE_ADD; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 481) + return OPCODE_ADDX4; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 482) + return OPCODE_ADDX2; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 483) + return OPCODE_AND; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 488) + return OPCODE_MAX; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 489) + return OPCODE_MAXU; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 496) + return OPCODE_MUL16U; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 497) + return OPCODE_MOVGEZ; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 498) + return OPCODE_SALT; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 499) + return OPCODE_MOVNEZ; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 504) + return OPCODE_MIN; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 505) + return OPCODE_MINU; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 168) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 169) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 170) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 171) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 172) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 173) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 174) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 175) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 176) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 177) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 178) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 179) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 180) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 181) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 182) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 183) + return OPCODE_SRAI; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 184 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT32UNX48L; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 184 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 54) + return OPCODE_IVP_CVT64UN_2X96L; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 184 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 55) + return OPCODE_IVP_GATHERD2NX8_L; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 185 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT64S48; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 185 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 54) + return OPCODE_IVP_PACKHN_2X64W; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 185 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 55) + return OPCODE_IVP_GATHERDNX16; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 186 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT64SNX48HH; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 186 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 54) + return OPCODE_IVP_PACKL2NX24; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 186 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 55) + return OPCODE_IVP_GATHERDNX8S; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 187 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 222) + return OPCODE_IVP_SEQNX16; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 187 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT64SNX48HL; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 187 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 54) + return OPCODE_IVP_PACKL2NX24_1; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 187 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 221) + return OPCODE_IVP_SEQ2NX8; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 187 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 223) + return OPCODE_IVP_SEQN_2X32; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 188 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT64SNX48LH; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 188 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 54) + return OPCODE_IVP_PACKLNX48; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 189 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT64SNX48LL; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 189 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 54) + return OPCODE_IVP_PACKLN_2X96; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 190 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT64U96; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 190 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 54) + return OPCODE_IVP_PACKMNX48; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 191 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT64UN_2X96H; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 191 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 54) + return OPCODE_IVP_GATHERD2NX8_H; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 227 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVR2NX24; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 227 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVR2NX24_0; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 227 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVR2NX24_1; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 227 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNR2NX24; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 230 && + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get (insn) == 6) + return OPCODE_IVP_MOVVA16; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 230 && + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get (insn) == 4) + return OPCODE_IVP_MOVPA16; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 230 && + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get (insn) == 5) + return OPCODE_IVP_MOVQA16; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 230 && + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get (insn) == 7) + return OPCODE_IVP_MOVVA32; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 230 && + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get (insn) == 8) + return OPCODE_IVP_MOVVA8; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 230 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRU2NX24_1; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 235 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNR2NX24_0; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 235 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNR2NX24_1; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 235 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNRNX48_0; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 235 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNRNX48; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_6_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINX16; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 28) + return OPCODE_IVP_CVT32S2NX24LL; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 27) + return OPCODE_IVP_CVT32S2NX24LH; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 26) + return OPCODE_IVP_CVT32S2NX24HL; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 25) + return OPCODE_IVP_CVT32S2NX24HH; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 21) + return OPCODE_IVP_CVT16S2NX24L; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 20) + return OPCODE_IVP_CVT16S2NX24H; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 30) + return OPCODE_IVP_CVT32SNX48L; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 29) + return OPCODE_IVP_CVT32SNX48H; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 22) + return OPCODE_IVP_CVT16U2NX24H; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 31) + return OPCODE_IVP_CVT32UNX48H; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 23) + return OPCODE_IVP_CVT16U2NX24L; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 24) + return OPCODE_IVP_CVT32S24; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 243 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNX48; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 243 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNRN_2X64W; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 243 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNX48_0; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 243 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNRNX48_1; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 245 && + Field_fld_f0_s1_ld_7_7_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVPINT16; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 245 && + Field_fld_f0_s1_ld_7_7_Slot_f0_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVVINT16; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 251 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRU2NX24; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 251 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRU2NX24_0; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 251 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRN_2X64W; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 251 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNX48_1; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 253 && + Field_fld_f0_s1_ld_7_7_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVQINT16; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 253 && + Field_fld_f0_s1_ld_7_7_Slot_f0_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVVINT8; + if (Field_fld_f0_s1_ld_24_14_Slot_f0_s1_ld_get (insn) == 112 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_SLLI; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 14) + return OPCODE_ADDI; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 15) + return OPCODE_ADDMI; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 20) + return OPCODE_L32I; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 24) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 211) + return OPCODE_IVP_NOTB; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 2 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 15) + return OPCODE_IVP_ANDB; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 3 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 24) + return OPCODE_IVP_ORB; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 2 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 25) + return OPCODE_IVP_XORB; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 3 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 15) + return OPCODE_IVP_ANDNOTB; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 210) + return OPCODE_IVP_MB; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_get (insn) == 30) + return OPCODE_IVP_LTRN; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 3 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 25) + return OPCODE_IVP_LTRNI; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 0 && + Field_fld_f0_s1_ld_7_6_Slot_f0_s1_ld_get (insn) == 1) + return OPCODE_IVP_LBN_I; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 6) + return OPCODE_IVP_LBN_IP; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 2 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 24) + return OPCODE_IVP_JOINB; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_get (insn) == 46) + return OPCODE_IVP_LTRN_2; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 0 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 52) + return OPCODE_IVP_LTRN_2I; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_6_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_LBN_2_I; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 5) + return OPCODE_IVP_LBN_2_IP; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 209) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 208) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_get (insn) == 110) + return OPCODE_IVP_MOVBA1; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 2 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 208) + return OPCODE_IVP_NOTB1; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 0 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 24) + return OPCODE_IVP_ANDNOTB1; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 25) + return OPCODE_IVP_ORNOTB1; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 0 && + Field_fld_f0_s1_ld_7_6_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_LB2N_I; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 4) + return OPCODE_IVP_LB2N_IP; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_get (insn) == 14) + return OPCODE_IVP_LTR2N; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 14) + return OPCODE_IVP_LTR2NI; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 0 && + Field_fld_f0_s1_ld_7_5_Slot_f0_s1_ld_get (insn) == 5) + return OPCODE_IVP_SQZN; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_5_Slot_f0_s1_ld_get (insn) == 5) + return OPCODE_IVP_UNSQZN; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_get (insn) == 62) + return OPCODE_IVP_LTRS2N; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_get (insn) == 78) + return OPCODE_IVP_LTRSN; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_get (insn) == 94) + return OPCODE_IVP_LTRSN_2; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 0 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 25) + return OPCODE_IVP_ORNOTB; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 3 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 208) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 2 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 210) + return OPCODE_IVP_RORB2N; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 2 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 209) + return OPCODE_IVP_RANDBN; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 3 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 210) + return OPCODE_IVP_RORBN; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 3 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 209) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 2 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 211) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f0_s1_ld_24_17_Slot_f0_s1_ld_get (insn) == 2) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_f0_s1_ld_24_17_Slot_f0_s1_ld_get (insn) == 3) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_f0_s1_ld_24_17_Slot_f0_s1_ld_get (insn) == 4) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_f0_s1_ld_24_17_Slot_f0_s1_ld_get (insn) == 5) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_f0_s1_ld_24_17_Slot_f0_s1_ld_get (insn) == 6) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_LAT2NX8_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 4 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 7) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 4 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 6) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 4 && + Field_fld_f0_s1_ld_15_15_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 4 && + Field_fld_f0_s1_ld_15_14_Slot_f0_s1_ld_get (insn) == 2) + return OPCODE_MOVI; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 6 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 3) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 6 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 4) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 6 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 5) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 6 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 2) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 6 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 1) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 6 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 6) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 6 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 7) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 6 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_15_10_Slot_f0_s1_ld_get (insn) == 16) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_15_8_Slot_f0_s1_ld_get (insn) == 68) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_15_4_Slot_f0_s1_ld_get (insn) == 1120) + return OPCODE_IVP_LA_PP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_15_2_Slot_f0_s1_ld_get (insn) == 4544) + return OPCODE_IVP_MALIGN; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 1) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 2) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 3) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 4) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_f0_s1_ld_24_8_Slot_f0_s1_ld_get (insn) == 7237) + return OPCODE_NSA; + if (Field_fld_f0_s1_ld_24_8_Slot_f0_s1_ld_get (insn) == 7493) + return OPCODE_NSAU; + return XTENSA_UNDEFINED; +} + +static int +Slot_f1_s1_ld_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f1_s1_ld_26_11_Slot_f1_s1_ld_get (insn) == 1294 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_IVP_MOVAB1; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 570) + return OPCODE_ADD; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 571) + return OPCODE_ADDX2; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 572) + return OPCODE_ADDX4; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 573) + return OPCODE_ADDX8; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 574) + return OPCODE_AND; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 575) + return OPCODE_MAX; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 576) + return OPCODE_MAXU; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 577) + return OPCODE_MIN; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 578) + return OPCODE_MINU; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 579) + return OPCODE_MOVEQZ; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 580) + return OPCODE_MOVGEZ; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 581) + return OPCODE_MOVLTZ; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 582) + return OPCODE_MOVNEZ; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 583) + return OPCODE_OR; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 584) + return OPCODE_SALT; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 585) + return OPCODE_SALTU; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 586) + return OPCODE_SUB; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 587) + return OPCODE_SUBX2; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 588) + return OPCODE_SUBX4; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 589) + return OPCODE_SUBX8; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 590) + return OPCODE_XOR; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 591) + return OPCODE_SEXT; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 592) + return OPCODE_SRLI; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 593 && + Field_fld_f1_s1_ld_3_0_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 593 && + Field_fld_f1_s1_ld_3_0_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_SRA; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 646 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_SLL; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 229) + return OPCODE_SLLI; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 230) + return OPCODE_IVP_LSNX16_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 231) + return OPCODE_IVP_LSNX8S_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 237) + return OPCODE_IVP_LS2NX8_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 238) + return OPCODE_IVP_LSNX8S_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 239) + return OPCODE_IVP_LSN_2X16S_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 245) + return OPCODE_IVP_LS2NX8_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 246) + return OPCODE_IVP_LSN_2X16S_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 247) + return OPCODE_IVP_LSN_2X32_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 253) + return OPCODE_IVP_LSNX16_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 254) + return OPCODE_IVP_LSN_2X32_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 255) + return OPCODE_IVP_LSR2NX8_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 256) + return OPCODE_IVP_LSR2NX8_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 257) + return OPCODE_IVP_LSRNX16_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 258) + return OPCODE_IVP_LSRNX16_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 259) + return OPCODE_IVP_LSRN_2X32_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 260) + return OPCODE_IVP_LSRN_2X32_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 261) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 262) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 263) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 264) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 265) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 266) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 267) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 268) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 269) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 270) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 271) + return OPCODE_IVP_LS2NX8_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 272) + return OPCODE_IVP_LSNX16_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 273) + return OPCODE_IVP_LSNX8S_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 274) + return OPCODE_IVP_LSN_2X16S_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 275) + return OPCODE_IVP_LSN_2X32_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 276) + return OPCODE_IVP_LSR2NX8_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 277) + return OPCODE_IVP_LSRNX16_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 278) + return OPCODE_IVP_LSRN_2X32_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 279) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 280) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 281) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 282) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 283) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 284) + return OPCODE_SRAI; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 297 && + Field_fld_f1_s1_ld_7_7_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVPINT16; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 297 && + Field_fld_f1_s1_ld_7_7_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVQINT16; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 298 && + Field_fld_f1_s1_ld_7_7_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINT16; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 298 && + Field_fld_f1_s1_ld_7_6_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_IVP_MOVVINX16; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 299 && + Field_fld_f1_s1_ld_7_7_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINT8; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 300 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVR2NX24; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 300 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVR2NX24_0; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 300 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNRN_2X64W; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 300 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNRNX48_1; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 301 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVR2NX24_1; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 301 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNX48; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 301 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNX48_0; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 301 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNR2NX24; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 302 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNR2NX24_0; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 302 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNR2NX24_1; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 302 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRN_2X64W; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 302 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNX48_1; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 303 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRU2NX24; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 303 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRU2NX24_0; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 303 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNRNX48_0; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 303 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNRNX48; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 304 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 22) + return OPCODE_IVP_CVT32UNX48L; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 304 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 23) + return OPCODE_IVP_PACKMNX48; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 305 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 22) + return OPCODE_IVP_CVT64S48; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 305 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 23) + return OPCODE_IVP_GATHERD2NX8_H; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 306 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 22) + return OPCODE_IVP_CVT64U96; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 306 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 23) + return OPCODE_IVP_GATHERD2NX8_L; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 307 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 22) + return OPCODE_IVP_PACKHN_2X64W; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 307 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 23) + return OPCODE_IVP_GATHERDNX16; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 308 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 22) + return OPCODE_IVP_PACKL2NX24; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 308 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 23) + return OPCODE_IVP_GATHERDNX8S; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 309 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 94) + return OPCODE_IVP_SEQNX16; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 309 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 22) + return OPCODE_IVP_PACKL2NX24_1; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 309 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 93) + return OPCODE_IVP_SEQ2NX8; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 309 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 95) + return OPCODE_IVP_SEQN_2X32; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 310 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 22) + return OPCODE_IVP_PACKLNX48; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 311 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 22) + return OPCODE_IVP_PACKLN_2X96; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 321 && + Field_fld_f1_s1_ld_3_0_Slot_f1_s1_ld_get (insn) == 4) + return OPCODE_IVP_MOVVA16; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 321 && + Field_fld_f1_s1_ld_3_0_Slot_f1_s1_ld_get (insn) == 5) + return OPCODE_IVP_MOVVA32; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 321 && + Field_fld_f1_s1_ld_3_0_Slot_f1_s1_ld_get (insn) == 6) + return OPCODE_IVP_MOVVA8; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 321 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRU2NX24_1; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 331 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 9) + return OPCODE_IVP_CVT16S2NX24L; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 331 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 8) + return OPCODE_IVP_CVT16S2NX24H; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 331 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 10) + return OPCODE_IVP_CVT16U2NX24H; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 331 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 11) + return OPCODE_IVP_CVT16U2NX24L; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 339 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 11) + return OPCODE_IVP_CVT32S2NX24LH; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 339 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 10) + return OPCODE_IVP_CVT32S2NX24HL; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 339 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 9) + return OPCODE_IVP_CVT32S2NX24HH; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 339 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 8) + return OPCODE_IVP_CVT32S24; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 347 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 8) + return OPCODE_IVP_CVT32S2NX24LL; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 347 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 10) + return OPCODE_IVP_CVT32SNX48L; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 347 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 9) + return OPCODE_IVP_CVT32SNX48H; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 347 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 11) + return OPCODE_IVP_CVT32UNX48H; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (insn) == 8) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 81) + return OPCODE_IVP_NOTB; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 1 && + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (insn) == 8) + return OPCODE_IVP_ANDB; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (insn) == 9) + return OPCODE_IVP_ORB; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (insn) == 10) + return OPCODE_IVP_XORB; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 1 && + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (insn) == 9) + return OPCODE_IVP_ANDNOTB; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 80) + return OPCODE_IVP_MB; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_get (insn) == 118) + return OPCODE_IVP_LTRN; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_10_Slot_f1_s1_ld_get (insn) == 0 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 6) + return OPCODE_IVP_LTRNI; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (insn) == 9) + return OPCODE_IVP_JOINB; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_get (insn) == 134) + return OPCODE_IVP_LTRN_2; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_9_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 6) + return OPCODE_IVP_LTRN_2I; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_get (insn) == 198) + return OPCODE_IVP_MOVBA1; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 82) + return OPCODE_IVP_NOTB1; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (insn) == 8) + return OPCODE_IVP_ANDNOTB1; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 1 && + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (insn) == 10) + return OPCODE_IVP_ORNOTB1; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_get (insn) == 102) + return OPCODE_IVP_LTR2N; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 0 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 4) + return OPCODE_IVP_LTR2NI; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_12_Slot_f1_s1_ld_get (insn) == 0 && + Field_fld_f1_s1_ld_7_5_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_SQZN; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_12_Slot_f1_s1_ld_get (insn) == 1 && + Field_fld_f1_s1_ld_7_5_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_UNSQZN; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_get (insn) == 150) + return OPCODE_IVP_LTRS2N; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_get (insn) == 166) + return OPCODE_IVP_LTRSN; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_get (insn) == 182) + return OPCODE_IVP_LTRSN_2; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 0 && + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (insn) == 10) + return OPCODE_IVP_ORNOTB; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 83) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 86) + return OPCODE_IVP_RORB2N; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 84) + return OPCODE_IVP_RANDBN; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 87) + return OPCODE_IVP_RORBN; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 85) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 96) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_LAT2NX8_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 1 && + Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 1 && + Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_LSN_2X32_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 4 && + Field_fld_f1_s1_ld_15_14_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 4 && + Field_fld_f1_s1_ld_15_14_Slot_f1_s1_ld_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 4 && + Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 5 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 7) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 5 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 5) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 5 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 6) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 5 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 4) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 5 && + Field_fld_f1_s1_ld_15_14_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_L32I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 5 && + Field_fld_f1_s1_ld_15_14_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_MOVI; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 6 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 7) + return OPCODE_IVP_LSNX16_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 6 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 6 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 6 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 3) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 6 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 6 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 4) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 6 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 5) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 6 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 6) + return OPCODE_IVP_LS2NX8_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 7 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_LSNX8S_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 7 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_LSN_2X16S_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 7 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_IVP_LSR2NX8_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 7 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 3) + return OPCODE_IVP_LSRNX16_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 7 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 4) + return OPCODE_IVP_LSRN_2X32_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 10 && + Field_fld_f1_s1_ld_15_10_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 10 && + Field_fld_f1_s1_ld_15_8_Slot_f1_s1_ld_get (insn) == 4) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 10 && + Field_fld_f1_s1_ld_15_4_Slot_f1_s1_ld_get (insn) == 80) + return OPCODE_IVP_LA_PP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 10 && + Field_fld_f1_s1_ld_15_2_Slot_f1_s1_ld_get (insn) == 324) + return OPCODE_IVP_MALIGN; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 10 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 10 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 10 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 10 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 10 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_f1_s1_ld_26_2_Slot_f1_s1_ld_get (insn) == 655685 && + Field_fld_f1_s1_ld_1_0_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_f2_s1_ld_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f2_s1_ld_26_11_Slot_f2_s1_ld_get (insn) == 1294 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_MOVAB1; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 570) + return OPCODE_ADD; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 571) + return OPCODE_ADDX2; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 572) + return OPCODE_ADDX4; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 573) + return OPCODE_ADDX8; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 574) + return OPCODE_AND; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 575) + return OPCODE_IVP_ADDMOD16U; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 576) + return OPCODE_MAX; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 577) + return OPCODE_MAXU; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 578) + return OPCODE_MIN; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 579) + return OPCODE_MINU; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 580) + return OPCODE_MOVEQZ; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 581) + return OPCODE_MOVGEZ; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 582) + return OPCODE_MOVLTZ; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 583) + return OPCODE_MOVNEZ; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 584) + return OPCODE_OR; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 585) + return OPCODE_SALT; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 586) + return OPCODE_SALTU; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 587) + return OPCODE_SUB; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 588) + return OPCODE_SUBX2; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 589) + return OPCODE_SUBX4; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 590) + return OPCODE_SUBX8; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 591) + return OPCODE_XOR; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 592) + return OPCODE_SEXT; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 593) + return OPCODE_SRLI; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 642 && + Field_fld_f2_s1_ld_3_0_Slot_f2_s1_ld_get (insn) == 9) + return OPCODE_SRL; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 642 && + Field_fld_f2_s1_ld_3_0_Slot_f2_s1_ld_get (insn) == 8) + return OPCODE_SRA; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 646 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_SLL; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 229) + return OPCODE_IVP_LS2NX8_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 230) + return OPCODE_IVP_LSNX8S_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 231) + return OPCODE_IVP_LSNX8S_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 237) + return OPCODE_IVP_LS2NX8_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 238) + return OPCODE_IVP_LSN_2X16S_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 239) + return OPCODE_IVP_LSN_2X16S_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 245) + return OPCODE_IVP_LSNX16_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 246) + return OPCODE_IVP_LSN_2X32_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 247) + return OPCODE_IVP_LSN_2X32_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 253) + return OPCODE_IVP_LSNX16_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 254) + return OPCODE_IVP_LSR2NX8_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 255) + return OPCODE_IVP_LSR2NX8_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 256) + return OPCODE_IVP_LSRNX16_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 257) + return OPCODE_IVP_LSRNX16_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 258) + return OPCODE_IVP_LSRN_2X32_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 259) + return OPCODE_IVP_LSRN_2X32_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 260) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 261) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 262) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 263) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 264) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 265) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 266) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 267) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 268) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 269) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 270) + return OPCODE_SLLI; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 271) + return OPCODE_IVP_LS2NX8_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 272) + return OPCODE_IVP_LSNX16_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 273) + return OPCODE_IVP_LSNX8S_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 274) + return OPCODE_IVP_LSN_2X16S_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 275) + return OPCODE_IVP_LSN_2X32_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 276) + return OPCODE_IVP_LSR2NX8_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 277) + return OPCODE_IVP_LSRNX16_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 278) + return OPCODE_IVP_LSRN_2X32_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 279) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 280) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 281) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 282) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 283) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 284) + return OPCODE_SRAI; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 297 && + Field_fld_f2_s1_ld_7_7_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVPINT16; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 297 && + Field_fld_f2_s1_ld_7_7_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVQINT16; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 298 && + Field_fld_f2_s1_ld_7_7_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINT16; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 298 && + Field_fld_f2_s1_ld_7_6_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_MOVVINX16; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 299 && + Field_fld_f2_s1_ld_7_7_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINT8; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 300 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVR2NX24; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 300 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVR2NX24_0; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 300 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNRN_2X64W; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 300 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNRNX48_1; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 301 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVR2NX24_1; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 301 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNX48; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 301 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNX48_0; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 301 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNR2NX24; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 302 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNR2NX24_0; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 302 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNR2NX24_1; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 302 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRN_2X64W; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 302 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNX48_1; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 303 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRU2NX24; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 303 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRU2NX24_0; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 303 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNRNX48_0; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 303 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNRNX48; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_3_0_Slot_f2_s1_ld_get (insn) == 4) + return OPCODE_IVP_MOVVA16; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 222) + return OPCODE_IVP_SEQNX16; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 3) + return OPCODE_IVP_CVT32UNX48L; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 7) + return OPCODE_IVP_CVT64S48; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 11) + return OPCODE_IVP_CVT64U96; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_3_0_Slot_f2_s1_ld_get (insn) == 5) + return OPCODE_IVP_MOVVA32; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_3_0_Slot_f2_s1_ld_get (insn) == 6) + return OPCODE_IVP_MOVVA8; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 19) + return OPCODE_IVP_PACKL2NX24; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 27) + return OPCODE_IVP_PACKLNX48; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 23) + return OPCODE_IVP_PACKL2NX24_1; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRU2NX24_1; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 35) + return OPCODE_IVP_PACKMNX48; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 31) + return OPCODE_IVP_PACKLN_2X96; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 15) + return OPCODE_IVP_PACKHN_2X64W; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 221) + return OPCODE_IVP_SEQ2NX8; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 223) + return OPCODE_IVP_SEQN_2X32; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 47) + return OPCODE_IVP_GATHERDNX16; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 51) + return OPCODE_IVP_GATHERDNX8S; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 43) + return OPCODE_IVP_GATHERD2NX8_L; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 39) + return OPCODE_IVP_GATHERD2NX8_H; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 331 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 9) + return OPCODE_IVP_CVT16S2NX24L; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 331 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 8) + return OPCODE_IVP_CVT16S2NX24H; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 331 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 10) + return OPCODE_IVP_CVT16U2NX24H; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 331 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 11) + return OPCODE_IVP_CVT16U2NX24L; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 339 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 11) + return OPCODE_IVP_CVT32S2NX24LH; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 339 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 10) + return OPCODE_IVP_CVT32S2NX24HL; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 339 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 9) + return OPCODE_IVP_CVT32S2NX24HH; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 339 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 8) + return OPCODE_IVP_CVT32S24; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 347 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 8) + return OPCODE_IVP_CVT32S2NX24LL; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 347 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 10) + return OPCODE_IVP_CVT32SNX48L; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 347 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 9) + return OPCODE_IVP_CVT32SNX48H; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 347 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 11) + return OPCODE_IVP_CVT32UNX48H; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 19) + return OPCODE_IVP_NOTB; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 1 && + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_ANDB; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_ORB; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_XORB; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 1 && + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_ANDNOTB; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 18) + return OPCODE_IVP_MB; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_get (insn) == 114) + return OPCODE_IVP_LTRN; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_10_Slot_f2_s1_ld_get (insn) == 0 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_LTRNI; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_JOINB; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_get (insn) == 130) + return OPCODE_IVP_LTRN_2; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_9_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_LTRN_2I; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 17) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 16) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_get (insn) == 194) + return OPCODE_IVP_MOVBA1; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 20) + return OPCODE_IVP_NOTB1; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_ANDNOTB1; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 1 && + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_ORNOTB1; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_get (insn) == 98) + return OPCODE_IVP_LTR2N; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 0 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTR2NI; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_get (insn) == 146) + return OPCODE_IVP_LTRS2N; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_get (insn) == 162) + return OPCODE_IVP_LTRSN; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_get (insn) == 178) + return OPCODE_IVP_LTRSN_2; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 0 && + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_ORNOTB; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 21) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 32) + return OPCODE_IVP_RORB2N; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 22) + return OPCODE_IVP_RANDBN; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 32) + return OPCODE_IVP_RORBN; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 23) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 33) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LAT2NX8_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 1 && + Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 1 && + Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LSN_2X32_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 4 && + Field_fld_f2_s1_ld_15_14_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 4 && + Field_fld_f2_s1_ld_15_14_Slot_f2_s1_ld_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 4 && + Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 5 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 7) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 5 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 5) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 5 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 6) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 5 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 4) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 5 && + Field_fld_f2_s1_ld_15_14_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_L32I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 5 && + Field_fld_f2_s1_ld_15_14_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_MOVI; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 6 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 7) + return OPCODE_IVP_LSNX16_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 6 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 6 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 6 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 3) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 6 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 6 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 4) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 6 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 5) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 6 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 6) + return OPCODE_IVP_LS2NX8_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 7 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LSNX8S_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 7 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LSN_2X16S_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 7 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_LSR2NX8_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 7 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 3) + return OPCODE_IVP_LSRNX16_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 7 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 4) + return OPCODE_IVP_LSRN_2X32_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 10 && + Field_fld_f2_s1_ld_15_10_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 10 && + Field_fld_f2_s1_ld_15_8_Slot_f2_s1_ld_get (insn) == 4) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 10 && + Field_fld_f2_s1_ld_15_4_Slot_f2_s1_ld_get (insn) == 80) + return OPCODE_IVP_LA_PP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 10 && + Field_fld_f2_s1_ld_15_2_Slot_f2_s1_ld_get (insn) == 324) + return OPCODE_IVP_MALIGN; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 10 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 10 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 10 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 10 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 10 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_f2_s1_ld_26_2_Slot_f2_s1_ld_get (insn) == 655685 && + Field_fld_f2_s1_ld_1_0_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_f3_s1_ld_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f3_s1_ld_21_0_Slot_f3_s1_ld_get (insn) == 1769748) + return OPCODE_NOP; + if (Field_fld_f3_s1_ld_21_10_Slot_f3_s1_ld_get (insn) == 1729 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRNI; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 830 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTR2NI; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 831 && + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_ANDB; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 831 && + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_ANDNOTB; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 848 && + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_ANDNOTB1; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 848 && + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_ORNOTB; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 849 && + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 849 && + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_ORNOTB1; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 850 && + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_XORB; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 850 && + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_JOINB; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 851 && + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_ORB; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 851 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 24) + return OPCODE_IVP_RORB2N; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 851 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 25) + return OPCODE_IVP_RORBN; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 851 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 26) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 854 && + Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_get (insn) == 8) + return OPCODE_IVP_MOVAB1; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 866 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_MB; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 866 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 2) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 866 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 18) + return OPCODE_IVP_NOTB1; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 866 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 19) + return OPCODE_IVP_RANDBN; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 867 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_NOTB; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 867 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 2) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 867 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 18) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 867 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 19) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 376) + return OPCODE_ADD; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 377) + return OPCODE_ADDX2; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 378) + return OPCODE_ADDX4; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 379) + return OPCODE_ADDX8; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 380) + return OPCODE_AND; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 381) + return OPCODE_IVP_ADDMOD16U; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 382) + return OPCODE_MAX; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 383) + return OPCODE_MAXU; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 384) + return OPCODE_MIN; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 385) + return OPCODE_MINU; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 386) + return OPCODE_MOVEQZ; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 387) + return OPCODE_MOVGEZ; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 388) + return OPCODE_MOVLTZ; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 389) + return OPCODE_MOVNEZ; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 390) + return OPCODE_OR; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 391) + return OPCODE_SALT; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 392) + return OPCODE_SALTU; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 393) + return OPCODE_SUB; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 394) + return OPCODE_SUBX2; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 395) + return OPCODE_SUBX4; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 396) + return OPCODE_SUBX8; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 397) + return OPCODE_XOR; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 398) + return OPCODE_SEXT; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 399) + return OPCODE_SRLI; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 400) + return OPCODE_IVP_SQZN; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 401) + return OPCODE_IVP_UNSQZN; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 409 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LB2N_IP; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 411 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LBN_2_IP; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 413 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LBN_IP; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 426 && + Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_get (insn) == 8) + return OPCODE_SLL; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 433 && + Field_fld_f3_s1_ld_3_0_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 433 && + Field_fld_f3_s1_ld_3_0_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_SRA; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 168) + return OPCODE_SLLI; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 169) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 170) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 171) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 172) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 173) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 174) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 175) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 176) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 177) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 178) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 179) + return OPCODE_IVP_LB2N_I; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 180) + return OPCODE_IVP_LBN_2_I; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 181) + return OPCODE_IVP_LBN_I; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 182) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 183) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 184) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 185) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 186) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 187) + return OPCODE_SRAI; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 202 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVPINT16; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 202 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVQINT16; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 203 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINT16; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 203 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVVINT8; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 204 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 52) + return OPCODE_IVP_CVT32UNX48L; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 204 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 60) + return OPCODE_IVP_CVT64S48; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 204 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT64U96; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 204 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 54) + return OPCODE_IVP_PACKL2NX24; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 204 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 55) + return OPCODE_IVP_PACKLNX48; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 204 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 62) + return OPCODE_IVP_PACKL2NX24_1; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 204 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 63) + return OPCODE_IVP_PACKLN_2X96; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 204 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 61) + return OPCODE_IVP_PACKHN_2X64W; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 205 && + Field_fld_f3_s1_ld_7_0_Slot_f3_s1_ld_get (insn) == 250) + return OPCODE_IVP_SEQNX16; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 205 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 52) + return OPCODE_IVP_PACKMNX48; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 205 && + Field_fld_f3_s1_ld_7_0_Slot_f3_s1_ld_get (insn) == 249) + return OPCODE_IVP_SEQ2NX8; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 205 && + Field_fld_f3_s1_ld_7_0_Slot_f3_s1_ld_get (insn) == 251) + return OPCODE_IVP_SEQN_2X32; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 205 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 61) + return OPCODE_IVP_GATHERDNX16; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 205 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 54) + return OPCODE_IVP_GATHERDNX8S; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 205 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 53) + return OPCODE_IVP_GATHERD2NX8_L; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 205 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 60) + return OPCODE_IVP_GATHERD2NX8_H; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 208 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVR2NX24; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 208 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVR2NX24_0; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 208 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVR2NX24_1; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 208 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNR2NX24; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 209 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNR2NX24_0; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 209 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNR2NX24_1; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 209 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNRNX48_0; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 209 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNRNX48; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 210 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNX48; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 210 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNRN_2X64W; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 210 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNX48_0; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 210 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNRNX48_1; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 211 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRU2NX24; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 211 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRU2NX24_0; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 211 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRN_2X64W; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 211 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNX48_1; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 212 && + Field_fld_f3_s1_ld_3_0_Slot_f3_s1_ld_get (insn) == 4) + return OPCODE_IVP_MOVVA16; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 212 && + Field_fld_f3_s1_ld_3_0_Slot_f3_s1_ld_get (insn) == 5) + return OPCODE_IVP_MOVVA32; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 212 && + Field_fld_f3_s1_ld_3_0_Slot_f3_s1_ld_get (insn) == 6) + return OPCODE_IVP_MOVVA8; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 212 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRU2NX24_1; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_7_Slot_f3_s1_ld_get (insn) == 0 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINX16; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 50) + return OPCODE_IVP_CVT32S2NX24LL; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 57) + return OPCODE_IVP_CVT32S2NX24LH; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 49) + return OPCODE_IVP_CVT32S2NX24HL; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 56) + return OPCODE_IVP_CVT32S2NX24HH; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 41) + return OPCODE_IVP_CVT16S2NX24L; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 40) + return OPCODE_IVP_CVT16S2NX24H; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 51) + return OPCODE_IVP_CVT32SNX48L; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 58) + return OPCODE_IVP_CVT32SNX48H; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 42) + return OPCODE_IVP_CVT16U2NX24H; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 59) + return OPCODE_IVP_CVT32UNX48H; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 43) + return OPCODE_IVP_CVT16U2NX24L; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 48) + return OPCODE_IVP_CVT32S24; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 32) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 33) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 34) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 35) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 36) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 37) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 38) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 39) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 40) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 41) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 51 && + Field_fld_f3_s1_ld_12_11_Slot_f3_s1_ld_get (insn) == 0 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 51 && + Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 51 && + Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 51 && + Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_get (insn) == 5) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 51 && + Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_get (insn) == 7) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 51 && + Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_get (insn) == 9) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 54 && + Field_fld_f3_s1_ld_12_8_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 54 && + Field_fld_f3_s1_ld_12_4_Slot_f3_s1_ld_get (insn) == 16) + return OPCODE_IVP_LA_PP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 54 && + Field_fld_f3_s1_ld_12_2_Slot_f3_s1_ld_get (insn) == 68) + return OPCODE_IVP_MALIGN; + if (Field_fld_f3_s1_ld_21_16_Slot_f3_s1_ld_get (insn) == 12) + return OPCODE_ADDI; + if (Field_fld_f3_s1_ld_21_16_Slot_f3_s1_ld_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_fld_f3_s1_ld_21_16_Slot_f3_s1_ld_get (insn) == 14) + return OPCODE_L32I; + if (Field_fld_f3_s1_ld_21_16_Slot_f3_s1_ld_get (insn) == 15) + return OPCODE_MOVI; + if (Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_get (insn) == 2) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_get (insn) == 4) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_get (insn) == 5) + return OPCODE_EXTUI; + if (Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_get (insn) == 6918 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTR2N; + if (Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_get (insn) == 6919 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTRN; + if (Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_get (insn) == 6948 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRN_2; + if (Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_get (insn) == 6948 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVBA1; + if (Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_get (insn) == 6949 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRS2N; + if (Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_get (insn) == 6950 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRSN; + if (Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_get (insn) == 6951 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRSN_2; + if (Field_fld_f3_s1_ld_21_9_Slot_f3_s1_ld_get (insn) == 3458 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTRN_2I; + return XTENSA_UNDEFINED; +} + +static int +Slot_f11_s1_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f11_s1_alu_22_0_Slot_f11_s1_alu_get (insn) == 794628) + return OPCODE_NOP; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 165) + return OPCODE_ADD; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 167) + return OPCODE_ADDX2; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 168) + return OPCODE_ADDX4; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 169) + return OPCODE_MAXU; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 170) + return OPCODE_ADDX8; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 171) + return OPCODE_MIN; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 172) + return OPCODE_AND; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 173) + return OPCODE_MINU; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 174) + return OPCODE_MAX; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 175) + return OPCODE_MOVEQZ; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 176) + return OPCODE_MOVGEZ; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 177) + return OPCODE_SUBX4; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 178) + return OPCODE_MOVLTZ; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 179) + return OPCODE_SUBX8; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 180) + return OPCODE_MOVNEZ; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 181) + return OPCODE_XOR; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 182) + return OPCODE_OR; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 183) + return OPCODE_SEXT; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 184) + return OPCODE_SALT; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 185) + return OPCODE_SRLI; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 186) + return OPCODE_SALTU; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 187 && + Field_fld_f11_s1_alu_3_0_Slot_f11_s1_alu_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 187 && + Field_fld_f11_s1_alu_3_0_Slot_f11_s1_alu_get (insn) == 0) + return OPCODE_SRA; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 188) + return OPCODE_SUB; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 190) + return OPCODE_SUBX2; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 208 && + Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_get (insn) == 1) + return OPCODE_SLL; + if (Field_fld_f11_s1_alu_22_13_Slot_f11_s1_alu_get (insn) == 80) + return OPCODE_IVP_L2U2NX8_XP; + if (Field_fld_f11_s1_alu_22_13_Slot_f11_s1_alu_get (insn) == 81) + return OPCODE_SRAI; + if (Field_fld_f11_s1_alu_22_14_Slot_f11_s1_alu_get (insn) == 41 && + Field_fld_f11_s1_alu_12_12_Slot_f11_s1_alu_get (insn) == 0) + return OPCODE_SLLI; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 8) + return OPCODE_ADDI; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 9) + return OPCODE_ADDMI; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 12 && + Field_fld_f11_s1_alu_12_10_Slot_f11_s1_alu_get (insn) == 2 && + Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_get (insn) == 1) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 12 && + Field_fld_f11_s1_alu_12_10_Slot_f11_s1_alu_get (insn) == 3 && + Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_get (insn) == 1) + return OPCODE_IVP_LTRNI; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 12 && + Field_fld_f11_s1_alu_12_11_Slot_f11_s1_alu_get (insn) == 0 && + Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_get (insn) == 1) + return OPCODE_IVP_LTR2NI; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 14 && + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (insn) == 130) + return OPCODE_IVP_MB; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 14 && + Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_get (insn) == 33) + return OPCODE_IVP_LTRN_2; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 14 && + Field_fld_f11_s1_alu_12_9_Slot_f11_s1_alu_get (insn) == 0 && + Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_get (insn) == 1) + return OPCODE_IVP_LTRN_2I; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 14 && + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (insn) == 131) + return OPCODE_IVP_NOTB1; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 14 && + Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_get (insn) == 49) + return OPCODE_IVP_LTRSN; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 14 && + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (insn) == 163) + return OPCODE_IVP_RORB2N; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 14 && + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (insn) == 162) + return OPCODE_IVP_RANDBN; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 14 && + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (insn) == 194) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 15 && + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (insn) == 130) + return OPCODE_IVP_NOTB; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 15 && + Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_get (insn) == 17) + return OPCODE_IVP_LTRN; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 15 && + Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_get (insn) == 1) + return OPCODE_IVP_LTR2N; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 15 && + Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_get (insn) == 33) + return OPCODE_IVP_LTRS2N; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 15 && + Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_get (insn) == 49) + return OPCODE_IVP_LTRSN_2; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 15 && + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (insn) == 131) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 15 && + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (insn) == 163) + return OPCODE_IVP_RORBN; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 15 && + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (insn) == 162) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_get (insn) == 0) + return OPCODE_IVP_LAT2NX8_XP; + if (Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_get (insn) == 1 && + Field_fld_f11_s1_alu_15_14_Slot_f11_s1_alu_get (insn) == 2) + return OPCODE_IVP_L2A4NX8_IP; + if (Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_get (insn) == 1 && + Field_fld_f11_s1_alu_15_15_Slot_f11_s1_alu_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_get (insn) == 1 && + Field_fld_f11_s1_alu_15_14_Slot_f11_s1_alu_get (insn) == 3) + return OPCODE_MOVI; + if (Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_get (insn) == 3 && + Field_fld_f11_s1_alu_15_2_Slot_f11_s1_alu_get (insn) == 2048) + return OPCODE_IVP_MALIGN; + if (Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_get (insn) == 3 && + Field_fld_f11_s1_alu_15_13_Slot_f11_s1_alu_get (insn) == 0 && + Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_get (insn) == 0) + return OPCODE_IVP_L2AU2NX8_IP; + return XTENSA_UNDEFINED; +} + +static int +Slot_n2_s1_ld_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_n2_s1_ld_26_10_Slot_n2_s1_ld_get (insn) == 1840 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTRNI; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 908 && + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_ANDNOTB1; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 908 && + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_ORNOTB; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 909 && + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_EXT0IB; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 909 && + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_ORNOTB1; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 910 && + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_XORB; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 910 && + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_JOINB; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 911 && + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_ORB; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 911 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 24) + return OPCODE_IVP_NOTB1; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 911 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 25) + return OPCODE_IVP_RANDB2N; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 911 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 28) + return OPCODE_IVP_RORB2N; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 911 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 26) + return OPCODE_IVP_RANDBN; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 911 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 29) + return OPCODE_IVP_RORBN; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 911 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 27) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 911 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 30) + return OPCODE_IVP_RORBN_2; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 918 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTR2NI; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 919 && + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (insn) == 2) + return OPCODE_IVP_ANDB; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 919 && + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_ANDNOTB; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 922 && + Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_MOVAB1; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 934 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 19) + return OPCODE_IVP_MB; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 934 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 935 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 19) + return OPCODE_IVP_NOTB; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 935 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 408) + return OPCODE_ADD; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 409) + return OPCODE_ADDX2; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 410) + return OPCODE_ADDX4; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 411) + return OPCODE_ADDX8; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 412) + return OPCODE_AND; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 413) + return OPCODE_MAX; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 414) + return OPCODE_MAXU; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 415) + return OPCODE_MIN; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 416) + return OPCODE_MINU; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 417) + return OPCODE_MOVEQZ; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 418) + return OPCODE_MOVGEZ; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 419) + return OPCODE_MOVLTZ; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 420) + return OPCODE_MOVNEZ; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 421) + return OPCODE_OR; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 422) + return OPCODE_SALT; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 423) + return OPCODE_SALTU; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 424) + return OPCODE_SUB; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 425) + return OPCODE_SUBX2; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 426) + return OPCODE_SUBX4; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 427) + return OPCODE_SUBX8; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 428) + return OPCODE_XOR; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 429) + return OPCODE_SEXT; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 430) + return OPCODE_L32I_N; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 431) + return OPCODE_SRLI; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 432) + return OPCODE_IVP_SQZN; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 433) + return OPCODE_IVP_UNSQZN; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 456 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LB2N_IP; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 457 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LBN_2_IP; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 458 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LBN_IP; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 461 && + Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_SLL; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 466 && + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 466 && + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 467 && + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get (insn) == 2) + return OPCODE_SRL; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 184) + return OPCODE_SLLI; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 185) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 186) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 187) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 188) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 189) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 190) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 191) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 192) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 193) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 194) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 195) + return OPCODE_IVP_LB2N_I; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 196) + return OPCODE_IVP_LBN_2_I; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 197) + return OPCODE_IVP_LBN_I; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 198) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 199) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 200) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 201) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 202) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 203) + return OPCODE_SRAI; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 217 && + Field_fld_n2_s1_ld_7_7_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVPINT16; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 217 && + Field_fld_n2_s1_ld_7_7_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVQINT16; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 218 && + Field_fld_n2_s1_ld_7_7_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINT16; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 218 && + Field_fld_n2_s1_ld_7_7_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVVINT8; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 219 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVR2NX24; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 219 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVR2NX24_0; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 219 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVR2NX24_1; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 219 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNR2NX24; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 224 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNR2NX24_0; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 224 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNR2NX24_1; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 224 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNRNX48_0; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 224 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNRNX48; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 225 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNX48; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 225 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNRN_2X64W; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 225 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNX48_0; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 225 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNRNX48_1; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 226 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRU2NX24; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 226 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRU2NX24_0; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 226 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRN_2X64W; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 226 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNX48_1; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 227 && + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get (insn) == 6) + return OPCODE_IVP_MOVVA16; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 227 && + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get (insn) == 4) + return OPCODE_IVP_MOVPA16; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 227 && + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get (insn) == 5) + return OPCODE_IVP_MOVQA16; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 227 && + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get (insn) == 7) + return OPCODE_IVP_MOVVA32; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 227 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRU2NX24_1; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 228 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 41) + return OPCODE_IVP_CVT64SNX48LL; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 228 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 40) + return OPCODE_IVP_CVT64SNX48LH; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 228 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 43) + return OPCODE_IVP_CVT64UN_2X96H; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 228 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 42) + return OPCODE_IVP_CVT64U96; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 229 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 40) + return OPCODE_IVP_CVT64UN_2X96L; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 229 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 42) + return OPCODE_IVP_PACKL2NX24; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 229 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 43) + return OPCODE_IVP_PACKL2NX24_1; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 229 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 41) + return OPCODE_IVP_PACKHN_2X64W; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 230 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 40) + return OPCODE_IVP_PACKLNX48; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 230 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 42) + return OPCODE_IVP_PACKMNX48; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 230 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 41) + return OPCODE_IVP_PACKLN_2X96; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 230 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 43) + return OPCODE_IVP_GATHERD2NX8_H; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 231 && + Field_fld_n2_s1_ld_7_0_Slot_n2_s1_ld_get (insn) == 173) + return OPCODE_IVP_SEQNX16; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 231 && + Field_fld_n2_s1_ld_7_0_Slot_n2_s1_ld_get (insn) == 172) + return OPCODE_IVP_SEQ2NX8; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 231 && + Field_fld_n2_s1_ld_7_0_Slot_n2_s1_ld_get (insn) == 174) + return OPCODE_IVP_SEQN_2X32; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 231 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 41) + return OPCODE_IVP_GATHERDNX16; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 231 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 42) + return OPCODE_IVP_GATHERDNX8S; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 231 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 40) + return OPCODE_IVP_GATHERD2NX8_L; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 232 && + Field_fld_n2_s1_ld_7_6_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINX16; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 5) + return OPCODE_IVP_CVT32S2NX24LL; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 57) + return OPCODE_IVP_CVT32S2NX24LH; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 49) + return OPCODE_IVP_CVT32S2NX24HL; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 41) + return OPCODE_IVP_CVT32S2NX24HH; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 61) + return OPCODE_IVP_CVT64SNX48HL; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT64SNX48HH; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 9) + return OPCODE_IVP_CVT16S2NX24L; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_CVT16S2NX24H; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 21) + return OPCODE_IVP_CVT32SNX48L; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 13) + return OPCODE_IVP_CVT32SNX48H; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 17) + return OPCODE_IVP_CVT16U2NX24H; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 29) + return OPCODE_IVP_CVT32UNX48H; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 25) + return OPCODE_IVP_CVT16U2NX24L; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 33) + return OPCODE_IVP_CVT32S24; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 37) + return OPCODE_IVP_CVT32UNX48L; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 45) + return OPCODE_IVP_CVT64S48; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVA8; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 36) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 37) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 38) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 39) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 40) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 41) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 42) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 43) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 44) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 45) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 55 && + Field_fld_n2_s1_ld_12_10_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 55 && + Field_fld_n2_s1_ld_12_8_Slot_n2_s1_ld_get (insn) == 4) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 55 && + Field_fld_n2_s1_ld_12_4_Slot_n2_s1_ld_get (insn) == 96) + return OPCODE_IVP_LA_PP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 55 && + Field_fld_n2_s1_ld_12_2_Slot_n2_s1_ld_get (insn) == 448) + return OPCODE_IVP_MALIGN; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 57 && + Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 57 && + Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_get (insn) == 2) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 57 && + Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_get (insn) == 4) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 57 && + Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_get (insn) == 6) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 57 && + Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_get (insn) == 8) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_get (insn) == 12) + return OPCODE_ADDI; + if (Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_get (insn) == 14) + return OPCODE_L16SI; + if (Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_get (insn) == 15) + return OPCODE_L16UI; + if (Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_get (insn) == 16) + return OPCODE_L8UI; + if (Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_get (insn) == 17) + return OPCODE_MOVI; + if (Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_get (insn) == 2) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_get (insn) == 4) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_get (insn) == 5) + return OPCODE_EXTUI; + if (Field_fld_n2_s1_ld_26_2_Slot_n2_s1_ld_get (insn) == 451009 && + Field_fld_n2_s1_ld_1_0_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_NOP; + if (Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (insn) == 7045) + return OPCODE_NSA; + if (Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (insn) == 7077) + return OPCODE_NSAU; + if (Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (insn) == 7109 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRN_2; + if (Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (insn) == 7109 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTRSN; + if (Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (insn) == 7141 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRS2N; + if (Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (insn) == 7141 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTRSN_2; + if (Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (insn) == 7366 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTR2N; + if (Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (insn) == 7367 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTRN; + if (Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (insn) == 7368 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVBA1; + if (Field_fld_n2_s1_ld_26_9_Slot_n2_s1_ld_get (insn) == 3682 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTRN_2I; + return XTENSA_UNDEFINED; +} + +static int +Slot_f4_s1_ld_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f4_s1_ld_23_0_Slot_f4_s1_ld_get (insn) == 1672468) + return OPCODE_NOP; + if (Field_fld_f4_s1_ld_23_10_Slot_f4_s1_ld_get (insn) == 1720 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRNI; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 848 && + Field_fld_f4_s1_ld_4_0_Slot_f4_s1_ld_get (insn) == 25) + return OPCODE_IVP_MB; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 848 && + Field_fld_f4_s1_ld_4_0_Slot_f4_s1_ld_get (insn) == 9) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 848 && + Field_fld_f4_s1_ld_4_0_Slot_f4_s1_ld_get (insn) == 10) + return OPCODE_IVP_NOTB1; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 849 && + Field_fld_f4_s1_ld_4_0_Slot_f4_s1_ld_get (insn) == 25) + return OPCODE_IVP_NOTB; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 849 && + Field_fld_f4_s1_ld_4_0_Slot_f4_s1_ld_get (insn) == 9) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 852 && + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_ANDNOTB1; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 852 && + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get (insn) == 3) + return OPCODE_IVP_ORNOTB1; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 853 && + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get (insn) == 3) + return OPCODE_IVP_XORB; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 853 && + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_JOINB; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 854 && + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_ORB; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 854 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTR2NI; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 855 && + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_ANDB; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 855 && + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get (insn) == 1) + return OPCODE_IVP_ANDNOTB; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 855 && + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_ORNOTB; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 858 && + Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_get (insn) == 4) + return OPCODE_IVP_MOVAB1; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 376) + return OPCODE_ADD; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 377) + return OPCODE_ADDX2; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 378) + return OPCODE_ADDX4; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 379) + return OPCODE_ADDX8; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 380) + return OPCODE_AND; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 381) + return OPCODE_IVP_ADDMOD16U; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 382) + return OPCODE_MAX; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 383) + return OPCODE_MAXU; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 384) + return OPCODE_MIN; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 385) + return OPCODE_MINU; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 386) + return OPCODE_MOVEQZ; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 387) + return OPCODE_MOVGEZ; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 388) + return OPCODE_MOVLTZ; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 389) + return OPCODE_MOVNEZ; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 390) + return OPCODE_OR; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 391) + return OPCODE_SALT; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 392) + return OPCODE_SALTU; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 393) + return OPCODE_SUB; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 394) + return OPCODE_SUBX2; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 395) + return OPCODE_SUBX4; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 396) + return OPCODE_SUBX8; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 397) + return OPCODE_XOR; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 398) + return OPCODE_CLAMPS; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 399) + return OPCODE_SEXT; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 400) + return OPCODE_SRLI; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 401) + return OPCODE_IVP_SQZN; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 402) + return OPCODE_IVP_UNSQZN; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 403 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 1) + return OPCODE_IVP_LBN_2_IP; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 403 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LB2N_IP; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 424 && + Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_get (insn) == 7) + return OPCODE_ABS; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 424 && + Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_get (insn) == 8) + return OPCODE_SRL; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 425 && + Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_get (insn) == 7) + return OPCODE_SRA; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 426 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LBN_IP; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 428 && + Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_get (insn) == 4) + return OPCODE_SLL; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 168) + return OPCODE_SLLI; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 169) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 170) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 171) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 172) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 173) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 174) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 175) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 176) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 177) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 178) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 179) + return OPCODE_IVP_LB2N_I; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 180) + return OPCODE_IVP_LBN_2_I; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 181) + return OPCODE_IVP_LBN_I; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 182) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 183) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 184) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 185) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 186) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 187) + return OPCODE_SRAI; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 202 && + Field_fld_f4_s1_ld_7_7_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVPINT16; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 202 && + Field_fld_f4_s1_ld_7_7_Slot_f4_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVQINT16; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 203 && + Field_fld_f4_s1_ld_7_7_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINT16; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 203 && + Field_fld_f4_s1_ld_7_7_Slot_f4_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVVINT8; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 208 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVR2NX24; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 208 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVR2NX24_0; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 208 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVR2NX24_1; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 208 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNR2NX24; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 209 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNR2NX24_0; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 209 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNR2NX24_1; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 209 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNRNX48_0; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 209 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNRNX48; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 210 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNX48; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 210 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNRN_2X64W; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 210 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNX48_0; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 210 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNRNX48_1; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 211 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRU2NX24; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 211 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRU2NX24_0; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 211 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRN_2X64W; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 211 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNX48_1; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 212 && + Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_get (insn) == 4) + return OPCODE_IVP_MOVVA16; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 212 && + Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_get (insn) == 5) + return OPCODE_IVP_MOVVA32; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 212 && + Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_get (insn) == 6) + return OPCODE_IVP_MOVVA8; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 212 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRU2NX24_1; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_6_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINX16; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 22) + return OPCODE_IVP_CVT32S2NX24LL; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 29) + return OPCODE_IVP_CVT32S2NX24LH; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 21) + return OPCODE_IVP_CVT32S2NX24HL; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 28) + return OPCODE_IVP_CVT32S2NX24HH; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 25) + return OPCODE_IVP_CVT16S2NX24L; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 24) + return OPCODE_IVP_CVT16S2NX24H; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 23) + return OPCODE_IVP_CVT32SNX48L; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 30) + return OPCODE_IVP_CVT32SNX48H; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 26) + return OPCODE_IVP_CVT16U2NX24H; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 31) + return OPCODE_IVP_CVT32UNX48H; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 27) + return OPCODE_IVP_CVT16U2NX24L; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 20) + return OPCODE_IVP_CVT32S24; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 216 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 40) + return OPCODE_IVP_CVT32UNX48L; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 216 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 41) + return OPCODE_IVP_CVT64S48; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 216 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 42) + return OPCODE_IVP_CVT64U96; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 216 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 43) + return OPCODE_IVP_PACKHN_2X64W; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 217 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 40) + return OPCODE_IVP_PACKL2NX24; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 217 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 42) + return OPCODE_IVP_PACKLNX48; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 217 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 41) + return OPCODE_IVP_PACKL2NX24_1; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 217 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 43) + return OPCODE_IVP_PACKLN_2X96; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 218 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 40) + return OPCODE_IVP_PACKMNX48; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 218 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 43) + return OPCODE_IVP_GATHERDNX16; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 218 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 42) + return OPCODE_IVP_GATHERD2NX8_L; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 218 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 41) + return OPCODE_IVP_GATHERD2NX8_H; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 219 && + Field_fld_f4_s1_ld_7_0_Slot_f4_s1_ld_get (insn) == 165) + return OPCODE_IVP_SEQNX16; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 219 && + Field_fld_f4_s1_ld_7_0_Slot_f4_s1_ld_get (insn) == 164) + return OPCODE_IVP_SEQ2NX8; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 219 && + Field_fld_f4_s1_ld_7_0_Slot_f4_s1_ld_get (insn) == 166) + return OPCODE_IVP_SEQN_2X32; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 219 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 40) + return OPCODE_IVP_GATHERDNX8S; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 32) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 33) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 34) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 35) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 36) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 37) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 38) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 39) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 40) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 41) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 51 && + Field_fld_f4_s1_ld_12_10_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 51 && + Field_fld_f4_s1_ld_12_8_Slot_f4_s1_ld_get (insn) == 4) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 51 && + Field_fld_f4_s1_ld_12_4_Slot_f4_s1_ld_get (insn) == 80) + return OPCODE_IVP_LA_PP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 51 && + Field_fld_f4_s1_ld_12_2_Slot_f4_s1_ld_get (insn) == 324) + return OPCODE_IVP_MALIGN; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 54 && + Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 54 && + Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 54 && + Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_get (insn) == 4) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 54 && + Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_get (insn) == 6) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 54 && + Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_get (insn) == 8) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_f4_s1_ld_23_16_Slot_f4_s1_ld_get (insn) == 12) + return OPCODE_ADDI; + if (Field_fld_f4_s1_ld_23_16_Slot_f4_s1_ld_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_fld_f4_s1_ld_23_16_Slot_f4_s1_ld_get (insn) == 14) + return OPCODE_L32I; + if (Field_fld_f4_s1_ld_23_16_Slot_f4_s1_ld_get (insn) == 15) + return OPCODE_MOVI; + if (Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_get (insn) == 1) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_get (insn) == 3) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_get (insn) == 4) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_get (insn) == 5) + return OPCODE_EXTUI; + if (Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_get (insn) == 6886 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTR2N; + if (Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_get (insn) == 6887 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRN; + if (Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_get (insn) == 6888 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRN_2; + if (Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_get (insn) == 6889 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRS2N; + if (Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_get (insn) == 6890 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRSN; + if (Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_get (insn) == 6891 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRSN_2; + if (Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_get (insn) == 6892 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVBA1; + if (Field_fld_f4_s1_ld_23_9_Slot_f4_s1_ld_get (insn) == 3442 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRN_2I; + return XTENSA_UNDEFINED; +} + +static int +Slot_f2_s0_ldst_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f2_s0_ldst_28_11_Slot_f2_s0_ldst_get (insn) == 2708 && + Field_fld_f2_s0_ldst_7_2_Slot_f2_s0_ldst_get (insn) == 7) + return OPCODE_SSAI; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1352 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 15) + return OPCODE_NEG; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1352 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 14) + return OPCODE_ABS; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1353 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 15) + return OPCODE_SRL; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1353 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 14) + return OPCODE_SRA; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1430) + return OPCODE_ADD; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1431) + return OPCODE_ADDX2; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1432) + return OPCODE_ADDX4; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1433) + return OPCODE_MAXU; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1434) + return OPCODE_ADDX8; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1435) + return OPCODE_MIN; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1436) + return OPCODE_AND; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1437) + return OPCODE_MINU; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1438) + return OPCODE_MAX; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1439) + return OPCODE_MOVEQZ; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1441) + return OPCODE_MOVGEZ; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1443) + return OPCODE_MOVLTZ; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1445) + return OPCODE_MOVNEZ; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1447) + return OPCODE_MUL16S; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1449) + return OPCODE_MUL16U; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1451) + return OPCODE_MULL; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1453) + return OPCODE_MULSH; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1455) + return OPCODE_MULUH; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1456) + return OPCODE_OR; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1457) + return OPCODE_SUB; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1458) + return OPCODE_SALT; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1459) + return OPCODE_SUBX2; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1460) + return OPCODE_SALTU; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1461) + return OPCODE_SUBX4; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1462) + return OPCODE_SRC; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1463) + return OPCODE_SUBX8; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1464) + return OPCODE_XOR; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1466) + return OPCODE_CLAMPS; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1468) + return OPCODE_SEXT; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1470) + return OPCODE_SRLI; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1472 && + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (insn) == 7) + return OPCODE_SLL; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 672 && + Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_get (insn) == 3) + return OPCODE_IVP_GATHERANX16; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 673 && + Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_get (insn) == 3) + return OPCODE_IVP_GATHERANX8U; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 674 && + Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_get (insn) == 3) + return OPCODE_IVP_GATHERAN_2X32; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 675 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 12) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 675 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 15) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 675 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 13) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 675 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 14) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 676 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 12) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 677 && + Field_fld_f2_s0_ldst_7_2_Slot_f2_s0_ldst_get (insn) == 3) + return OPCODE_IVP_MOVGATHERD; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 682) + return OPCODE_IVP_SS2NX8_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 683) + return OPCODE_IVP_SS2NX8_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 684) + return OPCODE_IVP_SSNX16_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 685) + return OPCODE_IVP_SSNX16_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 686) + return OPCODE_IVP_SSNX8S_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 687) + return OPCODE_IVP_SSNX8S_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 688) + return OPCODE_IVP_SSN_2X16S_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 689) + return OPCODE_IVP_SSN_2X16S_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 690) + return OPCODE_IVP_SSN_2X32_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 691) + return OPCODE_IVP_SSN_2X32_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 692) + return OPCODE_IVP_SV2NX8_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 693) + return OPCODE_IVP_SV2NX8_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 694) + return OPCODE_IVP_SVNX8S_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 695) + return OPCODE_IVP_SVNX8S_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 696) + return OPCODE_IVP_SVNX8U_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 697) + return OPCODE_IVP_SVNX8U_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 698) + return OPCODE_IVP_SVN_2X16S_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 699) + return OPCODE_IVP_SVN_2X16S_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 700) + return OPCODE_IVP_SVN_2X16U_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 701) + return OPCODE_IVP_SVN_2X16U_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 702) + return OPCODE_SLLI; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 703) + return OPCODE_IVP_SS2NX8_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 704) + return OPCODE_IVP_SSNX16_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 705) + return OPCODE_IVP_SSNX8S_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 706) + return OPCODE_IVP_SSN_2X16S_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 707) + return OPCODE_IVP_SSN_2X32_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 708) + return OPCODE_IVP_SV2NX8_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 709) + return OPCODE_IVP_SVNX8S_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 710) + return OPCODE_IVP_SVNX8U_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 711) + return OPCODE_IVP_SVN_2X16S_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 712) + return OPCODE_IVP_SVN_2X16U_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 713) + return OPCODE_SRAI; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 714) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f2_s0_ldst_28_14_Slot_f2_s0_ldst_get (insn) == 340) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 158) + return OPCODE_IVP_SAV2NX8_XP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 159) + return OPCODE_IVP_SAVNX8S_XP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 160) + return OPCODE_IVP_SAVNX8U_XP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 161) + return OPCODE_IVP_SAVN_2X16S_XP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 162) + return OPCODE_IVP_SAVN_2X16U_XP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 163) + return OPCODE_IVP_SS2NX8_I; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 164) + return OPCODE_IVP_SSNX16_I; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 165) + return OPCODE_IVP_SSNX8S_I; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 166) + return OPCODE_IVP_SSN_2X16S_I; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 167) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 180 && + Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_get (insn) == 15) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 181 && + Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_get (insn) == 15) + return OPCODE_IVP_SALIGN_IP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 184 && + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SA2NX8_IP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 184 && + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (insn) == 4) + return OPCODE_IVP_SANX8U_IP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 184 && + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (insn) == 6) + return OPCODE_IVP_SAN_2X16U_IP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 184 && + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (insn) == 5) + return OPCODE_IVP_SAN_2X16S_IP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 185 && + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SANX8S_IP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 192 && + Field_fld_f2_s0_ldst_12_4_Slot_f2_s0_ldst_get (insn) == 48) + return OPCODE_IVP_LA_PP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 192 && + Field_fld_f2_s0_ldst_12_4_Slot_f2_s0_ldst_get (insn) == 49) + return OPCODE_IVP_SAPOS_FP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 192 && + Field_fld_f2_s0_ldst_12_2_Slot_f2_s0_ldst_get (insn) == 204) + return OPCODE_IVP_MALIGN; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 192 && + Field_fld_f2_s0_ldst_12_0_Slot_f2_s0_ldst_get (insn) == 820) + return OPCODE_IVP_ZALIGN; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 54) + return OPCODE_ADDI; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 55) + return OPCODE_ADDMI; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 56) + return OPCODE_IVP_SV2NX8T_X; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 57) + return OPCODE_IVP_SV2NX8T_XP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 58) + return OPCODE_IVP_SVNX8ST_X; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 59) + return OPCODE_IVP_SVNX8ST_XP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 60) + return OPCODE_IVP_SVNX8UT_X; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 61) + return OPCODE_IVP_SVNX8UT_XP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 62) + return OPCODE_IVP_SVN_2X16ST_X; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 63) + return OPCODE_IVP_SVN_2X16ST_XP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 64) + return OPCODE_IVP_SVN_2X16UT_X; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 65) + return OPCODE_IVP_SVN_2X16UT_XP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 66) + return OPCODE_L16SI; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 67) + return OPCODE_L16UI; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 68) + return OPCODE_L32I; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 69) + return OPCODE_L8UI; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 70) + return OPCODE_S16I; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 71) + return OPCODE_S32I; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 72) + return OPCODE_S8I; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 73) + return OPCODE_IVP_SV2NX8T_IP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 74) + return OPCODE_IVP_SVNX8ST_IP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 75) + return OPCODE_IVP_SVNX8UT_IP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 76) + return OPCODE_IVP_SVN_2X16ST_IP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 77) + return OPCODE_IVP_SVN_2X16UT_IP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 78) + return OPCODE_MOVI; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 84 && + Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_get (insn) == 1) + return OPCODE_IVP_GATHERANX8UT; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 84 && + Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_get (insn) == 0) + return OPCODE_IVP_GATHERANX16T; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 84 && + Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_get (insn) == 2) + return OPCODE_IVP_GATHERAN_2X32T; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 90 && + Field_fld_f2_s0_ldst_12_10_Slot_f2_s0_ldst_get (insn) == 2) + return OPCODE_IVP_SBN_I; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 90 && + Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_get (insn) == 14) + return OPCODE_IVP_SBN_IP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 90 && + Field_fld_f2_s0_ldst_12_10_Slot_f2_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SBN_2_I; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 90 && + Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_get (insn) == 13) + return OPCODE_IVP_SBN_2_IP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 90 && + Field_fld_f2_s0_ldst_12_10_Slot_f2_s0_ldst_get (insn) == 0) + return OPCODE_IVP_SB2N_I; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 90 && + Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_get (insn) == 12) + return OPCODE_IVP_SB2N_IP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 92 && + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 92 && + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 92 && + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_get (insn) == 20) + return OPCODE_IVP_SSN_2X32_I; + if (Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_get (insn) == 21) + return OPCODE_IVP_SV2NX8_I; + if (Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_get (insn) == 22) + return OPCODE_IVP_SVNX8S_I; + if (Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_get (insn) == 23) + return OPCODE_IVP_SVNX8U_I; + if (Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_get (insn) == 24) + return OPCODE_IVP_SVN_2X16S_I; + if (Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_get (insn) == 25) + return OPCODE_IVP_SVN_2X16U_I; + if (Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_get (insn) == 26) + return OPCODE_EXTUI; + if (Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get (insn) == 4) + return OPCODE_IVP_SV2NX8T_I; + if (Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get (insn) == 5) + return OPCODE_IVP_SVNX8ST_I; + if (Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get (insn) == 6) + return OPCODE_IVP_SVNX8UT_I; + if (Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SVN_2X16ST_I; + if (Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get (insn) == 8) + return OPCODE_IVP_SVN_2X16UT_I; + if (Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get (insn) == 9) + return OPCODE_J; + if (Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get (insn) == 24 && + Field_fld_f2_s0_ldst_15_15_Slot_f2_s0_ldst_get (insn) == 0 && + Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get (insn) == 24 && + Field_fld_f2_s0_ldst_15_15_Slot_f2_s0_ldst_get (insn) == 0 && + Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SALIGN_I; + if (Field_fld_f2_s0_ldst_28_20_Slot_f2_s0_ldst_get (insn) == 0) + return OPCODE_CONST16; + if (Field_fld_f2_s0_ldst_28_4_Slot_f2_s0_ldst_get (insn) == 393266) + return OPCODE_SSA8L; + if (Field_fld_f2_s0_ldst_28_4_Slot_f2_s0_ldst_get (insn) == 393267 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 5) + return OPCODE_IVP_SCATTERW; + if (Field_fld_f2_s0_ldst_28_4_Slot_f2_s0_ldst_get (insn) == 393778) + return OPCODE_SSL; + if (Field_fld_f2_s0_ldst_28_4_Slot_f2_s0_ldst_get (insn) == 393779 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 5) + return OPCODE_NOP; + if (Field_fld_f2_s0_ldst_28_4_Slot_f2_s0_ldst_get (insn) == 394290) + return OPCODE_SSR; + if (Field_fld_f2_s0_ldst_28_8_Slot_f2_s0_ldst_get (insn) == 24578) + return OPCODE_NSA; + if (Field_fld_f2_s0_ldst_28_8_Slot_f2_s0_ldst_get (insn) == 24610) + return OPCODE_NSAU; + return XTENSA_UNDEFINED; +} + +static int +Slot_n1_s0_ldst_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 1974 && + Field_fld_n1_s0_ldst_3_0_Slot_n1_s0_ldst_get (insn) == 13) + return OPCODE_NEG; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 1974 && + Field_fld_n1_s0_ldst_3_0_Slot_n1_s0_ldst_get (insn) == 12) + return OPCODE_ABS; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 1974 && + Field_fld_n1_s0_ldst_3_0_Slot_n1_s0_ldst_get (insn) == 15) + return OPCODE_SRL; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 1974 && + Field_fld_n1_s0_ldst_3_0_Slot_n1_s0_ldst_get (insn) == 14) + return OPCODE_SRA; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2040) + return OPCODE_MIN; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2041) + return OPCODE_MOVLTZ; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2042) + return OPCODE_MINU; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2043) + return OPCODE_MOVNEZ; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2044) + return OPCODE_MOVEQZ; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2045) + return OPCODE_MUL16S; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2046) + return OPCODE_MOVGEZ; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2047) + return OPCODE_MUL16U; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2049) + return OPCODE_ADD; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2051) + return OPCODE_ADDX2; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2053) + return OPCODE_ADDX4; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2055) + return OPCODE_ADDX8; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2057) + return OPCODE_AND; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2059) + return OPCODE_L32I_N; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2061) + return OPCODE_MAX; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2063) + return OPCODE_MAXU; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2064) + return OPCODE_MULL; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2065) + return OPCODE_S32I_N; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2066) + return OPCODE_MULSH; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2067) + return OPCODE_SALT; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2068) + return OPCODE_MULUH; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2069) + return OPCODE_SALTU; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2070) + return OPCODE_OR; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2071) + return OPCODE_SRC; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2072) + return OPCODE_SUB; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2073) + return OPCODE_XOR; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2074) + return OPCODE_SUBX2; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2075) + return OPCODE_CLAMPS; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2076) + return OPCODE_SUBX4; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2077) + return OPCODE_SEXT; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2078) + return OPCODE_SUBX8; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2079) + return OPCODE_SRLI; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2082 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 14) + return OPCODE_SLL; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 980) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 981) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 982) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 983) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 984 && + Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_get (insn) == 3) + return OPCODE_IVP_GATHERANX16; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 985 && + Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_get (insn) == 3) + return OPCODE_IVP_GATHERANX8U; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 986 && + Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_get (insn) == 3) + return OPCODE_IVP_GATHERAN_2X32; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 992) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 993) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 994) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 995) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 996) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 997) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 998) + return OPCODE_IVP_SV2NX8_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 999) + return OPCODE_IVP_SV2NX8_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1000) + return OPCODE_IVP_SVNX8S_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1001) + return OPCODE_IVP_SVNX8S_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1002) + return OPCODE_IVP_SVNX8U_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1003) + return OPCODE_IVP_SVNX8U_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1004) + return OPCODE_IVP_SVN_2X16S_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1005) + return OPCODE_IVP_SVN_2X16S_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1006) + return OPCODE_IVP_SVN_2X16U_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1007) + return OPCODE_IVP_SVN_2X16U_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1008) + return OPCODE_SLLI; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1009) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1010) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1011) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1012) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1013) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1014) + return OPCODE_IVP_SV2NX8_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1015) + return OPCODE_IVP_SVNX8S_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1016) + return OPCODE_IVP_SVNX8U_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1017) + return OPCODE_IVP_SVN_2X16S_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1018) + return OPCODE_IVP_SVN_2X16U_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1019) + return OPCODE_SRAI; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1040 && + Field_fld_n1_s0_ldst_7_6_Slot_n1_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SHFL2NX8I_S0; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1041 && + Field_fld_n1_s0_ldst_7_5_Slot_n1_s0_ldst_get (insn) == 6) + return OPCODE_IVP_MOVVV; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1041 && + Field_fld_n1_s0_ldst_7_2_Slot_n1_s0_ldst_get (insn) == 60) + return OPCODE_IVP_MOVGATHERD; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 230) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 231) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 232) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 233) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 234) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 235) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 236) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 237) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 238) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 239) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 240) + return OPCODE_IVP_SAV2NX8_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 241) + return OPCODE_IVP_SAVNX8S_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 242) + return OPCODE_IVP_SAVNX8U_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 243) + return OPCODE_IVP_SAVN_2X16S_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 244) + return OPCODE_IVP_SAVN_2X16U_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 5) + return OPCODE_IVP_SA2NX8_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 1) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 2) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SANX8U_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 6) + return OPCODE_IVP_SANX8S_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 3) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 4) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 9) + return OPCODE_IVP_SAN_2X16U_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 8) + return OPCODE_IVP_SAN_2X16S_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 264 && + Field_fld_n1_s0_ldst_12_8_Slot_n1_s0_ldst_get (insn) == 2) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 264 && + Field_fld_n1_s0_ldst_12_8_Slot_n1_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SALIGN_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 266 && + Field_fld_n1_s0_ldst_12_4_Slot_n1_s0_ldst_get (insn) == 48) + return OPCODE_IVP_LA_PP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 266 && + Field_fld_n1_s0_ldst_12_4_Slot_n1_s0_ldst_get (insn) == 49) + return OPCODE_IVP_SAPOS_FP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 266 && + Field_fld_n1_s0_ldst_12_2_Slot_n1_s0_ldst_get (insn) == 200) + return OPCODE_IVP_MALIGN; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 266 && + Field_fld_n1_s0_ldst_12_0_Slot_n1_s0_ldst_get (insn) == 804) + return OPCODE_IVP_ZALIGN; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 78) + return OPCODE_ADDI; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 79) + return OPCODE_ADDMI; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 80) + return OPCODE_IVP_LV2NX8T_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 81) + return OPCODE_IVP_LV2NX8T_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 82) + return OPCODE_IVP_LVNX8ST_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 83) + return OPCODE_IVP_LVNX8ST_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 84) + return OPCODE_IVP_LVNX8UT_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 85) + return OPCODE_IVP_LVNX8UT_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 86) + return OPCODE_IVP_LVN_2X16ST_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 87) + return OPCODE_IVP_LVN_2X16ST_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 88) + return OPCODE_IVP_LVN_2X16UT_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 89) + return OPCODE_IVP_LVN_2X16UT_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 90) + return OPCODE_IVP_SV2NX8T_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 91) + return OPCODE_IVP_SV2NX8T_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 92) + return OPCODE_IVP_SVNX8ST_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 93) + return OPCODE_IVP_SVNX8ST_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 94) + return OPCODE_IVP_SVNX8UT_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 95) + return OPCODE_IVP_SVNX8UT_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 96) + return OPCODE_IVP_SVN_2X16ST_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 97) + return OPCODE_IVP_SVN_2X16ST_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 98) + return OPCODE_IVP_SVN_2X16UT_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 99) + return OPCODE_IVP_SVN_2X16UT_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 100) + return OPCODE_L16SI; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 101) + return OPCODE_L16UI; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 102) + return OPCODE_L8UI; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 103) + return OPCODE_S16I; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 104) + return OPCODE_IVP_LV2NX8T_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 105) + return OPCODE_IVP_LVNX8ST_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 106) + return OPCODE_IVP_LVNX8UT_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 107) + return OPCODE_IVP_LVN_2X16ST_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 108) + return OPCODE_IVP_LVN_2X16UT_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 109) + return OPCODE_IVP_SV2NX8T_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 110) + return OPCODE_IVP_SVNX8ST_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 111) + return OPCODE_IVP_SVNX8UT_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 112) + return OPCODE_IVP_SVN_2X16ST_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 113) + return OPCODE_IVP_SVN_2X16UT_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 114) + return OPCODE_MOVI; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 123 && + Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_get (insn) == 1) + return OPCODE_IVP_GATHERANX8UT; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 123 && + Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_get (insn) == 0) + return OPCODE_IVP_GATHERANX16T; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 123 && + Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_get (insn) == 2) + return OPCODE_IVP_GATHERAN_2X32T; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 128 && + Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_get (insn) == 0 && + Field_fld_n1_s0_ldst_7_6_Slot_n1_s0_ldst_get (insn) == 2) + return OPCODE_IVP_SBN_I; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 128 && + Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_get (insn) == 0 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 14) + return OPCODE_IVP_SBN_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 128 && + Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_get (insn) == 0 && + Field_fld_n1_s0_ldst_7_6_Slot_n1_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SBN_2_I; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 128 && + Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_get (insn) == 0 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 13) + return OPCODE_IVP_SBN_2_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 128 && + Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_get (insn) == 0 && + Field_fld_n1_s0_ldst_7_6_Slot_n1_s0_ldst_get (insn) == 0) + return OPCODE_IVP_SB2N_I; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 128 && + Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_get (insn) == 0 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 12) + return OPCODE_IVP_SB2N_IP; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 28) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 29) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 30) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 31) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 32) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 33) + return OPCODE_IVP_SV2NX8_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 34) + return OPCODE_IVP_SVNX8S_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 35) + return OPCODE_IVP_SVNX8U_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 36) + return OPCODE_IVP_SVN_2X16S_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 37) + return OPCODE_IVP_SVN_2X16U_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 38) + return OPCODE_EXTUI; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 4) + return OPCODE_IVP_LV2NX8T_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 5) + return OPCODE_IVP_LVNX8ST_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 6) + return OPCODE_IVP_LVNX8UT_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 7) + return OPCODE_IVP_LVN_2X16ST_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 8) + return OPCODE_IVP_LVN_2X16UT_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 9) + return OPCODE_IVP_SV2NX8T_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 10) + return OPCODE_IVP_SVNX8ST_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 11) + return OPCODE_IVP_SVNX8UT_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 12) + return OPCODE_IVP_SVN_2X16ST_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 13) + return OPCODE_IVP_SVN_2X16UT_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 33 && + Field_fld_n1_s0_ldst_15_15_Slot_n1_s0_ldst_get (insn) == 0 && + Field_fld_n1_s0_ldst_12_8_Slot_n1_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 33 && + Field_fld_n1_s0_ldst_15_15_Slot_n1_s0_ldst_get (insn) == 0 && + Field_fld_n1_s0_ldst_12_8_Slot_n1_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SALIGN_I; + if (Field_fld_n1_s0_ldst_26_2_Slot_n1_s0_ldst_get (insn) == 2179273 && + Field_fld_n1_s0_ldst_1_0_Slot_n1_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SCATTERW; + if (Field_fld_n1_s0_ldst_26_2_Slot_n1_s0_ldst_get (insn) == 2181321 && + Field_fld_n1_s0_ldst_1_0_Slot_n1_s0_ldst_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_n1_s0_ldst_26_20_Slot_n1_s0_ldst_get (insn) == 0) + return OPCODE_CONST16; + if (Field_fld_n1_s0_ldst_26_4_Slot_n1_s0_ldst_get (insn) == 533294) + return OPCODE_SSA8L; + if (Field_fld_n1_s0_ldst_26_4_Slot_n1_s0_ldst_get (insn) == 533310) + return OPCODE_SSL; + if (Field_fld_n1_s0_ldst_26_4_Slot_n1_s0_ldst_get (insn) == 533326) + return OPCODE_SSR; + if (Field_fld_n1_s0_ldst_26_8_Slot_n1_s0_ldst_get (insn) == 34050) + return OPCODE_NSA; + if (Field_fld_n1_s0_ldst_26_8_Slot_n1_s0_ldst_get (insn) == 34082) + return OPCODE_NSAU; + if (Field_fld_n1_s0_ldst_26_9_Slot_n1_s0_ldst_get (insn) == 16664 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 14) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_n2_s0_ldst_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_n2_s0_ldst_29_10_Slot_n2_s0_ldst_get (insn) == 10190 && + Field_fld_n2_s0_ldst_8_4_Slot_n2_s0_ldst_get (insn) == 15) + return OPCODE_SSAI; + if (Field_fld_n2_s0_ldst_29_11_Slot_n2_s0_ldst_get (insn) == 5089) + return OPCODE_IVP_GATHERANX16; + if (Field_fld_n2_s0_ldst_29_11_Slot_n2_s0_ldst_get (insn) == 5093) + return OPCODE_IVP_GATHERANX8U; + if (Field_fld_n2_s0_ldst_29_11_Slot_n2_s0_ldst_get (insn) == 5094 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 15) + return OPCODE_IVP_MOVGATHERD; + if (Field_fld_n2_s0_ldst_29_11_Slot_n2_s0_ldst_get (insn) == 5097) + return OPCODE_IVP_GATHERAN_2X32; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2545 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 15) + return OPCODE_SLL; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2620) + return OPCODE_ADD; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2621) + return OPCODE_ADDX4; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2622) + return OPCODE_ADDX2; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2623) + return OPCODE_ADDX8; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2624) + return OPCODE_AND; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2625) + return OPCODE_MIN; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2626) + return OPCODE_L32I_N; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2627) + return OPCODE_MINU; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2628) + return OPCODE_MAX; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2629) + return OPCODE_MOVEQZ; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2630) + return OPCODE_MAXU; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2631) + return OPCODE_MOVGEZ; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2632) + return OPCODE_MOVLTZ; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2633) + return OPCODE_MULL; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2634) + return OPCODE_MOVNEZ; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2635) + return OPCODE_MULSH; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2636) + return OPCODE_MUL16S; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2637) + return OPCODE_MULUH; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2638) + return OPCODE_MUL16U; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2639) + return OPCODE_OR; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2640) + return OPCODE_S32I_N; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2641) + return OPCODE_SUB; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2642) + return OPCODE_SALT; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2643) + return OPCODE_SUBX2; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2644) + return OPCODE_SALTU; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2645) + return OPCODE_SUBX4; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2646) + return OPCODE_SRC; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2647) + return OPCODE_SUBX8; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2648) + return OPCODE_XOR; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2649 && + Field_fld_n2_s0_ldst_3_0_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2649 && + Field_fld_n2_s0_ldst_3_0_Slot_n2_s0_ldst_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2649 && + Field_fld_n2_s0_ldst_3_0_Slot_n2_s0_ldst_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2649 && + Field_fld_n2_s0_ldst_3_0_Slot_n2_s0_ldst_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2650) + return OPCODE_CLAMPS; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2652) + return OPCODE_SEXT; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2654) + return OPCODE_SRLI; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1206) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1207) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1280) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1281) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1282) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1283) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1284) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1285) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1286) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1287) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1288) + return OPCODE_IVP_SV2NX8_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1289) + return OPCODE_IVP_SV2NX8_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1290) + return OPCODE_IVP_SVNX8S_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1291) + return OPCODE_IVP_SVNX8S_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1292) + return OPCODE_IVP_SVNX8U_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1293) + return OPCODE_IVP_SVNX8U_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1294) + return OPCODE_IVP_SVN_2X16S_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1295) + return OPCODE_IVP_SVN_2X16S_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1296) + return OPCODE_IVP_SVN_2X16U_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1297) + return OPCODE_IVP_SVN_2X16U_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1298) + return OPCODE_SLLI; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1299) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1300) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1301) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1302) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1303) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1304) + return OPCODE_IVP_SV2NX8_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1305) + return OPCODE_IVP_SVNX8S_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1306) + return OPCODE_IVP_SVNX8U_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1307) + return OPCODE_IVP_SVN_2X16S_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1308) + return OPCODE_IVP_SVN_2X16U_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1309) + return OPCODE_SRAI; + if (Field_fld_n2_s0_ldst_29_14_Slot_n2_s0_ldst_get (insn) == 598) + return OPCODE_IVP_SCATTER2NX8_H; + if (Field_fld_n2_s0_ldst_29_14_Slot_n2_s0_ldst_get (insn) == 599) + return OPCODE_IVP_SCATTER2NX8_L; + if (Field_fld_n2_s0_ldst_29_14_Slot_n2_s0_ldst_get (insn) == 600) + return OPCODE_IVP_SCATTERNX16; + if (Field_fld_n2_s0_ldst_29_14_Slot_n2_s0_ldst_get (insn) == 601) + return OPCODE_IVP_SCATTERNX8U; + if (Field_fld_n2_s0_ldst_29_14_Slot_n2_s0_ldst_get (insn) == 602) + return OPCODE_IVP_SCATTERN_2X32; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 284) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 285) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 286) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 287) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 288) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 289) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 290) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 291) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 292) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 293) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 294) + return OPCODE_IVP_SAV2NX8_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 295) + return OPCODE_IVP_SAVNX8S_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 296) + return OPCODE_IVP_SAVNX8U_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 297) + return OPCODE_IVP_SAVN_2X16S_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 298) + return OPCODE_IVP_SAVN_2X16U_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 319 && + Field_fld_n2_s0_ldst_12_8_Slot_n2_s0_ldst_get (insn) == 8) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 319 && + Field_fld_n2_s0_ldst_12_8_Slot_n2_s0_ldst_get (insn) == 10) + return OPCODE_IVP_SALIGN_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 319 && + Field_fld_n2_s0_ldst_12_11_Slot_n2_s0_ldst_get (insn) == 2 && + Field_fld_n2_s0_ldst_8_0_Slot_n2_s0_ldst_get (insn) == 240) + return OPCODE_IVP_MALIGN; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 319 && + Field_fld_n2_s0_ldst_12_0_Slot_n2_s0_ldst_get (insn) == 4337) + return OPCODE_IVP_ZALIGN; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_9_5_Slot_n2_s0_ldst_get (insn) == 22) + return OPCODE_IVP_MOVVV; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_12_4_Slot_n2_s0_ldst_get (insn) == 46) + return OPCODE_IVP_LA_PP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_12_4_Slot_n2_s0_ldst_get (insn) == 110) + return OPCODE_IVP_SAPOS_FP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 5) + return OPCODE_IVP_SA2NX8_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 2) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SANX8U_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 6) + return OPCODE_IVP_SANX8S_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 3) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 4) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 9) + return OPCODE_IVP_SAN_2X16U_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 8) + return OPCODE_IVP_SAN_2X16S_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_9_6_Slot_n2_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SHFL2NX8I_S0; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 104) + return OPCODE_ADDI; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 105) + return OPCODE_ADDMI; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 106) + return OPCODE_IVP_LV2NX8T_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 107) + return OPCODE_IVP_LV2NX8T_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 108) + return OPCODE_IVP_LVNX8ST_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 109) + return OPCODE_IVP_LVNX8ST_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 110) + return OPCODE_IVP_LVNX8UT_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 111) + return OPCODE_IVP_LVNX8UT_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 112) + return OPCODE_IVP_LVN_2X16ST_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 113) + return OPCODE_IVP_LVN_2X16ST_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 114) + return OPCODE_IVP_LVN_2X16UT_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 115) + return OPCODE_IVP_LVN_2X16UT_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 116) + return OPCODE_IVP_SV2NX8T_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 117) + return OPCODE_IVP_SV2NX8T_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 118) + return OPCODE_IVP_SVNX8ST_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 119) + return OPCODE_IVP_SVNX8ST_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 120) + return OPCODE_IVP_SVNX8UT_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 121) + return OPCODE_IVP_SVNX8UT_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 122) + return OPCODE_IVP_SVN_2X16ST_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 123) + return OPCODE_IVP_SVN_2X16ST_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 124) + return OPCODE_IVP_SVN_2X16UT_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 125) + return OPCODE_IVP_SVN_2X16UT_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 126) + return OPCODE_L16SI; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 127) + return OPCODE_L16UI; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 128) + return OPCODE_L8UI; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 129) + return OPCODE_S16I; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 130) + return OPCODE_S8I; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 131) + return OPCODE_IVP_LV2NX8T_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 132) + return OPCODE_IVP_LVNX8ST_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 133) + return OPCODE_IVP_LVNX8UT_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 134) + return OPCODE_IVP_LVN_2X16ST_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 135) + return OPCODE_IVP_LVN_2X16UT_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 136) + return OPCODE_IVP_SV2NX8T_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 137) + return OPCODE_IVP_SVNX8ST_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 138) + return OPCODE_IVP_SVNX8UT_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 139) + return OPCODE_IVP_SVN_2X16ST_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 140) + return OPCODE_IVP_SVN_2X16UT_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 141) + return OPCODE_MOVI; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 151 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 4) + return OPCODE_IVP_LENX16; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 151 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_IVP_EQNX16; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 151 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 7) + return OPCODE_IVP_LEUNX16; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 151 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 3) + return OPCODE_IVP_LE2NX8; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 151 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 151 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 6) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 151 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 5) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 151 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 2) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 152 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 6) + return OPCODE_IVP_LTNX16; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 152 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 5) + return OPCODE_IVP_LT2NX8; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 152 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 7) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 152 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 4) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 153 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 5) + return OPCODE_IVP_LTUNX16; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 153 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 7) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 153 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 4) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 153 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 6) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 154 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 0) + return OPCODE_IVP_NEQNX16; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 154 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 159 && + Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_get (insn) == 1 && + Field_fld_n2_s0_ldst_7_6_Slot_n2_s0_ldst_get (insn) == 2) + return OPCODE_IVP_SBN_I; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 159 && + Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_get (insn) == 1 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 14) + return OPCODE_IVP_SBN_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 159 && + Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_get (insn) == 1 && + Field_fld_n2_s0_ldst_7_6_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SBN_2_I; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 159 && + Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_get (insn) == 1 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 13) + return OPCODE_IVP_SBN_2_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 159 && + Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_get (insn) == 1 && + Field_fld_n2_s0_ldst_7_6_Slot_n2_s0_ldst_get (insn) == 0) + return OPCODE_IVP_SB2N_I; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 159 && + Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_get (insn) == 1 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 12) + return OPCODE_IVP_SB2N_IP; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 36) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 37) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 38) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 39) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 40) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 41) + return OPCODE_IVP_SV2NX8_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 42) + return OPCODE_IVP_SVNX8S_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 43) + return OPCODE_IVP_SVNX8U_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 44) + return OPCODE_IVP_SVN_2X16S_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 45) + return OPCODE_IVP_SVN_2X16U_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 46) + return OPCODE_EXTUI; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 47) + return OPCODE_IVP_SCATTER2NX8T_H; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 48) + return OPCODE_IVP_SCATTER2NX8T_L; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 49) + return OPCODE_IVP_SCATTERNX16T; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 50) + return OPCODE_IVP_SCATTERNX8UT; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 51) + return OPCODE_IVP_SCATTERN_2X32T; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 76 && + Field_fld_n2_s0_ldst_13_11_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_IVP_GATHERANX8UT; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 76 && + Field_fld_n2_s0_ldst_13_11_Slot_n2_s0_ldst_get (insn) == 0) + return OPCODE_IVP_GATHERANX16T; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 76 && + Field_fld_n2_s0_ldst_13_11_Slot_n2_s0_ldst_get (insn) == 4) + return OPCODE_IVP_GATHERAN_2X32T; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 8) + return OPCODE_IVP_LV2NX8T_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 9) + return OPCODE_IVP_LVNX8ST_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 10) + return OPCODE_IVP_LVNX8UT_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 11) + return OPCODE_IVP_LVN_2X16ST_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 12) + return OPCODE_IVP_LVN_2X16UT_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 13) + return OPCODE_IVP_SV2NX8T_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 14) + return OPCODE_IVP_SVNX8ST_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 15) + return OPCODE_IVP_SVNX8UT_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 16) + return OPCODE_IVP_SVN_2X16ST_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 17) + return OPCODE_IVP_SVN_2X16UT_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 42 && + Field_fld_n2_s0_ldst_15_15_Slot_n2_s0_ldst_get (insn) == 0 && + Field_fld_n2_s0_ldst_12_8_Slot_n2_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 42 && + Field_fld_n2_s0_ldst_15_15_Slot_n2_s0_ldst_get (insn) == 0 && + Field_fld_n2_s0_ldst_12_8_Slot_n2_s0_ldst_get (insn) == 4) + return OPCODE_IVP_SALIGN_I; + if (Field_fld_n2_s0_ldst_29_20_Slot_n2_s0_ldst_get (insn) == 0) + return OPCODE_CONST16; + if (Field_fld_n2_s0_ldst_29_20_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SEL2NX8I_S0; + if (Field_fld_n2_s0_ldst_29_5_Slot_n2_s0_ldst_get (insn) == 326095 && + Field_fld_n2_s0_ldst_4_4_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_SSR; + if (Field_fld_n2_s0_ldst_29_5_Slot_n2_s0_ldst_get (insn) == 326119 && + Field_fld_n2_s0_ldst_4_4_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_SSA8L; + if (Field_fld_n2_s0_ldst_29_5_Slot_n2_s0_ldst_get (insn) == 326135 && + Field_fld_n2_s0_ldst_4_4_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_SSL; + if (Field_fld_n2_s0_ldst_29_5_Slot_n2_s0_ldst_get (insn) == 326807 && + Field_fld_n2_s0_ldst_4_0_Slot_n2_s0_ldst_get (insn) == 17) + return OPCODE_IVP_SCATTERW; + if (Field_fld_n2_s0_ldst_29_5_Slot_n2_s0_ldst_get (insn) == 327063 && + Field_fld_n2_s0_ldst_4_0_Slot_n2_s0_ldst_get (insn) == 17) + return OPCODE_NOP; + if (Field_fld_n2_s0_ldst_29_8_Slot_n2_s0_ldst_get (insn) == 40844) + return OPCODE_NSA; + if (Field_fld_n2_s0_ldst_29_8_Slot_n2_s0_ldst_get (insn) == 40846) + return OPCODE_NSAU; + return XTENSA_UNDEFINED; +} + +static int +Slot_f4_s0_ld_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67018) + return OPCODE_ADD; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67019) + return OPCODE_ADDX2; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67020) + return OPCODE_ADDX4; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67021) + return OPCODE_AND; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67022) + return OPCODE_ADDX8; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67023) + return OPCODE_MAX; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67024) + return OPCODE_MAXU; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67025) + return OPCODE_MOVGEZ; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67026) + return OPCODE_MIN; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67027) + return OPCODE_MOVLTZ; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67028) + return OPCODE_MINU; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67029) + return OPCODE_MOVNEZ; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67030) + return OPCODE_MOVEQZ; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67031) + return OPCODE_MUL16S; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67032) + return OPCODE_MUL16U; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67033) + return OPCODE_OR; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67034) + return OPCODE_MULL; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67035) + return OPCODE_SALT; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67036) + return OPCODE_MULSH; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67037) + return OPCODE_SALTU; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67038) + return OPCODE_MULUH; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67039) + return OPCODE_SRC; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67040) + return OPCODE_SUB; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67041) + return OPCODE_XOR; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67042) + return OPCODE_SUBX2; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67043) + return OPCODE_CLAMPS; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67044) + return OPCODE_SUBX4; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67045) + return OPCODE_SEXT; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67046) + return OPCODE_SUBX8; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67047) + return OPCODE_SRLI; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67048 && + Field_fld_f4_s0_ld_3_0_Slot_f4_s0_ld_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67048 && + Field_fld_f4_s0_ld_3_0_Slot_f4_s0_ld_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67048 && + Field_fld_f4_s0_ld_3_0_Slot_f4_s0_ld_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67048 && + Field_fld_f4_s0_ld_3_0_Slot_f4_s0_ld_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67056 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 7) + return OPCODE_SLL; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33468) + return OPCODE_IVP_LS2NX8_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33469) + return OPCODE_IVP_LS2NX8_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33470) + return OPCODE_IVP_LSNX16_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33471) + return OPCODE_IVP_LSNX16_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33472) + return OPCODE_IVP_LSNX8S_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33473) + return OPCODE_IVP_LSNX8S_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33474) + return OPCODE_IVP_LSN_2X16S_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33475) + return OPCODE_IVP_LSN_2X16S_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33476) + return OPCODE_IVP_LSN_2X32_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33477) + return OPCODE_IVP_LSN_2X32_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33478) + return OPCODE_IVP_LSR2NX8_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33479) + return OPCODE_IVP_LSR2NX8_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33480) + return OPCODE_IVP_LSRNX16_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33481) + return OPCODE_IVP_LSRNX16_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33482) + return OPCODE_IVP_LSRN_2X32_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33483) + return OPCODE_IVP_LSRN_2X32_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33484) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33485) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33486) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33487) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33488) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33489) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33490) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33491) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33492) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33493) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33494) + return OPCODE_SLLI; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33495) + return OPCODE_IVP_LS2NX8_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33496) + return OPCODE_IVP_LSNX16_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33497) + return OPCODE_IVP_LSNX8S_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33498) + return OPCODE_IVP_LSN_2X16S_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33499) + return OPCODE_IVP_LSN_2X32_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33500) + return OPCODE_IVP_LSR2NX8_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33501) + return OPCODE_IVP_LSRNX16_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33502) + return OPCODE_IVP_LSRN_2X32_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33503) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33504) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33505) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33506) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33507) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33508) + return OPCODE_SRAI; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8350) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8351) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8352) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8353) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8354) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8355) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8356) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8357) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8358) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8359) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8360) + return OPCODE_IVP_LS2NX8_I; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8361) + return OPCODE_IVP_LSNX16_I; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8362) + return OPCODE_IVP_LSNX8S_I; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8363) + return OPCODE_IVP_LSN_2X16S_I; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8364) + return OPCODE_IVP_LSR2NX8_I; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8365) + return OPCODE_IVP_LSRNX16_I; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8366) + return OPCODE_IVP_LSRN_2X32_I; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8382 && + Field_fld_f4_s0_ld_12_4_Slot_f4_s0_ld_get (insn) == 263) + return OPCODE_IVP_LA_PP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8382 && + Field_fld_f4_s0_ld_12_2_Slot_f4_s0_ld_get (insn) == 1308) + return OPCODE_IVP_MALIGN; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8382 && + Field_fld_f4_s0_ld_12_0_Slot_f4_s0_ld_get (insn) == 5236) + return OPCODE_IVP_ZALIGN; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8382 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 3) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8382 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 4) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8382 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 5) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8382 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 6) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8383 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 3) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8384 && + Field_fld_f4_s0_ld_12_8_Slot_f4_s0_ld_get (insn) == 1) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4150) + return OPCODE_ADDI; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4151) + return OPCODE_ADDMI; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4152) + return OPCODE_IVP_LV2NX8T_X; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4153) + return OPCODE_IVP_LV2NX8T_XP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4154) + return OPCODE_IVP_LVNX8ST_X; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4155) + return OPCODE_IVP_LVNX8ST_XP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4156) + return OPCODE_IVP_LVNX8UT_X; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4157) + return OPCODE_IVP_LVNX8UT_XP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4158) + return OPCODE_IVP_LVN_2X16ST_X; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4159) + return OPCODE_IVP_LVN_2X16ST_XP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4160) + return OPCODE_IVP_LVN_2X16UT_X; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4161) + return OPCODE_IVP_LVN_2X16UT_XP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4162) + return OPCODE_L16SI; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4163) + return OPCODE_L16UI; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4164) + return OPCODE_L32I; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4165) + return OPCODE_L8UI; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4166) + return OPCODE_S16I; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4167) + return OPCODE_S32I; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4168) + return OPCODE_S8I; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4169) + return OPCODE_IVP_LV2NX8T_IP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4170) + return OPCODE_IVP_LVNX8ST_IP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4171) + return OPCODE_IVP_LVNX8UT_IP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4172) + return OPCODE_IVP_LVN_2X16ST_IP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4173) + return OPCODE_IVP_LVN_2X16UT_IP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4174) + return OPCODE_MOVI; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4191 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4191 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4191 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_get (insn) == 2068) + return OPCODE_IVP_LSN_2X32_I; + if (Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_get (insn) == 2069) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_get (insn) == 2070) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_get (insn) == 2071) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_get (insn) == 2072) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_get (insn) == 2073) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_get (insn) == 2074) + return OPCODE_EXTUI; + if (Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_get (insn) == 1028) + return OPCODE_IVP_LV2NX8T_I; + if (Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_get (insn) == 1029) + return OPCODE_IVP_LVNX8ST_I; + if (Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_get (insn) == 1030) + return OPCODE_IVP_LVNX8UT_I; + if (Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_get (insn) == 1031) + return OPCODE_IVP_LVN_2X16ST_I; + if (Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_get (insn) == 1032) + return OPCODE_IVP_LVN_2X16UT_I; + if (Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_get (insn) == 1033) + return OPCODE_J; + if (Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_get (insn) == 1048 && + Field_fld_f4_s0_ld_15_15_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_12_8_Slot_f4_s0_ld_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f4_s0_ld_31_20_Slot_f4_s0_ld_get (insn) == 256) + return OPCODE_CONST16; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_9_Slot_f4_s0_ld_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_9_Slot_f4_s0_ld_get (insn) == 1) + return OPCODE_BBSI_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 8) + return OPCODE_BEQ_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 14) + return OPCODE_BNE_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 10) + return OPCODE_BGE_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 12) + return OPCODE_BLT_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 9) + return OPCODE_BGEU_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 11) + return OPCODE_BLTU_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 5) + return OPCODE_BANY_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 4) + return OPCODE_BALL_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 13) + return OPCODE_BNALL_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 6) + return OPCODE_BBC_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 7) + return OPCODE_BBS_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_11_4_Slot_f4_s0_ld_get (insn) == 6) + return OPCODE_BEQZ_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_11_4_Slot_f4_s0_ld_get (insn) == 54) + return OPCODE_BNEZ_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_11_4_Slot_f4_s0_ld_get (insn) == 22) + return OPCODE_BGEZ_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_11_4_Slot_f4_s0_ld_get (insn) == 38) + return OPCODE_BLTZ_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 5) + return OPCODE_BNEI_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 1) + return OPCODE_BGEI_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 3) + return OPCODE_BLTI_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 2) + return OPCODE_BGEUI_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 4) + return OPCODE_BLTUI_W15; + if (Field_fld_f4_s0_ld_31_7_Slot_f4_s0_ld_get (insn) == 2145826 && + Field_fld_f4_s0_ld_6_4_Slot_f4_s0_ld_get (insn) == 7) + return OPCODE_SSR; + if (Field_fld_f4_s0_ld_31_7_Slot_f4_s0_ld_get (insn) == 2145832 && + Field_fld_f4_s0_ld_6_0_Slot_f4_s0_ld_get (insn) == 117) + return OPCODE_IVP_SCATTERW; + if (Field_fld_f4_s0_ld_31_7_Slot_f4_s0_ld_get (insn) == 2145892 && + Field_fld_f4_s0_ld_6_4_Slot_f4_s0_ld_get (insn) == 7) + return OPCODE_SSA8L; + if (Field_fld_f4_s0_ld_31_7_Slot_f4_s0_ld_get (insn) == 2145894 && + Field_fld_f4_s0_ld_6_4_Slot_f4_s0_ld_get (insn) == 7) + return OPCODE_SSL; + if (Field_fld_f4_s0_ld_31_7_Slot_f4_s0_ld_get (insn) == 2145896 && + Field_fld_f4_s0_ld_6_0_Slot_f4_s0_ld_get (insn) == 117) + return OPCODE_NOP; + if (Field_fld_f4_s0_ld_31_8_Slot_f4_s0_ld_get (insn) == 1073409) + return OPCODE_NSA; + if (Field_fld_f4_s0_ld_31_8_Slot_f4_s0_ld_get (insn) == 1073441) + return OPCODE_NSAU; + if (Field_fld_f4_s0_ld_31_9_Slot_f4_s0_ld_get (insn) == 536457 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 7) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_n0_s0_ldst_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_n0_s0_ldst_22_0_Slot_n0_s0_ldst_get (insn) == 1933861) + return OPCODE_NOP; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 432) + return OPCODE_ADD; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 433) + return OPCODE_AND; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 434) + return OPCODE_ADDX2; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 435) + return OPCODE_L32I_N; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 436) + return OPCODE_ADDX4; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 437) + return OPCODE_MAX; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 438) + return OPCODE_ADDX8; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 439) + return OPCODE_MAXU; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 440) + return OPCODE_MIN; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 441) + return OPCODE_MOVLTZ; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 442) + return OPCODE_MINU; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 443) + return OPCODE_MOVNEZ; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 444) + return OPCODE_MOVEQZ; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 445) + return OPCODE_OR; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 446) + return OPCODE_MOVGEZ; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 447) + return OPCODE_S32I_N; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 448) + return OPCODE_SALT; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 449) + return OPCODE_SUBX4; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 450) + return OPCODE_SALTU; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 451) + return OPCODE_SUBX8; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 452) + return OPCODE_SUB; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 453) + return OPCODE_XOR; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 454) + return OPCODE_SUBX2; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 455) + return OPCODE_SEXT; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 456) + return OPCODE_SRLI; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 458 && + Field_fld_n0_s0_ldst_3_0_Slot_n0_s0_ldst_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 458 && + Field_fld_n0_s0_ldst_3_0_Slot_n0_s0_ldst_get (insn) == 0) + return OPCODE_SRA; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 466 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 14) + return OPCODE_SLL; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 196) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 197) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 198) + return OPCODE_IVP_SV2NX8_X; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 199) + return OPCODE_IVP_SV2NX8_XP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 200) + return OPCODE_IVP_SVNX8S_X; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 201) + return OPCODE_IVP_SVNX8S_XP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 202) + return OPCODE_IVP_SVNX8U_X; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 203) + return OPCODE_IVP_SVNX8U_XP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 204) + return OPCODE_IVP_SVN_2X16S_X; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 205) + return OPCODE_IVP_SVN_2X16S_XP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 206) + return OPCODE_IVP_SVN_2X16U_X; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 207) + return OPCODE_IVP_SVN_2X16U_XP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 208) + return OPCODE_SLLI; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 209) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 210) + return OPCODE_IVP_SV2NX8_IP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 211) + return OPCODE_IVP_SVNX8S_IP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 212) + return OPCODE_IVP_SVNX8U_IP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 213) + return OPCODE_IVP_SVN_2X16S_IP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 214) + return OPCODE_IVP_SVN_2X16U_IP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 215) + return OPCODE_SRAI; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 232 && + Field_fld_n0_s0_ldst_7_6_Slot_n0_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SHFL2NX8I_S0; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 233 && + Field_fld_n0_s0_ldst_7_5_Slot_n0_s0_ldst_get (insn) == 6) + return OPCODE_IVP_MOVVV; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 34) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 35) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 36) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 37) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 38) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 39) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 40) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 41) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 42) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 43) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 44) + return OPCODE_IVP_SAV2NX8_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 45) + return OPCODE_IVP_SAVNX8S_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 46) + return OPCODE_IVP_SAVNX8U_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 47) + return OPCODE_IVP_SAVN_2X16S_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 48) + return OPCODE_IVP_SAVN_2X16U_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 57 && + Field_fld_n0_s0_ldst_12_12_Slot_n0_s0_ldst_get (insn) == 1 && + Field_fld_n0_s0_ldst_7_6_Slot_n0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 57 && + Field_fld_n0_s0_ldst_12_12_Slot_n0_s0_ldst_get (insn) == 1 && + Field_fld_n0_s0_ldst_7_6_Slot_n0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SALIGN_I; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 5) + return OPCODE_IVP_SA2NX8_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 2) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SANX8U_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 6) + return OPCODE_IVP_SANX8S_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 3) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 4) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 9) + return OPCODE_IVP_SAN_2X16U_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 8) + return OPCODE_IVP_SAN_2X16S_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 59 && + Field_fld_n0_s0_ldst_12_8_Slot_n0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 59 && + Field_fld_n0_s0_ldst_12_8_Slot_n0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SALIGN_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 59 && + Field_fld_n0_s0_ldst_12_4_Slot_n0_s0_ldst_get (insn) == 32) + return OPCODE_IVP_LA_PP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 59 && + Field_fld_n0_s0_ldst_12_4_Slot_n0_s0_ldst_get (insn) == 33) + return OPCODE_IVP_SAPOS_FP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 59 && + Field_fld_n0_s0_ldst_12_2_Slot_n0_s0_ldst_get (insn) == 136) + return OPCODE_IVP_MALIGN; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 59 && + Field_fld_n0_s0_ldst_12_0_Slot_n0_s0_ldst_get (insn) == 548) + return OPCODE_IVP_ZALIGN; + if (Field_fld_n0_s0_ldst_22_16_Slot_n0_s0_ldst_get (insn) == 14) + return OPCODE_ADDI; + if (Field_fld_n0_s0_ldst_22_16_Slot_n0_s0_ldst_get (insn) == 15) + return OPCODE_ADDMI; + if (Field_fld_n0_s0_ldst_22_16_Slot_n0_s0_ldst_get (insn) == 16) + return OPCODE_MOVI; + if (Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SV2NX8_I; + if (Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_get (insn) == 2) + return OPCODE_IVP_SVNX8S_I; + if (Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SVNX8U_I; + if (Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_get (insn) == 4) + return OPCODE_IVP_SVN_2X16S_I; + if (Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_get (insn) == 5) + return OPCODE_IVP_SVN_2X16U_I; + if (Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_get (insn) == 6) + return OPCODE_EXTUI; + return XTENSA_UNDEFINED; +} + +static int +Slot_f3_s4_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f3_s4_alu_23_0_Slot_f3_s4_alu_get (insn) == 5931392) + return OPCODE_NOP; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 144) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 145) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 146) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 147) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 148) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 149) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 150) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 151) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 152) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 153) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 154) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 155) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 156) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 157) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 158) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 159) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 160) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 161) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 162) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 163) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 164) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 165) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 166) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 167) + return OPCODE_IVP_MINNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 168) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 169) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 170) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 171) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 172) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 173) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 174) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 175) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 176) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 177) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 178) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 179) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 180) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 6) + return OPCODE_IVP_MOVVV; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 11) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 8) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 10) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 7) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 2) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 4) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 9) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_6_Slot_f3_s4_alu_get (insn) == 0) + return OPCODE_IVP_SHFL2NX8I_S4; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 3) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 5) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f3_s4_alu_23_16_Slot_f3_s4_alu_get (insn) == 160) + return OPCODE_MTK_AndPOPC; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 4) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 5) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 6) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 7) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 8) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 9) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 10) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 11) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 12) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 13) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 14) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 15) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 16) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 17) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 10) + return OPCODE_IVP_LTNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 4) + return OPCODE_IVP_LENX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 1) + return OPCODE_IVP_EQNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 16) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 13) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 7) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 9) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 3) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 15) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 12) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 6) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 11) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 5) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 2) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 17) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 14) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 8) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f3_s4_alu_23_20_Slot_f3_s4_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8I_S4; + return XTENSA_UNDEFINED; +} + +static int +Slot_f11_s4_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f11_s4_alu_24_0_Slot_f11_s4_alu_get (insn) == 4882752) + return OPCODE_NOP; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 112) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 113) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 114) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 115) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 116) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 117) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 118) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 119) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 120) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 121) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 122) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 123) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 124) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 125) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 126) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 127) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 128) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 129) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 130) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 131) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 132) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 133) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 134) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 135) + return OPCODE_IVP_MINNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 136) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 137) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 138) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 139) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 140) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 141) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 142) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 143) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 144) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 145) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 146) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 147) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 148) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 4) + return OPCODE_IVP_MOVVV; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 9) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 6) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 8) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 5) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 0) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 2) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 7) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 1) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 3) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f11_s4_alu_24_16_Slot_f11_s4_alu_get (insn) == 75) + return OPCODE_MTK_AndPOPC; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 0) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 1) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 2) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 3) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 4) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 5) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 6) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 7) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 8) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 9) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 10) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 11) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 12) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 13) + return OPCODE_IVP_BSUBNORMNX16; + return XTENSA_UNDEFINED; +} + +static int +Slot_n1_s2_mul_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_n1_s2_mul_25_1_Slot_n1_s2_mul_get (insn) == 3332098 && + Field_fld_n1_s2_mul_0_0_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1624) + return OPCODE_MOVNEZ; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1625) + return OPCODE_SUB; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1626) + return OPCODE_XOR; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1628 && + Field_fld_n1_s2_mul_7_4_Slot_n1_s2_mul_get (insn) == 4) + return OPCODE_SRL; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1732) + return OPCODE_ADD; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1733) + return OPCODE_ADDX2; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1734) + return OPCODE_ADDX4; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1735) + return OPCODE_ADDX8; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1752) + return OPCODE_OR; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1753) + return OPCODE_SUBX2; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1754) + return OPCODE_CLAMPS; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1860) + return OPCODE_AND; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1861) + return OPCODE_MAXU; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1862) + return OPCODE_MINU; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1863) + return OPCODE_MOVGEZ; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1880) + return OPCODE_SALT; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1881) + return OPCODE_SUBX4; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1882 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1988) + return OPCODE_MAX; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1989) + return OPCODE_MIN; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1990) + return OPCODE_MOVEQZ; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1991) + return OPCODE_MOVLTZ; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 2008) + return OPCODE_SALTU; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 2009) + return OPCODE_SUBX8; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 397 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_LENX16; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 397 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 398 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 398 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 399 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEQNX16; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 401 && + Field_fld_n1_s2_mul_8_8_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_EXTRVRN_2X32; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 429 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQNX16; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 429 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 430 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTUNX16; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 430 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_LT2NX8; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 431 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 461 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 461 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 462 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_LTNX16; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 462 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 493 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEUNX16; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 493 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_LE2NX8; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 494 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 494 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 7 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULANX16PACKL; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 7 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULANX16PACKQ; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 7 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULSNX16PACKL; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 7 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULNX16PACKP; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 7 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULANX16PACKP; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 7 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULSNX16PACKP; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 7 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULNX16PACKL; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 7 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULNX16PACKQ; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 8 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSNX16PACKQ; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 10 && + Field_fld_n1_s2_mul_13_9_Slot_n1_s2_mul_get (insn) == 0 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 9) + return OPCODE_IVP_MOVVV; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 2 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULI2NX8X16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 2 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULAI2NX8X16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 2 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSI2NX8X16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 2 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSAI2NX8X16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 21 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_CVT24U2NX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_9_Slot_n1_s2_mul_get (insn) == 728 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_CVT24U32; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 21 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT24UNX32L; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 21 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 2) + return OPCODE_IVP_CVT24UNX32H; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_9_Slot_n1_s2_mul_get (insn) == 728 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 2) + return OPCODE_IVP_CVT48UNX32L; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 21 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 4) + return OPCODE_IVP_CVT48UNX32; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_9_Slot_n1_s2_mul_get (insn) == 728 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_CVT48U64; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 21 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 6) + return OPCODE_IVP_CVT48UN_2X64L; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 21 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 5) + return OPCODE_IVP_CVT48UN_2X64H; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 21 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 7) + return OPCODE_IVP_CVT96UN_2X64; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_9_Slot_n1_s2_mul_get (insn) == 728 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT96U64; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUU2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUUA2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUS2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUSA2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 23 && + Field_fld_n1_s2_mul_8_4_Slot_n1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSA2N8XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 23 && + Field_fld_n1_s2_mul_8_4_Slot_n1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUS2N8XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 23 && + Field_fld_n1_s2_mul_8_4_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULA2N8XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 23 && + Field_fld_n1_s2_mul_8_4_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL2N8XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_6_Slot_n1_s2_mul_get (insn) == 5824 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 4) + return OPCODE_IVP_MOVWW; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULNX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULANX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUNX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUUANX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUSNX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSANX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 16 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 14) + return OPCODE_IVP_MUL2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 16 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULA2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 16 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 8) + return OPCODE_IVP_ADDW2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 16 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 9) + return OPCODE_IVP_ADDWA2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 16 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 10) + return OPCODE_IVP_ADDWS2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 16 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 11) + return OPCODE_IVP_ADDWU2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 16 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 12) + return OPCODE_IVP_ADDWUA2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 16 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 13) + return OPCODE_IVP_ADDWUS2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULSNX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUUSNX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUSSNX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUUN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUSN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULSUN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUUN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUSN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULSUN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUUHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUSHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULSUHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULAN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUUAN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUSAN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULSUAN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULAHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUUAHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSAHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULSUAHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULAN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUUAN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUSAN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULSUAN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULSHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUUSHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUSSHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULSUSHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULSN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUUSN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUSSN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULSUSN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULSN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 21 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUUSN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSSN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSUSN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULPN16XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULPAN16XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUSPN16XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUSPAN16XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULP2N8XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULPA2N8XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSP2N8XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUSPA2N8XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL4T2N8XR8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MUL4TA2N8XR8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUS4T2N8XR8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUS4TA2N8XR8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 12) + return OPCODE_ADDI; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 4 && + Field_fld_n1_s2_mul_13_9_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULI2NR8X16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 4 && + Field_fld_n1_s2_mul_13_9_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULAI2NR8X16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 4 && + Field_fld_n1_s2_mul_13_9_Slot_n1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSI2NR8X16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 4 && + Field_fld_n1_s2_mul_13_9_Slot_n1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSAI2NR8X16; + return XTENSA_UNDEFINED; +} + +static int +Slot_f0_s2_mul_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 597) + return OPCODE_SUBX2; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 620 && + Field_fld_f0_s2_mul_7_4_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_ABS; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 725) + return OPCODE_SUBX4; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 726) + return OPCODE_ADD; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 727) + return OPCODE_ADDX2; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 748 && + Field_fld_f0_s2_mul_7_4_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_SRA; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 848 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 852) + return OPCODE_ADDX4; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 853) + return OPCODE_SUBX8; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 854) + return OPCODE_AND; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 855) + return OPCODE_SRLI; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 876 && + Field_fld_f0_s2_mul_7_4_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 980) + return OPCODE_ADDX8; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 981) + return OPCODE_XOR; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 982) + return OPCODE_OR; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 983) + return OPCODE_SUB; + if (Field_fld_f0_s2_mul_26_13_Slot_f0_s2_mul_get (insn) == 299) + return OPCODE_SLLI; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 141 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_LENX16; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 141 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 142 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 142 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 143 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 173 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQNX16; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 173 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 174 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 174 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 175 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 205 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 205 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 206 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_LTNX16; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 206 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 237 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 237 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 238 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 238 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f0_s2_mul_26_2_Slot_f0_s2_mul_get (insn) == 630915 && + Field_fld_f0_s2_mul_1_0_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_f0_s2_mul_26_20_Slot_f0_s2_mul_get (insn) == 2 && + Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_get (insn) == 84) + return OPCODE_SRAI; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULI2NX8X16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULAI2NX8X16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSI2NX8X16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSAI2NX8X16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 26 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_CVT24U2NX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 15) + return OPCODE_IVP_CVT24S2NX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_get (insn) == 104 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 8) + return OPCODE_IVP_CVT24U32; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 26 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 2) + return OPCODE_IVP_CVT24UNX32L; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 26 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_CVT24UNX32H; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_get (insn) == 104 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 11) + return OPCODE_IVP_CVT48UNX32L; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 26 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 4) + return OPCODE_IVP_CVT48UNX32; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_get (insn) == 104 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 9) + return OPCODE_IVP_CVT48SNX32L; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 26 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT48SNX32; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_get (insn) == 104 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 10) + return OPCODE_IVP_CVT48U64; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 26 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 6) + return OPCODE_IVP_CVT48UN_2X64L; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 26 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 5) + return OPCODE_IVP_CVT48UN_2X64H; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 26 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 7) + return OPCODE_IVP_CVT96UN_2X64; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_get (insn) == 104 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT96U64; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUU2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUA2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUS2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUSA2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 27 && + Field_fld_f0_s2_mul_11_8_Slot_f0_s2_mul_get (insn) == 3 && + Field_fld_f0_s2_mul_4_4_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUSA2N8XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 27 && + Field_fld_f0_s2_mul_11_8_Slot_f0_s2_mul_get (insn) == 2 && + Field_fld_f0_s2_mul_4_4_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUS2N8XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 27 && + Field_fld_f0_s2_mul_11_8_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_4_4_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULA2N8XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 27 && + Field_fld_f0_s2_mul_11_8_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_4_4_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL2N8XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_9_Slot_f0_s2_mul_get (insn) == 832 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 13) + return OPCODE_IVP_MOVWW; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULANX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUUNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUUANX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUSANX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 4) + return OPCODE_IVP_MUL2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULA2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 20 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 8) + return OPCODE_IVP_ADDW2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 20 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 9) + return OPCODE_IVP_ADDWA2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 20 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 12) + return OPCODE_IVP_ADDWS2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 20 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 14) + return OPCODE_IVP_ADDWU2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 20 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 15) + return OPCODE_IVP_ADDWUA2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 2) + return OPCODE_IVP_ADDWUS2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULSNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUUSNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUSSNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUUN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULSUN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUUN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUSN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULSUN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUUHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUSHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULSUHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULAN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUUAN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUSAN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULSUAN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULAHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUUAHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUSAHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULSUAHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULAN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUUAN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUSAN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSUAN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULSHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUUSHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUSSHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULSUSHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULSN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUUSN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSSN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULSUSN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULSN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUUSN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSSN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULSUSN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULPN16XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULPAN16XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUSPN16XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUSPAN16XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULP2N8XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULPA2N8XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSP2N8XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUSPA2N8XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL4T2N8XR8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_MUL4TA2N8XR8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUS4T2N8XR8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUS4TA2N8XR8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 20 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 11) + return OPCODE_IVP_ADDWNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 20 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 10) + return OPCODE_IVP_ADDWANX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 20 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 13) + return OPCODE_IVP_ADDWSNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_ADDWUNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADDWUANX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 3) + return OPCODE_IVP_ADDWUSNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 10) + return OPCODE_IVP_SUBWNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 9) + return OPCODE_IVP_SUBWANX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 14) + return OPCODE_IVP_SUBWUNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 13) + return OPCODE_IVP_SUBWUANX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 7) + return OPCODE_IVP_SUBW2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 8) + return OPCODE_IVP_SUBWA2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWU2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 12) + return OPCODE_IVP_SUBWUA2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 12) + return OPCODE_ADDI; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 2 && + Field_fld_f0_s2_mul_13_12_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULI2NR8X16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 2 && + Field_fld_f0_s2_mul_13_12_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULAI2NR8X16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 2 && + Field_fld_f0_s2_mul_13_12_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSI2NR8X16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 2 && + Field_fld_f0_s2_mul_13_12_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSAI2NR8X16; + return XTENSA_UNDEFINED; +} + +static int +Slot_f3_s2_mul_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f3_s2_mul_21_0_Slot_f3_s2_mul_get (insn) == 1703951) + return OPCODE_NOP; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 337) + return OPCODE_SUBX2; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 341) + return OPCODE_SUBX4; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 342) + return OPCODE_ADD; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 343) + return OPCODE_ADDX2; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 344) + return OPCODE_ADDX4; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 345) + return OPCODE_SUBX8; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 346) + return OPCODE_AND; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 347) + return OPCODE_SRLI; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 348) + return OPCODE_ADDX8; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 349) + return OPCODE_XOR; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 350) + return OPCODE_OR; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 351) + return OPCODE_SUB; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 432 && + Field_fld_f3_s2_mul_7_4_Slot_f3_s2_mul_get (insn) == 10) + return OPCODE_SRL; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 432 && + Field_fld_f3_s2_mul_7_4_Slot_f3_s2_mul_get (insn) == 8) + return OPCODE_SRA; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 433 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_f3_s2_mul_21_13_Slot_f3_s2_mul_get (insn) == 169) + return OPCODE_SLLI; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 52 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_LENX16; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 52 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 53 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQNX16; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 53 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 54 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 54 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 55 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 55 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 56 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 56 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 57 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 57 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 58 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_LTNX16; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 58 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 59 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 59 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 60 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 61 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f3_s2_mul_21_15_Slot_f3_s2_mul_get (insn) == 42 && + Field_fld_f3_s2_mul_13_12_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_SRAI; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL4T2N8XR8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_MUL4TA2N8XR8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULP2N8XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULPA2N8XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULPAN16XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULPN16XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUS4T2N8XR8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUS4TA2N8XR8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSP2N8XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUSPA2N8XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUSPAN16XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUSPN16XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 12) + return OPCODE_ADDI; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 20 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 8) + return OPCODE_IVP_ADDW2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 20 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 9) + return OPCODE_IVP_ADDWA2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 20 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 12) + return OPCODE_IVP_ADDWS2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 20 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 14) + return OPCODE_IVP_ADDWU2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 20 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 15) + return OPCODE_IVP_ADDWUA2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 20 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 11) + return OPCODE_IVP_ADDWNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 20 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 10) + return OPCODE_IVP_ADDWANX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 20 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 13) + return OPCODE_IVP_ADDWSNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULANX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 4) + return OPCODE_IVP_MUL2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULA2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 2) + return OPCODE_IVP_ADDWUS2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULSNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULAN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULAHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULAN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULSHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_ADDWUNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADDWUANX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 3) + return OPCODE_IVP_ADDWUSNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUS2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUSA2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUSANX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULSUN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULSUN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULSUHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUSAN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULSUAN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUSAHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULSUAHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSUAN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULSUSHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULSN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULSUSN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULSN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULSUSN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUU2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUA2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUUANX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUSSNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUSN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUUHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUSHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUUAN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUUAHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUUAN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUSAN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUSSHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSSN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSSN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 15) + return OPCODE_IVP_CVT24S2NX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUUNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUUSNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUUN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUUN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUUSHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUUSN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUUSN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 10) + return OPCODE_IVP_SUBWNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 9) + return OPCODE_IVP_SUBWANX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 14) + return OPCODE_IVP_SUBWUNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 13) + return OPCODE_IVP_SUBWUANX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 7) + return OPCODE_IVP_SUBW2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 8) + return OPCODE_IVP_SUBWA2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWU2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 12) + return OPCODE_IVP_SUBWUA2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_CVT24U2NX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_11_8_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_get (insn) == 8) + return OPCODE_IVP_CVT24U32; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 2) + return OPCODE_IVP_CVT24UNX32L; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_CVT24UNX32H; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_11_8_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_get (insn) == 11) + return OPCODE_IVP_CVT48UNX32L; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 4) + return OPCODE_IVP_CVT48UNX32; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_11_8_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_get (insn) == 9) + return OPCODE_IVP_CVT48SNX32L; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT48SNX32; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_11_8_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_get (insn) == 10) + return OPCODE_IVP_CVT48U64; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 6) + return OPCODE_IVP_CVT48UN_2X64L; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 5) + return OPCODE_IVP_CVT48UN_2X64H; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 7) + return OPCODE_IVP_CVT96UN_2X64; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_11_8_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT96U64; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_13_7_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_get (insn) == 14) + return OPCODE_IVP_MOVWW; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 27 && + Field_fld_f3_s2_mul_13_12_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_7_5_Slot_f3_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSA2N8XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 27 && + Field_fld_f3_s2_mul_13_12_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_7_5_Slot_f3_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUS2N8XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 27 && + Field_fld_f3_s2_mul_13_12_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_7_5_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULA2N8XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 27 && + Field_fld_f3_s2_mul_13_12_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_7_5_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL2N8XR16; + return XTENSA_UNDEFINED; +} + +static int +Slot_f11_s2_mul_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f11_s2_mul_22_0_Slot_f11_s2_mul_get (insn) == 1392651) + return OPCODE_NOP; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 248 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 258) + return OPCODE_ADDX4; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 259) + return OPCODE_SRC; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 262) + return OPCODE_ADDX8; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 263) + return OPCODE_SUB; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 265) + return OPCODE_ADD; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 266) + return OPCODE_AND; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 267) + return OPCODE_SUBX2; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 269) + return OPCODE_ADDX2; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 270) + return OPCODE_OR; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 271) + return OPCODE_SUBX4; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 352) + return OPCODE_SUBX8; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 356) + return OPCODE_XOR; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 360) + return OPCODE_SRLI; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 364 && + Field_fld_f11_s2_mul_7_4_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 364 && + Field_fld_f11_s2_mul_7_4_Slot_f11_s2_mul_get (insn) == 4) + return OPCODE_SRL; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 364 && + Field_fld_f11_s2_mul_7_4_Slot_f11_s2_mul_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_f11_s2_mul_22_13_Slot_f11_s2_mul_get (insn) == 128) + return OPCODE_SLLI; + if (Field_fld_f11_s2_mul_22_13_Slot_f11_s2_mul_get (insn) == 130) + return OPCODE_IVP_EXTRVRN_2X32; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 52 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_LENX16; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 52 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 53 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQNX16; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 53 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 54 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 54 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 55 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 55 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 56 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 56 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 57 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 57 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 58 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_LTNX16; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 58 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 59 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 59 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 60 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 61 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f11_s2_mul_22_15_Slot_f11_s2_mul_get (insn) == 33 && + Field_fld_f11_s2_mul_13_12_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_SRAI; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL4T2N8XR8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_MUL4TA2N8XR8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULP2N8XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULPA2N8XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULPAN16XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULPN16XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUS4T2N8XR8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUS4TA2N8XR8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSP2N8XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUSPA2N8XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUSPAN16XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUSPN16XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 12) + return OPCODE_ADDI; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 15 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 8) + return OPCODE_IVP_ADDW2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 15 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 9) + return OPCODE_IVP_ADDWA2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 15 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 12) + return OPCODE_IVP_ADDWS2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 15 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 14) + return OPCODE_IVP_ADDWU2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 15 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 15) + return OPCODE_IVP_ADDWUA2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 15 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 11) + return OPCODE_IVP_ADDWNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 15 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 10) + return OPCODE_IVP_ADDWANX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 15 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 13) + return OPCODE_IVP_ADDWSNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULANX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 4) + return OPCODE_IVP_MUL2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULA2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 2) + return OPCODE_IVP_ADDWUS2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULSNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULAN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULAHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULAN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULSHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_ADDWUNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADDWUANX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 3) + return OPCODE_IVP_ADDWUSNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUS2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUSA2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUSANX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULSUN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULSUN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULSUHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUSAN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULSUAN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUSAHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULSUAHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSUAN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULSUSHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULSN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULSUSN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULSN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULSUSN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUU2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUA2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUUANX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUSSNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUSN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUUHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUSHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUUAN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUUAHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUUAN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUSAN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUSSHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSSN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSSN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 15) + return OPCODE_IVP_CVT24S2NX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUUNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUUSNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUUN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUUN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUUSHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUUSN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUUSN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 10) + return OPCODE_IVP_SUBWNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 9) + return OPCODE_IVP_SUBWANX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 14) + return OPCODE_IVP_SUBWUNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 13) + return OPCODE_IVP_SUBWUANX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 7) + return OPCODE_IVP_SUBW2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 8) + return OPCODE_IVP_SUBWA2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWU2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 12) + return OPCODE_IVP_SUBWUA2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_CVT24U2NX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_11_8_Slot_f11_s2_mul_get (insn) == 0 && + Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_get (insn) == 8) + return OPCODE_IVP_CVT24U32; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 2) + return OPCODE_IVP_CVT24UNX32L; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_CVT24UNX32H; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_11_8_Slot_f11_s2_mul_get (insn) == 0 && + Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_get (insn) == 25) + return OPCODE_IVP_CVT48UNX32L; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 4) + return OPCODE_IVP_CVT48UNX32; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_11_8_Slot_f11_s2_mul_get (insn) == 0 && + Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_get (insn) == 24) + return OPCODE_IVP_CVT48SNX32L; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT48SNX32; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_11_8_Slot_f11_s2_mul_get (insn) == 0 && + Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_get (insn) == 9) + return OPCODE_IVP_CVT48U64; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 6) + return OPCODE_IVP_CVT48UN_2X64L; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 5) + return OPCODE_IVP_CVT48UN_2X64H; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 7) + return OPCODE_IVP_CVT96UN_2X64; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_11_8_Slot_f11_s2_mul_get (insn) == 0 && + Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_get (insn) == 10) + return OPCODE_IVP_CVT96U64; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_13_7_Slot_f11_s2_mul_get (insn) == 32 && + Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_get (insn) == 11) + return OPCODE_IVP_MOVWW; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 22 && + Field_fld_f11_s2_mul_13_12_Slot_f11_s2_mul_get (insn) == 1 && + Field_fld_f11_s2_mul_7_5_Slot_f11_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSA2N8XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 22 && + Field_fld_f11_s2_mul_13_12_Slot_f11_s2_mul_get (insn) == 1 && + Field_fld_f11_s2_mul_7_5_Slot_f11_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUS2N8XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 22 && + Field_fld_f11_s2_mul_13_12_Slot_f11_s2_mul_get (insn) == 1 && + Field_fld_f11_s2_mul_7_5_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULA2N8XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 22 && + Field_fld_f11_s2_mul_13_12_Slot_f11_s2_mul_get (insn) == 1 && + Field_fld_f11_s2_mul_7_5_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL2N8XR16; + if (Field_fld_f11_s2_mul_22_8_Slot_f11_s2_mul_get (insn) == 5376 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 11) + return OPCODE_SSR; + return XTENSA_UNDEFINED; +} + +static int +Slot_f11_s0_ld_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f11_s0_ld_23_0_Slot_f11_s0_ld_get (insn) == 1486897) + return OPCODE_NOP; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 340) + return OPCODE_ADD; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 341) + return OPCODE_ADDX2; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 342) + return OPCODE_ADDX4; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 343) + return OPCODE_ADDX8; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 344) + return OPCODE_AND; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 345) + return OPCODE_MAX; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 346) + return OPCODE_MAXU; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 347) + return OPCODE_MIN; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 348) + return OPCODE_MINU; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 349) + return OPCODE_MOVEQZ; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 350) + return OPCODE_MOVGEZ; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 351) + return OPCODE_MOVLTZ; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 352) + return OPCODE_MOVNEZ; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 353) + return OPCODE_OR; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 354) + return OPCODE_SALT; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 355) + return OPCODE_SALTU; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 356) + return OPCODE_SRLI; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 357) + return OPCODE_SUB; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 358) + return OPCODE_SUBX2; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 359) + return OPCODE_SUBX4; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 360) + return OPCODE_SUBX8; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 361) + return OPCODE_XOR; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 362) + return OPCODE_SEXT; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 363 && + Field_fld_f11_s0_ld_7_4_Slot_f11_s0_ld_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 363 && + Field_fld_f11_s0_ld_7_4_Slot_f11_s0_ld_get (insn) == 0) + return OPCODE_SRA; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 364 && + Field_fld_f11_s0_ld_3_0_Slot_f11_s0_ld_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_f11_s0_ld_23_13_Slot_f11_s0_ld_get (insn) == 168) + return OPCODE_SRAI; + if (Field_fld_f11_s0_ld_23_13_Slot_f11_s0_ld_get (insn) == 169) + return OPCODE_SLLI; + if (Field_fld_f11_s0_ld_23_16_Slot_f11_s0_ld_get (insn) == 18) + return OPCODE_ADDI; + if (Field_fld_f11_s0_ld_23_16_Slot_f11_s0_ld_get (insn) == 19) + return OPCODE_ADDMI; + if (Field_fld_f11_s0_ld_23_16_Slot_f11_s0_ld_get (insn) == 20) + return OPCODE_MOVI; + if (Field_fld_f11_s0_ld_23_17_Slot_f11_s0_ld_get (insn) == 8) + return OPCODE_EXTUI; + if (Field_fld_f11_s0_ld_23_20_Slot_f11_s0_ld_get (insn) == 0) + return OPCODE_CONST16; + if (Field_fld_f11_s0_ld_23_4_Slot_f11_s0_ld_get (insn) == 92930) + return OPCODE_IVP_MALIGN; + if (Field_fld_f11_s0_ld_23_4_Slot_f11_s0_ld_get (insn) == 92931 && + Field_fld_f11_s0_ld_1_0_Slot_f11_s0_ld_get (insn) == 0) + return OPCODE_IVP_ZALIGN; + return XTENSA_UNDEFINED; +} + +static int +Slot_f4_s2_mul_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULPAI2NR8X16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULPI2NR8X16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULQ2N8XR8; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULQA2N8XR8; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUSPAI2NR8X16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUSPI2NR8X16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUSQ2N8XR8; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSQA2N8XR8; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULPNX16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULPANX16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSPNX16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUSPANX16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUUPNX16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUPANX16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULP2NX8; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULPA2NX8; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUSP2NX8; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUSPA2NX8; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUUP2NX8; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUUPA2NX8; + if (Field_fld_f4_s2_mul_32_8_Slot_f4_s2_mul_get (insn) == 2097152 && + Field_fld_f4_s2_mul_7_0_Slot_f4_s2_mul_get (insn) == 12) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_inst_23_12_Slot_inst_get (insn) == 864 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_oq_tie2apb_outq0_push_read; + if (Field_fld_inst_23_12_Slot_inst_get (insn) == 865 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_oq_tie2apb_outq0_push_write; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 6 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_oq_tie2apb_outq0_nonblocking_push_read; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 22 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_oq_tie2apb_outq0_nonblocking_push_write; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 38 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 0 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_iq_tie2apb_inq0_nonblocking_peek; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 38 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 1 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_iq_tie2apb_inq0_nonblocking_pop; + if (Field_fld_inst_23_8_Slot_inst_get (insn) == 13856 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_iq_tie2apb_inq0_blocking_peek; + if (Field_fld_inst_23_8_Slot_inst_get (insn) == 13857 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_iq_tie2apb_inq0_is_ready; + if (Field_fld_inst_23_8_Slot_inst_get (insn) == 13858 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_iq_tie2apb_inq0_pop; + if (Field_fld_inst_23_8_Slot_inst_get (insn) == 13859 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_oq_tie2apb_outq0_is_ready; + if (Field_op0_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 0) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_r_Slot_inst_get (insn) == 0) + { + if (Field_m_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return OPCODE_ILL; + if (Field_m_Slot_inst_get (insn) == 2) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_RET; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_RETW; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_JX; + } + if (Field_m_Slot_inst_get (insn) == 3) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALLX0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALLX4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALLX8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALLX12; + } + } + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_MOVSP; + if (Field_r_Slot_inst_get (insn) == 2) + { + if (Field_s_Slot_inst_get (insn) == 0) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_ISYNC; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RSYNC; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_ESYNC; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DSYNC; + if (Field_t_Slot_inst_get (insn) == 8) + return OPCODE_EXCW; + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_MEMW; + if (Field_t_Slot_inst_get (insn) == 13) + return OPCODE_EXTW; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_NOP; + } + } + if (Field_r_Slot_inst_get (insn) == 3) + { + if (Field_t_Slot_inst_get (insn) == 0) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_RFE; + if (Field_s_Slot_inst_get (insn) == 2) + return OPCODE_RFDE; + if (Field_s_Slot_inst_get (insn) == 4) + return OPCODE_RFWO; + if (Field_s_Slot_inst_get (insn) == 5) + return OPCODE_RFWU; + } + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFI; + if (Field_t_Slot_inst_get (insn) == 2 && + Field_s_Slot_inst_get (insn) == 1) + return OPCODE_CLREX; + } + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BREAK; + if (Field_r_Slot_inst_get (insn) == 5) + { + if (Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SYSCALL; + if (Field_s_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SIMCALL; + } + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RSIL; + if (Field_r_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_WAITI; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_LDDR32_P; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_SDDR32_P; + } + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_ANY4; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_ALL4; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_ANY8; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_ALL8; + } + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_AND; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OR; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_XOR; + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSR; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSL; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8L; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8B; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_thi3_Slot_inst_get (insn) == 0) + return OPCODE_SSAI; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RER; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_WER; + if (Field_r_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_ROTW; + if (Field_r_Slot_inst_get (insn) == 10 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_GETEX; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_NSA; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_NSAU; + } + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_RPTLB0; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_PPTLB; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_WPTLB; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_RPTLB1; + } + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_NEG; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_ABS; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_ADD; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_ADDX2; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_ADDX4; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_ADDX8; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_SUB; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_SUBX2; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_SUBX4; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_SUBX8; + } + if (Field_op1_Slot_inst_get (insn) == 1) + { + if ((Field_op2_Slot_inst_get (insn) == 0 || + Field_op2_Slot_inst_get (insn) == 1)) + return OPCODE_SLLI; + if ((Field_op2_Slot_inst_get (insn) == 2 || + Field_op2_Slot_inst_get (insn) == 3)) + return OPCODE_SRAI; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_SRLI; + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_XSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_XSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_XSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_XSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_XSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_XSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_XSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_XSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_XSR_MPUENB; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_XSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_XSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_XSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 98) + return OPCODE_XSR_CACHEADRDIS; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_XSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_XSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 116) + return OPCODE_XSR_GSERR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_XSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_XSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_XSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_XSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_XSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_XSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_XSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_XSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_XSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_XSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_XSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_XSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_XSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_XSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_XSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_XSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_XSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_XSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_XSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_XSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_XSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_XSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_XSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_XSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_XSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_XSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_XSR_CCOMPARE1; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_SRC; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRL; + if (Field_op2_Slot_inst_get (insn) == 10 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SLL; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRA; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MUL16U; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MUL16S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_LICT; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_SICT; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_LICW; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_SICW; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_L32EX; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S32EX; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_RFDO; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFDD; + } + } + if (Field_op1_Slot_inst_get (insn) == 2) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_ANDB; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_ANDBC; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_ORB; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_ORBC; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_XORB; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_SALTU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_SALT; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MULL; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MULUH; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MULSH; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_QUOU; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_QUOS; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_REMU; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_REMS; + } + if (Field_op1_Slot_inst_get (insn) == 3) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_RSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_RSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_RSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_RSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_RSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_RSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_RSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_RSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_RSR_MPUENB; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_RSR_MPUCFG; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_RSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_RSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_RSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 98) + return OPCODE_RSR_CACHEADRDIS; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_RSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_RSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 116) + return OPCODE_RSR_GSERR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_RSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_RSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_RSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_RSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_RSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_RSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_RSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_RSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_RSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_RSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_RSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_RSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 208) + return OPCODE_RSR_CONFIGID1; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_RSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_RSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_RSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_RSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_RSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_RSR_INTERRUPT; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_RSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_RSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_RSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_RSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_RSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_RSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 235) + return OPCODE_RSR_PRID; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_RSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_RSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_RSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_RSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_RSR_CCOMPARE1; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_WSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_WSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_WSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_WSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_WSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_WSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_WSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_WSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 89) + return OPCODE_WSR_MMID; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_WSR_MPUENB; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_WSR_MPUCFG; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_WSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_WSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_WSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 98) + return OPCODE_WSR_CACHEADRDIS; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_WSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_WSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 116) + return OPCODE_WSR_GSERR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_WSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_WSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_WSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_WSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_WSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_WSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_WSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_WSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_WSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_WSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_WSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_WSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_WSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_WSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_WSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_WSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_WSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_WSR_INTSET; + if (Field_sr_Slot_inst_get (insn) == 227) + return OPCODE_WSR_INTCLEAR; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_WSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_WSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_WSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_WSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_WSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WSR_CCOMPARE1; + } + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_SEXT; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_CLAMPS; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MIN; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MAX; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MINU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_MAXU; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MOVLTZ; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MOVF; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MOVT; + if (Field_op2_Slot_inst_get (insn) == 14) + { + if (Field_st_Slot_inst_get (insn) == 0) + return OPCODE_RUR_APB_PIPE; + if (Field_st_Slot_inst_get (insn) == 231) + return OPCODE_RUR_THREADPTR; + } + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_WUR_APB_PIPE; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WUR_THREADPTR; + } + } + if ((Field_op1_Slot_inst_get (insn) == 4 || + Field_op1_Slot_inst_get (insn) == 5)) + return OPCODE_EXTUI; + if (Field_op1_Slot_inst_get (insn) == 9) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_L32E; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_S32E; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_S32NB; + } + } + if (Field_op0_Slot_inst_get (insn) == 1) + return OPCODE_L32R; + if (Field_op0_Slot_inst_get (insn) == 2) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_L8UI; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_L16UI; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_L32I; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_S8I; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S16I; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_S32I; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_IPF; + if (Field_t_Slot_inst_get (insn) == 13) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_IPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_IHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_IIU; + } + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_IHI; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_III; + } + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_L16SI; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_MOVI; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_L32AI; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_ADDI; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_S32RI; + } + if (Field_op0_Slot_inst_get (insn) == 4) + return OPCODE_CONST16; + if (Field_op0_Slot_inst_get (insn) == 5) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALL0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALL4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALL8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALL12; + } + if (Field_op0_Slot_inst_get (insn) == 6) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_J; + if (Field_n_Slot_inst_get (insn) == 1) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQZ; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEZ; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTZ; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEZ; + } + if (Field_n_Slot_inst_get (insn) == 2) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQI; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEI; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEI; + } + if (Field_n_Slot_inst_get (insn) == 3) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_ENTRY; + if (Field_m_Slot_inst_get (insn) == 1) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BF; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BT; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LOOP; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_LOOPNEZ; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LOOPGTZ; + } + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTUI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEUI; + } + } + if (Field_op0_Slot_inst_get (insn) == 7) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BNONE; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BEQ; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_BLT; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_BLTU; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BALL; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_BBC; + if ((Field_r_Slot_inst_get (insn) == 6 || + Field_r_Slot_inst_get (insn) == 7)) + return OPCODE_BBCI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_BANY; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_BNE; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_BGE; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_BGEU; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_BNALL; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_BBS; + if ((Field_r_Slot_inst_get (insn) == 14 || + Field_r_Slot_inst_get (insn) == 15)) + return OPCODE_BBSI; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16b_get (insn) == 12) + { + if (Field_i_Slot_inst16b_get (insn) == 0) + return OPCODE_MOVI_N; + if (Field_i_Slot_inst16b_get (insn) == 1) + { + if (Field_z_Slot_inst16b_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_z_Slot_inst16b_get (insn) == 1) + return OPCODE_BNEZ_N; + } + } + if (Field_op0_Slot_inst16b_get (insn) == 13) + { + if (Field_r_Slot_inst16b_get (insn) == 0) + return OPCODE_MOV_N; + if (Field_r_Slot_inst16b_get (insn) == 15) + { + if (Field_t_Slot_inst16b_get (insn) == 0) + return OPCODE_RET_N; + if (Field_t_Slot_inst16b_get (insn) == 1) + return OPCODE_RETW_N; + if (Field_t_Slot_inst16b_get (insn) == 2) + return OPCODE_BREAK_N; + if (Field_t_Slot_inst16b_get (insn) == 3 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_NOP_N; + if (Field_t_Slot_inst16b_get (insn) == 6 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_ILL_N; + } + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16a_get (insn) == 8) + return OPCODE_L32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 9) + return OPCODE_S32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 10) + return OPCODE_ADD_N; + if (Field_op0_Slot_inst16a_get (insn) == 11) + return OPCODE_ADDI_N; + return XTENSA_UNDEFINED; +} + +static int +Slot_f5_s3_base_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f5_s3_base_25_1_Slot_f5_s3_base_get (insn) == 65664 && + Field_fld_f5_s3_base_0_0_Slot_f5_s3_base_get (insn) == 0) + return OPCODE_NOP; + if (Field_fld_f5_s3_base_25_16_Slot_f5_s3_base_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_f5_s3_base_25_16_Slot_f5_s3_base_get (insn) == 1) + return OPCODE_MOVI; + if (Field_fld_f5_s3_base_25_8_Slot_f5_s3_base_get (insn) == 512) + return OPCODE_MOV_N; + return XTENSA_UNDEFINED; +} + +static int +Slot_f5_s0_base_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66052) + return OPCODE_ADD; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66053) + return OPCODE_ADDX2; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66054) + return OPCODE_ADDX4; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66055) + return OPCODE_ADDX8; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66056) + return OPCODE_AND; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66057) + return OPCODE_MAX; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66058) + return OPCODE_MAXU; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66059) + return OPCODE_MIN; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66060) + return OPCODE_MINU; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66061) + return OPCODE_MOVEQZ; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66062) + return OPCODE_MOVGEZ; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66063) + return OPCODE_MOVLTZ; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66064) + return OPCODE_MOVNEZ; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66065) + return OPCODE_MUL16S; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66066) + return OPCODE_MUL16U; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66067) + return OPCODE_MULL; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66068) + return OPCODE_MULSH; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66069) + return OPCODE_MULUH; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66070) + return OPCODE_OR; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66071) + return OPCODE_SALT; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66072) + return OPCODE_SALTU; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66073) + return OPCODE_SRC; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66074) + return OPCODE_SUB; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66075) + return OPCODE_SUBX2; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66076) + return OPCODE_SUBX4; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66077) + return OPCODE_SUBX8; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66078) + return OPCODE_XOR; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66079) + return OPCODE_CLAMPS; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66080) + return OPCODE_SEXT; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66081) + return OPCODE_SRLI; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66082 && + Field_fld_f5_s0_base_7_4_Slot_f5_s0_base_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66082 && + Field_fld_f5_s0_base_7_4_Slot_f5_s0_base_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66082 && + Field_fld_f5_s0_base_7_4_Slot_f5_s0_base_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66082 && + Field_fld_f5_s0_base_7_4_Slot_f5_s0_base_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66083 && + Field_fld_f5_s0_base_11_0_Slot_f5_s0_base_get (insn) == 517) + return OPCODE_NOP; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66083 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 2 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 4) + return OPCODE_SSR; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66083 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 2 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 3) + return OPCODE_SSL; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66083 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 2 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 2) + return OPCODE_SSA8L; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66083 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 2 && + Field_fld_f5_s0_base_3_1_Slot_f5_s0_base_get (insn) == 0) + return OPCODE_SSAI; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66083 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 0) + return OPCODE_NSA; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66083 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 1) + return OPCODE_NSAU; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66096 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_f5_s0_base_36_13_Slot_f5_s0_base_get (insn) == 33024) + return OPCODE_SLLI; + if (Field_fld_f5_s0_base_36_13_Slot_f5_s0_base_get (insn) == 33025) + return OPCODE_SRAI; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4118) + return OPCODE_ADDI; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4119) + return OPCODE_ADDMI; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4120) + return OPCODE_L16SI; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4121) + return OPCODE_L16UI; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4122) + return OPCODE_L32I; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4123) + return OPCODE_L8UI; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4124) + return OPCODE_S16I; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4125) + return OPCODE_S32I; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4126) + return OPCODE_S8I; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4127) + return OPCODE_MOVI; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4131 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4131 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4131 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_f5_s0_base_36_17_Slot_f5_s0_base_get (insn) == 2058) + return OPCODE_EXTUI; + if (Field_fld_f5_s0_base_36_18_Slot_f5_s0_base_get (insn) == 1028) + return OPCODE_J; + if (Field_fld_f5_s0_base_36_20_Slot_f5_s0_base_get (insn) == 256) + return OPCODE_CONST16; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_9_Slot_f5_s0_base_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_9_Slot_f5_s0_base_get (insn) == 1) + return OPCODE_BBSI_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 8) + return OPCODE_BEQ_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 14) + return OPCODE_BNE_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 10) + return OPCODE_BGE_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 12) + return OPCODE_BLT_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 9) + return OPCODE_BGEU_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 11) + return OPCODE_BLTU_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 5) + return OPCODE_BANY_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 4) + return OPCODE_BALL_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 13) + return OPCODE_BNALL_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 6) + return OPCODE_BBC_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 7) + return OPCODE_BBS_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 6) + return OPCODE_BEQZ_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 3 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 6) + return OPCODE_BNEZ_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 6) + return OPCODE_BGEZ_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 2 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 6) + return OPCODE_BLTZ_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 5) + return OPCODE_BNEI_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 1) + return OPCODE_BGEI_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 3) + return OPCODE_BLTI_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 2) + return OPCODE_BGEUI_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 4) + return OPCODE_BLTUI_W15; + return XTENSA_UNDEFINED; +} + +static int +Slot_f5_s1_base_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 148) + return OPCODE_ADD; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 149) + return OPCODE_ADDX2; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 150) + return OPCODE_ADDX4; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 151) + return OPCODE_ADDX8; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 152) + return OPCODE_AND; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 153) + return OPCODE_MAX; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 154) + return OPCODE_MAXU; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 155) + return OPCODE_MIN; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 156) + return OPCODE_MINU; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 157) + return OPCODE_MOVEQZ; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 158) + return OPCODE_MOVGEZ; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 159) + return OPCODE_MOVLTZ; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 160) + return OPCODE_MOVNEZ; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 161) + return OPCODE_OR; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 162) + return OPCODE_SALT; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 163) + return OPCODE_SALTU; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 164) + return OPCODE_SRLI; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 165) + return OPCODE_SUB; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 166) + return OPCODE_SUBX2; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 167) + return OPCODE_SUBX4; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 168) + return OPCODE_SUBX8; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 169) + return OPCODE_XOR; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 170) + return OPCODE_CLAMPS; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 171) + return OPCODE_SEXT; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 172 && + Field_fld_f5_s1_base_7_4_Slot_f5_s1_base_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 172 && + Field_fld_f5_s1_base_7_4_Slot_f5_s1_base_get (insn) == 2) + return OPCODE_SRL; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 172 && + Field_fld_f5_s1_base_7_4_Slot_f5_s1_base_get (insn) == 1) + return OPCODE_SRA; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 173 && + Field_fld_f5_s1_base_3_0_Slot_f5_s1_base_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_f5_s1_base_27_13_Slot_f5_s1_base_get (insn) == 72) + return OPCODE_SRAI; + if (Field_fld_f5_s1_base_27_13_Slot_f5_s1_base_get (insn) == 73) + return OPCODE_SLLI; + if (Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_get (insn) == 4) + return OPCODE_L16SI; + if (Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_get (insn) == 5) + return OPCODE_L16UI; + if (Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_get (insn) == 6) + return OPCODE_L32I; + if (Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_get (insn) == 7) + return OPCODE_L8UI; + if (Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_get (insn) == 8) + return OPCODE_MOVI; + if (Field_fld_f5_s1_base_27_17_Slot_f5_s1_base_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_f5_s1_base_27_3_Slot_f5_s1_base_get (insn) == 88070 && + Field_fld_f5_s1_base_2_0_Slot_f5_s1_base_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_f5_s2_base_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 52) + return OPCODE_ADD; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 53) + return OPCODE_ADDX2; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 54) + return OPCODE_ADDX4; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 55) + return OPCODE_ADDX8; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 56) + return OPCODE_AND; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 57) + return OPCODE_MAX; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 58) + return OPCODE_MAXU; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 59) + return OPCODE_MIN; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 60) + return OPCODE_MINU; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 61) + return OPCODE_MOVEQZ; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 62) + return OPCODE_MOVGEZ; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 63) + return OPCODE_MOVLTZ; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 64) + return OPCODE_MOVNEZ; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 65) + return OPCODE_OR; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 66) + return OPCODE_SALT; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 67) + return OPCODE_SALTU; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 68) + return OPCODE_SRC; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 69) + return OPCODE_SRLI; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 70) + return OPCODE_SUB; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 71) + return OPCODE_SUBX2; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 72) + return OPCODE_SUBX4; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 73) + return OPCODE_SUBX8; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 74) + return OPCODE_XOR; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 75 && + Field_fld_f5_s2_base_7_4_Slot_f5_s2_base_get (insn) == 0) + return OPCODE_NEG; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 75 && + Field_fld_f5_s2_base_7_4_Slot_f5_s2_base_get (insn) == 2) + return OPCODE_SRL; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 75 && + Field_fld_f5_s2_base_7_4_Slot_f5_s2_base_get (insn) == 1) + return OPCODE_SRA; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 77 && + Field_fld_f5_s2_base_3_0_Slot_f5_s2_base_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_f5_s2_base_26_13_Slot_f5_s2_base_get (insn) == 24) + return OPCODE_SRAI; + if (Field_fld_f5_s2_base_26_13_Slot_f5_s2_base_get (insn) == 25) + return OPCODE_SLLI; + if (Field_fld_f5_s2_base_26_16_Slot_f5_s2_base_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_f5_s2_base_26_16_Slot_f5_s2_base_get (insn) == 1) + return OPCODE_ADDMI; + if (Field_fld_f5_s2_base_26_16_Slot_f5_s2_base_get (insn) == 2) + return OPCODE_MOVI; + if (Field_fld_f5_s2_base_26_2_Slot_f5_s2_base_get (insn) == 78848 && + Field_fld_f5_s2_base_1_0_Slot_f5_s2_base_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_f5_s2_base_26_8_Slot_f5_s2_base_get (insn) == 1216) + return OPCODE_NSA; + if (Field_fld_f5_s2_base_26_8_Slot_f5_s2_base_get (insn) == 1217) + return OPCODE_NSAU; + return XTENSA_UNDEFINED; +} + +static int +Slot_n1_s1_none_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_n1_s1_none_3_0_Slot_n1_s1_none_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_n0_s1_none_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_n0_s1_none_2_0_Slot_n0_s1_none_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_n0_s2_none_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_n0_s2_none_2_0_Slot_n0_s2_none_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_f0_Format_f0_s0_ldst_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[0] & 0x3e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x2) >> 1) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc000) | (((insn[1] & 0x600) >> 9) << 14); + slotbuf[0] = (slotbuf[0] & ~0x1ff0000) | (((insn[2] & 0xff800000) >> 23) << 16); + slotbuf[0] = (slotbuf[0] & ~0x1e000000) | ((insn[3] & 0xf) << 25); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x1000) >> 12) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x2000) >> 13) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x4000) >> 14) << 31); + slotbuf[1] = ((insn[3] & 0x8000) >> 15); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[3] & 0x10000) >> 16) << 1); +} + +static void +Slot_f0_Format_f0_s0_ldst_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0x3e0000) | (((slotbuf[0] & 0x1f00) >> 8) << 17); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x2000) >> 13) << 1); + insn[1] = (insn[1] & ~0x600) | (((slotbuf[0] & 0xc000) >> 14) << 9); + insn[2] = (insn[2] & ~0xff800000) | (((slotbuf[0] & 0x1ff0000) >> 16) << 23); + insn[3] = (insn[3] & ~0xf) | ((slotbuf[0] & 0x1e000000) >> 25); + insn[3] = (insn[3] & ~0x1000) | (((slotbuf[0] & 0x20000000) >> 29) << 12); + insn[3] = (insn[3] & ~0x2000) | (((slotbuf[0] & 0x40000000) >> 30) << 13); + insn[3] = (insn[3] & ~0x4000) | (((slotbuf[0] & 0x80000000) >> 31) << 14); + insn[3] = (insn[3] & ~0x8000) | ((slotbuf[1] & 0x1) << 15); + insn[3] = (insn[3] & ~0x10000) | (((slotbuf[1] & 0x2) >> 1) << 16); +} + +static void +Slot_f0_Format_f0_s1_ld_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xe0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x8) | (((insn[0] & 0x10000) >> 16) << 3); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0x3c00000) >> 22) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf0000000) >> 28) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x8000000) >> 27) << 12); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x4) >> 2) << 13); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[1] & 0x20000) >> 17) << 14); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[1] & 0x4000000) >> 26) << 15); + slotbuf[0] = (slotbuf[0] & ~0x30000) | (((insn[0] & 0xc000000) >> 26) << 16); + slotbuf[0] = (slotbuf[0] & ~0x1c0000) | (((insn[3] & 0x70) >> 4) << 18); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x80000) >> 19) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x100000) >> 20) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x200000) >> 21) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x400000) >> 22) << 24); +} + +static void +Slot_f0_Format_f0_s1_ld_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xe0) | ((slotbuf[0] & 0x7) << 5); + insn[0] = (insn[0] & ~0x10000) | (((slotbuf[0] & 0x8) >> 3) << 16); + insn[0] = (insn[0] & ~0x3c00000) | (((slotbuf[0] & 0xf0) >> 4) << 22); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf00) >> 8) << 28); + insn[1] = (insn[1] & ~0x8000000) | (((slotbuf[0] & 0x1000) >> 12) << 27); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[0] & 0x2000) >> 13) << 2); + insn[1] = (insn[1] & ~0x20000) | (((slotbuf[0] & 0x4000) >> 14) << 17); + insn[1] = (insn[1] & ~0x4000000) | (((slotbuf[0] & 0x8000) >> 15) << 26); + insn[0] = (insn[0] & ~0xc000000) | (((slotbuf[0] & 0x30000) >> 16) << 26); + insn[3] = (insn[3] & ~0x70) | (((slotbuf[0] & 0x1c0000) >> 18) << 4); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x200000) >> 21) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x400000) >> 22) << 20); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x800000) >> 23) << 21); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x1000000) >> 24) << 22); +} + +static void +Slot_f0_Format_f0_s2_mul_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x10) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x2) | ((insn[1] & 0x1) << 1); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[1] & 0x6000) >> 13) << 2); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[1] & 0x40000) >> 18) << 4); + slotbuf[0] = (slotbuf[0] & ~0xe0) | (((insn[1] & 0x3800000) >> 23) << 5); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[1] & 0x780000) >> 19) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x80000000) >> 31) << 12); + slotbuf[0] = (slotbuf[0] & ~0x2000) | ((insn[2] & 0x1) << 13); + slotbuf[0] = (slotbuf[0] & ~0x7c000) | (((insn[2] & 0xf800) >> 11) << 14); + slotbuf[0] = (slotbuf[0] & ~0x180000) | (((insn[1] & 0x18000) >> 15) << 19); + slotbuf[0] = (slotbuf[0] & ~0x600000) | (((insn[3] & 0x180) >> 7) << 21); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x800000) >> 23) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x1000000) >> 24) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x4000000) >> 26) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x8000000) >> 27) << 26); +} + +static void +Slot_f0_Format_f0_s2_mul_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x10) | ((slotbuf[0] & 0x1) << 4); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x2) >> 1); + insn[1] = (insn[1] & ~0x6000) | (((slotbuf[0] & 0xc) >> 2) << 13); + insn[1] = (insn[1] & ~0x40000) | (((slotbuf[0] & 0x10) >> 4) << 18); + insn[1] = (insn[1] & ~0x3800000) | (((slotbuf[0] & 0xe0) >> 5) << 23); + insn[1] = (insn[1] & ~0x780000) | (((slotbuf[0] & 0xf00) >> 8) << 19); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x1000) >> 12) << 31); + insn[2] = (insn[2] & ~0x1) | ((slotbuf[0] & 0x2000) >> 13); + insn[2] = (insn[2] & ~0xf800) | (((slotbuf[0] & 0x7c000) >> 14) << 11); + insn[1] = (insn[1] & ~0x18000) | (((slotbuf[0] & 0x180000) >> 19) << 15); + insn[3] = (insn[3] & ~0x180) | (((slotbuf[0] & 0x600000) >> 21) << 7); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x800000) >> 23) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x1000000) >> 24) << 24); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x2000000) >> 25) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x4000000) >> 26) << 27); +} + +static void +Slot_f0_Format_f0_s3_alu_35_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0x400000) >> 22); + slotbuf[0] = (slotbuf[0] & ~0x7e) | (((insn[1] & 0x1f8) >> 3) << 1); + slotbuf[0] = (slotbuf[0] & ~0x180) | (((insn[1] & 0x1800) >> 11) << 7); + slotbuf[0] = (slotbuf[0] & ~0x200) | (((insn[1] & 0x10000000) >> 28) << 9); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[2] & 0x7c0) >> 6) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[2] & 0x3e) >> 1) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[2] & 0x1f0000) >> 16) << 20); + slotbuf[0] = (slotbuf[0] & ~0x6000000) | (((insn[1] & 0x60000000) >> 29) << 25); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[2] & 0x200000) >> 21) << 27); + slotbuf[0] = (slotbuf[0] & ~0x30000000) | (((insn[3] & 0x600) >> 9) << 28); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x10000000) >> 28) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x20000000) >> 29) << 31); + slotbuf[1] = ((insn[3] & 0x40000000) >> 30); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[3] & 0x80000000) >> 31) << 1); +} + +static void +Slot_f0_Format_f0_s3_alu_35_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0x400000) | ((slotbuf[0] & 0x1) << 22); + insn[1] = (insn[1] & ~0x1f8) | (((slotbuf[0] & 0x7e) >> 1) << 3); + insn[1] = (insn[1] & ~0x1800) | (((slotbuf[0] & 0x180) >> 7) << 11); + insn[1] = (insn[1] & ~0x10000000) | (((slotbuf[0] & 0x200) >> 9) << 28); + insn[2] = (insn[2] & ~0x7c0) | (((slotbuf[0] & 0x7c00) >> 10) << 6); + insn[2] = (insn[2] & ~0x3e) | (((slotbuf[0] & 0xf8000) >> 15) << 1); + insn[2] = (insn[2] & ~0x1f0000) | (((slotbuf[0] & 0x1f00000) >> 20) << 16); + insn[1] = (insn[1] & ~0x60000000) | (((slotbuf[0] & 0x6000000) >> 25) << 29); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[0] & 0x8000000) >> 27) << 21); + insn[3] = (insn[3] & ~0x600) | (((slotbuf[0] & 0x30000000) >> 28) << 9); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x40000000) >> 30) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x80000000) >> 31) << 29); + insn[3] = (insn[3] & ~0x40000000) | ((slotbuf[1] & 0x1) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x2) >> 1) << 31); +} + +static void +Slot_f1_Format_f1_s0_ldstalu_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[0] & 0x3e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[1] & 0x300000) >> 20) << 13); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[1] & 0x2) >> 1) << 15); + slotbuf[0] = (slotbuf[0] & ~0x30000) | (((insn[1] & 0x600) >> 9) << 16); + slotbuf[0] = (slotbuf[0] & ~0x1c0000) | (((insn[2] & 0xe) >> 1) << 18); + slotbuf[0] = (slotbuf[0] & ~0x1e00000) | (((insn[2] & 0x7800) >> 11) << 21); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x80) >> 7) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x100) >> 8) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x200) >> 9) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x400) >> 10) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x1000) >> 12) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x2000) >> 13) << 30); +} + +static void +Slot_f1_Format_f1_s0_ldstalu_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0x3e0000) | (((slotbuf[0] & 0x1f00) >> 8) << 17); + insn[1] = (insn[1] & ~0x300000) | (((slotbuf[0] & 0x6000) >> 13) << 20); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x8000) >> 15) << 1); + insn[1] = (insn[1] & ~0x600) | (((slotbuf[0] & 0x30000) >> 16) << 9); + insn[2] = (insn[2] & ~0xe) | (((slotbuf[0] & 0x1c0000) >> 18) << 1); + insn[2] = (insn[2] & ~0x7800) | (((slotbuf[0] & 0x1e00000) >> 21) << 11); + insn[3] = (insn[3] & ~0x80) | (((slotbuf[0] & 0x2000000) >> 25) << 7); + insn[3] = (insn[3] & ~0x100) | (((slotbuf[0] & 0x4000000) >> 26) << 8); + insn[3] = (insn[3] & ~0x200) | (((slotbuf[0] & 0x8000000) >> 27) << 9); + insn[3] = (insn[3] & ~0x400) | (((slotbuf[0] & 0x10000000) >> 28) << 10); + insn[3] = (insn[3] & ~0x1000) | (((slotbuf[0] & 0x20000000) >> 29) << 12); + insn[3] = (insn[3] & ~0x2000) | (((slotbuf[0] & 0x40000000) >> 30) << 13); +} + +static void +Slot_f1_Format_f1_s1_ld_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xe0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x8) | (((insn[0] & 0x10000) >> 16) << 3); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0x3c00000) >> 22) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf0000000) >> 28) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | ((insn[2] & 0x1) << 12); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x80000) >> 19) << 13); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[1] & 0x20000) >> 17) << 14); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[1] & 0x1c000000) >> 26) << 15); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x8000) >> 15) << 18); + slotbuf[0] = (slotbuf[0] & ~0x180000) | (((insn[2] & 0xc00000) >> 22) << 19); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[2] & 0x8000000) >> 27) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x4000) >> 14) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x8000) >> 15) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x10000) >> 16) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x80000) >> 19) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x100000) >> 20) << 26); +} + +static void +Slot_f1_Format_f1_s1_ld_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xe0) | ((slotbuf[0] & 0x7) << 5); + insn[0] = (insn[0] & ~0x10000) | (((slotbuf[0] & 0x8) >> 3) << 16); + insn[0] = (insn[0] & ~0x3c00000) | (((slotbuf[0] & 0xf0) >> 4) << 22); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf00) >> 8) << 28); + insn[2] = (insn[2] & ~0x1) | ((slotbuf[0] & 0x1000) >> 12); + insn[1] = (insn[1] & ~0x80000) | (((slotbuf[0] & 0x2000) >> 13) << 19); + insn[1] = (insn[1] & ~0x20000) | (((slotbuf[0] & 0x4000) >> 14) << 17); + insn[1] = (insn[1] & ~0x1c000000) | (((slotbuf[0] & 0x38000) >> 15) << 26); + insn[2] = (insn[2] & ~0x8000) | (((slotbuf[0] & 0x40000) >> 18) << 15); + insn[2] = (insn[2] & ~0xc00000) | (((slotbuf[0] & 0x180000) >> 19) << 22); + insn[2] = (insn[2] & ~0x8000000) | (((slotbuf[0] & 0x200000) >> 21) << 27); + insn[3] = (insn[3] & ~0x4000) | (((slotbuf[0] & 0x400000) >> 22) << 14); + insn[3] = (insn[3] & ~0x8000) | (((slotbuf[0] & 0x800000) >> 23) << 15); + insn[3] = (insn[3] & ~0x10000) | (((slotbuf[0] & 0x1000000) >> 24) << 16); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x2000000) >> 25) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x4000000) >> 26) << 20); +} + +static void +Slot_f1_Format_f1_s2_mul_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x10) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x2) | ((insn[1] & 0x1) << 1); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[1] & 0x6000) >> 13) << 2); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[1] & 0x40000) >> 18) << 4); + slotbuf[0] = (slotbuf[0] & ~0xe0) | (((insn[1] & 0x3800000) >> 23) << 5); + slotbuf[0] = (slotbuf[0] & ~0x100) | (((insn[1] & 0x80000000) >> 31) << 8); + slotbuf[0] = (slotbuf[0] & ~0x200) | (((insn[1] & 0x400000) >> 22) << 9); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[2] & 0x1f0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x7000000) >> 24) << 15); + slotbuf[0] = (slotbuf[0] & ~0x3c0000) | (((insn[2] & 0xf0000000) >> 28) << 18); + slotbuf[0] = (slotbuf[0] & ~0xc00000) | ((insn[3] & 0x3) << 22); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x200000) >> 21) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x400000) >> 22) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x800000) >> 23) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x1000000) >> 24) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x4000000) >> 26) << 28); +} + +static void +Slot_f1_Format_f1_s2_mul_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x10) | ((slotbuf[0] & 0x1) << 4); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x2) >> 1); + insn[1] = (insn[1] & ~0x6000) | (((slotbuf[0] & 0xc) >> 2) << 13); + insn[1] = (insn[1] & ~0x40000) | (((slotbuf[0] & 0x10) >> 4) << 18); + insn[1] = (insn[1] & ~0x3800000) | (((slotbuf[0] & 0xe0) >> 5) << 23); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x100) >> 8) << 31); + insn[1] = (insn[1] & ~0x400000) | (((slotbuf[0] & 0x200) >> 9) << 22); + insn[2] = (insn[2] & ~0x1f0000) | (((slotbuf[0] & 0x7c00) >> 10) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0x38000) >> 15) << 24); + insn[2] = (insn[2] & ~0xf0000000) | (((slotbuf[0] & 0x3c0000) >> 18) << 28); + insn[3] = (insn[3] & ~0x3) | ((slotbuf[0] & 0xc00000) >> 22); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x1000000) >> 24) << 21); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x2000000) >> 25) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x4000000) >> 26) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x8000000) >> 27) << 24); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x10000000) >> 28) << 26); +} + +static void +Slot_f1_Format_f1_s3_alu_26_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x3c) >> 2); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[0] & 0x8000000) >> 27) << 4); + slotbuf[0] = (slotbuf[0] & ~0x20) | (((insn[0] & 0x4000000) >> 26) << 5); + slotbuf[0] = (slotbuf[0] & ~0xc0) | (((insn[1] & 0x18000) >> 15) << 6); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[2] & 0x600) >> 9) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1c00) | (((insn[1] & 0x1c0) >> 6) << 10); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[1] & 0x1800) >> 11) << 13); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x1c0) >> 6) << 15); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[2] & 0x30) >> 4) << 18); + slotbuf[0] = (slotbuf[0] & ~0x300000) | (((insn[1] & 0x60000000) >> 29) << 20); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[2] & 0x200000) >> 21) << 22); + slotbuf[0] = (slotbuf[0] & ~0x3800000) | (((insn[3] & 0x1c) >> 2) << 23); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x8000000) >> 27) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x10000000) >> 28) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x20000000) >> 29) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x40000000) >> 30) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x80000000) >> 31) << 30); +} + +static void +Slot_f1_Format_f1_s3_alu_26_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x3c) | ((slotbuf[0] & 0xf) << 2); + insn[0] = (insn[0] & ~0x8000000) | (((slotbuf[0] & 0x10) >> 4) << 27); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x20) >> 5) << 26); + insn[1] = (insn[1] & ~0x18000) | (((slotbuf[0] & 0xc0) >> 6) << 15); + insn[2] = (insn[2] & ~0x600) | (((slotbuf[0] & 0x300) >> 8) << 9); + insn[1] = (insn[1] & ~0x1c0) | (((slotbuf[0] & 0x1c00) >> 10) << 6); + insn[1] = (insn[1] & ~0x1800) | (((slotbuf[0] & 0x6000) >> 13) << 11); + insn[2] = (insn[2] & ~0x1c0) | (((slotbuf[0] & 0x38000) >> 15) << 6); + insn[2] = (insn[2] & ~0x30) | (((slotbuf[0] & 0xc0000) >> 18) << 4); + insn[1] = (insn[1] & ~0x60000000) | (((slotbuf[0] & 0x300000) >> 20) << 29); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[0] & 0x400000) >> 22) << 21); + insn[3] = (insn[3] & ~0x1c) | (((slotbuf[0] & 0x3800000) >> 23) << 2); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x4000000) >> 26) << 27); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x8000000) >> 27) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x10000000) >> 28) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x20000000) >> 29) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x40000000) >> 30) << 31); +} + +static void +Slot_f2_Format_f2_s0_ldst_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0x1e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[2] & 0x400) >> 10) << 12); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x2) >> 1) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc000) | (((insn[1] & 0x600) >> 9) << 14); + slotbuf[0] = (slotbuf[0] & ~0x70000) | (((insn[2] & 0xe) >> 1) << 16); + slotbuf[0] = (slotbuf[0] & ~0x380000) | (((insn[2] & 0x70000) >> 16) << 19); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[2] & 0x800000) >> 23) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x80) >> 7) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x100) >> 8) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x200) >> 9) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x400) >> 10) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x1000) >> 12) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x2000) >> 13) << 28); +} + +static void +Slot_f2_Format_f2_s0_ldst_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0x1e0000) | (((slotbuf[0] & 0xf00) >> 8) << 17); + insn[2] = (insn[2] & ~0x400) | (((slotbuf[0] & 0x1000) >> 12) << 10); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x2000) >> 13) << 1); + insn[1] = (insn[1] & ~0x600) | (((slotbuf[0] & 0xc000) >> 14) << 9); + insn[2] = (insn[2] & ~0xe) | (((slotbuf[0] & 0x70000) >> 16) << 1); + insn[2] = (insn[2] & ~0x70000) | (((slotbuf[0] & 0x380000) >> 19) << 16); + insn[2] = (insn[2] & ~0x800000) | (((slotbuf[0] & 0x400000) >> 22) << 23); + insn[3] = (insn[3] & ~0x80) | (((slotbuf[0] & 0x800000) >> 23) << 7); + insn[3] = (insn[3] & ~0x100) | (((slotbuf[0] & 0x1000000) >> 24) << 8); + insn[3] = (insn[3] & ~0x200) | (((slotbuf[0] & 0x2000000) >> 25) << 9); + insn[3] = (insn[3] & ~0x400) | (((slotbuf[0] & 0x4000000) >> 26) << 10); + insn[3] = (insn[3] & ~0x1000) | (((slotbuf[0] & 0x8000000) >> 27) << 12); + insn[3] = (insn[3] & ~0x2000) | (((slotbuf[0] & 0x10000000) >> 28) << 13); +} + +static void +Slot_f2_Format_f2_s1_ld_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xe0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x8) | (((insn[0] & 0x10000) >> 16) << 3); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0x3c00000) >> 22) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf0000000) >> 28) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | ((insn[2] & 0x1) << 12); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x4) >> 2) << 13); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[1] & 0x20000) >> 17) << 14); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[1] & 0x1c000000) >> 26) << 15); + slotbuf[0] = (slotbuf[0] & ~0x3c0000) | (((insn[2] & 0x1e000000) >> 25) << 18); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x4000) >> 14) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x8000) >> 15) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x10000) >> 16) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x80000) >> 19) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x100000) >> 20) << 26); +} + +static void +Slot_f2_Format_f2_s1_ld_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xe0) | ((slotbuf[0] & 0x7) << 5); + insn[0] = (insn[0] & ~0x10000) | (((slotbuf[0] & 0x8) >> 3) << 16); + insn[0] = (insn[0] & ~0x3c00000) | (((slotbuf[0] & 0xf0) >> 4) << 22); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf00) >> 8) << 28); + insn[2] = (insn[2] & ~0x1) | ((slotbuf[0] & 0x1000) >> 12); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[0] & 0x2000) >> 13) << 2); + insn[1] = (insn[1] & ~0x20000) | (((slotbuf[0] & 0x4000) >> 14) << 17); + insn[1] = (insn[1] & ~0x1c000000) | (((slotbuf[0] & 0x38000) >> 15) << 26); + insn[2] = (insn[2] & ~0x1e000000) | (((slotbuf[0] & 0x3c0000) >> 18) << 25); + insn[3] = (insn[3] & ~0x4000) | (((slotbuf[0] & 0x400000) >> 22) << 14); + insn[3] = (insn[3] & ~0x8000) | (((slotbuf[0] & 0x800000) >> 23) << 15); + insn[3] = (insn[3] & ~0x10000) | (((slotbuf[0] & 0x1000000) >> 24) << 16); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x2000000) >> 25) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x4000000) >> 26) << 20); +} + +static void +Slot_f2_Format_f2_s2_mul_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x10) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x2) | ((insn[1] & 0x1) << 1); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[1] & 0x6000) >> 13) << 2); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[1] & 0x40000) >> 18) << 4); + slotbuf[0] = (slotbuf[0] & ~0xe0) | (((insn[1] & 0x3800000) >> 23) << 5); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[2] & 0x180000) >> 19) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[2] & 0xf800) >> 11) << 10); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[0] & 0x8000000) >> 27) << 15); + slotbuf[0] = (slotbuf[0] & ~0xf0000) | (((insn[1] & 0x780000) >> 19) << 16); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[1] & 0x80000000) >> 31) << 20); + slotbuf[0] = (slotbuf[0] & ~0xe00000) | (((insn[2] & 0xe0000000) >> 29) << 21); + slotbuf[0] = (slotbuf[0] & ~0x3000000) | ((insn[3] & 0x3) << 24); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x200000) >> 21) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x400000) >> 22) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x800000) >> 23) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x1000000) >> 24) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x4000000) >> 26) << 30); +} + +static void +Slot_f2_Format_f2_s2_mul_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x10) | ((slotbuf[0] & 0x1) << 4); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x2) >> 1); + insn[1] = (insn[1] & ~0x6000) | (((slotbuf[0] & 0xc) >> 2) << 13); + insn[1] = (insn[1] & ~0x40000) | (((slotbuf[0] & 0x10) >> 4) << 18); + insn[1] = (insn[1] & ~0x3800000) | (((slotbuf[0] & 0xe0) >> 5) << 23); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x300) >> 8) << 19); + insn[2] = (insn[2] & ~0xf800) | (((slotbuf[0] & 0x7c00) >> 10) << 11); + insn[0] = (insn[0] & ~0x8000000) | (((slotbuf[0] & 0x8000) >> 15) << 27); + insn[1] = (insn[1] & ~0x780000) | (((slotbuf[0] & 0xf0000) >> 16) << 19); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x100000) >> 20) << 31); + insn[2] = (insn[2] & ~0xe0000000) | (((slotbuf[0] & 0xe00000) >> 21) << 29); + insn[3] = (insn[3] & ~0x3) | ((slotbuf[0] & 0x3000000) >> 24); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x4000000) >> 26) << 21); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x8000000) >> 27) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x10000000) >> 28) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x20000000) >> 29) << 24); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x40000000) >> 30) << 26); +} + +static void +Slot_f2_Format_f2_s3_alu_21_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0x400000) >> 22); + slotbuf[0] = (slotbuf[0] & ~0xe) | (((insn[1] & 0x38) >> 3) << 1); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[0] & 0x200000) >> 21) << 4); + slotbuf[0] = (slotbuf[0] & ~0x20) | (((insn[0] & 0x4000000) >> 26) << 5); + slotbuf[0] = (slotbuf[0] & ~0xc0) | (((insn[1] & 0x18000) >> 15) << 6); + slotbuf[0] = (slotbuf[0] & ~0x100) | (((insn[2] & 0x200) >> 9) << 8); + slotbuf[0] = (slotbuf[0] & ~0x200) | (((insn[2] & 0x1000000) >> 24) << 9); + slotbuf[0] = (slotbuf[0] & ~0x1c00) | (((insn[1] & 0x1c0) >> 6) << 10); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[1] & 0x1800) >> 11) << 13); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x1c0) >> 6) << 15); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[2] & 0x30) >> 4) << 18); + slotbuf[0] = (slotbuf[0] & ~0x300000) | (((insn[1] & 0x60000000) >> 29) << 20); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[2] & 0x200000) >> 21) << 22); + slotbuf[0] = (slotbuf[0] & ~0x3800000) | (((insn[3] & 0x1c) >> 2) << 23); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x8000000) >> 27) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x10000000) >> 28) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x20000000) >> 29) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x40000000) >> 30) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x80000000) >> 31) << 30); +} + +static void +Slot_f2_Format_f2_s3_alu_21_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0x400000) | ((slotbuf[0] & 0x1) << 22); + insn[1] = (insn[1] & ~0x38) | (((slotbuf[0] & 0xe) >> 1) << 3); + insn[0] = (insn[0] & ~0x200000) | (((slotbuf[0] & 0x10) >> 4) << 21); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x20) >> 5) << 26); + insn[1] = (insn[1] & ~0x18000) | (((slotbuf[0] & 0xc0) >> 6) << 15); + insn[2] = (insn[2] & ~0x200) | (((slotbuf[0] & 0x100) >> 8) << 9); + insn[2] = (insn[2] & ~0x1000000) | (((slotbuf[0] & 0x200) >> 9) << 24); + insn[1] = (insn[1] & ~0x1c0) | (((slotbuf[0] & 0x1c00) >> 10) << 6); + insn[1] = (insn[1] & ~0x1800) | (((slotbuf[0] & 0x6000) >> 13) << 11); + insn[2] = (insn[2] & ~0x1c0) | (((slotbuf[0] & 0x38000) >> 15) << 6); + insn[2] = (insn[2] & ~0x30) | (((slotbuf[0] & 0xc0000) >> 18) << 4); + insn[1] = (insn[1] & ~0x60000000) | (((slotbuf[0] & 0x300000) >> 20) << 29); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[0] & 0x400000) >> 22) << 21); + insn[3] = (insn[3] & ~0x1c) | (((slotbuf[0] & 0x3800000) >> 23) << 2); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x4000000) >> 26) << 27); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x8000000) >> 27) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x10000000) >> 28) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x20000000) >> 29) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x40000000) >> 30) << 31); +} + +static void +Slot_f3_Format_f3_s0_ldst_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[0] & 0x3e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x2) >> 1) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc000) | (((insn[1] & 0x600) >> 9) << 14); + slotbuf[0] = (slotbuf[0] & ~0x30000) | (((insn[2] & 0xc0000000) >> 30) << 16); + slotbuf[0] = (slotbuf[0] & ~0xfc0000) | ((insn[3] & 0x3f) << 18); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x4000000) >> 26) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x8000000) >> 27) << 25); +} + +static void +Slot_f3_Format_f3_s0_ldst_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0x3e0000) | (((slotbuf[0] & 0x1f00) >> 8) << 17); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x2000) >> 13) << 1); + insn[1] = (insn[1] & ~0x600) | (((slotbuf[0] & 0xc000) >> 14) << 9); + insn[2] = (insn[2] & ~0xc0000000) | (((slotbuf[0] & 0x30000) >> 16) << 30); + insn[3] = (insn[3] & ~0x3f) | ((slotbuf[0] & 0xfc0000) >> 18); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x1000000) >> 24) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x2000000) >> 25) << 27); +} + +static void +Slot_f3_Format_f3_s1_ld_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xe0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x8) | (((insn[0] & 0x10000) >> 16) << 3); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0x3c00000) >> 22) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf0000000) >> 28) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x20000) >> 17) << 12); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[0] & 0xc000000) >> 26) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1f8000) | (((insn[3] & 0xfc0) >> 6) << 15); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x10000000) >> 28) << 21); +} + +static void +Slot_f3_Format_f3_s1_ld_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xe0) | ((slotbuf[0] & 0x7) << 5); + insn[0] = (insn[0] & ~0x10000) | (((slotbuf[0] & 0x8) >> 3) << 16); + insn[0] = (insn[0] & ~0x3c00000) | (((slotbuf[0] & 0xf0) >> 4) << 22); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf00) >> 8) << 28); + insn[1] = (insn[1] & ~0x20000) | (((slotbuf[0] & 0x1000) >> 12) << 17); + insn[0] = (insn[0] & ~0xc000000) | (((slotbuf[0] & 0x6000) >> 13) << 26); + insn[3] = (insn[3] & ~0xfc0) | (((slotbuf[0] & 0x1f8000) >> 15) << 6); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x200000) >> 21) << 28); +} + +static void +Slot_f3_Format_f3_s2_mul_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x10) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x2) | ((insn[1] & 0x1) << 1); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[1] & 0x6000) >> 13) << 2); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[1] & 0x40000) >> 18) << 4); + slotbuf[0] = (slotbuf[0] & ~0xe0) | (((insn[1] & 0x3800000) >> 23) << 5); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[1] & 0x780000) >> 19) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3000) | (((insn[1] & 0xc000000) >> 26) << 12); + slotbuf[0] = (slotbuf[0] & ~0xc000) | (((insn[1] & 0x18000) >> 15) << 14); + slotbuf[0] = (slotbuf[0] & ~0x1f0000) | (((insn[3] & 0x1f000) >> 12) << 16); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x20000000) >> 29) << 21); +} + +static void +Slot_f3_Format_f3_s2_mul_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x10) | ((slotbuf[0] & 0x1) << 4); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x2) >> 1); + insn[1] = (insn[1] & ~0x6000) | (((slotbuf[0] & 0xc) >> 2) << 13); + insn[1] = (insn[1] & ~0x40000) | (((slotbuf[0] & 0x10) >> 4) << 18); + insn[1] = (insn[1] & ~0x3800000) | (((slotbuf[0] & 0xe0) >> 5) << 23); + insn[1] = (insn[1] & ~0x780000) | (((slotbuf[0] & 0xf00) >> 8) << 19); + insn[1] = (insn[1] & ~0xc000000) | (((slotbuf[0] & 0x3000) >> 12) << 26); + insn[1] = (insn[1] & ~0x18000) | (((slotbuf[0] & 0xc000) >> 14) << 15); + insn[3] = (insn[3] & ~0x1f000) | (((slotbuf[0] & 0x1f0000) >> 16) << 12); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x200000) >> 21) << 29); +} + +static void +Slot_f3_Format_f3_s3_alu_34_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1fc) >> 2); + slotbuf[0] = (slotbuf[0] & ~0x180) | (((insn[1] & 0x1800) >> 11) << 7); + slotbuf[0] = (slotbuf[0] & ~0x1e00) | (((insn[1] & 0xf0000000) >> 28) << 9); + slotbuf[0] = (slotbuf[0] & ~0x7e000) | ((insn[2] & 0x3f) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1f80000) | (((insn[2] & 0x7e00000) >> 21) << 19); + slotbuf[0] = (slotbuf[0] & ~0xe000000) | (((insn[3] & 0xe0000) >> 17) << 25); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x40000000) >> 30) << 28); +} + +static void +Slot_f3_Format_f3_s3_alu_34_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1fc) | ((slotbuf[0] & 0x7f) << 2); + insn[1] = (insn[1] & ~0x1800) | (((slotbuf[0] & 0x180) >> 7) << 11); + insn[1] = (insn[1] & ~0xf0000000) | (((slotbuf[0] & 0x1e00) >> 9) << 28); + insn[2] = (insn[2] & ~0x3f) | ((slotbuf[0] & 0x7e000) >> 13); + insn[2] = (insn[2] & ~0x7e00000) | (((slotbuf[0] & 0x1f80000) >> 19) << 21); + insn[3] = (insn[3] & ~0xe0000) | (((slotbuf[0] & 0xe000000) >> 25) << 17); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x10000000) >> 28) << 30); +} + +static void +Slot_f3_Format_f3_s4_alu_70_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0x1fffc0) >> 6); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x38000000) >> 27) << 15); + slotbuf[0] = (slotbuf[0] & ~0x7c0000) | (((insn[3] & 0x1f00000) >> 20) << 18); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x80000000) >> 31) << 23); +} + +static void +Slot_f3_Format_f3_s4_alu_70_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0x1fffc0) | ((slotbuf[0] & 0x7fff) << 6); + insn[2] = (insn[2] & ~0x38000000) | (((slotbuf[0] & 0x38000) >> 15) << 27); + insn[3] = (insn[3] & ~0x1f00000) | (((slotbuf[0] & 0x7c0000) >> 18) << 20); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x800000) >> 23) << 31); +} + +static void +Slot_f4_Format_f4_s0_ld_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[0] & 0x3e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x2) >> 1) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc000) | (((insn[1] & 0x600) >> 9) << 14); + slotbuf[0] = (slotbuf[0] & ~0x7f0000) | (((insn[2] & 0xfe000000) >> 25) << 16); + slotbuf[0] = (slotbuf[0] & ~0x1f800000) | ((insn[3] & 0x3f) << 23); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x80000) >> 19) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x100000) >> 20) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x200000) >> 21) << 31); +} + +static void +Slot_f4_Format_f4_s0_ld_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0x3e0000) | (((slotbuf[0] & 0x1f00) >> 8) << 17); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x2000) >> 13) << 1); + insn[1] = (insn[1] & ~0x600) | (((slotbuf[0] & 0xc000) >> 14) << 9); + insn[2] = (insn[2] & ~0xfe000000) | (((slotbuf[0] & 0x7f0000) >> 16) << 25); + insn[3] = (insn[3] & ~0x3f) | ((slotbuf[0] & 0x1f800000) >> 23); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x20000000) >> 29) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x40000000) >> 30) << 20); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x80000000) >> 31) << 21); +} + +static void +Slot_f4_Format_f4_s1_ld_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xe0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x8) | (((insn[0] & 0x10000) >> 16) << 3); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0x3c00000) >> 22) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf0000000) >> 28) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x20000) >> 17) << 12); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[0] & 0xc000000) >> 26) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1f8000) | (((insn[3] & 0xfc0) >> 6) << 15); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x400000) >> 22) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x800000) >> 23) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x1000000) >> 24) << 23); +} + +static void +Slot_f4_Format_f4_s1_ld_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xe0) | ((slotbuf[0] & 0x7) << 5); + insn[0] = (insn[0] & ~0x10000) | (((slotbuf[0] & 0x8) >> 3) << 16); + insn[0] = (insn[0] & ~0x3c00000) | (((slotbuf[0] & 0xf0) >> 4) << 22); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf00) >> 8) << 28); + insn[1] = (insn[1] & ~0x20000) | (((slotbuf[0] & 0x1000) >> 12) << 17); + insn[0] = (insn[0] & ~0xc000000) | (((slotbuf[0] & 0x6000) >> 13) << 26); + insn[3] = (insn[3] & ~0xfc0) | (((slotbuf[0] & 0x1f8000) >> 15) << 6); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x200000) >> 21) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x400000) >> 22) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x800000) >> 23) << 24); +} + +static void +Slot_f4_Format_f4_s2_mul_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x10) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x2) | ((insn[1] & 0x1) << 1); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[1] & 0x6000) >> 13) << 2); + slotbuf[0] = (slotbuf[0] & ~0x1f0) | (((insn[2] & 0x7c0) >> 6) << 4); + slotbuf[0] = (slotbuf[0] & ~0x3e00) | (((insn[1] & 0xf800000) >> 23) << 9); + slotbuf[0] = (slotbuf[0] & ~0x7c000) | (((insn[1] & 0x7c0000) >> 18) << 14); + slotbuf[0] = (slotbuf[0] & ~0xf80000) | (((insn[2] & 0xf800) >> 11) << 19); + slotbuf[0] = (slotbuf[0] & ~0x3000000) | (((insn[1] & 0x18000) >> 15) << 24); + slotbuf[0] = (slotbuf[0] & ~0x3c000000) | (((insn[3] & 0xf000) >> 12) << 26); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x4000000) >> 26) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x8000000) >> 27) << 31); + slotbuf[1] = ((insn[3] & 0x10000000) >> 28); +} + +static void +Slot_f4_Format_f4_s2_mul_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x10) | ((slotbuf[0] & 0x1) << 4); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x2) >> 1); + insn[1] = (insn[1] & ~0x6000) | (((slotbuf[0] & 0xc) >> 2) << 13); + insn[2] = (insn[2] & ~0x7c0) | (((slotbuf[0] & 0x1f0) >> 4) << 6); + insn[1] = (insn[1] & ~0xf800000) | (((slotbuf[0] & 0x3e00) >> 9) << 23); + insn[1] = (insn[1] & ~0x7c0000) | (((slotbuf[0] & 0x7c000) >> 14) << 18); + insn[2] = (insn[2] & ~0xf800) | (((slotbuf[0] & 0xf80000) >> 19) << 11); + insn[1] = (insn[1] & ~0x18000) | (((slotbuf[0] & 0x3000000) >> 24) << 15); + insn[3] = (insn[3] & ~0xf000) | (((slotbuf[0] & 0x3c000000) >> 26) << 12); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x40000000) >> 30) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x80000000) >> 31) << 27); + insn[3] = (insn[3] & ~0x10000000) | ((slotbuf[1] & 0x1) << 28); +} + +static void +Slot_f4_Format_f4_s3_alu_34_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1fc) >> 2); + slotbuf[0] = (slotbuf[0] & ~0x180) | (((insn[1] & 0x1800) >> 11) << 7); + slotbuf[0] = (slotbuf[0] & ~0x1e00) | (((insn[1] & 0xf0000000) >> 28) << 9); + slotbuf[0] = (slotbuf[0] & ~0x2000) | ((insn[2] & 0x1) << 13); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[2] & 0x1000000) >> 24) << 14); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[2] & 0x3e) >> 1) << 15); + slotbuf[0] = (slotbuf[0] & ~0xff00000) | (((insn[2] & 0xff0000) >> 16) << 20); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x10000) >> 16) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x20000000) >> 29) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x40000000) >> 30) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x80000000) >> 31) << 31); +} + +static void +Slot_f4_Format_f4_s3_alu_34_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1fc) | ((slotbuf[0] & 0x7f) << 2); + insn[1] = (insn[1] & ~0x1800) | (((slotbuf[0] & 0x180) >> 7) << 11); + insn[1] = (insn[1] & ~0xf0000000) | (((slotbuf[0] & 0x1e00) >> 9) << 28); + insn[2] = (insn[2] & ~0x1) | ((slotbuf[0] & 0x2000) >> 13); + insn[2] = (insn[2] & ~0x1000000) | (((slotbuf[0] & 0x4000) >> 14) << 24); + insn[2] = (insn[2] & ~0x3e) | (((slotbuf[0] & 0xf8000) >> 15) << 1); + insn[2] = (insn[2] & ~0xff0000) | (((slotbuf[0] & 0xff00000) >> 20) << 16); + insn[3] = (insn[3] & ~0x10000) | (((slotbuf[0] & 0x10000000) >> 28) << 16); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x20000000) >> 29) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x40000000) >> 30) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x80000000) >> 31) << 31); +} + +static void +Slot_f5_Format_f5_s0_base_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf000) >> 12); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf00) >> 8) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0x1e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7000) | ((insn[1] & 0x7) << 12); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[1] & 0x600) >> 9) << 15); + slotbuf[0] = (slotbuf[0] & ~0x7e0000) | (((insn[1] & 0x3f000) >> 12) << 17); + slotbuf[0] = (slotbuf[0] & ~0x7800000) | (((insn[1] & 0x780000) >> 19) << 23); + slotbuf[0] = (slotbuf[0] & ~0x18000000) | (((insn[1] & 0xc000000) >> 26) << 27); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[2] & 0x4000000) >> 26) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[2] & 0x8000000) >> 27) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[2] & 0x10000000) >> 28) << 31); + slotbuf[1] = ((insn[2] & 0x20000000) >> 29); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[2] & 0x40000000) >> 30) << 1); + slotbuf[1] = (slotbuf[1] & ~0x4) | (((insn[2] & 0x80000000) >> 31) << 2); + slotbuf[1] = (slotbuf[1] & ~0x8) | ((insn[3] & 0x1) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x2) >> 1) << 4); +} + +static void +Slot_f5_Format_f5_s0_base_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf000) | ((slotbuf[0] & 0xf) << 12); + insn[0] = (insn[0] & ~0xf00) | (((slotbuf[0] & 0xf0) >> 4) << 8); + insn[0] = (insn[0] & ~0x1e0000) | (((slotbuf[0] & 0xf00) >> 8) << 17); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x7000) >> 12); + insn[1] = (insn[1] & ~0x600) | (((slotbuf[0] & 0x18000) >> 15) << 9); + insn[1] = (insn[1] & ~0x3f000) | (((slotbuf[0] & 0x7e0000) >> 17) << 12); + insn[1] = (insn[1] & ~0x780000) | (((slotbuf[0] & 0x7800000) >> 23) << 19); + insn[1] = (insn[1] & ~0xc000000) | (((slotbuf[0] & 0x18000000) >> 27) << 26); + insn[2] = (insn[2] & ~0x4000000) | (((slotbuf[0] & 0x20000000) >> 29) << 26); + insn[2] = (insn[2] & ~0x8000000) | (((slotbuf[0] & 0x40000000) >> 30) << 27); + insn[2] = (insn[2] & ~0x10000000) | (((slotbuf[0] & 0x80000000) >> 31) << 28); + insn[2] = (insn[2] & ~0x20000000) | ((slotbuf[1] & 0x1) << 29); + insn[2] = (insn[2] & ~0x40000000) | (((slotbuf[1] & 0x2) >> 1) << 30); + insn[2] = (insn[2] & ~0x80000000) | (((slotbuf[1] & 0x4) >> 2) << 31); + insn[3] = (insn[3] & ~0x1) | ((slotbuf[1] & 0x8) >> 3); + insn[3] = (insn[3] & ~0x2) | (((slotbuf[1] & 0x10) >> 4) << 1); +} + +static void +Slot_f5_Format_f5_s1_base_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x3c00000) >> 22); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[0] & 0x10) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0x20) | (((insn[0] & 0x200000) >> 21) << 5); + slotbuf[0] = (slotbuf[0] & ~0xfc0) | (((insn[0] & 0xfc000000) >> 26) << 6); + slotbuf[0] = (slotbuf[0] & ~0xf000) | (((insn[1] & 0xf0000000) >> 28) << 12); + slotbuf[0] = (slotbuf[0] & ~0xf0000) | ((insn[2] & 0xf) << 16); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[3] & 0x4) >> 2) << 20); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x8) >> 3) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x10) >> 4) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x80) >> 7) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x100) >> 8) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x200) >> 9) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x400) >> 10) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x1000) >> 12) << 27); +} + +static void +Slot_f5_Format_f5_s1_base_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3c00000) | ((slotbuf[0] & 0xf) << 22); + insn[0] = (insn[0] & ~0x10) | (((slotbuf[0] & 0x10) >> 4) << 4); + insn[0] = (insn[0] & ~0x200000) | (((slotbuf[0] & 0x20) >> 5) << 21); + insn[0] = (insn[0] & ~0xfc000000) | (((slotbuf[0] & 0xfc0) >> 6) << 26); + insn[1] = (insn[1] & ~0xf0000000) | (((slotbuf[0] & 0xf000) >> 12) << 28); + insn[2] = (insn[2] & ~0xf) | ((slotbuf[0] & 0xf0000) >> 16); + insn[3] = (insn[3] & ~0x4) | (((slotbuf[0] & 0x100000) >> 20) << 2); + insn[3] = (insn[3] & ~0x8) | (((slotbuf[0] & 0x200000) >> 21) << 3); + insn[3] = (insn[3] & ~0x10) | (((slotbuf[0] & 0x400000) >> 22) << 4); + insn[3] = (insn[3] & ~0x80) | (((slotbuf[0] & 0x800000) >> 23) << 7); + insn[3] = (insn[3] & ~0x100) | (((slotbuf[0] & 0x1000000) >> 24) << 8); + insn[3] = (insn[3] & ~0x200) | (((slotbuf[0] & 0x2000000) >> 25) << 9); + insn[3] = (insn[3] & ~0x400) | (((slotbuf[0] & 0x4000000) >> 26) << 10); + insn[3] = (insn[3] & ~0x1000) | (((slotbuf[0] & 0x8000000) >> 27) << 12); +} + +static void +Slot_f5_Format_f5_s2_base_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x10000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0xe) | (((insn[0] & 0xe0) >> 5) << 1); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[1] & 0x40000) >> 18) << 4); + slotbuf[0] = (slotbuf[0] & ~0xe0) | (((insn[1] & 0x3800000) >> 23) << 5); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[2] & 0x180000) >> 19) << 8); + slotbuf[0] = (slotbuf[0] & ~0xc00) | (((insn[2] & 0x1800) >> 11) << 10); + slotbuf[0] = (slotbuf[0] & ~0x7f000) | (((insn[2] & 0x7f0) >> 4) << 12); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[3] & 0x2000) >> 13) << 19); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[3] & 0x4000) >> 14) << 20); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x8000) >> 15) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x10000) >> 16) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x80000) >> 19) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x100000) >> 20) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x200000) >> 21) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x400000) >> 22) << 26); +} + +static void +Slot_f5_Format_f5_s2_base_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x10000) | ((slotbuf[0] & 0x1) << 16); + insn[0] = (insn[0] & ~0xe0) | (((slotbuf[0] & 0xe) >> 1) << 5); + insn[1] = (insn[1] & ~0x40000) | (((slotbuf[0] & 0x10) >> 4) << 18); + insn[1] = (insn[1] & ~0x3800000) | (((slotbuf[0] & 0xe0) >> 5) << 23); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x300) >> 8) << 19); + insn[2] = (insn[2] & ~0x1800) | (((slotbuf[0] & 0xc00) >> 10) << 11); + insn[2] = (insn[2] & ~0x7f0) | (((slotbuf[0] & 0x7f000) >> 12) << 4); + insn[3] = (insn[3] & ~0x2000) | (((slotbuf[0] & 0x80000) >> 19) << 13); + insn[3] = (insn[3] & ~0x4000) | (((slotbuf[0] & 0x100000) >> 20) << 14); + insn[3] = (insn[3] & ~0x8000) | (((slotbuf[0] & 0x200000) >> 21) << 15); + insn[3] = (insn[3] & ~0x10000) | (((slotbuf[0] & 0x400000) >> 22) << 16); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x800000) >> 23) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x1000000) >> 24) << 20); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x2000000) >> 25) << 21); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x4000000) >> 26) << 22); +} + +static void +Slot_f5_Format_f5_s3_base_35_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0x400000) >> 22); + slotbuf[0] = (slotbuf[0] & ~0x7e) | (((insn[1] & 0x1f8) >> 3) << 1); + slotbuf[0] = (slotbuf[0] & ~0x80) | (((insn[1] & 0x800) >> 11) << 7); + slotbuf[0] = (slotbuf[0] & ~0x3f00) | (((insn[2] & 0x7e000) >> 13) << 8); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[2] & 0x200000) >> 21) << 14); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x3800000) >> 23) << 15); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[3] & 0x800000) >> 23) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[3] & 0x1000000) >> 24) << 19); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[3] & 0x4000000) >> 26) << 20); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x8000000) >> 27) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x10000000) >> 28) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x20000000) >> 29) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x40000000) >> 30) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x80000000) >> 31) << 25); +} + +static void +Slot_f5_Format_f5_s3_base_35_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0x400000) | ((slotbuf[0] & 0x1) << 22); + insn[1] = (insn[1] & ~0x1f8) | (((slotbuf[0] & 0x7e) >> 1) << 3); + insn[1] = (insn[1] & ~0x800) | (((slotbuf[0] & 0x80) >> 7) << 11); + insn[2] = (insn[2] & ~0x7e000) | (((slotbuf[0] & 0x3f00) >> 8) << 13); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[0] & 0x4000) >> 14) << 21); + insn[2] = (insn[2] & ~0x3800000) | (((slotbuf[0] & 0x38000) >> 15) << 23); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x40000) >> 18) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x80000) >> 19) << 24); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x100000) >> 20) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x200000) >> 21) << 27); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x400000) >> 22) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x800000) >> 23) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x1000000) >> 24) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x2000000) >> 25) << 31); +} + +static void +Slot_f11_Format_f11_s0_ld_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf000) >> 12); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf00) >> 8) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0x1e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0xf000) | ((insn[2] & 0xf) << 12); + slotbuf[0] = (slotbuf[0] & ~0xf0000) | (((insn[2] & 0x7800000) >> 23) << 16); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[2] & 0x40000000) >> 30) << 20); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x80000) >> 19) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x100000) >> 20) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x200000) >> 21) << 23); +} + +static void +Slot_f11_Format_f11_s0_ld_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf000) | ((slotbuf[0] & 0xf) << 12); + insn[0] = (insn[0] & ~0xf00) | (((slotbuf[0] & 0xf0) >> 4) << 8); + insn[0] = (insn[0] & ~0x1e0000) | (((slotbuf[0] & 0xf00) >> 8) << 17); + insn[2] = (insn[2] & ~0xf) | ((slotbuf[0] & 0xf000) >> 12); + insn[2] = (insn[2] & ~0x7800000) | (((slotbuf[0] & 0xf0000) >> 16) << 23); + insn[2] = (insn[2] & ~0x40000000) | (((slotbuf[0] & 0x100000) >> 20) << 30); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x200000) >> 21) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x400000) >> 22) << 20); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x800000) >> 23) << 21); +} + +static void +Slot_f11_Format_f11_s1_alu_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xe0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x8) | (((insn[0] & 0x10000) >> 16) << 3); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0x3c00000) >> 22) << 4); + slotbuf[0] = (slotbuf[0] & ~0x100) | (((insn[0] & 0x200000) >> 21) << 8); + slotbuf[0] = (slotbuf[0] & ~0x200) | (((insn[1] & 0x2) >> 1) << 9); + slotbuf[0] = (slotbuf[0] & ~0xc00) | (((insn[1] & 0x600) >> 9) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x8000000) >> 27) << 12); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x4) >> 2) << 13); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[1] & 0x20000) >> 17) << 14); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[1] & 0x4000000) >> 26) << 15); + slotbuf[0] = (slotbuf[0] & ~0x10000) | (((insn[0] & 0x4000000) >> 26) << 16); + slotbuf[0] = (slotbuf[0] & ~0x20000) | (((insn[0] & 0x80000000) >> 31) << 17); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x80000000) >> 31) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | ((insn[3] & 0x1) << 19); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[3] & 0x400000) >> 22) << 20); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x800000) >> 23) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x1000000) >> 24) << 22); +} + +static void +Slot_f11_Format_f11_s1_alu_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xe0) | ((slotbuf[0] & 0x7) << 5); + insn[0] = (insn[0] & ~0x10000) | (((slotbuf[0] & 0x8) >> 3) << 16); + insn[0] = (insn[0] & ~0x3c00000) | (((slotbuf[0] & 0xf0) >> 4) << 22); + insn[0] = (insn[0] & ~0x200000) | (((slotbuf[0] & 0x100) >> 8) << 21); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x200) >> 9) << 1); + insn[1] = (insn[1] & ~0x600) | (((slotbuf[0] & 0xc00) >> 10) << 9); + insn[1] = (insn[1] & ~0x8000000) | (((slotbuf[0] & 0x1000) >> 12) << 27); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[0] & 0x2000) >> 13) << 2); + insn[1] = (insn[1] & ~0x20000) | (((slotbuf[0] & 0x4000) >> 14) << 17); + insn[1] = (insn[1] & ~0x4000000) | (((slotbuf[0] & 0x8000) >> 15) << 26); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x10000) >> 16) << 26); + insn[0] = (insn[0] & ~0x80000000) | (((slotbuf[0] & 0x20000) >> 17) << 31); + insn[2] = (insn[2] & ~0x80000000) | (((slotbuf[0] & 0x40000) >> 18) << 31); + insn[3] = (insn[3] & ~0x1) | ((slotbuf[0] & 0x80000) >> 19); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x100000) >> 20) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x200000) >> 21) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x400000) >> 22) << 24); +} + +static void +Slot_f11_Format_f11_s2_mul_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x10) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x2) | ((insn[1] & 0x1) << 1); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[1] & 0x6000) >> 13) << 2); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0x78000000) >> 27) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[1] & 0x780000) >> 19) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x40000) >> 18) << 12); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x800000) >> 23) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc000) | (((insn[1] & 0x18000) >> 15) << 14); + slotbuf[0] = (slotbuf[0] & ~0x1f0000) | (((insn[3] & 0x3e) >> 1) << 16); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x4000000) >> 26) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x8000000) >> 27) << 22); +} + +static void +Slot_f11_Format_f11_s2_mul_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x10) | ((slotbuf[0] & 0x1) << 4); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x2) >> 1); + insn[1] = (insn[1] & ~0x6000) | (((slotbuf[0] & 0xc) >> 2) << 13); + insn[0] = (insn[0] & ~0x78000000) | (((slotbuf[0] & 0xf0) >> 4) << 27); + insn[1] = (insn[1] & ~0x780000) | (((slotbuf[0] & 0xf00) >> 8) << 19); + insn[1] = (insn[1] & ~0x40000) | (((slotbuf[0] & 0x1000) >> 12) << 18); + insn[1] = (insn[1] & ~0x800000) | (((slotbuf[0] & 0x2000) >> 13) << 23); + insn[1] = (insn[1] & ~0x18000) | (((slotbuf[0] & 0xc000) >> 14) << 15); + insn[3] = (insn[3] & ~0x3e) | (((slotbuf[0] & 0x1f0000) >> 16) << 1); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x200000) >> 21) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x400000) >> 22) << 27); +} + +static void +Slot_f11_Format_f11_s3_alu_35_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0x400000) >> 22); + slotbuf[0] = (slotbuf[0] & ~0x7e) | (((insn[1] & 0x1f8) >> 3) << 1); + slotbuf[0] = (slotbuf[0] & ~0x180) | (((insn[1] & 0x1800) >> 11) << 7); + slotbuf[0] = (slotbuf[0] & ~0x200) | (((insn[1] & 0x10000000) >> 28) << 9); + slotbuf[0] = (slotbuf[0] & ~0x1c00) | (((insn[2] & 0x1c0) >> 6) << 10); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[2] & 0x30) >> 4) << 13); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[1] & 0x60000000) >> 29) << 15); + slotbuf[0] = (slotbuf[0] & ~0x20000) | (((insn[2] & 0x200000) >> 21) << 17); + slotbuf[0] = (slotbuf[0] & ~0xfc0000) | (((insn[3] & 0xfc0) >> 6) << 18); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x10000000) >> 28) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x20000000) >> 29) << 25); +} + +static void +Slot_f11_Format_f11_s3_alu_35_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0x400000) | ((slotbuf[0] & 0x1) << 22); + insn[1] = (insn[1] & ~0x1f8) | (((slotbuf[0] & 0x7e) >> 1) << 3); + insn[1] = (insn[1] & ~0x1800) | (((slotbuf[0] & 0x180) >> 7) << 11); + insn[1] = (insn[1] & ~0x10000000) | (((slotbuf[0] & 0x200) >> 9) << 28); + insn[2] = (insn[2] & ~0x1c0) | (((slotbuf[0] & 0x1c00) >> 10) << 6); + insn[2] = (insn[2] & ~0x30) | (((slotbuf[0] & 0x6000) >> 13) << 4); + insn[1] = (insn[1] & ~0x60000000) | (((slotbuf[0] & 0x18000) >> 15) << 29); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[0] & 0x20000) >> 17) << 21); + insn[3] = (insn[3] & ~0xfc0) | (((slotbuf[0] & 0xfc0000) >> 18) << 6); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x1000000) >> 24) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x2000000) >> 25) << 29); +} + +static void +Slot_f11_Format_f11_s4_alu_56_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x3000000) >> 24); + slotbuf[0] = (slotbuf[0] & ~0x4) | (((insn[1] & 0x80000000) >> 31) << 2); + slotbuf[0] = (slotbuf[0] & ~0x7ff8) | (((insn[2] & 0x1ffe00) >> 9) << 3); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x38000000) >> 27) << 15); + slotbuf[0] = (slotbuf[0] & ~0x7c0000) | (((insn[3] & 0x1f000) >> 12) << 18); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x40000000) >> 30) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x80000000) >> 31) << 24); +} + +static void +Slot_f11_Format_f11_s4_alu_56_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x3000000) | ((slotbuf[0] & 0x3) << 24); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x4) >> 2) << 31); + insn[2] = (insn[2] & ~0x1ffe00) | (((slotbuf[0] & 0x7ff8) >> 3) << 9); + insn[2] = (insn[2] & ~0x38000000) | (((slotbuf[0] & 0x38000) >> 15) << 27); + insn[3] = (insn[3] & ~0x1f000) | (((slotbuf[0] & 0x7c0000) >> 18) << 12); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x800000) >> 23) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x1000000) >> 24) << 31); +} + +static void +Slot_n1_Format_n1_s0_ldst_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[0] & 0x3e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0x6000) | ((insn[1] & 0x3) << 13); + slotbuf[0] = (slotbuf[0] & ~0xff8000) | (((insn[1] & 0x3fe00) >> 9) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[1] & 0x1000000) >> 24) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[1] & 0x2000000) >> 25) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[1] & 0x4000000) >> 26) << 26); +} + +static void +Slot_n1_Format_n1_s0_ldst_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0x3e0000) | (((slotbuf[0] & 0x1f00) >> 8) << 17); + insn[1] = (insn[1] & ~0x3) | ((slotbuf[0] & 0x6000) >> 13); + insn[1] = (insn[1] & ~0x3fe00) | (((slotbuf[0] & 0xff8000) >> 15) << 9); + insn[1] = (insn[1] & ~0x1000000) | (((slotbuf[0] & 0x1000000) >> 24) << 24); + insn[1] = (insn[1] & ~0x2000000) | (((slotbuf[0] & 0x2000000) >> 25) << 25); + insn[1] = (insn[1] & ~0x4000000) | (((slotbuf[0] & 0x4000000) >> 26) << 26); +} + +static void +Slot_n1_Format_n1_s1_none_50_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x40000) >> 18); + slotbuf[0] = (slotbuf[0] & ~0x2) | (((insn[1] & 0x8000000) >> 27) << 1); + slotbuf[0] = (slotbuf[0] & ~0x4) | (((insn[1] & 0x10000000) >> 28) << 2); + slotbuf[0] = (slotbuf[0] & ~0x8) | (((insn[1] & 0x20000000) >> 29) << 3); +} + +static void +Slot_n1_Format_n1_s1_none_50_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x40000) | ((slotbuf[0] & 0x1) << 18); + insn[1] = (insn[1] & ~0x8000000) | (((slotbuf[0] & 0x2) >> 1) << 27); + insn[1] = (insn[1] & ~0x10000000) | (((slotbuf[0] & 0x4) >> 2) << 28); + insn[1] = (insn[1] & ~0x20000000) | (((slotbuf[0] & 0x8) >> 3) << 29); +} + +static void +Slot_n1_Format_n1_s2_mul_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x10000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0xe) | (((insn[0] & 0xe0) >> 5) << 1); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0x78000000) >> 27) << 4); + slotbuf[0] = (slotbuf[0] & ~0x3f00) | (((insn[1] & 0x1f8) >> 3) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7c000) | (((insn[0] & 0x7c00000) >> 22) << 14); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[0] & 0x80000000) >> 31) << 19); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[1] & 0x4) >> 2) << 20); + slotbuf[0] = (slotbuf[0] & ~0xe00000) | (((insn[1] & 0x380000) >> 19) << 21); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[1] & 0x40000000) >> 30) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[1] & 0x80000000) >> 31) << 25); +} + +static void +Slot_n1_Format_n1_s2_mul_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x10000) | ((slotbuf[0] & 0x1) << 16); + insn[0] = (insn[0] & ~0xe0) | (((slotbuf[0] & 0xe) >> 1) << 5); + insn[0] = (insn[0] & ~0x78000000) | (((slotbuf[0] & 0xf0) >> 4) << 27); + insn[1] = (insn[1] & ~0x1f8) | (((slotbuf[0] & 0x3f00) >> 8) << 3); + insn[0] = (insn[0] & ~0x7c00000) | (((slotbuf[0] & 0x7c000) >> 14) << 22); + insn[0] = (insn[0] & ~0x80000000) | (((slotbuf[0] & 0x80000) >> 19) << 31); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[0] & 0x100000) >> 20) << 2); + insn[1] = (insn[1] & ~0x380000) | (((slotbuf[0] & 0xe00000) >> 21) << 19); + insn[1] = (insn[1] & ~0x40000000) | (((slotbuf[0] & 0x1000000) >> 24) << 30); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x2000000) >> 25) << 31); +} + +static void +Slot_n2_Format_n2_s0_ldst_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[0] & 0x3e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0x6000) | ((insn[1] & 0x3) << 13); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[1] & 0x600) >> 9) << 15); + slotbuf[0] = (slotbuf[0] & ~0x7e0000) | (((insn[1] & 0x1f8) >> 3) << 17); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[1] & 0x800) >> 11) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[1] & 0x40000) >> 18) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[1] & 0x80000) >> 19) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[1] & 0x100000) >> 20) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[1] & 0x200000) >> 21) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[1] & 0x1000000) >> 24) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[1] & 0x2000000) >> 25) << 29); +} + +static void +Slot_n2_Format_n2_s0_ldst_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0x3e0000) | (((slotbuf[0] & 0x1f00) >> 8) << 17); + insn[1] = (insn[1] & ~0x3) | ((slotbuf[0] & 0x6000) >> 13); + insn[1] = (insn[1] & ~0x600) | (((slotbuf[0] & 0x18000) >> 15) << 9); + insn[1] = (insn[1] & ~0x1f8) | (((slotbuf[0] & 0x7e0000) >> 17) << 3); + insn[1] = (insn[1] & ~0x800) | (((slotbuf[0] & 0x800000) >> 23) << 11); + insn[1] = (insn[1] & ~0x40000) | (((slotbuf[0] & 0x1000000) >> 24) << 18); + insn[1] = (insn[1] & ~0x80000) | (((slotbuf[0] & 0x2000000) >> 25) << 19); + insn[1] = (insn[1] & ~0x100000) | (((slotbuf[0] & 0x4000000) >> 26) << 20); + insn[1] = (insn[1] & ~0x200000) | (((slotbuf[0] & 0x8000000) >> 27) << 21); + insn[1] = (insn[1] & ~0x1000000) | (((slotbuf[0] & 0x10000000) >> 28) << 24); + insn[1] = (insn[1] & ~0x2000000) | (((slotbuf[0] & 0x20000000) >> 29) << 25); +} + +static void +Slot_n2_Format_n2_s1_ld_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xe0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x8) | (((insn[0] & 0x10000) >> 16) << 3); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0x3c00000) >> 22) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf0000000) >> 28) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x4) >> 2) << 12); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[0] & 0xc000000) >> 26) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1f8000) | (((insn[1] & 0x3f000) >> 12) << 15); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[1] & 0x4000000) >> 26) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[1] & 0x8000000) >> 27) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[1] & 0x10000000) >> 28) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[1] & 0x20000000) >> 29) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[1] & 0x40000000) >> 30) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[1] & 0x80000000) >> 31) << 26); +} + +static void +Slot_n2_Format_n2_s1_ld_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xe0) | ((slotbuf[0] & 0x7) << 5); + insn[0] = (insn[0] & ~0x10000) | (((slotbuf[0] & 0x8) >> 3) << 16); + insn[0] = (insn[0] & ~0x3c00000) | (((slotbuf[0] & 0xf0) >> 4) << 22); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf00) >> 8) << 28); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[0] & 0x1000) >> 12) << 2); + insn[0] = (insn[0] & ~0xc000000) | (((slotbuf[0] & 0x6000) >> 13) << 26); + insn[1] = (insn[1] & ~0x3f000) | (((slotbuf[0] & 0x1f8000) >> 15) << 12); + insn[1] = (insn[1] & ~0x4000000) | (((slotbuf[0] & 0x200000) >> 21) << 26); + insn[1] = (insn[1] & ~0x8000000) | (((slotbuf[0] & 0x400000) >> 22) << 27); + insn[1] = (insn[1] & ~0x10000000) | (((slotbuf[0] & 0x800000) >> 23) << 28); + insn[1] = (insn[1] & ~0x20000000) | (((slotbuf[0] & 0x1000000) >> 24) << 29); + insn[1] = (insn[1] & ~0x40000000) | (((slotbuf[0] & 0x2000000) >> 25) << 30); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x4000000) >> 26) << 31); +} + +static void +Slot_n0_Format_n0_s0_ldst_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[0] & 0x3e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0x6000) | ((insn[1] & 0x3) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1f8000) | (((insn[1] & 0x1f800) >> 11) << 15); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[1] & 0x1000000) >> 24) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[1] & 0x2000000) >> 25) << 22); +} + +static void +Slot_n0_Format_n0_s0_ldst_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0x3e0000) | (((slotbuf[0] & 0x1f00) >> 8) << 17); + insn[1] = (insn[1] & ~0x3) | ((slotbuf[0] & 0x6000) >> 13); + insn[1] = (insn[1] & ~0x1f800) | (((slotbuf[0] & 0x1f8000) >> 15) << 11); + insn[1] = (insn[1] & ~0x1000000) | (((slotbuf[0] & 0x200000) >> 21) << 24); + insn[1] = (insn[1] & ~0x2000000) | (((slotbuf[0] & 0x400000) >> 22) << 25); +} + +static void +Slot_n0_Format_n0_s1_none_49_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x20000) >> 17); + slotbuf[0] = (slotbuf[0] & ~0x2) | (((insn[1] & 0x4000000) >> 26) << 1); + slotbuf[0] = (slotbuf[0] & ~0x4) | (((insn[1] & 0x8000000) >> 27) << 2); +} + +static void +Slot_n0_Format_n0_s1_none_49_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x20000) | ((slotbuf[0] & 0x1) << 17); + insn[1] = (insn[1] & ~0x4000000) | (((slotbuf[0] & 0x2) >> 1) << 26); + insn[1] = (insn[1] & ~0x8000000) | (((slotbuf[0] & 0x4) >> 2) << 27); +} + +static void +Slot_n0_Format_n0_s2_none_50_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x40000) >> 18); + slotbuf[0] = (slotbuf[0] & ~0x2) | (((insn[1] & 0x10000000) >> 28) << 1); + slotbuf[0] = (slotbuf[0] & ~0x4) | (((insn[1] & 0x20000000) >> 29) << 2); +} + +static void +Slot_n0_Format_n0_s2_none_50_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x40000) | ((slotbuf[0] & 0x1) << 18); + insn[1] = (insn[1] & ~0x10000000) | (((slotbuf[0] & 0x2) >> 1) << 28); + insn[1] = (insn[1] & ~0x20000000) | (((slotbuf[0] & 0x4) >> 2) << 29); +} + +static void +Slot_n0_Format_n0_s3_alu_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x10000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0xe) | (((insn[0] & 0xe0) >> 5) << 1); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[1] & 0x3c) >> 2) << 4); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[0] & 0x18000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x7c00000) >> 22) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[1] & 0x7c0) >> 6) << 15); + slotbuf[0] = (slotbuf[0] & ~0x700000) | (((insn[0] & 0xe0000000) >> 29) << 20); + slotbuf[0] = (slotbuf[0] & ~0x3800000) | (((insn[1] & 0x380000) >> 19) << 23); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[1] & 0x40000000) >> 30) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[1] & 0x80000000) >> 31) << 27); +} + +static void +Slot_n0_Format_n0_s3_alu_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x10000) | ((slotbuf[0] & 0x1) << 16); + insn[0] = (insn[0] & ~0xe0) | (((slotbuf[0] & 0xe) >> 1) << 5); + insn[1] = (insn[1] & ~0x3c) | (((slotbuf[0] & 0xf0) >> 4) << 2); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x300) >> 8) << 27); + insn[0] = (insn[0] & ~0x7c00000) | (((slotbuf[0] & 0x7c00) >> 10) << 22); + insn[1] = (insn[1] & ~0x7c0) | (((slotbuf[0] & 0xf8000) >> 15) << 6); + insn[0] = (insn[0] & ~0xe0000000) | (((slotbuf[0] & 0x700000) >> 20) << 29); + insn[1] = (insn[1] & ~0x380000) | (((slotbuf[0] & 0x3800000) >> 23) << 19); + insn[1] = (insn[1] & ~0x40000000) | (((slotbuf[0] & 0x4000000) >> 26) << 30); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x8000000) >> 27) << 31); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst_get, + Field_s2_Slot_inst_get, + Field_r2_Slot_inst_get, + Field_t4_Slot_inst_get, + Field_s4_Slot_inst_get, + Field_r4_Slot_inst_get, + Field_t8_Slot_inst_get, + Field_s8_Slot_inst_get, + Field_r8_Slot_inst_get, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wbr18_imm_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 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+ 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_iq_tie2apb_inq0_pop_qdata_Slot_inst_get, + Field_fld_iq_tie2apb_inq0_is_ready_is_ready_Slot_inst_get, + Field_fld_inst_11_8_Slot_inst_get, + Field_fld_iq_tie2apb_inq0_nonblocking_peek_success_Slot_inst_get, + Field_fld_iq_tie2apb_inq0_nonblocking_peek_qdata_Slot_inst_get, + Field_fld_iq_tie2apb_inq0_nonblocking_pop_success_Slot_inst_get, + Field_fld_iq_tie2apb_inq0_nonblocking_pop_qdata_Slot_inst_get, + Field_fld_inst_23_8_Slot_inst_get, + Field_fld_iq_tie2apb_inq0_blocking_peek_qdata_Slot_inst_get, + Field_fld_inst_23_12_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_push_read_qaddr_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_push_read_qdata_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_push_write_qaddr_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_push_write_qdata_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_is_ready_is_ready_Slot_inst_get, + Field_fld_inst_3_0_Slot_inst_get, + Field_fld_inst_23_16_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_nonblocking_push_read_success_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_nonblocking_push_read_qaddr_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_nonblocking_push_read_qdata_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_nonblocking_push_write_success_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_nonblocking_push_write_qaddr_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_nonblocking_push_write_qdata_Slot_inst_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst_set, + Field_s2_Slot_inst_set, + Field_r2_Slot_inst_set, + Field_t4_Slot_inst_set, + Field_s4_Slot_inst_set, + Field_r4_Slot_inst_set, + Field_t8_Slot_inst_set, + Field_s8_Slot_inst_set, + Field_r8_Slot_inst_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wbr18_imm_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_iq_tie2apb_inq0_pop_qdata_Slot_inst_set, + Field_fld_iq_tie2apb_inq0_is_ready_is_ready_Slot_inst_set, + Field_fld_inst_11_8_Slot_inst_set, + Field_fld_iq_tie2apb_inq0_nonblocking_peek_success_Slot_inst_set, + Field_fld_iq_tie2apb_inq0_nonblocking_peek_qdata_Slot_inst_set, + Field_fld_iq_tie2apb_inq0_nonblocking_pop_success_Slot_inst_set, + Field_fld_iq_tie2apb_inq0_nonblocking_pop_qdata_Slot_inst_set, + Field_fld_inst_23_8_Slot_inst_set, + Field_fld_iq_tie2apb_inq0_blocking_peek_qdata_Slot_inst_set, + Field_fld_inst_23_12_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_push_read_qaddr_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_push_read_qdata_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_push_write_qaddr_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_push_write_qdata_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_is_ready_is_ready_Slot_inst_set, + Field_fld_inst_3_0_Slot_inst_set, + Field_fld_inst_23_16_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_nonblocking_push_read_success_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_nonblocking_push_read_qaddr_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_nonblocking_push_read_qdata_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_nonblocking_push_write_success_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_nonblocking_push_write_qaddr_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_nonblocking_push_write_qdata_Slot_inst_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_get, + Field_st_Slot_inst16a_get, + 0, + Field_imm4_Slot_inst16a_get, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + Field_imm6_Slot_inst16a_get, + Field_imm7_Slot_inst16a_get, + Field_t2_Slot_inst16a_get, + Field_s2_Slot_inst16a_get, + Field_r2_Slot_inst16a_get, + Field_t4_Slot_inst16a_get, + Field_s4_Slot_inst16a_get, + Field_r4_Slot_inst16a_get, + Field_t8_Slot_inst16a_get, + Field_s8_Slot_inst16a_get, + Field_r8_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 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+ 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_set, + Field_st_Slot_inst16a_set, + 0, + Field_imm4_Slot_inst16a_set, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + Field_imm6_Slot_inst16a_set, + Field_imm7_Slot_inst16a_set, + Field_t2_Slot_inst16a_set, + Field_s2_Slot_inst16a_set, + Field_r2_Slot_inst16a_set, + Field_t4_Slot_inst16a_set, + Field_s4_Slot_inst16a_set, + Field_r4_Slot_inst16a_set, + Field_t8_Slot_inst16a_set, + Field_s8_Slot_inst16a_set, + Field_r8_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 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+ 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_get, + Field_st_Slot_inst16b_get, + 0, + Field_imm4_Slot_inst16b_get, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + Field_t2_Slot_inst16b_get, + Field_s2_Slot_inst16b_get, + Field_r2_Slot_inst16b_get, + Field_t4_Slot_inst16b_get, + Field_s4_Slot_inst16b_get, + Field_r4_Slot_inst16b_get, + Field_t8_Slot_inst16b_get, + Field_s8_Slot_inst16b_get, + Field_r8_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 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+ 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_set, + Field_st_Slot_inst16b_set, + 0, + Field_imm4_Slot_inst16b_set, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + Field_t2_Slot_inst16b_set, + Field_s2_Slot_inst16b_set, + Field_r2_Slot_inst16b_set, + Field_t4_Slot_inst16b_set, + Field_s4_Slot_inst16b_set, + Field_r4_Slot_inst16b_set, + Field_t8_Slot_inst16b_set, + Field_s8_Slot_inst16b_set, + Field_r8_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f0_s0_ldst_get_field_fns[] = { + Field_t_Slot_f0_s0_ldst_get, + 0, + Field_bbi_Slot_f0_s0_ldst_get, + 0, + Field_imm8_Slot_f0_s0_ldst_get, + Field_s_Slot_f0_s0_ldst_get, + Field_imm12b_Slot_f0_s0_ldst_get, + Field_imm16_Slot_f0_s0_ldst_get, + 0, + 0, + Field_offset_Slot_f0_s0_ldst_get, + 0, + 0, + Field_op2_Slot_f0_s0_ldst_get, + Field_r_Slot_f0_s0_ldst_get, + 0, + 0, + Field_sae_Slot_f0_s0_ldst_get, + Field_sal_Slot_f0_s0_ldst_get, + Field_sargt_Slot_f0_s0_ldst_get, + 0, + Field_sas_Slot_f0_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_f0_s0_ldst_get, + 0, + Field_fld_f0_s0_ldst_11_4_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_11_9_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_12_0_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_12_11_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_12_2_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_12_4_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_12_8_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_13_9_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_15_15_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_11_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_19_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_20_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_3_0_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_7_5_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_7_6_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_7_7_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_8_0_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_8_4_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_8_8_Slot_f0_s0_ldst_get, + Field_fld_bbe_shflimm_s0_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uus_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_valignr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vbre_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vrr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vrul_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_arr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_shift_vr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f0_s0_ldst_get, + Field_fld_saimm4_Slot_f0_s0_ldst_get, + Field_fld_saimm5_Slot_f0_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f0_s0_ldst_set_field_fns[] = { + Field_t_Slot_f0_s0_ldst_set, + 0, + Field_bbi_Slot_f0_s0_ldst_set, + 0, + Field_imm8_Slot_f0_s0_ldst_set, + Field_s_Slot_f0_s0_ldst_set, + Field_imm12b_Slot_f0_s0_ldst_set, + Field_imm16_Slot_f0_s0_ldst_set, + 0, + 0, + Field_offset_Slot_f0_s0_ldst_set, + 0, + 0, + Field_op2_Slot_f0_s0_ldst_set, + Field_r_Slot_f0_s0_ldst_set, + 0, + 0, + Field_sae_Slot_f0_s0_ldst_set, + Field_sal_Slot_f0_s0_ldst_set, + Field_sargt_Slot_f0_s0_ldst_set, + 0, + Field_sas_Slot_f0_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_f0_s0_ldst_set, + 0, + Field_fld_f0_s0_ldst_11_4_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_11_9_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_12_0_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_12_11_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_12_2_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_12_4_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_12_8_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_13_9_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_15_15_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_11_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_19_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_20_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_3_0_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_7_5_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_7_6_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_7_7_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_8_0_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_8_4_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_8_8_Slot_f0_s0_ldst_set, + Field_fld_bbe_shflimm_s0_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uus_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_valignr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vbre_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vrr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vrul_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_arr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_shift_vr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f0_s0_ldst_set, + Field_fld_saimm4_Slot_f0_s0_ldst_set, + Field_fld_saimm5_Slot_f0_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f0_s1_ld_get_field_fns[] = { + Field_t_Slot_f0_s1_ld_get, + 0, + 0, + 0, + Field_imm8_Slot_f0_s1_ld_get, + Field_s_Slot_f0_s1_ld_get, + Field_imm12b_Slot_f0_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f0_s1_ld_get, + Field_r_Slot_f0_s1_ld_get, + 0, + 0, + Field_sae_Slot_f0_s1_ld_get, + Field_sal_Slot_f0_s1_ld_get, + Field_sargt_Slot_f0_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f0_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f0_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f0_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f0_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f0_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f0_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f0_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f0_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_f0_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_15_10_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_15_14_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_15_15_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_15_2_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_15_4_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_15_8_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_24_0_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_24_11_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_24_14_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_24_17_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_24_8_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_7_5_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_7_6_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_7_7_Slot_f0_s1_ld_get, + Field_fld_bbe_ltrx2nimm_Slot_f0_s1_ld_get, + Field_fld_bbe_ltrxn_2imm_Slot_f0_s1_ld_get, + Field_fld_bbe_ltrxnimm_Slot_f0_s1_ld_get, + Field_fld_imm1_2n_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_sqz_vbr_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_sqz_vt_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vec_mov_arr_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vec_mov_vbr_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vec_mov_vt_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f0_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f0_s1_ld_set_field_fns[] = { + Field_t_Slot_f0_s1_ld_set, + 0, + 0, + 0, + Field_imm8_Slot_f0_s1_ld_set, + Field_s_Slot_f0_s1_ld_set, + Field_imm12b_Slot_f0_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f0_s1_ld_set, + Field_r_Slot_f0_s1_ld_set, + 0, + 0, + Field_sae_Slot_f0_s1_ld_set, + Field_sal_Slot_f0_s1_ld_set, + Field_sargt_Slot_f0_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f0_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f0_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f0_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f0_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f0_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f0_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f0_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f0_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_f0_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_15_10_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_15_14_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_15_15_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_15_2_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_15_4_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_15_8_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_24_0_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_24_11_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_24_14_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_24_17_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_24_8_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_7_5_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_7_6_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_7_7_Slot_f0_s1_ld_set, + Field_fld_bbe_ltrx2nimm_Slot_f0_s1_ld_set, + Field_fld_bbe_ltrxn_2imm_Slot_f0_s1_ld_set, + Field_fld_bbe_ltrxnimm_Slot_f0_s1_ld_set, + Field_fld_imm1_2n_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_sqz_vbr_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_sqz_vt_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vec_mov_arr_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vec_mov_vbr_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vec_mov_vt_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f0_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f0_s2_mul_get_field_fns[] = { + Field_t_Slot_f0_s2_mul_get, + 0, + 0, + 0, + Field_imm8_Slot_f0_s2_mul_get, + Field_s_Slot_f0_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f0_s2_mul_get, + 0, + 0, + 0, + Field_sal_Slot_f0_s2_mul_get, + Field_sargt_Slot_f0_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f0_s2_mul_11_8_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_13_12_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_18_9_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_1_0_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_26_13_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_26_2_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_26_20_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_4_4_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_7_4_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_multiply_arr_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_multiply_vp_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_multiply_vr_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_multiply_vs_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_multiply_wvt_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f0_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f0_s2_mul_set_field_fns[] = { + Field_t_Slot_f0_s2_mul_set, + 0, + 0, + 0, + Field_imm8_Slot_f0_s2_mul_set, + Field_s_Slot_f0_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f0_s2_mul_set, + 0, + 0, + 0, + Field_sal_Slot_f0_s2_mul_set, + Field_sargt_Slot_f0_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f0_s2_mul_11_8_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_13_12_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_18_9_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_1_0_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_26_13_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_26_2_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_26_20_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_4_4_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_7_4_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_multiply_arr_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_multiply_vp_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_multiply_vr_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_multiply_vs_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_multiply_wvt_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f0_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f0_s3_alu_get_field_fns[] = { + Field_t_Slot_f0_s3_alu_get, + 0, + 0, + 0, + Field_imm8_Slot_f0_s3_alu_get, + Field_s_Slot_f0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f0_s3_alu_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f0_s3_alu_get, + 0, + 0, + Field_fld_saimm4_Slot_f0_s3_alu_get, + Field_fld_saimm5_Slot_f0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f0_s3_alu_get, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f0_s3_alu_get, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_14_11_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_14_14_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_24_19_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_10_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_18_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_19_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_25_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_26_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_27_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_9_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_3_2_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_3_3_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_7_3_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_7_7_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_8_0_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_8_8_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_9_7_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_get, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f0_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vbr_Slot_f0_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vr_Slot_f0_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vs_Slot_f0_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vt_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vt_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_spmisc_vbr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_spmisc_vr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_spmisc_vs_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_spmisc_vsm_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_spmisc_vt_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_arr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_isel_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_slct_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_slct_h_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_sr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_vbr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_vr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_vs_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_vt_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_vu_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_shift_vs_Slot_f0_s3_alu_get, + Field_fld_saimm6_31_Slot_f0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f0_s3_alu_set_field_fns[] = { + Field_t_Slot_f0_s3_alu_set, + 0, + 0, + 0, + Field_imm8_Slot_f0_s3_alu_set, + Field_s_Slot_f0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f0_s3_alu_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f0_s3_alu_set, + 0, + 0, + Field_fld_saimm4_Slot_f0_s3_alu_set, + Field_fld_saimm5_Slot_f0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f0_s3_alu_set, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f0_s3_alu_set, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_14_11_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_14_14_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_24_19_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_10_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_18_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_19_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_25_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_26_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_27_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_9_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_3_2_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_3_3_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_7_3_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_7_7_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_8_0_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_8_8_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_9_7_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_set, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f0_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vbr_Slot_f0_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vr_Slot_f0_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vs_Slot_f0_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vt_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vt_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_spmisc_vbr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_spmisc_vr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_spmisc_vs_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_spmisc_vsm_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_spmisc_vt_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_arr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_isel_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_slct_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_slct_h_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_sr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_vbr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_vr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_vs_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_vt_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_vu_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_shift_vs_Slot_f0_s3_alu_set, + Field_fld_saimm6_31_Slot_f0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 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+ 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f1_s0_ldstalu_get_field_fns[] = { + Field_t_Slot_f1_s0_ldstalu_get, + 0, + 0, + 0, + Field_imm8_Slot_f1_s0_ldstalu_get, + Field_s_Slot_f1_s0_ldstalu_get, + Field_imm12b_Slot_f1_s0_ldstalu_get, + Field_imm16_Slot_f1_s0_ldstalu_get, + 0, + 0, + Field_offset_Slot_f1_s0_ldstalu_get, + 0, + 0, + Field_op2_Slot_f1_s0_ldstalu_get, + Field_r_Slot_f1_s0_ldstalu_get, + 0, + 0, + Field_sae_Slot_f1_s0_ldstalu_get, + Field_sal_Slot_f1_s0_ldstalu_get, + Field_sargt_Slot_f1_s0_ldstalu_get, + 0, + Field_sas_Slot_f1_s0_ldstalu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_uus_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_valignr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_vbre_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_vr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_vrr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_vrul_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_alu_arr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f1_s0_ldstalu_get, + Field_fld_saimm4_Slot_f1_s0_ldstalu_get, + Field_fld_saimm5_Slot_f1_s0_ldstalu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s0_ldstalu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f1_s0_ldstalu_12_0_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_12_12_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_12_2_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_12_4_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_12_8_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_14_12_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_14_14_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_15_15_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_14_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_19_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_20_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_6_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_8_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_3_0_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_5_0_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_5_4_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_7_5_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_7_7_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get, + Field_fld_bbe_selimm_s0_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_scatter_gather_vr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f1_s0_ldstalu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f1_s0_ldstalu_set_field_fns[] = { + Field_t_Slot_f1_s0_ldstalu_set, + 0, + 0, + 0, + Field_imm8_Slot_f1_s0_ldstalu_set, + Field_s_Slot_f1_s0_ldstalu_set, + Field_imm12b_Slot_f1_s0_ldstalu_set, + Field_imm16_Slot_f1_s0_ldstalu_set, + 0, + 0, + Field_offset_Slot_f1_s0_ldstalu_set, + 0, + 0, + Field_op2_Slot_f1_s0_ldstalu_set, + Field_r_Slot_f1_s0_ldstalu_set, + 0, + 0, + Field_sae_Slot_f1_s0_ldstalu_set, + Field_sal_Slot_f1_s0_ldstalu_set, + Field_sargt_Slot_f1_s0_ldstalu_set, + 0, + Field_sas_Slot_f1_s0_ldstalu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_uus_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_valignr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_vbre_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_vr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_vrr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_vrul_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_alu_arr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f1_s0_ldstalu_set, + Field_fld_saimm4_Slot_f1_s0_ldstalu_set, + Field_fld_saimm5_Slot_f1_s0_ldstalu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s0_ldstalu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f1_s0_ldstalu_12_0_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_12_12_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_12_2_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_12_4_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_12_8_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_14_12_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_14_14_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_15_15_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_14_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_19_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_20_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_6_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_8_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_3_0_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_5_0_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_5_4_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_7_5_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_7_7_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_set, + Field_fld_bbe_selimm_s0_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_scatter_gather_vr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f1_s0_ldstalu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f1_s1_ld_get_field_fns[] = { + Field_t_Slot_f1_s1_ld_get, + 0, + 0, + 0, + Field_imm8_Slot_f1_s1_ld_get, + Field_s_Slot_f1_s1_ld_get, + Field_imm12b_Slot_f1_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f1_s1_ld_get, + Field_r_Slot_f1_s1_ld_get, + 0, + 0, + Field_sae_Slot_f1_s1_ld_get, + Field_sal_Slot_f1_s1_ld_get, + Field_sargt_Slot_f1_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f1_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f1_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f1_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f1_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f1_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f1_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_vrr_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_vrul_Slot_f1_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f1_s1_ld_get, + Field_fld_bbe_ltrxn_2imm_Slot_f1_s1_ld_get, + Field_fld_bbe_ltrxnimm_Slot_f1_s1_ld_get, + Field_fld_imm1_2n_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_sqz_vbr_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_sqz_vt_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vec_mov_arr_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vec_mov_vbr_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vec_mov_vt_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f1_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f1_s1_ld_12_10_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_12_12_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_12_9_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_15_10_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_15_14_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_15_2_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_15_4_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_15_8_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_1_0_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_26_11_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_26_2_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_3_0_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_7_5_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_7_6_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_7_7_Slot_f1_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f1_s1_ld_set_field_fns[] = { + Field_t_Slot_f1_s1_ld_set, + 0, + 0, + 0, + Field_imm8_Slot_f1_s1_ld_set, + Field_s_Slot_f1_s1_ld_set, + Field_imm12b_Slot_f1_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f1_s1_ld_set, + Field_r_Slot_f1_s1_ld_set, + 0, + 0, + Field_sae_Slot_f1_s1_ld_set, + Field_sal_Slot_f1_s1_ld_set, + Field_sargt_Slot_f1_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f1_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f1_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f1_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f1_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f1_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f1_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_vrr_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_vrul_Slot_f1_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f1_s1_ld_set, + Field_fld_bbe_ltrxn_2imm_Slot_f1_s1_ld_set, + Field_fld_bbe_ltrxnimm_Slot_f1_s1_ld_set, + Field_fld_imm1_2n_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_sqz_vbr_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_sqz_vt_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vec_mov_arr_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vec_mov_vbr_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vec_mov_vt_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f1_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f1_s1_ld_12_10_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_12_12_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_12_9_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_15_10_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_15_14_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_15_2_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_15_4_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_15_8_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_1_0_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_26_11_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_26_2_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_3_0_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_7_5_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_7_6_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_7_7_Slot_f1_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f1_s2_mul_get_field_fns[] = { + Field_t_Slot_f1_s2_mul_get, + 0, + 0, + 0, + Field_imm8_Slot_f1_s2_mul_get, + Field_s_Slot_f1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s2_mul_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f1_s2_mul_get, + Field_fld_saimm4_Slot_f1_s2_mul_get, + Field_fld_saimm5_Slot_f1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f1_s2_mul_get, + 0, + Field_fld_ivp_sem_multiply_vr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_multiply_vs_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_multiply_wvt_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_13_2_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_13_5_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_28_20_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_28_4_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_28_5_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_3_2_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_4_4_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_9_6_Slot_f1_s2_mul_get, + Field_fld_bbe_selimm_s2_Slot_f1_s2_mul_get, + Field_fld_bbe_shflimm_s2_Slot_f1_s2_mul_get, + Field_fld_fp_sem_hp_fma_vbr_Slot_f1_s2_mul_get, + Field_fld_fp_sem_hp_fma_vr_Slot_f1_s2_mul_get, + Field_fld_fp_sem_hp_fma_vs_Slot_f1_s2_mul_get, + Field_fld_fp_sem_hp_fma_vt_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_multiply_vt_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_spfma_vbr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_spfma_vr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_spfma_vs_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_spfma_vt_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vt_Slot_f1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f1_s2_mul_set_field_fns[] = { + Field_t_Slot_f1_s2_mul_set, + 0, + 0, + 0, + Field_imm8_Slot_f1_s2_mul_set, + Field_s_Slot_f1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s2_mul_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f1_s2_mul_set, + Field_fld_saimm4_Slot_f1_s2_mul_set, + Field_fld_saimm5_Slot_f1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f1_s2_mul_set, + 0, + Field_fld_ivp_sem_multiply_vr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_multiply_vs_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_multiply_wvt_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_13_2_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_13_5_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_28_20_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_28_4_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_28_5_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_3_2_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_4_4_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_9_6_Slot_f1_s2_mul_set, + Field_fld_bbe_selimm_s2_Slot_f1_s2_mul_set, + Field_fld_bbe_shflimm_s2_Slot_f1_s2_mul_set, + Field_fld_fp_sem_hp_fma_vbr_Slot_f1_s2_mul_set, + Field_fld_fp_sem_hp_fma_vr_Slot_f1_s2_mul_set, + Field_fld_fp_sem_hp_fma_vs_Slot_f1_s2_mul_set, + Field_fld_fp_sem_hp_fma_vt_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_multiply_vt_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_spfma_vbr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_spfma_vr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_spfma_vs_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_spfma_vt_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vt_Slot_f1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f1_s3_alu_get_field_fns[] = { + Field_t_Slot_f1_s3_alu_get, + 0, + 0, + 0, + Field_imm8_Slot_f1_s3_alu_get, + Field_s_Slot_f1_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f1_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s3_alu_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s3_alu_get, + 0, + 0, + Field_fld_saimm4_Slot_f1_s3_alu_get, + Field_fld_saimm5_Slot_f1_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f1_s3_alu_get, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f1_s3_alu_get, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f1_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f1_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vbr_Slot_f1_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vr_Slot_f1_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vs_Slot_f1_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vt_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vt_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_spmisc_vbr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_spmisc_vr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_spmisc_vs_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_spmisc_vsm_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_spmisc_vt_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_rep_arr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_select_isel_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f1_s3_alu_get, + 0, + 0, + Field_fld_ivp_sem_vec_select_sr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_select_vbr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_select_vr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_select_vs_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_select_vt_Slot_f1_s3_alu_get, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_f1_s3_alu_get, + Field_fld_saimm6_31_Slot_f1_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_14_10_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_14_13_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_14_14_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_19_14_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_19_19_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_19_7_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_30_17_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_30_19_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_30_22_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_30_6_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_30_8_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_3_2_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_3_3_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_5_0_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_9_1_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_9_2_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_9_3_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_9_7_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_arr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vs_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vt_Slot_f1_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f1_s3_alu_set_field_fns[] = { + Field_t_Slot_f1_s3_alu_set, + 0, + 0, + 0, + Field_imm8_Slot_f1_s3_alu_set, + Field_s_Slot_f1_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f1_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s3_alu_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s3_alu_set, + 0, + 0, + Field_fld_saimm4_Slot_f1_s3_alu_set, + Field_fld_saimm5_Slot_f1_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f1_s3_alu_set, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f1_s3_alu_set, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f1_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f1_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vbr_Slot_f1_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vr_Slot_f1_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vs_Slot_f1_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vt_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vt_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_spmisc_vbr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_spmisc_vr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_spmisc_vs_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_spmisc_vsm_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_spmisc_vt_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_rep_arr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_select_isel_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f1_s3_alu_set, + 0, + 0, + Field_fld_ivp_sem_vec_select_sr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_select_vbr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_select_vr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_select_vs_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_select_vt_Slot_f1_s3_alu_set, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_f1_s3_alu_set, + Field_fld_saimm6_31_Slot_f1_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_14_10_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_14_13_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_14_14_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_19_14_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_19_19_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_19_7_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_30_17_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_30_19_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_30_22_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_30_6_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_30_8_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_3_2_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_3_3_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_5_0_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_9_1_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_9_2_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_9_3_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_9_7_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_arr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vs_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vt_Slot_f1_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f2_s0_ldst_get_field_fns[] = { + Field_t_Slot_f2_s0_ldst_get, + 0, + 0, + 0, + Field_imm8_Slot_f2_s0_ldst_get, + Field_s_Slot_f2_s0_ldst_get, + Field_imm12b_Slot_f2_s0_ldst_get, + Field_imm16_Slot_f2_s0_ldst_get, + 0, + 0, + Field_offset_Slot_f2_s0_ldst_get, + 0, + 0, + Field_op2_Slot_f2_s0_ldst_get, + Field_r_Slot_f2_s0_ldst_get, + 0, + 0, + Field_sae_Slot_f2_s0_ldst_get, + Field_sal_Slot_f2_s0_ldst_get, + Field_sargt_Slot_f2_s0_ldst_get, + 0, + Field_sas_Slot_f2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f2_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uus_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_valignr_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f2_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_i_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s0_ldst_get, + 0, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f2_s0_ldst_12_0_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_12_10_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_12_2_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_12_4_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_15_15_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_11_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_14_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_20_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_4_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_8_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_7_2_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f2_s0_ldst_set_field_fns[] = { + Field_t_Slot_f2_s0_ldst_set, + 0, + 0, + 0, + Field_imm8_Slot_f2_s0_ldst_set, + Field_s_Slot_f2_s0_ldst_set, + Field_imm12b_Slot_f2_s0_ldst_set, + Field_imm16_Slot_f2_s0_ldst_set, + 0, + 0, + Field_offset_Slot_f2_s0_ldst_set, + 0, + 0, + Field_op2_Slot_f2_s0_ldst_set, + Field_r_Slot_f2_s0_ldst_set, + 0, + 0, + Field_sae_Slot_f2_s0_ldst_set, + Field_sal_Slot_f2_s0_ldst_set, + Field_sargt_Slot_f2_s0_ldst_set, + 0, + Field_sas_Slot_f2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f2_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uus_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_valignr_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f2_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_i_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s0_ldst_set, + 0, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f2_s0_ldst_12_0_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_12_10_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_12_2_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_12_4_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_15_15_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_11_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_14_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_20_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_4_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_8_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_7_2_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f2_s1_ld_get_field_fns[] = { + Field_t_Slot_f2_s1_ld_get, + 0, + 0, + 0, + Field_imm8_Slot_f2_s1_ld_get, + Field_s_Slot_f2_s1_ld_get, + Field_imm12b_Slot_f2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f2_s1_ld_get, + Field_r_Slot_f2_s1_ld_get, + 0, + 0, + Field_sae_Slot_f2_s1_ld_get, + Field_sal_Slot_f2_s1_ld_get, + Field_sargt_Slot_f2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f2_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f2_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_vrr_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_vrul_Slot_f2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f2_s1_ld_get, + Field_fld_bbe_ltrxn_2imm_Slot_f2_s1_ld_get, + Field_fld_bbe_ltrxnimm_Slot_f2_s1_ld_get, + Field_fld_imm1_2n_Slot_f2_s1_ld_get, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_arr_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f2_s1_ld_get, + 0, + Field_fld_ivp_sem_vec_mov_vt_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f2_s1_ld_12_10_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_12_9_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_15_10_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_15_14_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_15_2_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_15_4_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_15_8_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_1_0_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_26_11_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_26_2_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_3_0_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_7_6_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_7_7_Slot_f2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f2_s1_ld_set_field_fns[] = { + Field_t_Slot_f2_s1_ld_set, + 0, + 0, + 0, + Field_imm8_Slot_f2_s1_ld_set, + Field_s_Slot_f2_s1_ld_set, + Field_imm12b_Slot_f2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f2_s1_ld_set, + Field_r_Slot_f2_s1_ld_set, + 0, + 0, + Field_sae_Slot_f2_s1_ld_set, + Field_sal_Slot_f2_s1_ld_set, + Field_sargt_Slot_f2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f2_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f2_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_vrr_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_vrul_Slot_f2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f2_s1_ld_set, + Field_fld_bbe_ltrxn_2imm_Slot_f2_s1_ld_set, + Field_fld_bbe_ltrxnimm_Slot_f2_s1_ld_set, + Field_fld_imm1_2n_Slot_f2_s1_ld_set, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_arr_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f2_s1_ld_set, + 0, + Field_fld_ivp_sem_vec_mov_vt_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f2_s1_ld_12_10_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_12_9_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_15_10_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_15_14_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_15_2_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_15_4_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_15_8_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_1_0_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_26_11_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_26_2_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_3_0_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_7_6_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_7_7_Slot_f2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f2_s2_mul_get_field_fns[] = { + Field_t_Slot_f2_s2_mul_get, + 0, + 0, + 0, + Field_imm8_Slot_f2_s2_mul_get, + Field_s_Slot_f2_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f2_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f2_s2_mul_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f2_s2_mul_get, + 0, + 0, + Field_fld_saimm4_Slot_f2_s2_mul_get, + Field_fld_saimm5_Slot_f2_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_multiply_vp_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_multiply_vr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_multiply_vs_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_multiply_wvt_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f2_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_fma_vbr_Slot_f2_s2_mul_get, + Field_fld_fp_sem_hp_fma_vr_Slot_f2_s2_mul_get, + Field_fld_fp_sem_hp_fma_vs_Slot_f2_s2_mul_get, + Field_fld_fp_sem_hp_fma_vt_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_multiply_vt_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_spfma_vbr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_spfma_vr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_spfma_vs_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_spfma_vt_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vt_Slot_f2_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_14_11_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_14_5_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_19_10_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_19_7_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_30_10_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_30_18_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_30_6_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_5_0_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_divide_lane_ctrl_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_divide_vr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_divide_vs_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_divide_vt_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_divide_vu_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_multiply_vbr_Slot_f2_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f2_s2_mul_set_field_fns[] = { + Field_t_Slot_f2_s2_mul_set, + 0, + 0, + 0, + Field_imm8_Slot_f2_s2_mul_set, + Field_s_Slot_f2_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f2_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f2_s2_mul_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f2_s2_mul_set, + 0, + 0, + Field_fld_saimm4_Slot_f2_s2_mul_set, + Field_fld_saimm5_Slot_f2_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_multiply_vp_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_multiply_vr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_multiply_vs_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_multiply_wvt_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f2_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_fma_vbr_Slot_f2_s2_mul_set, + Field_fld_fp_sem_hp_fma_vr_Slot_f2_s2_mul_set, + Field_fld_fp_sem_hp_fma_vs_Slot_f2_s2_mul_set, + Field_fld_fp_sem_hp_fma_vt_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_multiply_vt_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_spfma_vbr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_spfma_vr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_spfma_vs_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_spfma_vt_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vt_Slot_f2_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_14_11_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_14_5_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_19_10_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_19_7_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_30_10_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_30_18_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_30_6_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_5_0_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_divide_lane_ctrl_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_divide_vr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_divide_vs_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_divide_vt_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_divide_vu_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_multiply_vbr_Slot_f2_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f2_s3_alu_get_field_fns[] = { + Field_t_Slot_f2_s3_alu_get, + 0, + 0, + 0, + Field_imm8_Slot_f2_s3_alu_get, + Field_s_Slot_f2_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f2_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f2_s3_alu_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f2_s3_alu_get, + 0, + 0, + Field_fld_saimm4_Slot_f2_s3_alu_get, + Field_fld_saimm5_Slot_f2_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f2_s3_alu_get, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f2_s3_alu_get, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f2_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f2_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f2_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vbr_Slot_f2_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vr_Slot_f2_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vs_Slot_f2_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vt_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vt_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_spmisc_vbr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_spmisc_vr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_spmisc_vs_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_spmisc_vsm_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_spmisc_vt_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_rep_arr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_select_isel_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f2_s3_alu_get, + 0, + 0, + Field_fld_ivp_sem_vec_select_sr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_select_vbr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_select_vr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_select_vs_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_select_vt_Slot_f2_s3_alu_get, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_f2_s3_alu_get, + Field_fld_saimm6_31_Slot_f2_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_14_10_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_14_13_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_14_14_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_19_14_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_19_19_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_19_7_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_30_18_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_30_19_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_30_22_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_30_6_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_30_8_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_3_2_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_3_3_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_5_0_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_9_1_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_9_2_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_9_3_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_9_7_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_9_9_Slot_f2_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f2_s3_alu_set_field_fns[] = { + Field_t_Slot_f2_s3_alu_set, + 0, + 0, + 0, + Field_imm8_Slot_f2_s3_alu_set, + Field_s_Slot_f2_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f2_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f2_s3_alu_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f2_s3_alu_set, + 0, + 0, + Field_fld_saimm4_Slot_f2_s3_alu_set, + Field_fld_saimm5_Slot_f2_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f2_s3_alu_set, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f2_s3_alu_set, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f2_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f2_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f2_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vbr_Slot_f2_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vr_Slot_f2_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vs_Slot_f2_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vt_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vt_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_spmisc_vbr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_spmisc_vr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_spmisc_vs_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_spmisc_vsm_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_spmisc_vt_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_rep_arr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_select_isel_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f2_s3_alu_set, + 0, + 0, + Field_fld_ivp_sem_vec_select_sr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_select_vbr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_select_vr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_select_vs_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_select_vt_Slot_f2_s3_alu_set, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_f2_s3_alu_set, + Field_fld_saimm6_31_Slot_f2_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_14_10_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_14_13_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_14_14_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_19_14_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_19_19_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_19_7_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_30_18_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_30_19_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_30_22_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_30_6_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_30_8_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_3_2_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_3_3_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_5_0_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_9_1_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_9_2_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_9_3_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_9_7_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_9_9_Slot_f2_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f3_s0_ldst_get_field_fns[] = { + Field_t_Slot_f3_s0_ldst_get, + 0, + 0, + 0, + Field_imm8_Slot_f3_s0_ldst_get, + Field_s_Slot_f3_s0_ldst_get, + Field_imm12b_Slot_f3_s0_ldst_get, + Field_imm16_Slot_f3_s0_ldst_get, + 0, + 0, + Field_offset_Slot_f3_s0_ldst_get, + 0, + 0, + Field_op2_Slot_f3_s0_ldst_get, + Field_r_Slot_f3_s0_ldst_get, + 0, + 0, + Field_sae_Slot_f3_s0_ldst_get, + Field_sal_Slot_f3_s0_ldst_get, + Field_sargt_Slot_f3_s0_ldst_get, + 0, + Field_sas_Slot_f3_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uus_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_valignr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vbre_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vrr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vrul_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_arr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_shift_vr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f3_s0_ldst_get, + Field_fld_saimm4_Slot_f3_s0_ldst_get, + Field_fld_saimm5_Slot_f3_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s0_ldst_0_0_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_12_0_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_12_11_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_12_12_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_12_4_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_12_8_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_13_9_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_15_15_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_1_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_11_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_19_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_20_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_4_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_8_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_3_0_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_7_5_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_7_7_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_8_0_Slot_f3_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f3_s0_ldst_set_field_fns[] = { + Field_t_Slot_f3_s0_ldst_set, + 0, + 0, + 0, + Field_imm8_Slot_f3_s0_ldst_set, + Field_s_Slot_f3_s0_ldst_set, + Field_imm12b_Slot_f3_s0_ldst_set, + Field_imm16_Slot_f3_s0_ldst_set, + 0, + 0, + Field_offset_Slot_f3_s0_ldst_set, + 0, + 0, + Field_op2_Slot_f3_s0_ldst_set, + Field_r_Slot_f3_s0_ldst_set, + 0, + 0, + Field_sae_Slot_f3_s0_ldst_set, + Field_sal_Slot_f3_s0_ldst_set, + Field_sargt_Slot_f3_s0_ldst_set, + 0, + Field_sas_Slot_f3_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uus_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_valignr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vbre_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vrr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vrul_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_arr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_shift_vr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f3_s0_ldst_set, + Field_fld_saimm4_Slot_f3_s0_ldst_set, + Field_fld_saimm5_Slot_f3_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s0_ldst_0_0_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_12_0_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_12_11_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_12_12_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_12_4_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_12_8_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_13_9_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_15_15_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_1_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_11_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_19_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_20_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_4_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_8_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_3_0_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_7_5_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_7_7_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_8_0_Slot_f3_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f3_s1_ld_get_field_fns[] = { + Field_t_Slot_f3_s1_ld_get, + 0, + 0, + 0, + Field_imm8_Slot_f3_s1_ld_get, + Field_s_Slot_f3_s1_ld_get, + Field_imm12b_Slot_f3_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f3_s1_ld_get, + Field_r_Slot_f3_s1_ld_get, + 0, + 0, + Field_sae_Slot_f3_s1_ld_get, + Field_sal_Slot_f3_s1_ld_get, + Field_sargt_Slot_f3_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f3_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f3_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f3_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f3_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f3_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f3_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f3_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f3_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_f3_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f3_s1_ld_get, + Field_fld_bbe_ltrxn_2imm_Slot_f3_s1_ld_get, + Field_fld_bbe_ltrxnimm_Slot_f3_s1_ld_get, + Field_fld_imm1_2n_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_sqz_vbr_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_sqz_vt_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vec_mov_arr_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vec_mov_vbr_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vec_mov_vt_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f3_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s1_ld_12_11_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_12_2_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_12_4_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_12_8_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_0_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_10_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_16_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_9_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_3_0_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_7_0_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_7_7_Slot_f3_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f3_s1_ld_set_field_fns[] = { + Field_t_Slot_f3_s1_ld_set, + 0, + 0, + 0, + Field_imm8_Slot_f3_s1_ld_set, + Field_s_Slot_f3_s1_ld_set, + Field_imm12b_Slot_f3_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f3_s1_ld_set, + Field_r_Slot_f3_s1_ld_set, + 0, + 0, + Field_sae_Slot_f3_s1_ld_set, + Field_sal_Slot_f3_s1_ld_set, + Field_sargt_Slot_f3_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f3_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f3_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f3_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f3_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f3_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f3_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f3_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f3_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_f3_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f3_s1_ld_set, + Field_fld_bbe_ltrxn_2imm_Slot_f3_s1_ld_set, + Field_fld_bbe_ltrxnimm_Slot_f3_s1_ld_set, + Field_fld_imm1_2n_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_sqz_vbr_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_sqz_vt_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vec_mov_arr_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vec_mov_vbr_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vec_mov_vt_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f3_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s1_ld_12_11_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_12_2_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_12_4_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_12_8_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_0_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_10_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_16_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_9_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_3_0_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_7_0_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_7_7_Slot_f3_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f3_s2_mul_get_field_fns[] = { + Field_t_Slot_f3_s2_mul_get, + 0, + 0, + 0, + Field_imm8_Slot_f3_s2_mul_get, + Field_s_Slot_f3_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f3_s2_mul_get, + 0, + 0, + 0, + Field_sal_Slot_f3_s2_mul_get, + Field_sargt_Slot_f3_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f3_s2_mul_get, + 0, + Field_fld_ivp_sem_multiply_vr_Slot_f3_s2_mul_get, + Field_fld_ivp_sem_multiply_vs_Slot_f3_s2_mul_get, + Field_fld_ivp_sem_multiply_wvt_Slot_f3_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f3_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f3_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f3_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f3_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s2_mul_11_8_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_13_12_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_13_7_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_21_0_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_21_13_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_21_15_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_7_4_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_7_5_Slot_f3_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f3_s2_mul_set_field_fns[] = { + Field_t_Slot_f3_s2_mul_set, + 0, + 0, + 0, + Field_imm8_Slot_f3_s2_mul_set, + Field_s_Slot_f3_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f3_s2_mul_set, + 0, + 0, + 0, + Field_sal_Slot_f3_s2_mul_set, + Field_sargt_Slot_f3_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f3_s2_mul_set, + 0, + Field_fld_ivp_sem_multiply_vr_Slot_f3_s2_mul_set, + Field_fld_ivp_sem_multiply_vs_Slot_f3_s2_mul_set, + Field_fld_ivp_sem_multiply_wvt_Slot_f3_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f3_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f3_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f3_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f3_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s2_mul_11_8_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_13_12_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_13_7_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_21_0_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_21_13_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_21_15_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_7_4_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_7_5_Slot_f3_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f3_s3_alu_get_field_fns[] = { + Field_t_Slot_f3_s3_alu_get, + 0, + 0, + 0, + Field_imm8_Slot_f3_s3_alu_get, + Field_s_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f3_s3_alu_get, + 0, + 0, + Field_fld_saimm4_Slot_f3_s3_alu_get, + Field_fld_saimm5_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f3_s3_alu_get, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f3_s3_alu_get, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f3_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vbr_Slot_f3_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vr_Slot_f3_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vs_Slot_f3_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vt_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vt_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_spmisc_vbr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_spmisc_vr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_spmisc_vs_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_spmisc_vsm_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_spmisc_vt_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_rep_arr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_select_isel_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_select_vr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_select_vs_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_select_vt_Slot_f3_s3_alu_get, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_f3_s3_alu_get, + Field_fld_saimm6_31_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_histogram_arr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vs_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vt_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_18_12_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_18_13_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_18_14_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_18_18_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_18_7_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_18_8_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_12_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_18_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_20_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_21_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_25_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_4_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_8_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_9_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_3_2_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_7_6_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vbr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vbs_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f3_s3_alu_set_field_fns[] = { + Field_t_Slot_f3_s3_alu_set, + 0, + 0, + 0, + Field_imm8_Slot_f3_s3_alu_set, + Field_s_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f3_s3_alu_set, + 0, + 0, + Field_fld_saimm4_Slot_f3_s3_alu_set, + Field_fld_saimm5_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f3_s3_alu_set, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f3_s3_alu_set, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f3_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vbr_Slot_f3_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vr_Slot_f3_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vs_Slot_f3_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vt_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vt_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_spmisc_vbr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_spmisc_vr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_spmisc_vs_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_spmisc_vsm_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_spmisc_vt_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_rep_arr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_select_isel_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_select_vr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_select_vs_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_select_vt_Slot_f3_s3_alu_set, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_f3_s3_alu_set, + Field_fld_saimm6_31_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_histogram_arr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vs_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vt_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_18_12_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_18_13_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_18_14_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_18_18_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_18_7_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_18_8_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_12_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_18_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_20_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_21_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_25_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_4_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_8_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_9_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_3_2_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_7_6_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vbr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vbs_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f3_s4_alu_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s4_alu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f3_s4_alu_get, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f3_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s4_alu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f3_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get, + Field_fld_f3_s4_alu_23_0_Slot_f3_s4_alu_get, + Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get, + Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get, + Field_fld_f3_s4_alu_23_20_Slot_f3_s4_alu_get, + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get, + Field_fld_f3_s4_alu_9_6_Slot_f3_s4_alu_get, + Field_fld_bbe_selimm_s4_Slot_f3_s4_alu_get, + Field_fld_bbe_shflimm_s4_Slot_f3_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_mtk_andpopc_c_Slot_f3_s4_alu_get, + Field_fld_mtk_andpopc_inb_Slot_f3_s4_alu_get, + Field_fld_mtk_andpopc_ina_Slot_f3_s4_alu_get, + Field_fld_mtk_andpopc_odata_Slot_f3_s4_alu_get, + 0, + Field_fld_f3_s4_alu_23_16_Slot_f3_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f3_s4_alu_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s4_alu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f3_s4_alu_set, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f3_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s4_alu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f3_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_set, + Field_fld_f3_s4_alu_23_0_Slot_f3_s4_alu_set, + Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_set, + Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_set, + Field_fld_f3_s4_alu_23_20_Slot_f3_s4_alu_set, + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_set, + Field_fld_f3_s4_alu_9_6_Slot_f3_s4_alu_set, + Field_fld_bbe_selimm_s4_Slot_f3_s4_alu_set, + Field_fld_bbe_shflimm_s4_Slot_f3_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_mtk_andpopc_c_Slot_f3_s4_alu_set, + Field_fld_mtk_andpopc_inb_Slot_f3_s4_alu_set, + Field_fld_mtk_andpopc_ina_Slot_f3_s4_alu_set, + Field_fld_mtk_andpopc_odata_Slot_f3_s4_alu_set, + 0, + Field_fld_f3_s4_alu_23_16_Slot_f3_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f4_s0_ld_get_field_fns[] = { + Field_t_Slot_f4_s0_ld_get, + 0, + Field_bbi_Slot_f4_s0_ld_get, + 0, + Field_imm8_Slot_f4_s0_ld_get, + Field_s_Slot_f4_s0_ld_get, + Field_imm12b_Slot_f4_s0_ld_get, + Field_imm16_Slot_f4_s0_ld_get, + 0, + 0, + Field_offset_Slot_f4_s0_ld_get, + 0, + 0, + Field_op2_Slot_f4_s0_ld_get, + Field_r_Slot_f4_s0_ld_get, + 0, + 0, + Field_sae_Slot_f4_s0_ld_get, + Field_sal_Slot_f4_s0_ld_get, + Field_sargt_Slot_f4_s0_ld_get, + 0, + Field_sas_Slot_f4_s0_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_f4_s0_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f4_s0_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f4_s0_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f4_s0_ld_get, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f4_s0_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vbre_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_vr_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_vrr_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_vrul_Slot_f4_s0_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f4_s0_ld_11_4_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_11_9_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_12_0_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_12_2_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_12_4_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_12_8_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_15_15_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_20_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_7_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_8_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_9_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_3_0_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_6_0_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_6_4_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f4_s0_ld_set_field_fns[] = { + Field_t_Slot_f4_s0_ld_set, + 0, + Field_bbi_Slot_f4_s0_ld_set, + 0, + Field_imm8_Slot_f4_s0_ld_set, + Field_s_Slot_f4_s0_ld_set, + Field_imm12b_Slot_f4_s0_ld_set, + Field_imm16_Slot_f4_s0_ld_set, + 0, + 0, + Field_offset_Slot_f4_s0_ld_set, + 0, + 0, + Field_op2_Slot_f4_s0_ld_set, + Field_r_Slot_f4_s0_ld_set, + 0, + 0, + Field_sae_Slot_f4_s0_ld_set, + Field_sal_Slot_f4_s0_ld_set, + Field_sargt_Slot_f4_s0_ld_set, + 0, + Field_sas_Slot_f4_s0_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_f4_s0_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f4_s0_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f4_s0_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f4_s0_ld_set, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f4_s0_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vbre_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_vr_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_vrr_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_vrul_Slot_f4_s0_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f4_s0_ld_11_4_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_11_9_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_12_0_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_12_2_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_12_4_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_12_8_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_15_15_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_20_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_7_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_8_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_9_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_3_0_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_6_0_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_6_4_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f4_s1_ld_get_field_fns[] = { + Field_t_Slot_f4_s1_ld_get, + 0, + 0, + 0, + Field_imm8_Slot_f4_s1_ld_get, + Field_s_Slot_f4_s1_ld_get, + Field_imm12b_Slot_f4_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f4_s1_ld_get, + Field_r_Slot_f4_s1_ld_get, + 0, + 0, + Field_sae_Slot_f4_s1_ld_get, + Field_sal_Slot_f4_s1_ld_get, + Field_sargt_Slot_f4_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f4_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f4_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f4_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f4_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f4_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f4_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f4_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f4_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_f4_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f4_s1_ld_get, + Field_fld_bbe_ltrxn_2imm_Slot_f4_s1_ld_get, + Field_fld_bbe_ltrxnimm_Slot_f4_s1_ld_get, + 0, + Field_fld_ivp_sem_sqz_vbr_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_sqz_vt_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_vec_mov_arr_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f4_s1_ld_get, + 0, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f4_s1_ld_get, + 0, + Field_fld_ivp_sem_vec_mov_vt_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f4_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f4_s1_ld_12_10_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_12_2_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_12_4_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_12_8_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_0_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_10_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_16_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_9_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_4_0_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_7_0_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_7_6_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_7_7_Slot_f4_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f4_s1_ld_set_field_fns[] = { + Field_t_Slot_f4_s1_ld_set, + 0, + 0, + 0, + Field_imm8_Slot_f4_s1_ld_set, + Field_s_Slot_f4_s1_ld_set, + Field_imm12b_Slot_f4_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f4_s1_ld_set, + Field_r_Slot_f4_s1_ld_set, + 0, + 0, + Field_sae_Slot_f4_s1_ld_set, + Field_sal_Slot_f4_s1_ld_set, + Field_sargt_Slot_f4_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f4_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f4_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f4_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f4_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f4_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f4_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f4_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f4_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_f4_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f4_s1_ld_set, + Field_fld_bbe_ltrxn_2imm_Slot_f4_s1_ld_set, + Field_fld_bbe_ltrxnimm_Slot_f4_s1_ld_set, + 0, + Field_fld_ivp_sem_sqz_vbr_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_sqz_vt_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_vec_mov_arr_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f4_s1_ld_set, + 0, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f4_s1_ld_set, + 0, + Field_fld_ivp_sem_vec_mov_vt_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f4_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f4_s1_ld_12_10_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_12_2_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_12_4_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_12_8_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_0_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_10_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_16_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_9_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_4_0_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_7_0_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_7_6_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_7_7_Slot_f4_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f4_s2_mul_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f4_s2_mul_get, + Field_fld_ivp_sem_multiply_vp_Slot_f4_s2_mul_get, + Field_fld_ivp_sem_multiply_vr_Slot_f4_s2_mul_get, + Field_fld_ivp_sem_multiply_vs_Slot_f4_s2_mul_get, + Field_fld_ivp_sem_multiply_wvt_Slot_f4_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get, + Field_fld_f4_s2_mul_32_8_Slot_f4_s2_mul_get, + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get, + Field_fld_f4_s2_mul_7_0_Slot_f4_s2_mul_get, + Field_fld_ivp_sem_multiply_vq_Slot_f4_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f4_s2_mul_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f4_s2_mul_set, + Field_fld_ivp_sem_multiply_vp_Slot_f4_s2_mul_set, + Field_fld_ivp_sem_multiply_vr_Slot_f4_s2_mul_set, + Field_fld_ivp_sem_multiply_vs_Slot_f4_s2_mul_set, + Field_fld_ivp_sem_multiply_wvt_Slot_f4_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_set, + Field_fld_f4_s2_mul_32_8_Slot_f4_s2_mul_set, + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_set, + Field_fld_f4_s2_mul_7_0_Slot_f4_s2_mul_set, + Field_fld_ivp_sem_multiply_vq_Slot_f4_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f4_s3_alu_get_field_fns[] = { + Field_t_Slot_f4_s3_alu_get, + 0, + 0, + 0, + Field_imm8_Slot_f4_s3_alu_get, + Field_s_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f4_s3_alu_get, + 0, + 0, + Field_fld_saimm4_Slot_f4_s3_alu_get, + Field_fld_saimm5_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f4_s3_alu_get, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_rep_arr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_isel_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_slct_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_slct_h_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_sr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_vbr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_vr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_vs_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_vt_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_vu_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_shift_vs_Slot_f4_s3_alu_get, + Field_fld_saimm6_31_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_histogram_arr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vs_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vt_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_histogram_vbr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vbs_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_14_14_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_14_6_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_19_13_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_19_6_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_19_8_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_24_13_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_24_18_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_24_21_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_31_19_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_31_28_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_31_7_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_31_8_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_3_2_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_3_3_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_6_0_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_9_8_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f4_s3_alu_set_field_fns[] = { + Field_t_Slot_f4_s3_alu_set, + 0, + 0, + 0, + Field_imm8_Slot_f4_s3_alu_set, + Field_s_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f4_s3_alu_set, + 0, + 0, + Field_fld_saimm4_Slot_f4_s3_alu_set, + Field_fld_saimm5_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f4_s3_alu_set, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_rep_arr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_isel_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_slct_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_slct_h_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_sr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_vbr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_vr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_vs_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_vt_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_vu_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_shift_vs_Slot_f4_s3_alu_set, + Field_fld_saimm6_31_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_histogram_arr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vs_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vt_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_histogram_vbr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vbs_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_14_14_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_14_6_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_19_13_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_19_6_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_19_8_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_24_13_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_24_18_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_24_21_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_31_19_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_31_28_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_31_7_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_31_8_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_3_2_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_3_3_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_6_0_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_9_8_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f5_s0_base_get_field_fns[] = { + Field_t_Slot_f5_s0_base_get, + 0, + Field_bbi_Slot_f5_s0_base_get, + 0, + Field_imm8_Slot_f5_s0_base_get, + Field_s_Slot_f5_s0_base_get, + Field_imm12b_Slot_f5_s0_base_get, + Field_imm16_Slot_f5_s0_base_get, + 0, + 0, + Field_offset_Slot_f5_s0_base_get, + 0, + 0, + Field_op2_Slot_f5_s0_base_get, + Field_r_Slot_f5_s0_base_get, + 0, + 0, + Field_sae_Slot_f5_s0_base_get, + Field_sal_Slot_f5_s0_base_get, + Field_sargt_Slot_f5_s0_base_get, + 0, + Field_sas_Slot_f5_s0_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_f5_s0_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f5_s0_base_11_0_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_11_9_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_36_13_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_36_17_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_36_18_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_36_20_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_3_1_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_7_4_Slot_f5_s0_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f5_s0_base_set_field_fns[] = { + Field_t_Slot_f5_s0_base_set, + 0, + Field_bbi_Slot_f5_s0_base_set, + 0, + Field_imm8_Slot_f5_s0_base_set, + Field_s_Slot_f5_s0_base_set, + Field_imm12b_Slot_f5_s0_base_set, + Field_imm16_Slot_f5_s0_base_set, + 0, + 0, + Field_offset_Slot_f5_s0_base_set, + 0, + 0, + Field_op2_Slot_f5_s0_base_set, + Field_r_Slot_f5_s0_base_set, + 0, + 0, + Field_sae_Slot_f5_s0_base_set, + Field_sal_Slot_f5_s0_base_set, + Field_sargt_Slot_f5_s0_base_set, + 0, + Field_sas_Slot_f5_s0_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_f5_s0_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f5_s0_base_11_0_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_11_9_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_36_13_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_36_17_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_36_18_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_36_20_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_3_1_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_7_4_Slot_f5_s0_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f5_s1_base_get_field_fns[] = { + Field_t_Slot_f5_s1_base_get, + 0, + 0, + 0, + Field_imm8_Slot_f5_s1_base_get, + Field_s_Slot_f5_s1_base_get, + Field_imm12b_Slot_f5_s1_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f5_s1_base_get, + Field_r_Slot_f5_s1_base_get, + 0, + 0, + Field_sae_Slot_f5_s1_base_get, + Field_sal_Slot_f5_s1_base_get, + Field_sargt_Slot_f5_s1_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get, + Field_fld_f5_s1_base_27_13_Slot_f5_s1_base_get, + Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_get, + Field_fld_f5_s1_base_27_17_Slot_f5_s1_base_get, + Field_fld_f5_s1_base_27_3_Slot_f5_s1_base_get, + Field_fld_f5_s1_base_2_0_Slot_f5_s1_base_get, + Field_fld_f5_s1_base_3_0_Slot_f5_s1_base_get, + Field_fld_f5_s1_base_7_4_Slot_f5_s1_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f5_s1_base_set_field_fns[] = { + Field_t_Slot_f5_s1_base_set, + 0, + 0, + 0, + Field_imm8_Slot_f5_s1_base_set, + Field_s_Slot_f5_s1_base_set, + Field_imm12b_Slot_f5_s1_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f5_s1_base_set, + Field_r_Slot_f5_s1_base_set, + 0, + 0, + Field_sae_Slot_f5_s1_base_set, + Field_sal_Slot_f5_s1_base_set, + Field_sargt_Slot_f5_s1_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_set, + Field_fld_f5_s1_base_27_13_Slot_f5_s1_base_set, + Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_set, + Field_fld_f5_s1_base_27_17_Slot_f5_s1_base_set, + Field_fld_f5_s1_base_27_3_Slot_f5_s1_base_set, + Field_fld_f5_s1_base_2_0_Slot_f5_s1_base_set, + Field_fld_f5_s1_base_3_0_Slot_f5_s1_base_set, + Field_fld_f5_s1_base_7_4_Slot_f5_s1_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f5_s2_base_get_field_fns[] = { + Field_t_Slot_f5_s2_base_get, + 0, + 0, + 0, + Field_imm8_Slot_f5_s2_base_get, + Field_s_Slot_f5_s2_base_get, + Field_imm12b_Slot_f5_s2_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f5_s2_base_get, + 0, + 0, + 0, + Field_sal_Slot_f5_s2_base_get, + Field_sargt_Slot_f5_s2_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f5_s2_base_1_0_Slot_f5_s2_base_get, + Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get, + Field_fld_f5_s2_base_26_13_Slot_f5_s2_base_get, + Field_fld_f5_s2_base_26_16_Slot_f5_s2_base_get, + Field_fld_f5_s2_base_26_2_Slot_f5_s2_base_get, + Field_fld_f5_s2_base_26_8_Slot_f5_s2_base_get, + Field_fld_f5_s2_base_3_0_Slot_f5_s2_base_get, + Field_fld_f5_s2_base_7_4_Slot_f5_s2_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f5_s2_base_set_field_fns[] = { + Field_t_Slot_f5_s2_base_set, + 0, + 0, + 0, + Field_imm8_Slot_f5_s2_base_set, + Field_s_Slot_f5_s2_base_set, + Field_imm12b_Slot_f5_s2_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f5_s2_base_set, + 0, + 0, + 0, + Field_sal_Slot_f5_s2_base_set, + Field_sargt_Slot_f5_s2_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f5_s2_base_1_0_Slot_f5_s2_base_set, + Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_set, + Field_fld_f5_s2_base_26_13_Slot_f5_s2_base_set, + Field_fld_f5_s2_base_26_16_Slot_f5_s2_base_set, + Field_fld_f5_s2_base_26_2_Slot_f5_s2_base_set, + Field_fld_f5_s2_base_26_8_Slot_f5_s2_base_set, + Field_fld_f5_s2_base_3_0_Slot_f5_s2_base_set, + Field_fld_f5_s2_base_7_4_Slot_f5_s2_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f5_s3_base_get_field_fns[] = { + Field_t_Slot_f5_s3_base_get, + 0, + 0, + 0, + Field_imm8_Slot_f5_s3_base_get, + Field_s_Slot_f5_s3_base_get, + Field_imm12b_Slot_f5_s3_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f5_s3_base_0_0_Slot_f5_s3_base_get, + Field_fld_f5_s3_base_25_1_Slot_f5_s3_base_get, + Field_fld_f5_s3_base_25_16_Slot_f5_s3_base_get, + Field_fld_f5_s3_base_25_8_Slot_f5_s3_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f5_s3_base_set_field_fns[] = { + Field_t_Slot_f5_s3_base_set, + 0, + 0, + 0, + Field_imm8_Slot_f5_s3_base_set, + Field_s_Slot_f5_s3_base_set, + Field_imm12b_Slot_f5_s3_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f5_s3_base_0_0_Slot_f5_s3_base_set, + Field_fld_f5_s3_base_25_1_Slot_f5_s3_base_set, + Field_fld_f5_s3_base_25_16_Slot_f5_s3_base_set, + Field_fld_f5_s3_base_25_8_Slot_f5_s3_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f11_s0_ld_get_field_fns[] = { + Field_t_Slot_f11_s0_ld_get, + 0, + 0, + 0, + Field_imm8_Slot_f11_s0_ld_get, + Field_s_Slot_f11_s0_ld_get, + Field_imm12b_Slot_f11_s0_ld_get, + Field_imm16_Slot_f11_s0_ld_get, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f11_s0_ld_get, + Field_r_Slot_f11_s0_ld_get, + 0, + 0, + Field_sae_Slot_f11_s0_ld_get, + Field_sal_Slot_f11_s0_ld_get, + Field_sargt_Slot_f11_s0_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_uul_Slot_f11_s0_ld_get, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f11_s0_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s0_ld_1_0_Slot_f11_s0_ld_get, + Field_fld_f11_s0_ld_23_0_Slot_f11_s0_ld_get, + Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get, + Field_fld_f11_s0_ld_23_13_Slot_f11_s0_ld_get, + Field_fld_f11_s0_ld_23_16_Slot_f11_s0_ld_get, + Field_fld_f11_s0_ld_23_17_Slot_f11_s0_ld_get, + Field_fld_f11_s0_ld_23_20_Slot_f11_s0_ld_get, + Field_fld_f11_s0_ld_23_4_Slot_f11_s0_ld_get, + Field_fld_f11_s0_ld_3_0_Slot_f11_s0_ld_get, + Field_fld_f11_s0_ld_7_4_Slot_f11_s0_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f11_s0_ld_set_field_fns[] = { + Field_t_Slot_f11_s0_ld_set, + 0, + 0, + 0, + Field_imm8_Slot_f11_s0_ld_set, + Field_s_Slot_f11_s0_ld_set, + Field_imm12b_Slot_f11_s0_ld_set, + Field_imm16_Slot_f11_s0_ld_set, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f11_s0_ld_set, + Field_r_Slot_f11_s0_ld_set, + 0, + 0, + Field_sae_Slot_f11_s0_ld_set, + Field_sal_Slot_f11_s0_ld_set, + Field_sargt_Slot_f11_s0_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_uul_Slot_f11_s0_ld_set, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f11_s0_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s0_ld_1_0_Slot_f11_s0_ld_set, + Field_fld_f11_s0_ld_23_0_Slot_f11_s0_ld_set, + Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_set, + Field_fld_f11_s0_ld_23_13_Slot_f11_s0_ld_set, + Field_fld_f11_s0_ld_23_16_Slot_f11_s0_ld_set, + Field_fld_f11_s0_ld_23_17_Slot_f11_s0_ld_set, + Field_fld_f11_s0_ld_23_20_Slot_f11_s0_ld_set, + Field_fld_f11_s0_ld_23_4_Slot_f11_s0_ld_set, + Field_fld_f11_s0_ld_3_0_Slot_f11_s0_ld_set, + Field_fld_f11_s0_ld_7_4_Slot_f11_s0_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f11_s1_alu_get_field_fns[] = { + Field_t_Slot_f11_s1_alu_get, + 0, + 0, + 0, + Field_imm8_Slot_f11_s1_alu_get, + Field_s_Slot_f11_s1_alu_get, + Field_imm12b_Slot_f11_s1_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f11_s1_alu_get, + Field_r_Slot_f11_s1_alu_get, + 0, + 0, + Field_sae_Slot_f11_s1_alu_get, + Field_sal_Slot_f11_s1_alu_get, + Field_sargt_Slot_f11_s1_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_uul_Slot_f11_s1_alu_get, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f11_s1_alu_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f11_s1_alu_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_f11_s1_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f11_s1_alu_get, + Field_fld_bbe_ltrxn_2imm_Slot_f11_s1_alu_get, + Field_fld_bbe_ltrxnimm_Slot_f11_s1_alu_get, + Field_fld_imm1_2n_Slot_f11_s1_alu_get, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f11_s1_alu_get, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f11_s1_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s1_alu_12_10_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_12_11_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_12_12_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_12_9_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_15_13_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_15_14_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_15_15_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_15_2_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_22_0_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_22_13_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_22_14_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_3_0_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_get, + Field_fld_ivp_sem_ld_st_vrul2_Slot_f11_s1_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f11_s1_alu_set_field_fns[] = { + Field_t_Slot_f11_s1_alu_set, + 0, + 0, + 0, + Field_imm8_Slot_f11_s1_alu_set, + Field_s_Slot_f11_s1_alu_set, + Field_imm12b_Slot_f11_s1_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f11_s1_alu_set, + Field_r_Slot_f11_s1_alu_set, + 0, + 0, + Field_sae_Slot_f11_s1_alu_set, + Field_sal_Slot_f11_s1_alu_set, + Field_sargt_Slot_f11_s1_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_uul_Slot_f11_s1_alu_set, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f11_s1_alu_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f11_s1_alu_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_f11_s1_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f11_s1_alu_set, + Field_fld_bbe_ltrxn_2imm_Slot_f11_s1_alu_set, + Field_fld_bbe_ltrxnimm_Slot_f11_s1_alu_set, + Field_fld_imm1_2n_Slot_f11_s1_alu_set, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f11_s1_alu_set, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f11_s1_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s1_alu_12_10_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_12_11_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_12_12_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_12_9_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_15_13_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_15_14_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_15_15_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_15_2_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_22_0_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_22_13_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_22_14_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_3_0_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_set, + Field_fld_ivp_sem_ld_st_vrul2_Slot_f11_s1_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f11_s2_mul_get_field_fns[] = { + Field_t_Slot_f11_s2_mul_get, + 0, + 0, + 0, + Field_imm8_Slot_f11_s2_mul_get, + Field_s_Slot_f11_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f11_s2_mul_get, + 0, + 0, + 0, + Field_sal_Slot_f11_s2_mul_get, + Field_sargt_Slot_f11_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s2_mul_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_vr_Slot_f11_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f11_s2_mul_get, + 0, + Field_fld_ivp_sem_multiply_vr_Slot_f11_s2_mul_get, + Field_fld_ivp_sem_multiply_vs_Slot_f11_s2_mul_get, + Field_fld_ivp_sem_multiply_wvt_Slot_f11_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f11_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f11_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f11_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f11_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_arr_Slot_f11_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s2_mul_11_8_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_13_12_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_13_7_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_22_0_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_22_13_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_22_15_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_22_8_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_7_4_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_7_5_Slot_f11_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f11_s2_mul_set_field_fns[] = { + Field_t_Slot_f11_s2_mul_set, + 0, + 0, + 0, + Field_imm8_Slot_f11_s2_mul_set, + Field_s_Slot_f11_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f11_s2_mul_set, + 0, + 0, + 0, + Field_sal_Slot_f11_s2_mul_set, + Field_sargt_Slot_f11_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s2_mul_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_vr_Slot_f11_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f11_s2_mul_set, + 0, + Field_fld_ivp_sem_multiply_vr_Slot_f11_s2_mul_set, + Field_fld_ivp_sem_multiply_vs_Slot_f11_s2_mul_set, + Field_fld_ivp_sem_multiply_wvt_Slot_f11_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f11_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f11_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f11_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f11_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_arr_Slot_f11_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s2_mul_11_8_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_13_12_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_13_7_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_22_0_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_22_13_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_22_15_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_22_8_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_7_4_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_7_5_Slot_f11_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f11_s3_alu_get_field_fns[] = { + Field_t_Slot_f11_s3_alu_get, + 0, + 0, + 0, + Field_imm8_Slot_f11_s3_alu_get, + Field_s_Slot_f11_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f11_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f11_s3_alu_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f11_s3_alu_get, + 0, + 0, + Field_fld_saimm4_Slot_f11_s3_alu_get, + Field_fld_saimm5_Slot_f11_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f11_s3_alu_get, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f11_s3_alu_get, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f11_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_rep_arr_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_select_isel_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f11_s3_alu_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_select_vr_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_select_vs_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_select_vt_Slot_f11_s3_alu_get, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_f11_s3_alu_get, + Field_fld_saimm6_31_Slot_f11_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_14_13_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_14_8_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_1_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_11_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_14_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_16_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_17_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_22_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_8_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_9_9_Slot_f11_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f11_s3_alu_set_field_fns[] = { + Field_t_Slot_f11_s3_alu_set, + 0, + 0, + 0, + Field_imm8_Slot_f11_s3_alu_set, + Field_s_Slot_f11_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f11_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f11_s3_alu_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f11_s3_alu_set, + 0, + 0, + Field_fld_saimm4_Slot_f11_s3_alu_set, + Field_fld_saimm5_Slot_f11_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f11_s3_alu_set, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f11_s3_alu_set, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f11_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_rep_arr_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_select_isel_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f11_s3_alu_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_select_vr_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_select_vs_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_select_vt_Slot_f11_s3_alu_set, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_f11_s3_alu_set, + Field_fld_saimm6_31_Slot_f11_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_14_13_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_14_8_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_1_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_11_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_14_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_16_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_17_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_22_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_8_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_9_9_Slot_f11_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f11_s4_alu_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s4_alu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f11_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s4_alu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s4_alu_24_0_Slot_f11_s4_alu_get, + Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get, + Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get, + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_mtk_andpopc_c_Slot_f11_s4_alu_get, + Field_fld_mtk_andpopc_inb_Slot_f11_s4_alu_get, + Field_fld_mtk_andpopc_ina_Slot_f11_s4_alu_get, + Field_fld_mtk_andpopc_odata_Slot_f11_s4_alu_get, + Field_fld_f11_s4_alu_24_16_Slot_f11_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f11_s4_alu_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s4_alu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f11_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s4_alu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s4_alu_24_0_Slot_f11_s4_alu_set, + Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_set, + Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_set, + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_mtk_andpopc_c_Slot_f11_s4_alu_set, + Field_fld_mtk_andpopc_inb_Slot_f11_s4_alu_set, + Field_fld_mtk_andpopc_ina_Slot_f11_s4_alu_set, + Field_fld_mtk_andpopc_odata_Slot_f11_s4_alu_set, + Field_fld_f11_s4_alu_24_16_Slot_f11_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_n1_s0_ldst_get_field_fns[] = { + Field_t_Slot_n1_s0_ldst_get, + 0, + 0, + 0, + Field_imm8_Slot_n1_s0_ldst_get, + Field_s_Slot_n1_s0_ldst_get, + Field_imm12b_Slot_n1_s0_ldst_get, + Field_imm16_Slot_n1_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_n1_s0_ldst_get, + Field_r_Slot_n1_s0_ldst_get, + 0, + 0, + Field_sae_Slot_n1_s0_ldst_get, + Field_sal_Slot_n1_s0_ldst_get, + Field_sargt_Slot_n1_s0_ldst_get, + 0, + Field_sas_Slot_n1_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n1_s0_ldst_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n1_s0_ldst_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n1_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uul_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uus_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_valignr_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vbre_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vr_Slot_n1_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_n1_s0_ldst_get, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_n1_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_n1_s0_ldst_get, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n1_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n1_s0_ldst_12_0_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_12_2_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_12_4_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_12_8_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_15_15_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_1_0_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_2_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_20_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_4_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_8_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_9_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_3_0_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_7_2_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_7_5_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_7_6_Slot_n1_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_n1_s0_ldst_set_field_fns[] = { + Field_t_Slot_n1_s0_ldst_set, + 0, + 0, + 0, + Field_imm8_Slot_n1_s0_ldst_set, + Field_s_Slot_n1_s0_ldst_set, + Field_imm12b_Slot_n1_s0_ldst_set, + Field_imm16_Slot_n1_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_n1_s0_ldst_set, + Field_r_Slot_n1_s0_ldst_set, + 0, + 0, + Field_sae_Slot_n1_s0_ldst_set, + Field_sal_Slot_n1_s0_ldst_set, + Field_sargt_Slot_n1_s0_ldst_set, + 0, + Field_sas_Slot_n1_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n1_s0_ldst_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n1_s0_ldst_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n1_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uul_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uus_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_valignr_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vbre_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vr_Slot_n1_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_n1_s0_ldst_set, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_n1_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_n1_s0_ldst_set, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n1_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n1_s0_ldst_12_0_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_12_2_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_12_4_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_12_8_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_15_15_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_1_0_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_2_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_20_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_4_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_8_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_9_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_3_0_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_7_2_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_7_5_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_7_6_Slot_n1_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_n1_s1_none_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 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+ 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n1_s1_none_3_0_Slot_n1_s1_none_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_n1_s1_none_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n1_s1_none_3_0_Slot_n1_s1_none_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_n1_s2_mul_get_field_fns[] = { + Field_t_Slot_n1_s2_mul_get, + 0, + 0, + 0, + Field_imm8_Slot_n1_s2_mul_get, + Field_s_Slot_n1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_n1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_n1_s2_mul_get, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_vr_Slot_n1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_multiply_vp_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_multiply_vr_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_multiply_vs_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_multiply_wvt_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vbt_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_n1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_arr_Slot_n1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_fma_vbr_Slot_n1_s2_mul_get, + Field_fld_fp_sem_hp_fma_vr_Slot_n1_s2_mul_get, + Field_fld_fp_sem_hp_fma_vs_Slot_n1_s2_mul_get, + Field_fld_fp_sem_hp_fma_vt_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_multiply_vt_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_spfma_vbr_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_spfma_vr_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_spfma_vs_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_spfma_vt_Slot_n1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n1_s2_mul_0_0_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_13_9_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_18_6_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_18_9_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_25_1_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_7_4_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_8_4_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_8_8_Slot_n1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_n1_s2_mul_set_field_fns[] = { + Field_t_Slot_n1_s2_mul_set, + 0, + 0, + 0, + Field_imm8_Slot_n1_s2_mul_set, + Field_s_Slot_n1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_n1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_n1_s2_mul_set, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_vr_Slot_n1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_multiply_vp_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_multiply_vr_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_multiply_vs_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_multiply_wvt_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vbt_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_n1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_arr_Slot_n1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_fma_vbr_Slot_n1_s2_mul_set, + Field_fld_fp_sem_hp_fma_vr_Slot_n1_s2_mul_set, + Field_fld_fp_sem_hp_fma_vs_Slot_n1_s2_mul_set, + Field_fld_fp_sem_hp_fma_vt_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_multiply_vt_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_spfma_vbr_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_spfma_vr_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_spfma_vs_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_spfma_vt_Slot_n1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n1_s2_mul_0_0_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_13_9_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_18_6_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_18_9_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_25_1_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_7_4_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_8_4_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_8_8_Slot_n1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_n2_s0_ldst_get_field_fns[] = { + Field_t_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + Field_imm8_Slot_n2_s0_ldst_get, + Field_s_Slot_n2_s0_ldst_get, + Field_imm12b_Slot_n2_s0_ldst_get, + Field_imm16_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_n2_s0_ldst_get, + Field_r_Slot_n2_s0_ldst_get, + 0, + 0, + Field_sae_Slot_n2_s0_ldst_get, + Field_sal_Slot_n2_s0_ldst_get, + Field_sargt_Slot_n2_s0_ldst_get, + 0, + Field_sas_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n2_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uul_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uus_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_valignr_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vbre_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vr_Slot_n2_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_n2_s0_ldst_get, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_n2_s0_ldst_get, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_selimm_s0_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vr_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n2_s0_ldst_12_0_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_12_11_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_12_4_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_12_8_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_13_11_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_15_15_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_10_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_11_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_14_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_20_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_5_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_8_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_3_0_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_4_0_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_4_4_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_7_6_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_8_0_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_8_4_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_9_5_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_9_6_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_n2_s0_ldst_set_field_fns[] = { + Field_t_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + Field_imm8_Slot_n2_s0_ldst_set, + Field_s_Slot_n2_s0_ldst_set, + Field_imm12b_Slot_n2_s0_ldst_set, + Field_imm16_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_n2_s0_ldst_set, + Field_r_Slot_n2_s0_ldst_set, + 0, + 0, + Field_sae_Slot_n2_s0_ldst_set, + Field_sal_Slot_n2_s0_ldst_set, + Field_sargt_Slot_n2_s0_ldst_set, + 0, + Field_sas_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n2_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uul_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uus_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_valignr_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vbre_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vr_Slot_n2_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_n2_s0_ldst_set, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_n2_s0_ldst_set, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_selimm_s0_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vr_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n2_s0_ldst_12_0_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_12_11_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_12_4_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_12_8_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_13_11_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_15_15_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_10_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_11_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_14_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_20_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_5_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_8_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_3_0_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_4_0_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_4_4_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_7_6_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_8_0_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_8_4_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_9_5_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_9_6_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_n2_s1_ld_get_field_fns[] = { + Field_t_Slot_n2_s1_ld_get, + 0, + 0, + 0, + Field_imm8_Slot_n2_s1_ld_get, + Field_s_Slot_n2_s1_ld_get, + Field_imm12b_Slot_n2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_n2_s1_ld_get, + Field_r_Slot_n2_s1_ld_get, + 0, + 0, + Field_sae_Slot_n2_s1_ld_get, + Field_sal_Slot_n2_s1_ld_get, + Field_sargt_Slot_n2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n2_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n2_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_ld_st_uul_Slot_n2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_n2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_n2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_n2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_n2_s1_ld_get, + Field_fld_bbe_ltrxn_2imm_Slot_n2_s1_ld_get, + Field_fld_bbe_ltrxnimm_Slot_n2_s1_ld_get, + Field_fld_imm1_2n_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_sqz_vbr_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_sqz_vt_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_arr_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_n2_s1_ld_get, + 0, + Field_fld_ivp_sem_vec_mov_vt_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_wvr_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_arr_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_vt_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_n2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n2_s1_ld_12_10_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_12_2_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_12_4_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_12_8_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_1_0_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_10_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_2_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_9_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_7_0_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_7_6_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_7_7_Slot_n2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_n2_s1_ld_set_field_fns[] = { + Field_t_Slot_n2_s1_ld_set, + 0, + 0, + 0, + Field_imm8_Slot_n2_s1_ld_set, + Field_s_Slot_n2_s1_ld_set, + Field_imm12b_Slot_n2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_n2_s1_ld_set, + Field_r_Slot_n2_s1_ld_set, + 0, + 0, + Field_sae_Slot_n2_s1_ld_set, + Field_sal_Slot_n2_s1_ld_set, + Field_sargt_Slot_n2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n2_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n2_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_ld_st_uul_Slot_n2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_n2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_n2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_n2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_n2_s1_ld_set, + Field_fld_bbe_ltrxn_2imm_Slot_n2_s1_ld_set, + Field_fld_bbe_ltrxnimm_Slot_n2_s1_ld_set, + Field_fld_imm1_2n_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_sqz_vbr_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_sqz_vt_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_arr_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_n2_s1_ld_set, + 0, + Field_fld_ivp_sem_vec_mov_vt_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_wvr_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_arr_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_vt_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_n2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n2_s1_ld_12_10_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_12_2_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_12_4_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_12_8_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_1_0_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_10_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_2_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_9_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_7_0_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_7_6_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_7_7_Slot_n2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_n0_s0_ldst_get_field_fns[] = { + Field_t_Slot_n0_s0_ldst_get, + 0, + 0, + 0, + Field_imm8_Slot_n0_s0_ldst_get, + Field_s_Slot_n0_s0_ldst_get, + Field_imm12b_Slot_n0_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_n0_s0_ldst_get, + Field_r_Slot_n0_s0_ldst_get, + 0, + 0, + Field_sae_Slot_n0_s0_ldst_get, + Field_sal_Slot_n0_s0_ldst_get, + Field_sargt_Slot_n0_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_n0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n0_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n0_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n0_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n0_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n0_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uul_Slot_n0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uus_Slot_n0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_valignr_Slot_n0_s0_ldst_get, + 0, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_n0_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_n0_s0_ldst_get, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_n0_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_n0_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n0_s0_ldst_get, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n0_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n0_s0_ldst_12_0_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_12_12_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_12_2_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_12_4_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_12_8_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_22_0_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_22_16_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_3_0_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_7_5_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_7_6_Slot_n0_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_n0_s0_ldst_set_field_fns[] = { + Field_t_Slot_n0_s0_ldst_set, + 0, + 0, + 0, + Field_imm8_Slot_n0_s0_ldst_set, + Field_s_Slot_n0_s0_ldst_set, + Field_imm12b_Slot_n0_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_n0_s0_ldst_set, + Field_r_Slot_n0_s0_ldst_set, + 0, + 0, + Field_sae_Slot_n0_s0_ldst_set, + Field_sal_Slot_n0_s0_ldst_set, + Field_sargt_Slot_n0_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_n0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n0_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n0_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n0_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n0_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n0_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uul_Slot_n0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uus_Slot_n0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_valignr_Slot_n0_s0_ldst_set, + 0, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_n0_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_n0_s0_ldst_set, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_n0_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_n0_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n0_s0_ldst_set, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n0_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n0_s0_ldst_12_0_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_12_12_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_12_2_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_12_4_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_12_8_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_22_0_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_22_16_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_3_0_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_7_5_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_7_6_Slot_n0_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_n0_s1_none_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n0_s1_none_2_0_Slot_n0_s1_none_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_n0_s1_none_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 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0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_n0_s2_none_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n0_s2_none_2_0_Slot_n0_s2_none_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_n0_s3_alu_get_field_fns[] = { + Field_t_Slot_n0_s3_alu_get, + 0, + 0, + 0, + Field_imm8_Slot_n0_s3_alu_get, + Field_s_Slot_n0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_n0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_n0_s3_alu_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_n0_s3_alu_get, + 0, + 0, + Field_fld_saimm4_Slot_n0_s3_alu_get, + Field_fld_saimm5_Slot_n0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_n0_s3_alu_get, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_n0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_n0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_n0_s3_alu_get, + 0, + Field_fld_fp_sem_hp_cnv_vr_Slot_n0_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vs_Slot_n0_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vt_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vt_Slot_n0_s3_alu_get, + 0, + Field_fld_ivp_sem_spmisc_vr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_spmisc_vs_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_spmisc_vsm_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_spmisc_vt_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vt_Slot_n0_s3_alu_get, + 0, + Field_fld_ivp_sem_vec_select_isel_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_select_ishfl_Slot_n0_s3_alu_get, + 0, + 0, + Field_fld_ivp_sem_vec_select_sr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_select_vbr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_select_vr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_select_vs_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_select_vt_Slot_n0_s3_alu_get, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_n0_s3_alu_get, + Field_fld_saimm6_31_Slot_n0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n0_s3_alu_14_10_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_14_13_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_14_14_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_19_12_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_19_13_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_27_13_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_27_15_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_27_16_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_27_19_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_27_22_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_27_3_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_2_0_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_7_0_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_9_3_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_9_6_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_9_7_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_9_9_Slot_n0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_n0_s3_alu_set_field_fns[] = { + Field_t_Slot_n0_s3_alu_set, + 0, + 0, + 0, + Field_imm8_Slot_n0_s3_alu_set, + Field_s_Slot_n0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_n0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_n0_s3_alu_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_n0_s3_alu_set, + 0, + 0, + Field_fld_saimm4_Slot_n0_s3_alu_set, + Field_fld_saimm5_Slot_n0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_n0_s3_alu_set, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_n0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_n0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_n0_s3_alu_set, + 0, + Field_fld_fp_sem_hp_cnv_vr_Slot_n0_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vs_Slot_n0_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vt_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vt_Slot_n0_s3_alu_set, + 0, + Field_fld_ivp_sem_spmisc_vr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_spmisc_vs_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_spmisc_vsm_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_spmisc_vt_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vt_Slot_n0_s3_alu_set, + 0, + Field_fld_ivp_sem_vec_select_isel_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_select_ishfl_Slot_n0_s3_alu_set, + 0, + 0, + Field_fld_ivp_sem_vec_select_sr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_select_vbr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_select_vr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_select_vs_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_select_vt_Slot_n0_s3_alu_set, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_n0_s3_alu_set, + Field_fld_saimm6_31_Slot_n0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n0_s3_alu_14_10_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_14_13_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_14_14_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_19_12_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_19_13_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_27_13_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_27_15_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_27_16_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_27_19_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_27_22_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_27_3_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_2_0_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_7_0_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_9_3_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_9_6_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_9_7_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_9_9_Slot_n0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" }, + { "F0_S0_LdSt", "F0", 0, + Slot_f0_Format_f0_s0_ldst_8_get, Slot_f0_Format_f0_s0_ldst_8_set, + Slot_f0_s0_ldst_get_field_fns, Slot_f0_s0_ldst_set_field_fns, + Slot_f0_s0_ldst_decode, "nop" }, + { "F0_S1_Ld", "F0", 1, + Slot_f0_Format_f0_s1_ld_5_get, Slot_f0_Format_f0_s1_ld_5_set, + Slot_f0_s1_ld_get_field_fns, Slot_f0_s1_ld_set_field_fns, + Slot_f0_s1_ld_decode, "nop" }, + { "F0_S2_Mul", "F0", 2, + Slot_f0_Format_f0_s2_mul_4_get, Slot_f0_Format_f0_s2_mul_4_set, + Slot_f0_s2_mul_get_field_fns, Slot_f0_s2_mul_set_field_fns, + Slot_f0_s2_mul_decode, "nop" }, + { "F0_S3_ALU", "F0", 3, + Slot_f0_Format_f0_s3_alu_35_get, Slot_f0_Format_f0_s3_alu_35_set, + Slot_f0_s3_alu_get_field_fns, Slot_f0_s3_alu_set_field_fns, + Slot_f0_s3_alu_decode, "nop" }, + { "F1_S0_LdStALU", "F1", 0, + Slot_f1_Format_f1_s0_ldstalu_8_get, Slot_f1_Format_f1_s0_ldstalu_8_set, + Slot_f1_s0_ldstalu_get_field_fns, Slot_f1_s0_ldstalu_set_field_fns, + Slot_f1_s0_ldstalu_decode, "nop" }, + { "F1_S1_Ld", "F1", 1, + Slot_f1_Format_f1_s1_ld_5_get, Slot_f1_Format_f1_s1_ld_5_set, + Slot_f1_s1_ld_get_field_fns, Slot_f1_s1_ld_set_field_fns, + Slot_f1_s1_ld_decode, "nop" }, + { "F1_S2_Mul", "F1", 2, + Slot_f1_Format_f1_s2_mul_4_get, Slot_f1_Format_f1_s2_mul_4_set, + Slot_f1_s2_mul_get_field_fns, Slot_f1_s2_mul_set_field_fns, + Slot_f1_s2_mul_decode, "nop" }, + { "F1_S3_ALU", "F1", 3, + Slot_f1_Format_f1_s3_alu_26_get, Slot_f1_Format_f1_s3_alu_26_set, + Slot_f1_s3_alu_get_field_fns, Slot_f1_s3_alu_set_field_fns, + Slot_f1_s3_alu_decode, "nop" }, + { "F2_S0_LdSt", "F2", 0, + Slot_f2_Format_f2_s0_ldst_8_get, Slot_f2_Format_f2_s0_ldst_8_set, + Slot_f2_s0_ldst_get_field_fns, Slot_f2_s0_ldst_set_field_fns, + Slot_f2_s0_ldst_decode, "nop" }, + { "F2_S1_Ld", "F2", 1, + Slot_f2_Format_f2_s1_ld_5_get, Slot_f2_Format_f2_s1_ld_5_set, + Slot_f2_s1_ld_get_field_fns, Slot_f2_s1_ld_set_field_fns, + Slot_f2_s1_ld_decode, "nop" }, + { "F2_S2_Mul", "F2", 2, + Slot_f2_Format_f2_s2_mul_4_get, Slot_f2_Format_f2_s2_mul_4_set, + Slot_f2_s2_mul_get_field_fns, Slot_f2_s2_mul_set_field_fns, + Slot_f2_s2_mul_decode, "nop" }, + { "F2_S3_ALU", "F2", 3, + Slot_f2_Format_f2_s3_alu_21_get, Slot_f2_Format_f2_s3_alu_21_set, + Slot_f2_s3_alu_get_field_fns, Slot_f2_s3_alu_set_field_fns, + Slot_f2_s3_alu_decode, "nop" }, + { "F3_S0_LdSt", "F3", 0, + Slot_f3_Format_f3_s0_ldst_8_get, Slot_f3_Format_f3_s0_ldst_8_set, + Slot_f3_s0_ldst_get_field_fns, Slot_f3_s0_ldst_set_field_fns, + Slot_f3_s0_ldst_decode, "nop" }, + { "F3_S1_Ld", "F3", 1, + Slot_f3_Format_f3_s1_ld_5_get, Slot_f3_Format_f3_s1_ld_5_set, + Slot_f3_s1_ld_get_field_fns, Slot_f3_s1_ld_set_field_fns, + Slot_f3_s1_ld_decode, "nop" }, + { "F3_S2_Mul", "F3", 2, + Slot_f3_Format_f3_s2_mul_4_get, Slot_f3_Format_f3_s2_mul_4_set, + Slot_f3_s2_mul_get_field_fns, Slot_f3_s2_mul_set_field_fns, + Slot_f3_s2_mul_decode, "nop" }, + { "F3_S3_ALU", "F3", 3, + Slot_f3_Format_f3_s3_alu_34_get, Slot_f3_Format_f3_s3_alu_34_set, + Slot_f3_s3_alu_get_field_fns, Slot_f3_s3_alu_set_field_fns, + Slot_f3_s3_alu_decode, "nop" }, + { "F3_S4_ALU", "F3", 4, + Slot_f3_Format_f3_s4_alu_70_get, Slot_f3_Format_f3_s4_alu_70_set, + Slot_f3_s4_alu_get_field_fns, Slot_f3_s4_alu_set_field_fns, + Slot_f3_s4_alu_decode, "nop" }, + { "F4_S0_Ld", "F4", 0, + Slot_f4_Format_f4_s0_ld_8_get, Slot_f4_Format_f4_s0_ld_8_set, + Slot_f4_s0_ld_get_field_fns, Slot_f4_s0_ld_set_field_fns, + Slot_f4_s0_ld_decode, "nop" }, + { "F4_S1_Ld", "F4", 1, + Slot_f4_Format_f4_s1_ld_5_get, Slot_f4_Format_f4_s1_ld_5_set, + Slot_f4_s1_ld_get_field_fns, Slot_f4_s1_ld_set_field_fns, + Slot_f4_s1_ld_decode, "nop" }, + { "F4_S2_Mul", "F4", 2, + Slot_f4_Format_f4_s2_mul_4_get, Slot_f4_Format_f4_s2_mul_4_set, + Slot_f4_s2_mul_get_field_fns, Slot_f4_s2_mul_set_field_fns, + Slot_f4_s2_mul_decode, "nop" }, + { "F4_S3_ALU", "F4", 3, + Slot_f4_Format_f4_s3_alu_34_get, Slot_f4_Format_f4_s3_alu_34_set, + Slot_f4_s3_alu_get_field_fns, Slot_f4_s3_alu_set_field_fns, + Slot_f4_s3_alu_decode, "nop" }, + { "F5_S0_Base", "F5", 0, + Slot_f5_Format_f5_s0_base_8_get, Slot_f5_Format_f5_s0_base_8_set, + Slot_f5_s0_base_get_field_fns, Slot_f5_s0_base_set_field_fns, + Slot_f5_s0_base_decode, "nop" }, + { "F5_S1_Base", "F5", 1, + Slot_f5_Format_f5_s1_base_4_get, Slot_f5_Format_f5_s1_base_4_set, + Slot_f5_s1_base_get_field_fns, Slot_f5_s1_base_set_field_fns, + Slot_f5_s1_base_decode, "nop" }, + { "F5_S2_Base", "F5", 2, + Slot_f5_Format_f5_s2_base_5_get, Slot_f5_Format_f5_s2_base_5_set, + Slot_f5_s2_base_get_field_fns, Slot_f5_s2_base_set_field_fns, + Slot_f5_s2_base_decode, "nop" }, + { "F5_S3_Base", "F5", 3, + Slot_f5_Format_f5_s3_base_35_get, Slot_f5_Format_f5_s3_base_35_set, + Slot_f5_s3_base_get_field_fns, Slot_f5_s3_base_set_field_fns, + Slot_f5_s3_base_decode, "nop" }, + { "F11_S0_Ld", "F11", 0, + Slot_f11_Format_f11_s0_ld_8_get, Slot_f11_Format_f11_s0_ld_8_set, + Slot_f11_s0_ld_get_field_fns, Slot_f11_s0_ld_set_field_fns, + Slot_f11_s0_ld_decode, "nop" }, + { "F11_S1_ALU", "F11", 1, + Slot_f11_Format_f11_s1_alu_5_get, Slot_f11_Format_f11_s1_alu_5_set, + Slot_f11_s1_alu_get_field_fns, Slot_f11_s1_alu_set_field_fns, + Slot_f11_s1_alu_decode, "nop" }, + { "F11_S2_Mul", "F11", 2, + Slot_f11_Format_f11_s2_mul_4_get, Slot_f11_Format_f11_s2_mul_4_set, + Slot_f11_s2_mul_get_field_fns, Slot_f11_s2_mul_set_field_fns, + Slot_f11_s2_mul_decode, "nop" }, + { "F11_S3_ALU", "F11", 3, + Slot_f11_Format_f11_s3_alu_35_get, Slot_f11_Format_f11_s3_alu_35_set, + Slot_f11_s3_alu_get_field_fns, Slot_f11_s3_alu_set_field_fns, + Slot_f11_s3_alu_decode, "nop" }, + { "F11_S4_ALU", "F11", 4, + Slot_f11_Format_f11_s4_alu_56_get, Slot_f11_Format_f11_s4_alu_56_set, + Slot_f11_s4_alu_get_field_fns, Slot_f11_s4_alu_set_field_fns, + Slot_f11_s4_alu_decode, "nop" }, + { "N1_S0_LdSt", "N1", 0, + Slot_n1_Format_n1_s0_ldst_8_get, Slot_n1_Format_n1_s0_ldst_8_set, + Slot_n1_s0_ldst_get_field_fns, Slot_n1_s0_ldst_set_field_fns, + Slot_n1_s0_ldst_decode, "nop" }, + { "N1_S1_None", "N1", 1, + Slot_n1_Format_n1_s1_none_50_get, Slot_n1_Format_n1_s1_none_50_set, + Slot_n1_s1_none_get_field_fns, Slot_n1_s1_none_set_field_fns, + Slot_n1_s1_none_decode, "nop" }, + { "N1_S2_Mul", "N1", 2, + Slot_n1_Format_n1_s2_mul_5_get, Slot_n1_Format_n1_s2_mul_5_set, + Slot_n1_s2_mul_get_field_fns, Slot_n1_s2_mul_set_field_fns, + Slot_n1_s2_mul_decode, "nop" }, + { "N2_S0_LdSt", "N2", 0, + Slot_n2_Format_n2_s0_ldst_8_get, Slot_n2_Format_n2_s0_ldst_8_set, + Slot_n2_s0_ldst_get_field_fns, Slot_n2_s0_ldst_set_field_fns, + Slot_n2_s0_ldst_decode, "nop" }, + { "N2_S1_Ld", "N2", 1, + Slot_n2_Format_n2_s1_ld_5_get, Slot_n2_Format_n2_s1_ld_5_set, + Slot_n2_s1_ld_get_field_fns, Slot_n2_s1_ld_set_field_fns, + Slot_n2_s1_ld_decode, "nop" }, + { "N0_S0_LdSt", "N0", 0, + Slot_n0_Format_n0_s0_ldst_8_get, Slot_n0_Format_n0_s0_ldst_8_set, + Slot_n0_s0_ldst_get_field_fns, Slot_n0_s0_ldst_set_field_fns, + Slot_n0_s0_ldst_decode, "nop" }, + { "N0_S1_None", "N0", 1, + Slot_n0_Format_n0_s1_none_49_get, Slot_n0_Format_n0_s1_none_49_set, + Slot_n0_s1_none_get_field_fns, Slot_n0_s1_none_set_field_fns, + Slot_n0_s1_none_decode, "nop" }, + { "N0_S2_None", "N0", 2, + Slot_n0_Format_n0_s2_none_50_get, Slot_n0_Format_n0_s2_none_50_set, + Slot_n0_s2_none_get_field_fns, Slot_n0_s2_none_set_field_fns, + Slot_n0_s2_none_decode, "nop" }, + { "N0_S3_ALU", "N0", 3, + Slot_n0_Format_n0_s3_alu_5_get, Slot_n0_Format_n0_s3_alu_5_set, + Slot_n0_s3_alu_get_field_fns, Slot_n0_s3_alu_set_field_fns, + Slot_n0_s3_alu_decode, "nop" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_F0_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0x2040000; +} + +static void +Format_F1_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0x2040800; +} + +static void +Format_F2_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0x2040820; +} + +static void +Format_F3_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_F4_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0x2000000; +} + +static void +Format_F5_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0x2040840; +} + +static void +Format_F11_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0x2020000; +} + +static void +Format_N1_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xf; + insn[1] = 0x400000; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_N2_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xf; + insn[1] = 0x800000; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_N0_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xf; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static int Format_F0_slots[] = { 5, 4, 3, 6 }; + +static int Format_F1_slots[] = { 9, 8, 7, 10 }; + +static int Format_F2_slots[] = { 13, 12, 11, 14 }; + +static int Format_F3_slots[] = { 17, 16, 15, 18, 19 }; + +static int Format_F4_slots[] = { 22, 21, 20, 23 }; + +static int Format_F5_slots[] = { 25, 26, 24, 27 }; + +static int Format_F11_slots[] = { 30, 29, 28, 31, 32 }; + +static int Format_N1_slots[] = { 35, 33, 34 }; + +static int Format_N2_slots[] = { 37, 36 }; + +static int Format_N0_slots[] = { 41, 38, 39, 40 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, + { "F0", 16, Format_F0_encode, 4, Format_F0_slots }, + { "F1", 16, Format_F1_encode, 4, Format_F1_slots }, + { "F2", 16, Format_F2_encode, 4, Format_F2_slots }, + { "F3", 16, Format_F3_encode, 5, Format_F3_slots }, + { "F4", 16, Format_F4_encode, 4, Format_F4_slots }, + { "F5", 16, Format_F5_encode, 4, Format_F5_slots }, + { "F11", 16, Format_F11_encode, 5, Format_F11_slots }, + { "N1", 8, Format_N1_encode, 3, Format_N1_slots }, + { "N2", 8, Format_N2_encode, 2, Format_N2_slots }, + { "N0", 8, Format_N0_encode, 4, Format_N0_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 1; /* x16a */ + if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 2; /* x16b */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0x2060800) == 0x2040000) + return 3; /* F0 */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0x2060860) == 0x2040800) + return 4; /* F1 */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0x2060860) == 0x2040820) + return 5; /* F2 */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0x2000000) == 0) + return 6; /* F3 */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0x2060000) == 0x2000000) + return 7; /* F4 */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0x2060860) == 0x2040840) + return 8; /* F5 */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0x2060000) == 0x2020000) + return 9; /* F11 */ + if ((insn[0] & 0x1f) == 0xf && (insn[1] & 0xc00000) == 0x400000 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 10; /* N1 */ + if ((insn[0] & 0x1f) == 0xf && (insn[1] & 0xc00000) == 0x800000 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 11; /* N2 */ + if ((insn[0] & 0x1f) == 0xf && (insn[1] & 0xc00000) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 12; /* N0 */ + return -1; +} + +static int length_table[256] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + -1 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int l = insn[0]; + return length_table[l]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, + 16 /* insn_size */, 0, + 13, formats, format_decoder, length_decoder, + 42, slots, + 955 /* num_fields */, + 1145, operands, + 930, iclasses, + 1015, opcodes, 0, + 11, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 13, interfaces, 0, + 0, funcUnits, 0 +}; diff --git a/overlays/xtensa_mtk_mvpu6_0226/binutils/include/xtensa-config.h b/overlays/xtensa_mtk_mvpu6_0226/binutils/include/xtensa-config.h new file mode 100644 index 00000000..0bfb2b65 --- /dev/null +++ b/overlays/xtensa_mtk_mvpu6_0226/binutils/include/xtensa-config.h @@ -0,0 +1,189 @@ +/* Xtensa configuration settings. + Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 + Free Software Foundation, Inc. + Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +/* The macros defined here match those with the same names in the Xtensa + compile-time HAL (Hardware Abstraction Layer). Please refer to the + Xtensa System Software Reference Manual for documentation of these + macros. */ + +#undef XCHAL_HAVE_BE +#define XCHAL_HAVE_BE 0 + +#undef XCHAL_HAVE_DENSITY +#define XCHAL_HAVE_DENSITY 1 + +#undef XCHAL_HAVE_CONST16 +#define XCHAL_HAVE_CONST16 1 + +#undef XCHAL_HAVE_ABS +#define XCHAL_HAVE_ABS 1 + +#undef XCHAL_HAVE_ADDX +#define XCHAL_HAVE_ADDX 1 + +#undef XCHAL_HAVE_L32R +#define XCHAL_HAVE_L32R 1 + +#undef XSHAL_USE_ABSOLUTE_LITERALS +#define XSHAL_USE_ABSOLUTE_LITERALS 0 + +#undef XSHAL_HAVE_TEXT_SECTION_LITERALS +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#undef XCHAL_HAVE_MAC16 +#define XCHAL_HAVE_MAC16 0 + +#undef XCHAL_HAVE_MUL16 +#define XCHAL_HAVE_MUL16 1 + +#undef XCHAL_HAVE_MUL32 +#define XCHAL_HAVE_MUL32 1 + +#undef XCHAL_HAVE_MUL32_HIGH +#define XCHAL_HAVE_MUL32_HIGH 1 + +#undef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 1 + +#undef XCHAL_HAVE_NSA +#define XCHAL_HAVE_NSA 1 + +#undef XCHAL_HAVE_MINMAX +#define XCHAL_HAVE_MINMAX 1 + +#undef XCHAL_HAVE_SEXT +#define XCHAL_HAVE_SEXT 1 + +#undef XCHAL_HAVE_LOOPS +#define XCHAL_HAVE_LOOPS 1 + +#undef XCHAL_HAVE_THREADPTR +#define XCHAL_HAVE_THREADPTR 1 + +#undef XCHAL_HAVE_RELEASE_SYNC +#define XCHAL_HAVE_RELEASE_SYNC 1 + +#undef XCHAL_HAVE_S32C1I +#define XCHAL_HAVE_S32C1I 0 + +#undef XCHAL_HAVE_BOOLEANS +#define XCHAL_HAVE_BOOLEANS 1 + +#undef XCHAL_HAVE_FP +#define XCHAL_HAVE_FP 0 + +#undef XCHAL_HAVE_FP_DIV +#define XCHAL_HAVE_FP_DIV 0 + +#undef XCHAL_HAVE_FP_RECIP +#define XCHAL_HAVE_FP_RECIP 0 + +#undef XCHAL_HAVE_FP_SQRT +#define XCHAL_HAVE_FP_SQRT 0 + +#undef XCHAL_HAVE_FP_RSQRT +#define XCHAL_HAVE_FP_RSQRT 0 + +#undef XCHAL_HAVE_DFP_ACCEL +#define XCHAL_HAVE_DFP_ACCEL 0 +/* For backward compatibility */ +#undef XCHAL_HAVE_DFP_accel +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL + +#undef XCHAL_HAVE_WINDOWED +#define XCHAL_HAVE_WINDOWED 1 + +#undef XCHAL_NUM_AREGS +#define XCHAL_NUM_AREGS 32 + +#undef XCHAL_HAVE_WIDE_BRANCHES +#define XCHAL_HAVE_WIDE_BRANCHES 0 + +#undef XCHAL_HAVE_PREDICTED_BRANCHES +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 + + +#undef XCHAL_ICACHE_SIZE +#define XCHAL_ICACHE_SIZE 131072 + +#undef XCHAL_DCACHE_SIZE +#define XCHAL_DCACHE_SIZE 0 + +#undef XCHAL_ICACHE_LINESIZE +#define XCHAL_ICACHE_LINESIZE 128 + +#undef XCHAL_DCACHE_LINESIZE +#define XCHAL_DCACHE_LINESIZE 16 + +#undef XCHAL_ICACHE_LINEWIDTH +#define XCHAL_ICACHE_LINEWIDTH 7 + +#undef XCHAL_DCACHE_LINEWIDTH +#define XCHAL_DCACHE_LINEWIDTH 4 + +#undef XCHAL_DCACHE_IS_WRITEBACK +#define XCHAL_DCACHE_IS_WRITEBACK 0 + + +#undef XCHAL_HAVE_MMU +#define XCHAL_HAVE_MMU 0 + + +#undef XCHAL_HAVE_DEBUG +#define XCHAL_HAVE_DEBUG 1 + +#undef XCHAL_NUM_IBREAK +#define XCHAL_NUM_IBREAK 1 + +#undef XCHAL_NUM_DBREAK +#define XCHAL_NUM_DBREAK 1 + +#undef XCHAL_DEBUGLEVEL +#define XCHAL_DEBUGLEVEL 3 + + +#undef XCHAL_MAX_INSTRUCTION_SIZE +#define XCHAL_MAX_INSTRUCTION_SIZE 16 + +#undef XCHAL_INST_FETCH_WIDTH +#define XCHAL_INST_FETCH_WIDTH 16 + + +#undef XSHAL_ABI +#undef XTHAL_ABI_WINDOWED +#undef XTHAL_ABI_CALL0 +#define XSHAL_ABI XTHAL_ABI_WINDOWED +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 + + +#undef XCHAL_M_STAGE +#define XCHAL_M_STAGE 3 + +#undef XTENSA_MARCH_LATEST +#define XTENSA_MARCH_LATEST 270008 + +#undef XTENSA_MARCH_EARLIEST +#define XTENSA_MARCH_EARLIEST 270008 + + +#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_mtk_mvpu6_0226/gcc/include/xtensa-config.h b/overlays/xtensa_mtk_mvpu6_0226/gcc/include/xtensa-config.h new file mode 100644 index 00000000..0bfb2b65 --- /dev/null +++ b/overlays/xtensa_mtk_mvpu6_0226/gcc/include/xtensa-config.h @@ -0,0 +1,189 @@ +/* Xtensa configuration settings. + Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 + Free Software Foundation, Inc. + Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +/* The macros defined here match those with the same names in the Xtensa + compile-time HAL (Hardware Abstraction Layer). Please refer to the + Xtensa System Software Reference Manual for documentation of these + macros. */ + +#undef XCHAL_HAVE_BE +#define XCHAL_HAVE_BE 0 + +#undef XCHAL_HAVE_DENSITY +#define XCHAL_HAVE_DENSITY 1 + +#undef XCHAL_HAVE_CONST16 +#define XCHAL_HAVE_CONST16 1 + +#undef XCHAL_HAVE_ABS +#define XCHAL_HAVE_ABS 1 + +#undef XCHAL_HAVE_ADDX +#define XCHAL_HAVE_ADDX 1 + +#undef XCHAL_HAVE_L32R +#define XCHAL_HAVE_L32R 1 + +#undef XSHAL_USE_ABSOLUTE_LITERALS +#define XSHAL_USE_ABSOLUTE_LITERALS 0 + +#undef XSHAL_HAVE_TEXT_SECTION_LITERALS +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#undef XCHAL_HAVE_MAC16 +#define XCHAL_HAVE_MAC16 0 + +#undef XCHAL_HAVE_MUL16 +#define XCHAL_HAVE_MUL16 1 + +#undef XCHAL_HAVE_MUL32 +#define XCHAL_HAVE_MUL32 1 + +#undef XCHAL_HAVE_MUL32_HIGH +#define XCHAL_HAVE_MUL32_HIGH 1 + +#undef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 1 + +#undef XCHAL_HAVE_NSA +#define XCHAL_HAVE_NSA 1 + +#undef XCHAL_HAVE_MINMAX +#define XCHAL_HAVE_MINMAX 1 + +#undef XCHAL_HAVE_SEXT +#define XCHAL_HAVE_SEXT 1 + +#undef XCHAL_HAVE_LOOPS +#define XCHAL_HAVE_LOOPS 1 + +#undef XCHAL_HAVE_THREADPTR +#define XCHAL_HAVE_THREADPTR 1 + +#undef XCHAL_HAVE_RELEASE_SYNC +#define XCHAL_HAVE_RELEASE_SYNC 1 + +#undef XCHAL_HAVE_S32C1I +#define XCHAL_HAVE_S32C1I 0 + +#undef XCHAL_HAVE_BOOLEANS +#define XCHAL_HAVE_BOOLEANS 1 + +#undef XCHAL_HAVE_FP +#define XCHAL_HAVE_FP 0 + +#undef XCHAL_HAVE_FP_DIV +#define XCHAL_HAVE_FP_DIV 0 + +#undef XCHAL_HAVE_FP_RECIP +#define XCHAL_HAVE_FP_RECIP 0 + +#undef XCHAL_HAVE_FP_SQRT +#define XCHAL_HAVE_FP_SQRT 0 + +#undef XCHAL_HAVE_FP_RSQRT +#define XCHAL_HAVE_FP_RSQRT 0 + +#undef XCHAL_HAVE_DFP_ACCEL +#define XCHAL_HAVE_DFP_ACCEL 0 +/* For backward compatibility */ +#undef XCHAL_HAVE_DFP_accel +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL + +#undef XCHAL_HAVE_WINDOWED +#define XCHAL_HAVE_WINDOWED 1 + +#undef XCHAL_NUM_AREGS +#define XCHAL_NUM_AREGS 32 + +#undef XCHAL_HAVE_WIDE_BRANCHES +#define XCHAL_HAVE_WIDE_BRANCHES 0 + +#undef XCHAL_HAVE_PREDICTED_BRANCHES +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 + + +#undef XCHAL_ICACHE_SIZE +#define XCHAL_ICACHE_SIZE 131072 + +#undef XCHAL_DCACHE_SIZE +#define XCHAL_DCACHE_SIZE 0 + +#undef XCHAL_ICACHE_LINESIZE +#define XCHAL_ICACHE_LINESIZE 128 + +#undef XCHAL_DCACHE_LINESIZE +#define XCHAL_DCACHE_LINESIZE 16 + +#undef XCHAL_ICACHE_LINEWIDTH +#define XCHAL_ICACHE_LINEWIDTH 7 + +#undef XCHAL_DCACHE_LINEWIDTH +#define XCHAL_DCACHE_LINEWIDTH 4 + +#undef XCHAL_DCACHE_IS_WRITEBACK +#define XCHAL_DCACHE_IS_WRITEBACK 0 + + +#undef XCHAL_HAVE_MMU +#define XCHAL_HAVE_MMU 0 + + +#undef XCHAL_HAVE_DEBUG +#define XCHAL_HAVE_DEBUG 1 + +#undef XCHAL_NUM_IBREAK +#define XCHAL_NUM_IBREAK 1 + +#undef XCHAL_NUM_DBREAK +#define XCHAL_NUM_DBREAK 1 + +#undef XCHAL_DEBUGLEVEL +#define XCHAL_DEBUGLEVEL 3 + + +#undef XCHAL_MAX_INSTRUCTION_SIZE +#define XCHAL_MAX_INSTRUCTION_SIZE 16 + +#undef XCHAL_INST_FETCH_WIDTH +#define XCHAL_INST_FETCH_WIDTH 16 + + +#undef XSHAL_ABI +#undef XTHAL_ABI_WINDOWED +#undef XTHAL_ABI_CALL0 +#define XSHAL_ABI XTHAL_ABI_WINDOWED +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 + + +#undef XCHAL_M_STAGE +#define XCHAL_M_STAGE 3 + +#undef XTENSA_MARCH_LATEST +#define XTENSA_MARCH_LATEST 270008 + +#undef XTENSA_MARCH_EARLIEST +#define XTENSA_MARCH_EARLIEST 270008 + + +#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_mtk_mvpu6_0226/gdb/bfd/xtensa-modules.c b/overlays/xtensa_mtk_mvpu6_0226/gdb/bfd/xtensa-modules.c new file mode 100644 index 00000000..4ec19e71 --- /dev/null +++ b/overlays/xtensa_mtk_mvpu6_0226/gdb/bfd/xtensa-modules.c @@ -0,0 +1,211607 @@ +/* Xtensa configuration-specific ISA information. + + Copyright (c) 2003-2018 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "ansidecl.h" +#include +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "BR", 4, 0 }, + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "CONFIGID0", 176, 0 }, + { "CONFIGID1", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "GSERR", 116, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "MEMCTL", 97, 0 }, + { "SAR", 3, 0 }, + { "PS", 230, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "CACHEADRDIS", 98, 0 }, + { "MPUENB", 90, 0 }, + { "CPENABLE", 224, 0 }, + { "ATOMCTL", 99, 0 }, + { "THREADPTR", 231, 1 }, + { "APB_PIPE", 0, 1 } +}; + +#define NUM_SYSREGS 49 +#define MAX_SPECIAL_REG 241 +#define MAX_USER_REG 231 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "DDR", 32, 0 }, + { "INTERRUPT", 25, 0 }, + { "CCOUNT", 32, 0 }, + { "GSERR", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EPS2", 15, 0 }, + { "EPS3", 15, 0 }, + { "EPS4", 15, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSRING", 2, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 3, 0 }, + { "WindowStart", 8, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "MEMCTL", 24, 0 }, + { "SAR", 6, 0 }, + { "THREADPTR", 32, 0 }, + { "MPUNUMENTRIES", 6, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 25, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKC_SG0", 2, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKENABLE", 1, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "CACHEADRDIS", 8, 0 }, + { "MPUENB", 32, 0 }, + { "CPENABLE", 3, 0 }, + { "ATOMCTL", 9, 0 }, + { "ERI_RAW_INTERLOCK", 1, 0 }, + { "ERACCESS", 16, 0 }, + { "APB_PIPE", 1, 0 } +}; + +#define NUM_STATES 57 + +enum xtensa_state_id { + STATE_LCOUNT, + STATE_PC, + STATE_ICOUNT, + STATE_DDR, + STATE_INTERRUPT, + STATE_CCOUNT, + STATE_GSERR, + STATE_XTSYNC, + STATE_VECBASE, + STATE_EPC1, + STATE_EPC2, + STATE_EPC3, + STATE_EPC4, + STATE_EXCSAVE1, + STATE_EXCSAVE2, + STATE_EXCSAVE3, + STATE_EXCSAVE4, + STATE_EPS2, + STATE_EPS3, + STATE_EPS4, + STATE_EXCCAUSE, + STATE_PSINTLEVEL, + STATE_PSUM, + STATE_PSWOE, + STATE_PSRING, + STATE_PSEXCM, + STATE_DEPC, + STATE_EXCVADDR, + STATE_WindowBase, + STATE_WindowStart, + STATE_PSCALLINC, + STATE_PSOWB, + STATE_LBEG, + STATE_LEND, + STATE_MEMCTL, + STATE_SAR, + STATE_THREADPTR, + STATE_MPUNUMENTRIES, + STATE_InOCDMode, + STATE_INTENABLE, + STATE_DBREAKA0, + STATE_DBREAKC0, + STATE_DBREAKC_SG0, + STATE_IBREAKA0, + STATE_IBREAKENABLE, + STATE_ICOUNTLEVEL, + STATE_DEBUGCAUSE, + STATE_DBNUM, + STATE_CCOMPARE0, + STATE_CCOMPARE1, + STATE_CACHEADRDIS, + STATE_MPUENB, + STATE_CPENABLE, + STATE_ATOMCTL, + STATE_ERI_RAW_INTERLOCK, + STATE_ERACCESS, + STATE_APB_PIPE +}; + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_inst_23_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_fld_inst_23_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_inst_3_0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_inst_3_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_inst_23_16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fld_inst_23_16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_inst_11_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_inst_11_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_inst_23_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_inst_23_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s0_ldst_33_19_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 13) | (insn[0] >> 19); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_19_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfff80000) | (tie_t << 19); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 13); +} + +static unsigned +Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s0_ldst_33_20_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_20_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 12); +} + +static unsigned +Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 14); +} + +static unsigned +Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 16); +} + +static unsigned +Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_f0_s0_ldst_7_6_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_7_6_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 17); +} + +static unsigned +Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 19) | (insn[0] >> 13); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffffe000) | (tie_t << 13); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 19); +} + +static unsigned +Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 15) | (insn[0] >> 17); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfffe0000) | (tie_t << 17); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 15); +} + +static unsigned +Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 18); +} + +static unsigned +Field_fld_f0_s0_ldst_7_7_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_7_7_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f0_s0_ldst_15_15_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_15_15_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f0_s0_ldst_12_8_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_12_8_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s0_ldst_12_4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_12_4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s0_ldst_12_2_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_12_2_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f0_s0_ldst_12_0_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_12_0_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 23) | (insn[0] >> 9); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffe00) | (tie_t << 9); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 23); +} + +static unsigned +Field_fld_f0_s0_ldst_13_9_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_13_9_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_f0_s0_ldst_7_5_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_7_5_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f0_s0_ldst_33_11_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 21) | (insn[0] >> 11); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_11_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xfffff800) | (tie_t << 11); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 21); +} + +static unsigned +Field_fld_f0_s0_ldst_12_11_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_12_11_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_f0_s0_ldst_8_0_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_8_0_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 20); +} + +static unsigned +Field_fld_f0_s0_ldst_3_0_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_3_0_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s0_ldst_8_4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_8_4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s0_ldst_8_8_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_8_8_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 5) | (insn[0] >> 27); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 5); +} + +static unsigned +Field_fld_f0_s0_ldst_11_4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_11_4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s0_ldst_11_9_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_11_9_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 7) >> 23); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_f0_s1_ld_7_6_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_7_6_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_f0_s1_ld_24_17_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 7) >> 24); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_24_17_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 7) >> 20); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 7) >> 25); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f0_s1_ld_15_10_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 16) >> 26); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_15_10_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc00) | (tie_t << 10); +} + +static unsigned +Field_fld_f0_s1_ld_15_8_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_15_8_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s1_ld_15_4_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_15_4_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s1_ld_15_2_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 16) >> 18); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_15_2_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f0_s1_ld_7_7_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_7_7_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 7) >> 19); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f0_s1_ld_24_11_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 7) >> 18); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_24_11_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x1fff800) | (tie_t << 11); +} + +static unsigned +Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f0_s1_ld_7_5_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_7_5_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f0_s1_ld_15_15_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_15_15_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f0_s1_ld_15_14_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_15_14_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f0_s1_ld_24_0_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 7) >> 7); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_24_0_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s1_ld_24_14_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 7) >> 21); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_24_14_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f0_s1_ld_24_8_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 7) >> 15); + return tie_t; +} + +static void +Field_fld_f0_s1_ld_24_8_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 5) >> 19); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x7ffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 5) >> 26); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e00000) | (tie_t << 21); +} + +static unsigned +Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 13) >> 25); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f000) | (tie_t << 12); +} + +static unsigned +Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f0_s2_mul_13_12_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_13_12_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_f0_s2_mul_11_8_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_11_8_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s2_mul_4_4_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_4_4_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s2_mul_18_9_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 13) >> 22); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_18_9_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f0_s2_mul_7_4_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_7_4_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s2_mul_26_2_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_26_2_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f0_s2_mul_1_0_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_1_0_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s2_mul_26_13_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 5) >> 18); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_26_13_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f0_s2_mul_26_20_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25); + return tie_t; +} + +static void +Field_fld_f0_s2_mul_26_20_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f0_s3_alu_33_26_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 6) | (insn[0] >> 26); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_26_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 6); +} + +static unsigned +Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f0_s3_alu_33_27_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 5) | (insn[0] >> 27); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_27_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 5); +} + +static unsigned +Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 12); +} + +static unsigned +Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 4) | (insn[0] >> 28); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xf0000000) | (tie_t << 28); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 4); +} + +static unsigned +Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 7) >> 20); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f0_s3_alu_9_7_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_9_7_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 19) | (insn[0] >> 13); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffffe000) | (tie_t << 13); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 19); +} + +static unsigned +Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_f0_s3_alu_7_3_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_7_3_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f0_s3_alu_3_3_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_3_3_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_f0_s3_alu_3_2_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_3_2_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f0_s3_alu_14_11_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_14_11_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); +} + +static unsigned +Field_fld_f0_s3_alu_33_25_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_25_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 7); +} + +static unsigned +Field_fld_f0_s3_alu_7_7_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_7_7_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f0_s3_alu_14_14_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_14_14_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_f0_s3_alu_33_9_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 23) | (insn[0] >> 9); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_9_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffe00) | (tie_t << 9); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 23); +} + +static unsigned +Field_fld_f0_s3_alu_8_8_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_8_8_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_f0_s3_alu_33_18_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_18_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 14); +} + +static unsigned +Field_fld_f0_s3_alu_8_0_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_8_0_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_19_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 1) >> 20); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_19_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_20_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 1) >> 21); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_20_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 1) >> 19); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x7ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 1) >> 17); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f1_s0_ldstalu_7_5_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_7_5_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f1_s0_ldstalu_12_12_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_12_12_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 1) >> 16); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x7fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 1) >> 14); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x7fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 1) >> 18); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f1_s0_ldstalu_15_15_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_15_15_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f1_s0_ldstalu_12_8_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_12_8_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f1_s0_ldstalu_12_4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_12_4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f1_s0_ldstalu_12_2_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_12_2_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f1_s0_ldstalu_12_0_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_12_0_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 1) >> 10); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x7ffffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f1_s0_ldstalu_7_7_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_7_7_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 1) >> 13); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x7ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f1_s0_ldstalu_14_12_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_14_12_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_14_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 1) >> 15); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_14_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x7fffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f1_s0_ldstalu_14_14_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_14_14_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_6_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 1) >> 7); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_6_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f1_s0_ldstalu_5_0_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_5_0_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s0_ldstalu_3_0_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_3_0_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s0_ldstalu_5_4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_5_4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_f1_s0_ldstalu_30_8_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 1) >> 9); + return tie_t; +} + +static void +Field_fld_f1_s0_ldstalu_30_8_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 5) >> 21); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f1_s1_ld_12_10_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_12_10_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 5) >> 23); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 5) >> 18); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f1_s1_ld_12_9_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 19) >> 28); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_12_9_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e00) | (tie_t << 9); +} + +static unsigned +Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f1_s1_ld_3_0_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_3_0_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s1_ld_15_10_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 16) >> 26); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_15_10_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc00) | (tie_t << 10); +} + +static unsigned +Field_fld_f1_s1_ld_15_8_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_15_8_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f1_s1_ld_15_4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_15_4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f1_s1_ld_15_2_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 16) >> 18); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_15_2_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f1_s1_ld_7_7_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_7_7_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f1_s1_ld_7_6_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_7_6_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f1_s1_ld_26_11_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 5) >> 16); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_26_11_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x7fff800) | (tie_t << 11); +} + +static unsigned +Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f1_s1_ld_12_12_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_12_12_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_f1_s1_ld_7_5_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_7_5_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f1_s1_ld_15_14_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_15_14_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f1_s1_ld_26_2_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_26_2_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f1_s1_ld_1_0_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s1_ld_1_0_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 3) >> 18); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x1fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 3) >> 19); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 3) >> 21); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f1_s2_mul_13_5_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 18) >> 23); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_13_5_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f1_s2_mul_3_2_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_3_2_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s2_mul_4_4_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_4_4_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_f1_s2_mul_13_2_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 18) >> 20); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_13_2_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f1_s2_mul_28_20_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 3) >> 23); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_28_20_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f1_s2_mul_9_6_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_9_6_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 3) >> 15); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f1_s2_mul_28_4_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 3) >> 7); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_28_4_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 1) >> 24); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f800000) | (tie_t << 23); +} + +static unsigned +Field_fld_f1_s3_alu_9_2_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_9_2_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); +} + +static unsigned +Field_fld_f1_s3_alu_9_3_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_9_3_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); +} + +static unsigned +Field_fld_f1_s3_alu_9_1_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 22) >> 23); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_9_1_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe) | (tie_t << 1); +} + +static unsigned +Field_fld_f1_s3_alu_19_7_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_19_7_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7); +} + +static unsigned +Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f1_s3_alu_30_8_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 1) >> 9); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_30_8_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f1_s3_alu_19_14_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_19_14_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 1) >> 21); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_f1_s3_alu_14_14_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_14_14_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f1_s3_alu_14_10_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_14_10_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 1) >> 16); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x7fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f1_s3_alu_3_2_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_3_2_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f1_s3_alu_14_13_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_14_13_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_f1_s3_alu_9_7_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_9_7_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_f1_s3_alu_30_22_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 1) >> 23); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_30_22_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_f1_s3_alu_3_3_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_3_3_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_f1_s3_alu_30_17_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 1) >> 18); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_30_17_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f1_s3_alu_30_6_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 1) >> 7); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_30_6_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f1_s3_alu_5_0_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_5_0_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 3) >> 19); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f2_s0_ldst_12_10_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_12_10_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 3) >> 20); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 3) >> 16); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x1fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 3) >> 18); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x1fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 3) >> 21); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f2_s0_ldst_15_15_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_15_15_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f2_s0_ldst_12_4_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_12_4_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f2_s0_ldst_12_2_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_12_2_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f2_s0_ldst_12_0_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_12_0_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s0_ldst_28_14_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 3) >> 17); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_14_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f2_s0_ldst_7_2_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_7_2_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_f2_s0_ldst_28_4_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 3) >> 7); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_4_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 3) >> 15); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f2_s0_ldst_28_20_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 3) >> 23); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_20_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f2_s0_ldst_28_11_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 3) >> 14); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_11_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x1ffff800) | (tie_t << 11); +} + +static unsigned +Field_fld_f2_s0_ldst_28_8_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 3) >> 11); + return tie_t; +} + +static void +Field_fld_f2_s0_ldst_28_8_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x1fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 5) >> 21); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f2_s1_ld_12_10_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_12_10_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 5) >> 23); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 5) >> 18); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f2_s1_ld_12_9_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 19) >> 28); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_12_9_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e00) | (tie_t << 9); +} + +static unsigned +Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f2_s1_ld_3_0_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_3_0_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s1_ld_15_10_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 16) >> 26); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_15_10_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc00) | (tie_t << 10); +} + +static unsigned +Field_fld_f2_s1_ld_15_8_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_15_8_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f2_s1_ld_15_4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_15_4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f2_s1_ld_15_2_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 16) >> 18); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_15_2_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f2_s1_ld_7_7_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_7_7_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f2_s1_ld_7_6_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_7_6_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f2_s1_ld_26_11_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 5) >> 16); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_26_11_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x7fff800) | (tie_t << 11); +} + +static unsigned +Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f2_s1_ld_15_14_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_15_14_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f2_s1_ld_26_2_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_26_2_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f2_s1_ld_1_0_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s1_ld_1_0_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 1) >> 21); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f2_s2_mul_14_11_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_14_11_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); +} + +static unsigned +Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 1) >> 20); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 1) >> 16); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x7fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 1) >> 22); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe00000) | (tie_t << 21); +} + +static unsigned +Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s2_mul_19_10_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_19_10_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_f2_s2_mul_30_18_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 1) >> 19); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_30_18_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x7ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f2_s2_mul_14_5_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_14_5_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f2_s2_mul_19_7_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_19_7_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7); +} + +static unsigned +Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 1) >> 13); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x7ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f2_s2_mul_30_6_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 1) >> 7); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_30_6_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f2_s2_mul_5_0_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_5_0_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 1) >> 24); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f800000) | (tie_t << 23); +} + +static unsigned +Field_fld_f2_s3_alu_9_2_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_9_2_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); +} + +static unsigned +Field_fld_f2_s3_alu_9_3_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_9_3_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); +} + +static unsigned +Field_fld_f2_s3_alu_9_1_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 22) >> 23); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_9_1_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe) | (tie_t << 1); +} + +static unsigned +Field_fld_f2_s3_alu_19_7_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_19_7_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7); +} + +static unsigned +Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f2_s3_alu_30_8_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 1) >> 9); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_30_8_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f2_s3_alu_19_14_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_19_14_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 1) >> 21); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_f2_s3_alu_14_14_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_14_14_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f2_s3_alu_14_10_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_14_10_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 1) >> 16); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x7fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s3_alu_3_2_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_3_2_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f2_s3_alu_14_13_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_14_13_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_f2_s3_alu_9_7_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_9_7_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_f2_s3_alu_9_9_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_9_9_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_f2_s3_alu_30_22_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 1) >> 23); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_30_22_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_f2_s3_alu_3_3_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_3_3_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_f2_s3_alu_30_18_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 1) >> 19); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_30_18_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x7ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f2_s3_alu_30_6_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 1) >> 7); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_30_6_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f2_s3_alu_5_0_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_5_0_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s0_ldst_25_19_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 6) >> 25); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_19_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f80000) | (tie_t << 19); +} + +static unsigned +Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f3_s0_ldst_25_20_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 6) >> 26); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_20_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 6) >> 24); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 6) >> 22); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f3_s0_ldst_7_5_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_7_5_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f3_s0_ldst_12_12_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_12_12_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 6) >> 21); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x3ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 6) >> 19); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 6) >> 23); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 6) >> 20); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f3_s0_ldst_7_7_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_7_7_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f3_s0_ldst_15_15_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_15_15_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f3_s0_ldst_12_8_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_12_8_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f3_s0_ldst_12_4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_12_4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f3_s0_ldst_12_11_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_12_11_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_f3_s0_ldst_8_0_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_8_0_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s0_ldst_12_0_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_12_0_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 6) >> 15); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f3_s0_ldst_13_9_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_13_9_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_f3_s0_ldst_25_11_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 6) >> 17); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_11_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x3fff800) | (tie_t << 11); +} + +static unsigned +Field_fld_f3_s0_ldst_25_1_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 6) >> 7); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_1_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe) | (tie_t << 1); +} + +static unsigned +Field_fld_f3_s0_ldst_0_0_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_0_0_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 6) >> 18); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f3_s0_ldst_3_0_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_3_0_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s0_ldst_25_4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 6) >> 10); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f3_s0_ldst_25_8_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14); + return tie_t; +} + +static void +Field_fld_f3_s0_ldst_25_8_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 10) >> 21); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x3ff800) | (tie_t << 11); +} + +static unsigned +Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 10) >> 18); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_f3_s1_ld_21_10_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_10_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 10) >> 22); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f3_s1_ld_21_9_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 10) >> 19); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_9_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 10) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f3_s1_ld_3_0_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_3_0_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 10) >> 25); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f3_s1_ld_12_11_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_12_11_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_f3_s1_ld_12_8_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_12_8_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f3_s1_ld_12_4_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_12_4_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f3_s1_ld_12_2_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_12_2_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f3_s1_ld_7_7_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_7_7_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f3_s1_ld_7_0_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_7_0_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f3_s1_ld_21_16_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 10) >> 26); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_16_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f3_s1_ld_21_0_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 10) >> 10); + return tie_t; +} + +static void +Field_fld_f3_s1_ld_21_0_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 10) >> 26); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s2_mul_11_8_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_11_8_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s2_mul_13_12_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_13_12_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_f3_s2_mul_7_5_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_7_5_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f3_s2_mul_13_7_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 18) >> 25); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_13_7_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f80) | (tie_t << 7); +} + +static unsigned +Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 10) >> 22); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f3_s2_mul_21_0_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 10) >> 10); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_21_0_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s2_mul_7_4_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_7_4_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f3_s2_mul_21_13_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_21_13_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f3_s2_mul_21_15_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 10) >> 25); + return tie_t; +} + +static void +Field_fld_f3_s2_mul_21_15_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f3_s3_alu_28_20_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 3) >> 23); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_20_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_f3_s3_alu_28_21_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 3) >> 24); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_21_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe00000) | (tie_t << 21); +} + +static unsigned +Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 3) >> 22); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 3) >> 25); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_f3_s3_alu_18_7_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_18_7_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); +} + +static unsigned +Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 13) >> 16); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x7fff8) | (tie_t << 3); +} + +static unsigned +Field_fld_f3_s3_alu_18_8_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 13) >> 21); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_18_8_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s3_alu_28_9_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 3) >> 12); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_9_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0x1ffffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 3) >> 17); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 3) >> 16); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x1fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f3_s3_alu_18_14_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_18_14_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_f3_s3_alu_7_6_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_7_6_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f3_s3_alu_18_12_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 13) >> 25); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_18_12_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f000) | (tie_t << 12); +} + +static unsigned +Field_fld_f3_s3_alu_28_12_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 3) >> 15); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_12_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f3_s3_alu_3_2_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_3_2_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f3_s3_alu_28_25_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 3) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_25_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_f3_s3_alu_28_8_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 3) >> 11); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_8_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x1fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f3_s3_alu_18_13_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_18_13_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_fld_f3_s3_alu_28_4_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 3) >> 7); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_4_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 8) >> 23); + return tie_t; +} + +static void +Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + return tie_t; +} + +static void +Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f3_s4_alu_23_20_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s4_alu_23_20_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f3_s4_alu_9_6_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_fld_f3_s4_alu_9_6_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_fld_f3_s4_alu_23_0_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_f3_s4_alu_23_0_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_f3_s4_alu_23_16_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fld_f3_s4_alu_23_16_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 0) >> 15); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 0) >> 13); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xffffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 0) >> 17); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 0) >> 18); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 0) >> 16); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f4_s0_ld_15_15_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_15_15_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f4_s0_ld_12_8_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_12_8_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f4_s0_ld_12_4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_12_4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f4_s0_ld_12_2_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_12_2_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f4_s0_ld_12_0_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_12_0_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f4_s0_ld_31_7_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 0) >> 7); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_7_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff80) | (tie_t << 7); +} + +static unsigned +Field_fld_f4_s0_ld_6_0_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_6_0_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 0) >> 12); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f4_s0_ld_31_20_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 0) >> 20); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_20_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f4_s0_ld_3_0_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_3_0_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s0_ld_6_4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_6_4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_f4_s0_ld_31_9_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 0) >> 9); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_9_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xfffffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f4_s0_ld_31_8_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 0) >> 8); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_8_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 0) >> 27); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); +} + +static unsigned +Field_fld_f4_s0_ld_11_4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_11_4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f4_s0_ld_11_9_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_11_9_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 8) >> 19); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff800) | (tie_t << 11); +} + +static unsigned +Field_fld_f4_s1_ld_4_0_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_4_0_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_f4_s1_ld_23_10_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 8) >> 18); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_10_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 8) >> 21); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f4_s1_ld_23_9_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_9_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 8) >> 23); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f4_s1_ld_12_10_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_12_10_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f4_s1_ld_12_8_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_12_8_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f4_s1_ld_12_4_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_12_4_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f4_s1_ld_12_2_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_12_2_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f4_s1_ld_7_7_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_7_7_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_f4_s1_ld_7_6_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_7_6_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f4_s1_ld_7_0_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_7_0_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f4_s1_ld_23_16_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_16_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f4_s1_ld_23_0_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_f4_s1_ld_23_0_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 6) | (insn[0] >> 26); + return tie_t; +} + +static void +Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 6); +} + +static unsigned +Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s2_mul_32_8_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 24) | (insn[0] >> 8); + return tie_t; +} + +static void +Field_fld_f4_s2_mul_32_8_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff00) | (tie_t << 8); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 24); +} + +static unsigned +Field_fld_f4_s2_mul_7_0_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_f4_s2_mul_7_0_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 0) >> 26); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); +} + +static unsigned +Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f4_s3_alu_24_21_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 7) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_24_21_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e00000) | (tie_t << 21); +} + +static unsigned +Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 0) >> 20); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 0) >> 23); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff800000) | (tie_t << 23); +} + +static unsigned +Field_fld_f4_s3_alu_19_6_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 12) >> 18); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_19_6_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_f4_s3_alu_19_8_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_19_8_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s3_alu_31_19_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 0) >> 19); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_31_19_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_f4_s3_alu_14_6_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 17) >> 23); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_14_6_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f4_s3_alu_3_3_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_3_3_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 7) >> 19); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); +} + +static unsigned +Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_f4_s3_alu_9_8_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_9_8_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 0) >> 13); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xffffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f4_s3_alu_24_13_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 7) >> 20); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_24_13_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f4_s3_alu_3_2_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_3_2_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 0) >> 25); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_f4_s3_alu_14_14_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_14_14_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_f4_s3_alu_31_28_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 0) >> 28); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_31_28_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000000) | (tie_t << 28); +} + +static unsigned +Field_fld_f4_s3_alu_24_18_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 7) >> 25); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_24_18_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f4_s3_alu_19_13_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_19_13_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f4_s3_alu_31_8_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 0) >> 8); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_31_8_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f4_s3_alu_31_7_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 0) >> 7); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_31_7_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff80) | (tie_t << 7); +} + +static unsigned +Field_fld_f4_s3_alu_6_0_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_f4_s3_alu_6_0_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 16); +} + +static unsigned +Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 20); +} + +static unsigned +Field_fld_f5_s0_base_36_20_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_f5_s0_base_36_20_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 12); +} + +static unsigned +Field_fld_f5_s0_base_36_17_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 15) | (insn[0] >> 17); + return tie_t; +} + +static void +Field_fld_f5_s0_base_36_17_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffe0000) | (tie_t << 17); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 15); +} + +static unsigned +Field_fld_f5_s0_base_36_18_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_f5_s0_base_36_18_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 14); +} + +static unsigned +Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f5_s0_base_7_4_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f5_s0_base_7_4_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f5_s0_base_11_0_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_fld_f5_s0_base_11_0_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_f5_s0_base_3_1_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_f5_s0_base_3_1_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_f5_s0_base_36_13_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 19) | (insn[0] >> 13); + return tie_t; +} + +static void +Field_fld_f5_s0_base_36_13_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffe000) | (tie_t << 13); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 19); +} + +static unsigned +Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 5) | (insn[0] >> 27); + return tie_t; +} + +static void +Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 5); +} + +static unsigned +Field_fld_f5_s0_base_11_9_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_f5_s0_base_11_9_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 4) >> 20); + return tie_t; +} + +static void +Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 4) >> 16); + return tie_t; +} + +static void +Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f5_s1_base_27_17_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 4) >> 21); + return tie_t; +} + +static void +Field_fld_f5_s1_base_27_17_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f5_s1_base_7_4_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f5_s1_base_7_4_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f5_s1_base_27_3_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 4) >> 7); + return tie_t; +} + +static void +Field_fld_f5_s1_base_27_3_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_f5_s1_base_2_0_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_f5_s1_base_2_0_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_f5_s1_base_3_0_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f5_s1_base_3_0_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f5_s1_base_27_13_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 4) >> 17); + return tie_t; +} + +static void +Field_fld_f5_s1_base_27_13_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f5_s2_base_26_16_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 5) >> 21); + return tie_t; +} + +static void +Field_fld_f5_s2_base_26_16_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f5_s2_base_7_4_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f5_s2_base_7_4_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f5_s2_base_26_2_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_f5_s2_base_26_2_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f5_s2_base_1_0_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_f5_s2_base_1_0_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_f5_s2_base_3_0_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f5_s2_base_3_0_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f5_s2_base_26_13_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 5) >> 18); + return tie_t; +} + +static void +Field_fld_f5_s2_base_26_13_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f5_s2_base_26_8_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 5) >> 13); + return tie_t; +} + +static void +Field_fld_f5_s2_base_26_8_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x7ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f5_s3_base_25_8_Slot_f5_s3_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14); + return tie_t; +} + +static void +Field_fld_f5_s3_base_25_8_Slot_f5_s3_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f5_s3_base_25_16_Slot_f5_s3_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 6) >> 22); + return tie_t; +} + +static void +Field_fld_f5_s3_base_25_16_Slot_f5_s3_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f5_s3_base_25_1_Slot_f5_s3_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 6) >> 7); + return tie_t; +} + +static void +Field_fld_f5_s3_base_25_1_Slot_f5_s3_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe) | (tie_t << 1); +} + +static unsigned +Field_fld_f5_s3_base_0_0_Slot_f5_s3_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_f5_s3_base_0_0_Slot_f5_s3_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s0_ld_23_4_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 8) >> 12); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_23_4_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f11_s0_ld_1_0_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_1_0_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s0_ld_23_16_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_23_16_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f11_s0_ld_23_20_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_23_20_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_fld_f11_s0_ld_23_17_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_23_17_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f11_s0_ld_23_0_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_23_0_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s0_ld_3_0_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_3_0_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s0_ld_7_4_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_7_4_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f11_s0_ld_23_13_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 8) >> 21); + return tie_t; +} + +static void +Field_fld_f11_s0_ld_23_13_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f11_s1_alu_12_10_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_12_10_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 19) >> 22); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8) | (tie_t << 3); +} + +static unsigned +Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_f11_s1_alu_12_9_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 19) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_12_9_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e00) | (tie_t << 9); +} + +static unsigned +Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f11_s1_alu_15_2_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 16) >> 18); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_15_2_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc) | (tie_t << 2); +} + +static unsigned +Field_fld_f11_s1_alu_12_11_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_12_11_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_f11_s1_alu_15_14_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_15_14_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f11_s1_alu_15_13_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_15_13_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f11_s1_alu_22_13_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 9) >> 22); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_22_13_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 9) >> 21); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f11_s1_alu_15_15_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_15_15_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f11_s1_alu_22_0_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 9) >> 9); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_22_0_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s1_alu_3_0_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_3_0_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s1_alu_22_14_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 9) >> 23); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_22_14_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f11_s1_alu_12_12_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_f11_s1_alu_12_12_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 9) >> 23); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s2_mul_11_8_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_11_8_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s2_mul_13_12_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_13_12_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_f11_s2_mul_7_5_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_7_5_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_f11_s2_mul_13_7_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 18) >> 25); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_13_7_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f80) | (tie_t << 7); +} + +static unsigned +Field_fld_f11_s2_mul_22_13_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 9) >> 22); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_22_13_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 9) >> 21); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_f11_s2_mul_7_4_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_7_4_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f11_s2_mul_22_0_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 9) >> 9); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_22_0_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s2_mul_22_8_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 9) >> 17); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_22_8_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f11_s2_mul_22_15_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 9) >> 24); + return tie_t; +} + +static void +Field_fld_f11_s2_mul_22_15_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 6) >> 21); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x3ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f11_s3_alu_25_16_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 6) >> 22); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_16_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_f11_s3_alu_25_14_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 6) >> 20); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_14_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 6) >> 24); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); +} + +static unsigned +Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s3_alu_25_11_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 6) >> 17); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_11_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x3fff800) | (tie_t << 11); +} + +static unsigned +Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s3_alu_14_8_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_14_8_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); +} + +static unsigned +Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_f11_s3_alu_9_9_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_9_9_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 6) >> 19); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_f11_s3_alu_14_13_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_14_13_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_f11_s3_alu_25_22_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 6) >> 28); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_22_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00000) | (tie_t << 22); +} + +static unsigned +Field_fld_f11_s3_alu_25_17_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 6) >> 23); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_17_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_f11_s3_alu_25_8_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_8_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_f11_s3_alu_25_1_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 6) >> 7); + return tie_t; +} + +static void +Field_fld_f11_s3_alu_25_1_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe) | (tie_t << 1); +} + +static unsigned +Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 7) >> 22); + return tie_t; +} + +static void +Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 7) >> 25); + return tie_t; +} + +static void +Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_f11_s4_alu_24_0_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 7) >> 7); + return tie_t; +} + +static void +Field_fld_f11_s4_alu_24_0_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_f11_s4_alu_24_16_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 7) >> 23); + return tie_t; +} + +static void +Field_fld_f11_s4_alu_24_16_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 5) >> 21); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_n1_s0_ldst_7_6_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_7_6_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 5) >> 22); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 5) >> 18); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_n1_s0_ldst_7_5_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_7_5_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 5) >> 23); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_n1_s0_ldst_15_15_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_15_15_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_n1_s0_ldst_12_8_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_12_8_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 5) >> 20); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_n1_s0_ldst_12_4_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_12_4_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_n1_s0_ldst_12_2_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_12_2_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_n1_s0_ldst_12_0_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_12_0_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_n1_s0_ldst_7_2_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_7_2_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_n1_s0_ldst_26_2_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_2_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_n1_s0_ldst_1_0_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_1_0_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_n1_s0_ldst_26_20_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_20_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_n1_s0_ldst_3_0_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_3_0_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_n1_s0_ldst_26_4_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 5) >> 9); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_4_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_n1_s0_ldst_26_9_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 5) >> 14); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_9_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x7fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_n1_s0_ldst_26_8_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 5) >> 13); + return tie_t; +} + +static void +Field_fld_n1_s0_ldst_26_8_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x7ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_n1_s1_none_3_0_Slot_n1_s1_none_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_n1_s1_none_3_0_Slot_n1_s1_none_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 6) >> 25); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f80000) | (tie_t << 19); +} + +static unsigned +Field_fld_n1_s2_mul_13_9_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_13_9_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 6) >> 20); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 6) >> 27); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00000) | (tie_t << 21); +} + +static unsigned +Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_n1_s2_mul_18_9_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 13) >> 22); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_18_9_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe00) | (tie_t << 9); +} + +static unsigned +Field_fld_n1_s2_mul_8_4_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_8_4_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_n1_s2_mul_18_6_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 13) >> 19); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_18_6_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x7ffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_n1_s2_mul_8_8_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_8_8_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 6) >> 18); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_n1_s2_mul_25_1_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 6) >> 7); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_25_1_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe) | (tie_t << 1); +} + +static unsigned +Field_fld_n1_s2_mul_0_0_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_0_0_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_n1_s2_mul_7_4_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_n1_s2_mul_7_4_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 2) >> 18); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_n2_s0_ldst_7_6_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_7_6_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 2) >> 19); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 2) >> 15); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 2) >> 17); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x3fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_n2_s0_ldst_9_5_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_9_5_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 2) >> 20); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_n2_s0_ldst_15_15_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_15_15_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_n2_s0_ldst_12_8_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_12_8_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_n2_s0_ldst_12_4_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_12_4_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_n2_s0_ldst_12_11_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_12_11_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_n2_s0_ldst_8_0_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_8_0_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_n2_s0_ldst_12_0_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_12_0_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_n2_s0_ldst_29_20_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_20_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_n2_s0_ldst_9_6_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_9_6_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_fld_n2_s0_ldst_29_11_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 2) >> 13); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_11_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x3ffff800) | (tie_t << 11); +} + +static unsigned +Field_fld_n2_s0_ldst_13_11_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_13_11_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_fld_n2_s0_ldst_29_14_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 2) >> 16); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_14_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x3fffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_n2_s0_ldst_29_5_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 2) >> 7); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_5_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_n2_s0_ldst_4_0_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_4_0_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 2) >> 14); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_n2_s0_ldst_3_0_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_3_0_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_n2_s0_ldst_4_4_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_4_4_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_n2_s0_ldst_29_10_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 2) >> 12); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_10_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0x3ffffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_n2_s0_ldst_8_4_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_8_4_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_n2_s0_ldst_29_8_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 2) >> 10); + return tie_t; +} + +static void +Field_fld_n2_s0_ldst_29_8_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 5) >> 16); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x7fff800) | (tie_t << 11); +} + +static unsigned +Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 5) >> 13); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x7ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_n2_s1_ld_26_10_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 5) >> 15); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_10_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x7fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 5) >> 18); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_n2_s1_ld_26_9_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 5) >> 14); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_9_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x7fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 5) >> 22); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 5) >> 20); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_n2_s1_ld_12_10_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_12_10_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_n2_s1_ld_12_8_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_12_8_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_n2_s1_ld_12_4_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_12_4_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_n2_s1_ld_12_2_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_12_2_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_n2_s1_ld_7_7_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_7_7_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_n2_s1_ld_7_6_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_7_6_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_n2_s1_ld_7_0_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_7_0_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 5) >> 21); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_n2_s1_ld_26_2_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_26_2_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_n2_s1_ld_1_0_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_n2_s1_ld_1_0_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 9) >> 26); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e0000) | (tie_t << 17); +} + +static unsigned +Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 9) >> 22); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_n0_s0_ldst_7_5_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_7_5_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 9) >> 24); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_n0_s0_ldst_12_12_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_12_12_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_n0_s0_ldst_7_6_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_7_6_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_n0_s0_ldst_12_8_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_12_8_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_n0_s0_ldst_12_4_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_12_4_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_n0_s0_ldst_12_2_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_12_2_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_n0_s0_ldst_12_0_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_12_0_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 9) >> 21); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_n0_s0_ldst_22_16_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_22_16_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_n0_s0_ldst_22_0_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 9) >> 9); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_22_0_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_n0_s0_ldst_3_0_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_n0_s0_ldst_3_0_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_n0_s1_none_2_0_Slot_n0_s1_none_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_n0_s1_none_2_0_Slot_n0_s1_none_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_n0_s2_none_2_0_Slot_n0_s2_none_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_n0_s2_none_2_0_Slot_n0_s2_none_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 4) >> 27); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf800000) | (tie_t << 23); +} + +static unsigned +Field_fld_n0_s3_alu_9_6_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_9_6_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_n0_s3_alu_9_7_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_9_7_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_n0_s3_alu_19_13_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_19_13_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13); +} + +static unsigned +Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_n0_s3_alu_27_13_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 4) >> 17); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_27_13_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_n0_s3_alu_19_12_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_19_12_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_fld_n0_s3_alu_7_0_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_7_0_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 4) >> 24); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_n0_s3_alu_14_14_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_14_14_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_n0_s3_alu_14_10_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_14_10_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_n0_s3_alu_27_15_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 4) >> 19); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_27_15_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_n0_s3_alu_14_13_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_14_13_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_n0_s3_alu_9_3_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_9_3_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); +} + +static unsigned +Field_fld_n0_s3_alu_9_9_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_9_9_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_n0_s3_alu_27_22_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 4) >> 26); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_27_22_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_n0_s3_alu_27_16_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 4) >> 20); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_27_16_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 4) >> 16); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_n0_s3_alu_27_3_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 4) >> 7); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_27_3_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_n0_s3_alu_2_0_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_2_0_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_f5_s3_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f5_s3_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_bbi_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_bbi_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_bbi_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_bbi_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_imm8_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_imm8_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_imm8_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_imm8_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); + tie_t = (val << 24) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_imm8_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_imm8_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_imm8_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 15) >> 25); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_imm8_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 24) >> 25; + insn[0] = (insn[0] & ~0x1fc00) | (tie_t << 10); +} + +static unsigned +Field_imm8_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_imm8_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_imm8_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 11) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_imm8_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 24) >> 26; + insn[0] = (insn[0] & ~0x1f8000) | (tie_t << 15); +} + +static unsigned +Field_imm8_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 14) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc00) | (tie_t << 10); +} + +static unsigned +Field_imm8_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_imm8_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); + tie_t = (val << 24) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_imm8_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_imm8_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); + tie_t = (val << 24) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_imm8_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f5_s3_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f5_s3_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_imm8_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_imm8_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_f5_s3_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f5_s3_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 20) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_imm12b_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 20) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_imm12b_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 20) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_imm12b_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_f5_s3_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f5_s3_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 20) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_imm12b_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_offset_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_op2_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_op2_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_op2_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_op2_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_op2_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_op2_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_op2_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_op2_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_op2_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_r_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); + return tie_t; +} + +static void +Field_r_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6) | (tie_t << 1); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_r_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_r_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_r_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_r_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_r_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sal_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_sal_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_sal_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sargt_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_sargt_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sargt_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f5_s1_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f5_s1_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f5_s2_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f5_s2_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sargt_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_sas_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_sas_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_t2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_s2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_t4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_s4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_t8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_r8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr15_imm_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wbr15_imm_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wbr15_imm_Slot_f5_s0_base_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_f5_s0_base_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_bbe_shflimm_s0_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_bbe_shflimm_s0_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_bbe_shflimm_s0_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_bbe_shflimm_s0_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_bbe_shflimm_s0_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_bbe_shflimm_s0_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_bbe_shflimm_s0_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_fld_bbe_shflimm_s0_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_fld_bbe_shflimm_s0_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_fld_bbe_shflimm_s0_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_fld_bbe_shflimm_s0_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_fld_bbe_shflimm_s0_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 21) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uul_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uul_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uus_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uus_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uus_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uus_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uus_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uus_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uus_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uus_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uus_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uus_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uus_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uus_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_uus_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_uus_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f11_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f11_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_valignr_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_valignr_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbr_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbr_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbre_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbre_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbre_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbre_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbre_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbre_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbre_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbre_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbre_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbre_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vbre_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vbre_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vr_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vr_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrr_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrr_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrr_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrr_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f4_s0_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f4_s0_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_arr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_arr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_arr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_arr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_arr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_arr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i32_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i32_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_i8_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_i8_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_vt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_vt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n1_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n1_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm4_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_saimm4_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2) | (tie_t << 1); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm4_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_saimm4_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_saimm4_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_saimm4_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_saimm4_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_saimm4_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_saimm4_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm4_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2) | (tie_t << 1); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm4_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_saimm4_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_saimm4_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_saimm5_Slot_f0_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f0_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_saimm5_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6) | (tie_t << 1); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm5_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_saimm5_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_saimm5_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_saimm5_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_saimm5_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_saimm5_Slot_f3_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f3_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_saimm5_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm5_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6) | (tie_t << 1); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm5_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm5_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_saimm5_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_bbe_ltrx2nimm_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_bbe_ltrx2nimm_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrx2nimm_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrx2nimm_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrx2nimm_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrx2nimm_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrx2nimm_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrx2nimm_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrx2nimm_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrx2nimm_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrx2nimm_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrx2nimm_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrx2nimm_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrx2nimm_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxn_2imm_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_bbe_ltrxn_2imm_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxn_2imm_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxn_2imm_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxn_2imm_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxn_2imm_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxn_2imm_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxn_2imm_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxn_2imm_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxn_2imm_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxn_2imm_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxn_2imm_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxn_2imm_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxn_2imm_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxnimm_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_bbe_ltrxnimm_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxnimm_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxnimm_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxnimm_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxnimm_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxnimm_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxnimm_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxnimm_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxnimm_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxnimm_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxnimm_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_bbe_ltrxnimm_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_bbe_ltrxnimm_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_imm1_2n_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_imm1_2n_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_imm1_2n_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_imm1_2n_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_imm1_2n_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_imm1_2n_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_imm1_2n_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_imm1_2n_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_imm1_2n_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_imm1_2n_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_imm1_2n_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_imm1_2n_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_sqz_vbr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vbr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_sqz_vbr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vbr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_sqz_vbr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vbr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_sqz_vbr_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vbr_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_sqz_vbr_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vbr_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_sqz_vt_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vt_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_sqz_vt_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vt_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_sqz_vt_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vt_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_sqz_vt_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vt_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_sqz_vt_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sqz_vt_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_arr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_arr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_arr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_arr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_arr_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_arr_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_arr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_arr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_arr_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_arr_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_arr_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_arr_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_i_imm4_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_immmovvi_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_vbr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_vbr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_vbr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_vbr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_vbr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_vbr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_vt_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_vt_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_vt_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_vt_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_vt_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_vt_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_vt_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_vt_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_vt_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_vt_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_vt_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_vt_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_wvr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_wvr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_wvr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_wvr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_wvr_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_wvr_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_wvr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_wvr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_wvr_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_wvr_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_mov_wvr_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_mov_wvr_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_arr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_arr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_arr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_arr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_arr_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_arr_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_arr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_arr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_arr_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_arr_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_arr_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_arr_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_vt_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_vt_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_vt_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_vt_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_vt_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_vt_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_vt_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_vt_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_vt_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_vt_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_vt_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_vt_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f0_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f0_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f1_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f1_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f3_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f3_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f4_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_wvr_Slot_f4_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_wvec_pack_wvr_Slot_n2_s1_ld_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_wvec_pack_wvr_Slot_n2_s1_ld_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_multiply_arr_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_arr_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_multiply_arr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_arr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_multiply_arr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_arr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_multiply_arr_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_arr_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_multiply_arr_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_arr_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_multiply_arr_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_arr_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_multiply_arr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_arr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_multiply_vp_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vp_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_multiply_vp_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vp_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_multiply_vp_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vp_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_multiply_vp_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vp_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_multiply_vr_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vr_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_multiply_vr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_multiply_vr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_multiply_vr_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vr_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ivp_sem_multiply_vr_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vr_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_multiply_vr_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vr_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ivp_sem_multiply_vr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_multiply_vs_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vs_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ivp_sem_multiply_vs_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vs_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_multiply_vs_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vs_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_multiply_vs_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vs_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_multiply_vs_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vs_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_multiply_vs_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vs_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_multiply_vs_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vs_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_multiply_wvt_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_wvt_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_multiply_wvt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_wvt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_multiply_wvt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_wvt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_multiply_wvt_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_wvt_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_multiply_wvt_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 6) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_wvt_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ivp_sem_multiply_wvt_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_wvt_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_multiply_wvt_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_wvt_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vbt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vbt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f0_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f0_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_vs_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_vs_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f0_s3_alu_24_19_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 7) >> 26); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_24_19_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x1f80000) | (tie_t << 19); +} + +static unsigned +Field_fld_f0_s3_alu_33_10_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 22) | (insn[0] >> 10); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_10_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xfffffc00) | (tie_t << 10); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 22); +} + +static unsigned +Field_fld_f0_s3_alu_33_19_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 13) | (insn[0] >> 19); + return tie_t; +} + +static void +Field_fld_f0_s3_alu_33_19_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfff80000) | (tie_t << 19); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 13); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_i_imm4_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vbr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vbr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vbr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vbr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vbr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vbr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vbr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vbr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vs_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vs_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vs_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vs_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vs_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vs_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vs_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vs_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vs_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vs_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_fp_sem_hp_cnv_vt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_cnv_vt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vbr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vbr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vbr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vbr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vbr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vbr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vbr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vbr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vbr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vbr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_sp32cvt_vt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_sp32cvt_vt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vbr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vbr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vbr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vbr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vbr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vbr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vbr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vbr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vs_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vs_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vs_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vs_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vs_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vs_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vs_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vs_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vs_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vs_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vsm_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vsm_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vsm_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vsm_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vsm_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vsm_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vsm_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vsm_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vsm_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vsm_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_spmisc_vt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spmisc_vt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_alu_i_imm3_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbr_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbt_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vbt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vbt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vr_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vr_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vt_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vt_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vt_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vt_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_reduce_vt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_reduce_vt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_arr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_arr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_arr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_arr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_arr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_arr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_arr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_arr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_arr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_arr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_arr_Slot_f11_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_arr_Slot_f11_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_arr_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_arr_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_rep_arr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_rep_arr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_select_isel_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_isel_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_select_isel_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_isel_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_isel_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_isel_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_isel_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_isel_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_vec_select_isel_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_isel_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_isel_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 10) >> 25); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_isel_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_select_isel_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_isel_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_ishfl_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_ishfl_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_select_ishfl_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_ishfl_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_ishfl_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_ishfl_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_ishfl_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_ishfl_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_select_ishfl_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_ishfl_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_select_ishfl_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_ishfl_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_select_ishfl_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_ishfl_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_slct_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_slct_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_select_slct_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_slct_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_select_slct_h_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_slct_h_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_select_slct_h_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_slct_h_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_select_sr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_sr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_select_sr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_sr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_select_sr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_sr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_select_sr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_sr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_select_sr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_sr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vbr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vbr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vbr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vbr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vbr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vbr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vbr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vbr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vbr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vbr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vr_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vr_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vr_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vr_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vr_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vr_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vr_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vr_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vs_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vs_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vs_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vs_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vs_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vs_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vs_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vs_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vs_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vs_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vs_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vs_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vs_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vs_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vt_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vt_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vt_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vt_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vt_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vt_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vt_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vt_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vt_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vt_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vu_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vu_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_select_vu_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_select_vu_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vs_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vs_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vs_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vs_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vs_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vs_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vs_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vs_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vs_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vs_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vs_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vs_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ivp_sem_vec_shift_vs_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_shift_vs_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_saimm6_31_Slot_f0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_saimm6_31_Slot_f0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm6_31_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_saimm6_31_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_saimm6_31_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_saimm6_31_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_saimm6_31_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_saimm6_31_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_saimm6_31_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_saimm6_31_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm6_31_Slot_f11_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_saimm6_31_Slot_f11_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_saimm6_31_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_saimm6_31_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_bbe_selimm_s0_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_bbe_selimm_s0_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_bbe_selimm_s0_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_bbe_selimm_s0_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vr_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vr_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_scatter_gather_vr_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_scatter_gather_vr_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f1_s0_ldstalu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f1_s0_ldstalu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_n2_s0_ldst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_n2_s0_ldst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_f1_s2_mul_28_5_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 3) >> 8); + return tie_t; +} + +static void +Field_fld_f1_s2_mul_28_5_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0x1fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_bbe_selimm_s2_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_bbe_selimm_s2_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_bbe_shflimm_s2_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_fld_bbe_shflimm_s2_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vbr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vbr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vbr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vbr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vbr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vbr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vs_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vs_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vs_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vs_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vs_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vs_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_fp_sem_hp_fma_vt_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_fp_sem_hp_fma_vt_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_multiply_vt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_multiply_vt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_multiply_vt_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vt_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_spfma_vbr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vbr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_spfma_vbr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vbr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_spfma_vbr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vbr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_spfma_vr_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vr_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_spfma_vr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_spfma_vr_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vr_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_spfma_vs_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vs_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_spfma_vs_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vs_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_spfma_vs_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vs_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_spfma_vt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spfma_vt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_spfma_vt_Slot_n1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_spfma_vt_Slot_n1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vt_Slot_f1_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vt_Slot_f1_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_unpack_wvec_mov_vt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_unpack_wvec_mov_vt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_f1_s3_alu_19_19_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_19_19_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_f1_s3_alu_30_19_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 1) >> 20); + return tie_t; +} + +static void +Field_fld_f1_s3_alu_30_19_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_arr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_arr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_arr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_arr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_arr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_arr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vr_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vr_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vs_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vs_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vs_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vs_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vs_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vs_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vt_Slot_f1_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vt_Slot_f1_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vt_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vt_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vt_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vt_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_f2_s2_mul_30_10_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 1) >> 11); + return tie_t; +} + +static void +Field_fld_f2_s2_mul_30_10_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x7ffffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_divide_lane_ctrl_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_divide_lane_ctrl_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ivp_sem_divide_vr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_divide_vr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ivp_sem_divide_vs_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_divide_vs_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ivp_sem_divide_vt_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_divide_vt_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ivp_sem_divide_vu_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_divide_vu_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_multiply_vbr_Slot_f2_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vbr_Slot_f2_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_f2_s3_alu_19_19_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_19_19_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_f2_s3_alu_30_19_Slot_f2_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 1) >> 20); + return tie_t; +} + +static void +Field_fld_f2_s3_alu_30_19_Slot_f2_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_f3_s3_alu_18_18_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_18_18_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_f3_s3_alu_28_18_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 3) >> 21); + return tie_t; +} + +static void +Field_fld_f3_s3_alu_28_18_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vbr_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 7) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vbr_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vbr_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 7) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vbr_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x1800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vbs_Slot_f3_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vbs_Slot_f3_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ivp_sem_vec_histogram_vbs_Slot_f4_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ivp_sem_vec_histogram_vbs_Slot_f4_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_bbe_selimm_s4_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_bbe_selimm_s4_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_bbe_shflimm_s4_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_fld_bbe_shflimm_s4_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_fld_ivp_sem_multiply_vq_Slot_f4_s2_mul_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ivp_sem_multiply_vq_Slot_f4_s2_mul_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ivp_sem_ld_st_vrul2_Slot_f11_s1_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ivp_sem_ld_st_vrul2_Slot_f11_s1_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_n0_s3_alu_27_19_Slot_n0_s3_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 4) >> 23); + return tie_t; +} + +static void +Field_fld_n0_s3_alu_27_19_Slot_n0_s3_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_mtk_andpopc_c_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_mtk_andpopc_c_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_mtk_andpopc_c_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_mtk_andpopc_c_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_mtk_andpopc_inb_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_mtk_andpopc_inb_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_mtk_andpopc_inb_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_mtk_andpopc_inb_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_mtk_andpopc_ina_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_mtk_andpopc_ina_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_mtk_andpopc_ina_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_mtk_andpopc_ina_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_mtk_andpopc_odata_Slot_f3_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_mtk_andpopc_odata_Slot_f3_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_mtk_andpopc_odata_Slot_f11_s4_alu_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_mtk_andpopc_odata_Slot_f11_s4_alu_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_iq_tie2apb_inq0_pop_qdata_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_iq_tie2apb_inq0_pop_qdata_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_iq_tie2apb_inq0_is_ready_is_ready_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_iq_tie2apb_inq0_is_ready_is_ready_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_iq_tie2apb_inq0_nonblocking_peek_success_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_iq_tie2apb_inq0_nonblocking_peek_success_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_iq_tie2apb_inq0_nonblocking_peek_qdata_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_iq_tie2apb_inq0_nonblocking_peek_qdata_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_iq_tie2apb_inq0_nonblocking_pop_success_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_iq_tie2apb_inq0_nonblocking_pop_success_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_iq_tie2apb_inq0_nonblocking_pop_qdata_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_iq_tie2apb_inq0_nonblocking_pop_qdata_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_iq_tie2apb_inq0_blocking_peek_qdata_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_iq_tie2apb_inq0_blocking_peek_qdata_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_push_read_qaddr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_push_read_qaddr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_push_read_qdata_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_push_read_qdata_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_push_write_qaddr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_push_write_qaddr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_push_write_qdata_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_push_write_qdata_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_is_ready_is_ready_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_is_ready_is_ready_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_nonblocking_push_read_success_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_nonblocking_push_read_success_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_nonblocking_push_read_qaddr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_nonblocking_push_read_qaddr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_nonblocking_push_read_qdata_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_nonblocking_push_read_qdata_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_nonblocking_push_write_success_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_nonblocking_push_write_success_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_nonblocking_push_write_qaddr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_nonblocking_push_write_qaddr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_oq_tie2apb_outq0_nonblocking_push_write_qdata_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_oq_tie2apb_outq0_nonblocking_push_write_qdata_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +static unsigned +Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +enum xtensa_field_id { + FIELD_t, + FIELD_bbi4, + FIELD_bbi, + FIELD_imm12, + FIELD_imm8, + FIELD_s, + FIELD_imm12b, + FIELD_imm16, + FIELD_m, + FIELD_n, + FIELD_offset, + FIELD_op0, + FIELD_op1, + FIELD_op2, + FIELD_r, + FIELD_sa4, + FIELD_sae4, + FIELD_sae, + FIELD_sal, + FIELD_sargt, + FIELD_sas4, + FIELD_sas, + FIELD_sr, + FIELD_st, + FIELD_thi3, + FIELD_imm4, + FIELD_mn, + FIELD_i, + FIELD_imm6lo, + FIELD_imm6hi, + FIELD_imm7lo, + FIELD_imm7hi, + FIELD_z, + FIELD_imm6, + FIELD_imm7, + FIELD_t2, + FIELD_s2, + FIELD_r2, + FIELD_t4, + FIELD_s4, + FIELD_r4, + FIELD_t8, + FIELD_s8, + FIELD_r8, + FIELD_xt_wbr15_imm, + FIELD_xt_wbr18_imm, + FIELD_fld_F0_S0_LdSt_11_4, + FIELD_fld_F0_S0_LdSt_11_8, + FIELD_fld_F0_S0_LdSt_11_9, + FIELD_fld_F0_S0_LdSt_12_0, + FIELD_fld_F0_S0_LdSt_12_11, + FIELD_fld_F0_S0_LdSt_12_12, + FIELD_fld_F0_S0_LdSt_12_2, + FIELD_fld_F0_S0_LdSt_12_4, + FIELD_fld_F0_S0_LdSt_12_8, + FIELD_fld_F0_S0_LdSt_13_9, + FIELD_fld_F0_S0_LdSt_15_15, + FIELD_fld_F0_S0_LdSt_33_11, + FIELD_fld_F0_S0_LdSt_33_12, + FIELD_fld_F0_S0_LdSt_33_13, + FIELD_fld_F0_S0_LdSt_33_14, + FIELD_fld_F0_S0_LdSt_33_15, + FIELD_fld_F0_S0_LdSt_33_16, + FIELD_fld_F0_S0_LdSt_33_17, + FIELD_fld_F0_S0_LdSt_33_18, + FIELD_fld_F0_S0_LdSt_33_19, + FIELD_fld_F0_S0_LdSt_33_20, + FIELD_fld_F0_S0_LdSt_33_27, + FIELD_fld_F0_S0_LdSt_33_9, + FIELD_fld_F0_S0_LdSt_3_0, + FIELD_fld_F0_S0_LdSt_7_4, + FIELD_fld_F0_S0_LdSt_7_5, + FIELD_fld_F0_S0_LdSt_7_6, + FIELD_fld_F0_S0_LdSt_7_7, + FIELD_fld_F0_S0_LdSt_8_0, + FIELD_fld_F0_S0_LdSt_8_4, + FIELD_fld_F0_S0_LdSt_8_8, + FIELD_fld_bbe_shflimm_S0, + FIELD_fld_ivp_sem_ld_st_i_bimm4, + FIELD_fld_ivp_sem_ld_st_i_bimm4b2n, + FIELD_fld_ivp_sem_ld_st_i_bimm4bn, + FIELD_fld_ivp_sem_ld_st_i_bimm4bn_2, + FIELD_fld_ivp_sem_ld_st_i_bimm4x1, + FIELD_fld_ivp_sem_ld_st_i_bimm4x2, + FIELD_fld_ivp_sem_ld_st_i_bimm4x4, + FIELD_fld_ivp_sem_ld_st_i_bimm6, + FIELD_fld_ivp_sem_ld_st_i_bimm6b2n, + FIELD_fld_ivp_sem_ld_st_i_bimm6bn, + FIELD_fld_ivp_sem_ld_st_i_bimm6bn_2, + FIELD_fld_ivp_sem_ld_st_i_bimm6x1, + FIELD_fld_ivp_sem_ld_st_i_bimm6x2, + FIELD_fld_ivp_sem_ld_st_i_bimm6x4, + FIELD_fld_ivp_sem_ld_st_i_bimm8, + FIELD_fld_ivp_sem_ld_st_i_bimm8x4, + FIELD_fld_ivp_sem_ld_st_i_bimmb4, + FIELD_fld_ivp_sem_ld_st_i_bimmb6, + FIELD_fld_ivp_sem_ld_st_i_bimmb8, + FIELD_fld_ivp_sem_ld_st_i_bimmh4, + FIELD_fld_ivp_sem_ld_st_i_bimmh6, + FIELD_fld_ivp_sem_ld_st_i_bimmh8, + FIELD_fld_ivp_sem_ld_st_uul, + FIELD_fld_ivp_sem_ld_st_uus, + FIELD_fld_ivp_sem_ld_st_valignr, + FIELD_fld_ivp_sem_ld_st_vbr, + FIELD_fld_ivp_sem_ld_st_vbre, + FIELD_fld_ivp_sem_ld_st_vr, + FIELD_fld_ivp_sem_ld_st_vrr, + FIELD_fld_ivp_sem_ld_st_vrul, + FIELD_fld_ivp_sem_vec_alu_arr, + FIELD_fld_ivp_sem_vec_alu_vbr, + FIELD_fld_ivp_sem_vec_alu_vr, + FIELD_fld_ivp_sem_vec_alu_vt, + FIELD_fld_ivp_sem_vec_rep_i, + FIELD_fld_ivp_sem_vec_rep_i32, + FIELD_fld_ivp_sem_vec_rep_i8, + FIELD_fld_ivp_sem_vec_rep_vr, + FIELD_fld_ivp_sem_vec_rep_vt, + FIELD_fld_ivp_sem_vec_scatter_gather_ars, + FIELD_fld_ivp_sem_vec_scatter_gather_gt, + FIELD_fld_ivp_sem_vec_scatter_gather_vbr, + FIELD_fld_ivp_sem_vec_scatter_gather_vs, + FIELD_fld_ivp_sem_vec_shift_vr, + FIELD_fld_ivp_sem_vec_shift_vt, + FIELD_fld_ivp_sem_vec_specialized_seli_vr, + FIELD_fld_ivp_sem_vec_specialized_seli_vt, + FIELD_fld_saimm4, + FIELD_fld_saimm5, + FIELD_fld_F0_S1_Ld_12_11, + FIELD_fld_F0_S1_Ld_12_12, + FIELD_fld_F0_S1_Ld_12_4, + FIELD_fld_F0_S1_Ld_15_10, + FIELD_fld_F0_S1_Ld_15_13, + FIELD_fld_F0_S1_Ld_15_14, + FIELD_fld_F0_S1_Ld_15_15, + FIELD_fld_F0_S1_Ld_15_2, + FIELD_fld_F0_S1_Ld_15_4, + FIELD_fld_F0_S1_Ld_15_8, + FIELD_fld_F0_S1_Ld_24_0, + FIELD_fld_F0_S1_Ld_24_11, + FIELD_fld_F0_S1_Ld_24_12, + FIELD_fld_F0_S1_Ld_24_13, + FIELD_fld_F0_S1_Ld_24_14, + FIELD_fld_F0_S1_Ld_24_16, + FIELD_fld_F0_S1_Ld_24_17, + FIELD_fld_F0_S1_Ld_24_18, + FIELD_fld_F0_S1_Ld_24_8, + FIELD_fld_F0_S1_Ld_3_0, + FIELD_fld_F0_S1_Ld_3_2, + FIELD_fld_F0_S1_Ld_7_0, + FIELD_fld_F0_S1_Ld_7_2, + FIELD_fld_F0_S1_Ld_7_3, + FIELD_fld_F0_S1_Ld_7_4, + FIELD_fld_F0_S1_Ld_7_5, + FIELD_fld_F0_S1_Ld_7_6, + FIELD_fld_F0_S1_Ld_7_7, + FIELD_fld_bbe_ltrx2nimm, + FIELD_fld_bbe_ltrxn_2imm, + FIELD_fld_bbe_ltrxnimm, + FIELD_fld_imm1_2N, + FIELD_fld_ivp_sem_sqz_vbr, + FIELD_fld_ivp_sem_sqz_vt, + FIELD_fld_ivp_sem_vbool_alu_ltr_art, + FIELD_fld_ivp_sem_vbool_alu_ltr_vbr, + FIELD_fld_ivp_sem_vbool_alu_ltr_vbs, + FIELD_fld_ivp_sem_vbool_alu_ltr_vbt, + FIELD_fld_ivp_sem_vec_mov_arr, + FIELD_fld_ivp_sem_vec_mov_i_IMM_movint, + FIELD_fld_ivp_sem_vec_mov_i_imm4, + FIELD_fld_ivp_sem_vec_mov_immmovvi, + FIELD_fld_ivp_sem_vec_mov_vbr, + FIELD_fld_ivp_sem_vec_mov_vt, + FIELD_fld_ivp_sem_vec_mov_wvr, + FIELD_fld_ivp_sem_vec_scatter_gather_gs, + FIELD_fld_ivp_sem_vec_scatter_gather_vt, + FIELD_fld_ivp_sem_wvec_pack_arr, + FIELD_fld_ivp_sem_wvec_pack_vt, + FIELD_fld_ivp_sem_wvec_pack_wvr, + FIELD_fld_F0_S2_Mul_11_8, + FIELD_fld_F0_S2_Mul_13_12, + FIELD_fld_F0_S2_Mul_18_12, + FIELD_fld_F0_S2_Mul_18_14, + FIELD_fld_F0_S2_Mul_18_9, + FIELD_fld_F0_S2_Mul_1_0, + FIELD_fld_F0_S2_Mul_26_12, + FIELD_fld_F0_S2_Mul_26_13, + FIELD_fld_F0_S2_Mul_26_14, + FIELD_fld_F0_S2_Mul_26_2, + FIELD_fld_F0_S2_Mul_26_20, + FIELD_fld_F0_S2_Mul_26_21, + FIELD_fld_F0_S2_Mul_3_0, + FIELD_fld_F0_S2_Mul_3_3, + FIELD_fld_F0_S2_Mul_4_4, + FIELD_fld_F0_S2_Mul_7_4, + FIELD_fld_F0_S2_Mul_7_5, + FIELD_fld_ivp_sem_multiply_arr, + FIELD_fld_ivp_sem_multiply_vp, + FIELD_fld_ivp_sem_multiply_vr, + FIELD_fld_ivp_sem_multiply_vs, + FIELD_fld_ivp_sem_multiply_wvt, + FIELD_fld_ivp_sem_unpack_wvec_mov_vr, + FIELD_fld_ivp_sem_unpack_wvec_mov_vs, + FIELD_fld_ivp_sem_unpack_wvec_mov_wvr, + FIELD_fld_ivp_sem_unpack_wvec_mov_wvt, + FIELD_fld_ivp_sem_vec_alu_vbt, + FIELD_fld_ivp_sem_vec_alu_vs, + FIELD_fld_F0_S3_ALU_0_0, + FIELD_fld_F0_S3_ALU_14_10, + FIELD_fld_F0_S3_ALU_14_11, + FIELD_fld_F0_S3_ALU_14_13, + FIELD_fld_F0_S3_ALU_14_14, + FIELD_fld_F0_S3_ALU_14_8, + FIELD_fld_F0_S3_ALU_24_10, + FIELD_fld_F0_S3_ALU_24_13, + FIELD_fld_F0_S3_ALU_24_19, + FIELD_fld_F0_S3_ALU_24_20, + FIELD_fld_F0_S3_ALU_33_10, + FIELD_fld_F0_S3_ALU_33_13, + FIELD_fld_F0_S3_ALU_33_18, + FIELD_fld_F0_S3_ALU_33_19, + FIELD_fld_F0_S3_ALU_33_20, + FIELD_fld_F0_S3_ALU_33_25, + FIELD_fld_F0_S3_ALU_33_26, + FIELD_fld_F0_S3_ALU_33_27, + FIELD_fld_F0_S3_ALU_33_28, + FIELD_fld_F0_S3_ALU_33_9, + FIELD_fld_F0_S3_ALU_3_0, + FIELD_fld_F0_S3_ALU_3_1, + FIELD_fld_F0_S3_ALU_3_2, + FIELD_fld_F0_S3_ALU_3_3, + FIELD_fld_F0_S3_ALU_7_3, + FIELD_fld_F0_S3_ALU_7_4, + FIELD_fld_F0_S3_ALU_7_7, + FIELD_fld_F0_S3_ALU_8_0, + FIELD_fld_F0_S3_ALU_8_8, + FIELD_fld_F0_S3_ALU_9_0, + FIELD_fld_F0_S3_ALU_9_7, + FIELD_fld_F0_S3_ALU_9_8, + FIELD_fld_fp_sem_hp_cnv_i_imm4, + FIELD_fld_fp_sem_hp_cnv_vbr, + FIELD_fld_fp_sem_hp_cnv_vr, + FIELD_fld_fp_sem_hp_cnv_vs, + FIELD_fld_fp_sem_hp_cnv_vt, + FIELD_fld_ivp_sem_sp32cvt_i_imm5, + FIELD_fld_ivp_sem_sp32cvt_vbr, + FIELD_fld_ivp_sem_sp32cvt_vr, + FIELD_fld_ivp_sem_sp32cvt_vt, + FIELD_fld_ivp_sem_spmisc_vbr, + FIELD_fld_ivp_sem_spmisc_vr, + FIELD_fld_ivp_sem_spmisc_vs, + FIELD_fld_ivp_sem_spmisc_vsM, + FIELD_fld_ivp_sem_spmisc_vt, + FIELD_fld_ivp_sem_vec_alu_i_imm3, + FIELD_fld_ivp_sem_vec_reduce_vbr, + FIELD_fld_ivp_sem_vec_reduce_vbt, + FIELD_fld_ivp_sem_vec_reduce_vr, + FIELD_fld_ivp_sem_vec_reduce_vt, + FIELD_fld_ivp_sem_vec_rep_arr, + FIELD_fld_ivp_sem_vec_select_isel, + FIELD_fld_ivp_sem_vec_select_ishfl, + FIELD_fld_ivp_sem_vec_select_slct, + FIELD_fld_ivp_sem_vec_select_slct_h, + FIELD_fld_ivp_sem_vec_select_sr, + FIELD_fld_ivp_sem_vec_select_vbr, + FIELD_fld_ivp_sem_vec_select_vr, + FIELD_fld_ivp_sem_vec_select_vs, + FIELD_fld_ivp_sem_vec_select_vt, + FIELD_fld_ivp_sem_vec_select_vu, + FIELD_fld_ivp_sem_vec_shift_vs, + FIELD_fld_saimm6_31, + FIELD_fld_F1_S0_LdStALU_12_0, + FIELD_fld_F1_S0_LdStALU_12_12, + FIELD_fld_F1_S0_LdStALU_12_2, + FIELD_fld_F1_S0_LdStALU_12_4, + FIELD_fld_F1_S0_LdStALU_12_8, + FIELD_fld_F1_S0_LdStALU_14_10, + FIELD_fld_F1_S0_LdStALU_14_12, + FIELD_fld_F1_S0_LdStALU_14_14, + FIELD_fld_F1_S0_LdStALU_15_15, + FIELD_fld_F1_S0_LdStALU_30_12, + FIELD_fld_F1_S0_LdStALU_30_13, + FIELD_fld_F1_S0_LdStALU_30_14, + FIELD_fld_F1_S0_LdStALU_30_15, + FIELD_fld_F1_S0_LdStALU_30_16, + FIELD_fld_F1_S0_LdStALU_30_17, + FIELD_fld_F1_S0_LdStALU_30_18, + FIELD_fld_F1_S0_LdStALU_30_19, + FIELD_fld_F1_S0_LdStALU_30_20, + FIELD_fld_F1_S0_LdStALU_30_6, + FIELD_fld_F1_S0_LdStALU_30_8, + FIELD_fld_F1_S0_LdStALU_30_9, + FIELD_fld_F1_S0_LdStALU_3_0, + FIELD_fld_F1_S0_LdStALU_5_0, + FIELD_fld_F1_S0_LdStALU_5_4, + FIELD_fld_F1_S0_LdStALU_7_4, + FIELD_fld_F1_S0_LdStALU_7_5, + FIELD_fld_F1_S0_LdStALU_7_7, + FIELD_fld_F1_S0_LdStALU_9_9, + FIELD_fld_bbe_selimm_S0, + FIELD_fld_ivp_sem_vec_scatter_gather_vr, + FIELD_fld_ivp_sem_vec_specialized_seli_vs, + FIELD_fld_F1_S1_Ld_12_10, + FIELD_fld_F1_S1_Ld_12_11, + FIELD_fld_F1_S1_Ld_12_12, + FIELD_fld_F1_S1_Ld_12_4, + FIELD_fld_F1_S1_Ld_12_9, + FIELD_fld_F1_S1_Ld_15_10, + FIELD_fld_F1_S1_Ld_15_13, + FIELD_fld_F1_S1_Ld_15_14, + FIELD_fld_F1_S1_Ld_15_15, + FIELD_fld_F1_S1_Ld_15_2, + FIELD_fld_F1_S1_Ld_15_4, + FIELD_fld_F1_S1_Ld_15_8, + FIELD_fld_F1_S1_Ld_1_0, + FIELD_fld_F1_S1_Ld_26_11, + FIELD_fld_F1_S1_Ld_26_12, + FIELD_fld_F1_S1_Ld_26_13, + FIELD_fld_F1_S1_Ld_26_16, + FIELD_fld_F1_S1_Ld_26_18, + FIELD_fld_F1_S1_Ld_26_2, + FIELD_fld_F1_S1_Ld_3_0, + FIELD_fld_F1_S1_Ld_3_2, + FIELD_fld_F1_S1_Ld_7_0, + FIELD_fld_F1_S1_Ld_7_2, + FIELD_fld_F1_S1_Ld_7_3, + FIELD_fld_F1_S1_Ld_7_4, + FIELD_fld_F1_S1_Ld_7_5, + FIELD_fld_F1_S1_Ld_7_6, + FIELD_fld_F1_S1_Ld_7_7, + FIELD_fld_F1_S2_Mul_13_10, + FIELD_fld_F1_S2_Mul_13_2, + FIELD_fld_F1_S2_Mul_13_5, + FIELD_fld_F1_S2_Mul_14_10, + FIELD_fld_F1_S2_Mul_28_12, + FIELD_fld_F1_S2_Mul_28_15, + FIELD_fld_F1_S2_Mul_28_16, + FIELD_fld_F1_S2_Mul_28_18, + FIELD_fld_F1_S2_Mul_28_20, + FIELD_fld_F1_S2_Mul_28_4, + FIELD_fld_F1_S2_Mul_28_5, + FIELD_fld_F1_S2_Mul_3_0, + FIELD_fld_F1_S2_Mul_3_2, + FIELD_fld_F1_S2_Mul_3_3, + FIELD_fld_F1_S2_Mul_4_4, + FIELD_fld_F1_S2_Mul_9_5, + FIELD_fld_F1_S2_Mul_9_6, + FIELD_fld_bbe_selimm_S2, + FIELD_fld_bbe_shflimm_S2, + FIELD_fld_fp_sem_hp_fma_vbr, + FIELD_fld_fp_sem_hp_fma_vr, + FIELD_fld_fp_sem_hp_fma_vs, + FIELD_fld_fp_sem_hp_fma_vt, + FIELD_fld_ivp_sem_multiply_vt, + FIELD_fld_ivp_sem_spfma_vbr, + FIELD_fld_ivp_sem_spfma_vr, + FIELD_fld_ivp_sem_spfma_vs, + FIELD_fld_ivp_sem_spfma_vt, + FIELD_fld_ivp_sem_unpack_wvec_mov_vt, + FIELD_fld_F1_S3_ALU_0_0, + FIELD_fld_F1_S3_ALU_14_10, + FIELD_fld_F1_S3_ALU_14_13, + FIELD_fld_F1_S3_ALU_14_14, + FIELD_fld_F1_S3_ALU_14_8, + FIELD_fld_F1_S3_ALU_19_14, + FIELD_fld_F1_S3_ALU_19_15, + FIELD_fld_F1_S3_ALU_19_19, + FIELD_fld_F1_S3_ALU_19_4, + FIELD_fld_F1_S3_ALU_19_7, + FIELD_fld_F1_S3_ALU_30_15, + FIELD_fld_F1_S3_ALU_30_17, + FIELD_fld_F1_S3_ALU_30_19, + FIELD_fld_F1_S3_ALU_30_20, + FIELD_fld_F1_S3_ALU_30_22, + FIELD_fld_F1_S3_ALU_30_23, + FIELD_fld_F1_S3_ALU_30_6, + FIELD_fld_F1_S3_ALU_30_8, + FIELD_fld_F1_S3_ALU_3_0, + FIELD_fld_F1_S3_ALU_3_1, + FIELD_fld_F1_S3_ALU_3_2, + FIELD_fld_F1_S3_ALU_3_3, + FIELD_fld_F1_S3_ALU_5_0, + FIELD_fld_F1_S3_ALU_9_0, + FIELD_fld_F1_S3_ALU_9_1, + FIELD_fld_F1_S3_ALU_9_2, + FIELD_fld_F1_S3_ALU_9_3, + FIELD_fld_F1_S3_ALU_9_7, + FIELD_fld_F1_S3_ALU_9_8, + FIELD_fld_F1_S3_ALU_9_9, + FIELD_fld_ivp_sem_vec_histogram_arr, + FIELD_fld_ivp_sem_vec_histogram_vr, + FIELD_fld_ivp_sem_vec_histogram_vs, + FIELD_fld_ivp_sem_vec_histogram_vt, + FIELD_fld_F2_S0_LdSt_12_0, + FIELD_fld_F2_S0_LdSt_12_10, + FIELD_fld_F2_S0_LdSt_12_2, + FIELD_fld_F2_S0_LdSt_12_4, + FIELD_fld_F2_S0_LdSt_12_8, + FIELD_fld_F2_S0_LdSt_15_15, + FIELD_fld_F2_S0_LdSt_28_11, + FIELD_fld_F2_S0_LdSt_28_12, + FIELD_fld_F2_S0_LdSt_28_13, + FIELD_fld_F2_S0_LdSt_28_14, + FIELD_fld_F2_S0_LdSt_28_15, + FIELD_fld_F2_S0_LdSt_28_16, + FIELD_fld_F2_S0_LdSt_28_17, + FIELD_fld_F2_S0_LdSt_28_18, + FIELD_fld_F2_S0_LdSt_28_20, + FIELD_fld_F2_S0_LdSt_28_4, + FIELD_fld_F2_S0_LdSt_28_8, + FIELD_fld_F2_S0_LdSt_3_0, + FIELD_fld_F2_S0_LdSt_3_2, + FIELD_fld_F2_S0_LdSt_7_2, + FIELD_fld_F2_S0_LdSt_7_4, + FIELD_fld_F2_S1_Ld_12_10, + FIELD_fld_F2_S1_Ld_12_11, + FIELD_fld_F2_S1_Ld_12_4, + FIELD_fld_F2_S1_Ld_12_9, + FIELD_fld_F2_S1_Ld_15_10, + FIELD_fld_F2_S1_Ld_15_13, + FIELD_fld_F2_S1_Ld_15_14, + FIELD_fld_F2_S1_Ld_15_15, + FIELD_fld_F2_S1_Ld_15_2, + FIELD_fld_F2_S1_Ld_15_4, + FIELD_fld_F2_S1_Ld_15_8, + FIELD_fld_F2_S1_Ld_1_0, + FIELD_fld_F2_S1_Ld_26_11, + FIELD_fld_F2_S1_Ld_26_12, + FIELD_fld_F2_S1_Ld_26_13, + FIELD_fld_F2_S1_Ld_26_16, + FIELD_fld_F2_S1_Ld_26_18, + FIELD_fld_F2_S1_Ld_26_2, + FIELD_fld_F2_S1_Ld_3_0, + FIELD_fld_F2_S1_Ld_3_2, + FIELD_fld_F2_S1_Ld_7_0, + FIELD_fld_F2_S1_Ld_7_2, + FIELD_fld_F2_S1_Ld_7_3, + FIELD_fld_F2_S1_Ld_7_4, + FIELD_fld_F2_S1_Ld_7_6, + FIELD_fld_F2_S1_Ld_7_7, + FIELD_fld_F2_S2_Mul_14_10, + FIELD_fld_F2_S2_Mul_14_11, + FIELD_fld_F2_S2_Mul_14_5, + FIELD_fld_F2_S2_Mul_19_10, + FIELD_fld_F2_S2_Mul_19_15, + FIELD_fld_F2_S2_Mul_19_7, + FIELD_fld_F2_S2_Mul_30_10, + FIELD_fld_F2_S2_Mul_30_12, + FIELD_fld_F2_S2_Mul_30_15, + FIELD_fld_F2_S2_Mul_30_18, + FIELD_fld_F2_S2_Mul_30_19, + FIELD_fld_F2_S2_Mul_30_20, + FIELD_fld_F2_S2_Mul_30_21, + FIELD_fld_F2_S2_Mul_30_6, + FIELD_fld_F2_S2_Mul_3_0, + FIELD_fld_F2_S2_Mul_4_0, + FIELD_fld_F2_S2_Mul_4_3, + FIELD_fld_F2_S2_Mul_5_0, + FIELD_fld_ivp_sem_divide_lane_ctrl, + FIELD_fld_ivp_sem_divide_vr, + FIELD_fld_ivp_sem_divide_vs, + FIELD_fld_ivp_sem_divide_vt, + FIELD_fld_ivp_sem_divide_vu, + FIELD_fld_ivp_sem_multiply_vbr, + FIELD_fld_F2_S3_ALU_0_0, + FIELD_fld_F2_S3_ALU_14_10, + FIELD_fld_F2_S3_ALU_14_13, + FIELD_fld_F2_S3_ALU_14_14, + FIELD_fld_F2_S3_ALU_14_8, + FIELD_fld_F2_S3_ALU_19_14, + FIELD_fld_F2_S3_ALU_19_15, + FIELD_fld_F2_S3_ALU_19_19, + FIELD_fld_F2_S3_ALU_19_4, + FIELD_fld_F2_S3_ALU_19_7, + FIELD_fld_F2_S3_ALU_30_15, + FIELD_fld_F2_S3_ALU_30_18, + FIELD_fld_F2_S3_ALU_30_19, + FIELD_fld_F2_S3_ALU_30_20, + FIELD_fld_F2_S3_ALU_30_22, + FIELD_fld_F2_S3_ALU_30_23, + FIELD_fld_F2_S3_ALU_30_6, + FIELD_fld_F2_S3_ALU_30_8, + FIELD_fld_F2_S3_ALU_3_0, + FIELD_fld_F2_S3_ALU_3_1, + FIELD_fld_F2_S3_ALU_3_2, + FIELD_fld_F2_S3_ALU_3_3, + FIELD_fld_F2_S3_ALU_5_0, + FIELD_fld_F2_S3_ALU_9_0, + FIELD_fld_F2_S3_ALU_9_1, + FIELD_fld_F2_S3_ALU_9_2, + FIELD_fld_F2_S3_ALU_9_3, + FIELD_fld_F2_S3_ALU_9_7, + FIELD_fld_F2_S3_ALU_9_8, + FIELD_fld_F2_S3_ALU_9_9, + FIELD_fld_F3_S0_LdSt_0_0, + FIELD_fld_F3_S0_LdSt_12_0, + FIELD_fld_F3_S0_LdSt_12_11, + FIELD_fld_F3_S0_LdSt_12_12, + FIELD_fld_F3_S0_LdSt_12_4, + FIELD_fld_F3_S0_LdSt_12_8, + FIELD_fld_F3_S0_LdSt_13_9, + FIELD_fld_F3_S0_LdSt_15_15, + FIELD_fld_F3_S0_LdSt_25_1, + FIELD_fld_F3_S0_LdSt_25_11, + FIELD_fld_F3_S0_LdSt_25_12, + FIELD_fld_F3_S0_LdSt_25_13, + FIELD_fld_F3_S0_LdSt_25_14, + FIELD_fld_F3_S0_LdSt_25_15, + FIELD_fld_F3_S0_LdSt_25_16, + FIELD_fld_F3_S0_LdSt_25_17, + FIELD_fld_F3_S0_LdSt_25_18, + FIELD_fld_F3_S0_LdSt_25_19, + FIELD_fld_F3_S0_LdSt_25_20, + FIELD_fld_F3_S0_LdSt_25_4, + FIELD_fld_F3_S0_LdSt_25_8, + FIELD_fld_F3_S0_LdSt_25_9, + FIELD_fld_F3_S0_LdSt_3_0, + FIELD_fld_F3_S0_LdSt_7_4, + FIELD_fld_F3_S0_LdSt_7_5, + FIELD_fld_F3_S0_LdSt_7_7, + FIELD_fld_F3_S0_LdSt_8_0, + FIELD_fld_F3_S1_Ld_12_11, + FIELD_fld_F3_S1_Ld_12_2, + FIELD_fld_F3_S1_Ld_12_4, + FIELD_fld_F3_S1_Ld_12_8, + FIELD_fld_F3_S1_Ld_21_0, + FIELD_fld_F3_S1_Ld_21_10, + FIELD_fld_F3_S1_Ld_21_11, + FIELD_fld_F3_S1_Ld_21_12, + FIELD_fld_F3_S1_Ld_21_13, + FIELD_fld_F3_S1_Ld_21_15, + FIELD_fld_F3_S1_Ld_21_16, + FIELD_fld_F3_S1_Ld_21_17, + FIELD_fld_F3_S1_Ld_21_8, + FIELD_fld_F3_S1_Ld_21_9, + FIELD_fld_F3_S1_Ld_3_0, + FIELD_fld_F3_S1_Ld_3_2, + FIELD_fld_F3_S1_Ld_4_0, + FIELD_fld_F3_S1_Ld_4_3, + FIELD_fld_F3_S1_Ld_4_4, + FIELD_fld_F3_S1_Ld_7_0, + FIELD_fld_F3_S1_Ld_7_2, + FIELD_fld_F3_S1_Ld_7_4, + FIELD_fld_F3_S1_Ld_7_7, + FIELD_fld_F3_S2_Mul_11_8, + FIELD_fld_F3_S2_Mul_13_12, + FIELD_fld_F3_S2_Mul_13_7, + FIELD_fld_F3_S2_Mul_21_0, + FIELD_fld_F3_S2_Mul_21_12, + FIELD_fld_F3_S2_Mul_21_13, + FIELD_fld_F3_S2_Mul_21_14, + FIELD_fld_F3_S2_Mul_21_15, + FIELD_fld_F3_S2_Mul_21_16, + FIELD_fld_F3_S2_Mul_3_0, + FIELD_fld_F3_S2_Mul_3_3, + FIELD_fld_F3_S2_Mul_4_0, + FIELD_fld_F3_S2_Mul_7_4, + FIELD_fld_F3_S2_Mul_7_5, + FIELD_fld_F3_S3_ALU_13_9, + FIELD_fld_F3_S3_ALU_18_12, + FIELD_fld_F3_S3_ALU_18_13, + FIELD_fld_F3_S3_ALU_18_14, + FIELD_fld_F3_S3_ALU_18_18, + FIELD_fld_F3_S3_ALU_18_3, + FIELD_fld_F3_S3_ALU_18_7, + FIELD_fld_F3_S3_ALU_18_8, + FIELD_fld_F3_S3_ALU_28_12, + FIELD_fld_F3_S3_ALU_28_13, + FIELD_fld_F3_S3_ALU_28_14, + FIELD_fld_F3_S3_ALU_28_18, + FIELD_fld_F3_S3_ALU_28_19, + FIELD_fld_F3_S3_ALU_28_20, + FIELD_fld_F3_S3_ALU_28_21, + FIELD_fld_F3_S3_ALU_28_22, + FIELD_fld_F3_S3_ALU_28_25, + FIELD_fld_F3_S3_ALU_28_4, + FIELD_fld_F3_S3_ALU_28_8, + FIELD_fld_F3_S3_ALU_28_9, + FIELD_fld_F3_S3_ALU_3_0, + FIELD_fld_F3_S3_ALU_3_2, + FIELD_fld_F3_S3_ALU_3_3, + FIELD_fld_F3_S3_ALU_7_3, + FIELD_fld_F3_S3_ALU_7_6, + FIELD_fld_F3_S3_ALU_7_7, + FIELD_fld_F3_S3_ALU_8_0, + FIELD_fld_ivp_sem_vec_histogram_vbr, + FIELD_fld_ivp_sem_vec_histogram_vbs, + FIELD_fld_F3_S4_ALU_14_10, + FIELD_fld_F3_S4_ALU_23_0, + FIELD_fld_F3_S4_ALU_23_15, + FIELD_fld_F3_S4_ALU_23_18, + FIELD_fld_F3_S4_ALU_23_20, + FIELD_fld_F3_S4_ALU_9_5, + FIELD_fld_F3_S4_ALU_9_6, + FIELD_fld_bbe_selimm_S4, + FIELD_fld_bbe_shflimm_S4, + FIELD_fld_F4_S0_Ld_11_4, + FIELD_fld_F4_S0_Ld_11_8, + FIELD_fld_F4_S0_Ld_11_9, + FIELD_fld_F4_S0_Ld_12_0, + FIELD_fld_F4_S0_Ld_12_2, + FIELD_fld_F4_S0_Ld_12_4, + FIELD_fld_F4_S0_Ld_12_8, + FIELD_fld_F4_S0_Ld_15_15, + FIELD_fld_F4_S0_Ld_31_12, + FIELD_fld_F4_S0_Ld_31_13, + FIELD_fld_F4_S0_Ld_31_15, + FIELD_fld_F4_S0_Ld_31_16, + FIELD_fld_F4_S0_Ld_31_17, + FIELD_fld_F4_S0_Ld_31_18, + FIELD_fld_F4_S0_Ld_31_20, + FIELD_fld_F4_S0_Ld_31_27, + FIELD_fld_F4_S0_Ld_31_7, + FIELD_fld_F4_S0_Ld_31_8, + FIELD_fld_F4_S0_Ld_31_9, + FIELD_fld_F4_S0_Ld_3_0, + FIELD_fld_F4_S0_Ld_6_0, + FIELD_fld_F4_S0_Ld_6_4, + FIELD_fld_F4_S0_Ld_7_4, + FIELD_fld_F4_S1_Ld_12_10, + FIELD_fld_F4_S1_Ld_12_2, + FIELD_fld_F4_S1_Ld_12_4, + FIELD_fld_F4_S1_Ld_12_8, + FIELD_fld_F4_S1_Ld_23_0, + FIELD_fld_F4_S1_Ld_23_10, + FIELD_fld_F4_S1_Ld_23_11, + FIELD_fld_F4_S1_Ld_23_12, + FIELD_fld_F4_S1_Ld_23_13, + FIELD_fld_F4_S1_Ld_23_15, + FIELD_fld_F4_S1_Ld_23_16, + FIELD_fld_F4_S1_Ld_23_17, + FIELD_fld_F4_S1_Ld_23_8, + FIELD_fld_F4_S1_Ld_23_9, + FIELD_fld_F4_S1_Ld_3_0, + FIELD_fld_F4_S1_Ld_3_2, + FIELD_fld_F4_S1_Ld_4_0, + FIELD_fld_F4_S1_Ld_4_3, + FIELD_fld_F4_S1_Ld_4_4, + FIELD_fld_F4_S1_Ld_7_0, + FIELD_fld_F4_S1_Ld_7_2, + FIELD_fld_F4_S1_Ld_7_4, + FIELD_fld_F4_S1_Ld_7_6, + FIELD_fld_F4_S1_Ld_7_7, + FIELD_fld_F4_S2_Mul_32_26, + FIELD_fld_F4_S2_Mul_32_8, + FIELD_fld_F4_S2_Mul_3_0, + FIELD_fld_F4_S2_Mul_7_0, + FIELD_fld_ivp_sem_multiply_vq, + FIELD_fld_F4_S3_ALU_0_0, + FIELD_fld_F4_S3_ALU_14_10, + FIELD_fld_F4_S3_ALU_14_11, + FIELD_fld_F4_S3_ALU_14_12, + FIELD_fld_F4_S3_ALU_14_13, + FIELD_fld_F4_S3_ALU_14_14, + FIELD_fld_F4_S3_ALU_14_6, + FIELD_fld_F4_S3_ALU_14_8, + FIELD_fld_F4_S3_ALU_19_13, + FIELD_fld_F4_S3_ALU_19_6, + FIELD_fld_F4_S3_ALU_19_8, + FIELD_fld_F4_S3_ALU_24_12, + FIELD_fld_F4_S3_ALU_24_13, + FIELD_fld_F4_S3_ALU_24_18, + FIELD_fld_F4_S3_ALU_24_20, + FIELD_fld_F4_S3_ALU_24_21, + FIELD_fld_F4_S3_ALU_31_13, + FIELD_fld_F4_S3_ALU_31_19, + FIELD_fld_F4_S3_ALU_31_20, + FIELD_fld_F4_S3_ALU_31_23, + FIELD_fld_F4_S3_ALU_31_25, + FIELD_fld_F4_S3_ALU_31_26, + FIELD_fld_F4_S3_ALU_31_28, + FIELD_fld_F4_S3_ALU_31_7, + FIELD_fld_F4_S3_ALU_31_8, + FIELD_fld_F4_S3_ALU_3_0, + FIELD_fld_F4_S3_ALU_3_1, + FIELD_fld_F4_S3_ALU_3_2, + FIELD_fld_F4_S3_ALU_3_3, + FIELD_fld_F4_S3_ALU_6_0, + FIELD_fld_F4_S3_ALU_7_4, + FIELD_fld_F4_S3_ALU_7_5, + FIELD_fld_F4_S3_ALU_9_8, + FIELD_fld_F5_S0_Base_11_0, + FIELD_fld_F5_S0_Base_11_8, + FIELD_fld_F5_S0_Base_11_9, + FIELD_fld_F5_S0_Base_36_12, + FIELD_fld_F5_S0_Base_36_13, + FIELD_fld_F5_S0_Base_36_16, + FIELD_fld_F5_S0_Base_36_17, + FIELD_fld_F5_S0_Base_36_18, + FIELD_fld_F5_S0_Base_36_20, + FIELD_fld_F5_S0_Base_36_27, + FIELD_fld_F5_S0_Base_3_0, + FIELD_fld_F5_S0_Base_3_1, + FIELD_fld_F5_S0_Base_7_4, + FIELD_fld_F5_S1_Base_27_12, + FIELD_fld_F5_S1_Base_27_13, + FIELD_fld_F5_S1_Base_27_16, + FIELD_fld_F5_S1_Base_27_17, + FIELD_fld_F5_S1_Base_27_3, + FIELD_fld_F5_S1_Base_2_0, + FIELD_fld_F5_S1_Base_3_0, + FIELD_fld_F5_S1_Base_7_4, + FIELD_fld_F5_S2_Base_1_0, + FIELD_fld_F5_S2_Base_26_12, + FIELD_fld_F5_S2_Base_26_13, + FIELD_fld_F5_S2_Base_26_16, + FIELD_fld_F5_S2_Base_26_2, + FIELD_fld_F5_S2_Base_26_8, + FIELD_fld_F5_S2_Base_3_0, + FIELD_fld_F5_S2_Base_7_4, + FIELD_fld_F5_S3_Base_0_0, + FIELD_fld_F5_S3_Base_25_1, + FIELD_fld_F5_S3_Base_25_16, + FIELD_fld_F5_S3_Base_25_8, + FIELD_fld_F11_S0_Ld_1_0, + FIELD_fld_F11_S0_Ld_23_0, + FIELD_fld_F11_S0_Ld_23_12, + FIELD_fld_F11_S0_Ld_23_13, + FIELD_fld_F11_S0_Ld_23_16, + FIELD_fld_F11_S0_Ld_23_17, + FIELD_fld_F11_S0_Ld_23_20, + FIELD_fld_F11_S0_Ld_23_4, + FIELD_fld_F11_S0_Ld_3_0, + FIELD_fld_F11_S0_Ld_7_4, + FIELD_fld_F11_S1_ALU_12_10, + FIELD_fld_F11_S1_ALU_12_11, + FIELD_fld_F11_S1_ALU_12_12, + FIELD_fld_F11_S1_ALU_12_3, + FIELD_fld_F11_S1_ALU_12_4, + FIELD_fld_F11_S1_ALU_12_9, + FIELD_fld_F11_S1_ALU_15_13, + FIELD_fld_F11_S1_ALU_15_14, + FIELD_fld_F11_S1_ALU_15_15, + FIELD_fld_F11_S1_ALU_15_2, + FIELD_fld_F11_S1_ALU_22_0, + FIELD_fld_F11_S1_ALU_22_12, + FIELD_fld_F11_S1_ALU_22_13, + FIELD_fld_F11_S1_ALU_22_14, + FIELD_fld_F11_S1_ALU_22_16, + FIELD_fld_F11_S1_ALU_22_18, + FIELD_fld_F11_S1_ALU_3_0, + FIELD_fld_F11_S1_ALU_7_4, + FIELD_fld_ivp_sem_ld_st_vrul2, + FIELD_fld_F11_S2_Mul_11_8, + FIELD_fld_F11_S2_Mul_13_12, + FIELD_fld_F11_S2_Mul_13_7, + FIELD_fld_F11_S2_Mul_22_0, + FIELD_fld_F11_S2_Mul_22_12, + FIELD_fld_F11_S2_Mul_22_13, + FIELD_fld_F11_S2_Mul_22_14, + FIELD_fld_F11_S2_Mul_22_15, + FIELD_fld_F11_S2_Mul_22_16, + FIELD_fld_F11_S2_Mul_22_8, + FIELD_fld_F11_S2_Mul_3_0, + FIELD_fld_F11_S2_Mul_3_3, + FIELD_fld_F11_S2_Mul_4_0, + FIELD_fld_F11_S2_Mul_7_4, + FIELD_fld_F11_S2_Mul_7_5, + FIELD_fld_F11_S3_ALU_0_0, + FIELD_fld_F11_S3_ALU_14_10, + FIELD_fld_F11_S3_ALU_14_11, + FIELD_fld_F11_S3_ALU_14_13, + FIELD_fld_F11_S3_ALU_14_8, + FIELD_fld_F11_S3_ALU_25_1, + FIELD_fld_F11_S3_ALU_25_11, + FIELD_fld_F11_S3_ALU_25_13, + FIELD_fld_F11_S3_ALU_25_14, + FIELD_fld_F11_S3_ALU_25_15, + FIELD_fld_F11_S3_ALU_25_16, + FIELD_fld_F11_S3_ALU_25_17, + FIELD_fld_F11_S3_ALU_25_18, + FIELD_fld_F11_S3_ALU_25_22, + FIELD_fld_F11_S3_ALU_25_8, + FIELD_fld_F11_S3_ALU_3_0, + FIELD_fld_F11_S3_ALU_3_1, + FIELD_fld_F11_S3_ALU_7_0, + FIELD_fld_F11_S3_ALU_7_4, + FIELD_fld_F11_S3_ALU_9_8, + FIELD_fld_F11_S3_ALU_9_9, + FIELD_fld_F11_S4_ALU_24_0, + FIELD_fld_F11_S4_ALU_24_15, + FIELD_fld_F11_S4_ALU_24_18, + FIELD_fld_F11_S4_ALU_9_5, + FIELD_fld_N1_S0_LdSt_12_0, + FIELD_fld_N1_S0_LdSt_12_12, + FIELD_fld_N1_S0_LdSt_12_2, + FIELD_fld_N1_S0_LdSt_12_4, + FIELD_fld_N1_S0_LdSt_12_8, + FIELD_fld_N1_S0_LdSt_15_15, + FIELD_fld_N1_S0_LdSt_1_0, + FIELD_fld_N1_S0_LdSt_26_12, + FIELD_fld_N1_S0_LdSt_26_13, + FIELD_fld_N1_S0_LdSt_26_15, + FIELD_fld_N1_S0_LdSt_26_16, + FIELD_fld_N1_S0_LdSt_26_17, + FIELD_fld_N1_S0_LdSt_26_18, + FIELD_fld_N1_S0_LdSt_26_2, + FIELD_fld_N1_S0_LdSt_26_20, + FIELD_fld_N1_S0_LdSt_26_4, + FIELD_fld_N1_S0_LdSt_26_8, + FIELD_fld_N1_S0_LdSt_26_9, + FIELD_fld_N1_S0_LdSt_3_0, + FIELD_fld_N1_S0_LdSt_3_2, + FIELD_fld_N1_S0_LdSt_7_2, + FIELD_fld_N1_S0_LdSt_7_4, + FIELD_fld_N1_S0_LdSt_7_5, + FIELD_fld_N1_S0_LdSt_7_6, + FIELD_fld_N1_S1_None_3_0, + FIELD_fld_N1_S2_Mul_0_0, + FIELD_fld_N1_S2_Mul_13_9, + FIELD_fld_N1_S2_Mul_18_14, + FIELD_fld_N1_S2_Mul_18_6, + FIELD_fld_N1_S2_Mul_18_9, + FIELD_fld_N1_S2_Mul_25_1, + FIELD_fld_N1_S2_Mul_25_12, + FIELD_fld_N1_S2_Mul_25_14, + FIELD_fld_N1_S2_Mul_25_19, + FIELD_fld_N1_S2_Mul_25_21, + FIELD_fld_N1_S2_Mul_3_0, + FIELD_fld_N1_S2_Mul_3_3, + FIELD_fld_N1_S2_Mul_7_4, + FIELD_fld_N1_S2_Mul_8_4, + FIELD_fld_N1_S2_Mul_8_8, + FIELD_fld_N2_S0_LdSt_12_0, + FIELD_fld_N2_S0_LdSt_12_10, + FIELD_fld_N2_S0_LdSt_12_11, + FIELD_fld_N2_S0_LdSt_12_12, + FIELD_fld_N2_S0_LdSt_12_4, + FIELD_fld_N2_S0_LdSt_12_8, + FIELD_fld_N2_S0_LdSt_13_11, + FIELD_fld_N2_S0_LdSt_15_15, + FIELD_fld_N2_S0_LdSt_29_10, + FIELD_fld_N2_S0_LdSt_29_11, + FIELD_fld_N2_S0_LdSt_29_12, + FIELD_fld_N2_S0_LdSt_29_13, + FIELD_fld_N2_S0_LdSt_29_14, + FIELD_fld_N2_S0_LdSt_29_15, + FIELD_fld_N2_S0_LdSt_29_16, + FIELD_fld_N2_S0_LdSt_29_17, + FIELD_fld_N2_S0_LdSt_29_18, + FIELD_fld_N2_S0_LdSt_29_20, + FIELD_fld_N2_S0_LdSt_29_5, + FIELD_fld_N2_S0_LdSt_29_8, + FIELD_fld_N2_S0_LdSt_3_0, + FIELD_fld_N2_S0_LdSt_4_0, + FIELD_fld_N2_S0_LdSt_4_4, + FIELD_fld_N2_S0_LdSt_7_4, + FIELD_fld_N2_S0_LdSt_7_6, + FIELD_fld_N2_S0_LdSt_8_0, + FIELD_fld_N2_S0_LdSt_8_4, + FIELD_fld_N2_S0_LdSt_9_5, + FIELD_fld_N2_S0_LdSt_9_6, + FIELD_fld_N2_S1_Ld_12_10, + FIELD_fld_N2_S1_Ld_12_2, + FIELD_fld_N2_S1_Ld_12_4, + FIELD_fld_N2_S1_Ld_12_8, + FIELD_fld_N2_S1_Ld_1_0, + FIELD_fld_N2_S1_Ld_26_10, + FIELD_fld_N2_S1_Ld_26_11, + FIELD_fld_N2_S1_Ld_26_12, + FIELD_fld_N2_S1_Ld_26_13, + FIELD_fld_N2_S1_Ld_26_15, + FIELD_fld_N2_S1_Ld_26_16, + FIELD_fld_N2_S1_Ld_26_17, + FIELD_fld_N2_S1_Ld_26_2, + FIELD_fld_N2_S1_Ld_26_8, + FIELD_fld_N2_S1_Ld_26_9, + FIELD_fld_N2_S1_Ld_3_0, + FIELD_fld_N2_S1_Ld_3_2, + FIELD_fld_N2_S1_Ld_4_0, + FIELD_fld_N2_S1_Ld_4_3, + FIELD_fld_N2_S1_Ld_4_4, + FIELD_fld_N2_S1_Ld_7_0, + FIELD_fld_N2_S1_Ld_7_2, + FIELD_fld_N2_S1_Ld_7_4, + FIELD_fld_N2_S1_Ld_7_6, + FIELD_fld_N2_S1_Ld_7_7, + FIELD_fld_N0_S0_LdSt_12_0, + FIELD_fld_N0_S0_LdSt_12_12, + FIELD_fld_N0_S0_LdSt_12_2, + FIELD_fld_N0_S0_LdSt_12_4, + FIELD_fld_N0_S0_LdSt_12_8, + FIELD_fld_N0_S0_LdSt_22_0, + FIELD_fld_N0_S0_LdSt_22_12, + FIELD_fld_N0_S0_LdSt_22_13, + FIELD_fld_N0_S0_LdSt_22_15, + FIELD_fld_N0_S0_LdSt_22_16, + FIELD_fld_N0_S0_LdSt_22_17, + FIELD_fld_N0_S0_LdSt_3_0, + FIELD_fld_N0_S0_LdSt_7_4, + FIELD_fld_N0_S0_LdSt_7_5, + FIELD_fld_N0_S0_LdSt_7_6, + FIELD_fld_N0_S1_None_2_0, + FIELD_fld_N0_S2_None_2_0, + FIELD_fld_N0_S3_ALU_14_10, + FIELD_fld_N0_S3_ALU_14_13, + FIELD_fld_N0_S3_ALU_14_14, + FIELD_fld_N0_S3_ALU_14_5, + FIELD_fld_N0_S3_ALU_19_12, + FIELD_fld_N0_S3_ALU_19_13, + FIELD_fld_N0_S3_ALU_19_15, + FIELD_fld_N0_S3_ALU_27_12, + FIELD_fld_N0_S3_ALU_27_13, + FIELD_fld_N0_S3_ALU_27_15, + FIELD_fld_N0_S3_ALU_27_16, + FIELD_fld_N0_S3_ALU_27_19, + FIELD_fld_N0_S3_ALU_27_20, + FIELD_fld_N0_S3_ALU_27_22, + FIELD_fld_N0_S3_ALU_27_23, + FIELD_fld_N0_S3_ALU_27_3, + FIELD_fld_N0_S3_ALU_2_0, + FIELD_fld_N0_S3_ALU_3_0, + FIELD_fld_N0_S3_ALU_7_0, + FIELD_fld_N0_S3_ALU_9_0, + FIELD_fld_N0_S3_ALU_9_3, + FIELD_fld_N0_S3_ALU_9_4, + FIELD_fld_N0_S3_ALU_9_5, + FIELD_fld_N0_S3_ALU_9_6, + FIELD_fld_N0_S3_ALU_9_7, + FIELD_fld_N0_S3_ALU_9_9, + FIELD_fld_MTK_AndPOPC_c, + FIELD_fld_MTK_AndPOPC_inB, + FIELD_fld_MTK_AndPOPC_inA, + FIELD_fld_MTK_AndPOPC_oData, + FIELD_fld_F11_S4_ALU_24_16, + FIELD_fld_F3_S4_ALU_23_16, + FIELD_fld_iq_tie2apb_inq0_pop_qdata, + FIELD_fld_iq_tie2apb_inq0_is_ready_is_ready, + FIELD_fld_Inst_11_8, + FIELD_fld_iq_tie2apb_inq0_nonblocking_peek_success, + FIELD_fld_iq_tie2apb_inq0_nonblocking_peek_qdata, + FIELD_fld_iq_tie2apb_inq0_nonblocking_pop_success, + FIELD_fld_iq_tie2apb_inq0_nonblocking_pop_qdata, + FIELD_fld_Inst_23_8, + FIELD_fld_iq_tie2apb_inq0_blocking_peek_qdata, + FIELD_fld_Inst_23_12, + FIELD_fld_oq_tie2apb_outq0_push_read_qaddr, + FIELD_fld_oq_tie2apb_outq0_push_read_qdata, + FIELD_fld_oq_tie2apb_outq0_push_write_qaddr, + FIELD_fld_oq_tie2apb_outq0_push_write_qdata, + FIELD_fld_oq_tie2apb_outq0_is_ready_is_ready, + FIELD_fld_Inst_3_0, + FIELD_fld_Inst_23_16, + FIELD_fld_oq_tie2apb_outq0_nonblocking_push_read_success, + FIELD_fld_oq_tie2apb_outq0_nonblocking_push_read_qaddr, + FIELD_fld_oq_tie2apb_outq0_nonblocking_push_read_qdata, + FIELD_fld_oq_tie2apb_outq0_nonblocking_push_write_success, + FIELD_fld_oq_tie2apb_outq0_nonblocking_push_write_qaddr, + FIELD_fld_oq_tie2apb_outq0_nonblocking_push_write_qdata, + FIELD__ar0, + FIELD__ar4, + FIELD__ar8, + FIELD__ar12, + FIELD__bt16, + FIELD__bs16, + FIELD__br16, + FIELD__brall +}; + + +/* Functional units. */ + +#define funcUnits 0 + + +/* Register files. */ + +enum xtensa_regfile_id { + REGFILE_AR, + REGFILE_BR, + REGFILE_vec, + REGFILE_vbool, + REGFILE_valign, + REGFILE_wvec, + REGFILE_gvr, + REGFILE_BR2, + REGFILE_BR4, + REGFILE_BR8, + REGFILE_BR16 +}; + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", REGFILE_AR, 32, 32 }, + { "BR", "b", REGFILE_BR, 1, 16 }, + { "vec", "v", REGFILE_vec, 512, 32 }, + { "vbool", "vb", REGFILE_vbool, 64, 8 }, + { "valign", "u", REGFILE_valign, 512, 4 }, + { "wvec", "wv", REGFILE_wvec, 1536, 4 }, + { "gvr", "gr", REGFILE_gvr, 512, 4 }, + { "BR2", "b", REGFILE_BR, 2, 8 }, + { "BR4", "b", REGFILE_BR, 4, 4 }, + { "BR8", "b", REGFILE_BR, 8, 2 }, + { "BR16", "b", REGFILE_BR, 16, 1 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "ERI_RD_Out", 14, 0, 0, 'o' }, + { "ERI_RD_In", 32, 0, 1, 'i' }, + { "ERI_RD_Rdy", 1, 0, 0, 'i' }, + { "ERI_WR_Out", 46, 0, 2, 'o' }, + { "ERI_WR_In", 1, 0, 3, 'i' }, + { "iq_tie2apb_inq0_Empty", 1, 0, 4, 'i' }, + { "iq_tie2apb_inq0", 32, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 4, 'i' }, + { "iq_tie2apb_inq0_NOTRDY", 1, 0, 4, 'i' }, + { "iq_tie2apb_inq0_KILL", 1, 0, 4, 'o' }, + { "oq_tie2apb_outq0_Full", 1, 0, 5, 'i' }, + { "oq_tie2apb_outq0", 65, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 5, 'o' }, + { "oq_tie2apb_outq0_NOTRDY", 1, 0, 5, 'i' }, + { "oq_tie2apb_outq0_KILL", 1, 0, 5, 'o' } +}; + +enum xtensa_interface_id { + INTERFACE_ERI_RD_Out, + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Rdy, + INTERFACE_ERI_WR_Out, + INTERFACE_ERI_WR_In, + INTERFACE_iq_tie2apb_inq0_Empty, + INTERFACE_iq_tie2apb_inq0, + INTERFACE_iq_tie2apb_inq0_NOTRDY, + INTERFACE_iq_tie2apb_inq0_KILL, + INTERFACE_oq_tie2apb_outq0_Full, + INTERFACE_oq_tie2apb_outq0, + INTERFACE_oq_tie2apb_outq0_NOTRDY, + INTERFACE_oq_tie2apb_outq0_KILL +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table imm1_2N_tab */ +static const unsigned CONST_TBL_imm1_2N_tab_0[] = { + 0x1 & 0x7f, + 0x2 & 0x7f, + 0x4 & 0x7f, + 0x8 & 0x7f, + 0x10 & 0x7f, + 0x20 & 0x7f, + 0x40 & 0x7f, + 0, + 0 +}; + +/* constant table tab_selimm_7b */ +static const unsigned CONST_TBL_tab_selimm_7b_0[] = { + 0 & 0x7f, + 0x1 & 0x7f, + 0x2 & 0x7f, + 0x3 & 0x7f, + 0x8 & 0x7f, + 0x9 & 0x7f, + 0xa & 0x7f, + 0xb & 0x7f, + 0x10 & 0x7f, + 0x11 & 0x7f, + 0x20 & 0x7f, + 0x21 & 0x7f, + 0x22 & 0x7f, + 0x23 & 0x7f, + 0x3b & 0x7f, + 0x3c & 0x7f, + 0x3d & 0x7f, + 0x3e & 0x7f, + 0x3f & 0x7f, + 0x40 & 0x7f, + 0x41 & 0x7f, + 0x42 & 0x7f, + 0x43 & 0x7f, + 0x44 & 0x7f, + 0x45 & 0x7f, + 0x46 & 0x7f, + 0x47 & 0x7f, + 0x48 & 0x7f, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table tab_shflimm_7b */ +static const unsigned CONST_TBL_tab_shflimm_7b_0[] = { + 0x8 & 0x7f, + 0x1e & 0x7f, + 0 +}; + +/* constant table imm5_19_tab */ +static const unsigned CONST_TBL_imm5_19_tab_0[] = { + 0, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0x10, + 0x11, + 0x12, + 0x13, + 0x14, + 0x15, + 0x16, + 0x17, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table imm6_39_tab */ +static const unsigned CONST_TBL_imm6_39_tab_0[] = { + 0, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0x10, + 0x11, + 0x12, + 0x13, + 0x14, + 0x15, + 0x16, + 0x17, + 0x18, + 0x19, + 0x1a, + 0x1b, + 0x1c, + 0x1d, + 0x1e, + 0x1f, + 0x20, + 0x21, + 0x22, + 0x23, + 0x24, + 0x25, + 0x26, + 0x27, + 0x28, + 0x29, + 0x2a, + 0x2b, + 0x2c, + 0x2d, + 0x2e, + 0x2f, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table imm7_79_tab */ +static const unsigned CONST_TBL_imm7_79_tab_0[] = { + 0, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0x10, + 0x11, + 0x12, + 0x13, + 0x14, + 0x15, + 0x16, + 0x17, + 0x18, + 0x19, + 0x1a, + 0x1b, + 0x1c, + 0x1d, + 0x1e, + 0x1f, + 0x20, + 0x21, + 0x22, + 0x23, + 0x24, + 0x25, + 0x26, + 0x27, + 0x28, + 0x29, + 0x2a, + 0x2b, + 0x2c, + 0x2d, + 0x2e, + 0x2f, + 0x30, + 0x31, + 0x32, + 0x33, + 0x34, + 0x35, + 0x36, + 0x37, + 0x38, + 0x39, + 0x3a, + 0x3b, + 0x3c, + 0x3d, + 0x3e, + 0x3f, + 0x40, + 0x41, + 0x42, + 0x43, + 0x44, + 0x45, + 0x46, + 0x47, + 0x48, + 0x49, + 0x4a, + 0x4b, + 0x4c, + 0x4d, + 0x4e, + 0x4f, + 0x50, + 0x51, + 0x52, + 0x53, + 0x54, + 0x55, + 0x56, + 0x57, + 0x58, + 0x59, + 0x5a, + 0x5b, + 0x5c, + 0x5d, + 0x5e, + 0x5f, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table0 */ +static const unsigned CONST_TBL_xd_seli_table0_0[] = { + 0x60a10182, + 0x80e18284, + 0xa1220386, + 0xc1628488, + 0x42648890, + 0xc3668c98, + 0x446890a0, + 0x1e3868c, + 0x28301fbe, + 0x7ef9ebc, + 0xe7af1dba, + 0xc76e9cb8, + 0x466c98b0, + 0xc56a94a8, + 0x446890a0, + 0x82e58a94, + 0x80a10080, + 0xa0e18182, + 0xc0e18080, + 0xe1220182, + 0x1628284, + 0x1220080, + 0x21628182, + 0x41a30284, + 0x61e38386, + 0x60608080, + 0x80a10182, + 0xa0e18284, + 0x80608080, + 0xc0e18284, + 0x40608080, + 0xc1628488, + 0x28300080, + 0x2c3810a0, + 0x48300080, + 0x68708182, + 0x48708080, + 0x608080, + 0x46890a0, + 0x608080, + 0x40e18284, + 0x40608080, + 0x40608080, + 0x446890a0, + 0x40608080, + 0xc1628488, + 0x40608080, + 0x28300080, + 0x608080, + 0x40608080, + 0x40608080, + 0x40608080, + 0x40608080, + 0x40608080, + 0x40608080, + 0x40608080, + 0x40608080, + 0x40608080, + 0x446890a0, + 0x28206000, + 0x2c287020, + 0x4840a000, + 0x5860e081, + 0x80c10100, + 0x90e14181, + 0x5080c101, + 0x3850603f, + 0x70c14203, + 0x180fdf3d, + 0x9101c305, + 0xf7cf5e3b, + 0xb1424407, + 0xd78edd39, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table1 */ +static const unsigned CONST_TBL_xd_seli_table1_0[] = { + 0x8a122038, + 0x8c162848, + 0x8e1a3058, + 0x901e3868, + 0x982e58a9, + 0xa03e78e9, + 0xa84e992a, + 0x94264889, + 0xc68b121c, + 0xc4870a0c, + 0xc28301fb, + 0xc07ef9eb, + 0xb86ed9ab, + 0xb05eb96a, + 0xa84e992a, + 0x9c3668c9, + 0x901a3048, + 0x921e3858, + 0x98264868, + 0x9a2a5078, + 0x9c2e5889, + 0xa0326089, + 0xa2366899, + 0xa43a70a9, + 0xa63e78b9, + 0x8c122038, + 0x8e162848, + 0x901a3058, + 0x90162848, + 0x941e3868, + 0x900e1828, + 0x981e3868, + 0x84870818, + 0xa4c7891a, + 0x888b1028, + 0x8a8f1838, + 0x888f1828, + 0x84870a0c, + 0xa4c78b0e, + 0x88870a0c, + 0x8c8f1a2c, + 0x888f1a2c, + 0xc00e1828, + 0xe04e992a, + 0xc00e1828, + 0xc81e3868, + 0xc80e1828, + 0xc68b121c, + 0xc4870a0c, + 0xc2830028, + 0xc00e1828, + 0x880e1828, + 0x880e1828, + 0x880e1828, + 0x880e1828, + 0x880e1828, + 0x880e1828, + 0x880e1828, + 0xa84e992a, + 0x4860e10, + 0x24c68f12, + 0x88c1a20, + 0x898e1e28, + 0x101c3050, + 0x911e3458, + 0x9101c30, + 0x478d1624, + 0xb142440, + 0x45890e14, + 0xd182c50, + 0x43850603, + 0xf1c3460, + 0x4180fdf3, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table2 */ +static const unsigned CONST_TBL_xd_seli_table2_0[] = { + 0x78e1a305, + 0x8901e386, + 0x99222407, + 0xa9426488, + 0xe9c3668c, + 0x2a446890, + 0x6ac56a94, + 0xc982e58a, + 0x5ca93223, + 0x4c88f1a2, + 0x3c68b121, + 0x2c4870a0, + 0xebc76e9c, + 0xab466c98, + 0x6ac56a94, + 0xa03e78e, + 0xc982a508, + 0xd9a2e589, + 0x2a43e78c, + 0x3a64280d, + 0x4a84688e, + 0x8b052a10, + 0x9b256a91, + 0xab45ab12, + 0xbb65eb93, + 0x9921e386, + 0xa9422407, + 0xb9626488, + 0xc9826488, + 0xe9c2e58a, + 0xa9426488, + 0xe9c3668c, + 0x3868b102, + 0x3a6cb912, + 0x68c93204, + 0x78e97285, + 0x68c97284, + 0x2c40e182, + 0x2e44e992, + 0x4c816284, + 0x6cc1e386, + 0x6cc16284, + 0x2c4870a0, + 0x2e4c78b0, + 0x2c4870a0, + 0x6cc972a4, + 0x6cc972a4, + 0x5ca93223, + 0x4c88f1a2, + 0x3c68b121, + 0x2c4870a0, + 0x1c283004, + 0xc016284, + 0x68c16284, + 0x68c16284, + 0x68c16284, + 0x68c16284, + 0x68c16284, + 0x6ac56a94, + 0x3068a162, + 0x326ca972, + 0x60c942a4, + 0x68d962e4, + 0xd182c509, + 0xd992e549, + 0x70d182c5, + 0x64b95264, + 0x80f1c346, + 0x549911e3, + 0x911203c7, + 0x4478d162, + 0xa1324448, + 0x345890e1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table3 */ +static const unsigned CONST_TBL_xd_seli_table3_0[] = { + 0x9922240, + 0x8a942648, + 0xb962a50, + 0x8c982e58, + 0x90a03e78, + 0x94a84e99, + 0x98b05eb9, + 0x8e9c3668, + 0x27ce9b32, + 0xa6cc972a, + 0x25ca9322, + 0xa4c88f1a, + 0xa0c07ef9, + 0x9cb86ed9, + 0x98b05eb9, + 0x92a44689, + 0x10a03a70, + 0x91a23e78, + 0x98b056a9, + 0x19b25ab1, + 0x9ab45eb9, + 0x20c072e1, + 0xa1c276e9, + 0x22c47af1, + 0xa3c67ef9, + 0x8c982a50, + 0xd9a2e58, + 0x8e9c3260, + 0x90a03668, + 0x92a43e78, + 0x90a02e58, + 0x94a83e78, + 0x4888f18, + 0x14a8cf99, + 0x8909b30, + 0x89929f38, + 0x88909f38, + 0x84888f1a, + 0x94a8cf9b, + 0x8890972a, + 0x8a949f3a, + 0x88909f3a, + 0x84888f1a, + 0x94a8cf9b, + 0x88908f1a, + 0x8c989f3a, + 0x88909f3a, + 0x27ce9b32, + 0xa6cc972a, + 0x25ca9322, + 0xa4c88f1a, + 0x23c68b12, + 0xa2c4870a, + 0x21c28300, + 0xa0c01e38, + 0xa8d01e38, + 0x88901e38, + 0x88901e38, + 0x98b05eb9, + 0x64088e1e, + 0x7428ce9f, + 0xa8109c3a, + 0xe8919e3e, + 0x11203c70, + 0x51a13e74, + 0xc911203c, + 0x684f9d36, + 0x4a132444, + 0xe74d992e, + 0xcb15284c, + 0x664b9526, + 0x4c172c54, + 0xe549911e, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table4 */ +static const unsigned CONST_TBL_xd_seli_table4_0[] = { + 0x60b962a5, + 0x68c982e5, + 0x70d9a326, + 0x78e9c366, + 0x992a4468, + 0xb96ac56a, + 0xd9ab466c, + 0x890a03e7, + 0x529d2a34, + 0x4a8d09f3, + 0x427ce9b3, + 0x3a6cc972, + 0x1a2c4870, + 0xf9ebc76e, + 0xd9ab466c, + 0xa94a84e9, + 0xb14a84a9, + 0xb95aa4e9, + 0x9ebc6ed, + 0x11fbe72e, + 0x1a0c076e, + 0x628d0932, + 0x6a9d2972, + 0x72ad49b3, + 0x7abd69f3, + 0x80f9e366, + 0x890a03a7, + 0x911a23e7, + 0xa94a8468, + 0xb96ac4e9, + 0x992a4468, + 0xb96ac56a, + 0x2858a932, + 0xa95aad3a, + 0x50a94a34, + 0x58b96a74, + 0x58a94a74, + 0x2a4c8162, + 0xab4e856a, + 0x4a8d0264, + 0x5aad42e5, + 0x5aad4264, + 0x3868c162, + 0xb96ac56a, + 0x58a94264, + 0x78e9c366, + 0x58a94264, + 0x529d2a34, + 0x4a8d09f3, + 0x427ce9b3, + 0x3a6cc972, + 0x325ca932, + 0x2a4c88f1, + 0x223c68b1, + 0x1a2c4870, + 0x5aad4a74, + 0x58a94264, + 0x58a94264, + 0xd9ab466c, + 0x2e50a922, + 0xaf52ad2a, + 0x5aa14a44, + 0x5ea95a64, + 0xb15284c9, + 0xb55a94e9, + 0x5cb15284, + 0x56a53a54, + 0x64c172c5, + 0x4e951a13, + 0x6cd19305, + 0x4684f9d3, + 0x74e1b346, + 0x3e74d992, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table5 */ +static const unsigned CONST_TBL_xd_seli_table5_0[] = { + 0xa70d9a32, + 0xe78e9c36, + 0x280f9e3a, + 0x6890a03e, + 0x6a94a84e, + 0x6c98b05e, + 0x6e9cb86e, + 0xe992a446, + 0x362bd6ab, + 0xf5aad4a7, + 0xb529d2a3, + 0x74a8d09f, + 0x72a4c88f, + 0x70a0c07e, + 0x6e9cb86e, + 0xeb96ac56, + 0xad18b05a, + 0xed99b25e, + 0xf3a4c887, + 0x3425ca8b, + 0x74a6cc8f, + 0x3a30e0b3, + 0x7ab1e2b7, + 0xbb32e4bb, + 0xfbb3e6bf, + 0xe992a442, + 0x2a13a646, + 0x6a94a84a, + 0x6c98b056, + 0xed9ab45e, + 0x6c98b04e, + 0x6e9cb85e, + 0xb3068c97, + 0xbb16acd7, + 0x360c98ab, + 0x768d9aaf, + 0x768c98af, + 0xe3868c97, + 0xeb96acd7, + 0x668c98a7, + 0xe78e9caf, + 0x668c98af, + 0x72a4c81e, + 0x7ab4e85e, + 0x74a8d02e, + 0x76acd83e, + 0x76acd82e, + 0x362bd6ab, + 0xf5aad4a7, + 0xb529d2a3, + 0x74a8d09f, + 0x3427ce9b, + 0xf3a6cc97, + 0xb325ca93, + 0x72a4c88f, + 0x76acd8af, + 0x668c982e, + 0x668c982e, + 0x6e9cb86e, + 0xa3660c96, + 0xab762cd6, + 0x46ac18ac, + 0x66ec99ae, + 0xcd19305c, + 0xed59b15e, + 0x86cd1930, + 0x566c57ad, + 0xc74e1b34, + 0x15eb55a9, + 0x7cf1d38, + 0xd56a53a5, + 0x48501f3c, + 0x94e951a1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table6 */ +static const unsigned CONST_TBL_xd_seli_table6_0[] = { + 0x4280f9e3, + 0x46890a03, + 0x4a911a24, + 0x4e992a44, + 0x5eb96ac5, + 0x6ed9ab46, + 0x7ef9ebc7, + 0x56a94a84, + 0xbb72ddab, + 0xb76acd8a, + 0xb362bd6a, + 0xaf5aad4a, + 0x9f3a6cc9, + 0x8f1a2c48, + 0x7ef9ebc7, + 0x66c98b05, + 0x7af1cb86, + 0x7ef9dba6, + 0xb76aad49, + 0xbb72bd6a, + 0xbf7acd8a, + 0xf3e38f0d, + 0xf7eb9f2d, + 0xfbf3af4d, + 0xfffbbf6d, + 0x5ab15aa4, + 0x5eb96ac5, + 0x62c17ae5, + 0x76e9cb86, + 0x7ef9ebc6, + 0x6ed9ab46, + 0x7ef9ebc7, + 0x9f3878e9, + 0xdfb97aed, + 0xbb70e9cb, + 0xbf78f9eb, + 0xbf78e9cb, + 0x9f3a6cc1, + 0xdfbb6ec5, + 0xb76acd83, + 0xbf7aedc3, + 0xbf7aedc3, + 0x9f3a6cc9, + 0xdfbb6ecd, + 0xaf5aad4a, + 0xbf7aedcb, + 0xbf7aedcb, + 0xbb72ddab, + 0xb76acd8a, + 0xb362bd6a, + 0xaf5aad4a, + 0xab529d2a, + 0xa74a8d09, + 0xa3427ce9, + 0x9f3a6cc9, + 0xbf7aedcb, + 0x3e78e9c3, + 0x3e78e9c3, + 0x7ef9ebc7, + 0x9e3e70e9, + 0xdebf72ed, + 0xbc7ae1cb, + 0xbe7ee9db, + 0x7cf1d386, + 0x7ef5db96, + 0x407cf1d3, + 0xbd76e5bb, + 0x448501f3, + 0xb96ed59b, + 0x488d1214, + 0xb566c57a, + 0x4c952234, + 0xb15eb55a, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table7 */ +static const unsigned CONST_TBL_xd_seli_table7_0[] = { + 0x64a911a2, + 0x84e992a4, + 0xa52a13a6, + 0xc56a94a8, + 0x466c98b0, + 0xc76e9cb8, + 0x4870a0c0, + 0x5eb96ac, + 0x2c382fde, + 0xbf7aedc, + 0xebb72dda, + 0xcb76acd8, + 0x4a74a8d0, + 0xc972a4c8, + 0x4870a0c0, + 0x86ed9ab4, + 0x88b120c0, + 0xa8f1a1c2, + 0xccf9b0e0, + 0xed3a31e2, + 0xd7ab2e4, + 0x1220080, + 0x21628182, + 0x41a30284, + 0x61e38386, + 0x666c98b0, + 0x86ad19b2, + 0xa6ed9ab4, + 0x8870a0c0, + 0xc8f1a2c4, + 0x4870a0c0, + 0xc972a4c8, + 0x2a340890, + 0x2e3c18b0, + 0x4c3810a0, + 0x6c7891a2, + 0x4c7890a0, + 0x2648890, + 0x66c98b0, + 0x46890a0, + 0x44e992a4, + 0x446890a0, + 0x42648890, + 0x466c98b0, + 0x446890a0, + 0xc56a94a8, + 0x446890a0, + 0x2c382fde, + 0xbf7aedc, + 0xebb72dda, + 0xcb76acd8, + 0xab362bd6, + 0x8af5aad4, + 0x6ab529d2, + 0x4a74a8d0, + 0x4c78b0e0, + 0x446890a0, + 0x4870a0c0, + 0x4c78b0e0, + 0x2a246810, + 0x2e2c7830, + 0x4c48b020, + 0x5c68f0a1, + 0x88d12140, + 0x98f161c1, + 0x5488d121, + 0x3c58705f, + 0x74c95223, + 0x1c17ef5d, + 0x9509d325, + 0xfbd76e5b, + 0xb54a5427, + 0xdb96ed59, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table8 */ +static const unsigned CONST_TBL_xd_seli_table8_0[] = { + 0xaa52a13a, + 0xac56a94a, + 0xae5ab15a, + 0xb05eb96a, + 0xb86ed9ab, + 0xc07ef9eb, + 0xc88f1a2c, + 0xb466c98b, + 0xe6cb931e, + 0xe4c78b0e, + 0xe2c382fd, + 0xe0bf7aed, + 0xd8af5aad, + 0xd09f3a6c, + 0xc88f1a2c, + 0xbc76e9cb, + 0xd09b324c, + 0xd29f3a5c, + 0xf8e7cb6e, + 0xfaebd37e, + 0xfcefdb8f, + 0xa0326089, + 0xa2366899, + 0xa43a70a9, + 0xa63e78b9, + 0xbc72e1bb, + 0xbe76e9cb, + 0xc07af1db, + 0xd0972a4c, + 0xd49f3a6c, + 0xd08f1a2c, + 0xd89f3a6c, + 0x94a74899, + 0xb4e7c99b, + 0xa8cb912a, + 0xaacf993a, + 0xa8cf992a, + 0x94a74a8d, + 0xb4e7cb8f, + 0xa8c78b0e, + 0xaccf9b2e, + 0xa8cf9b2e, + 0xd02e58a9, + 0xf06ed9ab, + 0xe04e992a, + 0xe85eb96a, + 0xe84e992a, + 0xe6cb931e, + 0xe4c78b0e, + 0xe2c382fd, + 0xe0bf7aed, + 0xdebb72dd, + 0xdcb76acd, + 0xdab362bd, + 0xd8af5aad, + 0xe8cf9b2e, + 0xa84e992a, + 0xc88f1a2c, + 0xe8cf9b2e, + 0x14a64e91, + 0x34e6cf93, + 0x28cc9b22, + 0xa9ce9f2a, + 0x509d3254, + 0xd19f365c, + 0x29509d32, + 0x67cd9726, + 0x2b54a542, + 0x65c98f16, + 0x2d58ad52, + 0x63c58705, + 0x2f5cb562, + 0x61c17ef5, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table9 */ +static const unsigned CONST_TBL_xd_seli_table9_0[] = { + 0x7ae5ab15, + 0x8b05eb96, + 0x9b262c17, + 0xab466c98, + 0xebc76e9c, + 0x2c4870a0, + 0x6cc972a4, + 0xcb86ed9a, + 0x5ead3a33, + 0x4e8cf9b2, + 0x3e6cb931, + 0x2e4c78b0, + 0xedcb76ac, + 0xad4a74a8, + 0x6cc972a4, + 0xc07ef9e, + 0xcd8ab528, + 0xddaaf5a9, + 0x284fffbc, + 0x3860203d, + 0x488060be, + 0x8b052a10, + 0x9b256a91, + 0xab45ab12, + 0xbb65eb93, + 0x1c27ef9e, + 0x2c48301f, + 0x3c6870a0, + 0xcd8a74a8, + 0xedcaf5aa, + 0xad4a74a8, + 0xedcb76ac, + 0xb96ab50a, + 0xbb6ebd1a, + 0x6acd3a14, + 0x7aed7a95, + 0x6acd7a94, + 0xad42e58a, + 0xaf46ed9a, + 0x4e856a94, + 0x6ec5eb96, + 0x6ec56a94, + 0xad4a74a8, + 0xaf4e7cb8, + 0x2e4c78b0, + 0x6ecd7ab4, + 0x6ecd7ab4, + 0x5ead3a33, + 0x4e8cf9b2, + 0x3e6cb931, + 0x2e4c78b0, + 0x1e2c382f, + 0xe0bf7ae, + 0xfdebb72d, + 0xedcb76ac, + 0x6ecd7ab4, + 0x6ac56a94, + 0x6cc972a4, + 0x6ecd7ab4, + 0xb16aa56a, + 0xb36ead7a, + 0x62cd4ab4, + 0x6add6af4, + 0xd58ad529, + 0xdd9af569, + 0x72d58ad5, + 0x66bd5a74, + 0x82f5cb56, + 0x569d19f3, + 0x93160bd7, + 0x467cd972, + 0xa3364c58, + 0x365c98f1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table10 */ +static const unsigned CONST_TBL_xd_seli_table10_0[] = { + 0x19b262c1, + 0x9ab466c9, + 0x1bb66ad1, + 0x9cb86ed9, + 0xa0c07ef9, + 0xa4c88f1a, + 0xa8d09f3a, + 0x9ebc76e9, + 0x37eedbb3, + 0xb6ecd7ab, + 0x35ead3a3, + 0xb4e8cf9b, + 0xb0e0bf7a, + 0xacd8af5a, + 0xa8d09f3a, + 0xa2c4870a, + 0x30e0bb72, + 0xb1e2bf7a, + 0x88901628, + 0x9921a30, + 0x8a941e38, + 0x20c072e1, + 0xa1c276e9, + 0x22c47af1, + 0xa3c67ef9, + 0xa4c88b12, + 0x25ca8f1a, + 0xa6cc9322, + 0xb0e0b76a, + 0xb2e4bf7a, + 0xb0e0af5a, + 0xb4e8bf7a, + 0xc98af58, + 0x1cb8efd9, + 0x18b0dbb1, + 0x99b2dfb9, + 0x98b0dfb9, + 0x8c98af5a, + 0x9cb8efdb, + 0x98b0d7ab, + 0x9ab4dfbb, + 0x98b0dfbb, + 0x8c98af5a, + 0x9cb8efdb, + 0x98b0cf9b, + 0x9cb8dfbb, + 0x98b0dfbb, + 0x37eedbb3, + 0xb6ecd7ab, + 0x35ead3a3, + 0xb4e8cf9b, + 0x33e6cb93, + 0xb2e4c78b, + 0x31e2c382, + 0xb0e0bf7a, + 0xb8f0dfbb, + 0xb8f05eb9, + 0xa8d09f3a, + 0xb8f0dfbb, + 0x6c18ae5e, + 0x7c38eedf, + 0xb830dcbb, + 0xf8b1debf, + 0x3160bd72, + 0x71e1bf76, + 0xd93160bd, + 0x786fddb7, + 0x5a3364c5, + 0xf76dd9af, + 0xdb3568cd, + 0x766bd5a7, + 0x5c376cd5, + 0xf569d19f, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table11 */ +static const unsigned CONST_TBL_xd_seli_table11_0[] = { + 0xe1bb66ad, + 0xe9cb86ed, + 0xf1dba72e, + 0xf9ebc76e, + 0x1a2c4870, + 0x3a6cc972, + 0x5aad4a74, + 0xa0c07ef, + 0xd39f2e3c, + 0xcb8f0dfb, + 0xc37eedbb, + 0xbb6ecd7a, + 0x9b2e4c78, + 0x7aedcb76, + 0x5aad4a74, + 0x2a4c88f1, + 0xb34e8cb9, + 0xbb5eacf9, + 0x88e9c2e5, + 0x90f9e326, + 0x990a0366, + 0x628d0932, + 0x6a9d2972, + 0x72ad49b3, + 0x7abd69f3, + 0x427ce972, + 0x4a8d09b3, + 0x529d29f3, + 0xab4e8c78, + 0xbb6eccf9, + 0x9b2e4c78, + 0xbb6ecd7a, + 0x68d9ab36, + 0xe9dbaf3e, + 0xd1ab4e3c, + 0xd9bb6e7c, + 0xd9ab4e7c, + 0x6acd8366, + 0xebcf876e, + 0xcb8f066c, + 0xdbaf46ed, + 0xdbaf466c, + 0x78e9c366, + 0xf9ebc76e, + 0xd9ab466c, + 0xf9ebc76e, + 0xd9ab466c, + 0xd39f2e3c, + 0xcb8f0dfb, + 0xc37eedbb, + 0xbb6ecd7a, + 0xb35ead3a, + 0xab4e8cf9, + 0xa33e6cb9, + 0x9b2e4c78, + 0xdbaf4e7c, + 0xdbaf4e7c, + 0x5aad4a74, + 0xdbaf4e7c, + 0x6ed1ab26, + 0xefd3af2e, + 0xdba34e4c, + 0xdfab5e6c, + 0xb3568cd9, + 0xb75e9cf9, + 0xddb3568c, + 0xd7a73e5c, + 0xe5c376cd, + 0xcf971e1b, + 0xedd3970d, + 0xc786fddb, + 0xf5e3b74e, + 0xbf76dd9a, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table12 */ +static const unsigned CONST_TBL_xd_seli_table12_0[] = { + 0xaf1dba72, + 0xef9ebc76, + 0x301fbe7a, + 0x70a0c07e, + 0x72a4c88f, + 0x74a8d09f, + 0x76acd8af, + 0xf1a2c487, + 0x3e3bf6eb, + 0xfdbaf4e7, + 0xbd39f2e3, + 0x7cb8f0df, + 0x7ab4e8cf, + 0x78b0e0bf, + 0x76acd8af, + 0xf3a6cc97, + 0xbd38f0db, + 0xfdb9f2df, + 0xeb94a846, + 0x2c15aa4a, + 0x6c96ac4e, + 0x3a30e0b3, + 0x7ab1e2b7, + 0xbb32e4bb, + 0xfbb3e6bf, + 0xf5aad4a3, + 0x362bd6a7, + 0x76acd8ab, + 0x7cb8f0d7, + 0xfdbaf4df, + 0x7cb8f0cf, + 0x7ebcf8df, + 0xb70e9cb7, + 0xbf1ebcf7, + 0x3e1cb8eb, + 0x7e9dbaef, + 0x7e9cb8ef, + 0xe78e9cb7, + 0xef9ebcf7, + 0x6e9cb8e7, + 0xef9ebcef, + 0x6e9cb8ef, + 0x76acd83e, + 0x7ebcf87e, + 0x7cb8f06e, + 0x7ebcf87e, + 0x7ebcf86e, + 0x3e3bf6eb, + 0xfdbaf4e7, + 0xbd39f2e3, + 0x7cb8f0df, + 0x3c37eedb, + 0xfbb6ecd7, + 0xbb35ead3, + 0x7ab4e8cf, + 0x7ebcf8ef, + 0x7ebcf8ef, + 0x76acd8af, + 0x7ebcf8ef, + 0xa76e1cb6, + 0xaf7e3cf6, + 0x4ebc38ec, + 0x6efcb9ee, + 0xdd3970dd, + 0xfd79f1df, + 0x8edd3970, + 0x5e7c77ed, + 0xcf5e3b74, + 0x1dfb75e9, + 0xfdf3d78, + 0xdd7a73e5, + 0x50603f7c, + 0x9cf971e1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_seli_table13 */ +static const unsigned CONST_TBL_xd_seli_table13_0[] = { + 0x8301fbe7, + 0x870a0c07, + 0x8b121c28, + 0x8f1a2c48, + 0x9f3a6cc9, + 0xaf5aad4a, + 0xbf7aedcb, + 0x972a4c88, + 0xfbf3dfaf, + 0xf7ebcf8e, + 0xf3e3bf6e, + 0xefdbaf4e, + 0xdfbb6ecd, + 0xcf9b2e4c, + 0xbf7aedcb, + 0xa74a8d09, + 0xfbf3cf8e, + 0xfffbdfae, + 0x76e9ab45, + 0x7af1bb66, + 0x7ef9cb86, + 0xf3e38f0d, + 0xf7eb9f2d, + 0xfbf3af4d, + 0xfffbbf6d, + 0xbb72ddaa, + 0xbf7aedcb, + 0xc382fdeb, + 0xf7ebcf8e, + 0xfffbefce, + 0xefdbaf4e, + 0xfffbefcf, + 0xbf78f9eb, + 0xfff9fbef, + 0xfbf1ebcf, + 0xfff9fbef, + 0xfff9ebcf, + 0xbf7aedc3, + 0xfffbefc7, + 0xf7ebcf87, + 0xfffbefc7, + 0xfffbefc7, + 0xbf7aedcb, + 0xfffbefcf, + 0xefdbaf4e, + 0xfffbefcf, + 0xfffbefcf, + 0xfbf3dfaf, + 0xf7ebcf8e, + 0xf3e3bf6e, + 0xefdbaf4e, + 0xebd39f2e, + 0xe7cb8f0d, + 0xe3c37eed, + 0xdfbb6ecd, + 0xfffbefcf, + 0xfffbefcf, + 0xbf7aedcb, + 0xfffbefcf, + 0xbe7ef1eb, + 0xfefff3ef, + 0xfcfbe3cf, + 0xfeffebdf, + 0xfdf3d78e, + 0xfff7df9e, + 0x80fdf3d7, + 0xfdf7e7bf, + 0x850603f7, + 0xf9efd79f, + 0x890e1418, + 0xf5e7c77e, + 0x8d162438, + 0xf1dfb75e, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table xd_shfli_table0 */ +static const unsigned CONST_TBL_xd_shfli_table0_0[] = { + 0x440c2040, + 0x4c2ca248, + 0x544d2450, + 0x5c6da658, + 0x648e2860, + 0x6caeaa68, + 0x74cf2c70, + 0x7cefae78, + 0xc60400c2, + 0x401c6144, + 0x4c2ca248, + 0x544d2450, + 0xc2040040, + 0xe2860860, + 0x400c2040, + 0x608e2860, + 0x440c2040, + 0x648e2860, + 0x44040040, + 0xc60c20c2, + 0x400c2040, + 0x441c6144, + 0x440c2040, + 0x4c2ca248, + 0xfaf7cffe, + 0x78ffef7c, + 0x7cefae78, + 0x500c2040, + 0x600c2040, + 0x440c2040, + 0x82841800, + 0x648e2860, + 0 +}; + +/* constant table xd_shfli_table1 */ +static const unsigned CONST_TBL_xd_shfli_table1_0[] = { + 0x20401c61, + 0xa2483ce3, + 0x24505d65, + 0xa6587de7, + 0x28609e69, + 0xaa68beeb, + 0x2c70df6d, + 0xae78ffef, + 0x82ca1441, + 0xe34c0c20, + 0x20403ce3, + 0xa6585d65, + 0x41440c20, + 0x49648e28, + 0x61440c20, + 0x69648e28, + 0x20401c61, + 0x28609e69, + 0x82481441, + 0xa2ca1c61, + 0xa2480c20, + 0xe34c1c61, + 0x20401c61, + 0xa2483ce3, + 0x4df6e78e, + 0x6d74efae, + 0x2c70ffef, + 0x28604d24, + 0x24508e28, + 0xa2481c61, + 0x59048c38, + 0xaa689e69, + 0 +}; + +/* constant table xd_shfli_table2 */ +static const unsigned CONST_TBL_xd_shfli_table2_0[] = { + 0x1c61440c, + 0x3ce34c2c, + 0x5d65544d, + 0x7de75c6d, + 0x9e69648e, + 0xbeeb6cae, + 0xdf6d74cf, + 0xffef7cef, + 0x34c3ce24, + 0x2ca2483c, + 0x1c61440c, + 0x7de75c6d, + 0x1c61c614, + 0x9e69e696, + 0x1c61441c, + 0x9e69649e, + 0x1c61440c, + 0x9e69648e, + 0x34c34c24, + 0x3ce3ce2c, + 0x2ca2482c, + 0x3ce34c3c, + 0x1c61440c, + 0x3ce34c2c, + 0xc70cf2d7, + 0xcf2c70df, + 0xdf6d74cf, + 0xcf2c708e, + 0xcf2c704d, + 0x4d24502c, + 0x9c798694, + 0xbeeb6cae, + 0 +}; + +/* constant table xd_shfli_table3 */ +static const unsigned CONST_TBL_xd_shfli_table3_0[] = { + 0x440c2040, + 0x4c2ca248, + 0x544d2450, + 0x5c6da658, + 0x648e2860, + 0x6caeaa68, + 0x74cf2c70, + 0x7cefae78, + 0xd64504d2, + 0x505d6554, + 0x5c6da658, + 0x440c2040, + 0xca248248, + 0xeaa68a68, + 0x482ca248, + 0x68aeaa68, + 0x4c2ca248, + 0x6caeaa68, + 0x54450450, + 0xd64d24d2, + 0x504d2450, + 0x545d6554, + 0x544d2450, + 0x5c6da658, + 0xeab6cbee, + 0x68beeb6c, + 0x6caeaa68, + 0x541c6144, + 0x641c6144, + 0x585d6554, + 0x8aa49a08, + 0x74cf2c70, + 0 +}; + +/* constant table xd_shfli_table4 */ +static const unsigned CONST_TBL_xd_shfli_table4_0[] = { + 0x20401c61, + 0xa2483ce3, + 0x24505d65, + 0xa6587de7, + 0x28609e69, + 0xaa68beeb, + 0x2c70df6d, + 0xae78ffef, + 0x86da5545, + 0xe75c4d24, + 0x24507de7, + 0xa2481c61, + 0xc34c2ca2, + 0xcb6caeaa, + 0xe34c2ca2, + 0xeb6caeaa, + 0xa2483ce3, + 0xaa68beeb, + 0x86585545, + 0xa6da5d65, + 0xa6584d24, + 0xe75c5d65, + 0x24505d65, + 0xa6587de7, + 0x49e6a68a, + 0x6964aeaa, + 0x2860beeb, + 0x69645d65, + 0x65549e69, + 0x28606da6, + 0xdb0cacba, + 0xae78df6d, + 0 +}; + +/* constant table xd_shfli_table5 */ +static const unsigned CONST_TBL_xd_shfli_table5_0[] = { + 0x1c61440c, + 0x3ce34c2c, + 0x5d65544d, + 0x7de75c6d, + 0x9e69648e, + 0xbeeb6cae, + 0xdf6d74cf, + 0xffef7cef, + 0x75c7de65, + 0x6da6587d, + 0x5d65544d, + 0x3ce34c2c, + 0x3ce3ce34, + 0xbeebeeb6, + 0x3ce34c3c, + 0xbeeb6cbe, + 0x3ce34c2c, + 0xbeeb6cae, + 0x75c75c65, + 0x7de7de6d, + 0x6da6586d, + 0x7de75c7d, + 0x5d65544d, + 0x7de75c6d, + 0x8608e296, + 0x8e28609e, + 0x9e69648e, + 0xdf6d749e, + 0xdf6d745d, + 0x9e69648e, + 0xbcfb8eb4, + 0xffef7cef, + 0 +}; + +/* constant table xd_shfli_table6 */ +static const unsigned CONST_TBL_xd_shfli_table6_0[] = { + 0x440c2040, + 0x4c2ca248, + 0x544d2450, + 0x5c6da658, + 0x648e2860, + 0x6caeaa68, + 0x74cf2c70, + 0x7cefae78, + 0xe68608e2, + 0x609e6964, + 0x6caeaa68, + 0x74cf2c70, + 0xd2450450, + 0xf2c70c70, + 0x504d2450, + 0x70cf2c70, + 0x544d2450, + 0x74cf2c70, + 0x64860860, + 0xe68e28e2, + 0x608e2860, + 0x649e6964, + 0x648e2860, + 0x6caeaa68, + 0xda75c7de, + 0x587de75c, + 0x5c6da658, + 0x582ca248, + 0x682ca248, + 0x70aeaa68, + 0x92c51c10, + 0x440c2040, + 0 +}; + +/* constant table xd_shfli_table7 */ +static const unsigned CONST_TBL_xd_shfli_table7_0[] = { + 0x20401c61, + 0xa2483ce3, + 0x24505d65, + 0xa6587de7, + 0x28609e69, + 0xaa68beeb, + 0x2c70df6d, + 0xae78ffef, + 0x8aea9649, + 0xeb6c8e28, + 0x2860beeb, + 0xae78df6d, + 0x45544d24, + 0x4d74cf2c, + 0x65544d24, + 0x6d74cf2c, + 0x24505d65, + 0x2c70df6d, + 0x8a689649, + 0xaaea9e69, + 0xaa688e28, + 0xeb6c9e69, + 0x28609e69, + 0xaa68beeb, + 0x45d66586, + 0x65546da6, + 0x24507de7, + 0xaa686da6, + 0xa658aeaa, + 0x6d74cf2c, + 0x5d14cd3c, + 0xa2481c61, + 0 +}; + +/* constant table xd_shfli_table8 */ +static const unsigned CONST_TBL_xd_shfli_table8_0[] = { + 0x1c61440c, + 0x3ce34c2c, + 0x5d65544d, + 0x7de75c6d, + 0x9e69648e, + 0xbeeb6cae, + 0xdf6d74cf, + 0xffef7cef, + 0xb6cbeea6, + 0xaeaa68be, + 0x9e69648e, + 0xffef7cef, + 0x5d65d655, + 0xdf6df6d7, + 0x5d65545d, + 0xdf6d74df, + 0x5d65544d, + 0xdf6d74cf, + 0xb6cb6ca6, + 0xbeebeeae, + 0xaeaa68ae, + 0xbeeb6cbe, + 0x9e69648e, + 0xbeeb6cae, + 0x4504d255, + 0x4d24505d, + 0x5d65544d, + 0xefae78ae, + 0xefae786d, + 0xefae78df, + 0xdd7d96d5, + 0x3ce34c2c, + 0 +}; + +/* constant table xd_shfli_table9 */ +static const unsigned CONST_TBL_xd_shfli_table9_0[] = { + 0x440c2040, + 0x4c2ca248, + 0x544d2450, + 0x5c6da658, + 0x648e2860, + 0x6caeaa68, + 0x74cf2c70, + 0x7cefae78, + 0xf6c70cf2, + 0x70df6d74, + 0x7cefae78, + 0x648e2860, + 0xda658658, + 0xfae78e78, + 0x586da658, + 0x78efae78, + 0x5c6da658, + 0x7cefae78, + 0x74c70c70, + 0xf6cf2cf2, + 0x70cf2c70, + 0x74df6d74, + 0x74cf2c70, + 0x7cefae78, + 0xca34c3ce, + 0x483ce34c, + 0x4c2ca248, + 0x5c3ce34c, + 0x6c3ce34c, + 0x5c3ce34c, + 0x9ae59e18, + 0x544d2450, + 0 +}; + +/* constant table xd_shfli_table10 */ +static const unsigned CONST_TBL_xd_shfli_table10_0[] = { + 0x20401c61, + 0xa2483ce3, + 0x24505d65, + 0xa6587de7, + 0x28609e69, + 0xaa68beeb, + 0x2c70df6d, + 0xae78ffef, + 0x8efad74d, + 0xef7ccf2c, + 0x2c70ffef, + 0xaa689e69, + 0xc75c6da6, + 0xcf7cefae, + 0xe75c6da6, + 0xef7cefae, + 0xa6587de7, + 0xae78ffef, + 0x8e78d74d, + 0xaefadf6d, + 0xae78cf2c, + 0xef7cdf6d, + 0x2c70df6d, + 0xae78ffef, + 0x41c62482, + 0x61442ca2, + 0x20403ce3, + 0xeb6c7de7, + 0xe75cbeeb, + 0xeb6c7de7, + 0xdf1cedbe, + 0xa6585d65, + 0 +}; + +/* constant table xd_shfli_table11 */ +static const unsigned CONST_TBL_xd_shfli_table11_0[] = { + 0x1c61440c, + 0x3ce34c2c, + 0x5d65544d, + 0x7de75c6d, + 0x9e69648e, + 0xbeeb6cae, + 0xdf6d74cf, + 0xffef7cef, + 0xf7cffee7, + 0xefae78ff, + 0xdf6d74cf, + 0xbeeb6cae, + 0x7de7de75, + 0xffeffef7, + 0x7de75c7d, + 0xffef7cff, + 0x7de75c6d, + 0xffef7cef, + 0xf7cf7ce7, + 0xffeffeef, + 0xefae78ef, + 0xffef7cff, + 0xdf6d74cf, + 0xffef7cef, + 0x400c214, + 0xc20401c, + 0x1c61440c, + 0xffef7cbe, + 0xffef7c7d, + 0xffef7cbe, + 0xfdff9ef5, + 0x7de75c6d, + 0 +}; + +/* constant table bbe_ltrxnimm_tab */ +static const unsigned CONST_TBL_bbe_ltrxnimm_tab_0[] = { + 0, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0x10, + 0x11, + 0x12, + 0x13, + 0x14, + 0x15, + 0x16, + 0x17, + 0x18, + 0x19, + 0x1a, + 0x1b, + 0x1c, + 0x1d, + 0x1e, + 0x1f, + 0x20, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table bbe_ltrxn_2imm_tab */ +static const unsigned CONST_TBL_bbe_ltrxn_2imm_tab_0[] = { + 0, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0x10, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table bbe_ltrx2nimm_tab */ +static const unsigned CONST_TBL_bbe_ltrx2nimm_tab_0[] = { + 0, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0x10, + 0x11, + 0x12, + 0x13, + 0x14, + 0x15, + 0x16, + 0x17, + 0x18, + 0x19, + 0x1a, + 0x1b, + 0x1c, + 0x1d, + 0x1e, + 0x1f, + 0x20, + 0x21, + 0x22, + 0x23, + 0x24, + 0x25, + 0x26, + 0x27, + 0x28, + 0x29, + 0x2a, + 0x2b, + 0x2c, + 0x2d, + 0x2e, + 0x2f, + 0x30, + 0x31, + 0x32, + 0x33, + 0x34, + 0x35, + 0x36, + 0x37, + 0x38, + 0x39, + 0x3a, + 0x3b, + 0x3c, + 0x3d, + 0x3e, + 0x3f, + 0x40, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table es_dist8 */ +static const unsigned CONST_TBL_es_dist8_0[] = { + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 & 0xffff, + 0x1 & 0xffff, + 0x3 & 0xffff, + 0x7 & 0xffff, + 0xf & 0xffff, + 0x11e & 0xffff, + 0x33c & 0xffff, + 0x778 & 0xffff, + 0xff0 & 0xffff, + 0x1ee0 & 0xffff, + 0x3cc0 & 0xffff, + 0x7880 & 0xffff, + 0 +}; + +/* constant table es_dist4 */ +static const unsigned CONST_TBL_es_dist4_0[] = { + 0x3c0 & 0xffff, + 0x1680 & 0xffff, + 0x3c00 & 0xffff, + 0x6801 & 0xffff, + 0xc003 & 0xffff, + 0x8016 & 0xffff, + 0x3c & 0xffff, + 0x168 & 0xffff, + 0x3c0 & 0xffff, + 0x1680 & 0xffff, + 0x3c00 & 0xffff, + 0x6801 & 0xffff, + 0xc003 & 0xffff, + 0x8016 & 0xffff, + 0x3c & 0xffff, + 0x168 & 0xffff, + 0 +}; + +/* constant table es_dist2 */ +static const unsigned CONST_TBL_es_dist2_0[] = { + 0x1818 & 0xffff, + 0x6060 & 0xffff, + 0x8181 & 0xffff, + 0xe06 & 0xffff, + 0x3818 & 0xffff, + 0x6060 & 0xffff, + 0x81c1 & 0xffff, + 0x70e & 0xffff, + 0x1c38 & 0xffff, + 0x7060 & 0xffff, + 0x8181 & 0xffff, + 0xe06 & 0xffff, + 0x381c & 0xffff, + 0x6070 & 0xffff, + 0x8181 & 0xffff, + 0x606 & 0xffff, + 0 +}; + +/* constant table es_dist1 */ +static const unsigned CONST_TBL_es_dist1_0[] = { + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0 +}; + +/* constant table et_dist8 */ +static const unsigned CONST_TBL_et_dist8_0[] = { + 0xc00 & 0xffff, + 0x1800 & 0xffff, + 0x3000 & 0xffff, + 0x6000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 & 0xffff, + 0x1 & 0xffff, + 0x3 & 0xffff, + 0x6 & 0xffff, + 0xc & 0xffff, + 0x18 & 0xffff, + 0x30 & 0xffff, + 0x160 & 0xffff, + 0x3c0 & 0xffff, + 0x680 & 0xffff, + 0 +}; + +/* constant table et_dist4 */ +static const unsigned CONST_TBL_et_dist4_0[] = { + 0x8020 & 0xffff, + 0x40 & 0xffff, + 0x180 & 0xffff, + 0x200 & 0xffff, + 0x401 & 0xffff, + 0x1802 & 0xffff, + 0x2004 & 0xffff, + 0x4018 & 0xffff, + 0x8020 & 0xffff, + 0x40 & 0xffff, + 0x180 & 0xffff, + 0x200 & 0xffff, + 0x401 & 0xffff, + 0x1802 & 0xffff, + 0x2004 & 0xffff, + 0x4018 & 0xffff, + 0 +}; + +/* constant table et_dist2 */ +static const unsigned CONST_TBL_et_dist2_0[] = { + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8c21 & 0xffff, + 0x1842 & 0xffff, + 0x218c & 0xffff, + 0x4318 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0x3184 & 0xffff, + 0x4218 & 0xffff, + 0x8c31 & 0xffff, + 0x1842 & 0xffff, + 0 +}; + +/* constant table et_dist1 */ +static const unsigned CONST_TBL_et_dist1_0[] = { + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0 +}; + +/* constant table st_dist8 */ +static const unsigned CONST_TBL_st_dist8_0[] = { + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 & 0xffff, + 0x1 & 0xffff, + 0x3 & 0xffff, + 0x7 & 0xffff, + 0xf & 0xffff, + 0x11e & 0xffff, + 0x33c & 0xffff, + 0x778 & 0xffff, + 0xff0 & 0xffff, + 0x1ee0 & 0xffff, + 0x3cc0 & 0xffff, + 0x7880 & 0xffff, + 0 +}; + +/* constant table st_dist4 */ +static const unsigned CONST_TBL_st_dist4_0[] = { + 0x3c0 & 0xffff, + 0x1680 & 0xffff, + 0x3c00 & 0xffff, + 0x6801 & 0xffff, + 0xc003 & 0xffff, + 0x8016 & 0xffff, + 0x3c & 0xffff, + 0x168 & 0xffff, + 0x3c0 & 0xffff, + 0x1680 & 0xffff, + 0x3c00 & 0xffff, + 0x6801 & 0xffff, + 0xc003 & 0xffff, + 0x8016 & 0xffff, + 0x3c & 0xffff, + 0x168 & 0xffff, + 0 +}; + +/* constant table st_dist2 */ +static const unsigned CONST_TBL_st_dist2_0[] = { + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0 +}; + +/* constant table st_dist1 */ +static const unsigned CONST_TBL_st_dist1_0[] = { + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 +}; + +/* constant table re_dist_sel */ +static const unsigned CONST_TBL_re_dist_sel_0[] = { + 0x100 & 0xffff, + 0x1010 & 0xffff, + 0x4444 & 0xffff, + 0xaaaa & 0xffff, + 0 +}; + +/* constant table rs_dist_sel */ +static const unsigned CONST_TBL_rs_dist_sel_0[] = { + 0x300 & 0xffff, + 0x3030 & 0xffff, + 0xcccc & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table rt_dist_sel */ +static const unsigned CONST_TBL_rt_dist_sel_0[] = { + 0xf00 & 0xffff, + 0xf0f0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table r64_dist_sel */ +static const unsigned CONST_TBL_r64_dist_sel_0[] = { + 0xff00 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table align_dist8 */ +static const unsigned CONST_TBL_align_dist8_0[] = { + 0 & 0xffff, + 0x101 & 0xffff, + 0x303 & 0xffff, + 0x707 & 0xffff, + 0xf0f & 0xffff, + 0x1f1f & 0xffff, + 0x3f3f & 0xffff, + 0x7f7f & 0xffff, + 0xffff & 0xffff, + 0xfefe & 0xffff, + 0xfcfc & 0xffff, + 0xf8f8 & 0xffff, + 0xf0f0 & 0xffff, + 0xe0e0 & 0xffff, + 0xc0c0 & 0xffff, + 0x8080 & 0xffff, + 0 +}; + +/* constant table align_dist4 */ +static const unsigned CONST_TBL_align_dist4_0[] = { + 0 & 0xffff, + 0x1111 & 0xffff, + 0x3333 & 0xffff, + 0x7777 & 0xffff, + 0xffff & 0xffff, + 0xeeee & 0xffff, + 0xcccc & 0xffff, + 0x8888 & 0xffff, + 0 & 0xffff, + 0x1111 & 0xffff, + 0x3333 & 0xffff, + 0x7777 & 0xffff, + 0xffff & 0xffff, + 0xeeee & 0xffff, + 0xcccc & 0xffff, + 0x8888 & 0xffff, + 0 +}; + +/* constant table align_dist2 */ +static const unsigned CONST_TBL_align_dist2_0[] = { + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 +}; + +/* constant table align_dist1 */ +static const unsigned CONST_TBL_align_dist1_0[] = { + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 +}; + +/* constant table store_dist8 */ +static const unsigned CONST_TBL_store_dist8_0[] = { + 0 & 0xffff, + 0x8080 & 0xffff, + 0xc0c0 & 0xffff, + 0xe0e0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf8f8 & 0xffff, + 0xfcfc & 0xffff, + 0xfefe & 0xffff, + 0xffff & 0xffff, + 0x7f7f & 0xffff, + 0x3f3f & 0xffff, + 0x1f1f & 0xffff, + 0xf0f & 0xffff, + 0x707 & 0xffff, + 0x303 & 0xffff, + 0x101 & 0xffff, + 0 +}; + +/* constant table store_dist4 */ +static const unsigned CONST_TBL_store_dist4_0[] = { + 0 & 0xffff, + 0x888 & 0xffff, + 0xcccc & 0xffff, + 0xeee & 0xffff, + 0xffff & 0xffff, + 0x7777 & 0xffff, + 0x3333 & 0xffff, + 0x1111 & 0xffff, + 0 & 0xffff, + 0x8888 & 0xffff, + 0xcccc & 0xffff, + 0xee0e & 0xffff, + 0xffff & 0xffff, + 0x7077 & 0xffff, + 0x3333 & 0xffff, + 0x1011 & 0xffff, + 0 +}; + +/* constant table store_dist2 */ +static const unsigned CONST_TBL_store_dist2_0[] = { + 0 & 0xffff, + 0x22a & 0xffff, + 0xffff & 0xffff, + 0x7c44 & 0xffff, + 0 & 0xffff, + 0x223e & 0xffff, + 0xffff & 0xffff, + 0x4455 & 0xffff, + 0 & 0xffff, + 0x2222 & 0xffff, + 0xffff & 0xffff, + 0x7c7c & 0xffff, + 0 & 0xffff, + 0x3fe2 & 0xffff, + 0xffff & 0xffff, + 0x4045 & 0xffff, + 0 +}; + +/* constant table store_dist1 */ +static const unsigned CONST_TBL_store_dist1_0[] = { + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 +}; + +/* constant table pdx8_es_dist16 */ +static const unsigned CONST_TBL_pdx8_es_dist16_0[] = { + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0 +}; + +/* constant table pdx8_es_dist8 */ +static const unsigned CONST_TBL_pdx8_es_dist8_0[] = { + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0 +}; + +/* constant table pdx8_es_dist4 */ +static const unsigned CONST_TBL_pdx8_es_dist4_0[] = { + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table pdx8_es_dist2 */ +static const unsigned CONST_TBL_pdx8_es_dist2_0[] = { + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0 +}; + +/* constant table pdx8_es_dist1 */ +static const unsigned CONST_TBL_pdx8_es_dist1_0[] = { + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0 +}; + +/* constant table pdx8_et_dist16 */ +static const unsigned CONST_TBL_pdx8_et_dist16_0[] = { + 0xf00000, + 0x1e00000, + 0x3c00000, + 0x7800000, + 0xf000000, + 0x1e000000, + 0x3c000000, + 0x78000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1e, + 0x3c, + 0x78, + 0xf0, + 0x1e0, + 0x3c0, + 0x780, + 0xf00, + 0x11e00, + 0x33c00, + 0x77800, + 0xff000, + 0x1ee000, + 0x3cc000, + 0x788000, + 0 +}; + +/* constant table pdx8_et_dist8 */ +static const unsigned CONST_TBL_pdx8_et_dist8_0[] = { + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0 +}; + +/* constant table pdx8_et_dist4 */ +static const unsigned CONST_TBL_pdx8_et_dist4_0[] = { + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0 +}; + +/* constant table pdx8_et_dist2 */ +static const unsigned CONST_TBL_pdx8_et_dist2_0[] = { + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0 +}; + +/* constant table pdx8_et_dist1 */ +static const unsigned CONST_TBL_pdx8_et_dist1_0[] = { + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0 +}; + +/* constant table pdx8_st_dist16 */ +static const unsigned CONST_TBL_pdx8_st_dist16_0[] = { + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0 +}; + +/* constant table pdx8_st_dist8 */ +static const unsigned CONST_TBL_pdx8_st_dist8_0[] = { + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0 +}; + +/* constant table pdx8_st_dist4 */ +static const unsigned CONST_TBL_pdx8_st_dist4_0[] = { + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table pdx8_st_dist2 */ +static const unsigned CONST_TBL_pdx8_st_dist2_0[] = { + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0 +}; + +/* constant table pdx8_st_dist1 */ +static const unsigned CONST_TBL_pdx8_st_dist1_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table pdx8_re_dist_sel */ +static const unsigned CONST_TBL_pdx8_re_dist_sel_0[] = { + 0x10000, + 0x1000100, + 0x10101010, + 0x44444444, + 0xaaaaaaaa, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx8_rs_dist_sel */ +static const unsigned CONST_TBL_pdx8_rs_dist_sel_0[] = { + 0x30000, + 0x3000300, + 0x30303030, + 0xcccccccc, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx8_rt_dist_sel */ +static const unsigned CONST_TBL_pdx8_rt_dist_sel_0[] = { + 0xf0000, + 0xf000f00, + 0xf0f0f0f0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx8_r64_dist_sel */ +static const unsigned CONST_TBL_pdx8_r64_dist_sel_0[] = { + 0xff0000, + 0xff00ff00, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx8_align_dist16 */ +static const unsigned CONST_TBL_pdx8_align_dist16_0[] = { + 0, + 0x10001, + 0x30003, + 0x70007, + 0xf000f, + 0x1f001f, + 0x3f003f, + 0x7f007f, + 0xff00ff, + 0x1ff01ff, + 0x3ff03ff, + 0x7ff07ff, + 0xfff0fff, + 0x1fff1fff, + 0x3fff3fff, + 0x7fff7fff, + 0xffffffff, + 0xfffefffe, + 0xfffcfffc, + 0xfff8fff8, + 0xfff0fff0, + 0xffe0ffe0, + 0xffc0ffc0, + 0xff80ff80, + 0xff00ff00, + 0xfe00fe00, + 0xfc00fc00, + 0xf800f800, + 0xf000f000, + 0xe000e000, + 0xc000c000, + 0x80008000, + 0 +}; + +/* constant table pdx8_align_dist8 */ +static const unsigned CONST_TBL_pdx8_align_dist8_0[] = { + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0 +}; + +/* constant table pdx8_align_dist4 */ +static const unsigned CONST_TBL_pdx8_align_dist4_0[] = { + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0 +}; + +/* constant table pdx8_align_dist2 */ +static const unsigned CONST_TBL_pdx8_align_dist2_0[] = { + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0 +}; + +/* constant table pdx8_align_dist1 */ +static const unsigned CONST_TBL_pdx8_align_dist1_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table pdx16_es_dist32l */ +static const unsigned CONST_TBL_pdx16_es_dist32l_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x1ff, + 0x3ff, + 0x7ff, + 0xfff, + 0x1fff, + 0x3fff, + 0x7fff, + 0xffff, + 0x1fffe, + 0x3fffc, + 0x7fff8, + 0xffff0, + 0x1fffe0, + 0x3fffc0, + 0x7fff80, + 0xffff00, + 0x1fffe00, + 0x3fffc00, + 0x7fff800, + 0xffff000, + 0x1fffe000, + 0x3fffc000, + 0x7fff8000, + 0xffff0000, + 0xfffe0000, + 0xfffc0000, + 0xfff80000, + 0xfff00000, + 0xffe00000, + 0xffc00000, + 0xff800000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0 +}; + +/* constant table pdx16_es_dist32h */ +static const unsigned CONST_TBL_pdx16_es_dist32h_0[] = { + 0xffff0000, + 0xfffe0000, + 0xfffc0000, + 0xfff80000, + 0xfff00000, + 0xffe00000, + 0xffc00000, + 0xff800000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x1ff, + 0x3ff, + 0x7ff, + 0xfff, + 0x1fff, + 0x3fff, + 0x7fff, + 0xffff, + 0x1fffe, + 0x3fffc, + 0x7fff8, + 0xffff0, + 0x1fffe0, + 0x3fffc0, + 0x7fff80, + 0xffff00, + 0x1fffe00, + 0x3fffc00, + 0x7fff800, + 0xffff000, + 0x1fffe000, + 0x3fffc000, + 0x7fff8000, + 0 +}; + +/* constant table pdx16_es_dist16l */ +static const unsigned CONST_TBL_pdx16_es_dist16l_0[] = { + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0 +}; + +/* constant table pdx16_es_dist16h */ +static const unsigned CONST_TBL_pdx16_es_dist16h_0[] = { + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0 +}; + +/* constant table pdx16_es_dist8l */ +static const unsigned CONST_TBL_pdx16_es_dist8l_0[] = { + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0 +}; + +/* constant table pdx16_es_dist8h */ +static const unsigned CONST_TBL_pdx16_es_dist8h_0[] = { + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0 +}; + +/* constant table pdx16_es_dist4l */ +static const unsigned CONST_TBL_pdx16_es_dist4l_0[] = { + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table pdx16_es_dist4h */ +static const unsigned CONST_TBL_pdx16_es_dist4h_0[] = { + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table pdx16_es_dist2l */ +static const unsigned CONST_TBL_pdx16_es_dist2l_0[] = { + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0 +}; + +/* constant table pdx16_es_dist2h */ +static const unsigned CONST_TBL_pdx16_es_dist2h_0[] = { + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0x18181818, + 0x60606060, + 0x81818181, + 0x6060606, + 0 +}; + +/* constant table pdx16_es_dist1l */ +static const unsigned CONST_TBL_pdx16_es_dist1l_0[] = { + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0 +}; + +/* constant table pdx16_es_dist1h */ +static const unsigned CONST_TBL_pdx16_es_dist1h_0[] = { + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0 +}; + +/* constant table pdx16_et_dist32l */ +static const unsigned CONST_TBL_pdx16_et_dist32l_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x1fe, + 0x3fc, + 0x7f8, + 0xff0, + 0x1fe0, + 0x3fc0, + 0x7f80, + 0xff00, + 0x1fe00, + 0x3fc00, + 0x7f800, + 0xff000, + 0x1fe000, + 0x3fc000, + 0x7f8000, + 0xff0000, + 0x1fe0000, + 0x3fc0000, + 0x7f80000, + 0xff00000, + 0x1fe00000, + 0x3fc00000, + 0x7f800000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0 +}; + +/* constant table pdx16_et_dist32h */ +static const unsigned CONST_TBL_pdx16_et_dist32h_0[] = { + 0xff00, + 0x1fe00, + 0x3fc00, + 0x7f800, + 0xff000, + 0x1fe000, + 0x3fc000, + 0x7f8000, + 0xff0000, + 0x1fe0000, + 0x3fc0000, + 0x7f80000, + 0xff00000, + 0x1fe00000, + 0x3fc00000, + 0x7f800000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x1fe, + 0x3fc, + 0x7f8, + 0xff0, + 0x1fe0, + 0x3fc0, + 0x7f80, + 0 +}; + +/* constant table pdx16_et_dist16l */ +static const unsigned CONST_TBL_pdx16_et_dist16l_0[] = { + 0xf00000, + 0x1e00000, + 0x3c00000, + 0x7800000, + 0xf000000, + 0x1e000000, + 0x3c000000, + 0x78000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1e, + 0x3c, + 0x78, + 0xf0, + 0x1e0, + 0x3c0, + 0x780, + 0xf00, + 0x11e00, + 0x33c00, + 0x77800, + 0xff000, + 0x1ee000, + 0x3cc000, + 0x788000, + 0xf00000, + 0x1e00000, + 0x3c00000, + 0x7800000, + 0xf000000, + 0x1e000000, + 0x3c000000, + 0x78000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1e, + 0x3c, + 0x78, + 0xf0, + 0x1e0, + 0x3c0, + 0x780, + 0xf00, + 0x11e00, + 0x33c00, + 0x77800, + 0xff000, + 0x1ee000, + 0x3cc000, + 0x788000, + 0 +}; + +/* constant table pdx16_et_dist16h */ +static const unsigned CONST_TBL_pdx16_et_dist16h_0[] = { + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1e, + 0x3c, + 0x78, + 0xf0, + 0x1e0, + 0x3c0, + 0x780, + 0xf00, + 0x11e00, + 0x33c00, + 0x77800, + 0xff000, + 0x1ee000, + 0x3cc000, + 0x788000, + 0xf00000, + 0x1e00000, + 0x3c00000, + 0x7800000, + 0xf000000, + 0x1e000000, + 0x3c000000, + 0x78000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1e, + 0x3c, + 0x78, + 0xf0, + 0x1e0, + 0x3c0, + 0x780, + 0xf00, + 0x11e00, + 0x33c00, + 0x77800, + 0xff000, + 0x1ee000, + 0x3cc000, + 0x788000, + 0xf00000, + 0x1e00000, + 0x3c00000, + 0x7800000, + 0xf000000, + 0x1e000000, + 0x3c000000, + 0x78000000, + 0 +}; + +/* constant table pdx16_et_dist8l */ +static const unsigned CONST_TBL_pdx16_et_dist8l_0[] = { + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0 +}; + +/* constant table pdx16_et_dist8h */ +static const unsigned CONST_TBL_pdx16_et_dist8h_0[] = { + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0x300003, + 0x1600006, + 0x3c0000c, + 0x6800018, + 0xc000030, + 0x18000160, + 0x300003c0, + 0x60000680, + 0xc0000c00, + 0x80001800, + 0x3000, + 0x16000, + 0x3c000, + 0x68000, + 0xc0000, + 0x180001, + 0 +}; + +/* constant table pdx16_et_dist4l */ +static const unsigned CONST_TBL_pdx16_et_dist4l_0[] = { + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0 +}; + +/* constant table pdx16_et_dist4h */ +static const unsigned CONST_TBL_pdx16_et_dist4h_0[] = { + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0x4018020, + 0x18020040, + 0x20040180, + 0x40180200, + 0x80200401, + 0x401802, + 0x1802004, + 0x2004018, + 0 +}; + +/* constant table pdx16_et_dist2l */ +static const unsigned CONST_TBL_pdx16_et_dist2l_0[] = { + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0 +}; + +/* constant table pdx16_et_dist2h */ +static const unsigned CONST_TBL_pdx16_et_dist2h_0[] = { + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0x21842184, + 0x42184218, + 0x84218421, + 0x18421842, + 0 +}; + +/* constant table pdx16_et_dist1l */ +static const unsigned CONST_TBL_pdx16_et_dist1l_0[] = { + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0 +}; + +/* constant table pdx16_et_dist1h */ +static const unsigned CONST_TBL_pdx16_et_dist1h_0[] = { + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0x5a5a5a5a, + 0xa5a5a5a5, + 0 +}; + +/* constant table pdx16_st_dist32l */ +static const unsigned CONST_TBL_pdx16_st_dist32l_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x1ff, + 0x3ff, + 0x7ff, + 0xfff, + 0x1fff, + 0x3fff, + 0x7fff, + 0xffff, + 0x1fffe, + 0x3fffc, + 0x7fff8, + 0xffff0, + 0x1fffe0, + 0x3fffc0, + 0x7fff80, + 0xffff00, + 0x1fffe00, + 0x3fffc00, + 0x7fff800, + 0xffff000, + 0x1fffe000, + 0x3fffc000, + 0x7fff8000, + 0xffff0000, + 0xfffe0000, + 0xfffc0000, + 0xfff80000, + 0xfff00000, + 0xffe00000, + 0xffc00000, + 0xff800000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0 +}; + +/* constant table pdx16_st_dist32h */ +static const unsigned CONST_TBL_pdx16_st_dist32h_0[] = { + 0xffff0000, + 0xfffe0000, + 0xfffc0000, + 0xfff80000, + 0xfff00000, + 0xffe00000, + 0xffc00000, + 0xff800000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x1ff, + 0x3ff, + 0x7ff, + 0xfff, + 0x1fff, + 0x3fff, + 0x7fff, + 0xffff, + 0x1fffe, + 0x3fffc, + 0x7fff8, + 0xffff0, + 0x1fffe0, + 0x3fffc0, + 0x7fff80, + 0xffff00, + 0x1fffe00, + 0x3fffc00, + 0x7fff800, + 0xffff000, + 0x1fffe000, + 0x3fffc000, + 0x7fff8000, + 0 +}; + +/* constant table pdx16_st_dist16l */ +static const unsigned CONST_TBL_pdx16_st_dist16l_0[] = { + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0 +}; + +/* constant table pdx16_st_dist16h */ +static const unsigned CONST_TBL_pdx16_st_dist16h_0[] = { + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x101fe, + 0x303fc, + 0x707f8, + 0xf0ff0, + 0x1f1fe0, + 0x3f3fc0, + 0x7f7f80, + 0xffff00, + 0x1fefe00, + 0x3fcfc00, + 0x7f8f800, + 0xff0f000, + 0x1fe0e000, + 0x3fc0c000, + 0x7f808000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0 +}; + +/* constant table pdx16_st_dist8l */ +static const unsigned CONST_TBL_pdx16_st_dist8l_0[] = { + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0 +}; + +/* constant table pdx16_st_dist8h */ +static const unsigned CONST_TBL_pdx16_st_dist8h_0[] = { + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0xff000, + 0x11ee000, + 0x33cc000, + 0x7788000, + 0xff00000, + 0x1ee00001, + 0x3cc00003, + 0x78800007, + 0xf000000f, + 0xe000011e, + 0xc000033c, + 0x80000778, + 0xff0, + 0x11ee0, + 0x33cc0, + 0x77880, + 0 +}; + +/* constant table pdx16_st_dist4l */ +static const unsigned CONST_TBL_pdx16_st_dist4l_0[] = { + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table pdx16_st_dist4h */ +static const unsigned CONST_TBL_pdx16_st_dist4h_0[] = { + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table pdx16_st_dist2l */ +static const unsigned CONST_TBL_pdx16_st_dist2l_0[] = { + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0 +}; + +/* constant table pdx16_st_dist2h */ +static const unsigned CONST_TBL_pdx16_st_dist2h_0[] = { + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0 +}; + +/* constant table pdx16_st_dist1l */ +static const unsigned CONST_TBL_pdx16_st_dist1l_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table pdx16_st_dist1h */ +static const unsigned CONST_TBL_pdx16_st_dist1h_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table pdx16_re_dist_sell */ +static const unsigned CONST_TBL_pdx16_re_dist_sell_0[] = { + 0, + 0x10000, + 0x1000100, + 0x10101010, + 0x44444444, + 0xaaaaaaaa, + 0, + 0, + 0 +}; + +/* constant table pdx16_re_dist_selh */ +static const unsigned CONST_TBL_pdx16_re_dist_selh_0[] = { + 0x1, + 0x10000, + 0x1000100, + 0x10101010, + 0x44444444, + 0xaaaaaaaa, + 0, + 0, + 0 +}; + +/* constant table pdx16_rs_dist_sell */ +static const unsigned CONST_TBL_pdx16_rs_dist_sell_0[] = { + 0, + 0x30000, + 0x3000300, + 0x30303030, + 0xcccccccc, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx16_rs_dist_selh */ +static const unsigned CONST_TBL_pdx16_rs_dist_selh_0[] = { + 0x3, + 0x30000, + 0x3000300, + 0x30303030, + 0xcccccccc, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx16_rt_dist_sell */ +static const unsigned CONST_TBL_pdx16_rt_dist_sell_0[] = { + 0, + 0xf0000, + 0xf000f00, + 0xf0f0f0f0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx16_rt_dist_selh */ +static const unsigned CONST_TBL_pdx16_rt_dist_selh_0[] = { + 0xf, + 0xf0000, + 0xf000f00, + 0xf0f0f0f0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx16_r64_dist_sell */ +static const unsigned CONST_TBL_pdx16_r64_dist_sell_0[] = { + 0, + 0xff0000, + 0xff00ff00, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx16_r64_dist_selh */ +static const unsigned CONST_TBL_pdx16_r64_dist_selh_0[] = { + 0xff, + 0xff0000, + 0xff00ff00, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx16_align_dist32l */ +static const unsigned CONST_TBL_pdx16_align_dist32l_0[] = { + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x1ff, + 0x3ff, + 0x7ff, + 0xfff, + 0x1fff, + 0x3fff, + 0x7fff, + 0xffff, + 0x1ffff, + 0x3ffff, + 0x7ffff, + 0xfffff, + 0x1fffff, + 0x3fffff, + 0x7fffff, + 0xffffff, + 0x1ffffff, + 0x3ffffff, + 0x7ffffff, + 0xfffffff, + 0x1fffffff, + 0x3fffffff, + 0x7fffffff, + 0xffffffff, + 0xfffffffe, + 0xfffffffc, + 0xfffffff8, + 0xfffffff0, + 0xffffffe0, + 0xffffffc0, + 0xffffff80, + 0xffffff00, + 0xfffffe00, + 0xfffffc00, + 0xfffff800, + 0xfffff000, + 0xffffe000, + 0xffffc000, + 0xffff8000, + 0xffff0000, + 0xfffe0000, + 0xfffc0000, + 0xfff80000, + 0xfff00000, + 0xffe00000, + 0xffc00000, + 0xff800000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0 +}; + +/* constant table pdx16_align_dist32h */ +static const unsigned CONST_TBL_pdx16_align_dist32h_0[] = { + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1f, + 0x3f, + 0x7f, + 0xff, + 0x1ff, + 0x3ff, + 0x7ff, + 0xfff, + 0x1fff, + 0x3fff, + 0x7fff, + 0xffff, + 0x1ffff, + 0x3ffff, + 0x7ffff, + 0xfffff, + 0x1fffff, + 0x3fffff, + 0x7fffff, + 0xffffff, + 0x1ffffff, + 0x3ffffff, + 0x7ffffff, + 0xfffffff, + 0x1fffffff, + 0x3fffffff, + 0x7fffffff, + 0xffffffff, + 0xfffffffe, + 0xfffffffc, + 0xfffffff8, + 0xfffffff0, + 0xffffffe0, + 0xffffffc0, + 0xffffff80, + 0xffffff00, + 0xfffffe00, + 0xfffffc00, + 0xfffff800, + 0xfffff000, + 0xffffe000, + 0xffffc000, + 0xffff8000, + 0xffff0000, + 0xfffe0000, + 0xfffc0000, + 0xfff80000, + 0xfff00000, + 0xffe00000, + 0xffc00000, + 0xff800000, + 0xff000000, + 0xfe000000, + 0xfc000000, + 0xf8000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0 +}; + +/* constant table pdx16_align_dist16l */ +static const unsigned CONST_TBL_pdx16_align_dist16l_0[] = { + 0, + 0x10001, + 0x30003, + 0x70007, + 0xf000f, + 0x1f001f, + 0x3f003f, + 0x7f007f, + 0xff00ff, + 0x1ff01ff, + 0x3ff03ff, + 0x7ff07ff, + 0xfff0fff, + 0x1fff1fff, + 0x3fff3fff, + 0x7fff7fff, + 0xffffffff, + 0xfffefffe, + 0xfffcfffc, + 0xfff8fff8, + 0xfff0fff0, + 0xffe0ffe0, + 0xffc0ffc0, + 0xff80ff80, + 0xff00ff00, + 0xfe00fe00, + 0xfc00fc00, + 0xf800f800, + 0xf000f000, + 0xe000e000, + 0xc000c000, + 0x80008000, + 0, + 0x10001, + 0x30003, + 0x70007, + 0xf000f, + 0x1f001f, + 0x3f003f, + 0x7f007f, + 0xff00ff, + 0x1ff01ff, + 0x3ff03ff, + 0x7ff07ff, + 0xfff0fff, + 0x1fff1fff, + 0x3fff3fff, + 0x7fff7fff, + 0xffffffff, + 0xfffefffe, + 0xfffcfffc, + 0xfff8fff8, + 0xfff0fff0, + 0xffe0ffe0, + 0xffc0ffc0, + 0xff80ff80, + 0xff00ff00, + 0xfe00fe00, + 0xfc00fc00, + 0xf800f800, + 0xf000f000, + 0xe000e000, + 0xc000c000, + 0x80008000, + 0 +}; + +/* constant table pdx16_align_dist16h */ +static const unsigned CONST_TBL_pdx16_align_dist16h_0[] = { + 0, + 0x10001, + 0x30003, + 0x70007, + 0xf000f, + 0x1f001f, + 0x3f003f, + 0x7f007f, + 0xff00ff, + 0x1ff01ff, + 0x3ff03ff, + 0x7ff07ff, + 0xfff0fff, + 0x1fff1fff, + 0x3fff3fff, + 0x7fff7fff, + 0xffffffff, + 0xfffefffe, + 0xfffcfffc, + 0xfff8fff8, + 0xfff0fff0, + 0xffe0ffe0, + 0xffc0ffc0, + 0xff80ff80, + 0xff00ff00, + 0xfe00fe00, + 0xfc00fc00, + 0xf800f800, + 0xf000f000, + 0xe000e000, + 0xc000c000, + 0x80008000, + 0, + 0x10001, + 0x30003, + 0x70007, + 0xf000f, + 0x1f001f, + 0x3f003f, + 0x7f007f, + 0xff00ff, + 0x1ff01ff, + 0x3ff03ff, + 0x7ff07ff, + 0xfff0fff, + 0x1fff1fff, + 0x3fff3fff, + 0x7fff7fff, + 0xffffffff, + 0xfffefffe, + 0xfffcfffc, + 0xfff8fff8, + 0xfff0fff0, + 0xffe0ffe0, + 0xffc0ffc0, + 0xff80ff80, + 0xff00ff00, + 0xfe00fe00, + 0xfc00fc00, + 0xf800f800, + 0xf000f000, + 0xe000e000, + 0xc000c000, + 0x80008000, + 0 +}; + +/* constant table pdx16_align_dist8l */ +static const unsigned CONST_TBL_pdx16_align_dist8l_0[] = { + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0 +}; + +/* constant table pdx16_align_dist8h */ +static const unsigned CONST_TBL_pdx16_align_dist8h_0[] = { + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0, + 0x1010101, + 0x3030303, + 0x7070707, + 0xf0f0f0f, + 0x1f1f1f1f, + 0x3f3f3f3f, + 0x7f7f7f7f, + 0xffffffff, + 0xfefefefe, + 0xfcfcfcfc, + 0xf8f8f8f8, + 0xf0f0f0f0, + 0xe0e0e0e0, + 0xc0c0c0c0, + 0x80808080, + 0 +}; + +/* constant table pdx16_align_dist4l */ +static const unsigned CONST_TBL_pdx16_align_dist4l_0[] = { + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0 +}; + +/* constant table pdx16_align_dist4h */ +static const unsigned CONST_TBL_pdx16_align_dist4h_0[] = { + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0, + 0x11111111, + 0x33333333, + 0x77777777, + 0xffffffff, + 0xeeeeeeee, + 0xcccccccc, + 0x88888888, + 0 +}; + +/* constant table pdx16_align_dist2l */ +static const unsigned CONST_TBL_pdx16_align_dist2l_0[] = { + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0 +}; + +/* constant table pdx16_align_dist2h */ +static const unsigned CONST_TBL_pdx16_align_dist2h_0[] = { + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0 +}; + +/* constant table pdx16_align_dist1l */ +static const unsigned CONST_TBL_pdx16_align_dist1l_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table pdx16_align_dist1h */ +static const unsigned CONST_TBL_pdx16_align_dist1h_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl0_low */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl0_low_0[] = { + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl0_high */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl0_high_0[] = { + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl1_low */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl1_low_0[] = { + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl1_high */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl1_high_0[] = { + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0x44444444, + 0x88888888, + 0x11111111, + 0x22222222, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl2_low */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl2_low_0[] = { + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl2_high */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl2_high_0[] = { + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0x10101010, + 0x20202020, + 0x40404040, + 0x80808080, + 0x1010101, + 0x2020202, + 0x4040404, + 0x8080808, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl3_low */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl3_low_0[] = { + 0x1000100, + 0x2000200, + 0x4000400, + 0x8000800, + 0x10001000, + 0x20002000, + 0x40004000, + 0x80008000, + 0x10001, + 0x20002, + 0x40004, + 0x80008, + 0x100010, + 0x200020, + 0x400040, + 0x800080, + 0x1000100, + 0x2000200, + 0x4000400, + 0x8000800, + 0x10001000, + 0x20002000, + 0x40004000, + 0x80008000, + 0x10001, + 0x20002, + 0x40004, + 0x80008, + 0x100010, + 0x200020, + 0x400040, + 0x800080, + 0x1000100, + 0x2000200, + 0x4000400, + 0x8000800, + 0x10001000, + 0x20002000, + 0x40004000, + 0x80008000, + 0x10001, + 0x20002, + 0x40004, + 0x80008, + 0x100010, + 0x200020, + 0x400040, + 0x800080, + 0x1000100, + 0x2000200, + 0x4000400, + 0x8000800, + 0x10001000, + 0x20002000, + 0x40004000, + 0x80008000, + 0x10001, + 0x20002, + 0x40004, + 0x80008, + 0x100010, + 0x200020, + 0x400040, + 0x800080, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl3_high */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl3_high_0[] = { + 0x1000100, + 0x2000200, + 0x4000400, + 0x8000800, + 0x10001000, + 0x20002000, + 0x40004000, + 0x80008000, + 0x10001, + 0x20002, + 0x40004, + 0x80008, + 0x100010, + 0x200020, + 0x400040, + 0x800080, + 0x1000100, + 0x2000200, + 0x4000400, + 0x8000800, + 0x10001000, + 0x20002000, + 0x40004000, + 0x80008000, + 0x10001, + 0x20002, + 0x40004, + 0x80008, + 0x100010, + 0x200020, + 0x400040, + 0x800080, + 0x1000100, + 0x2000200, + 0x4000400, + 0x8000800, + 0x10001000, + 0x20002000, + 0x40004000, + 0x80008000, + 0x10001, + 0x20002, + 0x40004, + 0x80008, + 0x100010, + 0x200020, + 0x400040, + 0x800080, + 0x1000100, + 0x2000200, + 0x4000400, + 0x8000800, + 0x10001000, + 0x20002000, + 0x40004000, + 0x80008000, + 0x10001, + 0x20002, + 0x40004, + 0x80008, + 0x100010, + 0x200020, + 0x400040, + 0x800080, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl4_low */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl4_low_0[] = { + 0x10000, + 0x20000, + 0x40000, + 0x80000, + 0x100000, + 0x200000, + 0x400000, + 0x800000, + 0x1000000, + 0x2000000, + 0x4000000, + 0x8000000, + 0x10000000, + 0x20000000, + 0x40000000, + 0x80000000, + 0x1, + 0x2, + 0x4, + 0x8, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0x200, + 0x400, + 0x800, + 0x1000, + 0x2000, + 0x4000, + 0x8000, + 0x10000, + 0x20000, + 0x40000, + 0x80000, + 0x100000, + 0x200000, + 0x400000, + 0x800000, + 0x1000000, + 0x2000000, + 0x4000000, + 0x8000000, + 0x10000000, + 0x20000000, + 0x40000000, + 0x80000000, + 0x1, + 0x2, + 0x4, + 0x8, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0x200, + 0x400, + 0x800, + 0x1000, + 0x2000, + 0x4000, + 0x8000, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl4_high */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl4_high_0[] = { + 0x10000, + 0x20000, + 0x40000, + 0x80000, + 0x100000, + 0x200000, + 0x400000, + 0x800000, + 0x1000000, + 0x2000000, + 0x4000000, + 0x8000000, + 0x10000000, + 0x20000000, + 0x40000000, + 0x80000000, + 0x1, + 0x2, + 0x4, + 0x8, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0x200, + 0x400, + 0x800, + 0x1000, + 0x2000, + 0x4000, + 0x8000, + 0x10000, + 0x20000, + 0x40000, + 0x80000, + 0x100000, + 0x200000, + 0x400000, + 0x800000, + 0x1000000, + 0x2000000, + 0x4000000, + 0x8000000, + 0x10000000, + 0x20000000, + 0x40000000, + 0x80000000, + 0x1, + 0x2, + 0x4, + 0x8, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0x200, + 0x400, + 0x800, + 0x1000, + 0x2000, + 0x4000, + 0x8000, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl5_low */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl5_low_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x2, + 0x4, + 0x8, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0x200, + 0x400, + 0x800, + 0x1000, + 0x2000, + 0x4000, + 0x8000, + 0x10000, + 0x20000, + 0x40000, + 0x80000, + 0x100000, + 0x200000, + 0x400000, + 0x800000, + 0x1000000, + 0x2000000, + 0x4000000, + 0x8000000, + 0x10000000, + 0x20000000, + 0x40000000, + 0x80000000, + 0 +}; + +/* constant table pdx16_shft_rep8_lvl5_high */ +static const unsigned CONST_TBL_pdx16_shft_rep8_lvl5_high_0[] = { + 0x1, + 0x2, + 0x4, + 0x8, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0x200, + 0x400, + 0x800, + 0x1000, + 0x2000, + 0x4000, + 0x8000, + 0x10000, + 0x20000, + 0x40000, + 0x80000, + 0x100000, + 0x200000, + 0x400000, + 0x800000, + 0x1000000, + 0x2000000, + 0x4000000, + 0x8000000, + 0x10000000, + 0x20000000, + 0x40000000, + 0x80000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table pdx16_shft_rep16_lvl3_high */ +static const unsigned CONST_TBL_pdx16_shft_rep16_lvl3_high_0[] = { + 0x3000300, + 0x6000600, + 0xc000c00, + 0x18001800, + 0x30003000, + 0x60006000, + 0xc000c000, + 0x80018001, + 0x30003, + 0x60006, + 0xc000c, + 0x180018, + 0x300030, + 0x600060, + 0xc000c0, + 0x1800180, + 0x3000300, + 0x6000600, + 0xc000c00, + 0x18001800, + 0x30003000, + 0x60006000, + 0xc000c000, + 0x80018001, + 0x30003, + 0x60006, + 0xc000c, + 0x180018, + 0x300030, + 0x600060, + 0xc000c0, + 0x1800180, + 0x3000300, + 0x6000600, + 0xc000c00, + 0x18001800, + 0x30003000, + 0x60006000, + 0xc000c000, + 0x80018001, + 0x30003, + 0x60006, + 0xc000c, + 0x180018, + 0x300030, + 0x600060, + 0xc000c0, + 0x1800180, + 0x3000300, + 0x6000600, + 0xc000c00, + 0x18001800, + 0x30003000, + 0x60006000, + 0xc000c000, + 0x80018001, + 0x30003, + 0x60006, + 0xc000c, + 0x180018, + 0x300030, + 0x600060, + 0xc000c0, + 0x1800180, + 0 +}; + +/* constant table pdx16_shft_rep16_lvl3_low */ +static const unsigned CONST_TBL_pdx16_shft_rep16_lvl3_low_0[] = { + 0x3000300, + 0x6000600, + 0xc000c00, + 0x18001800, + 0x30003000, + 0x60006000, + 0xc000c000, + 0x80018001, + 0x30003, + 0x60006, + 0xc000c, + 0x180018, + 0x300030, + 0x600060, + 0xc000c0, + 0x1800180, + 0x3000300, + 0x6000600, + 0xc000c00, + 0x18001800, + 0x30003000, + 0x60006000, + 0xc000c000, + 0x80018001, + 0x30003, + 0x60006, + 0xc000c, + 0x180018, + 0x300030, + 0x600060, + 0xc000c0, + 0x1800180, + 0x3000300, + 0x6000600, + 0xc000c00, + 0x18001800, + 0x30003000, + 0x60006000, + 0xc000c000, + 0x80018001, + 0x30003, + 0x60006, + 0xc000c, + 0x180018, + 0x300030, + 0x600060, + 0xc000c0, + 0x1800180, + 0x3000300, + 0x6000600, + 0xc000c00, + 0x18001800, + 0x30003000, + 0x60006000, + 0xc000c000, + 0x80018001, + 0x30003, + 0x60006, + 0xc000c, + 0x180018, + 0x300030, + 0x600060, + 0xc000c0, + 0x1800180, + 0 +}; + +/* constant table pdx16_shft_rep16_lvl4_high */ +static const unsigned CONST_TBL_pdx16_shft_rep16_lvl4_high_0[] = { + 0x30000, + 0x60000, + 0xc0000, + 0x180000, + 0x300000, + 0x600000, + 0xc00000, + 0x1800000, + 0x3000000, + 0x6000000, + 0xc000000, + 0x18000000, + 0x30000000, + 0x60000000, + 0xc0000000, + 0x80000001, + 0x3, + 0x6, + 0xc, + 0x18, + 0x30, + 0x60, + 0xc0, + 0x180, + 0x300, + 0x600, + 0xc00, + 0x1800, + 0x3000, + 0x6000, + 0xc000, + 0x18000, + 0x30000, + 0x60000, + 0xc0000, + 0x180000, + 0x300000, + 0x600000, + 0xc00000, + 0x1800000, + 0x3000000, + 0x6000000, + 0xc000000, + 0x18000000, + 0x30000000, + 0x60000000, + 0xc0000000, + 0x80000001, + 0x3, + 0x6, + 0xc, + 0x18, + 0x30, + 0x60, + 0xc0, + 0x180, + 0x300, + 0x600, + 0xc00, + 0x1800, + 0x3000, + 0x6000, + 0xc000, + 0x18000, + 0 +}; + +/* constant table pdx16_shft_rep16_lvl4_low */ +static const unsigned CONST_TBL_pdx16_shft_rep16_lvl4_low_0[] = { + 0x30000, + 0x60000, + 0xc0000, + 0x180000, + 0x300000, + 0x600000, + 0xc00000, + 0x1800000, + 0x3000000, + 0x6000000, + 0xc000000, + 0x18000000, + 0x30000000, + 0x60000000, + 0xc0000000, + 0x80000001, + 0x3, + 0x6, + 0xc, + 0x18, + 0x30, + 0x60, + 0xc0, + 0x180, + 0x300, + 0x600, + 0xc00, + 0x1800, + 0x3000, + 0x6000, + 0xc000, + 0x18000, + 0x30000, + 0x60000, + 0xc0000, + 0x180000, + 0x300000, + 0x600000, + 0xc00000, + 0x1800000, + 0x3000000, + 0x6000000, + 0xc000000, + 0x18000000, + 0x30000000, + 0x60000000, + 0xc0000000, + 0x80000001, + 0x3, + 0x6, + 0xc, + 0x18, + 0x30, + 0x60, + 0xc0, + 0x180, + 0x300, + 0x600, + 0xc00, + 0x1800, + 0x3000, + 0x6000, + 0xc000, + 0x18000, + 0 +}; + +/* constant table pdx16_shft_rep16_lvl5_high */ +static const unsigned CONST_TBL_pdx16_shft_rep16_lvl5_high_0[] = { + 0x3, + 0x6, + 0xc, + 0x18, + 0x30, + 0x60, + 0xc0, + 0x180, + 0x300, + 0x600, + 0xc00, + 0x1800, + 0x3000, + 0x6000, + 0xc000, + 0x18000, + 0x30000, + 0x60000, + 0xc0000, + 0x180000, + 0x300000, + 0x600000, + 0xc00000, + 0x1800000, + 0x3000000, + 0x6000000, + 0xc000000, + 0x18000000, + 0x30000000, + 0x60000000, + 0xc0000000, + 0x80000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0 +}; + +/* constant table pdx16_shft_rep16_lvl5_low */ +static const unsigned CONST_TBL_pdx16_shft_rep16_lvl5_low_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x6, + 0xc, + 0x18, + 0x30, + 0x60, + 0xc0, + 0x180, + 0x300, + 0x600, + 0xc00, + 0x1800, + 0x3000, + 0x6000, + 0xc000, + 0x18000, + 0x30000, + 0x60000, + 0xc0000, + 0x180000, + 0x300000, + 0x600000, + 0xc00000, + 0x1800000, + 0x3000000, + 0x6000000, + 0xc000000, + 0x18000000, + 0x30000000, + 0x60000000, + 0xc0000000, + 0x80000000, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl0_low */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl0_low_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl1_low */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl1_low_0[] = { + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl2_low */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl2_low_0[] = { + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl3_low */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl3_low_0[] = { + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl4_low */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl4_low_0[] = { + 0xff0000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf000000f, + 0xf000000f, + 0xf000000f, + 0xf000000f, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff0, + 0xff0, + 0xff0, + 0xff0, + 0xff00, + 0xff00, + 0xff00, + 0xff00, + 0xff000, + 0xff000, + 0xff000, + 0xff000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf000000f, + 0xf000000f, + 0xf000000f, + 0xf000000f, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff0, + 0xff0, + 0xff0, + 0xff0, + 0xff00, + 0xff00, + 0xff00, + 0xff00, + 0xff000, + 0xff000, + 0xff000, + 0xff000, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl5_low */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl5_low_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0xf, + 0xf, + 0xf, + 0xf, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff0, + 0xff0, + 0xff0, + 0xff0, + 0xff00, + 0xff00, + 0xff00, + 0xff00, + 0xff000, + 0xff000, + 0xff000, + 0xff000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl0_high */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl0_high_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl1_high */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl1_high_0[] = { + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0, + 0x55555555, + 0xffffffff, + 0xaaaaaaaa, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl2_high */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl2_high_0[] = { + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0xf0f0f0f0, + 0xe1e1e1e1, + 0xc3c3c3c3, + 0x87878787, + 0xf0f0f0f, + 0x1e1e1e1e, + 0x3c3c3c3c, + 0x78787878, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl3_high */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl3_high_0[] = { + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xff00ff00, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xf00ff00f, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0xff00ff0, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl4_high */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl4_high_0[] = { + 0xff0000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf000000f, + 0xf000000f, + 0xf000000f, + 0xf000000f, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff0, + 0xff0, + 0xff0, + 0xff0, + 0xff00, + 0xff00, + 0xff00, + 0xff00, + 0xff000, + 0xff000, + 0xff000, + 0xff000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf000000f, + 0xf000000f, + 0xf000000f, + 0xf000000f, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff0, + 0xff0, + 0xff0, + 0xff0, + 0xff00, + 0xff00, + 0xff00, + 0xff00, + 0xff000, + 0xff000, + 0xff000, + 0xff000, + 0 +}; + +/* constant table pdx16_shft_rep32_lvl5_high */ +static const unsigned CONST_TBL_pdx16_shft_rep32_lvl5_high_0[] = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff0, + 0xff0, + 0xff0, + 0xff0, + 0xff00, + 0xff00, + 0xff00, + 0xff00, + 0xff000, + 0xff000, + 0xff000, + 0xff000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff0000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff00000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0xf, + 0xf, + 0xf, + 0xf, + 0 +}; + +/* constant table la_32_high */ +static const unsigned CONST_TBL_la_32_high_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x7, + 0xf, + 0x1e, + 0x3c, + 0x78, + 0xf0, + 0x1e0, + 0x3c0, + 0x780, + 0xf00, + 0x1e00, + 0x3c00, + 0x7800, + 0xf000, + 0x1e000, + 0x3c000, + 0x78000, + 0xf0000, + 0x1e0000, + 0x3c0000, + 0x780000, + 0xf00000, + 0x1e00000, + 0x3c00000, + 0x7800000, + 0xf000000, + 0x1e000000, + 0x3c000000, + 0x78000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0 +}; + +/* constant table la_32_low */ +static const unsigned CONST_TBL_la_32_low_0[] = { + 0xf, + 0x1e, + 0x3c, + 0x78, + 0xf0, + 0x1e0, + 0x3c0, + 0x780, + 0xf00, + 0x1e00, + 0x3c00, + 0x7800, + 0xf000, + 0x1e000, + 0x3c000, + 0x78000, + 0xf0000, + 0x1e0000, + 0x3c0000, + 0x780000, + 0xf00000, + 0x1e00000, + 0x3c00000, + 0x7800000, + 0xf000000, + 0x1e000000, + 0x3c000000, + 0x78000000, + 0xf0000000, + 0xe0000000, + 0xc0000000, + 0x80000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x7, + 0 +}; + +/* constant table la_8_low */ +static const unsigned CONST_TBL_la_8_low_0[] = { + 0x1, + 0x2, + 0x4, + 0x8, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0x200, + 0x400, + 0x800, + 0x1000, + 0x2000, + 0x4000, + 0x8000, + 0x10000, + 0x20000, + 0x40000, + 0x80000, + 0x100000, + 0x200000, + 0x400000, + 0x800000, + 0x1000000, + 0x2000000, + 0x4000000, + 0x8000000, + 0x10000000, + 0x20000000, + 0x40000000, + 0x80000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table la_8_high */ +static const unsigned CONST_TBL_la_8_high_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x2, + 0x4, + 0x8, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0x200, + 0x400, + 0x800, + 0x1000, + 0x2000, + 0x4000, + 0x8000, + 0x10000, + 0x20000, + 0x40000, + 0x80000, + 0x100000, + 0x200000, + 0x400000, + 0x800000, + 0x1000000, + 0x2000000, + 0x4000000, + 0x8000000, + 0x10000000, + 0x20000000, + 0x40000000, + 0x80000000, + 0 +}; + +/* constant table la_16_high */ +static const unsigned CONST_TBL_la_16_high_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0x3, + 0x6, + 0xc, + 0x18, + 0x30, + 0x60, + 0xc0, + 0x180, + 0x300, + 0x600, + 0xc00, + 0x1800, + 0x3000, + 0x6000, + 0xc000, + 0x18000, + 0x30000, + 0x60000, + 0xc0000, + 0x180000, + 0x300000, + 0x600000, + 0xc00000, + 0x1800000, + 0x3000000, + 0x6000000, + 0xc000000, + 0x18000000, + 0x30000000, + 0x60000000, + 0xc0000000, + 0x80000000, + 0 +}; + +/* constant table la_16_low */ +static const unsigned CONST_TBL_la_16_low_0[] = { + 0x3, + 0x6, + 0xc, + 0x18, + 0x30, + 0x60, + 0xc0, + 0x180, + 0x300, + 0x600, + 0xc00, + 0x1800, + 0x3000, + 0x6000, + 0xc000, + 0x18000, + 0x30000, + 0x60000, + 0xc0000, + 0x180000, + 0x300000, + 0x600000, + 0xc00000, + 0x1800000, + 0x3000000, + 0x6000000, + 0xc000000, + 0x18000000, + 0x30000000, + 0x60000000, + 0xc0000000, + 0x80000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x1, + 0 +}; + +/* constant table shft_rep16_lvl0_high */ +static const unsigned CONST_TBL_shft_rep16_lvl0_high_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table shft_rep16_lvl0_low */ +static const unsigned CONST_TBL_shft_rep16_lvl0_low_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table shft_rep16_lvl1_high */ +static const unsigned CONST_TBL_shft_rep16_lvl1_high_0[] = { + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0 +}; + +/* constant table shft_rep16_lvl1_low */ +static const unsigned CONST_TBL_shft_rep16_lvl1_low_0[] = { + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0xcccccccc, + 0x99999999, + 0x33333333, + 0x66666666, + 0 +}; + +/* constant table shft_rep16_lvl2_high */ +static const unsigned CONST_TBL_shft_rep16_lvl2_high_0[] = { + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0 +}; + +/* constant table shft_rep16_lvl2_low */ +static const unsigned CONST_TBL_shft_rep16_lvl2_low_0[] = { + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0x30303030, + 0x60606060, + 0xc0c0c0c0, + 0x81818181, + 0x3030303, + 0x6060606, + 0xc0c0c0c, + 0x18181818, + 0 +}; + +/* constant table leadzero_lvl0_es_high */ +static const unsigned CONST_TBL_leadzero_lvl0_es_high_0[] = { + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0 +}; + +/* constant table leadzero_lvl0_st_high */ +static const unsigned CONST_TBL_leadzero_lvl0_st_high_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table leadzero_lvl1_es_high */ +static const unsigned CONST_TBL_leadzero_lvl1_es_high_0[] = { + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0 +}; + +/* constant table leadzero_lvl1_st_high */ +static const unsigned CONST_TBL_leadzero_lvl1_st_high_0[] = { + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0 +}; + +/* constant table leadzero_lvl2_es_high */ +static const unsigned CONST_TBL_leadzero_lvl2_es_high_0[] = { + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table leadzero_lvl2_st_high */ +static const unsigned CONST_TBL_leadzero_lvl2_st_high_0[] = { + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table leadzero_lvl3_high */ +static const unsigned CONST_TBL_leadzero_lvl3_high_0[] = { + 0xffff000, + 0xffff000, + 0xffff000, + 0xffff000, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff000, + 0xffff000, + 0xffff000, + 0xffff000, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff000, + 0xffff000, + 0xffff000, + 0xffff000, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff000, + 0xffff000, + 0xffff000, + 0xffff000, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff0, + 0 +}; + +/* constant table leadzero_lvl4_high */ +static const unsigned CONST_TBL_leadzero_lvl4_high_0[] = { + 0xf0fff, + 0xf0fff, + 0xf0fff, + 0xf0fff, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfff0f000, + 0xfff0f000, + 0xfff0f000, + 0xfff0f000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf, + 0xf, + 0xf, + 0xf, + 0xff, + 0xff, + 0xff, + 0xff, + 0xf0fff, + 0xf0fff, + 0xf0fff, + 0xf0fff, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfff0f000, + 0xfff0f000, + 0xfff0f000, + 0xfff0f000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf, + 0xf, + 0xf, + 0xf, + 0xff, + 0xff, + 0xff, + 0xff, + 0 +}; + +/* constant table leadzero_lvl5_high */ +static const unsigned CONST_TBL_leadzero_lvl5_high_0[] = { + 0xffff0000, + 0xffff0000, + 0xffff0000, + 0xffff0000, + 0xfff00000, + 0xfff00000, + 0xfff00000, + 0xfff00000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0xf, + 0xf, + 0xf, + 0xf, + 0xff, + 0xff, + 0xff, + 0xff, + 0xfff, + 0xfff, + 0xfff, + 0xfff, + 0xffff, + 0xffff, + 0xffff, + 0xffff, + 0xfffff, + 0xfffff, + 0xfffff, + 0xfffff, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfffff000, + 0xfffff000, + 0xfffff000, + 0xfffff000, + 0 +}; + +/* constant table leadzero_lvl0_es_low */ +static const unsigned CONST_TBL_leadzero_lvl0_es_low_0[] = { + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0x66666666, + 0x99999999, + 0 +}; + +/* constant table leadzero_lvl0_st_low */ +static const unsigned CONST_TBL_leadzero_lvl0_st_low_0[] = { + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0, + 0xffffffff, + 0 +}; + +/* constant table leadzero_lvl1_es_low */ +static const unsigned CONST_TBL_leadzero_lvl1_es_low_0[] = { + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69606960, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x60696069, + 0xc3c3c3c3, + 0x96969696, + 0 +}; + +/* constant table leadzero_lvl1_st_low */ +static const unsigned CONST_TBL_leadzero_lvl1_st_low_0[] = { + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0x3c3c3c3c, + 0x69696969, + 0xc3c3c3c3, + 0x96969696, + 0 +}; + +/* constant table leadzero_lvl2_es_low */ +static const unsigned CONST_TBL_leadzero_lvl2_es_low_0[] = { + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0xfe00fe0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xe00fe00f, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table leadzero_lvl2_st_low */ +static const unsigned CONST_TBL_leadzero_lvl2_st_low_0[] = { + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0x3c003c0, + 0x16801680, + 0x3c003c00, + 0x68016801, + 0xc003c003, + 0x80168016, + 0x3c003c, + 0x1680168, + 0 +}; + +/* constant table leadzero_lvl3_low */ +static const unsigned CONST_TBL_leadzero_lvl3_low_0[] = { + 0xffff000, + 0xffff000, + 0xffff000, + 0xffff000, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff000, + 0xffff000, + 0xffff000, + 0xffff000, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff000, + 0xffff000, + 0xffff000, + 0xffff000, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff000, + 0xffff000, + 0xffff000, + 0xffff000, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xfff0000f, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xf0000fff, + 0xffff0, + 0xffff0, + 0xffff0, + 0xffff0, + 0 +}; + +/* constant table leadzero_lvl4_low */ +static const unsigned CONST_TBL_leadzero_lvl4_low_0[] = { + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf, + 0xf, + 0xf, + 0xf, + 0xff, + 0xff, + 0xff, + 0xff, + 0xf0fff, + 0xf0fff, + 0xf0fff, + 0xf0fff, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfff0f000, + 0xfff0f000, + 0xfff0f000, + 0xfff0f000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf, + 0xf, + 0xf, + 0xf, + 0xff, + 0xff, + 0xff, + 0xff, + 0xf0fff, + 0xf0fff, + 0xf0fff, + 0xf0fff, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfff0f000, + 0xfff0f000, + 0xfff0f000, + 0xfff0f000, + 0 +}; + +/* constant table leadzero_lvl5_low */ +static const unsigned CONST_TBL_leadzero_lvl5_low_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0xf, + 0xf, + 0xf, + 0xf, + 0xff, + 0xff, + 0xff, + 0xff, + 0xfff, + 0xfff, + 0xfff, + 0xfff, + 0xffff, + 0xffff, + 0xffff, + 0xffff, + 0xfffff, + 0xfffff, + 0xfffff, + 0xfffff, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff0, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfffff00, + 0xfffff000, + 0xfffff000, + 0xfffff000, + 0xfffff000, + 0xffff0000, + 0xffff0000, + 0xffff0000, + 0xffff0000, + 0xfff00000, + 0xfff00000, + 0xfff00000, + 0xfff00000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xff000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0xf0000000, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_0 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_0_0[] = { + 0x1060000, + 0xc3081000, + 0xc2081040, + 0x30c2081, + 0xa186081f, + 0x6081f7de, + 0x41800800, + 0x440c2040, + 0x82041000, + 0x82041000, + 0x20041000, + 0x4041000, + 0x41820000, + 0x4082000, + 0x82041000, + 0x1060000, + 0xcd4b2f5, + 0xd3491410, + 0xcd75d34, + 0xb2c71c30, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_1 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_1_0[] = { + 0x30e10828, + 0x71861440, + 0x51441030, + 0x61851441, + 0x49238e28, + 0x38e28a18, + 0x28828418, + 0xa2481c61, + 0x18200c30, + 0x71860c30, + 0x30828618, + 0x92081451, + 0x20828610, + 0xa2081861, + 0x18200c30, + 0x30e10828, + 0xed8d3763, + 0x75965544, + 0xf38e34d3, + 0x7db6cf3c, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_2 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_2_0[] = { + 0x16210484, + 0x2ca24920, + 0x2071c618, + 0x2482071c, + 0x9e69a596, + 0x9a596492, + 0x8c38c388, + 0x3ce34c2c, + 0x14510486, + 0x2492081c, + 0x8e38a20c, + 0x34d30c24, + 0x8e30c38a, + 0x38e30c28, + 0x8e38a286, + 0x16210484, + 0xdcf3f738, + 0x6da65961, + 0xdf7db63c, + 0xe79e38df, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_3 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_3_0[] = { + 0xe3186885, + 0xcf38d30c, + 0xca289248, + 0xb2ca289, + 0xa9a68a27, + 0x68a279e6, + 0x45904904, + 0x544d2450, + 0xa21c7186, + 0x8e34d30c, + 0x24145104, + 0x14451410, + 0x45924104, + 0x14492410, + 0x86145104, + 0xe3186885, + 0x11478410, + 0xdf79d71c, + 0x92451410, + 0xbef7df3c, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_4 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_4_0[] = { + 0x42088c71, + 0x34924503, + 0xd34c30b2, + 0xe38d34c3, + 0xcb2baeaa, + 0xbaeaaa9a, + 0x69869459, + 0xa6585d65, + 0x92088e38, + 0x34923cf3, + 0x71869659, + 0x96185555, + 0x61869651, + 0xa6185965, + 0x59241c71, + 0x42088c71, + 0x34f9492e, + 0x38a28607, + 0x9e384d34, + 0x3082ffff, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_5 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_5_0[] = { + 0x28a90926, + 0x5d655551, + 0x40f3ce38, + 0x45040f3c, + 0xbeebadb6, + 0xbadb6cb2, + 0x9c79c798, + 0x7de75c6d, + 0x2cb28a24, + 0x5555144d, + 0x9e79a61c, + 0x75d71c65, + 0x9e71c79a, + 0x79e71c69, + 0x9e79a696, + 0x28a90926, + 0x57a514e5, + 0x9e696592, + 0x555514e7, + 0x1451040c, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_6 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_6_0[] = { + 0xc94b2e5, + 0xdb699618, + 0xd2491450, + 0x134d2491, + 0xb1c70c2f, + 0x70c2fbee, + 0x49a08a08, + 0x648e2860, + 0xc965924, + 0x9a659618, + 0x28249208, + 0x24861820, + 0x49a28208, + 0x248a2820, + 0x8a249208, + 0xc94b2e5, + 0xfb596e95, + 0xebaa9a28, + 0xba5d7596, + 0x8a249208, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_7 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_7_0[] = { + 0xe98d3663, + 0xf79e75c6, + 0x55545134, + 0x65955545, + 0x4d33cf2c, + 0x3cf2cb1c, + 0xaa8aa49a, + 0xaa689e69, + 0xf38e34d3, + 0xf79e6db6, + 0xb28aa69a, + 0x9a289659, + 0xa28aa692, + 0xaa289a69, + 0x9a282cb2, + 0xe98d3663, + 0xc618ed75, + 0xfbaeb6ca, + 0x9618efbe, + 0xf38e2cb2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_8 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_8_0[] = { + 0x9cf3e738, + 0x8e286181, + 0x6175d659, + 0x6586175d, + 0xdf6db5d7, + 0xdb5d74d3, + 0xacbacba8, + 0xbeeb6cae, + 0x9e79a63c, + 0x8618207d, + 0xaebaaa2c, + 0xb6db2ca6, + 0xaeb2cbaa, + 0xbaeb2caa, + 0xaebaaaa6, + 0x9cf3e738, + 0x69af1967, + 0xcf2c71c2, + 0x6db69a65, + 0x4514103c, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_9 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_9_0[] = { + 0x11468410, + 0xe79a5924, + 0xda699658, + 0x1b6da699, + 0xb9e78e37, + 0x78e37df6, + 0x4db0cb0c, + 0x74cf2c70, + 0x92451410, + 0xa6965924, + 0x2c34d30c, + 0x34c71c30, + 0x4db2c30c, + 0x34cb2c30, + 0x8e34d30c, + 0x11468410, + 0x1cf5b6fd, + 0xf7db5d34, + 0x1cf7df3c, + 0x96555514, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_10 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_10_0[] = { + 0x34e9492a, + 0xbaaaa689, + 0xd75c71b6, + 0xe79d75c7, + 0xcf3befae, + 0xbefaeb9e, + 0xeb8eb4db, + 0xae78df6d, + 0x9a284d34, + 0xbaaa9e79, + 0xf38eb6db, + 0x9e38d75d, + 0xe38eb6d3, + 0xae38db6d, + 0xdb2c3cf3, + 0x34e9492a, + 0xef9d77e7, + 0xbebae78d, + 0xf79e75d7, + 0xb69a5d75, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_8b_11 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_8b_11_0[] = { + 0x56a514a5, + 0xbeeb6db2, + 0x81f7de79, + 0x86081f7d, + 0xffefbdf7, + 0xfbdf7cf3, + 0xbcfbcfb8, + 0xffef7cef, + 0x555514a6, + 0xb6db2cae, + 0xbefbae3c, + 0xf7df3ce7, + 0xbef3cfba, + 0xfbef3ceb, + 0xbefbaeb6, + 0x56a514a5, + 0xfdf7ff79, + 0xffef7df3, + 0xffffbe7d, + 0x75d71c6d, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_lsb_8b_0 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_lsb_8b_0_0[] = { + 0xb2cb2cb2, + 0x66666666, + 0x55555555, + 0x55555555, + 0x55555555, + 0x55555555, + 0xcccccccc, + 0, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xb2cb2cb2, + 0x2cb2cb2c, + 0x66666666, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_lo_lsb_8b_1 */ +static const unsigned CONST_TBL_ivp_sem_dseli_lo_lsb_8b_1_0[] = { + 0x2cb2cb2c, + 0x66666666, + 0x55555555, + 0x55555555, + 0x55555555, + 0x55555555, + 0xcccccccc, + 0, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0x2cb2cb2c, + 0xcb2cb2cb, + 0x66666666, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_0 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_0_0[] = { + 0xeb596a95, + 0x7144081, + 0xc3082041, + 0x40c3082, + 0x618207df, + 0x207df79e, + 0x51c10c10, + 0x440c2040, + 0xaa5d7596, + 0x8a145104, + 0x30451410, + 0x860c3082, + 0x51c30410, + 0x450c3041, + 0x92451410, + 0xeb596a95, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_1 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_1_0[] = { + 0xc618ad75, + 0x38d2ca2, + 0x61451040, + 0x71861451, + 0x48e38a28, + 0x38a28618, + 0x2c92c51c, + 0xa2481c61, + 0x9618aeba, + 0x14102cb2, + 0x3492c71c, + 0xb28a1c71, + 0x2492c714, + 0xb2491c71, + 0x1c304d34, + 0xc618ad75, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_2 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_2_0[] = { + 0x69ab1966, + 0x5d651345, + 0x2081c718, + 0x2492081c, + 0x9a696592, + 0x9659248e, + 0xcd3cd3c9, + 0x3ce34c2c, + 0x6db69a65, + 0x5d759645, + 0xcf3cb24d, + 0x3cf38e2c, + 0xcf34d3cb, + 0x3cf34d2c, + 0xcf3cb2c7, + 0x69ab1966, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_3 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_3_0[] = { + 0x1cb5b6ed, + 0x1f75c699, + 0xcb28a249, + 0xc2cb28a, + 0x69a289e7, + 0x289e79a6, + 0x55d14d14, + 0x544d2450, + 0x1cb6db2c, + 0xa275d71c, + 0x34555514, + 0x964d3492, + 0x55d34514, + 0x554d3451, + 0x96555514, + 0x1cb5b6ed, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_4 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_4_0[] = { + 0xeb9d76e7, + 0x89a58e28, + 0xe34d30c2, + 0xf38e34d3, + 0xcaebaaaa, + 0xbaaaa69a, + 0x6d96d55d, + 0xa6585d65, + 0xf79e75d7, + 0x9a288e38, + 0x7596d75d, + 0xb69a5d75, + 0x6596d755, + 0xb6595d75, + 0x5d345d75, + 0xeb9d76e7, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_5 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_5_0[] = { + 0xbdf7ef79, + 0xbeeb2ba6, + 0x4103cf38, + 0x4514103c, + 0xbaeb6db2, + 0xb6db2cae, + 0xdd7dd7d9, + 0x7de75c6d, + 0xbefbae7d, + 0xbefbaea6, + 0xdf7db65d, + 0x7df79e6d, + 0xdf75d7db, + 0x7df75d6d, + 0xdf7db6d7, + 0xbdf7ef79, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_6 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_6_0[] = { + 0x1070000, + 0x17554491, + 0xd3492451, + 0x144d3492, + 0x71c30bef, + 0x30befbae, + 0x59e18e18, + 0x648e2860, + 0x82041000, + 0xbad75d34, + 0x38659618, + 0xa68e38a2, + 0x59e38618, + 0x658e3861, + 0x9a659618, + 0x1070000, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_7 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_7_0[] = { + 0x30f1082c, + 0x79d6da6, + 0x65555144, + 0x75965555, + 0x4cf3cb2c, + 0x3cb2c71c, + 0xae9ae59e, + 0xaa689e69, + 0x1c300c30, + 0x1000efbe, + 0xb69ae79e, + 0xbaaa9e79, + 0xa69ae796, + 0xba699e79, + 0x9e386db6, + 0x30f1082c, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_8 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_8_0[] = { + 0x172104c4, + 0x9e692386, + 0x6185d759, + 0x6596185d, + 0xdb6d75d3, + 0xd75d34cf, + 0xedbedbe9, + 0xbeeb6cae, + 0x145104c7, + 0x1c718604, + 0xefbeba6d, + 0xbefbaeae, + 0xefb6dbeb, + 0xbefb6dae, + 0xefbebae7, + 0x172104c4, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_9 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_9_0[] = { + 0xf3186c85, + 0x2fb6caa9, + 0xdb69a659, + 0x1c6db69a, + 0x79e38df7, + 0x38df7db6, + 0x5df1cf1c, + 0x74cf2c70, + 0xb21c7186, + 0x9234d30c, + 0x3c75d71c, + 0xb6cf3cb2, + 0x5df3c71c, + 0x75cf3c71, + 0x9e75d71c, + 0xf3186c85, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_10 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_10_0[] = { + 0x4208cc71, + 0x8db5cf2c, + 0xe75d71c6, + 0xf79e75d7, + 0xcefbebae, + 0xbebae79e, + 0xef9ef5df, + 0xae78df6d, + 0x9208cf3c, + 0x96184d34, + 0xf79ef7df, + 0xbebadf7d, + 0xe79ef7d7, + 0xbe79df7d, + 0xdf3c7df7, + 0x4208cc71, + 0 +}; + +/* constant table ivp_sem_dseli_hi_8b_11 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_8b_11_0[] = { + 0x28ad0927, + 0xffef3be7, + 0x8207df79, + 0x8618207d, + 0xfbef7df3, + 0xf7df3cef, + 0xfdffdff9, + 0xffef7cef, + 0x2cb28a24, + 0x7df79e65, + 0xffffbe7d, + 0xffffbeef, + 0xfff7dffb, + 0xffff7def, + 0xffffbef7, + 0x28ad0927, + 0 +}; + +/* constant table ivp_sem_dseli_hi_lsb_8b_0 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_lsb_8b_0_0[] = { + 0xcb2cb2cb, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xcccccccc, + 0xffffffff, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xcb2cb2cb, + 0 +}; + +/* constant table ivp_sem_dseli_hi_lsb_8b_1 */ +static const unsigned CONST_TBL_ivp_sem_dseli_hi_lsb_8b_1_0[] = { + 0xb2cb2cb2, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xcccccccc, + 0xffffffff, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0xb2cb2cb2, + 0 +}; + +/* constant table ivp_sem_special_seli8_0 */ +static const unsigned CONST_TBL_ivp_sem_special_seli8_0_0[] = { + 0x86082fbe, + 0x4f3cf3c, + 0xbafbeeba, + 0x38e38e38, + 0, + 0, + 0, + 0, + 0x82186082, + 0xc104104, + 0x8e28a186, + 0x8208208, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x4704307f, + 0xc11c10c1, + 0xc50fdffd, + 0x43147143, + 0x7bf7ff7b, + 0xcd2c51c5, + 0xf9ff9ef9, + 0x4f24b247, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_special_seli8_1 */ +static const unsigned CONST_TBL_ivp_sem_special_seli8_1_0[] = { + 0x238e0821, + 0xc30c1041, + 0xe28a186e, + 0x8208e38e, + 0, + 0, + 0, + 0, + 0x608238e0, + 0x410430c3, + 0xa18628a3, + 0x86182082, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x304f0430, + 0x10c13c10, + 0xd3cd0c51, + 0x714334f3, + 0xf34b1471, + 0x51c52cd3, + 0x92c91f9e, + 0xb64724b2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_special_seli8_2 */ +static const unsigned CONST_TBL_ivp_sem_special_seli8_2_0[] = { + 0x8218608, + 0x10410430, + 0x18628a38, + 0x20820820, + 0, + 0, + 0, + 0, + 0x79e08218, + 0x71c71c10, + 0x69a79e69, + 0x61861861, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x4304704, + 0x7c10c11c, + 0xc51c50c, + 0x75f74314, + 0x14714b34, + 0x6dd7dd6c, + 0x1c92c93c, + 0x65b65f65, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_special_seli8_3 */ +static const unsigned CONST_TBL_ivp_sem_special_seli8_3_0[] = { + 0x8608279e, + 0x471c71c, + 0x9a79e69a, + 0x18618618, + 0, + 0, + 0, + 0, + 0x82186082, + 0xc104104, + 0x8e28a186, + 0x8208208, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x4704305f, + 0xc11c10c1, + 0xc50dd7dd, + 0x43147143, + 0x5b75f75b, + 0xcd2c51c5, + 0xd97d96d9, + 0x4f24b247, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_special_seli8_4 */ +static const unsigned CONST_TBL_ivp_sem_special_seli8_4_0[] = { + 0x238e0821, + 0xc30c1041, + 0xe28a1866, + 0x82086186, + 0, + 0, + 0, + 0, + 0x608238e0, + 0x410430c3, + 0xa18628a3, + 0x8e382082, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x304f0430, + 0x10c13c10, + 0xd3cd0c51, + 0x714334f3, + 0xf34b1471, + 0x51c52cd3, + 0x92c91d96, + 0xbe4724b2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_special_seli8_5 */ +static const unsigned CONST_TBL_ivp_sem_special_seli8_5_0[] = { + 0x8218608, + 0x10410430, + 0x18628a38, + 0x20820820, + 0, + 0, + 0, + 0, + 0xfbe08218, + 0xf3cf3c10, + 0xebafbeeb, + 0xe38e38e3, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x4304704, + 0xfc10c11c, + 0xc51c50c, + 0xf7ff4314, + 0x14714b34, + 0xefdffdec, + 0x1c92c93c, + 0xe7be7fe7, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_special_seli8_msb_0 */ +static const unsigned CONST_TBL_ivp_sem_special_seli8_msb_0_0[] = { + 0x3, + 0xf, + 0x3f, + 0xff, + 0, + 0, + 0, + 0, + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0, + 0, + 0, + 0, + 0, + 0x11111111, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0x1, + 0xffffffff, + 0x7, + 0xffffffff, + 0x1f, + 0xffffffff, + 0x7f, + 0xffffffff, + 0xcccccccc, + 0xcccccccd, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* constant table ivp_sem_special_seli8_msb_1 */ +static const unsigned CONST_TBL_ivp_sem_special_seli8_msb_1_0[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x3fffffff, + 0xfffffff, + 0x3ffffff, + 0xffffff, + 0, + 0, + 0, + 0, + 0, + 0x11111111, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0, + 0x7fffffff, + 0, + 0x1fffffff, + 0, + 0x7ffffff, + 0, + 0x1ffffff, + 0xcccccccc, + 0xcccccccd, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; + + +/* Instruction operands. */ + +static int +OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_out_0; + unsigned soffsetx4_in_0; + soffsetx4_in_0 = *valp & 0x3ffff; + soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); + *valp = soffsetx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) +{ + unsigned soffsetx4_in_0; + unsigned soffsetx4_out_0; + soffsetx4_out_0 = *valp; + soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; + *valp = soffsetx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_out_0; + unsigned uimm12x8_in_0; + uimm12x8_in_0 = *valp & 0xfff; + uimm12x8_out_0 = uimm12x8_in_0 << 3; + *valp = uimm12x8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) +{ + unsigned uimm12x8_in_0; + unsigned uimm12x8_out_0; + uimm12x8_out_0 = *valp; + uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); + *valp = uimm12x8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_decode (uint32 *valp) +{ + unsigned simm4_out_0; + unsigned simm4_in_0; + simm4_in_0 = *valp & 0xf; + simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; + *valp = simm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_encode (uint32 *valp) +{ + unsigned simm4_in_0; + unsigned simm4_out_0; + simm4_out_0 = *valp; + simm4_in_0 = (simm4_out_0 & 0xf); + *valp = simm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_0_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_1_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_2_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_3_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_4_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_out_0; + unsigned immrx4_in_0; + immrx4_in_0 = *valp & 0xf; + immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; + *valp = immrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immrx4_encode (uint32 *valp) +{ + unsigned immrx4_in_0; + unsigned immrx4_out_0; + immrx4_out_0 = *valp; + immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); + *valp = immrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_out_0; + unsigned lsi4x4_in_0; + lsi4x4_in_0 = *valp & 0xf; + lsi4x4_out_0 = lsi4x4_in_0 << 2; + *valp = lsi4x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) +{ + unsigned lsi4x4_in_0; + unsigned lsi4x4_out_0; + lsi4x4_out_0 = *valp; + lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); + *valp = lsi4x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_decode (uint32 *valp) +{ + unsigned simm7_out_0; + unsigned simm7_in_0; + simm7_in_0 = *valp & 0x7f; + simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; + *valp = simm7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_encode (uint32 *valp) +{ + unsigned simm7_in_0; + unsigned simm7_out_0; + simm7_out_0 = *valp; + simm7_in_0 = (simm7_out_0 & 0x7f); + *valp = simm7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_out_0; + unsigned uimm6_in_0; + uimm6_in_0 = *valp & 0x3f; + uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); + *valp = uimm6_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_encode (uint32 *valp) +{ + unsigned uimm6_in_0; + unsigned uimm6_out_0; + uimm6_out_0 = *valp; + uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; + *valp = uimm6_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_out_0; + unsigned ai4const_in_0; + ai4const_in_0 = *valp & 0xf; + ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; + *valp = ai4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_encode (uint32 *valp) +{ + unsigned ai4const_in_0; + unsigned ai4const_out_0; + ai4const_out_0 = *valp; + switch (ai4const_out_0) + { + case 0xffffffff: ai4const_in_0 = 0; break; + case 0x1: ai4const_in_0 = 0x1; break; + case 0x2: ai4const_in_0 = 0x2; break; + case 0x3: ai4const_in_0 = 0x3; break; + case 0x4: ai4const_in_0 = 0x4; break; + case 0x5: ai4const_in_0 = 0x5; break; + case 0x6: ai4const_in_0 = 0x6; break; + case 0x7: ai4const_in_0 = 0x7; break; + case 0x8: ai4const_in_0 = 0x8; break; + case 0x9: ai4const_in_0 = 0x9; break; + case 0xa: ai4const_in_0 = 0xa; break; + case 0xb: ai4const_in_0 = 0xb; break; + case 0xc: ai4const_in_0 = 0xc; break; + case 0xd: ai4const_in_0 = 0xd; break; + case 0xe: ai4const_in_0 = 0xe; break; + default: ai4const_in_0 = 0xf; break; + } + *valp = ai4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_decode (uint32 *valp) +{ + unsigned b4const_out_0; + unsigned b4const_in_0; + b4const_in_0 = *valp & 0xf; + b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; + *valp = b4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_encode (uint32 *valp) +{ + unsigned b4const_in_0; + unsigned b4const_out_0; + b4const_out_0 = *valp; + switch (b4const_out_0) + { + case 0xffffffff: b4const_in_0 = 0; break; + case 0x1: b4const_in_0 = 0x1; break; + case 0x2: b4const_in_0 = 0x2; break; + case 0x3: b4const_in_0 = 0x3; break; + case 0x4: b4const_in_0 = 0x4; break; + case 0x5: b4const_in_0 = 0x5; break; + case 0x6: b4const_in_0 = 0x6; break; + case 0x7: b4const_in_0 = 0x7; break; + case 0x8: b4const_in_0 = 0x8; break; + case 0xa: b4const_in_0 = 0x9; break; + case 0xc: b4const_in_0 = 0xa; break; + case 0x10: b4const_in_0 = 0xb; break; + case 0x20: b4const_in_0 = 0xc; break; + case 0x40: b4const_in_0 = 0xd; break; + case 0x80: b4const_in_0 = 0xe; break; + default: b4const_in_0 = 0xf; break; + } + *valp = b4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_out_0; + unsigned b4constu_in_0; + b4constu_in_0 = *valp & 0xf; + b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; + *valp = b4constu_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_encode (uint32 *valp) +{ + unsigned b4constu_in_0; + unsigned b4constu_out_0; + b4constu_out_0 = *valp; + switch (b4constu_out_0) + { + case 0x8000: b4constu_in_0 = 0; break; + case 0x10000: b4constu_in_0 = 0x1; break; + case 0x2: b4constu_in_0 = 0x2; break; + case 0x3: b4constu_in_0 = 0x3; break; + case 0x4: b4constu_in_0 = 0x4; break; + case 0x5: b4constu_in_0 = 0x5; break; + case 0x6: b4constu_in_0 = 0x6; break; + case 0x7: b4constu_in_0 = 0x7; break; + case 0x8: b4constu_in_0 = 0x8; break; + case 0xa: b4constu_in_0 = 0x9; break; + case 0xc: b4constu_in_0 = 0xa; break; + case 0x10: b4constu_in_0 = 0xb; break; + case 0x20: b4constu_in_0 = 0xc; break; + case 0x40: b4constu_in_0 = 0xd; break; + case 0x80: b4constu_in_0 = 0xe; break; + default: b4constu_in_0 = 0xf; break; + } + *valp = b4constu_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_out_0; + unsigned uimm8_in_0; + uimm8_in_0 = *valp & 0xff; + uimm8_out_0 = uimm8_in_0; + *valp = uimm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_encode (uint32 *valp) +{ + unsigned uimm8_in_0; + unsigned uimm8_out_0; + uimm8_out_0 = *valp; + uimm8_in_0 = (uimm8_out_0 & 0xff); + *valp = uimm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_out_0; + unsigned uimm8x2_in_0; + uimm8x2_in_0 = *valp & 0xff; + uimm8x2_out_0 = uimm8x2_in_0 << 1; + *valp = uimm8x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) +{ + unsigned uimm8x2_in_0; + unsigned uimm8x2_out_0; + uimm8x2_out_0 = *valp; + uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); + *valp = uimm8x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_out_0; + unsigned uimm8x4_in_0; + uimm8x4_in_0 = *valp & 0xff; + uimm8x4_out_0 = uimm8x4_in_0 << 2; + *valp = uimm8x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) +{ + unsigned uimm8x4_in_0; + unsigned uimm8x4_out_0; + uimm8x4_out_0 = *valp; + uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); + *valp = uimm8x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_out_0; + unsigned uimm4x16_in_0; + uimm4x16_in_0 = *valp & 0xf; + uimm4x16_out_0 = uimm4x16_in_0 << 4; + *valp = uimm4x16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) +{ + unsigned uimm4x16_in_0; + unsigned uimm4x16_out_0; + uimm4x16_out_0 = *valp; + uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); + *valp = uimm4x16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp) +{ + unsigned uimmrx4_out_0; + unsigned uimmrx4_in_0; + uimmrx4_in_0 = *valp & 0xf; + uimmrx4_out_0 = uimmrx4_in_0 << 2; + *valp = uimmrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp) +{ + unsigned uimmrx4_in_0; + unsigned uimmrx4_out_0; + uimmrx4_out_0 = *valp; + uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf); + *valp = uimmrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_decode (uint32 *valp) +{ + unsigned simm8_out_0; + unsigned simm8_in_0; + simm8_in_0 = *valp & 0xff; + simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; + *valp = simm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_encode (uint32 *valp) +{ + unsigned simm8_in_0; + unsigned simm8_out_0; + simm8_out_0 = *valp; + simm8_in_0 = (simm8_out_0 & 0xff); + *valp = simm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_out_0; + unsigned simm8x256_in_0; + simm8x256_in_0 = *valp & 0xff; + simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; + *valp = simm8x256_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) +{ + unsigned simm8x256_in_0; + unsigned simm8x256_out_0; + simm8x256_out_0 = *valp; + simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); + *valp = simm8x256_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_out_0; + unsigned simm12b_in_0; + simm12b_in_0 = *valp & 0xfff; + simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; + *valp = simm12b_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_encode (uint32 *valp) +{ + unsigned simm12b_in_0; + unsigned simm12b_out_0; + simm12b_out_0 = *valp; + simm12b_in_0 = (simm12b_out_0 & 0xfff); + *valp = simm12b_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_out_0; + unsigned msalp32_in_0; + msalp32_in_0 = *valp & 0x1f; + msalp32_out_0 = 0x20 - msalp32_in_0; + *valp = msalp32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_encode (uint32 *valp) +{ + unsigned msalp32_in_0; + unsigned msalp32_out_0; + msalp32_out_0 = *valp; + msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; + *valp = msalp32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_out_0; + unsigned op2p1_in_0; + op2p1_in_0 = *valp & 0xf; + op2p1_out_0 = op2p1_in_0 + 0x1; + *valp = op2p1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_encode (uint32 *valp) +{ + unsigned op2p1_in_0; + unsigned op2p1_out_0; + op2p1_out_0 = *valp; + op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; + *valp = op2p1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_decode (uint32 *valp) +{ + unsigned label8_out_0; + unsigned label8_in_0; + label8_in_0 = *valp & 0xff; + label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); + *valp = label8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_encode (uint32 *valp) +{ + unsigned label8_in_0; + unsigned label8_out_0; + label8_out_0 = *valp; + label8_in_0 = (label8_out_0 - 0x4) & 0xff; + *valp = label8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_out_0; + unsigned ulabel8_in_0; + ulabel8_in_0 = *valp & 0xff; + ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); + *valp = ulabel8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) +{ + unsigned ulabel8_in_0; + unsigned ulabel8_out_0; + ulabel8_out_0 = *valp; + ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; + *valp = ulabel8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_decode (uint32 *valp) +{ + unsigned label12_out_0; + unsigned label12_in_0; + label12_in_0 = *valp & 0xfff; + label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); + *valp = label12_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_encode (uint32 *valp) +{ + unsigned label12_in_0; + unsigned label12_out_0; + label12_out_0 = *valp; + label12_in_0 = (label12_out_0 - 0x4) & 0xfff; + *valp = label12_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_decode (uint32 *valp) +{ + unsigned soffset_out_0; + unsigned soffset_in_0; + soffset_in_0 = *valp & 0x3ffff; + soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); + *valp = soffset_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_encode (uint32 *valp) +{ + unsigned soffset_in_0; + unsigned soffset_out_0; + soffset_out_0 = *valp; + soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; + *valp = soffset_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_out_0; + unsigned uimm16x4_in_0; + uimm16x4_in_0 = *valp & 0xffff; + uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; + *valp = uimm16x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) +{ + unsigned uimm16x4_in_0; + unsigned uimm16x4_out_0; + uimm16x4_out_0 = *valp; + uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; + *valp = uimm16x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_decode (uint32 *valp) +{ + unsigned bbi_out_0; + unsigned bbi_in_0; + bbi_in_0 = *valp & 0x1f; + bbi_out_0 = (0 << 5) | bbi_in_0; + *valp = bbi_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_encode (uint32 *valp) +{ + unsigned bbi_in_0; + unsigned bbi_out_0; + bbi_out_0 = *valp; + bbi_in_0 = (bbi_out_0 & 0x1f); + *valp = bbi_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_imm16_decode (uint32 *valp) +{ + unsigned imm16_out_0; + unsigned imm16_in_0; + imm16_in_0 = *valp & 0xffff; + imm16_out_0 = (0 << 16) | imm16_in_0; + *valp = imm16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_imm16_encode (uint32 *valp) +{ + unsigned imm16_in_0; + unsigned imm16_out_0; + imm16_out_0 = *valp; + imm16_in_0 = (imm16_out_0 & 0xffff); + *valp = imm16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_decode (uint32 *valp) +{ + unsigned s_out_0; + unsigned s_in_0; + s_in_0 = *valp & 0xf; + s_out_0 = (0 << 4) | s_in_0; + *valp = s_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_encode (uint32 *valp) +{ + unsigned s_in_0; + unsigned s_out_0; + s_out_0 = *valp; + s_in_0 = (s_out_0 & 0xf); + *valp = s_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_decode (uint32 *valp) +{ + unsigned immt_out_0; + unsigned immt_in_0; + immt_in_0 = *valp & 0xf; + immt_out_0 = immt_in_0; + *valp = immt_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_encode (uint32 *valp) +{ + unsigned immt_in_0; + unsigned immt_out_0; + immt_out_0 = *valp; + immt_in_0 = immt_out_0 & 0xf; + *valp = immt_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_BR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16); + return error; +} + +static int +OperandSem_opnd_sem_BR2_decode (uint32 *valp) +{ + *valp = *valp << 1; + return 0; +} + +static int +OperandSem_opnd_sem_BR2_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 1) != 0); + *valp = *valp >> 1; + return error; +} + +static int +OperandSem_opnd_sem_BR4_decode (uint32 *valp) +{ + *valp = *valp << 2; + return 0; +} + +static int +OperandSem_opnd_sem_BR4_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 3) != 0); + *valp = *valp >> 2; + return error; +} + +static int +OperandSem_opnd_sem_BR8_decode (uint32 *valp) +{ + *valp = *valp << 3; + return 0; +} + +static int +OperandSem_opnd_sem_BR8_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 7) != 0); + *valp = *valp >> 3; + return error; +} + +static int +OperandSem_opnd_sem_BR16_decode (uint32 *valp) +{ + *valp = *valp << 4; + return 0; +} + +static int +OperandSem_opnd_sem_BR16_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 15) != 0); + *valp = *valp >> 4; + return error; +} + +static int +OperandSem_opnd_sem_tp7_decode (uint32 *valp) +{ + unsigned tp7_out_0; + unsigned tp7_in_0; + tp7_in_0 = *valp & 0xf; + tp7_out_0 = tp7_in_0 + 0x7; + *valp = tp7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_tp7_encode (uint32 *valp) +{ + unsigned tp7_in_0; + unsigned tp7_out_0; + tp7_out_0 = *valp; + tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; + *valp = tp7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_out_0; + unsigned xt_wbr15_label_in_0; + xt_wbr15_label_in_0 = *valp & 0x7fff; + xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); + *valp = xt_wbr15_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_label_in_0; + unsigned xt_wbr15_label_out_0; + xt_wbr15_label_out_0 = *valp; + xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp) +{ + unsigned xt_wbr18_label_out_0; + unsigned xt_wbr18_label_in_0; + xt_wbr18_label_in_0 = *valp & 0x3ffff; + xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14); + *valp = xt_wbr18_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp) +{ + unsigned xt_wbr18_label_in_0; + unsigned xt_wbr18_label_out_0; + xt_wbr18_label_out_0 = *valp; + xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff; + *valp = xt_wbr18_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_vec_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_vec_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_vbool_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_vbool_encode (uint32 *valp) +{ + int error; + error = (*valp >= 8); + return error; +} + +static int +OperandSem_opnd_sem_wvec_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_wvec_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_divide_lane_ctrl_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_divide_lane_ctrl_out_0; + unsigned opnd_ivp_sem_divide_lane_ctrl_in_0; + opnd_ivp_sem_divide_lane_ctrl_in_0 = *valp & 0x1; + opnd_ivp_sem_divide_lane_ctrl_out_0 = (0 << 1) | opnd_ivp_sem_divide_lane_ctrl_in_0; + *valp = opnd_ivp_sem_divide_lane_ctrl_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_divide_lane_ctrl_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_divide_lane_ctrl_in_0; + unsigned opnd_ivp_sem_divide_lane_ctrl_out_0; + opnd_ivp_sem_divide_lane_ctrl_out_0 = *valp; + opnd_ivp_sem_divide_lane_ctrl_in_0 = (((opnd_ivp_sem_divide_lane_ctrl_out_0 >> 0) & 1)) & 0x1; + *valp = opnd_ivp_sem_divide_lane_ctrl_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_i_imm4_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_vec_mov_i_imm4_out_0; + unsigned opnd_ivp_sem_vec_mov_i_imm4_in_0; + opnd_ivp_sem_vec_mov_i_imm4_in_0 = *valp & 0xf; + opnd_ivp_sem_vec_mov_i_imm4_out_0 = (0 << 4) | opnd_ivp_sem_vec_mov_i_imm4_in_0; + *valp = opnd_ivp_sem_vec_mov_i_imm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_i_imm4_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_vec_mov_i_imm4_in_0; + unsigned opnd_ivp_sem_vec_mov_i_imm4_out_0; + opnd_ivp_sem_vec_mov_i_imm4_out_0 = *valp; + opnd_ivp_sem_vec_mov_i_imm4_in_0 = (opnd_ivp_sem_vec_mov_i_imm4_out_0 & 0xf); + *valp = opnd_ivp_sem_vec_mov_i_imm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_vec_select_slct_h_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_vec_select_slct_h_out_0; + unsigned opnd_ivp_sem_vec_select_slct_h_in_0; + opnd_ivp_sem_vec_select_slct_h_in_0 = *valp & 0x3; + opnd_ivp_sem_vec_select_slct_h_out_0 = (0 << 2) | opnd_ivp_sem_vec_select_slct_h_in_0; + *valp = opnd_ivp_sem_vec_select_slct_h_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_vec_select_slct_h_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_vec_select_slct_h_in_0; + unsigned opnd_ivp_sem_vec_select_slct_h_out_0; + opnd_ivp_sem_vec_select_slct_h_out_0 = *valp; + opnd_ivp_sem_vec_select_slct_h_in_0 = (opnd_ivp_sem_vec_select_slct_h_out_0 & 0x3); + *valp = opnd_ivp_sem_vec_select_slct_h_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm4_decode (uint32 *valp) +{ + unsigned saimm4_out_0; + unsigned saimm4_in_0; + saimm4_in_0 = *valp & 0x7; + saimm4_out_0 = (0 << 3) | saimm4_in_0; + *valp = saimm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm4_encode (uint32 *valp) +{ + unsigned saimm4_in_0; + unsigned saimm4_out_0; + saimm4_out_0 = *valp; + saimm4_in_0 = (saimm4_out_0 & 0x7); + *valp = saimm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm5_decode (uint32 *valp) +{ + unsigned saimm5_out_0; + unsigned saimm5_in_0; + saimm5_in_0 = *valp & 0xf; + saimm5_out_0 = (0 << 4) | saimm5_in_0; + *valp = saimm5_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm5_encode (uint32 *valp) +{ + unsigned saimm5_in_0; + unsigned saimm5_out_0; + saimm5_out_0 = *valp; + saimm5_in_0 = (saimm5_out_0 & 0xf); + *valp = saimm5_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm6_31_decode (uint32 *valp) +{ + unsigned saimm6_31_out_0; + unsigned saimm6_31_in_0; + saimm6_31_in_0 = *valp & 0x1f; + saimm6_31_out_0 = (0 << 5) | saimm6_31_in_0; + *valp = saimm6_31_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm6_31_encode (uint32 *valp) +{ + unsigned saimm6_31_in_0; + unsigned saimm6_31_out_0; + saimm6_31_out_0 = *valp; + saimm6_31_in_0 = (saimm6_31_out_0 & 0x1f); + *valp = saimm6_31_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_valign_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_valign_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6_in_0; + opnd_ivp_sem_ld_st_i_bimm6_in_0 = *valp & 0x3f; + opnd_ivp_sem_ld_st_i_bimm6_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm6_in_0 >> 1) & 0x1f)) | 0xffffffe0)) == 0xffffffff))) & 0x3ffffff) << 6) | opnd_ivp_sem_ld_st_i_bimm6_in_0) << 6; + *valp = opnd_ivp_sem_ld_st_i_bimm6_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6_out_0; + opnd_ivp_sem_ld_st_i_bimm6_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm6_in_0 = ((opnd_ivp_sem_ld_st_i_bimm6_out_0 >> 6) & 0x3f); + *valp = opnd_ivp_sem_ld_st_i_bimm6_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4_in_0; + opnd_ivp_sem_ld_st_i_bimm4_in_0 = *valp & 0xf; + opnd_ivp_sem_ld_st_i_bimm4_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm4_in_0 >> 1) & 0x7)) | 0xfffffff8)) == 0xffffffff))) & 0xfffffff) << 4) | opnd_ivp_sem_ld_st_i_bimm4_in_0) << 6; + *valp = opnd_ivp_sem_ld_st_i_bimm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4_out_0; + opnd_ivp_sem_ld_st_i_bimm4_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm4_in_0 = ((opnd_ivp_sem_ld_st_i_bimm4_out_0 >> 6) & 0xf); + *valp = opnd_ivp_sem_ld_st_i_bimm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6b2n_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6b2n_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6b2n_in_0; + opnd_ivp_sem_ld_st_i_bimm6b2n_in_0 = *valp & 0x3f; + opnd_ivp_sem_ld_st_i_bimm6b2n_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm6b2n_in_0 >> 1) & 0x1f)) | 0xffffffe0)) == 0xffffffff))) & 0x3ffffff) << 6) | opnd_ivp_sem_ld_st_i_bimm6b2n_in_0) << 3; + *valp = opnd_ivp_sem_ld_st_i_bimm6b2n_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6b2n_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6b2n_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6b2n_out_0; + opnd_ivp_sem_ld_st_i_bimm6b2n_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm6b2n_in_0 = ((opnd_ivp_sem_ld_st_i_bimm6b2n_out_0 >> 3) & 0x3f); + *valp = opnd_ivp_sem_ld_st_i_bimm6b2n_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4b2n_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4b2n_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4b2n_in_0; + opnd_ivp_sem_ld_st_i_bimm4b2n_in_0 = *valp & 0xf; + opnd_ivp_sem_ld_st_i_bimm4b2n_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm4b2n_in_0 >> 1) & 0x7)) | 0xfffffff8)) == 0xffffffff))) & 0xfffffff) << 4) | opnd_ivp_sem_ld_st_i_bimm4b2n_in_0) << 3; + *valp = opnd_ivp_sem_ld_st_i_bimm4b2n_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4b2n_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4b2n_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4b2n_out_0; + opnd_ivp_sem_ld_st_i_bimm4b2n_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm4b2n_in_0 = ((opnd_ivp_sem_ld_st_i_bimm4b2n_out_0 >> 3) & 0xf); + *valp = opnd_ivp_sem_ld_st_i_bimm4b2n_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_2_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6bn_2_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6bn_2_in_0; + opnd_ivp_sem_ld_st_i_bimm6bn_2_in_0 = *valp & 0x3f; + opnd_ivp_sem_ld_st_i_bimm6bn_2_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm6bn_2_in_0 >> 1) & 0x1f)) | 0xffffffe0)) == 0xffffffff))) & 0x3ffffff) << 6) | opnd_ivp_sem_ld_st_i_bimm6bn_2_in_0) << 1; + *valp = opnd_ivp_sem_ld_st_i_bimm6bn_2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_2_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6bn_2_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6bn_2_out_0; + opnd_ivp_sem_ld_st_i_bimm6bn_2_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm6bn_2_in_0 = ((opnd_ivp_sem_ld_st_i_bimm6bn_2_out_0 >> 1) & 0x3f); + *valp = opnd_ivp_sem_ld_st_i_bimm6bn_2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_2_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4bn_2_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4bn_2_in_0; + opnd_ivp_sem_ld_st_i_bimm4bn_2_in_0 = *valp & 0xf; + opnd_ivp_sem_ld_st_i_bimm4bn_2_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm4bn_2_in_0 >> 1) & 0x7)) | 0xfffffff8)) == 0xffffffff))) & 0xfffffff) << 4) | opnd_ivp_sem_ld_st_i_bimm4bn_2_in_0) << 1; + *valp = opnd_ivp_sem_ld_st_i_bimm4bn_2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_2_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4bn_2_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4bn_2_out_0; + opnd_ivp_sem_ld_st_i_bimm4bn_2_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm4bn_2_in_0 = ((opnd_ivp_sem_ld_st_i_bimm4bn_2_out_0 >> 1) & 0xf); + *valp = opnd_ivp_sem_ld_st_i_bimm4bn_2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6bn_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6bn_in_0; + opnd_ivp_sem_ld_st_i_bimm6bn_in_0 = *valp & 0x3f; + opnd_ivp_sem_ld_st_i_bimm6bn_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm6bn_in_0 >> 1) & 0x1f)) | 0xffffffe0)) == 0xffffffff))) & 0x3ffffff) << 6) | opnd_ivp_sem_ld_st_i_bimm6bn_in_0) << 2; + *valp = opnd_ivp_sem_ld_st_i_bimm6bn_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6bn_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6bn_out_0; + opnd_ivp_sem_ld_st_i_bimm6bn_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm6bn_in_0 = ((opnd_ivp_sem_ld_st_i_bimm6bn_out_0 >> 2) & 0x3f); + *valp = opnd_ivp_sem_ld_st_i_bimm6bn_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4bn_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4bn_in_0; + opnd_ivp_sem_ld_st_i_bimm4bn_in_0 = *valp & 0xf; + opnd_ivp_sem_ld_st_i_bimm4bn_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm4bn_in_0 >> 1) & 0x7)) | 0xfffffff8)) == 0xffffffff))) & 0xfffffff) << 4) | opnd_ivp_sem_ld_st_i_bimm4bn_in_0) << 2; + *valp = opnd_ivp_sem_ld_st_i_bimm4bn_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4bn_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4bn_out_0; + opnd_ivp_sem_ld_st_i_bimm4bn_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm4bn_in_0 = ((opnd_ivp_sem_ld_st_i_bimm4bn_out_0 >> 2) & 0xf); + *valp = opnd_ivp_sem_ld_st_i_bimm4bn_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6x1_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6x1_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6x1_in_0; + opnd_ivp_sem_ld_st_i_bimm6x1_in_0 = *valp & 0x3f; + opnd_ivp_sem_ld_st_i_bimm6x1_out_0 = (((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm6x1_in_0 >> 1) & 0x1f)) | 0xffffffe0)) == 0xffffffff))) & 0x3ffffff) << 6) | opnd_ivp_sem_ld_st_i_bimm6x1_in_0; + *valp = opnd_ivp_sem_ld_st_i_bimm6x1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6x1_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm6x1_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm6x1_out_0; + opnd_ivp_sem_ld_st_i_bimm6x1_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm6x1_in_0 = (opnd_ivp_sem_ld_st_i_bimm6x1_out_0 & 0x3f); + *valp = opnd_ivp_sem_ld_st_i_bimm6x1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4x1_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4x1_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4x1_in_0; + opnd_ivp_sem_ld_st_i_bimm4x1_in_0 = *valp & 0xf; + opnd_ivp_sem_ld_st_i_bimm4x1_out_0 = (((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm4x1_in_0 >> 1) & 0x7)) | 0xfffffff8)) == 0xffffffff))) & 0xfffffff) << 4) | opnd_ivp_sem_ld_st_i_bimm4x1_in_0; + *valp = opnd_ivp_sem_ld_st_i_bimm4x1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4x1_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm4x1_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm4x1_out_0; + opnd_ivp_sem_ld_st_i_bimm4x1_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm4x1_in_0 = (opnd_ivp_sem_ld_st_i_bimm4x1_out_0 & 0xf); + *valp = opnd_ivp_sem_ld_st_i_bimm4x1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm8x4_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm8x4_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm8x4_in_0; + opnd_ivp_sem_ld_st_i_bimm8x4_in_0 = *valp & 0xff; + opnd_ivp_sem_ld_st_i_bimm8x4_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm8x4_in_0 >> 1) & 0x7f)) | 0xffffff80)) == 0xffffffff))) & 0xffffff) << 8) | opnd_ivp_sem_ld_st_i_bimm8x4_in_0) << 2; + *valp = opnd_ivp_sem_ld_st_i_bimm8x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm8x4_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm8x4_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm8x4_out_0; + opnd_ivp_sem_ld_st_i_bimm8x4_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm8x4_in_0 = ((opnd_ivp_sem_ld_st_i_bimm8x4_out_0 >> 2) & 0xff); + *valp = opnd_ivp_sem_ld_st_i_bimm8x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_ltrx2nimm_decode (uint32 *valp) +{ + unsigned bbe_ltrx2nimm_out_0; + unsigned bbe_ltrx2nimm_in_0; + bbe_ltrx2nimm_in_0 = *valp & 0x7f; + bbe_ltrx2nimm_out_0 = CONST_TBL_bbe_ltrx2nimm_tab_0[bbe_ltrx2nimm_in_0 & 0x7f]; + *valp = bbe_ltrx2nimm_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_ltrx2nimm_encode (uint32 *valp) +{ + unsigned bbe_ltrx2nimm_in_0; + unsigned bbe_ltrx2nimm_out_0; + bbe_ltrx2nimm_out_0 = *valp; + switch (bbe_ltrx2nimm_out_0) + { + case 0: bbe_ltrx2nimm_in_0 = 0; break; + case 0x1: bbe_ltrx2nimm_in_0 = 0x1; break; + case 0x2: bbe_ltrx2nimm_in_0 = 0x2; break; + case 0x3: bbe_ltrx2nimm_in_0 = 0x3; break; + case 0x4: bbe_ltrx2nimm_in_0 = 0x4; break; + case 0x5: bbe_ltrx2nimm_in_0 = 0x5; break; + case 0x6: bbe_ltrx2nimm_in_0 = 0x6; break; + case 0x7: bbe_ltrx2nimm_in_0 = 0x7; break; + case 0x8: bbe_ltrx2nimm_in_0 = 0x8; break; + case 0x9: bbe_ltrx2nimm_in_0 = 0x9; break; + case 0xa: bbe_ltrx2nimm_in_0 = 0xa; break; + case 0xb: bbe_ltrx2nimm_in_0 = 0xb; break; + case 0xc: bbe_ltrx2nimm_in_0 = 0xc; break; + case 0xd: bbe_ltrx2nimm_in_0 = 0xd; break; + case 0xe: bbe_ltrx2nimm_in_0 = 0xe; break; + case 0xf: bbe_ltrx2nimm_in_0 = 0xf; break; + case 0x10: bbe_ltrx2nimm_in_0 = 0x10; break; + case 0x11: bbe_ltrx2nimm_in_0 = 0x11; break; + case 0x12: bbe_ltrx2nimm_in_0 = 0x12; break; + case 0x13: bbe_ltrx2nimm_in_0 = 0x13; break; + case 0x14: bbe_ltrx2nimm_in_0 = 0x14; break; + case 0x15: bbe_ltrx2nimm_in_0 = 0x15; break; + case 0x16: bbe_ltrx2nimm_in_0 = 0x16; break; + case 0x17: bbe_ltrx2nimm_in_0 = 0x17; break; + case 0x18: bbe_ltrx2nimm_in_0 = 0x18; break; + case 0x19: bbe_ltrx2nimm_in_0 = 0x19; break; + case 0x1a: bbe_ltrx2nimm_in_0 = 0x1a; break; + case 0x1b: bbe_ltrx2nimm_in_0 = 0x1b; break; + case 0x1c: bbe_ltrx2nimm_in_0 = 0x1c; break; + case 0x1d: bbe_ltrx2nimm_in_0 = 0x1d; break; + case 0x1e: bbe_ltrx2nimm_in_0 = 0x1e; break; + case 0x1f: bbe_ltrx2nimm_in_0 = 0x1f; break; + case 0x20: bbe_ltrx2nimm_in_0 = 0x20; break; + case 0x21: bbe_ltrx2nimm_in_0 = 0x21; break; + case 0x22: bbe_ltrx2nimm_in_0 = 0x22; break; + case 0x23: bbe_ltrx2nimm_in_0 = 0x23; break; + case 0x24: bbe_ltrx2nimm_in_0 = 0x24; break; + case 0x25: bbe_ltrx2nimm_in_0 = 0x25; break; + case 0x26: bbe_ltrx2nimm_in_0 = 0x26; break; + case 0x27: bbe_ltrx2nimm_in_0 = 0x27; break; + case 0x28: bbe_ltrx2nimm_in_0 = 0x28; break; + case 0x29: bbe_ltrx2nimm_in_0 = 0x29; break; + case 0x2a: bbe_ltrx2nimm_in_0 = 0x2a; break; + case 0x2b: bbe_ltrx2nimm_in_0 = 0x2b; break; + case 0x2c: bbe_ltrx2nimm_in_0 = 0x2c; break; + case 0x2d: bbe_ltrx2nimm_in_0 = 0x2d; break; + case 0x2e: bbe_ltrx2nimm_in_0 = 0x2e; break; + case 0x2f: bbe_ltrx2nimm_in_0 = 0x2f; break; + case 0x30: bbe_ltrx2nimm_in_0 = 0x30; break; + case 0x31: bbe_ltrx2nimm_in_0 = 0x31; break; + case 0x32: bbe_ltrx2nimm_in_0 = 0x32; break; + case 0x33: bbe_ltrx2nimm_in_0 = 0x33; break; + case 0x34: bbe_ltrx2nimm_in_0 = 0x34; break; + case 0x35: bbe_ltrx2nimm_in_0 = 0x35; break; + case 0x36: bbe_ltrx2nimm_in_0 = 0x36; break; + case 0x37: bbe_ltrx2nimm_in_0 = 0x37; break; + case 0x38: bbe_ltrx2nimm_in_0 = 0x38; break; + case 0x39: bbe_ltrx2nimm_in_0 = 0x39; break; + case 0x3a: bbe_ltrx2nimm_in_0 = 0x3a; break; + case 0x3b: bbe_ltrx2nimm_in_0 = 0x3b; break; + case 0x3c: bbe_ltrx2nimm_in_0 = 0x3c; break; + case 0x3d: bbe_ltrx2nimm_in_0 = 0x3d; break; + case 0x3e: bbe_ltrx2nimm_in_0 = 0x3e; break; + case 0x3f: bbe_ltrx2nimm_in_0 = 0x3f; break; + case 0x40: bbe_ltrx2nimm_in_0 = 0x40; break; + default: bbe_ltrx2nimm_in_0 = 0; break; + } + *valp = bbe_ltrx2nimm_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_ltrxn_2imm_decode (uint32 *valp) +{ + unsigned bbe_ltrxn_2imm_out_0; + unsigned bbe_ltrxn_2imm_in_0; + bbe_ltrxn_2imm_in_0 = *valp & 0x1f; + bbe_ltrxn_2imm_out_0 = CONST_TBL_bbe_ltrxn_2imm_tab_0[bbe_ltrxn_2imm_in_0 & 0x1f]; + *valp = bbe_ltrxn_2imm_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_ltrxn_2imm_encode (uint32 *valp) +{ + unsigned bbe_ltrxn_2imm_in_0; + unsigned bbe_ltrxn_2imm_out_0; + bbe_ltrxn_2imm_out_0 = *valp; + switch (bbe_ltrxn_2imm_out_0) + { + case 0: bbe_ltrxn_2imm_in_0 = 0; break; + case 0x1: bbe_ltrxn_2imm_in_0 = 0x1; break; + case 0x2: bbe_ltrxn_2imm_in_0 = 0x2; break; + case 0x3: bbe_ltrxn_2imm_in_0 = 0x3; break; + case 0x4: bbe_ltrxn_2imm_in_0 = 0x4; break; + case 0x5: bbe_ltrxn_2imm_in_0 = 0x5; break; + case 0x6: bbe_ltrxn_2imm_in_0 = 0x6; break; + case 0x7: bbe_ltrxn_2imm_in_0 = 0x7; break; + case 0x8: bbe_ltrxn_2imm_in_0 = 0x8; break; + case 0x9: bbe_ltrxn_2imm_in_0 = 0x9; break; + case 0xa: bbe_ltrxn_2imm_in_0 = 0xa; break; + case 0xb: bbe_ltrxn_2imm_in_0 = 0xb; break; + case 0xc: bbe_ltrxn_2imm_in_0 = 0xc; break; + case 0xd: bbe_ltrxn_2imm_in_0 = 0xd; break; + case 0xe: bbe_ltrxn_2imm_in_0 = 0xe; break; + case 0xf: bbe_ltrxn_2imm_in_0 = 0xf; break; + case 0x10: bbe_ltrxn_2imm_in_0 = 0x10; break; + default: bbe_ltrxn_2imm_in_0 = 0; break; + } + *valp = bbe_ltrxn_2imm_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_ltrxnimm_decode (uint32 *valp) +{ + unsigned bbe_ltrxnimm_out_0; + unsigned bbe_ltrxnimm_in_0; + bbe_ltrxnimm_in_0 = *valp & 0x3f; + bbe_ltrxnimm_out_0 = CONST_TBL_bbe_ltrxnimm_tab_0[bbe_ltrxnimm_in_0 & 0x3f]; + *valp = bbe_ltrxnimm_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_ltrxnimm_encode (uint32 *valp) +{ + unsigned bbe_ltrxnimm_in_0; + unsigned bbe_ltrxnimm_out_0; + bbe_ltrxnimm_out_0 = *valp; + switch (bbe_ltrxnimm_out_0) + { + case 0: bbe_ltrxnimm_in_0 = 0; break; + case 0x1: bbe_ltrxnimm_in_0 = 0x1; break; + case 0x2: bbe_ltrxnimm_in_0 = 0x2; break; + case 0x3: bbe_ltrxnimm_in_0 = 0x3; break; + case 0x4: bbe_ltrxnimm_in_0 = 0x4; break; + case 0x5: bbe_ltrxnimm_in_0 = 0x5; break; + case 0x6: bbe_ltrxnimm_in_0 = 0x6; break; + case 0x7: bbe_ltrxnimm_in_0 = 0x7; break; + case 0x8: bbe_ltrxnimm_in_0 = 0x8; break; + case 0x9: bbe_ltrxnimm_in_0 = 0x9; break; + case 0xa: bbe_ltrxnimm_in_0 = 0xa; break; + case 0xb: bbe_ltrxnimm_in_0 = 0xb; break; + case 0xc: bbe_ltrxnimm_in_0 = 0xc; break; + case 0xd: bbe_ltrxnimm_in_0 = 0xd; break; + case 0xe: bbe_ltrxnimm_in_0 = 0xe; break; + case 0xf: bbe_ltrxnimm_in_0 = 0xf; break; + case 0x10: bbe_ltrxnimm_in_0 = 0x10; break; + case 0x11: bbe_ltrxnimm_in_0 = 0x11; break; + case 0x12: bbe_ltrxnimm_in_0 = 0x12; break; + case 0x13: bbe_ltrxnimm_in_0 = 0x13; break; + case 0x14: bbe_ltrxnimm_in_0 = 0x14; break; + case 0x15: bbe_ltrxnimm_in_0 = 0x15; break; + case 0x16: bbe_ltrxnimm_in_0 = 0x16; break; + case 0x17: bbe_ltrxnimm_in_0 = 0x17; break; + case 0x18: bbe_ltrxnimm_in_0 = 0x18; break; + case 0x19: bbe_ltrxnimm_in_0 = 0x19; break; + case 0x1a: bbe_ltrxnimm_in_0 = 0x1a; break; + case 0x1b: bbe_ltrxnimm_in_0 = 0x1b; break; + case 0x1c: bbe_ltrxnimm_in_0 = 0x1c; break; + case 0x1d: bbe_ltrxnimm_in_0 = 0x1d; break; + case 0x1e: bbe_ltrxnimm_in_0 = 0x1e; break; + case 0x1f: bbe_ltrxnimm_in_0 = 0x1f; break; + case 0x20: bbe_ltrxnimm_in_0 = 0x20; break; + default: bbe_ltrxnimm_in_0 = 0; break; + } + *valp = bbe_ltrxnimm_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm8_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm8_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimm8_in_0; + opnd_ivp_sem_ld_st_i_bimm8_in_0 = *valp & 0xff; + opnd_ivp_sem_ld_st_i_bimm8_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimm8_in_0 >> 1) & 0x7f)) | 0xffffff80)) == 0xffffffff))) & 0xffffff) << 8) | opnd_ivp_sem_ld_st_i_bimm8_in_0) << 6; + *valp = opnd_ivp_sem_ld_st_i_bimm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm8_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimm8_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimm8_out_0; + opnd_ivp_sem_ld_st_i_bimm8_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimm8_in_0 = ((opnd_ivp_sem_ld_st_i_bimm8_out_0 >> 6) & 0xff); + *valp = opnd_ivp_sem_ld_st_i_bimm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb8_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimmb8_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimmb8_in_0; + opnd_ivp_sem_ld_st_i_bimmb8_in_0 = *valp & 0xff; + opnd_ivp_sem_ld_st_i_bimmb8_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimmb8_in_0 >> 1) & 0x7f)) | 0xffffff80)) == 0xffffffff))) & 0xffffff) << 8) | opnd_ivp_sem_ld_st_i_bimmb8_in_0) << 5; + *valp = opnd_ivp_sem_ld_st_i_bimmb8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb8_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimmb8_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimmb8_out_0; + opnd_ivp_sem_ld_st_i_bimmb8_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimmb8_in_0 = ((opnd_ivp_sem_ld_st_i_bimmb8_out_0 >> 5) & 0xff); + *valp = opnd_ivp_sem_ld_st_i_bimmb8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb4_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimmb4_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimmb4_in_0; + opnd_ivp_sem_ld_st_i_bimmb4_in_0 = *valp & 0xf; + opnd_ivp_sem_ld_st_i_bimmb4_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimmb4_in_0 >> 1) & 0x7)) | 0xfffffff8)) == 0xffffffff))) & 0xfffffff) << 4) | opnd_ivp_sem_ld_st_i_bimmb4_in_0) << 5; + *valp = opnd_ivp_sem_ld_st_i_bimmb4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb4_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimmb4_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimmb4_out_0; + opnd_ivp_sem_ld_st_i_bimmb4_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimmb4_in_0 = ((opnd_ivp_sem_ld_st_i_bimmb4_out_0 >> 5) & 0xf); + *valp = opnd_ivp_sem_ld_st_i_bimmb4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb6_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimmb6_out_0; + unsigned opnd_ivp_sem_ld_st_i_bimmb6_in_0; + opnd_ivp_sem_ld_st_i_bimmb6_in_0 = *valp & 0x3f; + opnd_ivp_sem_ld_st_i_bimmb6_out_0 = ((((-(( ( ((((opnd_ivp_sem_ld_st_i_bimmb6_in_0 >> 1) & 0x1f)) | 0xffffffe0)) == 0xffffffff))) & 0x3ffffff) << 6) | opnd_ivp_sem_ld_st_i_bimmb6_in_0) << 5; + *valp = opnd_ivp_sem_ld_st_i_bimmb6_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb6_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_ld_st_i_bimmb6_in_0; + unsigned opnd_ivp_sem_ld_st_i_bimmb6_out_0; + opnd_ivp_sem_ld_st_i_bimmb6_out_0 = *valp; + opnd_ivp_sem_ld_st_i_bimmb6_in_0 = ((opnd_ivp_sem_ld_st_i_bimmb6_out_0 >> 5) & 0x3f); + *valp = opnd_ivp_sem_ld_st_i_bimmb6_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_i_IMM_movint_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_vec_mov_i_IMM_movint_out_0; + unsigned opnd_ivp_sem_vec_mov_i_IMM_movint_in_0; + opnd_ivp_sem_vec_mov_i_IMM_movint_in_0 = *valp & 0x7f; + opnd_ivp_sem_vec_mov_i_IMM_movint_out_0 = (((-(( ( ((((opnd_ivp_sem_vec_mov_i_IMM_movint_in_0 >> 5) & 0x3)) | 0xfffffffc)) == 0xffffffff))) & 0x1ffffff) << 7) | opnd_ivp_sem_vec_mov_i_IMM_movint_in_0; + *valp = opnd_ivp_sem_vec_mov_i_IMM_movint_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_i_IMM_movint_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_vec_mov_i_IMM_movint_in_0; + unsigned opnd_ivp_sem_vec_mov_i_IMM_movint_out_0; + opnd_ivp_sem_vec_mov_i_IMM_movint_out_0 = *valp; + opnd_ivp_sem_vec_mov_i_IMM_movint_in_0 = (opnd_ivp_sem_vec_mov_i_IMM_movint_out_0 & 0x7f); + *valp = opnd_ivp_sem_vec_mov_i_IMM_movint_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_immmovvi_decode (uint32 *valp) +{ + unsigned opnd_ivp_sem_vec_mov_immmovvi_out_0; + unsigned opnd_ivp_sem_vec_mov_immmovvi_in_0; + opnd_ivp_sem_vec_mov_immmovvi_in_0 = *valp & 0x3f; + opnd_ivp_sem_vec_mov_immmovvi_out_0 = (((-(( ( (((opnd_ivp_sem_vec_mov_immmovvi_in_0 & 0x3f)) | 0xffffffc0)) == 0xffffffff))) & 0x3ffffff) << 6) | opnd_ivp_sem_vec_mov_immmovvi_in_0; + *valp = opnd_ivp_sem_vec_mov_immmovvi_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_immmovvi_encode (uint32 *valp) +{ + unsigned opnd_ivp_sem_vec_mov_immmovvi_in_0; + unsigned opnd_ivp_sem_vec_mov_immmovvi_out_0; + opnd_ivp_sem_vec_mov_immmovvi_out_0 = *valp; + opnd_ivp_sem_vec_mov_immmovvi_in_0 = (opnd_ivp_sem_vec_mov_immmovvi_out_0 & 0x3f); + *valp = opnd_ivp_sem_vec_mov_immmovvi_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm7_63_decode (uint32 *valp) +{ + unsigned saimm7_63_out_0; + unsigned saimm7_63_in_0; + saimm7_63_in_0 = *valp & 0x3f; + saimm7_63_out_0 = (0 << 6) | saimm7_63_in_0; + *valp = saimm7_63_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm7_63_encode (uint32 *valp) +{ + unsigned saimm7_63_in_0; + unsigned saimm7_63_out_0; + saimm7_63_out_0 = *valp; + saimm7_63_in_0 = (saimm7_63_out_0 & 0x3f); + *valp = saimm7_63_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm7_decode (uint32 *valp) +{ + unsigned saimm7_out_0; + unsigned saimm7_in_0; + saimm7_in_0 = *valp & 0x7f; + saimm7_out_0 = (0 << 7) | saimm7_in_0; + *valp = saimm7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_saimm7_encode (uint32 *valp) +{ + unsigned saimm7_in_0; + unsigned saimm7_out_0; + saimm7_out_0 = *valp; + saimm7_in_0 = (saimm7_out_0 & 0x7f); + *valp = saimm7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_gvr_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_gvr_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_imm1_2N_decode (uint32 *valp) +{ + unsigned imm1_2N_out_0; + unsigned imm1_2N_in_0; + imm1_2N_in_0 = *valp & 0x7; + imm1_2N_out_0 = CONST_TBL_imm1_2N_tab_0[imm1_2N_in_0 & 0x7]; + *valp = imm1_2N_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_imm1_2N_encode (uint32 *valp) +{ + unsigned imm1_2N_in_0; + unsigned imm1_2N_out_0; + imm1_2N_out_0 = *valp; + switch (imm1_2N_out_0) + { + case 0x1: imm1_2N_in_0 = 0; break; + case 0x2: imm1_2N_in_0 = 0x1; break; + case 0x4: imm1_2N_in_0 = 0x2; break; + case 0x8: imm1_2N_in_0 = 0x3; break; + case 0x10: imm1_2N_in_0 = 0x4; break; + case 0x20: imm1_2N_in_0 = 0x5; break; + case 0x40: imm1_2N_in_0 = 0x6; break; + default: imm1_2N_in_0 = 0; break; + } + *valp = imm1_2N_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_selimm_S0_decode (uint32 *valp) +{ + unsigned bbe_selimm_S0_out_0; + unsigned bbe_selimm_S0_in_0; + bbe_selimm_S0_in_0 = *valp & 0x1f; + bbe_selimm_S0_out_0 = CONST_TBL_tab_selimm_7b_0[bbe_selimm_S0_in_0 & 0x1f]; + *valp = bbe_selimm_S0_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_selimm_S0_encode (uint32 *valp) +{ + unsigned bbe_selimm_S0_in_0; + unsigned bbe_selimm_S0_out_0; + bbe_selimm_S0_out_0 = *valp; + switch (bbe_selimm_S0_out_0) + { + case 0: bbe_selimm_S0_in_0 = 0; break; + case 0x1: bbe_selimm_S0_in_0 = 0x1; break; + case 0x2: bbe_selimm_S0_in_0 = 0x2; break; + case 0x3: bbe_selimm_S0_in_0 = 0x3; break; + case 0x8: bbe_selimm_S0_in_0 = 0x4; break; + case 0x9: bbe_selimm_S0_in_0 = 0x5; break; + case 0xa: bbe_selimm_S0_in_0 = 0x6; break; + case 0xb: bbe_selimm_S0_in_0 = 0x7; break; + case 0x10: bbe_selimm_S0_in_0 = 0x8; break; + case 0x11: bbe_selimm_S0_in_0 = 0x9; break; + case 0x20: bbe_selimm_S0_in_0 = 0xa; break; + case 0x21: bbe_selimm_S0_in_0 = 0xb; break; + case 0x22: bbe_selimm_S0_in_0 = 0xc; break; + case 0x23: bbe_selimm_S0_in_0 = 0xd; break; + case 0x3b: bbe_selimm_S0_in_0 = 0xe; break; + case 0x3c: bbe_selimm_S0_in_0 = 0xf; break; + case 0x3d: bbe_selimm_S0_in_0 = 0x10; break; + case 0x3e: bbe_selimm_S0_in_0 = 0x11; break; + case 0x3f: bbe_selimm_S0_in_0 = 0x12; break; + case 0x40: bbe_selimm_S0_in_0 = 0x13; break; + case 0x41: bbe_selimm_S0_in_0 = 0x14; break; + case 0x42: bbe_selimm_S0_in_0 = 0x15; break; + case 0x43: bbe_selimm_S0_in_0 = 0x16; break; + case 0x44: bbe_selimm_S0_in_0 = 0x17; break; + case 0x45: bbe_selimm_S0_in_0 = 0x18; break; + case 0x46: bbe_selimm_S0_in_0 = 0x19; break; + case 0x47: bbe_selimm_S0_in_0 = 0x1a; break; + default: bbe_selimm_S0_in_0 = 0x1b; break; + } + *valp = bbe_selimm_S0_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_shflimm_S0_decode (uint32 *valp) +{ + unsigned bbe_shflimm_S0_out_0; + unsigned bbe_shflimm_S0_in_0; + bbe_shflimm_S0_in_0 = *valp & 0x1; + bbe_shflimm_S0_out_0 = CONST_TBL_tab_shflimm_7b_0[bbe_shflimm_S0_in_0 & 0x1]; + *valp = bbe_shflimm_S0_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbe_shflimm_S0_encode (uint32 *valp) +{ + unsigned bbe_shflimm_S0_in_0; + unsigned bbe_shflimm_S0_out_0; + bbe_shflimm_S0_out_0 = *valp; + bbe_shflimm_S0_in_0 = (((bbe_shflimm_S0_out_0 == (CONST_TBL_tab_shflimm_7b_0[0]))) ? 0 : 0x1) & 0x1; + *valp = bbe_shflimm_S0_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_MTK_AndPOPC_c_decode (uint32 *valp) +{ + unsigned opnd_MTK_AndPOPC_c_out_0; + unsigned opnd_MTK_AndPOPC_c_in_0; + opnd_MTK_AndPOPC_c_in_0 = *valp & 0x1; + opnd_MTK_AndPOPC_c_out_0 = (0 << 1) | opnd_MTK_AndPOPC_c_in_0; + *valp = opnd_MTK_AndPOPC_c_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_MTK_AndPOPC_c_encode (uint32 *valp) +{ + unsigned opnd_MTK_AndPOPC_c_in_0; + unsigned opnd_MTK_AndPOPC_c_out_0; + opnd_MTK_AndPOPC_c_out_0 = *valp; + opnd_MTK_AndPOPC_c_in_0 = (((opnd_MTK_AndPOPC_c_out_0 >> 0) & 1)) & 0x1; + *valp = opnd_MTK_AndPOPC_c_in_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, + { "uimm12x8", FIELD_imm12, -1, 0, + 0, + OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, + 0, 0 }, + { "simm4", FIELD_mn, -1, 0, + 0, + OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, + 0, 0 }, + { "arr", FIELD_r, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "ars", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "*ars_invisible", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "art", FIELD_t, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "ar0", FIELD__ar0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, + 0, 0 }, + { "ar4", FIELD__ar4, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode, + 0, 0 }, + { "ar8", FIELD__ar8, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode, + 0, 0 }, + { "ar12", FIELD__ar12, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode, + 0, 0 }, + { "ars_entry", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, + 0, 0 }, + { "immrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, + 0, 0 }, + { "lsi4x4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, + 0, 0 }, + { "simm7", FIELD_imm7, -1, 0, + 0, + OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, + 0, 0 }, + { "uimm6", FIELD_imm6, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa }, + { "ai4const", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, + 0, 0 }, + { "b4const", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, + 0, 0 }, + { "b4constu", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, + 0, 0 }, + { "uimm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, + 0, 0 }, + { "uimm8x2", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, + 0, 0 }, + { "uimm8x4", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, + 0, 0 }, + { "uimm4x16", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, + 0, 0 }, + { "uimmrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode, + 0, 0 }, + { "simm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, + 0, 0 }, + { "simm8x256", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, + 0, 0 }, + { "simm12b", FIELD_imm12b, -1, 0, + 0, + OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, + 0, 0 }, + { "msalp32", FIELD_sal, -1, 0, + 0, + OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, + 0, 0 }, + { "op2p1", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, + 0, 0 }, + { "label8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, + Operand_label8_ator, Operand_label8_rtoa }, + { "ulabel8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa }, + { "label12", FIELD_imm12, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, + Operand_label12_ator, Operand_label12_rtoa }, + { "soffset", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa }, + { "uimm16x4", FIELD_imm16, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, + { "bbi", FIELD_bbi, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "imm16", FIELD_imm16, -1, 0, + 0, + OperandSem_opnd_sem_imm16_encode, OperandSem_opnd_sem_imm16_decode, + 0, 0 }, + { "sae", FIELD_sae, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sas", FIELD_sas, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sargt", FIELD_sargt, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "s", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, + 0, 0 }, + { "immt", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0 }, + { "imms", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0 }, + { "bt", FIELD_t, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "bs", FIELD_s, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "br", FIELD_r, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "bt2", FIELD_t2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0 }, + { "bs2", FIELD_s2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0 }, + { "br2", FIELD_r2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0 }, + { "bt4", FIELD_t4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0 }, + { "bs4", FIELD_s4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0 }, + { "br4", FIELD_r4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0 }, + { "bt8", FIELD_t8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0 }, + { "bs8", FIELD_s8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0 }, + { "br8", FIELD_r8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0 }, + { "bt16", FIELD__bt16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "bs16", FIELD__bs16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "br16", FIELD__br16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "brall", FIELD__brall, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "tp7", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, + 0, 0 }, + { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, + { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode, + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, + { "opnd_ivp_sem_vec_alu_vr", FIELD_fld_ivp_sem_vec_alu_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_alu_vt", FIELD_fld_ivp_sem_vec_alu_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_alu_vs", FIELD_fld_ivp_sem_vec_alu_vs, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_alu_vbr", FIELD_fld_ivp_sem_vec_alu_vbr, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_multiply_vr", FIELD_fld_ivp_sem_multiply_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_multiply_vs", FIELD_fld_ivp_sem_multiply_vs, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_multiply_wvt", FIELD_fld_ivp_sem_multiply_wvt, REGFILE_wvec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_wvec_encode, OperandSem_opnd_sem_wvec_decode, + 0, 0 }, + { "opnd_ivp_sem_vbool_alu_ltr_vbr", FIELD_fld_ivp_sem_vbool_alu_ltr_vbr, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vbool_alu_ltr_vbs", FIELD_fld_ivp_sem_vbool_alu_ltr_vbs, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vbool_alu_ltr_vbt", FIELD_fld_ivp_sem_vbool_alu_ltr_vbt, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_alu_vbt", FIELD_fld_ivp_sem_vec_alu_vbt, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_histogram_arr", FIELD_fld_ivp_sem_vec_histogram_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_histogram_vr", FIELD_fld_ivp_sem_vec_histogram_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_histogram_vs", FIELD_fld_ivp_sem_vec_histogram_vs, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_histogram_vt", FIELD_fld_ivp_sem_vec_histogram_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_histogram_vbr", FIELD_fld_ivp_sem_vec_histogram_vbr, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_histogram_vbs", FIELD_fld_ivp_sem_vec_histogram_vbs, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_divide_lane_ctrl", FIELD_fld_ivp_sem_divide_lane_ctrl, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_divide_lane_ctrl_encode, OperandSem_opnd_sem_opnd_ivp_sem_divide_lane_ctrl_decode, + 0, 0 }, + { "opnd_ivp_sem_divide_vr", FIELD_fld_ivp_sem_divide_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_divide_vt", FIELD_fld_ivp_sem_divide_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_divide_vu", FIELD_fld_ivp_sem_divide_vu, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_divide_vs", FIELD_fld_ivp_sem_divide_vs, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_slct", FIELD_fld_ivp_sem_vec_select_slct, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_i_imm4_encode, OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_i_imm4_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_vr", FIELD_fld_ivp_sem_vec_select_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_vs", FIELD_fld_ivp_sem_vec_select_vs, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_vt", FIELD_fld_ivp_sem_vec_select_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_vu", FIELD_fld_ivp_sem_vec_select_vu, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_slct_h", FIELD_fld_ivp_sem_vec_select_slct_h, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_vec_select_slct_h_encode, OperandSem_opnd_sem_opnd_ivp_sem_vec_select_slct_h_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_sr", FIELD_fld_ivp_sem_vec_select_sr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_vbr", FIELD_fld_ivp_sem_vec_select_vbr, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_alu_i_imm3", FIELD_fld_ivp_sem_vec_alu_i_imm3, -1, 0, + 0, + OperandSem_opnd_sem_saimm4_encode, OperandSem_opnd_sem_saimm4_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_rep_i32", FIELD_fld_ivp_sem_vec_rep_i32, -1, 0, + 0, + OperandSem_opnd_sem_saimm5_encode, OperandSem_opnd_sem_saimm5_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_rep_vr", FIELD_fld_ivp_sem_vec_rep_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_rep_i", FIELD_fld_ivp_sem_vec_rep_i, -1, 0, + 0, + OperandSem_opnd_sem_saimm6_31_encode, OperandSem_opnd_sem_saimm6_31_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_uul", FIELD_fld_ivp_sem_ld_st_uul, REGFILE_valign, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_valign_encode, OperandSem_opnd_sem_valign_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_vrul", FIELD_fld_ivp_sem_ld_st_vrul, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_vrul2", FIELD_fld_ivp_sem_ld_st_vrul2, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm6", FIELD_fld_ivp_sem_ld_st_i_bimm6, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm4", FIELD_fld_ivp_sem_ld_st_i_bimm4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_vbr", FIELD_fld_ivp_sem_ld_st_vbr, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm6b2n", FIELD_fld_ivp_sem_ld_st_i_bimm6b2n, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6b2n_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6b2n_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm4b2n", FIELD_fld_ivp_sem_ld_st_i_bimm4b2n, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4b2n_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4b2n_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm6bn_2", FIELD_fld_ivp_sem_ld_st_i_bimm6bn_2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_2_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_2_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm4bn_2", FIELD_fld_ivp_sem_ld_st_i_bimm4bn_2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_2_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_2_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm6bn", FIELD_fld_ivp_sem_ld_st_i_bimm6bn, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm4bn", FIELD_fld_ivp_sem_ld_st_i_bimm4bn, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm6x1", FIELD_fld_ivp_sem_ld_st_i_bimm6x1, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6x1_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6x1_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_vr", FIELD_fld_ivp_sem_ld_st_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm4x1", FIELD_fld_ivp_sem_ld_st_i_bimm4x1, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4x1_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4x1_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm8x4", FIELD_fld_ivp_sem_ld_st_i_bimm8x4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm8x4_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm8x4_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm4x4", FIELD_fld_ivp_sem_ld_st_i_bimm4x4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm6x2", FIELD_fld_ivp_sem_ld_st_i_bimm6x2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_2_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_2_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm4x2", FIELD_fld_ivp_sem_ld_st_i_bimm4x2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_2_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm4bn_2_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_vrr", FIELD_fld_ivp_sem_ld_st_vrr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm6x4", FIELD_fld_ivp_sem_ld_st_i_bimm6x4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm6bn_decode, + 0, 0 }, + { "bbe_ltrx2nimm", FIELD_fld_bbe_ltrx2nimm, -1, 0, + 0, + OperandSem_opnd_sem_bbe_ltrx2nimm_encode, OperandSem_opnd_sem_bbe_ltrx2nimm_decode, + 0, 0 }, + { "bbe_ltrxn_2imm", FIELD_fld_bbe_ltrxn_2imm, -1, 0, + 0, + OperandSem_opnd_sem_bbe_ltrxn_2imm_encode, OperandSem_opnd_sem_bbe_ltrxn_2imm_decode, + 0, 0 }, + { "bbe_ltrxnimm", FIELD_fld_bbe_ltrxnimm, -1, 0, + 0, + OperandSem_opnd_sem_bbe_ltrxnimm_encode, OperandSem_opnd_sem_bbe_ltrxnimm_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimm8", FIELD_fld_ivp_sem_ld_st_i_bimm8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm8_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimm8_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_vbre", FIELD_fld_ivp_sem_ld_st_vbre, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimmh8", FIELD_fld_ivp_sem_ld_st_i_bimmh8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb8_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb8_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimmh4", FIELD_fld_ivp_sem_ld_st_i_bimmh4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb4_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb4_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimmh6", FIELD_fld_ivp_sem_ld_st_i_bimmh6, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb6_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb6_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimmb8", FIELD_fld_ivp_sem_ld_st_i_bimmb8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb8_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb8_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimmb4", FIELD_fld_ivp_sem_ld_st_i_bimmb4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb4_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb4_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_i_bimmb6", FIELD_fld_ivp_sem_ld_st_i_bimmb6, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb6_encode, OperandSem_opnd_sem_opnd_ivp_sem_ld_st_i_bimmb6_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_valignr", FIELD_fld_ivp_sem_ld_st_valignr, REGFILE_valign, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_valign_encode, OperandSem_opnd_sem_valign_decode, + 0, 0 }, + { "opnd_ivp_sem_unpack_wvec_mov_vr", FIELD_fld_ivp_sem_unpack_wvec_mov_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_unpack_wvec_mov_vs", FIELD_fld_ivp_sem_unpack_wvec_mov_vs, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_unpack_wvec_mov_wvt", FIELD_fld_ivp_sem_unpack_wvec_mov_wvt, REGFILE_wvec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_wvec_encode, OperandSem_opnd_sem_wvec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_mov_vt", FIELD_fld_ivp_sem_vec_mov_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_mov_wvr", FIELD_fld_ivp_sem_vec_mov_wvr, REGFILE_wvec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_wvec_encode, OperandSem_opnd_sem_wvec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_mov_arr", FIELD_fld_ivp_sem_vec_mov_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_mov_i_IMM_movint", FIELD_fld_ivp_sem_vec_mov_i_IMM_movint, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_i_IMM_movint_encode, OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_i_IMM_movint_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_mov_immmovvi", FIELD_fld_ivp_sem_vec_mov_immmovvi, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_immmovvi_encode, OperandSem_opnd_sem_opnd_ivp_sem_vec_mov_immmovvi_decode, + 0, 0 }, + { "opnd_ivp_sem_unpack_wvec_mov_wvr", FIELD_fld_ivp_sem_unpack_wvec_mov_wvr, REGFILE_wvec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_wvec_encode, OperandSem_opnd_sem_wvec_decode, + 0, 0 }, + { "opnd_ivp_sem_multiply_arr", FIELD_fld_ivp_sem_multiply_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_ivp_sem_multiply_vp", FIELD_fld_ivp_sem_multiply_vp, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_multiply_vt", FIELD_fld_ivp_sem_multiply_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_multiply_vbr", FIELD_fld_ivp_sem_multiply_vbr, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_shift_vr", FIELD_fld_ivp_sem_vec_shift_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_shift_vt", FIELD_fld_ivp_sem_vec_shift_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_wvec_pack_vt", FIELD_fld_ivp_sem_wvec_pack_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_wvec_pack_wvr", FIELD_fld_ivp_sem_wvec_pack_wvr, REGFILE_wvec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_wvec_encode, OperandSem_opnd_sem_wvec_decode, + 0, 0 }, + { "opnd_ivp_sem_wvec_pack_arr", FIELD_fld_ivp_sem_wvec_pack_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_reduce_vr", FIELD_fld_ivp_sem_vec_reduce_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_reduce_vt", FIELD_fld_ivp_sem_vec_reduce_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_reduce_vbr", FIELD_fld_ivp_sem_vec_reduce_vbr, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_reduce_vbt", FIELD_fld_ivp_sem_vec_reduce_vbt, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_rep_i8", FIELD_fld_ivp_sem_vec_rep_i8, -1, 0, + 0, + OperandSem_opnd_sem_saimm7_63_encode, OperandSem_opnd_sem_saimm7_63_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_rep_vt", FIELD_fld_ivp_sem_vec_rep_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "saimm4", FIELD_fld_saimm4, -1, 0, + 0, + OperandSem_opnd_sem_saimm4_encode, OperandSem_opnd_sem_saimm4_decode, + 0, 0 }, + { "saimm6_31", FIELD_fld_saimm6_31, -1, 0, + 0, + OperandSem_opnd_sem_saimm6_31_encode, OperandSem_opnd_sem_saimm6_31_decode, + 0, 0 }, + { "saimm5", FIELD_fld_saimm5, -1, 0, + 0, + OperandSem_opnd_sem_saimm5_encode, OperandSem_opnd_sem_saimm5_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_shift_vs", FIELD_fld_ivp_sem_vec_shift_vs, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_ld_st_uus", FIELD_fld_ivp_sem_ld_st_uus, REGFILE_valign, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_valign_encode, OperandSem_opnd_sem_valign_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_isel", FIELD_fld_ivp_sem_vec_select_isel, -1, 0, + 0, + OperandSem_opnd_sem_saimm7_encode, OperandSem_opnd_sem_saimm7_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_select_ishfl", FIELD_fld_ivp_sem_vec_select_ishfl, -1, 0, + 0, + OperandSem_opnd_sem_saimm7_encode, OperandSem_opnd_sem_saimm7_decode, + 0, 0 }, + { "opnd_ivp_sem_sqz_vbr", FIELD_fld_ivp_sem_sqz_vbr, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_sqz_vt", FIELD_fld_ivp_sem_sqz_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_unpack_wvec_mov_vt", FIELD_fld_ivp_sem_unpack_wvec_mov_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_scatter_gather_ars", FIELD_fld_ivp_sem_vec_scatter_gather_ars, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_scatter_gather_gt", FIELD_fld_ivp_sem_vec_scatter_gather_gt, REGFILE_gvr, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_gvr_encode, OperandSem_opnd_sem_gvr_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_scatter_gather_vs", FIELD_fld_ivp_sem_vec_scatter_gather_vs, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_scatter_gather_vbr", FIELD_fld_ivp_sem_vec_scatter_gather_vbr, REGFILE_vbool, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vbool_encode, OperandSem_opnd_sem_vbool_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_scatter_gather_gs", FIELD_fld_ivp_sem_vec_scatter_gather_gs, REGFILE_gvr, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_gvr_encode, OperandSem_opnd_sem_gvr_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_scatter_gather_vt", FIELD_fld_ivp_sem_vec_scatter_gather_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_scatter_gather_vr", FIELD_fld_ivp_sem_vec_scatter_gather_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vbool_alu_ltr_art", FIELD_fld_ivp_sem_vbool_alu_ltr_art, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "imm1_2N", FIELD_fld_imm1_2N, -1, 0, + 0, + OperandSem_opnd_sem_imm1_2N_encode, OperandSem_opnd_sem_imm1_2N_decode, + 0, 0 }, + { "opnd_ivp_sem_multiply_vq", FIELD_fld_ivp_sem_multiply_vq, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_rep_arr", FIELD_fld_ivp_sem_vec_rep_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "bbe_selimm_S0", FIELD_fld_bbe_selimm_S0, -1, 0, + 0, + OperandSem_opnd_sem_bbe_selimm_S0_encode, OperandSem_opnd_sem_bbe_selimm_S0_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_specialized_seli_vr", FIELD_fld_ivp_sem_vec_specialized_seli_vr, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_specialized_seli_vs", FIELD_fld_ivp_sem_vec_specialized_seli_vs, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_ivp_sem_vec_specialized_seli_vt", FIELD_fld_ivp_sem_vec_specialized_seli_vt, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "bbe_selimm_S2", FIELD_fld_bbe_selimm_S2, -1, 0, + 0, + OperandSem_opnd_sem_bbe_selimm_S0_encode, OperandSem_opnd_sem_bbe_selimm_S0_decode, + 0, 0 }, + { "bbe_selimm_S4", FIELD_fld_bbe_selimm_S4, -1, 0, + 0, + OperandSem_opnd_sem_bbe_selimm_S0_encode, OperandSem_opnd_sem_bbe_selimm_S0_decode, + 0, 0 }, + { "bbe_shflimm_S0", FIELD_fld_bbe_shflimm_S0, -1, 0, + 0, + OperandSem_opnd_sem_bbe_shflimm_S0_encode, OperandSem_opnd_sem_bbe_shflimm_S0_decode, + 0, 0 }, + { "bbe_shflimm_S2", FIELD_fld_bbe_shflimm_S2, -1, 0, + 0, + OperandSem_opnd_sem_bbe_shflimm_S0_encode, OperandSem_opnd_sem_bbe_shflimm_S0_decode, + 0, 0 }, + { "bbe_shflimm_S4", FIELD_fld_bbe_shflimm_S4, -1, 0, + 0, + OperandSem_opnd_sem_bbe_shflimm_S0_encode, OperandSem_opnd_sem_bbe_shflimm_S0_decode, + 0, 0 }, + { "opnd_MTK_AndPOPC_c", FIELD_fld_MTK_AndPOPC_c, -1, 0, + 0, + OperandSem_opnd_sem_opnd_MTK_AndPOPC_c_encode, OperandSem_opnd_sem_opnd_MTK_AndPOPC_c_decode, + 0, 0 }, + { "opnd_MTK_AndPOPC_inB", FIELD_fld_MTK_AndPOPC_inB, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_MTK_AndPOPC_inA", FIELD_fld_MTK_AndPOPC_inA, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_MTK_AndPOPC_oData", FIELD_fld_MTK_AndPOPC_oData, REGFILE_vec, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_vec_encode, OperandSem_opnd_sem_vec_decode, + 0, 0 }, + { "opnd_iq_tie2apb_inq0_pop_qdata", FIELD_fld_iq_tie2apb_inq0_pop_qdata, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_iq_tie2apb_inq0_is_ready_is_ready", FIELD_fld_iq_tie2apb_inq0_is_ready_is_ready, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "opnd_iq_tie2apb_inq0_nonblocking_peek_success", FIELD_fld_iq_tie2apb_inq0_nonblocking_peek_success, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "opnd_iq_tie2apb_inq0_nonblocking_peek_qdata", FIELD_fld_iq_tie2apb_inq0_nonblocking_peek_qdata, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_iq_tie2apb_inq0_nonblocking_pop_success", FIELD_fld_iq_tie2apb_inq0_nonblocking_pop_success, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "opnd_iq_tie2apb_inq0_nonblocking_pop_qdata", FIELD_fld_iq_tie2apb_inq0_nonblocking_pop_qdata, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_iq_tie2apb_inq0_blocking_peek_qdata", FIELD_fld_iq_tie2apb_inq0_blocking_peek_qdata, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_push_read_qaddr", FIELD_fld_oq_tie2apb_outq0_push_read_qaddr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_push_read_qdata", FIELD_fld_oq_tie2apb_outq0_push_read_qdata, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_push_write_qaddr", FIELD_fld_oq_tie2apb_outq0_push_write_qaddr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_push_write_qdata", FIELD_fld_oq_tie2apb_outq0_push_write_qdata, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_is_ready_is_ready", FIELD_fld_oq_tie2apb_outq0_is_ready_is_ready, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_nonblocking_push_read_success", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_read_success, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_nonblocking_push_read_qaddr", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_read_qaddr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_nonblocking_push_read_qdata", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_read_qdata, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_nonblocking_push_write_success", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_write_success, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_nonblocking_push_write_qaddr", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_write_qaddr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "opnd_oq_tie2apb_outq0_nonblocking_push_write_qdata", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_write_qdata, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, + { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, + { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, + { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, + { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, + { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, + { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, + { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, + { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, + { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, + { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, + { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, + { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, + { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, + { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_11_4", FIELD_fld_F0_S0_LdSt_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_11_8", FIELD_fld_F0_S0_LdSt_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_11_9", FIELD_fld_F0_S0_LdSt_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_12_0", FIELD_fld_F0_S0_LdSt_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_12_11", FIELD_fld_F0_S0_LdSt_12_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_12_12", FIELD_fld_F0_S0_LdSt_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_12_2", FIELD_fld_F0_S0_LdSt_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_12_4", FIELD_fld_F0_S0_LdSt_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_12_8", FIELD_fld_F0_S0_LdSt_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_13_9", FIELD_fld_F0_S0_LdSt_13_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_15_15", FIELD_fld_F0_S0_LdSt_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_11", FIELD_fld_F0_S0_LdSt_33_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_12", FIELD_fld_F0_S0_LdSt_33_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_13", FIELD_fld_F0_S0_LdSt_33_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_14", FIELD_fld_F0_S0_LdSt_33_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_15", FIELD_fld_F0_S0_LdSt_33_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_16", FIELD_fld_F0_S0_LdSt_33_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_17", FIELD_fld_F0_S0_LdSt_33_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_18", FIELD_fld_F0_S0_LdSt_33_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_19", FIELD_fld_F0_S0_LdSt_33_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_20", FIELD_fld_F0_S0_LdSt_33_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_27", FIELD_fld_F0_S0_LdSt_33_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_33_9", FIELD_fld_F0_S0_LdSt_33_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_3_0", FIELD_fld_F0_S0_LdSt_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_7_4", FIELD_fld_F0_S0_LdSt_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_7_5", FIELD_fld_F0_S0_LdSt_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_7_6", FIELD_fld_F0_S0_LdSt_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_7_7", FIELD_fld_F0_S0_LdSt_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_8_0", FIELD_fld_F0_S0_LdSt_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_8_4", FIELD_fld_F0_S0_LdSt_8_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S0_LdSt_8_8", FIELD_fld_F0_S0_LdSt_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_bbe_shflimm_S0", FIELD_fld_bbe_shflimm_S0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm4", FIELD_fld_ivp_sem_ld_st_i_bimm4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm4b2n", FIELD_fld_ivp_sem_ld_st_i_bimm4b2n, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm4bn", FIELD_fld_ivp_sem_ld_st_i_bimm4bn, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm4bn_2", FIELD_fld_ivp_sem_ld_st_i_bimm4bn_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm4x1", FIELD_fld_ivp_sem_ld_st_i_bimm4x1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm4x2", FIELD_fld_ivp_sem_ld_st_i_bimm4x2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm4x4", FIELD_fld_ivp_sem_ld_st_i_bimm4x4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm6", FIELD_fld_ivp_sem_ld_st_i_bimm6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm6b2n", FIELD_fld_ivp_sem_ld_st_i_bimm6b2n, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm6bn", FIELD_fld_ivp_sem_ld_st_i_bimm6bn, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm6bn_2", FIELD_fld_ivp_sem_ld_st_i_bimm6bn_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm6x1", FIELD_fld_ivp_sem_ld_st_i_bimm6x1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm6x2", FIELD_fld_ivp_sem_ld_st_i_bimm6x2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm6x4", FIELD_fld_ivp_sem_ld_st_i_bimm6x4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm8", FIELD_fld_ivp_sem_ld_st_i_bimm8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimm8x4", FIELD_fld_ivp_sem_ld_st_i_bimm8x4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimmb4", FIELD_fld_ivp_sem_ld_st_i_bimmb4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimmb6", FIELD_fld_ivp_sem_ld_st_i_bimmb6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimmb8", FIELD_fld_ivp_sem_ld_st_i_bimmb8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimmh4", FIELD_fld_ivp_sem_ld_st_i_bimmh4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimmh6", FIELD_fld_ivp_sem_ld_st_i_bimmh6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_i_bimmh8", FIELD_fld_ivp_sem_ld_st_i_bimmh8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_uul", FIELD_fld_ivp_sem_ld_st_uul, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_uus", FIELD_fld_ivp_sem_ld_st_uus, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_valignr", FIELD_fld_ivp_sem_ld_st_valignr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_vbr", FIELD_fld_ivp_sem_ld_st_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_vbre", FIELD_fld_ivp_sem_ld_st_vbre, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_vr", FIELD_fld_ivp_sem_ld_st_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_vrr", FIELD_fld_ivp_sem_ld_st_vrr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_vrul", FIELD_fld_ivp_sem_ld_st_vrul, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_alu_arr", FIELD_fld_ivp_sem_vec_alu_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_alu_vbr", FIELD_fld_ivp_sem_vec_alu_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_alu_vr", FIELD_fld_ivp_sem_vec_alu_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_alu_vt", FIELD_fld_ivp_sem_vec_alu_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_rep_i", FIELD_fld_ivp_sem_vec_rep_i, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_rep_i32", FIELD_fld_ivp_sem_vec_rep_i32, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_rep_i8", FIELD_fld_ivp_sem_vec_rep_i8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_rep_vr", FIELD_fld_ivp_sem_vec_rep_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_rep_vt", FIELD_fld_ivp_sem_vec_rep_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_scatter_gather_ars", FIELD_fld_ivp_sem_vec_scatter_gather_ars, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_scatter_gather_gt", FIELD_fld_ivp_sem_vec_scatter_gather_gt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_scatter_gather_vbr", FIELD_fld_ivp_sem_vec_scatter_gather_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_scatter_gather_vs", FIELD_fld_ivp_sem_vec_scatter_gather_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_shift_vr", FIELD_fld_ivp_sem_vec_shift_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_shift_vt", FIELD_fld_ivp_sem_vec_shift_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_specialized_seli_vr", FIELD_fld_ivp_sem_vec_specialized_seli_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_specialized_seli_vt", FIELD_fld_ivp_sem_vec_specialized_seli_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_saimm4", FIELD_fld_saimm4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_saimm5", FIELD_fld_saimm5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_12_11", FIELD_fld_F0_S1_Ld_12_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_12_12", FIELD_fld_F0_S1_Ld_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_12_4", FIELD_fld_F0_S1_Ld_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_15_10", FIELD_fld_F0_S1_Ld_15_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_15_13", FIELD_fld_F0_S1_Ld_15_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_15_14", FIELD_fld_F0_S1_Ld_15_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_15_15", FIELD_fld_F0_S1_Ld_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_15_2", FIELD_fld_F0_S1_Ld_15_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_15_4", FIELD_fld_F0_S1_Ld_15_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_15_8", FIELD_fld_F0_S1_Ld_15_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_24_0", FIELD_fld_F0_S1_Ld_24_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_24_11", FIELD_fld_F0_S1_Ld_24_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_24_12", FIELD_fld_F0_S1_Ld_24_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_24_13", FIELD_fld_F0_S1_Ld_24_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_24_14", FIELD_fld_F0_S1_Ld_24_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_24_16", FIELD_fld_F0_S1_Ld_24_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_24_17", FIELD_fld_F0_S1_Ld_24_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_24_18", FIELD_fld_F0_S1_Ld_24_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_24_8", FIELD_fld_F0_S1_Ld_24_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_3_0", FIELD_fld_F0_S1_Ld_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_3_2", FIELD_fld_F0_S1_Ld_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_7_0", FIELD_fld_F0_S1_Ld_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_7_2", FIELD_fld_F0_S1_Ld_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_7_3", FIELD_fld_F0_S1_Ld_7_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_7_4", FIELD_fld_F0_S1_Ld_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_7_5", FIELD_fld_F0_S1_Ld_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_7_6", FIELD_fld_F0_S1_Ld_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S1_Ld_7_7", FIELD_fld_F0_S1_Ld_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_bbe_ltrx2nimm", FIELD_fld_bbe_ltrx2nimm, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_bbe_ltrxn_2imm", FIELD_fld_bbe_ltrxn_2imm, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_bbe_ltrxnimm", FIELD_fld_bbe_ltrxnimm, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_imm1_2N", FIELD_fld_imm1_2N, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_sqz_vbr", FIELD_fld_ivp_sem_sqz_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_sqz_vt", FIELD_fld_ivp_sem_sqz_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vbool_alu_ltr_art", FIELD_fld_ivp_sem_vbool_alu_ltr_art, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vbool_alu_ltr_vbr", FIELD_fld_ivp_sem_vbool_alu_ltr_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vbool_alu_ltr_vbs", FIELD_fld_ivp_sem_vbool_alu_ltr_vbs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vbool_alu_ltr_vbt", FIELD_fld_ivp_sem_vbool_alu_ltr_vbt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_mov_arr", FIELD_fld_ivp_sem_vec_mov_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_mov_i_IMM_movint", FIELD_fld_ivp_sem_vec_mov_i_IMM_movint, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_mov_i_imm4", FIELD_fld_ivp_sem_vec_mov_i_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_mov_immmovvi", FIELD_fld_ivp_sem_vec_mov_immmovvi, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_mov_vbr", FIELD_fld_ivp_sem_vec_mov_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_mov_vt", FIELD_fld_ivp_sem_vec_mov_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_mov_wvr", FIELD_fld_ivp_sem_vec_mov_wvr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_scatter_gather_gs", FIELD_fld_ivp_sem_vec_scatter_gather_gs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_scatter_gather_vt", FIELD_fld_ivp_sem_vec_scatter_gather_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_wvec_pack_arr", FIELD_fld_ivp_sem_wvec_pack_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_wvec_pack_vt", FIELD_fld_ivp_sem_wvec_pack_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_wvec_pack_wvr", FIELD_fld_ivp_sem_wvec_pack_wvr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_11_8", FIELD_fld_F0_S2_Mul_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_13_12", FIELD_fld_F0_S2_Mul_13_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_18_12", FIELD_fld_F0_S2_Mul_18_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_18_14", FIELD_fld_F0_S2_Mul_18_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_18_9", FIELD_fld_F0_S2_Mul_18_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_1_0", FIELD_fld_F0_S2_Mul_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_26_12", FIELD_fld_F0_S2_Mul_26_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_26_13", FIELD_fld_F0_S2_Mul_26_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_26_14", FIELD_fld_F0_S2_Mul_26_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_26_2", FIELD_fld_F0_S2_Mul_26_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_26_20", FIELD_fld_F0_S2_Mul_26_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_26_21", FIELD_fld_F0_S2_Mul_26_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_3_0", FIELD_fld_F0_S2_Mul_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_3_3", FIELD_fld_F0_S2_Mul_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_4_4", FIELD_fld_F0_S2_Mul_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_7_4", FIELD_fld_F0_S2_Mul_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S2_Mul_7_5", FIELD_fld_F0_S2_Mul_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_multiply_arr", FIELD_fld_ivp_sem_multiply_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_multiply_vp", FIELD_fld_ivp_sem_multiply_vp, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_multiply_vr", FIELD_fld_ivp_sem_multiply_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_multiply_vs", FIELD_fld_ivp_sem_multiply_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_multiply_wvt", FIELD_fld_ivp_sem_multiply_wvt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_unpack_wvec_mov_vr", FIELD_fld_ivp_sem_unpack_wvec_mov_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_unpack_wvec_mov_vs", FIELD_fld_ivp_sem_unpack_wvec_mov_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_unpack_wvec_mov_wvr", FIELD_fld_ivp_sem_unpack_wvec_mov_wvr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_unpack_wvec_mov_wvt", FIELD_fld_ivp_sem_unpack_wvec_mov_wvt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_alu_vbt", FIELD_fld_ivp_sem_vec_alu_vbt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_alu_vs", FIELD_fld_ivp_sem_vec_alu_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_0_0", FIELD_fld_F0_S3_ALU_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_14_10", FIELD_fld_F0_S3_ALU_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_14_11", FIELD_fld_F0_S3_ALU_14_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_14_13", FIELD_fld_F0_S3_ALU_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_14_14", FIELD_fld_F0_S3_ALU_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_14_8", FIELD_fld_F0_S3_ALU_14_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_24_10", FIELD_fld_F0_S3_ALU_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_24_13", FIELD_fld_F0_S3_ALU_24_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_24_19", FIELD_fld_F0_S3_ALU_24_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_24_20", FIELD_fld_F0_S3_ALU_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_10", FIELD_fld_F0_S3_ALU_33_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_13", FIELD_fld_F0_S3_ALU_33_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_18", FIELD_fld_F0_S3_ALU_33_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_19", FIELD_fld_F0_S3_ALU_33_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_20", FIELD_fld_F0_S3_ALU_33_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_25", FIELD_fld_F0_S3_ALU_33_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_26", FIELD_fld_F0_S3_ALU_33_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_27", FIELD_fld_F0_S3_ALU_33_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_28", FIELD_fld_F0_S3_ALU_33_28, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_33_9", FIELD_fld_F0_S3_ALU_33_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_3_0", FIELD_fld_F0_S3_ALU_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_3_1", FIELD_fld_F0_S3_ALU_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_3_2", FIELD_fld_F0_S3_ALU_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_3_3", FIELD_fld_F0_S3_ALU_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_7_3", FIELD_fld_F0_S3_ALU_7_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_7_4", FIELD_fld_F0_S3_ALU_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_7_7", FIELD_fld_F0_S3_ALU_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_8_0", FIELD_fld_F0_S3_ALU_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_8_8", FIELD_fld_F0_S3_ALU_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_9_0", FIELD_fld_F0_S3_ALU_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_9_7", FIELD_fld_F0_S3_ALU_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F0_S3_ALU_9_8", FIELD_fld_F0_S3_ALU_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_fp_sem_hp_cnv_i_imm4", FIELD_fld_fp_sem_hp_cnv_i_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_fp_sem_hp_cnv_vbr", FIELD_fld_fp_sem_hp_cnv_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_fp_sem_hp_cnv_vr", FIELD_fld_fp_sem_hp_cnv_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_fp_sem_hp_cnv_vs", FIELD_fld_fp_sem_hp_cnv_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_fp_sem_hp_cnv_vt", FIELD_fld_fp_sem_hp_cnv_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_sp32cvt_i_imm5", FIELD_fld_ivp_sem_sp32cvt_i_imm5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_sp32cvt_vbr", FIELD_fld_ivp_sem_sp32cvt_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_sp32cvt_vr", FIELD_fld_ivp_sem_sp32cvt_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_sp32cvt_vt", FIELD_fld_ivp_sem_sp32cvt_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_spmisc_vbr", FIELD_fld_ivp_sem_spmisc_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_spmisc_vr", FIELD_fld_ivp_sem_spmisc_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_spmisc_vs", FIELD_fld_ivp_sem_spmisc_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_spmisc_vsM", FIELD_fld_ivp_sem_spmisc_vsM, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_spmisc_vt", FIELD_fld_ivp_sem_spmisc_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_alu_i_imm3", FIELD_fld_ivp_sem_vec_alu_i_imm3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_reduce_vbr", FIELD_fld_ivp_sem_vec_reduce_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_reduce_vbt", FIELD_fld_ivp_sem_vec_reduce_vbt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_reduce_vr", FIELD_fld_ivp_sem_vec_reduce_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_reduce_vt", FIELD_fld_ivp_sem_vec_reduce_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_rep_arr", FIELD_fld_ivp_sem_vec_rep_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_isel", FIELD_fld_ivp_sem_vec_select_isel, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_ishfl", FIELD_fld_ivp_sem_vec_select_ishfl, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_slct", FIELD_fld_ivp_sem_vec_select_slct, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_slct_h", FIELD_fld_ivp_sem_vec_select_slct_h, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_sr", FIELD_fld_ivp_sem_vec_select_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_vbr", FIELD_fld_ivp_sem_vec_select_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_vr", FIELD_fld_ivp_sem_vec_select_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_vs", FIELD_fld_ivp_sem_vec_select_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_vt", FIELD_fld_ivp_sem_vec_select_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_select_vu", FIELD_fld_ivp_sem_vec_select_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_shift_vs", FIELD_fld_ivp_sem_vec_shift_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_saimm6_31", FIELD_fld_saimm6_31, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_12_0", FIELD_fld_F1_S0_LdStALU_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_12_12", FIELD_fld_F1_S0_LdStALU_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_12_2", FIELD_fld_F1_S0_LdStALU_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_12_4", FIELD_fld_F1_S0_LdStALU_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_12_8", FIELD_fld_F1_S0_LdStALU_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_14_10", FIELD_fld_F1_S0_LdStALU_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_14_12", FIELD_fld_F1_S0_LdStALU_14_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_14_14", FIELD_fld_F1_S0_LdStALU_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_15_15", FIELD_fld_F1_S0_LdStALU_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_12", FIELD_fld_F1_S0_LdStALU_30_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_13", FIELD_fld_F1_S0_LdStALU_30_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_14", FIELD_fld_F1_S0_LdStALU_30_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_15", FIELD_fld_F1_S0_LdStALU_30_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_16", FIELD_fld_F1_S0_LdStALU_30_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_17", FIELD_fld_F1_S0_LdStALU_30_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_18", FIELD_fld_F1_S0_LdStALU_30_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_19", FIELD_fld_F1_S0_LdStALU_30_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_20", FIELD_fld_F1_S0_LdStALU_30_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_6", FIELD_fld_F1_S0_LdStALU_30_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_8", FIELD_fld_F1_S0_LdStALU_30_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_30_9", FIELD_fld_F1_S0_LdStALU_30_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_3_0", FIELD_fld_F1_S0_LdStALU_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_5_0", FIELD_fld_F1_S0_LdStALU_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_5_4", FIELD_fld_F1_S0_LdStALU_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_7_4", FIELD_fld_F1_S0_LdStALU_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_7_5", FIELD_fld_F1_S0_LdStALU_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_7_7", FIELD_fld_F1_S0_LdStALU_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S0_LdStALU_9_9", FIELD_fld_F1_S0_LdStALU_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_bbe_selimm_S0", FIELD_fld_bbe_selimm_S0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_scatter_gather_vr", FIELD_fld_ivp_sem_vec_scatter_gather_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_specialized_seli_vs", FIELD_fld_ivp_sem_vec_specialized_seli_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_12_10", FIELD_fld_F1_S1_Ld_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_12_11", FIELD_fld_F1_S1_Ld_12_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_12_12", FIELD_fld_F1_S1_Ld_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_12_4", FIELD_fld_F1_S1_Ld_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_12_9", FIELD_fld_F1_S1_Ld_12_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_15_10", FIELD_fld_F1_S1_Ld_15_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_15_13", FIELD_fld_F1_S1_Ld_15_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_15_14", FIELD_fld_F1_S1_Ld_15_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_15_15", FIELD_fld_F1_S1_Ld_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_15_2", FIELD_fld_F1_S1_Ld_15_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_15_4", FIELD_fld_F1_S1_Ld_15_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_15_8", FIELD_fld_F1_S1_Ld_15_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_1_0", FIELD_fld_F1_S1_Ld_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_26_11", FIELD_fld_F1_S1_Ld_26_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_26_12", FIELD_fld_F1_S1_Ld_26_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_26_13", FIELD_fld_F1_S1_Ld_26_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_26_16", FIELD_fld_F1_S1_Ld_26_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_26_18", FIELD_fld_F1_S1_Ld_26_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_26_2", FIELD_fld_F1_S1_Ld_26_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_3_0", FIELD_fld_F1_S1_Ld_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_3_2", FIELD_fld_F1_S1_Ld_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_7_0", FIELD_fld_F1_S1_Ld_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_7_2", FIELD_fld_F1_S1_Ld_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_7_3", FIELD_fld_F1_S1_Ld_7_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_7_4", FIELD_fld_F1_S1_Ld_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_7_5", FIELD_fld_F1_S1_Ld_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_7_6", FIELD_fld_F1_S1_Ld_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S1_Ld_7_7", FIELD_fld_F1_S1_Ld_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_13_10", FIELD_fld_F1_S2_Mul_13_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_13_2", FIELD_fld_F1_S2_Mul_13_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_13_5", FIELD_fld_F1_S2_Mul_13_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_14_10", FIELD_fld_F1_S2_Mul_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_28_12", FIELD_fld_F1_S2_Mul_28_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_28_15", FIELD_fld_F1_S2_Mul_28_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_28_16", FIELD_fld_F1_S2_Mul_28_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_28_18", FIELD_fld_F1_S2_Mul_28_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_28_20", FIELD_fld_F1_S2_Mul_28_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_28_4", FIELD_fld_F1_S2_Mul_28_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_28_5", FIELD_fld_F1_S2_Mul_28_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_3_0", FIELD_fld_F1_S2_Mul_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_3_2", FIELD_fld_F1_S2_Mul_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_3_3", FIELD_fld_F1_S2_Mul_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_4_4", FIELD_fld_F1_S2_Mul_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_9_5", FIELD_fld_F1_S2_Mul_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S2_Mul_9_6", FIELD_fld_F1_S2_Mul_9_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_bbe_selimm_S2", FIELD_fld_bbe_selimm_S2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_bbe_shflimm_S2", FIELD_fld_bbe_shflimm_S2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_fp_sem_hp_fma_vbr", FIELD_fld_fp_sem_hp_fma_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_fp_sem_hp_fma_vr", FIELD_fld_fp_sem_hp_fma_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_fp_sem_hp_fma_vs", FIELD_fld_fp_sem_hp_fma_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_fp_sem_hp_fma_vt", FIELD_fld_fp_sem_hp_fma_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_multiply_vt", FIELD_fld_ivp_sem_multiply_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_spfma_vbr", FIELD_fld_ivp_sem_spfma_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_spfma_vr", FIELD_fld_ivp_sem_spfma_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_spfma_vs", FIELD_fld_ivp_sem_spfma_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_spfma_vt", FIELD_fld_ivp_sem_spfma_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_unpack_wvec_mov_vt", FIELD_fld_ivp_sem_unpack_wvec_mov_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_0_0", FIELD_fld_F1_S3_ALU_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_14_10", FIELD_fld_F1_S3_ALU_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_14_13", FIELD_fld_F1_S3_ALU_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_14_14", FIELD_fld_F1_S3_ALU_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_14_8", FIELD_fld_F1_S3_ALU_14_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_19_14", FIELD_fld_F1_S3_ALU_19_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_19_15", FIELD_fld_F1_S3_ALU_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_19_19", FIELD_fld_F1_S3_ALU_19_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_19_4", FIELD_fld_F1_S3_ALU_19_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_19_7", FIELD_fld_F1_S3_ALU_19_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_30_15", FIELD_fld_F1_S3_ALU_30_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_30_17", FIELD_fld_F1_S3_ALU_30_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_30_19", FIELD_fld_F1_S3_ALU_30_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_30_20", FIELD_fld_F1_S3_ALU_30_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_30_22", FIELD_fld_F1_S3_ALU_30_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_30_23", FIELD_fld_F1_S3_ALU_30_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_30_6", FIELD_fld_F1_S3_ALU_30_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_30_8", FIELD_fld_F1_S3_ALU_30_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_3_0", FIELD_fld_F1_S3_ALU_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_3_1", FIELD_fld_F1_S3_ALU_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_3_2", FIELD_fld_F1_S3_ALU_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_3_3", FIELD_fld_F1_S3_ALU_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_5_0", FIELD_fld_F1_S3_ALU_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_9_0", FIELD_fld_F1_S3_ALU_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_9_1", FIELD_fld_F1_S3_ALU_9_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_9_2", FIELD_fld_F1_S3_ALU_9_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_9_3", FIELD_fld_F1_S3_ALU_9_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_9_7", FIELD_fld_F1_S3_ALU_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_9_8", FIELD_fld_F1_S3_ALU_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F1_S3_ALU_9_9", FIELD_fld_F1_S3_ALU_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_histogram_arr", FIELD_fld_ivp_sem_vec_histogram_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_histogram_vr", FIELD_fld_ivp_sem_vec_histogram_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_histogram_vs", FIELD_fld_ivp_sem_vec_histogram_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_histogram_vt", FIELD_fld_ivp_sem_vec_histogram_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_12_0", FIELD_fld_F2_S0_LdSt_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_12_10", FIELD_fld_F2_S0_LdSt_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_12_2", FIELD_fld_F2_S0_LdSt_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_12_4", FIELD_fld_F2_S0_LdSt_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_12_8", FIELD_fld_F2_S0_LdSt_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_15_15", FIELD_fld_F2_S0_LdSt_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_11", FIELD_fld_F2_S0_LdSt_28_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_12", FIELD_fld_F2_S0_LdSt_28_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_13", FIELD_fld_F2_S0_LdSt_28_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_14", FIELD_fld_F2_S0_LdSt_28_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_15", FIELD_fld_F2_S0_LdSt_28_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_16", FIELD_fld_F2_S0_LdSt_28_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_17", FIELD_fld_F2_S0_LdSt_28_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_18", FIELD_fld_F2_S0_LdSt_28_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_20", FIELD_fld_F2_S0_LdSt_28_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_4", FIELD_fld_F2_S0_LdSt_28_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_28_8", FIELD_fld_F2_S0_LdSt_28_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_3_0", FIELD_fld_F2_S0_LdSt_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_3_2", FIELD_fld_F2_S0_LdSt_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_7_2", FIELD_fld_F2_S0_LdSt_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S0_LdSt_7_4", FIELD_fld_F2_S0_LdSt_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_12_10", FIELD_fld_F2_S1_Ld_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_12_11", FIELD_fld_F2_S1_Ld_12_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_12_4", FIELD_fld_F2_S1_Ld_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_12_9", FIELD_fld_F2_S1_Ld_12_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_15_10", FIELD_fld_F2_S1_Ld_15_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_15_13", FIELD_fld_F2_S1_Ld_15_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_15_14", FIELD_fld_F2_S1_Ld_15_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_15_15", FIELD_fld_F2_S1_Ld_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_15_2", FIELD_fld_F2_S1_Ld_15_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_15_4", FIELD_fld_F2_S1_Ld_15_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_15_8", FIELD_fld_F2_S1_Ld_15_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_1_0", FIELD_fld_F2_S1_Ld_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_26_11", FIELD_fld_F2_S1_Ld_26_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_26_12", FIELD_fld_F2_S1_Ld_26_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_26_13", FIELD_fld_F2_S1_Ld_26_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_26_16", FIELD_fld_F2_S1_Ld_26_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_26_18", FIELD_fld_F2_S1_Ld_26_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_26_2", FIELD_fld_F2_S1_Ld_26_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_3_0", FIELD_fld_F2_S1_Ld_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_3_2", FIELD_fld_F2_S1_Ld_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_7_0", FIELD_fld_F2_S1_Ld_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_7_2", FIELD_fld_F2_S1_Ld_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_7_3", FIELD_fld_F2_S1_Ld_7_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_7_4", FIELD_fld_F2_S1_Ld_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_7_6", FIELD_fld_F2_S1_Ld_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S1_Ld_7_7", FIELD_fld_F2_S1_Ld_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_14_10", FIELD_fld_F2_S2_Mul_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_14_11", FIELD_fld_F2_S2_Mul_14_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_14_5", FIELD_fld_F2_S2_Mul_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_19_10", FIELD_fld_F2_S2_Mul_19_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_19_15", FIELD_fld_F2_S2_Mul_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_19_7", FIELD_fld_F2_S2_Mul_19_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_30_10", FIELD_fld_F2_S2_Mul_30_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_30_12", FIELD_fld_F2_S2_Mul_30_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_30_15", FIELD_fld_F2_S2_Mul_30_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_30_18", FIELD_fld_F2_S2_Mul_30_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_30_19", FIELD_fld_F2_S2_Mul_30_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_30_20", FIELD_fld_F2_S2_Mul_30_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_30_21", FIELD_fld_F2_S2_Mul_30_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_30_6", FIELD_fld_F2_S2_Mul_30_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_3_0", FIELD_fld_F2_S2_Mul_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_4_0", FIELD_fld_F2_S2_Mul_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_4_3", FIELD_fld_F2_S2_Mul_4_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S2_Mul_5_0", FIELD_fld_F2_S2_Mul_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_divide_lane_ctrl", FIELD_fld_ivp_sem_divide_lane_ctrl, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_divide_vr", FIELD_fld_ivp_sem_divide_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_divide_vs", FIELD_fld_ivp_sem_divide_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_divide_vt", FIELD_fld_ivp_sem_divide_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_divide_vu", FIELD_fld_ivp_sem_divide_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_multiply_vbr", FIELD_fld_ivp_sem_multiply_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_0_0", FIELD_fld_F2_S3_ALU_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_14_10", FIELD_fld_F2_S3_ALU_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_14_13", FIELD_fld_F2_S3_ALU_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_14_14", FIELD_fld_F2_S3_ALU_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_14_8", FIELD_fld_F2_S3_ALU_14_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_19_14", FIELD_fld_F2_S3_ALU_19_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_19_15", FIELD_fld_F2_S3_ALU_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_19_19", FIELD_fld_F2_S3_ALU_19_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_19_4", FIELD_fld_F2_S3_ALU_19_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_19_7", FIELD_fld_F2_S3_ALU_19_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_30_15", FIELD_fld_F2_S3_ALU_30_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_30_18", FIELD_fld_F2_S3_ALU_30_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_30_19", FIELD_fld_F2_S3_ALU_30_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_30_20", FIELD_fld_F2_S3_ALU_30_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_30_22", FIELD_fld_F2_S3_ALU_30_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_30_23", FIELD_fld_F2_S3_ALU_30_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_30_6", FIELD_fld_F2_S3_ALU_30_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_30_8", FIELD_fld_F2_S3_ALU_30_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_3_0", FIELD_fld_F2_S3_ALU_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_3_1", FIELD_fld_F2_S3_ALU_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_3_2", FIELD_fld_F2_S3_ALU_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_3_3", FIELD_fld_F2_S3_ALU_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_5_0", FIELD_fld_F2_S3_ALU_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_9_0", FIELD_fld_F2_S3_ALU_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_9_1", FIELD_fld_F2_S3_ALU_9_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_9_2", FIELD_fld_F2_S3_ALU_9_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_9_3", FIELD_fld_F2_S3_ALU_9_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_9_7", FIELD_fld_F2_S3_ALU_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_9_8", FIELD_fld_F2_S3_ALU_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F2_S3_ALU_9_9", FIELD_fld_F2_S3_ALU_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_0_0", FIELD_fld_F3_S0_LdSt_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_12_0", FIELD_fld_F3_S0_LdSt_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_12_11", FIELD_fld_F3_S0_LdSt_12_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_12_12", FIELD_fld_F3_S0_LdSt_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_12_4", FIELD_fld_F3_S0_LdSt_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_12_8", FIELD_fld_F3_S0_LdSt_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_13_9", FIELD_fld_F3_S0_LdSt_13_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_15_15", FIELD_fld_F3_S0_LdSt_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_1", FIELD_fld_F3_S0_LdSt_25_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_11", FIELD_fld_F3_S0_LdSt_25_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_12", FIELD_fld_F3_S0_LdSt_25_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_13", FIELD_fld_F3_S0_LdSt_25_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_14", FIELD_fld_F3_S0_LdSt_25_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_15", FIELD_fld_F3_S0_LdSt_25_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_16", FIELD_fld_F3_S0_LdSt_25_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_17", FIELD_fld_F3_S0_LdSt_25_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_18", FIELD_fld_F3_S0_LdSt_25_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_19", FIELD_fld_F3_S0_LdSt_25_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_20", FIELD_fld_F3_S0_LdSt_25_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_4", FIELD_fld_F3_S0_LdSt_25_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_8", FIELD_fld_F3_S0_LdSt_25_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_25_9", FIELD_fld_F3_S0_LdSt_25_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_3_0", FIELD_fld_F3_S0_LdSt_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_7_4", FIELD_fld_F3_S0_LdSt_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_7_5", FIELD_fld_F3_S0_LdSt_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_7_7", FIELD_fld_F3_S0_LdSt_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S0_LdSt_8_0", FIELD_fld_F3_S0_LdSt_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_12_11", FIELD_fld_F3_S1_Ld_12_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_12_2", FIELD_fld_F3_S1_Ld_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_12_4", FIELD_fld_F3_S1_Ld_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_12_8", FIELD_fld_F3_S1_Ld_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_0", FIELD_fld_F3_S1_Ld_21_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_10", FIELD_fld_F3_S1_Ld_21_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_11", FIELD_fld_F3_S1_Ld_21_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_12", FIELD_fld_F3_S1_Ld_21_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_13", FIELD_fld_F3_S1_Ld_21_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_15", FIELD_fld_F3_S1_Ld_21_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_16", FIELD_fld_F3_S1_Ld_21_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_17", FIELD_fld_F3_S1_Ld_21_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_8", FIELD_fld_F3_S1_Ld_21_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_21_9", FIELD_fld_F3_S1_Ld_21_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_3_0", FIELD_fld_F3_S1_Ld_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_3_2", FIELD_fld_F3_S1_Ld_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_4_0", FIELD_fld_F3_S1_Ld_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_4_3", FIELD_fld_F3_S1_Ld_4_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_4_4", FIELD_fld_F3_S1_Ld_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_7_0", FIELD_fld_F3_S1_Ld_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_7_2", FIELD_fld_F3_S1_Ld_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_7_4", FIELD_fld_F3_S1_Ld_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S1_Ld_7_7", FIELD_fld_F3_S1_Ld_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_11_8", FIELD_fld_F3_S2_Mul_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_13_12", FIELD_fld_F3_S2_Mul_13_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_13_7", FIELD_fld_F3_S2_Mul_13_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_21_0", FIELD_fld_F3_S2_Mul_21_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_21_12", FIELD_fld_F3_S2_Mul_21_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_21_13", FIELD_fld_F3_S2_Mul_21_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_21_14", FIELD_fld_F3_S2_Mul_21_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_21_15", FIELD_fld_F3_S2_Mul_21_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_21_16", FIELD_fld_F3_S2_Mul_21_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_3_0", FIELD_fld_F3_S2_Mul_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_3_3", FIELD_fld_F3_S2_Mul_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_4_0", FIELD_fld_F3_S2_Mul_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_7_4", FIELD_fld_F3_S2_Mul_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S2_Mul_7_5", FIELD_fld_F3_S2_Mul_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_13_9", FIELD_fld_F3_S3_ALU_13_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_18_12", FIELD_fld_F3_S3_ALU_18_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_18_13", FIELD_fld_F3_S3_ALU_18_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_18_14", FIELD_fld_F3_S3_ALU_18_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_18_18", FIELD_fld_F3_S3_ALU_18_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_18_3", FIELD_fld_F3_S3_ALU_18_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_18_7", FIELD_fld_F3_S3_ALU_18_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_18_8", FIELD_fld_F3_S3_ALU_18_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_12", FIELD_fld_F3_S3_ALU_28_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_13", FIELD_fld_F3_S3_ALU_28_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_14", FIELD_fld_F3_S3_ALU_28_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_18", FIELD_fld_F3_S3_ALU_28_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_19", FIELD_fld_F3_S3_ALU_28_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_20", FIELD_fld_F3_S3_ALU_28_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_21", FIELD_fld_F3_S3_ALU_28_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_22", FIELD_fld_F3_S3_ALU_28_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_25", FIELD_fld_F3_S3_ALU_28_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_4", FIELD_fld_F3_S3_ALU_28_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_8", FIELD_fld_F3_S3_ALU_28_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_28_9", FIELD_fld_F3_S3_ALU_28_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_3_0", FIELD_fld_F3_S3_ALU_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_3_2", FIELD_fld_F3_S3_ALU_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_3_3", FIELD_fld_F3_S3_ALU_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_7_3", FIELD_fld_F3_S3_ALU_7_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_7_6", FIELD_fld_F3_S3_ALU_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_7_7", FIELD_fld_F3_S3_ALU_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S3_ALU_8_0", FIELD_fld_F3_S3_ALU_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_histogram_vbr", FIELD_fld_ivp_sem_vec_histogram_vbr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_vec_histogram_vbs", FIELD_fld_ivp_sem_vec_histogram_vbs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S4_ALU_14_10", FIELD_fld_F3_S4_ALU_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S4_ALU_23_0", FIELD_fld_F3_S4_ALU_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S4_ALU_23_15", FIELD_fld_F3_S4_ALU_23_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S4_ALU_23_18", FIELD_fld_F3_S4_ALU_23_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S4_ALU_23_20", FIELD_fld_F3_S4_ALU_23_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S4_ALU_9_5", FIELD_fld_F3_S4_ALU_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S4_ALU_9_6", FIELD_fld_F3_S4_ALU_9_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_bbe_selimm_S4", FIELD_fld_bbe_selimm_S4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_bbe_shflimm_S4", FIELD_fld_bbe_shflimm_S4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_11_4", FIELD_fld_F4_S0_Ld_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_11_8", FIELD_fld_F4_S0_Ld_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_11_9", FIELD_fld_F4_S0_Ld_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_12_0", FIELD_fld_F4_S0_Ld_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_12_2", FIELD_fld_F4_S0_Ld_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_12_4", FIELD_fld_F4_S0_Ld_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_12_8", FIELD_fld_F4_S0_Ld_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_15_15", FIELD_fld_F4_S0_Ld_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_12", FIELD_fld_F4_S0_Ld_31_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_13", FIELD_fld_F4_S0_Ld_31_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_15", FIELD_fld_F4_S0_Ld_31_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_16", FIELD_fld_F4_S0_Ld_31_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_17", FIELD_fld_F4_S0_Ld_31_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_18", FIELD_fld_F4_S0_Ld_31_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_20", FIELD_fld_F4_S0_Ld_31_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_27", FIELD_fld_F4_S0_Ld_31_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_7", FIELD_fld_F4_S0_Ld_31_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_8", FIELD_fld_F4_S0_Ld_31_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_31_9", FIELD_fld_F4_S0_Ld_31_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_3_0", FIELD_fld_F4_S0_Ld_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_6_0", FIELD_fld_F4_S0_Ld_6_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_6_4", FIELD_fld_F4_S0_Ld_6_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S0_Ld_7_4", FIELD_fld_F4_S0_Ld_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_12_10", FIELD_fld_F4_S1_Ld_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_12_2", FIELD_fld_F4_S1_Ld_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_12_4", FIELD_fld_F4_S1_Ld_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_12_8", FIELD_fld_F4_S1_Ld_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_0", FIELD_fld_F4_S1_Ld_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_10", FIELD_fld_F4_S1_Ld_23_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_11", FIELD_fld_F4_S1_Ld_23_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_12", FIELD_fld_F4_S1_Ld_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_13", FIELD_fld_F4_S1_Ld_23_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_15", FIELD_fld_F4_S1_Ld_23_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_16", FIELD_fld_F4_S1_Ld_23_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_17", FIELD_fld_F4_S1_Ld_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_8", FIELD_fld_F4_S1_Ld_23_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_23_9", FIELD_fld_F4_S1_Ld_23_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_3_0", FIELD_fld_F4_S1_Ld_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_3_2", FIELD_fld_F4_S1_Ld_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_4_0", FIELD_fld_F4_S1_Ld_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_4_3", FIELD_fld_F4_S1_Ld_4_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_4_4", FIELD_fld_F4_S1_Ld_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_7_0", FIELD_fld_F4_S1_Ld_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_7_2", FIELD_fld_F4_S1_Ld_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_7_4", FIELD_fld_F4_S1_Ld_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_7_6", FIELD_fld_F4_S1_Ld_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S1_Ld_7_7", FIELD_fld_F4_S1_Ld_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S2_Mul_32_26", FIELD_fld_F4_S2_Mul_32_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S2_Mul_32_8", FIELD_fld_F4_S2_Mul_32_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S2_Mul_3_0", FIELD_fld_F4_S2_Mul_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S2_Mul_7_0", FIELD_fld_F4_S2_Mul_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_multiply_vq", FIELD_fld_ivp_sem_multiply_vq, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_0_0", FIELD_fld_F4_S3_ALU_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_14_10", FIELD_fld_F4_S3_ALU_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_14_11", FIELD_fld_F4_S3_ALU_14_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_14_12", FIELD_fld_F4_S3_ALU_14_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_14_13", FIELD_fld_F4_S3_ALU_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_14_14", FIELD_fld_F4_S3_ALU_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_14_6", FIELD_fld_F4_S3_ALU_14_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_14_8", FIELD_fld_F4_S3_ALU_14_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_19_13", FIELD_fld_F4_S3_ALU_19_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_19_6", FIELD_fld_F4_S3_ALU_19_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_19_8", FIELD_fld_F4_S3_ALU_19_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_24_12", FIELD_fld_F4_S3_ALU_24_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_24_13", FIELD_fld_F4_S3_ALU_24_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_24_18", FIELD_fld_F4_S3_ALU_24_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_24_20", FIELD_fld_F4_S3_ALU_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_24_21", FIELD_fld_F4_S3_ALU_24_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_31_13", FIELD_fld_F4_S3_ALU_31_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_31_19", FIELD_fld_F4_S3_ALU_31_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_31_20", FIELD_fld_F4_S3_ALU_31_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_31_23", FIELD_fld_F4_S3_ALU_31_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_31_25", FIELD_fld_F4_S3_ALU_31_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_31_26", FIELD_fld_F4_S3_ALU_31_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_31_28", FIELD_fld_F4_S3_ALU_31_28, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_31_7", FIELD_fld_F4_S3_ALU_31_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_31_8", FIELD_fld_F4_S3_ALU_31_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_3_0", FIELD_fld_F4_S3_ALU_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_3_1", FIELD_fld_F4_S3_ALU_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_3_2", FIELD_fld_F4_S3_ALU_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_3_3", FIELD_fld_F4_S3_ALU_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_6_0", FIELD_fld_F4_S3_ALU_6_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_7_4", FIELD_fld_F4_S3_ALU_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_7_5", FIELD_fld_F4_S3_ALU_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F4_S3_ALU_9_8", FIELD_fld_F4_S3_ALU_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_11_0", FIELD_fld_F5_S0_Base_11_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_11_8", FIELD_fld_F5_S0_Base_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_11_9", FIELD_fld_F5_S0_Base_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_36_12", FIELD_fld_F5_S0_Base_36_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_36_13", FIELD_fld_F5_S0_Base_36_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_36_16", FIELD_fld_F5_S0_Base_36_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_36_17", FIELD_fld_F5_S0_Base_36_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_36_18", FIELD_fld_F5_S0_Base_36_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_36_20", FIELD_fld_F5_S0_Base_36_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_36_27", FIELD_fld_F5_S0_Base_36_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_3_0", FIELD_fld_F5_S0_Base_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_3_1", FIELD_fld_F5_S0_Base_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S0_Base_7_4", FIELD_fld_F5_S0_Base_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S1_Base_27_12", FIELD_fld_F5_S1_Base_27_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S1_Base_27_13", FIELD_fld_F5_S1_Base_27_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S1_Base_27_16", FIELD_fld_F5_S1_Base_27_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S1_Base_27_17", FIELD_fld_F5_S1_Base_27_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S1_Base_27_3", FIELD_fld_F5_S1_Base_27_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S1_Base_2_0", FIELD_fld_F5_S1_Base_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S1_Base_3_0", FIELD_fld_F5_S1_Base_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S1_Base_7_4", FIELD_fld_F5_S1_Base_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S2_Base_1_0", FIELD_fld_F5_S2_Base_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S2_Base_26_12", FIELD_fld_F5_S2_Base_26_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S2_Base_26_13", FIELD_fld_F5_S2_Base_26_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S2_Base_26_16", FIELD_fld_F5_S2_Base_26_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S2_Base_26_2", FIELD_fld_F5_S2_Base_26_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S2_Base_26_8", FIELD_fld_F5_S2_Base_26_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S2_Base_3_0", FIELD_fld_F5_S2_Base_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S2_Base_7_4", FIELD_fld_F5_S2_Base_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S3_Base_0_0", FIELD_fld_F5_S3_Base_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S3_Base_25_1", FIELD_fld_F5_S3_Base_25_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S3_Base_25_16", FIELD_fld_F5_S3_Base_25_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F5_S3_Base_25_8", FIELD_fld_F5_S3_Base_25_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_1_0", FIELD_fld_F11_S0_Ld_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_23_0", FIELD_fld_F11_S0_Ld_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_23_12", FIELD_fld_F11_S0_Ld_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_23_13", FIELD_fld_F11_S0_Ld_23_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_23_16", FIELD_fld_F11_S0_Ld_23_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_23_17", FIELD_fld_F11_S0_Ld_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_23_20", FIELD_fld_F11_S0_Ld_23_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_23_4", FIELD_fld_F11_S0_Ld_23_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_3_0", FIELD_fld_F11_S0_Ld_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S0_Ld_7_4", FIELD_fld_F11_S0_Ld_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_12_10", FIELD_fld_F11_S1_ALU_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_12_11", FIELD_fld_F11_S1_ALU_12_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_12_12", FIELD_fld_F11_S1_ALU_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_12_3", FIELD_fld_F11_S1_ALU_12_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_12_4", FIELD_fld_F11_S1_ALU_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_12_9", FIELD_fld_F11_S1_ALU_12_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_15_13", FIELD_fld_F11_S1_ALU_15_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_15_14", FIELD_fld_F11_S1_ALU_15_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_15_15", FIELD_fld_F11_S1_ALU_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_15_2", FIELD_fld_F11_S1_ALU_15_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_22_0", FIELD_fld_F11_S1_ALU_22_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_22_12", FIELD_fld_F11_S1_ALU_22_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_22_13", FIELD_fld_F11_S1_ALU_22_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_22_14", FIELD_fld_F11_S1_ALU_22_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_22_16", FIELD_fld_F11_S1_ALU_22_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_22_18", FIELD_fld_F11_S1_ALU_22_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_3_0", FIELD_fld_F11_S1_ALU_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S1_ALU_7_4", FIELD_fld_F11_S1_ALU_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ivp_sem_ld_st_vrul2", FIELD_fld_ivp_sem_ld_st_vrul2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_11_8", FIELD_fld_F11_S2_Mul_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_13_12", FIELD_fld_F11_S2_Mul_13_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_13_7", FIELD_fld_F11_S2_Mul_13_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_22_0", FIELD_fld_F11_S2_Mul_22_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_22_12", FIELD_fld_F11_S2_Mul_22_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_22_13", FIELD_fld_F11_S2_Mul_22_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_22_14", FIELD_fld_F11_S2_Mul_22_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_22_15", FIELD_fld_F11_S2_Mul_22_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_22_16", FIELD_fld_F11_S2_Mul_22_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_22_8", FIELD_fld_F11_S2_Mul_22_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_3_0", FIELD_fld_F11_S2_Mul_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_3_3", FIELD_fld_F11_S2_Mul_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_4_0", FIELD_fld_F11_S2_Mul_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_7_4", FIELD_fld_F11_S2_Mul_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S2_Mul_7_5", FIELD_fld_F11_S2_Mul_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_0_0", FIELD_fld_F11_S3_ALU_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_14_10", FIELD_fld_F11_S3_ALU_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_14_11", FIELD_fld_F11_S3_ALU_14_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_14_13", FIELD_fld_F11_S3_ALU_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_14_8", FIELD_fld_F11_S3_ALU_14_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_1", FIELD_fld_F11_S3_ALU_25_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_11", FIELD_fld_F11_S3_ALU_25_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_13", FIELD_fld_F11_S3_ALU_25_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_14", FIELD_fld_F11_S3_ALU_25_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_15", FIELD_fld_F11_S3_ALU_25_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_16", FIELD_fld_F11_S3_ALU_25_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_17", FIELD_fld_F11_S3_ALU_25_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_18", FIELD_fld_F11_S3_ALU_25_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_22", FIELD_fld_F11_S3_ALU_25_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_25_8", FIELD_fld_F11_S3_ALU_25_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_3_0", FIELD_fld_F11_S3_ALU_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_3_1", FIELD_fld_F11_S3_ALU_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_7_0", FIELD_fld_F11_S3_ALU_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_7_4", FIELD_fld_F11_S3_ALU_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_9_8", FIELD_fld_F11_S3_ALU_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S3_ALU_9_9", FIELD_fld_F11_S3_ALU_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S4_ALU_24_0", FIELD_fld_F11_S4_ALU_24_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S4_ALU_24_15", FIELD_fld_F11_S4_ALU_24_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S4_ALU_24_18", FIELD_fld_F11_S4_ALU_24_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S4_ALU_9_5", FIELD_fld_F11_S4_ALU_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_12_0", FIELD_fld_N1_S0_LdSt_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_12_12", FIELD_fld_N1_S0_LdSt_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_12_2", FIELD_fld_N1_S0_LdSt_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_12_4", FIELD_fld_N1_S0_LdSt_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_12_8", FIELD_fld_N1_S0_LdSt_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_15_15", FIELD_fld_N1_S0_LdSt_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_1_0", FIELD_fld_N1_S0_LdSt_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_12", FIELD_fld_N1_S0_LdSt_26_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_13", FIELD_fld_N1_S0_LdSt_26_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_15", FIELD_fld_N1_S0_LdSt_26_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_16", FIELD_fld_N1_S0_LdSt_26_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_17", FIELD_fld_N1_S0_LdSt_26_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_18", FIELD_fld_N1_S0_LdSt_26_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_2", FIELD_fld_N1_S0_LdSt_26_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_20", FIELD_fld_N1_S0_LdSt_26_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_4", FIELD_fld_N1_S0_LdSt_26_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_8", FIELD_fld_N1_S0_LdSt_26_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_26_9", FIELD_fld_N1_S0_LdSt_26_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_3_0", FIELD_fld_N1_S0_LdSt_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_3_2", FIELD_fld_N1_S0_LdSt_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_7_2", FIELD_fld_N1_S0_LdSt_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_7_4", FIELD_fld_N1_S0_LdSt_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_7_5", FIELD_fld_N1_S0_LdSt_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S0_LdSt_7_6", FIELD_fld_N1_S0_LdSt_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S1_None_3_0", FIELD_fld_N1_S1_None_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_0_0", FIELD_fld_N1_S2_Mul_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_13_9", FIELD_fld_N1_S2_Mul_13_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_18_14", FIELD_fld_N1_S2_Mul_18_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_18_6", FIELD_fld_N1_S2_Mul_18_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_18_9", FIELD_fld_N1_S2_Mul_18_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_25_1", FIELD_fld_N1_S2_Mul_25_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_25_12", FIELD_fld_N1_S2_Mul_25_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_25_14", FIELD_fld_N1_S2_Mul_25_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_25_19", FIELD_fld_N1_S2_Mul_25_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_25_21", FIELD_fld_N1_S2_Mul_25_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_3_0", FIELD_fld_N1_S2_Mul_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_3_3", FIELD_fld_N1_S2_Mul_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_7_4", FIELD_fld_N1_S2_Mul_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_8_4", FIELD_fld_N1_S2_Mul_8_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N1_S2_Mul_8_8", FIELD_fld_N1_S2_Mul_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_12_0", FIELD_fld_N2_S0_LdSt_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_12_10", FIELD_fld_N2_S0_LdSt_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_12_11", FIELD_fld_N2_S0_LdSt_12_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_12_12", FIELD_fld_N2_S0_LdSt_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_12_4", FIELD_fld_N2_S0_LdSt_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_12_8", FIELD_fld_N2_S0_LdSt_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_13_11", FIELD_fld_N2_S0_LdSt_13_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_15_15", FIELD_fld_N2_S0_LdSt_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_10", FIELD_fld_N2_S0_LdSt_29_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_11", FIELD_fld_N2_S0_LdSt_29_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_12", FIELD_fld_N2_S0_LdSt_29_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_13", FIELD_fld_N2_S0_LdSt_29_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_14", FIELD_fld_N2_S0_LdSt_29_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_15", FIELD_fld_N2_S0_LdSt_29_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_16", FIELD_fld_N2_S0_LdSt_29_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_17", FIELD_fld_N2_S0_LdSt_29_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_18", FIELD_fld_N2_S0_LdSt_29_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_20", FIELD_fld_N2_S0_LdSt_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_5", FIELD_fld_N2_S0_LdSt_29_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_29_8", FIELD_fld_N2_S0_LdSt_29_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_3_0", FIELD_fld_N2_S0_LdSt_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_4_0", FIELD_fld_N2_S0_LdSt_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_4_4", FIELD_fld_N2_S0_LdSt_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_7_4", FIELD_fld_N2_S0_LdSt_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_7_6", FIELD_fld_N2_S0_LdSt_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_8_0", FIELD_fld_N2_S0_LdSt_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_8_4", FIELD_fld_N2_S0_LdSt_8_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_9_5", FIELD_fld_N2_S0_LdSt_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S0_LdSt_9_6", FIELD_fld_N2_S0_LdSt_9_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_12_10", FIELD_fld_N2_S1_Ld_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_12_2", FIELD_fld_N2_S1_Ld_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_12_4", FIELD_fld_N2_S1_Ld_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_12_8", FIELD_fld_N2_S1_Ld_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_1_0", FIELD_fld_N2_S1_Ld_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_10", FIELD_fld_N2_S1_Ld_26_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_11", FIELD_fld_N2_S1_Ld_26_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_12", FIELD_fld_N2_S1_Ld_26_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_13", FIELD_fld_N2_S1_Ld_26_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_15", FIELD_fld_N2_S1_Ld_26_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_16", FIELD_fld_N2_S1_Ld_26_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_17", FIELD_fld_N2_S1_Ld_26_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_2", FIELD_fld_N2_S1_Ld_26_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_8", FIELD_fld_N2_S1_Ld_26_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_26_9", FIELD_fld_N2_S1_Ld_26_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_3_0", FIELD_fld_N2_S1_Ld_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_3_2", FIELD_fld_N2_S1_Ld_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_4_0", FIELD_fld_N2_S1_Ld_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_4_3", FIELD_fld_N2_S1_Ld_4_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_4_4", FIELD_fld_N2_S1_Ld_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_7_0", FIELD_fld_N2_S1_Ld_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_7_2", FIELD_fld_N2_S1_Ld_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_7_4", FIELD_fld_N2_S1_Ld_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_7_6", FIELD_fld_N2_S1_Ld_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N2_S1_Ld_7_7", FIELD_fld_N2_S1_Ld_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_12_0", FIELD_fld_N0_S0_LdSt_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_12_12", FIELD_fld_N0_S0_LdSt_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_12_2", FIELD_fld_N0_S0_LdSt_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_12_4", FIELD_fld_N0_S0_LdSt_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_12_8", FIELD_fld_N0_S0_LdSt_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_22_0", FIELD_fld_N0_S0_LdSt_22_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_22_12", FIELD_fld_N0_S0_LdSt_22_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_22_13", FIELD_fld_N0_S0_LdSt_22_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_22_15", FIELD_fld_N0_S0_LdSt_22_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_22_16", FIELD_fld_N0_S0_LdSt_22_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_22_17", FIELD_fld_N0_S0_LdSt_22_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_3_0", FIELD_fld_N0_S0_LdSt_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_7_4", FIELD_fld_N0_S0_LdSt_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_7_5", FIELD_fld_N0_S0_LdSt_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S0_LdSt_7_6", FIELD_fld_N0_S0_LdSt_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S1_None_2_0", FIELD_fld_N0_S1_None_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S2_None_2_0", FIELD_fld_N0_S2_None_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_14_10", FIELD_fld_N0_S3_ALU_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_14_13", FIELD_fld_N0_S3_ALU_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_14_14", FIELD_fld_N0_S3_ALU_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_14_5", FIELD_fld_N0_S3_ALU_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_19_12", FIELD_fld_N0_S3_ALU_19_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_19_13", FIELD_fld_N0_S3_ALU_19_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_19_15", FIELD_fld_N0_S3_ALU_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_27_12", FIELD_fld_N0_S3_ALU_27_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_27_13", FIELD_fld_N0_S3_ALU_27_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_27_15", FIELD_fld_N0_S3_ALU_27_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_27_16", FIELD_fld_N0_S3_ALU_27_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_27_19", FIELD_fld_N0_S3_ALU_27_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_27_20", FIELD_fld_N0_S3_ALU_27_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_27_22", FIELD_fld_N0_S3_ALU_27_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_27_23", FIELD_fld_N0_S3_ALU_27_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_27_3", FIELD_fld_N0_S3_ALU_27_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_2_0", FIELD_fld_N0_S3_ALU_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_3_0", FIELD_fld_N0_S3_ALU_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_7_0", FIELD_fld_N0_S3_ALU_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_9_0", FIELD_fld_N0_S3_ALU_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_9_3", FIELD_fld_N0_S3_ALU_9_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_9_4", FIELD_fld_N0_S3_ALU_9_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_9_5", FIELD_fld_N0_S3_ALU_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_9_6", FIELD_fld_N0_S3_ALU_9_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_9_7", FIELD_fld_N0_S3_ALU_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_N0_S3_ALU_9_9", FIELD_fld_N0_S3_ALU_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_MTK_AndPOPC_c", FIELD_fld_MTK_AndPOPC_c, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_MTK_AndPOPC_inB", FIELD_fld_MTK_AndPOPC_inB, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_MTK_AndPOPC_inA", FIELD_fld_MTK_AndPOPC_inA, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_MTK_AndPOPC_oData", FIELD_fld_MTK_AndPOPC_oData, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F11_S4_ALU_24_16", FIELD_fld_F11_S4_ALU_24_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_F3_S4_ALU_23_16", FIELD_fld_F3_S4_ALU_23_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_iq_tie2apb_inq0_pop_qdata", FIELD_fld_iq_tie2apb_inq0_pop_qdata, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_iq_tie2apb_inq0_is_ready_is_ready", FIELD_fld_iq_tie2apb_inq0_is_ready_is_ready, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_11_8", FIELD_fld_Inst_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_iq_tie2apb_inq0_nonblocking_peek_success", FIELD_fld_iq_tie2apb_inq0_nonblocking_peek_success, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_iq_tie2apb_inq0_nonblocking_peek_qdata", FIELD_fld_iq_tie2apb_inq0_nonblocking_peek_qdata, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_iq_tie2apb_inq0_nonblocking_pop_success", FIELD_fld_iq_tie2apb_inq0_nonblocking_pop_success, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_iq_tie2apb_inq0_nonblocking_pop_qdata", FIELD_fld_iq_tie2apb_inq0_nonblocking_pop_qdata, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_23_8", FIELD_fld_Inst_23_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_iq_tie2apb_inq0_blocking_peek_qdata", FIELD_fld_iq_tie2apb_inq0_blocking_peek_qdata, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_23_12", FIELD_fld_Inst_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_push_read_qaddr", FIELD_fld_oq_tie2apb_outq0_push_read_qaddr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_push_read_qdata", FIELD_fld_oq_tie2apb_outq0_push_read_qdata, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_push_write_qaddr", FIELD_fld_oq_tie2apb_outq0_push_write_qaddr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_push_write_qdata", FIELD_fld_oq_tie2apb_outq0_push_write_qdata, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_is_ready_is_ready", FIELD_fld_oq_tie2apb_outq0_is_ready_is_ready, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_3_0", FIELD_fld_Inst_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_23_16", FIELD_fld_Inst_23_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_nonblocking_push_read_success", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_read_success, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_nonblocking_push_read_qaddr", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_read_qaddr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_nonblocking_push_read_qdata", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_read_qdata, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_nonblocking_push_write_success", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_write_success, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_nonblocking_push_write_qaddr", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_write_qaddr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_oq_tie2apb_outq0_nonblocking_push_write_qdata", FIELD_fld_oq_tie2apb_outq0_nonblocking_push_write_qdata, -1, 0, 0, 0, 0, 0, 0 } +}; + +enum xtensa_operand_id { + OPERAND_soffsetx4, + OPERAND_uimm12x8, + OPERAND_simm4, + OPERAND_arr, + OPERAND_ars, + OPERAND__ars_invisible, + OPERAND_art, + OPERAND_ar0, + OPERAND_ar4, + OPERAND_ar8, + OPERAND_ar12, + OPERAND_ars_entry, + OPERAND_immrx4, + OPERAND_lsi4x4, + OPERAND_simm7, + OPERAND_uimm6, + OPERAND_ai4const, + OPERAND_b4const, + OPERAND_b4constu, + OPERAND_uimm8, + OPERAND_uimm8x2, + OPERAND_uimm8x4, + OPERAND_uimm4x16, + OPERAND_uimmrx4, + OPERAND_simm8, + OPERAND_simm8x256, + OPERAND_simm12b, + OPERAND_msalp32, + OPERAND_op2p1, + OPERAND_label8, + OPERAND_ulabel8, + OPERAND_label12, + OPERAND_soffset, + OPERAND_uimm16x4, + OPERAND_bbi, + OPERAND_imm16, + OPERAND_sae, + OPERAND_sas, + OPERAND_sargt, + OPERAND_s, + OPERAND_immt, + OPERAND_imms, + OPERAND_bt, + OPERAND_bs, + OPERAND_br, + OPERAND_bt2, + OPERAND_bs2, + OPERAND_br2, + OPERAND_bt4, + OPERAND_bs4, + OPERAND_br4, + OPERAND_bt8, + OPERAND_bs8, + OPERAND_br8, + OPERAND_bt16, + OPERAND_bs16, + OPERAND_br16, + OPERAND_brall, + OPERAND_tp7, + OPERAND_xt_wbr15_label, + OPERAND_xt_wbr18_label, + OPERAND_opnd_ivp_sem_vec_alu_vr, + OPERAND_opnd_ivp_sem_vec_alu_vt, + OPERAND_opnd_ivp_sem_vec_alu_vs, + OPERAND_opnd_ivp_sem_vec_alu_vbr, + OPERAND_opnd_ivp_sem_multiply_vr, + OPERAND_opnd_ivp_sem_multiply_vs, + OPERAND_opnd_ivp_sem_multiply_wvt, + OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr, + OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbs, + OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt, + OPERAND_opnd_ivp_sem_vec_alu_vbt, + OPERAND_opnd_ivp_sem_vec_histogram_arr, + OPERAND_opnd_ivp_sem_vec_histogram_vr, + OPERAND_opnd_ivp_sem_vec_histogram_vs, + OPERAND_opnd_ivp_sem_vec_histogram_vt, + OPERAND_opnd_ivp_sem_vec_histogram_vbr, + OPERAND_opnd_ivp_sem_vec_histogram_vbs, + OPERAND_opnd_ivp_sem_divide_lane_ctrl, + OPERAND_opnd_ivp_sem_divide_vr, + OPERAND_opnd_ivp_sem_divide_vt, + OPERAND_opnd_ivp_sem_divide_vu, + OPERAND_opnd_ivp_sem_divide_vs, + OPERAND_opnd_ivp_sem_vec_select_slct, + OPERAND_opnd_ivp_sem_vec_select_vr, + OPERAND_opnd_ivp_sem_vec_select_vs, + OPERAND_opnd_ivp_sem_vec_select_vt, + OPERAND_opnd_ivp_sem_vec_select_vu, + OPERAND_opnd_ivp_sem_vec_select_slct_h, + OPERAND_opnd_ivp_sem_vec_select_sr, + OPERAND_opnd_ivp_sem_vec_select_vbr, + OPERAND_opnd_ivp_sem_vec_alu_i_imm3, + OPERAND_opnd_ivp_sem_vec_rep_i32, + OPERAND_opnd_ivp_sem_vec_rep_vr, + OPERAND_opnd_ivp_sem_vec_rep_i, + OPERAND_opnd_ivp_sem_ld_st_uul, + OPERAND_opnd_ivp_sem_ld_st_vrul, + OPERAND_opnd_ivp_sem_ld_st_vrul2, + OPERAND_opnd_ivp_sem_ld_st_i_bimm6, + OPERAND_opnd_ivp_sem_ld_st_i_bimm4, + OPERAND_opnd_ivp_sem_ld_st_vbr, + OPERAND_opnd_ivp_sem_ld_st_i_bimm6b2n, + OPERAND_opnd_ivp_sem_ld_st_i_bimm4b2n, + OPERAND_opnd_ivp_sem_ld_st_i_bimm6bn_2, + OPERAND_opnd_ivp_sem_ld_st_i_bimm4bn_2, + OPERAND_opnd_ivp_sem_ld_st_i_bimm6bn, + OPERAND_opnd_ivp_sem_ld_st_i_bimm4bn, + OPERAND_opnd_ivp_sem_ld_st_i_bimm6x1, + OPERAND_opnd_ivp_sem_ld_st_vr, + OPERAND_opnd_ivp_sem_ld_st_i_bimm4x1, + OPERAND_opnd_ivp_sem_ld_st_i_bimm8x4, + OPERAND_opnd_ivp_sem_ld_st_i_bimm4x4, + OPERAND_opnd_ivp_sem_ld_st_i_bimm6x2, + OPERAND_opnd_ivp_sem_ld_st_i_bimm4x2, + OPERAND_opnd_ivp_sem_ld_st_vrr, + OPERAND_opnd_ivp_sem_ld_st_i_bimm6x4, + OPERAND_bbe_ltrx2nimm, + OPERAND_bbe_ltrxn_2imm, + OPERAND_bbe_ltrxnimm, + OPERAND_opnd_ivp_sem_ld_st_i_bimm8, + OPERAND_opnd_ivp_sem_ld_st_vbre, + OPERAND_opnd_ivp_sem_ld_st_i_bimmh8, + OPERAND_opnd_ivp_sem_ld_st_i_bimmh4, + OPERAND_opnd_ivp_sem_ld_st_i_bimmh6, + OPERAND_opnd_ivp_sem_ld_st_i_bimmb8, + OPERAND_opnd_ivp_sem_ld_st_i_bimmb4, + OPERAND_opnd_ivp_sem_ld_st_i_bimmb6, + OPERAND_opnd_ivp_sem_ld_st_valignr, + OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr, + OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs, + OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt, + OPERAND_opnd_ivp_sem_vec_mov_vt, + OPERAND_opnd_ivp_sem_vec_mov_wvr, + OPERAND_opnd_ivp_sem_vec_mov_arr, + OPERAND_opnd_ivp_sem_vec_mov_i_IMM_movint, + OPERAND_opnd_ivp_sem_vec_mov_immmovvi, + OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvr, + OPERAND_opnd_ivp_sem_multiply_arr, + OPERAND_opnd_ivp_sem_multiply_vp, + OPERAND_opnd_ivp_sem_multiply_vt, + OPERAND_opnd_ivp_sem_multiply_vbr, + OPERAND_opnd_ivp_sem_vec_shift_vr, + OPERAND_opnd_ivp_sem_vec_shift_vt, + OPERAND_opnd_ivp_sem_wvec_pack_vt, + OPERAND_opnd_ivp_sem_wvec_pack_wvr, + OPERAND_opnd_ivp_sem_wvec_pack_arr, + OPERAND_opnd_ivp_sem_vec_reduce_vr, + OPERAND_opnd_ivp_sem_vec_reduce_vt, + OPERAND_opnd_ivp_sem_vec_reduce_vbr, + OPERAND_opnd_ivp_sem_vec_reduce_vbt, + OPERAND_opnd_ivp_sem_vec_rep_i8, + OPERAND_opnd_ivp_sem_vec_rep_vt, + OPERAND_saimm4, + OPERAND_saimm6_31, + OPERAND_saimm5, + OPERAND_opnd_ivp_sem_vec_shift_vs, + OPERAND_opnd_ivp_sem_ld_st_uus, + OPERAND_opnd_ivp_sem_vec_select_isel, + OPERAND_opnd_ivp_sem_vec_select_ishfl, + OPERAND_opnd_ivp_sem_sqz_vbr, + OPERAND_opnd_ivp_sem_sqz_vt, + OPERAND_opnd_ivp_sem_unpack_wvec_mov_vt, + OPERAND_opnd_ivp_sem_vec_scatter_gather_ars, + OPERAND_opnd_ivp_sem_vec_scatter_gather_gt, + OPERAND_opnd_ivp_sem_vec_scatter_gather_vs, + OPERAND_opnd_ivp_sem_vec_scatter_gather_vbr, + OPERAND_opnd_ivp_sem_vec_scatter_gather_gs, + OPERAND_opnd_ivp_sem_vec_scatter_gather_vt, + OPERAND_opnd_ivp_sem_vec_scatter_gather_vr, + OPERAND_opnd_ivp_sem_vbool_alu_ltr_art, + OPERAND_imm1_2N, + OPERAND_opnd_ivp_sem_multiply_vq, + OPERAND_opnd_ivp_sem_vec_rep_arr, + OPERAND_bbe_selimm_S0, + OPERAND_opnd_ivp_sem_vec_specialized_seli_vr, + OPERAND_opnd_ivp_sem_vec_specialized_seli_vs, + OPERAND_opnd_ivp_sem_vec_specialized_seli_vt, + OPERAND_bbe_selimm_S2, + OPERAND_bbe_selimm_S4, + OPERAND_bbe_shflimm_S0, + OPERAND_bbe_shflimm_S2, + OPERAND_bbe_shflimm_S4, + OPERAND_opnd_MTK_AndPOPC_c, + OPERAND_opnd_MTK_AndPOPC_inB, + OPERAND_opnd_MTK_AndPOPC_inA, + OPERAND_opnd_MTK_AndPOPC_oData, + OPERAND_opnd_iq_tie2apb_inq0_pop_qdata, + OPERAND_opnd_iq_tie2apb_inq0_is_ready_is_ready, + OPERAND_opnd_iq_tie2apb_inq0_nonblocking_peek_success, + OPERAND_opnd_iq_tie2apb_inq0_nonblocking_peek_qdata, + OPERAND_opnd_iq_tie2apb_inq0_nonblocking_pop_success, + OPERAND_opnd_iq_tie2apb_inq0_nonblocking_pop_qdata, + OPERAND_opnd_iq_tie2apb_inq0_blocking_peek_qdata, + OPERAND_opnd_oq_tie2apb_outq0_push_read_qaddr, + OPERAND_opnd_oq_tie2apb_outq0_push_read_qdata, + OPERAND_opnd_oq_tie2apb_outq0_push_write_qaddr, + OPERAND_opnd_oq_tie2apb_outq0_push_write_qdata, + OPERAND_opnd_oq_tie2apb_outq0_is_ready_is_ready, + OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_read_success, + OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_read_qaddr, + OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_read_qdata, + OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_write_success, + OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_write_qaddr, + OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_write_qdata, + OPERAND_t, + OPERAND_bbi4, + OPERAND_imm12, + OPERAND_imm8, + OPERAND_imm12b, + OPERAND_m, + OPERAND_n, + OPERAND_offset, + OPERAND_op0, + OPERAND_op1, + OPERAND_op2, + OPERAND_r, + OPERAND_sa4, + OPERAND_sae4, + OPERAND_sal, + OPERAND_sas4, + OPERAND_sr, + OPERAND_st, + OPERAND_thi3, + OPERAND_imm4, + OPERAND_mn, + OPERAND_i, + OPERAND_imm6lo, + OPERAND_imm6hi, + OPERAND_imm7lo, + OPERAND_imm7hi, + OPERAND_z, + OPERAND_imm6, + OPERAND_imm7, + OPERAND_t2, + OPERAND_s2, + OPERAND_r2, + OPERAND_t4, + OPERAND_s4, + OPERAND_r4, + OPERAND_t8, + OPERAND_s8, + OPERAND_r8, + OPERAND_xt_wbr15_imm, + OPERAND_xt_wbr18_imm, + OPERAND_fld_F0_S0_LdSt_11_4, + OPERAND_fld_F0_S0_LdSt_11_8, + OPERAND_fld_F0_S0_LdSt_11_9, + OPERAND_fld_F0_S0_LdSt_12_0, + OPERAND_fld_F0_S0_LdSt_12_11, + OPERAND_fld_F0_S0_LdSt_12_12, + OPERAND_fld_F0_S0_LdSt_12_2, + OPERAND_fld_F0_S0_LdSt_12_4, + OPERAND_fld_F0_S0_LdSt_12_8, + OPERAND_fld_F0_S0_LdSt_13_9, + OPERAND_fld_F0_S0_LdSt_15_15, + OPERAND_fld_F0_S0_LdSt_33_11, + OPERAND_fld_F0_S0_LdSt_33_12, + OPERAND_fld_F0_S0_LdSt_33_13, + OPERAND_fld_F0_S0_LdSt_33_14, + OPERAND_fld_F0_S0_LdSt_33_15, + OPERAND_fld_F0_S0_LdSt_33_16, + OPERAND_fld_F0_S0_LdSt_33_17, + OPERAND_fld_F0_S0_LdSt_33_18, + OPERAND_fld_F0_S0_LdSt_33_19, + OPERAND_fld_F0_S0_LdSt_33_20, + OPERAND_fld_F0_S0_LdSt_33_27, + OPERAND_fld_F0_S0_LdSt_33_9, + OPERAND_fld_F0_S0_LdSt_3_0, + OPERAND_fld_F0_S0_LdSt_7_4, + OPERAND_fld_F0_S0_LdSt_7_5, + OPERAND_fld_F0_S0_LdSt_7_6, + OPERAND_fld_F0_S0_LdSt_7_7, + OPERAND_fld_F0_S0_LdSt_8_0, + OPERAND_fld_F0_S0_LdSt_8_4, + OPERAND_fld_F0_S0_LdSt_8_8, + OPERAND_fld_bbe_shflimm_S0, + OPERAND_fld_ivp_sem_ld_st_i_bimm4, + OPERAND_fld_ivp_sem_ld_st_i_bimm4b2n, + OPERAND_fld_ivp_sem_ld_st_i_bimm4bn, + OPERAND_fld_ivp_sem_ld_st_i_bimm4bn_2, + OPERAND_fld_ivp_sem_ld_st_i_bimm4x1, + OPERAND_fld_ivp_sem_ld_st_i_bimm4x2, + OPERAND_fld_ivp_sem_ld_st_i_bimm4x4, + OPERAND_fld_ivp_sem_ld_st_i_bimm6, + OPERAND_fld_ivp_sem_ld_st_i_bimm6b2n, + OPERAND_fld_ivp_sem_ld_st_i_bimm6bn, + OPERAND_fld_ivp_sem_ld_st_i_bimm6bn_2, + OPERAND_fld_ivp_sem_ld_st_i_bimm6x1, + OPERAND_fld_ivp_sem_ld_st_i_bimm6x2, + OPERAND_fld_ivp_sem_ld_st_i_bimm6x4, + OPERAND_fld_ivp_sem_ld_st_i_bimm8, + OPERAND_fld_ivp_sem_ld_st_i_bimm8x4, + OPERAND_fld_ivp_sem_ld_st_i_bimmb4, + OPERAND_fld_ivp_sem_ld_st_i_bimmb6, + OPERAND_fld_ivp_sem_ld_st_i_bimmb8, + OPERAND_fld_ivp_sem_ld_st_i_bimmh4, + OPERAND_fld_ivp_sem_ld_st_i_bimmh6, + OPERAND_fld_ivp_sem_ld_st_i_bimmh8, + OPERAND_fld_ivp_sem_ld_st_uul, + OPERAND_fld_ivp_sem_ld_st_uus, + OPERAND_fld_ivp_sem_ld_st_valignr, + OPERAND_fld_ivp_sem_ld_st_vbr, + OPERAND_fld_ivp_sem_ld_st_vbre, + OPERAND_fld_ivp_sem_ld_st_vr, + OPERAND_fld_ivp_sem_ld_st_vrr, + OPERAND_fld_ivp_sem_ld_st_vrul, + OPERAND_fld_ivp_sem_vec_alu_arr, + OPERAND_fld_ivp_sem_vec_alu_vbr, + OPERAND_fld_ivp_sem_vec_alu_vr, + OPERAND_fld_ivp_sem_vec_alu_vt, + OPERAND_fld_ivp_sem_vec_rep_i, + OPERAND_fld_ivp_sem_vec_rep_i32, + OPERAND_fld_ivp_sem_vec_rep_i8, + OPERAND_fld_ivp_sem_vec_rep_vr, + OPERAND_fld_ivp_sem_vec_rep_vt, + OPERAND_fld_ivp_sem_vec_scatter_gather_ars, + OPERAND_fld_ivp_sem_vec_scatter_gather_gt, + OPERAND_fld_ivp_sem_vec_scatter_gather_vbr, + OPERAND_fld_ivp_sem_vec_scatter_gather_vs, + OPERAND_fld_ivp_sem_vec_shift_vr, + OPERAND_fld_ivp_sem_vec_shift_vt, + OPERAND_fld_ivp_sem_vec_specialized_seli_vr, + OPERAND_fld_ivp_sem_vec_specialized_seli_vt, + OPERAND_fld_saimm4, + OPERAND_fld_saimm5, + OPERAND_fld_F0_S1_Ld_12_11, + OPERAND_fld_F0_S1_Ld_12_12, + OPERAND_fld_F0_S1_Ld_12_4, + OPERAND_fld_F0_S1_Ld_15_10, + OPERAND_fld_F0_S1_Ld_15_13, + OPERAND_fld_F0_S1_Ld_15_14, + OPERAND_fld_F0_S1_Ld_15_15, + OPERAND_fld_F0_S1_Ld_15_2, + OPERAND_fld_F0_S1_Ld_15_4, + OPERAND_fld_F0_S1_Ld_15_8, + OPERAND_fld_F0_S1_Ld_24_0, + OPERAND_fld_F0_S1_Ld_24_11, + OPERAND_fld_F0_S1_Ld_24_12, + OPERAND_fld_F0_S1_Ld_24_13, + OPERAND_fld_F0_S1_Ld_24_14, + OPERAND_fld_F0_S1_Ld_24_16, + OPERAND_fld_F0_S1_Ld_24_17, + OPERAND_fld_F0_S1_Ld_24_18, + OPERAND_fld_F0_S1_Ld_24_8, + OPERAND_fld_F0_S1_Ld_3_0, + OPERAND_fld_F0_S1_Ld_3_2, + OPERAND_fld_F0_S1_Ld_7_0, + OPERAND_fld_F0_S1_Ld_7_2, + OPERAND_fld_F0_S1_Ld_7_3, + OPERAND_fld_F0_S1_Ld_7_4, + OPERAND_fld_F0_S1_Ld_7_5, + OPERAND_fld_F0_S1_Ld_7_6, + OPERAND_fld_F0_S1_Ld_7_7, + OPERAND_fld_bbe_ltrx2nimm, + OPERAND_fld_bbe_ltrxn_2imm, + OPERAND_fld_bbe_ltrxnimm, + OPERAND_fld_imm1_2N, + OPERAND_fld_ivp_sem_sqz_vbr, + OPERAND_fld_ivp_sem_sqz_vt, + OPERAND_fld_ivp_sem_vbool_alu_ltr_art, + OPERAND_fld_ivp_sem_vbool_alu_ltr_vbr, + OPERAND_fld_ivp_sem_vbool_alu_ltr_vbs, + OPERAND_fld_ivp_sem_vbool_alu_ltr_vbt, + OPERAND_fld_ivp_sem_vec_mov_arr, + OPERAND_fld_ivp_sem_vec_mov_i_IMM_movint, + OPERAND_fld_ivp_sem_vec_mov_i_imm4, + OPERAND_fld_ivp_sem_vec_mov_immmovvi, + OPERAND_fld_ivp_sem_vec_mov_vbr, + OPERAND_fld_ivp_sem_vec_mov_vt, + OPERAND_fld_ivp_sem_vec_mov_wvr, + OPERAND_fld_ivp_sem_vec_scatter_gather_gs, + OPERAND_fld_ivp_sem_vec_scatter_gather_vt, + OPERAND_fld_ivp_sem_wvec_pack_arr, + OPERAND_fld_ivp_sem_wvec_pack_vt, + OPERAND_fld_ivp_sem_wvec_pack_wvr, + OPERAND_fld_F0_S2_Mul_11_8, + OPERAND_fld_F0_S2_Mul_13_12, + OPERAND_fld_F0_S2_Mul_18_12, + OPERAND_fld_F0_S2_Mul_18_14, + OPERAND_fld_F0_S2_Mul_18_9, + OPERAND_fld_F0_S2_Mul_1_0, + OPERAND_fld_F0_S2_Mul_26_12, + OPERAND_fld_F0_S2_Mul_26_13, + OPERAND_fld_F0_S2_Mul_26_14, + OPERAND_fld_F0_S2_Mul_26_2, + OPERAND_fld_F0_S2_Mul_26_20, + OPERAND_fld_F0_S2_Mul_26_21, + OPERAND_fld_F0_S2_Mul_3_0, + OPERAND_fld_F0_S2_Mul_3_3, + OPERAND_fld_F0_S2_Mul_4_4, + OPERAND_fld_F0_S2_Mul_7_4, + OPERAND_fld_F0_S2_Mul_7_5, + OPERAND_fld_ivp_sem_multiply_arr, + OPERAND_fld_ivp_sem_multiply_vp, + OPERAND_fld_ivp_sem_multiply_vr, + OPERAND_fld_ivp_sem_multiply_vs, + OPERAND_fld_ivp_sem_multiply_wvt, + OPERAND_fld_ivp_sem_unpack_wvec_mov_vr, + OPERAND_fld_ivp_sem_unpack_wvec_mov_vs, + OPERAND_fld_ivp_sem_unpack_wvec_mov_wvr, + OPERAND_fld_ivp_sem_unpack_wvec_mov_wvt, + OPERAND_fld_ivp_sem_vec_alu_vbt, + OPERAND_fld_ivp_sem_vec_alu_vs, + OPERAND_fld_F0_S3_ALU_0_0, + OPERAND_fld_F0_S3_ALU_14_10, + OPERAND_fld_F0_S3_ALU_14_11, + OPERAND_fld_F0_S3_ALU_14_13, + OPERAND_fld_F0_S3_ALU_14_14, + OPERAND_fld_F0_S3_ALU_14_8, + OPERAND_fld_F0_S3_ALU_24_10, + OPERAND_fld_F0_S3_ALU_24_13, + OPERAND_fld_F0_S3_ALU_24_19, + OPERAND_fld_F0_S3_ALU_24_20, + OPERAND_fld_F0_S3_ALU_33_10, + OPERAND_fld_F0_S3_ALU_33_13, + OPERAND_fld_F0_S3_ALU_33_18, + OPERAND_fld_F0_S3_ALU_33_19, + OPERAND_fld_F0_S3_ALU_33_20, + OPERAND_fld_F0_S3_ALU_33_25, + OPERAND_fld_F0_S3_ALU_33_26, + OPERAND_fld_F0_S3_ALU_33_27, + OPERAND_fld_F0_S3_ALU_33_28, + OPERAND_fld_F0_S3_ALU_33_9, + OPERAND_fld_F0_S3_ALU_3_0, + OPERAND_fld_F0_S3_ALU_3_1, + OPERAND_fld_F0_S3_ALU_3_2, + OPERAND_fld_F0_S3_ALU_3_3, + OPERAND_fld_F0_S3_ALU_7_3, + OPERAND_fld_F0_S3_ALU_7_4, + OPERAND_fld_F0_S3_ALU_7_7, + OPERAND_fld_F0_S3_ALU_8_0, + OPERAND_fld_F0_S3_ALU_8_8, + OPERAND_fld_F0_S3_ALU_9_0, + OPERAND_fld_F0_S3_ALU_9_7, + OPERAND_fld_F0_S3_ALU_9_8, + OPERAND_fld_fp_sem_hp_cnv_i_imm4, + OPERAND_fld_fp_sem_hp_cnv_vbr, + OPERAND_fld_fp_sem_hp_cnv_vr, + OPERAND_fld_fp_sem_hp_cnv_vs, + OPERAND_fld_fp_sem_hp_cnv_vt, + OPERAND_fld_ivp_sem_sp32cvt_i_imm5, + OPERAND_fld_ivp_sem_sp32cvt_vbr, + OPERAND_fld_ivp_sem_sp32cvt_vr, + OPERAND_fld_ivp_sem_sp32cvt_vt, + OPERAND_fld_ivp_sem_spmisc_vbr, + OPERAND_fld_ivp_sem_spmisc_vr, + OPERAND_fld_ivp_sem_spmisc_vs, + OPERAND_fld_ivp_sem_spmisc_vsM, + OPERAND_fld_ivp_sem_spmisc_vt, + OPERAND_fld_ivp_sem_vec_alu_i_imm3, + OPERAND_fld_ivp_sem_vec_reduce_vbr, + OPERAND_fld_ivp_sem_vec_reduce_vbt, + OPERAND_fld_ivp_sem_vec_reduce_vr, + OPERAND_fld_ivp_sem_vec_reduce_vt, + OPERAND_fld_ivp_sem_vec_rep_arr, + OPERAND_fld_ivp_sem_vec_select_isel, + OPERAND_fld_ivp_sem_vec_select_ishfl, + OPERAND_fld_ivp_sem_vec_select_slct, + OPERAND_fld_ivp_sem_vec_select_slct_h, + OPERAND_fld_ivp_sem_vec_select_sr, + OPERAND_fld_ivp_sem_vec_select_vbr, + OPERAND_fld_ivp_sem_vec_select_vr, + OPERAND_fld_ivp_sem_vec_select_vs, + OPERAND_fld_ivp_sem_vec_select_vt, + OPERAND_fld_ivp_sem_vec_select_vu, + OPERAND_fld_ivp_sem_vec_shift_vs, + OPERAND_fld_saimm6_31, + OPERAND_fld_F1_S0_LdStALU_12_0, + OPERAND_fld_F1_S0_LdStALU_12_12, + OPERAND_fld_F1_S0_LdStALU_12_2, + OPERAND_fld_F1_S0_LdStALU_12_4, + OPERAND_fld_F1_S0_LdStALU_12_8, + OPERAND_fld_F1_S0_LdStALU_14_10, + OPERAND_fld_F1_S0_LdStALU_14_12, + OPERAND_fld_F1_S0_LdStALU_14_14, + OPERAND_fld_F1_S0_LdStALU_15_15, + OPERAND_fld_F1_S0_LdStALU_30_12, + OPERAND_fld_F1_S0_LdStALU_30_13, + OPERAND_fld_F1_S0_LdStALU_30_14, + OPERAND_fld_F1_S0_LdStALU_30_15, + OPERAND_fld_F1_S0_LdStALU_30_16, + OPERAND_fld_F1_S0_LdStALU_30_17, + OPERAND_fld_F1_S0_LdStALU_30_18, + OPERAND_fld_F1_S0_LdStALU_30_19, + OPERAND_fld_F1_S0_LdStALU_30_20, + OPERAND_fld_F1_S0_LdStALU_30_6, + OPERAND_fld_F1_S0_LdStALU_30_8, + OPERAND_fld_F1_S0_LdStALU_30_9, + OPERAND_fld_F1_S0_LdStALU_3_0, + OPERAND_fld_F1_S0_LdStALU_5_0, + OPERAND_fld_F1_S0_LdStALU_5_4, + OPERAND_fld_F1_S0_LdStALU_7_4, + OPERAND_fld_F1_S0_LdStALU_7_5, + OPERAND_fld_F1_S0_LdStALU_7_7, + OPERAND_fld_F1_S0_LdStALU_9_9, + OPERAND_fld_bbe_selimm_S0, + OPERAND_fld_ivp_sem_vec_scatter_gather_vr, + OPERAND_fld_ivp_sem_vec_specialized_seli_vs, + OPERAND_fld_F1_S1_Ld_12_10, + OPERAND_fld_F1_S1_Ld_12_11, + OPERAND_fld_F1_S1_Ld_12_12, + OPERAND_fld_F1_S1_Ld_12_4, + OPERAND_fld_F1_S1_Ld_12_9, + OPERAND_fld_F1_S1_Ld_15_10, + OPERAND_fld_F1_S1_Ld_15_13, + OPERAND_fld_F1_S1_Ld_15_14, + OPERAND_fld_F1_S1_Ld_15_15, + OPERAND_fld_F1_S1_Ld_15_2, + OPERAND_fld_F1_S1_Ld_15_4, + OPERAND_fld_F1_S1_Ld_15_8, + OPERAND_fld_F1_S1_Ld_1_0, + OPERAND_fld_F1_S1_Ld_26_11, + OPERAND_fld_F1_S1_Ld_26_12, + OPERAND_fld_F1_S1_Ld_26_13, + OPERAND_fld_F1_S1_Ld_26_16, + OPERAND_fld_F1_S1_Ld_26_18, + OPERAND_fld_F1_S1_Ld_26_2, + OPERAND_fld_F1_S1_Ld_3_0, + OPERAND_fld_F1_S1_Ld_3_2, + OPERAND_fld_F1_S1_Ld_7_0, + OPERAND_fld_F1_S1_Ld_7_2, + OPERAND_fld_F1_S1_Ld_7_3, + OPERAND_fld_F1_S1_Ld_7_4, + OPERAND_fld_F1_S1_Ld_7_5, + OPERAND_fld_F1_S1_Ld_7_6, + OPERAND_fld_F1_S1_Ld_7_7, + OPERAND_fld_F1_S2_Mul_13_10, + OPERAND_fld_F1_S2_Mul_13_2, + OPERAND_fld_F1_S2_Mul_13_5, + OPERAND_fld_F1_S2_Mul_14_10, + OPERAND_fld_F1_S2_Mul_28_12, + OPERAND_fld_F1_S2_Mul_28_15, + OPERAND_fld_F1_S2_Mul_28_16, + OPERAND_fld_F1_S2_Mul_28_18, + OPERAND_fld_F1_S2_Mul_28_20, + OPERAND_fld_F1_S2_Mul_28_4, + OPERAND_fld_F1_S2_Mul_28_5, + OPERAND_fld_F1_S2_Mul_3_0, + OPERAND_fld_F1_S2_Mul_3_2, + OPERAND_fld_F1_S2_Mul_3_3, + OPERAND_fld_F1_S2_Mul_4_4, + OPERAND_fld_F1_S2_Mul_9_5, + OPERAND_fld_F1_S2_Mul_9_6, + OPERAND_fld_bbe_selimm_S2, + OPERAND_fld_bbe_shflimm_S2, + OPERAND_fld_fp_sem_hp_fma_vbr, + OPERAND_fld_fp_sem_hp_fma_vr, + OPERAND_fld_fp_sem_hp_fma_vs, + OPERAND_fld_fp_sem_hp_fma_vt, + OPERAND_fld_ivp_sem_multiply_vt, + OPERAND_fld_ivp_sem_spfma_vbr, + OPERAND_fld_ivp_sem_spfma_vr, + OPERAND_fld_ivp_sem_spfma_vs, + OPERAND_fld_ivp_sem_spfma_vt, + OPERAND_fld_ivp_sem_unpack_wvec_mov_vt, + OPERAND_fld_F1_S3_ALU_0_0, + OPERAND_fld_F1_S3_ALU_14_10, + OPERAND_fld_F1_S3_ALU_14_13, + OPERAND_fld_F1_S3_ALU_14_14, + OPERAND_fld_F1_S3_ALU_14_8, + OPERAND_fld_F1_S3_ALU_19_14, + OPERAND_fld_F1_S3_ALU_19_15, + OPERAND_fld_F1_S3_ALU_19_19, + OPERAND_fld_F1_S3_ALU_19_4, + OPERAND_fld_F1_S3_ALU_19_7, + OPERAND_fld_F1_S3_ALU_30_15, + OPERAND_fld_F1_S3_ALU_30_17, + OPERAND_fld_F1_S3_ALU_30_19, + OPERAND_fld_F1_S3_ALU_30_20, + OPERAND_fld_F1_S3_ALU_30_22, + OPERAND_fld_F1_S3_ALU_30_23, + OPERAND_fld_F1_S3_ALU_30_6, + OPERAND_fld_F1_S3_ALU_30_8, + OPERAND_fld_F1_S3_ALU_3_0, + OPERAND_fld_F1_S3_ALU_3_1, + OPERAND_fld_F1_S3_ALU_3_2, + OPERAND_fld_F1_S3_ALU_3_3, + OPERAND_fld_F1_S3_ALU_5_0, + OPERAND_fld_F1_S3_ALU_9_0, + OPERAND_fld_F1_S3_ALU_9_1, + OPERAND_fld_F1_S3_ALU_9_2, + OPERAND_fld_F1_S3_ALU_9_3, + OPERAND_fld_F1_S3_ALU_9_7, + OPERAND_fld_F1_S3_ALU_9_8, + OPERAND_fld_F1_S3_ALU_9_9, + OPERAND_fld_ivp_sem_vec_histogram_arr, + OPERAND_fld_ivp_sem_vec_histogram_vr, + OPERAND_fld_ivp_sem_vec_histogram_vs, + OPERAND_fld_ivp_sem_vec_histogram_vt, + OPERAND_fld_F2_S0_LdSt_12_0, + OPERAND_fld_F2_S0_LdSt_12_10, + OPERAND_fld_F2_S0_LdSt_12_2, + OPERAND_fld_F2_S0_LdSt_12_4, + OPERAND_fld_F2_S0_LdSt_12_8, + OPERAND_fld_F2_S0_LdSt_15_15, + OPERAND_fld_F2_S0_LdSt_28_11, + OPERAND_fld_F2_S0_LdSt_28_12, + OPERAND_fld_F2_S0_LdSt_28_13, + OPERAND_fld_F2_S0_LdSt_28_14, + OPERAND_fld_F2_S0_LdSt_28_15, + OPERAND_fld_F2_S0_LdSt_28_16, + OPERAND_fld_F2_S0_LdSt_28_17, + OPERAND_fld_F2_S0_LdSt_28_18, + OPERAND_fld_F2_S0_LdSt_28_20, + OPERAND_fld_F2_S0_LdSt_28_4, + OPERAND_fld_F2_S0_LdSt_28_8, + OPERAND_fld_F2_S0_LdSt_3_0, + OPERAND_fld_F2_S0_LdSt_3_2, + OPERAND_fld_F2_S0_LdSt_7_2, + OPERAND_fld_F2_S0_LdSt_7_4, + OPERAND_fld_F2_S1_Ld_12_10, + OPERAND_fld_F2_S1_Ld_12_11, + OPERAND_fld_F2_S1_Ld_12_4, + OPERAND_fld_F2_S1_Ld_12_9, + OPERAND_fld_F2_S1_Ld_15_10, + OPERAND_fld_F2_S1_Ld_15_13, + OPERAND_fld_F2_S1_Ld_15_14, + OPERAND_fld_F2_S1_Ld_15_15, + OPERAND_fld_F2_S1_Ld_15_2, + OPERAND_fld_F2_S1_Ld_15_4, + OPERAND_fld_F2_S1_Ld_15_8, + OPERAND_fld_F2_S1_Ld_1_0, + OPERAND_fld_F2_S1_Ld_26_11, + OPERAND_fld_F2_S1_Ld_26_12, + OPERAND_fld_F2_S1_Ld_26_13, + OPERAND_fld_F2_S1_Ld_26_16, + OPERAND_fld_F2_S1_Ld_26_18, + OPERAND_fld_F2_S1_Ld_26_2, + OPERAND_fld_F2_S1_Ld_3_0, + OPERAND_fld_F2_S1_Ld_3_2, + OPERAND_fld_F2_S1_Ld_7_0, + OPERAND_fld_F2_S1_Ld_7_2, + OPERAND_fld_F2_S1_Ld_7_3, + OPERAND_fld_F2_S1_Ld_7_4, + OPERAND_fld_F2_S1_Ld_7_6, + OPERAND_fld_F2_S1_Ld_7_7, + OPERAND_fld_F2_S2_Mul_14_10, + OPERAND_fld_F2_S2_Mul_14_11, + OPERAND_fld_F2_S2_Mul_14_5, + OPERAND_fld_F2_S2_Mul_19_10, + OPERAND_fld_F2_S2_Mul_19_15, + OPERAND_fld_F2_S2_Mul_19_7, + OPERAND_fld_F2_S2_Mul_30_10, + OPERAND_fld_F2_S2_Mul_30_12, + OPERAND_fld_F2_S2_Mul_30_15, + OPERAND_fld_F2_S2_Mul_30_18, + OPERAND_fld_F2_S2_Mul_30_19, + OPERAND_fld_F2_S2_Mul_30_20, + OPERAND_fld_F2_S2_Mul_30_21, + OPERAND_fld_F2_S2_Mul_30_6, + OPERAND_fld_F2_S2_Mul_3_0, + OPERAND_fld_F2_S2_Mul_4_0, + OPERAND_fld_F2_S2_Mul_4_3, + OPERAND_fld_F2_S2_Mul_5_0, + OPERAND_fld_ivp_sem_divide_lane_ctrl, + OPERAND_fld_ivp_sem_divide_vr, + OPERAND_fld_ivp_sem_divide_vs, + OPERAND_fld_ivp_sem_divide_vt, + OPERAND_fld_ivp_sem_divide_vu, + OPERAND_fld_ivp_sem_multiply_vbr, + OPERAND_fld_F2_S3_ALU_0_0, + OPERAND_fld_F2_S3_ALU_14_10, + OPERAND_fld_F2_S3_ALU_14_13, + OPERAND_fld_F2_S3_ALU_14_14, + OPERAND_fld_F2_S3_ALU_14_8, + OPERAND_fld_F2_S3_ALU_19_14, + OPERAND_fld_F2_S3_ALU_19_15, + OPERAND_fld_F2_S3_ALU_19_19, + OPERAND_fld_F2_S3_ALU_19_4, + OPERAND_fld_F2_S3_ALU_19_7, + OPERAND_fld_F2_S3_ALU_30_15, + OPERAND_fld_F2_S3_ALU_30_18, + OPERAND_fld_F2_S3_ALU_30_19, + OPERAND_fld_F2_S3_ALU_30_20, + OPERAND_fld_F2_S3_ALU_30_22, + OPERAND_fld_F2_S3_ALU_30_23, + OPERAND_fld_F2_S3_ALU_30_6, + OPERAND_fld_F2_S3_ALU_30_8, + OPERAND_fld_F2_S3_ALU_3_0, + OPERAND_fld_F2_S3_ALU_3_1, + OPERAND_fld_F2_S3_ALU_3_2, + OPERAND_fld_F2_S3_ALU_3_3, + OPERAND_fld_F2_S3_ALU_5_0, + OPERAND_fld_F2_S3_ALU_9_0, + OPERAND_fld_F2_S3_ALU_9_1, + OPERAND_fld_F2_S3_ALU_9_2, + OPERAND_fld_F2_S3_ALU_9_3, + OPERAND_fld_F2_S3_ALU_9_7, + OPERAND_fld_F2_S3_ALU_9_8, + OPERAND_fld_F2_S3_ALU_9_9, + OPERAND_fld_F3_S0_LdSt_0_0, + OPERAND_fld_F3_S0_LdSt_12_0, + OPERAND_fld_F3_S0_LdSt_12_11, + OPERAND_fld_F3_S0_LdSt_12_12, + OPERAND_fld_F3_S0_LdSt_12_4, + OPERAND_fld_F3_S0_LdSt_12_8, + OPERAND_fld_F3_S0_LdSt_13_9, + OPERAND_fld_F3_S0_LdSt_15_15, + OPERAND_fld_F3_S0_LdSt_25_1, + OPERAND_fld_F3_S0_LdSt_25_11, + OPERAND_fld_F3_S0_LdSt_25_12, + OPERAND_fld_F3_S0_LdSt_25_13, + OPERAND_fld_F3_S0_LdSt_25_14, + OPERAND_fld_F3_S0_LdSt_25_15, + OPERAND_fld_F3_S0_LdSt_25_16, + OPERAND_fld_F3_S0_LdSt_25_17, + OPERAND_fld_F3_S0_LdSt_25_18, + OPERAND_fld_F3_S0_LdSt_25_19, + OPERAND_fld_F3_S0_LdSt_25_20, + OPERAND_fld_F3_S0_LdSt_25_4, + OPERAND_fld_F3_S0_LdSt_25_8, + OPERAND_fld_F3_S0_LdSt_25_9, + OPERAND_fld_F3_S0_LdSt_3_0, + OPERAND_fld_F3_S0_LdSt_7_4, + OPERAND_fld_F3_S0_LdSt_7_5, + OPERAND_fld_F3_S0_LdSt_7_7, + OPERAND_fld_F3_S0_LdSt_8_0, + OPERAND_fld_F3_S1_Ld_12_11, + OPERAND_fld_F3_S1_Ld_12_2, + OPERAND_fld_F3_S1_Ld_12_4, + OPERAND_fld_F3_S1_Ld_12_8, + OPERAND_fld_F3_S1_Ld_21_0, + OPERAND_fld_F3_S1_Ld_21_10, + OPERAND_fld_F3_S1_Ld_21_11, + OPERAND_fld_F3_S1_Ld_21_12, + OPERAND_fld_F3_S1_Ld_21_13, + OPERAND_fld_F3_S1_Ld_21_15, + OPERAND_fld_F3_S1_Ld_21_16, + OPERAND_fld_F3_S1_Ld_21_17, + OPERAND_fld_F3_S1_Ld_21_8, + OPERAND_fld_F3_S1_Ld_21_9, + OPERAND_fld_F3_S1_Ld_3_0, + OPERAND_fld_F3_S1_Ld_3_2, + OPERAND_fld_F3_S1_Ld_4_0, + OPERAND_fld_F3_S1_Ld_4_3, + OPERAND_fld_F3_S1_Ld_4_4, + OPERAND_fld_F3_S1_Ld_7_0, + OPERAND_fld_F3_S1_Ld_7_2, + OPERAND_fld_F3_S1_Ld_7_4, + OPERAND_fld_F3_S1_Ld_7_7, + OPERAND_fld_F3_S2_Mul_11_8, + OPERAND_fld_F3_S2_Mul_13_12, + OPERAND_fld_F3_S2_Mul_13_7, + OPERAND_fld_F3_S2_Mul_21_0, + OPERAND_fld_F3_S2_Mul_21_12, + OPERAND_fld_F3_S2_Mul_21_13, + OPERAND_fld_F3_S2_Mul_21_14, + OPERAND_fld_F3_S2_Mul_21_15, + OPERAND_fld_F3_S2_Mul_21_16, + OPERAND_fld_F3_S2_Mul_3_0, + OPERAND_fld_F3_S2_Mul_3_3, + OPERAND_fld_F3_S2_Mul_4_0, + OPERAND_fld_F3_S2_Mul_7_4, + OPERAND_fld_F3_S2_Mul_7_5, + OPERAND_fld_F3_S3_ALU_13_9, + OPERAND_fld_F3_S3_ALU_18_12, + OPERAND_fld_F3_S3_ALU_18_13, + OPERAND_fld_F3_S3_ALU_18_14, + OPERAND_fld_F3_S3_ALU_18_18, + OPERAND_fld_F3_S3_ALU_18_3, + OPERAND_fld_F3_S3_ALU_18_7, + OPERAND_fld_F3_S3_ALU_18_8, + OPERAND_fld_F3_S3_ALU_28_12, + OPERAND_fld_F3_S3_ALU_28_13, + OPERAND_fld_F3_S3_ALU_28_14, + OPERAND_fld_F3_S3_ALU_28_18, + OPERAND_fld_F3_S3_ALU_28_19, + OPERAND_fld_F3_S3_ALU_28_20, + OPERAND_fld_F3_S3_ALU_28_21, + OPERAND_fld_F3_S3_ALU_28_22, + OPERAND_fld_F3_S3_ALU_28_25, + OPERAND_fld_F3_S3_ALU_28_4, + OPERAND_fld_F3_S3_ALU_28_8, + OPERAND_fld_F3_S3_ALU_28_9, + OPERAND_fld_F3_S3_ALU_3_0, + OPERAND_fld_F3_S3_ALU_3_2, + OPERAND_fld_F3_S3_ALU_3_3, + OPERAND_fld_F3_S3_ALU_7_3, + OPERAND_fld_F3_S3_ALU_7_6, + OPERAND_fld_F3_S3_ALU_7_7, + OPERAND_fld_F3_S3_ALU_8_0, + OPERAND_fld_ivp_sem_vec_histogram_vbr, + OPERAND_fld_ivp_sem_vec_histogram_vbs, + OPERAND_fld_F3_S4_ALU_14_10, + OPERAND_fld_F3_S4_ALU_23_0, + OPERAND_fld_F3_S4_ALU_23_15, + OPERAND_fld_F3_S4_ALU_23_18, + OPERAND_fld_F3_S4_ALU_23_20, + OPERAND_fld_F3_S4_ALU_9_5, + OPERAND_fld_F3_S4_ALU_9_6, + OPERAND_fld_bbe_selimm_S4, + OPERAND_fld_bbe_shflimm_S4, + OPERAND_fld_F4_S0_Ld_11_4, + OPERAND_fld_F4_S0_Ld_11_8, + OPERAND_fld_F4_S0_Ld_11_9, + OPERAND_fld_F4_S0_Ld_12_0, + OPERAND_fld_F4_S0_Ld_12_2, + OPERAND_fld_F4_S0_Ld_12_4, + OPERAND_fld_F4_S0_Ld_12_8, + OPERAND_fld_F4_S0_Ld_15_15, + OPERAND_fld_F4_S0_Ld_31_12, + OPERAND_fld_F4_S0_Ld_31_13, + OPERAND_fld_F4_S0_Ld_31_15, + OPERAND_fld_F4_S0_Ld_31_16, + OPERAND_fld_F4_S0_Ld_31_17, + OPERAND_fld_F4_S0_Ld_31_18, + OPERAND_fld_F4_S0_Ld_31_20, + OPERAND_fld_F4_S0_Ld_31_27, + OPERAND_fld_F4_S0_Ld_31_7, + OPERAND_fld_F4_S0_Ld_31_8, + OPERAND_fld_F4_S0_Ld_31_9, + OPERAND_fld_F4_S0_Ld_3_0, + OPERAND_fld_F4_S0_Ld_6_0, + OPERAND_fld_F4_S0_Ld_6_4, + OPERAND_fld_F4_S0_Ld_7_4, + OPERAND_fld_F4_S1_Ld_12_10, + OPERAND_fld_F4_S1_Ld_12_2, + OPERAND_fld_F4_S1_Ld_12_4, + OPERAND_fld_F4_S1_Ld_12_8, + OPERAND_fld_F4_S1_Ld_23_0, + OPERAND_fld_F4_S1_Ld_23_10, + OPERAND_fld_F4_S1_Ld_23_11, + OPERAND_fld_F4_S1_Ld_23_12, + OPERAND_fld_F4_S1_Ld_23_13, + OPERAND_fld_F4_S1_Ld_23_15, + OPERAND_fld_F4_S1_Ld_23_16, + OPERAND_fld_F4_S1_Ld_23_17, + OPERAND_fld_F4_S1_Ld_23_8, + OPERAND_fld_F4_S1_Ld_23_9, + OPERAND_fld_F4_S1_Ld_3_0, + OPERAND_fld_F4_S1_Ld_3_2, + OPERAND_fld_F4_S1_Ld_4_0, + OPERAND_fld_F4_S1_Ld_4_3, + OPERAND_fld_F4_S1_Ld_4_4, + OPERAND_fld_F4_S1_Ld_7_0, + OPERAND_fld_F4_S1_Ld_7_2, + OPERAND_fld_F4_S1_Ld_7_4, + OPERAND_fld_F4_S1_Ld_7_6, + OPERAND_fld_F4_S1_Ld_7_7, + OPERAND_fld_F4_S2_Mul_32_26, + OPERAND_fld_F4_S2_Mul_32_8, + OPERAND_fld_F4_S2_Mul_3_0, + OPERAND_fld_F4_S2_Mul_7_0, + OPERAND_fld_ivp_sem_multiply_vq, + OPERAND_fld_F4_S3_ALU_0_0, + OPERAND_fld_F4_S3_ALU_14_10, + OPERAND_fld_F4_S3_ALU_14_11, + OPERAND_fld_F4_S3_ALU_14_12, + OPERAND_fld_F4_S3_ALU_14_13, + OPERAND_fld_F4_S3_ALU_14_14, + OPERAND_fld_F4_S3_ALU_14_6, + OPERAND_fld_F4_S3_ALU_14_8, + OPERAND_fld_F4_S3_ALU_19_13, + OPERAND_fld_F4_S3_ALU_19_6, + OPERAND_fld_F4_S3_ALU_19_8, + OPERAND_fld_F4_S3_ALU_24_12, + OPERAND_fld_F4_S3_ALU_24_13, + OPERAND_fld_F4_S3_ALU_24_18, + OPERAND_fld_F4_S3_ALU_24_20, + OPERAND_fld_F4_S3_ALU_24_21, + OPERAND_fld_F4_S3_ALU_31_13, + OPERAND_fld_F4_S3_ALU_31_19, + OPERAND_fld_F4_S3_ALU_31_20, + OPERAND_fld_F4_S3_ALU_31_23, + OPERAND_fld_F4_S3_ALU_31_25, + OPERAND_fld_F4_S3_ALU_31_26, + OPERAND_fld_F4_S3_ALU_31_28, + OPERAND_fld_F4_S3_ALU_31_7, + OPERAND_fld_F4_S3_ALU_31_8, + OPERAND_fld_F4_S3_ALU_3_0, + OPERAND_fld_F4_S3_ALU_3_1, + OPERAND_fld_F4_S3_ALU_3_2, + OPERAND_fld_F4_S3_ALU_3_3, + OPERAND_fld_F4_S3_ALU_6_0, + OPERAND_fld_F4_S3_ALU_7_4, + OPERAND_fld_F4_S3_ALU_7_5, + OPERAND_fld_F4_S3_ALU_9_8, + OPERAND_fld_F5_S0_Base_11_0, + OPERAND_fld_F5_S0_Base_11_8, + OPERAND_fld_F5_S0_Base_11_9, + OPERAND_fld_F5_S0_Base_36_12, + OPERAND_fld_F5_S0_Base_36_13, + OPERAND_fld_F5_S0_Base_36_16, + OPERAND_fld_F5_S0_Base_36_17, + OPERAND_fld_F5_S0_Base_36_18, + OPERAND_fld_F5_S0_Base_36_20, + OPERAND_fld_F5_S0_Base_36_27, + OPERAND_fld_F5_S0_Base_3_0, + OPERAND_fld_F5_S0_Base_3_1, + OPERAND_fld_F5_S0_Base_7_4, + OPERAND_fld_F5_S1_Base_27_12, + OPERAND_fld_F5_S1_Base_27_13, + OPERAND_fld_F5_S1_Base_27_16, + OPERAND_fld_F5_S1_Base_27_17, + OPERAND_fld_F5_S1_Base_27_3, + OPERAND_fld_F5_S1_Base_2_0, + OPERAND_fld_F5_S1_Base_3_0, + OPERAND_fld_F5_S1_Base_7_4, + OPERAND_fld_F5_S2_Base_1_0, + OPERAND_fld_F5_S2_Base_26_12, + OPERAND_fld_F5_S2_Base_26_13, + OPERAND_fld_F5_S2_Base_26_16, + OPERAND_fld_F5_S2_Base_26_2, + OPERAND_fld_F5_S2_Base_26_8, + OPERAND_fld_F5_S2_Base_3_0, + OPERAND_fld_F5_S2_Base_7_4, + OPERAND_fld_F5_S3_Base_0_0, + OPERAND_fld_F5_S3_Base_25_1, + OPERAND_fld_F5_S3_Base_25_16, + OPERAND_fld_F5_S3_Base_25_8, + OPERAND_fld_F11_S0_Ld_1_0, + OPERAND_fld_F11_S0_Ld_23_0, + OPERAND_fld_F11_S0_Ld_23_12, + OPERAND_fld_F11_S0_Ld_23_13, + OPERAND_fld_F11_S0_Ld_23_16, + OPERAND_fld_F11_S0_Ld_23_17, + OPERAND_fld_F11_S0_Ld_23_20, + OPERAND_fld_F11_S0_Ld_23_4, + OPERAND_fld_F11_S0_Ld_3_0, + OPERAND_fld_F11_S0_Ld_7_4, + OPERAND_fld_F11_S1_ALU_12_10, + OPERAND_fld_F11_S1_ALU_12_11, + OPERAND_fld_F11_S1_ALU_12_12, + OPERAND_fld_F11_S1_ALU_12_3, + OPERAND_fld_F11_S1_ALU_12_4, + OPERAND_fld_F11_S1_ALU_12_9, + OPERAND_fld_F11_S1_ALU_15_13, + OPERAND_fld_F11_S1_ALU_15_14, + OPERAND_fld_F11_S1_ALU_15_15, + OPERAND_fld_F11_S1_ALU_15_2, + OPERAND_fld_F11_S1_ALU_22_0, + OPERAND_fld_F11_S1_ALU_22_12, + OPERAND_fld_F11_S1_ALU_22_13, + OPERAND_fld_F11_S1_ALU_22_14, + OPERAND_fld_F11_S1_ALU_22_16, + OPERAND_fld_F11_S1_ALU_22_18, + OPERAND_fld_F11_S1_ALU_3_0, + OPERAND_fld_F11_S1_ALU_7_4, + OPERAND_fld_ivp_sem_ld_st_vrul2, + OPERAND_fld_F11_S2_Mul_11_8, + OPERAND_fld_F11_S2_Mul_13_12, + OPERAND_fld_F11_S2_Mul_13_7, + OPERAND_fld_F11_S2_Mul_22_0, + OPERAND_fld_F11_S2_Mul_22_12, + OPERAND_fld_F11_S2_Mul_22_13, + OPERAND_fld_F11_S2_Mul_22_14, + OPERAND_fld_F11_S2_Mul_22_15, + OPERAND_fld_F11_S2_Mul_22_16, + OPERAND_fld_F11_S2_Mul_22_8, + OPERAND_fld_F11_S2_Mul_3_0, + OPERAND_fld_F11_S2_Mul_3_3, + OPERAND_fld_F11_S2_Mul_4_0, + OPERAND_fld_F11_S2_Mul_7_4, + OPERAND_fld_F11_S2_Mul_7_5, + OPERAND_fld_F11_S3_ALU_0_0, + OPERAND_fld_F11_S3_ALU_14_10, + OPERAND_fld_F11_S3_ALU_14_11, + OPERAND_fld_F11_S3_ALU_14_13, + OPERAND_fld_F11_S3_ALU_14_8, + OPERAND_fld_F11_S3_ALU_25_1, + OPERAND_fld_F11_S3_ALU_25_11, + OPERAND_fld_F11_S3_ALU_25_13, + OPERAND_fld_F11_S3_ALU_25_14, + OPERAND_fld_F11_S3_ALU_25_15, + OPERAND_fld_F11_S3_ALU_25_16, + OPERAND_fld_F11_S3_ALU_25_17, + OPERAND_fld_F11_S3_ALU_25_18, + OPERAND_fld_F11_S3_ALU_25_22, + OPERAND_fld_F11_S3_ALU_25_8, + OPERAND_fld_F11_S3_ALU_3_0, + OPERAND_fld_F11_S3_ALU_3_1, + OPERAND_fld_F11_S3_ALU_7_0, + OPERAND_fld_F11_S3_ALU_7_4, + OPERAND_fld_F11_S3_ALU_9_8, + OPERAND_fld_F11_S3_ALU_9_9, + OPERAND_fld_F11_S4_ALU_24_0, + OPERAND_fld_F11_S4_ALU_24_15, + OPERAND_fld_F11_S4_ALU_24_18, + OPERAND_fld_F11_S4_ALU_9_5, + OPERAND_fld_N1_S0_LdSt_12_0, + OPERAND_fld_N1_S0_LdSt_12_12, + OPERAND_fld_N1_S0_LdSt_12_2, + OPERAND_fld_N1_S0_LdSt_12_4, + OPERAND_fld_N1_S0_LdSt_12_8, + OPERAND_fld_N1_S0_LdSt_15_15, + OPERAND_fld_N1_S0_LdSt_1_0, + OPERAND_fld_N1_S0_LdSt_26_12, + OPERAND_fld_N1_S0_LdSt_26_13, + OPERAND_fld_N1_S0_LdSt_26_15, + OPERAND_fld_N1_S0_LdSt_26_16, + OPERAND_fld_N1_S0_LdSt_26_17, + OPERAND_fld_N1_S0_LdSt_26_18, + OPERAND_fld_N1_S0_LdSt_26_2, + OPERAND_fld_N1_S0_LdSt_26_20, + OPERAND_fld_N1_S0_LdSt_26_4, + OPERAND_fld_N1_S0_LdSt_26_8, + OPERAND_fld_N1_S0_LdSt_26_9, + OPERAND_fld_N1_S0_LdSt_3_0, + OPERAND_fld_N1_S0_LdSt_3_2, + OPERAND_fld_N1_S0_LdSt_7_2, + OPERAND_fld_N1_S0_LdSt_7_4, + OPERAND_fld_N1_S0_LdSt_7_5, + OPERAND_fld_N1_S0_LdSt_7_6, + OPERAND_fld_N1_S1_None_3_0, + OPERAND_fld_N1_S2_Mul_0_0, + OPERAND_fld_N1_S2_Mul_13_9, + OPERAND_fld_N1_S2_Mul_18_14, + OPERAND_fld_N1_S2_Mul_18_6, + OPERAND_fld_N1_S2_Mul_18_9, + OPERAND_fld_N1_S2_Mul_25_1, + OPERAND_fld_N1_S2_Mul_25_12, + OPERAND_fld_N1_S2_Mul_25_14, + OPERAND_fld_N1_S2_Mul_25_19, + OPERAND_fld_N1_S2_Mul_25_21, + OPERAND_fld_N1_S2_Mul_3_0, + OPERAND_fld_N1_S2_Mul_3_3, + OPERAND_fld_N1_S2_Mul_7_4, + OPERAND_fld_N1_S2_Mul_8_4, + OPERAND_fld_N1_S2_Mul_8_8, + OPERAND_fld_N2_S0_LdSt_12_0, + OPERAND_fld_N2_S0_LdSt_12_10, + OPERAND_fld_N2_S0_LdSt_12_11, + OPERAND_fld_N2_S0_LdSt_12_12, + OPERAND_fld_N2_S0_LdSt_12_4, + OPERAND_fld_N2_S0_LdSt_12_8, + OPERAND_fld_N2_S0_LdSt_13_11, + OPERAND_fld_N2_S0_LdSt_15_15, + OPERAND_fld_N2_S0_LdSt_29_10, + OPERAND_fld_N2_S0_LdSt_29_11, + OPERAND_fld_N2_S0_LdSt_29_12, + OPERAND_fld_N2_S0_LdSt_29_13, + OPERAND_fld_N2_S0_LdSt_29_14, + OPERAND_fld_N2_S0_LdSt_29_15, + OPERAND_fld_N2_S0_LdSt_29_16, + OPERAND_fld_N2_S0_LdSt_29_17, + OPERAND_fld_N2_S0_LdSt_29_18, + OPERAND_fld_N2_S0_LdSt_29_20, + OPERAND_fld_N2_S0_LdSt_29_5, + OPERAND_fld_N2_S0_LdSt_29_8, + OPERAND_fld_N2_S0_LdSt_3_0, + OPERAND_fld_N2_S0_LdSt_4_0, + OPERAND_fld_N2_S0_LdSt_4_4, + OPERAND_fld_N2_S0_LdSt_7_4, + OPERAND_fld_N2_S0_LdSt_7_6, + OPERAND_fld_N2_S0_LdSt_8_0, + OPERAND_fld_N2_S0_LdSt_8_4, + OPERAND_fld_N2_S0_LdSt_9_5, + OPERAND_fld_N2_S0_LdSt_9_6, + OPERAND_fld_N2_S1_Ld_12_10, + OPERAND_fld_N2_S1_Ld_12_2, + OPERAND_fld_N2_S1_Ld_12_4, + OPERAND_fld_N2_S1_Ld_12_8, + OPERAND_fld_N2_S1_Ld_1_0, + OPERAND_fld_N2_S1_Ld_26_10, + OPERAND_fld_N2_S1_Ld_26_11, + OPERAND_fld_N2_S1_Ld_26_12, + OPERAND_fld_N2_S1_Ld_26_13, + OPERAND_fld_N2_S1_Ld_26_15, + OPERAND_fld_N2_S1_Ld_26_16, + OPERAND_fld_N2_S1_Ld_26_17, + OPERAND_fld_N2_S1_Ld_26_2, + OPERAND_fld_N2_S1_Ld_26_8, + OPERAND_fld_N2_S1_Ld_26_9, + OPERAND_fld_N2_S1_Ld_3_0, + OPERAND_fld_N2_S1_Ld_3_2, + OPERAND_fld_N2_S1_Ld_4_0, + OPERAND_fld_N2_S1_Ld_4_3, + OPERAND_fld_N2_S1_Ld_4_4, + OPERAND_fld_N2_S1_Ld_7_0, + OPERAND_fld_N2_S1_Ld_7_2, + OPERAND_fld_N2_S1_Ld_7_4, + OPERAND_fld_N2_S1_Ld_7_6, + OPERAND_fld_N2_S1_Ld_7_7, + OPERAND_fld_N0_S0_LdSt_12_0, + OPERAND_fld_N0_S0_LdSt_12_12, + OPERAND_fld_N0_S0_LdSt_12_2, + OPERAND_fld_N0_S0_LdSt_12_4, + OPERAND_fld_N0_S0_LdSt_12_8, + OPERAND_fld_N0_S0_LdSt_22_0, + OPERAND_fld_N0_S0_LdSt_22_12, + OPERAND_fld_N0_S0_LdSt_22_13, + OPERAND_fld_N0_S0_LdSt_22_15, + OPERAND_fld_N0_S0_LdSt_22_16, + OPERAND_fld_N0_S0_LdSt_22_17, + OPERAND_fld_N0_S0_LdSt_3_0, + OPERAND_fld_N0_S0_LdSt_7_4, + OPERAND_fld_N0_S0_LdSt_7_5, + OPERAND_fld_N0_S0_LdSt_7_6, + OPERAND_fld_N0_S1_None_2_0, + OPERAND_fld_N0_S2_None_2_0, + OPERAND_fld_N0_S3_ALU_14_10, + OPERAND_fld_N0_S3_ALU_14_13, + OPERAND_fld_N0_S3_ALU_14_14, + OPERAND_fld_N0_S3_ALU_14_5, + OPERAND_fld_N0_S3_ALU_19_12, + OPERAND_fld_N0_S3_ALU_19_13, + OPERAND_fld_N0_S3_ALU_19_15, + OPERAND_fld_N0_S3_ALU_27_12, + OPERAND_fld_N0_S3_ALU_27_13, + OPERAND_fld_N0_S3_ALU_27_15, + OPERAND_fld_N0_S3_ALU_27_16, + OPERAND_fld_N0_S3_ALU_27_19, + OPERAND_fld_N0_S3_ALU_27_20, + OPERAND_fld_N0_S3_ALU_27_22, + OPERAND_fld_N0_S3_ALU_27_23, + OPERAND_fld_N0_S3_ALU_27_3, + OPERAND_fld_N0_S3_ALU_2_0, + OPERAND_fld_N0_S3_ALU_3_0, + OPERAND_fld_N0_S3_ALU_7_0, + OPERAND_fld_N0_S3_ALU_9_0, + OPERAND_fld_N0_S3_ALU_9_3, + OPERAND_fld_N0_S3_ALU_9_4, + OPERAND_fld_N0_S3_ALU_9_5, + OPERAND_fld_N0_S3_ALU_9_6, + OPERAND_fld_N0_S3_ALU_9_7, + OPERAND_fld_N0_S3_ALU_9_9, + OPERAND_fld_MTK_AndPOPC_c, + OPERAND_fld_MTK_AndPOPC_inB, + OPERAND_fld_MTK_AndPOPC_inA, + OPERAND_fld_MTK_AndPOPC_oData, + OPERAND_fld_F11_S4_ALU_24_16, + OPERAND_fld_F3_S4_ALU_23_16, + OPERAND_fld_iq_tie2apb_inq0_pop_qdata, + OPERAND_fld_iq_tie2apb_inq0_is_ready_is_ready, + OPERAND_fld_Inst_11_8, + OPERAND_fld_iq_tie2apb_inq0_nonblocking_peek_success, + OPERAND_fld_iq_tie2apb_inq0_nonblocking_peek_qdata, + OPERAND_fld_iq_tie2apb_inq0_nonblocking_pop_success, + OPERAND_fld_iq_tie2apb_inq0_nonblocking_pop_qdata, + OPERAND_fld_Inst_23_8, + OPERAND_fld_iq_tie2apb_inq0_blocking_peek_qdata, + OPERAND_fld_Inst_23_12, + OPERAND_fld_oq_tie2apb_outq0_push_read_qaddr, + OPERAND_fld_oq_tie2apb_outq0_push_read_qdata, + OPERAND_fld_oq_tie2apb_outq0_push_write_qaddr, + OPERAND_fld_oq_tie2apb_outq0_push_write_qdata, + OPERAND_fld_oq_tie2apb_outq0_is_ready_is_ready, + OPERAND_fld_Inst_3_0, + OPERAND_fld_Inst_23_16, + OPERAND_fld_oq_tie2apb_outq0_nonblocking_push_read_success, + OPERAND_fld_oq_tie2apb_outq0_nonblocking_push_read_qaddr, + OPERAND_fld_oq_tie2apb_outq0_nonblocking_push_read_qdata, + OPERAND_fld_oq_tie2apb_outq0_nonblocking_push_write_success, + OPERAND_fld_oq_tie2apb_outq0_nonblocking_push_write_qaddr, + OPERAND_fld_oq_tie2apb_outq0_nonblocking_push_write_qdata +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_IVP_REPNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_rep_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_i }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_REPNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_rep_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_i }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_REP2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_rep_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_REP2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELS2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_rep_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELS2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_REPN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_rep_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_REPN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELSN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_rep_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELSN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXT0IB_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' }, + { { OPERAND_imm1_2N }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXT0IB_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NOTB_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NOTB_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ANDB_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ANDB_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ORB_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ORB_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_XORB_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_XORB_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ANDNOTB_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ANDNOTB_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MB_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MB_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRN_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRNI_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_bbe_ltrxnimm }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRNI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LBN_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6bn }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LBN_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LBN_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4bn }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LBN_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SBN_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6bn }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SBN_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SBN_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4bn }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SBN_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX16_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX16_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX16_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX16_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX16_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX16_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX16_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX16_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVBRBV_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVBRBV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVBVBR_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_br }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVBVBR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_JOINB_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_JOINB_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRN_2_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRN_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRN_2I_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_bbe_ltrxn_2imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRN_2I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LBN_2_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6bn_2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LBN_2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LBN_2_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4bn_2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LBN_2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SBN_2_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6bn_2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SBN_2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SBN_2_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4bn_2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SBN_2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX16_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX16_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX16_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX16_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX16_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX16_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX16_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX16_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVA16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVV_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLINX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLINX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLSINX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLSINX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRAINX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRAINX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLINX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLINX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLANX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRANX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_XOR2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_XOR2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AND2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AND2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_OR2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_OR2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NOT2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NOT2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSGNNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSGNNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NSANX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NSANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NSAUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NSAUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LENX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LENX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EQNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EQNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEQNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEQNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LEUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LEUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RBMINNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RBMINNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RBMAXNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RBMAXNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOV2NX8T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOV2NX8T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKL_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKQ_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKQ_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSNX16PACKL_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSNX16PACKL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSNX16PACKQ_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSNX16PACKQ_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8T_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8T_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8T_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8T_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8T_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8T_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8T_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LV2NX8T_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8T_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8T_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8T_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8T_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8T_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8T_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8T_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SV2NX8T_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXUNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXUNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINUNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINUNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXUNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXUNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINUNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINUNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKLT_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKLT_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKQT_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKQT_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDSNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDSNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBSNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBSNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGSNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGSNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LALIGN_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LALIGN_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LALIGN_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LALIGN_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SALIGN_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SALIGN_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SALIGN_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SALIGN_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LA_PP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LA_PP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAPOS_FP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAPOS_FP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MALIGN_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_valignr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MALIGN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ZALIGN_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'o' } +}; + +static xtensa_arg_internal Iclass_IVP_ZALIGN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LA2NX8_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_LA2NX8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SA2NX8_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_SA2NX8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAV2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAV2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAV2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAV2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFLNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFLNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVPINT16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_i_IMM_movint }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVPINT16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVPA16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVPA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULNX16PACKP_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULNX16PACKP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKP_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSNX16PACKP_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSNX16PACKP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKPT_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16PACKPT_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDMOD16U_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8S_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8S_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8U_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8U_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8U_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8U_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8U_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8U_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8U_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8U_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8U_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8U_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8ST_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8ST_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8ST_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8ST_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8ST_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8ST_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8ST_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8ST_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8UT_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8UT_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8UT_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8UT_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8UT_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8UT_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8UT_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVNX8UT_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8UT_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8UT_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8UT_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8UT_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8UT_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8UT_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8UT_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8UT_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAVNX8S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAVNX8S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAVNX8U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAVNX8U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAVNX8U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAVNX8U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LANX8S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_LANX8S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LANX8U_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_LANX8U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SANX8U_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_SANX8U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRACTBL_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRACTBL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRACTBH_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRACTBH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVINT16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_i_IMM_movint }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVINT16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVQINT16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_i_IMM_movint }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVQINT16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVQA16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVQA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVINX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_immmovvi }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVINX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEQNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' } +}; + +static xtensa_arg_internal Iclass_IVP_SEQNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULNX16PACKL_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULNX16PACKL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULNX16PACKQ_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULNX16PACKQ_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAV16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAV16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAVU16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAVU16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRNX16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_i }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX8S_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX8S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX8S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX8S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX8S_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX8S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX8S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSNX8S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8S_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8S_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX8S_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX8S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX8S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX8S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX8S_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX8S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX8S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSNX8S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAVNX8S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAVNX8S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SANX8S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_SANX8S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8ST_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8ST_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8ST_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmb4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8ST_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8ST_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8ST_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8ST_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVNX8ST_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVBA1_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVBA1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAB1_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAB1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NOTB1_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NOTB1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ANDNOTB1_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ANDNOTB1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ORNOTB1_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ORNOTB1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S2NX24LL_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S2NX24LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S2NX24LH_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S2NX24LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S2NX24HL_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S2NX24HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S2NX24HH_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S2NX24HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64SNX48LL_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64SNX48LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64SNX48LH_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64SNX48LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64SNX48HL_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64SNX48HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64SNX48HH_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64SNX48HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT16S2NX24L_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT16S2NX24L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT16S2NX24H_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT16S2NX24H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32SNX48L_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32SNX48L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32SNX48H_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32SNX48H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT16U2NX24H_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT16U2NX24H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32UNX48H_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32UNX48H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64UN_2X96H_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64UN_2X96H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT16U2NX24L_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT16U2NX24L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24U2NX16_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24U2NX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24S2NX16_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24S2NX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S24_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32S24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24U32_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24U32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24UNX32L_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24UNX32L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24UNX32H_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT24UNX32H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32UNX48L_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT32UNX48L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48UNX32L_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48UNX32L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48UNX32_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48UNX32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48SNX32L_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48SNX32L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48SNX32_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48SNX32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64S48_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64S48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48U64_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48U64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48UN_2X64L_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48UN_2X64L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48UN_2X64H_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT48UN_2X64H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64UN_2X96L_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64UN_2X96L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT96UN_2X64_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT96UN_2X64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT96U64_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT96U64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64U96_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_CVT64U96_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LB2N_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6b2n }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LB2N_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LB2N_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4b2n }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LB2N_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SB2N_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6b2n }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SB2N_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SB2N_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4b2n }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SB2N_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTR2N_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTR2N_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTR2NI_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_bbe_ltrx2nimm }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTR2NI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16U_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16U_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16U_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16U_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16U_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16UT_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16UT_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16UT_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16UT_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16UT_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16UT_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16UT_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16UT_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16S_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16S_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16ST_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16ST_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16ST_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16ST_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16ST_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16ST_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16ST_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbre }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LVN_2X16ST_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16U_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16U_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16UT_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16UT_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16U_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16UT_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16UT_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16U_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16U_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16UT_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16UT_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16UT_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16UT_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16S_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16ST_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh6 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16ST_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16ST_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimmh4 }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16ST_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16S_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16ST_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16ST_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16ST_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SVN_2X16ST_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAN_2X16S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_LAN_2X16S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAN_2X16U_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_LAN_2X16U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAN_2X16U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAN_2X16U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAN_2X16S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAN_2X16S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAN_2X16U_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_SAN_2X16U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAN_2X16S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_SAN_2X16S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAVN_2X16S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAVN_2X16S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAVN_2X16U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAVN_2X16U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAVN_2X16U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAVN_2X16U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAVN_2X16S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_uus }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SAVN_2X16S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X16S_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X16S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X16S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X16S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X16S_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X16S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X16S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X16S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X16S_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X16S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X16S_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X16S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X16S_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X16S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X16S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X16S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X32_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X32_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X32_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X32_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X32_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X32_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X32_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSN_2X32_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X32_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X32_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X32_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X32_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X32_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X32_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X32_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SSN_2X32_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RBMINUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RBMINUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RBMAXUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RBMAXUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAX2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAX2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMIN2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMIN2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXUN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMAXUN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINUN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BMINUN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDN_2X32T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDN_2X32T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBN_2X32T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBN_2X32T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADD2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADD2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUB2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUB2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEG2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEG2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MIN2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MIN2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAX2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAX2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LT2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LT2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LE2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LE2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EQ2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EQ2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEQ2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEQ2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LEU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LEU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADD2NX8T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADD2NX8T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUB2NX8T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUB2NX8T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELN_2X32T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SELN_2X32T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFLN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFLN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLIN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm6_31 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLIN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLSIN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm6_31 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLSIN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRAIN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm6_31 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRAIN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLIN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm6_31 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLIN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLAN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLAN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRAN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRAN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLSN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLSN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRSN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRSN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXUN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMAXUN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINUN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RMINUN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDN_2X32T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDN_2X32T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABS2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABS2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSGNSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSGNSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRI2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRI2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRINX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRINX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRIN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm6_31 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRIN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ROTRN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEGN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINUN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MINUN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXUN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MAXUN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSGNN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSGNN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NSAN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NSAN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NSAUN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NSAUN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LEN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LEN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EQN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EQN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEQN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_NEQN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTUN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTUN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LEUN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LEUN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAT2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LAT2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUS2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUS2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULI2NX8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULI2NX8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAI2NX8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAI2NX8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSI2NX8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSI2NX8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAI2NX8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAI2NX8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULI2NR8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULI2NR8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAI2NR8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAI2NR8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSI2NR8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSI2NR8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAI2NR8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAI2NR8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSA2N8XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSA2N8XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUS2N8XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUS2N8XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULA2N8XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULA2N8XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MUL2N8XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MUL2N8XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DSEL2NX8I_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vu }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_slct }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DSEL2NX8I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DSEL2NX8I_H_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_slct_h }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DSEL2NX8I_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DSELNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vu }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DSELNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DSELNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DSELNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_INJBI2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vbr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_i_imm3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_INJBI2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTBI2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_i_imm3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTBI2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVA32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAV32_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAV32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVWW_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVWW_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LS2NX8_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LS2NX8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LS2NX8_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LS2NX8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LS2NX8_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LS2NX8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LS2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LS2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SS2NX8_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SS2NX8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SS2NX8_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SS2NX8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SS2NX8_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SS2NX8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SS2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SS2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LANX8S_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LANX8S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LANX8U_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LANX8U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LA2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LA2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSUBU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSUBU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSUB2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSUB2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVINT8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_i_IMM_movint }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVINT8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVA8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_mov_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVVA8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAVU8_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAVU8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLI2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SLLI2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRAI2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRAI2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLI2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_shift_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_shift_vr }, 'i' }, + { { OPERAND_saimm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SRLI2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKL2NX24_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKL2NX24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVR2NX24_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVR2NX24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRU2NX24_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRU2NX24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKLNX48_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKLNX48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKL2NX24_1_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKL2NX24_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVR2NX24_0_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVR2NX24_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVR2NX24_1_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVR2NX24_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRU2NX24_0_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRU2NX24_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRU2NX24_1_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRU2NX24_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNR2NX24_0_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNR2NX24_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNR2NX24_1_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNR2NX24_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKMNX48_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKMNX48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNX48_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNX48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKS2NX8_0_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKS2NX8_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKS2NX8_1_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKS2NX8_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKSNX16_L_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKSNX16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKSNX16_H_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKSNX16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8I_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_isel }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8I_S0_args[] = { + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vr }, 'i' }, + { { OPERAND_bbe_selimm_S0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8I_S0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8I_S2_args[] = { + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vr }, 'i' }, + { { OPERAND_bbe_selimm_S2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8I_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8I_S4_args[] = { + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vr }, 'i' }, + { { OPERAND_bbe_selimm_S4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8I_S4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8I_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_ishfl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8I_S0_args[] = { + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vr }, 'i' }, + { { OPERAND_bbe_shflimm_S0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8I_S0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8I_S2_args[] = { + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vr }, 'i' }, + { { OPERAND_bbe_shflimm_S2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8I_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8I_S4_args[] = { + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_specialized_seli_vr }, 'i' }, + { { OPERAND_bbe_shflimm_S4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8I_S4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SHFL2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_select_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_select_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_sr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_select_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEL2NX8T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SQZN_args[] = { + { { OPERAND_opnd_ivp_sem_sqz_vt }, 'o' }, + { { OPERAND_arr }, 'o' }, + { { OPERAND_opnd_ivp_sem_sqz_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SQZN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNSQZN_args[] = { + { { OPERAND_opnd_ivp_sem_sqz_vt }, 'o' }, + { { OPERAND_arr }, 'o' }, + { { OPERAND_opnd_ivp_sem_sqz_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNSQZN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MUL2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MUL2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDW2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDW2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWS2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWS2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUS2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUS2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16S_4STEP0_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16S_4STEP0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16S_4STEP_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16S_4STEP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16S_4STEPN_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16S_4STEPN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16U_4STEP0_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16U_4STEP0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16U_4STEP_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16U_4STEP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16U_4STEPN_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVN_2X32X16U_4STEPN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16S_4STEP0_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16S_4STEP0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16S_4STEP_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16S_4STEP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16S_4STEPN_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16S_4STEPN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16U_4STEP0_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16U_4STEP0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16U_4STEP_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16U_4STEP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16U_4STEPN_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16U_4STEPN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16SQ_4STEP0_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16SQ_4STEP0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16Q_4STEP0_args[] = { + { { OPERAND_opnd_ivp_sem_divide_vu }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_divide_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_divide_lane_ctrl }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_DIVNX16Q_4STEP0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUAN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUAN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUAN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUAN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUAHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUAHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUAHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUAHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULAN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUAN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUAN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSAN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUAN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUAN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUSHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUSHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSSHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSSHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUSHN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUSHN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUSN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUSN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSSN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSSN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUSN_2X16X32_0_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUSN_2X16X32_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUSN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUSN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSSN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSSN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUSN_2X16X32_1_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULSUSN_2X16X32_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKLN_2X96_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKLN_2X96_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKHN_2X64W_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKHN_2X64W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRN_2X64W_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRN_2X64W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNRN_2X64W_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNRN_2X64W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNX48_0_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNX48_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNX48_1_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNX48_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNRNX48_0_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNRNX48_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNRNX48_1_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNRNX48_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNRNX48_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNRNX48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNR2NX24_args[] = { + { { OPERAND_opnd_ivp_sem_wvec_pack_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_wvr }, 'i' }, + { { OPERAND_opnd_ivp_sem_wvec_pack_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_PACKVRNR2NX24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_L2A4NX8_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul2 }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_L2A4NX8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_L2AU2NX8_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_opnd_ivp_sem_ld_st_uul }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_IVP_L2AU2NX8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_L2U2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrul }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_L2U2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGRU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGRU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADD2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADD2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADD2NX8T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADD2NX8T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDUNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDUNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDU2NX8T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDU2NX8T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRS2N_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRS2N_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRSN_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRSN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRSN_2_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LTRSN_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEQ2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' } +}; + +static xtensa_arg_internal Iclass_IVP_SEQ2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SEQN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_mov_vt }, 'o' } +}; + +static xtensa_arg_internal Iclass_IVP_SEQN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRN_2X32_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKU2NX8_0_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKU2NX8_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKU2NX8_1_args[] = { + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_unpack_wvec_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_UNPKU2NX8_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BADDNORMNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BADDNORMNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BSUBNORMNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_BSUBNORMNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDSNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_reduce_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_reduce_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RADDSNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ORNOTB_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ORNOTB_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTR2NX8_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTR2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRVRN_2X32_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_rep_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_EXTRVRN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAV8_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_rep_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVAV8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPN16XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPN16XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPAN16XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPAN16XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPN16XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPN16XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPAN16XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPAN16XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULP2N8XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULP2N8XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPA2N8XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPA2N8XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSP2N8XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSP2N8XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPA2N8XR16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPA2N8XR16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUPNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUPNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUPANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUPANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULP2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULP2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSP2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSP2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUP2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUP2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUPA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUUPA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPI2NR8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPI2NR8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPAI2NR8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULPAI2NR8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPI2NR8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPI2NR8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPAI2NR8X16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSPAI2NR8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULQ2N8XR8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULQ2N8XR8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULQA2N8XR8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULQA2N8XR8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSQ2N8XR8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSQ2N8XR8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSQA2N8XR8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vq }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vp }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUSQA2N8XR8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MUL4T2N8XR8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MUL4T2N8XR8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MUL4TA2N8XR8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MUL4TA2N8XR8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUS4T2N8XR8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUS4T2N8XR8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUS4TA2N8XR8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MULUS4TA2N8XR8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ADDWUSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWUANX16_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWUANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBW2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBW2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWU2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'o' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWU2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWUA2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_multiply_wvt }, 'm' }, + { { OPERAND_opnd_ivp_sem_multiply_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_multiply_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SUBWUA2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RANDB2N_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RANDB2N_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RORB2N_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RORB2N_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RANDBN_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RANDBN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RORBN_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RORBN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RANDBN_2_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RANDBN_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RORBN_2_args[] = { + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vbool_alu_ltr_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_RORBN_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVG2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVG2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGR2NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGR2NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGRNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGRNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGRUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_AVGRUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERANX8U_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERANX8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERANX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERANX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERAN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERAN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERANX8UT_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERANX8UT_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERANX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERANX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERAN_2X32T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERAN_2X32T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERDNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERDNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERDNX8S_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERDNX8S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERD2NX8_L_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERD2NX8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERD2NX8_H_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vt }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_GATHERD2NX8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVGATHERD_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_gt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_MOVGATHERD_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERNX8U_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERNX8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTER2NX8_L_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTER2NX8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTER2NX8_H_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTER2NX8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERN_2X32_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERN_2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERNX8UT_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERNX8UT_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTER2NX8T_L_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTER2NX8T_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTER2NX8T_H_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTER2NX8T_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERNX16T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERNX16T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERN_2X32T_args[] = { + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_scatter_gather_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_SCATTERN_2X32T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTEQZ4NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_histogram_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_arr }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTEQZ4NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTEQ4NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_histogram_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_arr }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTEQ4NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTEQMZ4NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_histogram_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_arr }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTEQMZ4NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTEQM4NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_histogram_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_arr }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTEQM4NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTLEZ4NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_histogram_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_arr }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTLEZ4NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTLE4NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_histogram_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_arr }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTLE4NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTLEMZ4NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_histogram_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_arr }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTLEMZ4NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTLEM4NX8_args[] = { + { { OPERAND_opnd_ivp_sem_vec_histogram_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_arr }, 'm' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vr }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vbs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_histogram_vbr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_COUNTLEM4NX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSR2NX8_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSR2NX8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSR2NX8_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSR2NX8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSR2NX8_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSR2NX8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSR2NX8_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSR2NX8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRNX16_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRNX16_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRNX16_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRNX16_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRNX16_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRNX16_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRNX16_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRNX16_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRN_2X32_I_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm6x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRN_2X32_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRN_2X32_IP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ivp_sem_ld_st_i_bimm4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRN_2X32_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRN_2X32_X_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRN_2X32_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRN_2X32_XP_args[] = { + { { OPERAND_opnd_ivp_sem_ld_st_vrr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_LSRN_2X32_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSUBNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSUBNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSUBUNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSUBUNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSSUBNX16_args[] = { + { { OPERAND_opnd_ivp_sem_vec_alu_vt }, 'o' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vs }, 'i' }, + { { OPERAND_opnd_ivp_sem_vec_alu_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_IVP_ABSSSUBNX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSRING }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { OPERAND_ars_entry }, 's' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm12x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { OPERAND_simm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ai4const }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_simm7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8x256 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_label12 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_const16_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_imm16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sae }, 'i' }, + { { OPERAND_op2p1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { OPERAND_soffset }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_uimm16x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_simm12b }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ex_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ex_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_getex_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_getex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clrex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimmrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { OPERAND_sas }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_msalp32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sargt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_stateArgs[] = { + { { STATE_MEMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_stateArgs[] = { + { { STATE_MEMCTL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_stateArgs[] = { + { { STATE_MEMCTL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpucfg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpucfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUNUMENTRIES }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpucfg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpucfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUNUMENTRIES }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_gserr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_gserr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_gserr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_gserr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_gserr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_gserr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul16_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32h_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { OPERAND_imms }, 'i' }, + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'i' }, + { { STATE_DBREAKC_SG0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_DBREAKC_SG0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_DBREAKC_SG0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_bs }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { + { { OPERAND_bs }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_brall }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_brall }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_brall }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cacheadrdis_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cacheadrdis_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CACHEADRDIS }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cacheadrdis_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cacheadrdis_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CACHEADRDIS }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cacheadrdis_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cacheadrdis_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CACHEADRDIS }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb0_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wptlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wptlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpuenb_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpuenb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpuenb_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpuenb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_mpuenb_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_mpuenb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { + { { STATE_ERACCESS }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_ERI_RAW_INTERLOCK }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = { + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { + { { STATE_ERACCESS }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_ERI_RAW_INTERLOCK }, 'o' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = { + INTERFACE_ERI_WR_In, + INTERFACE_ERI_WR_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_1_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_2_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_3_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_MTK_AndPOPC_args[] = { + { { OPERAND_opnd_MTK_AndPOPC_oData }, 'o' }, + { { OPERAND_opnd_MTK_AndPOPC_inA }, 'i' }, + { { OPERAND_opnd_MTK_AndPOPC_inB }, 'i' }, + { { OPERAND_opnd_MTK_AndPOPC_c }, 'i' } +}; + +static xtensa_arg_internal Iclass_MTK_AndPOPC_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iq_tie2apb_inq0_pop_args[] = { + { { OPERAND_opnd_iq_tie2apb_inq0_pop_qdata }, 'o' } +}; + +static xtensa_arg_internal Iclass_iq_tie2apb_inq0_pop_stateArgs[] = { + { { STATE_APB_PIPE }, 'm' } +}; + +static xtensa_interface Iclass_iq_tie2apb_inq0_pop_intfArgs[] = { + INTERFACE_iq_tie2apb_inq0 +}; + +static xtensa_arg_internal Iclass_iq_tie2apb_inq0_is_ready_args[] = { + { { OPERAND_opnd_iq_tie2apb_inq0_is_ready_is_ready }, 'o' } +}; + +static xtensa_interface Iclass_iq_tie2apb_inq0_is_ready_intfArgs[] = { + INTERFACE_iq_tie2apb_inq0_NOTRDY +}; + +static xtensa_arg_internal Iclass_iq_tie2apb_inq0_nonblocking_peek_args[] = { + { { OPERAND_opnd_iq_tie2apb_inq0_nonblocking_peek_qdata }, 'm' }, + { { OPERAND_opnd_iq_tie2apb_inq0_nonblocking_peek_success }, 'o' } +}; + +static xtensa_interface Iclass_iq_tie2apb_inq0_nonblocking_peek_intfArgs[] = { + INTERFACE_iq_tie2apb_inq0, + INTERFACE_iq_tie2apb_inq0_NOTRDY, + INTERFACE_iq_tie2apb_inq0_KILL +}; + +static xtensa_arg_internal Iclass_iq_tie2apb_inq0_nonblocking_pop_args[] = { + { { OPERAND_opnd_iq_tie2apb_inq0_nonblocking_pop_qdata }, 'm' }, + { { OPERAND_opnd_iq_tie2apb_inq0_nonblocking_pop_success }, 'o' } +}; + +static xtensa_arg_internal Iclass_iq_tie2apb_inq0_nonblocking_pop_stateArgs[] = { + { { STATE_APB_PIPE }, 'm' } +}; + +static xtensa_interface Iclass_iq_tie2apb_inq0_nonblocking_pop_intfArgs[] = { + INTERFACE_iq_tie2apb_inq0, + INTERFACE_iq_tie2apb_inq0_NOTRDY, + INTERFACE_iq_tie2apb_inq0_KILL +}; + +static xtensa_arg_internal Iclass_iq_tie2apb_inq0_blocking_peek_args[] = { + { { OPERAND_opnd_iq_tie2apb_inq0_blocking_peek_qdata }, 'o' } +}; + +static xtensa_interface Iclass_iq_tie2apb_inq0_blocking_peek_intfArgs[] = { + INTERFACE_iq_tie2apb_inq0, + INTERFACE_iq_tie2apb_inq0_KILL, + INTERFACE_iq_tie2apb_inq0_NOTRDY +}; + +static xtensa_arg_internal Iclass_oq_tie2apb_outq0_push_read_args[] = { + { { OPERAND_opnd_oq_tie2apb_outq0_push_read_qdata }, 'i' }, + { { OPERAND_opnd_oq_tie2apb_outq0_push_read_qaddr }, 'i' } +}; + +static xtensa_arg_internal Iclass_oq_tie2apb_outq0_push_read_stateArgs[] = { + { { STATE_APB_PIPE }, 'm' } +}; + +static xtensa_interface Iclass_oq_tie2apb_outq0_push_read_intfArgs[] = { + INTERFACE_oq_tie2apb_outq0 +}; + +static xtensa_arg_internal Iclass_oq_tie2apb_outq0_push_write_args[] = { + { { OPERAND_opnd_oq_tie2apb_outq0_push_write_qdata }, 'i' }, + { { OPERAND_opnd_oq_tie2apb_outq0_push_write_qaddr }, 'i' } +}; + +static xtensa_arg_internal Iclass_oq_tie2apb_outq0_push_write_stateArgs[] = { + { { STATE_APB_PIPE }, 'm' } +}; + +static xtensa_interface Iclass_oq_tie2apb_outq0_push_write_intfArgs[] = { + INTERFACE_oq_tie2apb_outq0 +}; + +static xtensa_arg_internal Iclass_oq_tie2apb_outq0_is_ready_args[] = { + { { OPERAND_opnd_oq_tie2apb_outq0_is_ready_is_ready }, 'o' } +}; + +static xtensa_interface Iclass_oq_tie2apb_outq0_is_ready_intfArgs[] = { + INTERFACE_oq_tie2apb_outq0_NOTRDY +}; + +static xtensa_arg_internal Iclass_oq_tie2apb_outq0_nonblocking_push_read_args[] = { + { { OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_read_qdata }, 'i' }, + { { OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_read_qaddr }, 'i' }, + { { OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_read_success }, 'o' } +}; + +static xtensa_arg_internal Iclass_oq_tie2apb_outq0_nonblocking_push_read_stateArgs[] = { + { { STATE_APB_PIPE }, 'm' } +}; + +static xtensa_interface Iclass_oq_tie2apb_outq0_nonblocking_push_read_intfArgs[] = { + INTERFACE_oq_tie2apb_outq0, + INTERFACE_oq_tie2apb_outq0_NOTRDY, + INTERFACE_oq_tie2apb_outq0_KILL +}; + +static xtensa_arg_internal Iclass_oq_tie2apb_outq0_nonblocking_push_write_args[] = { + { { OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_write_qdata }, 'i' }, + { { OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_write_qaddr }, 'i' }, + { { OPERAND_opnd_oq_tie2apb_outq0_nonblocking_push_write_success }, 'o' } +}; + +static xtensa_arg_internal Iclass_oq_tie2apb_outq0_nonblocking_push_write_stateArgs[] = { + { { STATE_APB_PIPE }, 'm' } +}; + +static xtensa_interface Iclass_oq_tie2apb_outq0_nonblocking_push_write_intfArgs[] = { + INTERFACE_oq_tie2apb_outq0, + INTERFACE_oq_tie2apb_outq0_NOTRDY, + INTERFACE_oq_tie2apb_outq0_KILL +}; + +static xtensa_arg_internal Iclass_rur_apb_pipe_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_apb_pipe_stateArgs[] = { + { { STATE_APB_PIPE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_apb_pipe_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_apb_pipe_stateArgs[] = { + { { STATE_APB_PIPE }, 'o' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 3, Iclass_IVP_REPNX16_args, + 1, Iclass_IVP_REPNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SELSNX16_args, + 1, Iclass_IVP_SELSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_REP2NX8_args, + 1, Iclass_IVP_REP2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SELS2NX8_args, + 1, Iclass_IVP_SELS2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_REPN_2X32_args, + 1, Iclass_IVP_REPN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SELSN_2X32_args, + 1, Iclass_IVP_SELSN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_EXT0IB_args, + 1, Iclass_IVP_EXT0IB_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NOTB_args, + 1, Iclass_IVP_NOTB_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ANDB_args, + 1, Iclass_IVP_ANDB_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ORB_args, + 1, Iclass_IVP_ORB_stateArgs, 0, 0 }, + { 3, Iclass_IVP_XORB_args, + 1, Iclass_IVP_XORB_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ANDNOTB_args, + 1, Iclass_IVP_ANDNOTB_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MB_args, + 1, Iclass_IVP_MB_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LTRN_args, + 1, Iclass_IVP_LTRN_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LTRNI_args, + 1, Iclass_IVP_LTRNI_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LBN_I_args, + 1, Iclass_IVP_LBN_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LBN_IP_args, + 1, Iclass_IVP_LBN_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SBN_I_args, + 1, Iclass_IVP_SBN_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SBN_IP_args, + 1, Iclass_IVP_SBN_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSNX16_I_args, + 1, Iclass_IVP_LSNX16_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSNX16_IP_args, + 1, Iclass_IVP_LSNX16_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSNX16_X_args, + 1, Iclass_IVP_LSNX16_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSNX16_XP_args, + 1, Iclass_IVP_LSNX16_XP_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVBRBV_args, + 1, Iclass_IVP_MOVBRBV_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVBVBR_args, + 1, Iclass_IVP_MOVBVBR_stateArgs, 0, 0 }, + { 3, Iclass_IVP_JOINB_args, + 1, Iclass_IVP_JOINB_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LTRN_2_args, + 1, Iclass_IVP_LTRN_2_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LTRN_2I_args, + 1, Iclass_IVP_LTRN_2I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LBN_2_I_args, + 1, Iclass_IVP_LBN_2_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LBN_2_IP_args, + 1, Iclass_IVP_LBN_2_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SBN_2_I_args, + 1, Iclass_IVP_SBN_2_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SBN_2_IP_args, + 1, Iclass_IVP_SBN_2_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LV2NX8_I_args, + 1, Iclass_IVP_LV2NX8_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LV2NX8_IP_args, + 1, Iclass_IVP_LV2NX8_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LV2NX8_X_args, + 1, Iclass_IVP_LV2NX8_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LV2NX8_XP_args, + 1, Iclass_IVP_LV2NX8_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SV2NX8_I_args, + 1, Iclass_IVP_SV2NX8_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SV2NX8_IP_args, + 1, Iclass_IVP_SV2NX8_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SV2NX8_X_args, + 1, Iclass_IVP_SV2NX8_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SV2NX8_XP_args, + 1, Iclass_IVP_SV2NX8_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSNX16_I_args, + 1, Iclass_IVP_SSNX16_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSNX16_IP_args, + 1, Iclass_IVP_SSNX16_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSNX16_X_args, + 1, Iclass_IVP_SSNX16_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSNX16_XP_args, + 1, Iclass_IVP_SSNX16_XP_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVVA16_args, + 1, Iclass_IVP_MOVVA16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVVV_args, + 1, Iclass_IVP_MOVVV_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLLINX16_args, + 1, Iclass_IVP_SLLINX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLSINX16_args, + 1, Iclass_IVP_SLSINX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRAINX16_args, + 1, Iclass_IVP_SRAINX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRLINX16_args, + 1, Iclass_IVP_SRLINX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLLNX16_args, + 1, Iclass_IVP_SLLNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRLNX16_args, + 1, Iclass_IVP_SRLNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLANX16_args, + 1, Iclass_IVP_SLANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRANX16_args, + 1, Iclass_IVP_SRANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLSNX16_args, + 1, Iclass_IVP_SLSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRSNX16_args, + 1, Iclass_IVP_SRSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_XOR2NX8_args, + 1, Iclass_IVP_XOR2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_AND2NX8_args, + 1, Iclass_IVP_AND2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_OR2NX8_args, + 1, Iclass_IVP_OR2NX8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NOT2NX8_args, + 1, Iclass_IVP_NOT2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDNX16_args, + 1, Iclass_IVP_ADDNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBNX16_args, + 1, Iclass_IVP_SUBNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NEGNX16_args, + 1, Iclass_IVP_NEGNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MINNX16_args, + 1, Iclass_IVP_MINNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MINUNX16_args, + 1, Iclass_IVP_MINUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MAXNX16_args, + 1, Iclass_IVP_MAXNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MAXUNX16_args, + 1, Iclass_IVP_MAXUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSGNNX16_args, + 1, Iclass_IVP_MULSGNNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NSANX16_args, + 1, Iclass_IVP_NSANX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NSAUNX16_args, + 1, Iclass_IVP_NSAUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LTNX16_args, + 1, Iclass_IVP_LTNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LENX16_args, + 1, Iclass_IVP_LENX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_EQNX16_args, + 1, Iclass_IVP_EQNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_NEQNX16_args, + 1, Iclass_IVP_NEQNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LTUNX16_args, + 1, Iclass_IVP_LTUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LEUNX16_args, + 1, Iclass_IVP_LEUNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RADDNX16_args, + 1, Iclass_IVP_RADDNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RMAXNX16_args, + 1, Iclass_IVP_RMAXNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RMINNX16_args, + 1, Iclass_IVP_RMINNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RMAXUNX16_args, + 1, Iclass_IVP_RMAXUNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RMINUNX16_args, + 1, Iclass_IVP_RMINUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RBMINNX16_args, + 1, Iclass_IVP_RBMINNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RBMAXNX16_args, + 1, Iclass_IVP_RBMAXNX16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMAXNX16_args, + 1, Iclass_IVP_BMAXNX16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMINNX16_args, + 1, Iclass_IVP_BMINNX16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MOV2NX8T_args, + 1, Iclass_IVP_MOV2NX8T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULANX16PACKL_args, + 1, Iclass_IVP_MULANX16PACKL_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULANX16PACKQ_args, + 1, Iclass_IVP_MULANX16PACKQ_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSNX16PACKL_args, + 1, Iclass_IVP_MULSNX16PACKL_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSNX16PACKQ_args, + 1, Iclass_IVP_MULSNX16PACKQ_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDSNX16_args, + 1, Iclass_IVP_ADDSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBSNX16_args, + 1, Iclass_IVP_SUBSNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NEGSNX16_args, + 1, Iclass_IVP_NEGSNX16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LV2NX8T_I_args, + 1, Iclass_IVP_LV2NX8T_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LV2NX8T_IP_args, + 1, Iclass_IVP_LV2NX8T_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LV2NX8T_X_args, + 1, Iclass_IVP_LV2NX8T_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LV2NX8T_XP_args, + 1, Iclass_IVP_LV2NX8T_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SV2NX8T_I_args, + 1, Iclass_IVP_SV2NX8T_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SV2NX8T_IP_args, + 1, Iclass_IVP_SV2NX8T_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SV2NX8T_X_args, + 1, Iclass_IVP_SV2NX8T_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SV2NX8T_XP_args, + 1, Iclass_IVP_SV2NX8T_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RADDNX16T_args, + 1, Iclass_IVP_RADDNX16T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RMAXNX16T_args, + 1, Iclass_IVP_RMAXNX16T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RMINNX16T_args, + 1, Iclass_IVP_RMINNX16T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RMAXUNX16T_args, + 1, Iclass_IVP_RMAXUNX16T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RMINUNX16T_args, + 1, Iclass_IVP_RMINUNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_ADDNX16T_args, + 1, Iclass_IVP_ADDNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SUBNX16T_args, + 1, Iclass_IVP_SUBNX16T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_NEGNX16T_args, + 1, Iclass_IVP_NEGNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MAXNX16T_args, + 1, Iclass_IVP_MAXNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MINNX16T_args, + 1, Iclass_IVP_MINNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MAXUNX16T_args, + 1, Iclass_IVP_MAXUNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MINUNX16T_args, + 1, Iclass_IVP_MINUNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULANX16PACKLT_args, + 1, Iclass_IVP_MULANX16PACKLT_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULANX16PACKQT_args, + 1, Iclass_IVP_MULANX16PACKQT_stateArgs, 0, 0 }, + { 4, Iclass_IVP_ADDSNX16T_args, + 1, Iclass_IVP_ADDSNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SUBSNX16T_args, + 1, Iclass_IVP_SUBSNX16T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_NEGSNX16T_args, + 1, Iclass_IVP_NEGSNX16T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LALIGN_I_args, + 1, Iclass_IVP_LALIGN_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LALIGN_IP_args, + 1, Iclass_IVP_LALIGN_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SALIGN_I_args, + 1, Iclass_IVP_SALIGN_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SALIGN_IP_args, + 1, Iclass_IVP_SALIGN_IP_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LA_PP_args, + 1, Iclass_IVP_LA_PP_stateArgs, 0, 0 }, + { 2, Iclass_IVP_SAPOS_FP_args, + 1, Iclass_IVP_SAPOS_FP_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MALIGN_args, + 1, Iclass_IVP_MALIGN_stateArgs, 0, 0 }, + { 1, Iclass_IVP_ZALIGN_args, + 1, Iclass_IVP_ZALIGN_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LA2NX8_IP_args, + 1, Iclass_IVP_LA2NX8_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SA2NX8_IP_args, + 1, Iclass_IVP_SA2NX8_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LAV2NX8_XP_args, + 1, Iclass_IVP_LAV2NX8_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SAV2NX8_XP_args, + 1, Iclass_IVP_SAV2NX8_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SELNX16_args, + 1, Iclass_IVP_SELNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SHFLNX16_args, + 1, Iclass_IVP_SHFLNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVPINT16_args, + 1, Iclass_IVP_MOVPINT16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVPA16_args, + 1, Iclass_IVP_MOVPA16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULNX16PACKP_args, + 1, Iclass_IVP_MULNX16PACKP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULANX16PACKP_args, + 1, Iclass_IVP_MULANX16PACKP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSNX16PACKP_args, + 1, Iclass_IVP_MULSNX16PACKP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULANX16PACKPT_args, + 1, Iclass_IVP_MULANX16PACKPT_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDMOD16U_args, + 0, 0, 0, 0 }, + { 3, Iclass_IVP_LVNX8S_I_args, + 1, Iclass_IVP_LVNX8S_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVNX8S_IP_args, + 1, Iclass_IVP_LVNX8S_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVNX8S_X_args, + 1, Iclass_IVP_LVNX8S_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVNX8S_XP_args, + 1, Iclass_IVP_LVNX8S_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVNX8U_I_args, + 1, Iclass_IVP_LVNX8U_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVNX8U_IP_args, + 1, Iclass_IVP_LVNX8U_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVNX8U_X_args, + 1, Iclass_IVP_LVNX8U_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVNX8U_XP_args, + 1, Iclass_IVP_LVNX8U_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVNX8U_I_args, + 1, Iclass_IVP_SVNX8U_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVNX8U_IP_args, + 1, Iclass_IVP_SVNX8U_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVNX8U_X_args, + 1, Iclass_IVP_SVNX8U_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVNX8U_XP_args, + 1, Iclass_IVP_SVNX8U_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVNX8ST_I_args, + 1, Iclass_IVP_LVNX8ST_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVNX8ST_IP_args, + 1, Iclass_IVP_LVNX8ST_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVNX8ST_X_args, + 1, Iclass_IVP_LVNX8ST_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVNX8ST_XP_args, + 1, Iclass_IVP_LVNX8ST_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVNX8UT_I_args, + 1, Iclass_IVP_LVNX8UT_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVNX8UT_IP_args, + 1, Iclass_IVP_LVNX8UT_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVNX8UT_X_args, + 1, Iclass_IVP_LVNX8UT_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVNX8UT_XP_args, + 1, Iclass_IVP_LVNX8UT_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVNX8UT_I_args, + 1, Iclass_IVP_SVNX8UT_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVNX8UT_IP_args, + 1, Iclass_IVP_SVNX8UT_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVNX8UT_X_args, + 1, Iclass_IVP_SVNX8UT_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVNX8UT_XP_args, + 1, Iclass_IVP_SVNX8UT_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LAVNX8S_XP_args, + 1, Iclass_IVP_LAVNX8S_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LAVNX8U_XP_args, + 1, Iclass_IVP_LAVNX8U_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SAVNX8U_XP_args, + 1, Iclass_IVP_SAVNX8U_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LANX8S_IP_args, + 1, Iclass_IVP_LANX8S_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LANX8U_IP_args, + 1, Iclass_IVP_LANX8U_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SANX8U_IP_args, + 1, Iclass_IVP_SANX8U_IP_stateArgs, 0, 0 }, + { 2, Iclass_IVP_EXTRACTBL_args, + 1, Iclass_IVP_EXTRACTBL_stateArgs, 0, 0 }, + { 2, Iclass_IVP_EXTRACTBH_args, + 1, Iclass_IVP_EXTRACTBH_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVVINT16_args, + 1, Iclass_IVP_MOVVINT16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVQINT16_args, + 1, Iclass_IVP_MOVQINT16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVQA16_args, + 1, Iclass_IVP_MOVQA16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVVINX16_args, + 1, Iclass_IVP_MOVVINX16_stateArgs, 0, 0 }, + { 1, Iclass_IVP_SEQNX16_args, + 1, Iclass_IVP_SEQNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULNX16PACKL_args, + 1, Iclass_IVP_MULNX16PACKL_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULNX16PACKQ_args, + 1, Iclass_IVP_MULNX16PACKQ_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVAV16_args, + 1, Iclass_IVP_MOVAV16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVAVU16_args, + 1, Iclass_IVP_MOVAVU16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_EXTRNX16_args, + 1, Iclass_IVP_EXTRNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSNX8S_I_args, + 1, Iclass_IVP_LSNX8S_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSNX8S_IP_args, + 1, Iclass_IVP_LSNX8S_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSNX8S_X_args, + 1, Iclass_IVP_LSNX8S_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSNX8S_XP_args, + 1, Iclass_IVP_LSNX8S_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVNX8S_I_args, + 1, Iclass_IVP_SVNX8S_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVNX8S_IP_args, + 1, Iclass_IVP_SVNX8S_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVNX8S_X_args, + 1, Iclass_IVP_SVNX8S_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVNX8S_XP_args, + 1, Iclass_IVP_SVNX8S_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSNX8S_I_args, + 1, Iclass_IVP_SSNX8S_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSNX8S_IP_args, + 1, Iclass_IVP_SSNX8S_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSNX8S_X_args, + 1, Iclass_IVP_SSNX8S_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSNX8S_XP_args, + 1, Iclass_IVP_SSNX8S_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SAVNX8S_XP_args, + 1, Iclass_IVP_SAVNX8S_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SANX8S_IP_args, + 1, Iclass_IVP_SANX8S_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVNX8ST_I_args, + 1, Iclass_IVP_SVNX8ST_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVNX8ST_IP_args, + 1, Iclass_IVP_SVNX8ST_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVNX8ST_X_args, + 1, Iclass_IVP_SVNX8ST_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVNX8ST_XP_args, + 1, Iclass_IVP_SVNX8ST_XP_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVBA1_args, + 1, Iclass_IVP_MOVBA1_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVAB1_args, + 1, Iclass_IVP_MOVAB1_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NOTB1_args, + 1, Iclass_IVP_NOTB1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ANDNOTB1_args, + 1, Iclass_IVP_ANDNOTB1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ORNOTB1_args, + 1, Iclass_IVP_ORNOTB1_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT32S2NX24LL_args, + 1, Iclass_IVP_CVT32S2NX24LL_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT32S2NX24LH_args, + 1, Iclass_IVP_CVT32S2NX24LH_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT32S2NX24HL_args, + 1, Iclass_IVP_CVT32S2NX24HL_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT32S2NX24HH_args, + 1, Iclass_IVP_CVT32S2NX24HH_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT64SNX48LL_args, + 1, Iclass_IVP_CVT64SNX48LL_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT64SNX48LH_args, + 1, Iclass_IVP_CVT64SNX48LH_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT64SNX48HL_args, + 1, Iclass_IVP_CVT64SNX48HL_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT64SNX48HH_args, + 1, Iclass_IVP_CVT64SNX48HH_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT16S2NX24L_args, + 1, Iclass_IVP_CVT16S2NX24L_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT16S2NX24H_args, + 1, Iclass_IVP_CVT16S2NX24H_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT32SNX48L_args, + 1, Iclass_IVP_CVT32SNX48L_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT32SNX48H_args, + 1, Iclass_IVP_CVT32SNX48H_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT16U2NX24H_args, + 1, Iclass_IVP_CVT16U2NX24H_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT32UNX48H_args, + 1, Iclass_IVP_CVT32UNX48H_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT64UN_2X96H_args, + 1, Iclass_IVP_CVT64UN_2X96H_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT16U2NX24L_args, + 1, Iclass_IVP_CVT16U2NX24L_stateArgs, 0, 0 }, + { 3, Iclass_IVP_CVT24U2NX16_args, + 1, Iclass_IVP_CVT24U2NX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_CVT24S2NX16_args, + 1, Iclass_IVP_CVT24S2NX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT32S24_args, + 1, Iclass_IVP_CVT32S24_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT24U32_args, + 1, Iclass_IVP_CVT24U32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_CVT24UNX32L_args, + 1, Iclass_IVP_CVT24UNX32L_stateArgs, 0, 0 }, + { 3, Iclass_IVP_CVT24UNX32H_args, + 1, Iclass_IVP_CVT24UNX32H_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT32UNX48L_args, + 1, Iclass_IVP_CVT32UNX48L_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT48UNX32L_args, + 1, Iclass_IVP_CVT48UNX32L_stateArgs, 0, 0 }, + { 3, Iclass_IVP_CVT48UNX32_args, + 1, Iclass_IVP_CVT48UNX32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT48SNX32L_args, + 1, Iclass_IVP_CVT48SNX32L_stateArgs, 0, 0 }, + { 3, Iclass_IVP_CVT48SNX32_args, + 1, Iclass_IVP_CVT48SNX32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT64S48_args, + 1, Iclass_IVP_CVT64S48_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT48U64_args, + 1, Iclass_IVP_CVT48U64_stateArgs, 0, 0 }, + { 3, Iclass_IVP_CVT48UN_2X64L_args, + 1, Iclass_IVP_CVT48UN_2X64L_stateArgs, 0, 0 }, + { 3, Iclass_IVP_CVT48UN_2X64H_args, + 1, Iclass_IVP_CVT48UN_2X64H_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT64UN_2X96L_args, + 1, Iclass_IVP_CVT64UN_2X96L_stateArgs, 0, 0 }, + { 3, Iclass_IVP_CVT96UN_2X64_args, + 1, Iclass_IVP_CVT96UN_2X64_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT96U64_args, + 1, Iclass_IVP_CVT96U64_stateArgs, 0, 0 }, + { 2, Iclass_IVP_CVT64U96_args, + 1, Iclass_IVP_CVT64U96_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LB2N_I_args, + 1, Iclass_IVP_LB2N_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LB2N_IP_args, + 1, Iclass_IVP_LB2N_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SB2N_I_args, + 1, Iclass_IVP_SB2N_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SB2N_IP_args, + 1, Iclass_IVP_SB2N_IP_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LTR2N_args, + 1, Iclass_IVP_LTR2N_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LTR2NI_args, + 1, Iclass_IVP_LTR2NI_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVN_2X16U_I_args, + 1, Iclass_IVP_LVN_2X16U_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVN_2X16U_IP_args, + 1, Iclass_IVP_LVN_2X16U_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVN_2X16U_X_args, + 1, Iclass_IVP_LVN_2X16U_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVN_2X16U_XP_args, + 1, Iclass_IVP_LVN_2X16U_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVN_2X16UT_I_args, + 1, Iclass_IVP_LVN_2X16UT_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVN_2X16UT_IP_args, + 1, Iclass_IVP_LVN_2X16UT_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVN_2X16UT_X_args, + 1, Iclass_IVP_LVN_2X16UT_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVN_2X16UT_XP_args, + 1, Iclass_IVP_LVN_2X16UT_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVN_2X16S_I_args, + 1, Iclass_IVP_LVN_2X16S_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVN_2X16S_IP_args, + 1, Iclass_IVP_LVN_2X16S_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVN_2X16S_X_args, + 1, Iclass_IVP_LVN_2X16S_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LVN_2X16S_XP_args, + 1, Iclass_IVP_LVN_2X16S_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVN_2X16ST_I_args, + 1, Iclass_IVP_LVN_2X16ST_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVN_2X16ST_IP_args, + 1, Iclass_IVP_LVN_2X16ST_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVN_2X16ST_X_args, + 1, Iclass_IVP_LVN_2X16ST_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LVN_2X16ST_XP_args, + 1, Iclass_IVP_LVN_2X16ST_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVN_2X16U_I_args, + 1, Iclass_IVP_SVN_2X16U_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVN_2X16UT_I_args, + 1, Iclass_IVP_SVN_2X16UT_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVN_2X16U_IP_args, + 1, Iclass_IVP_SVN_2X16U_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVN_2X16UT_IP_args, + 1, Iclass_IVP_SVN_2X16UT_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVN_2X16U_X_args, + 1, Iclass_IVP_SVN_2X16U_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVN_2X16UT_X_args, + 1, Iclass_IVP_SVN_2X16UT_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVN_2X16U_XP_args, + 1, Iclass_IVP_SVN_2X16U_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVN_2X16UT_XP_args, + 1, Iclass_IVP_SVN_2X16UT_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVN_2X16S_I_args, + 1, Iclass_IVP_SVN_2X16S_I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVN_2X16ST_I_args, + 1, Iclass_IVP_SVN_2X16ST_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVN_2X16S_IP_args, + 1, Iclass_IVP_SVN_2X16S_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVN_2X16ST_IP_args, + 1, Iclass_IVP_SVN_2X16ST_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVN_2X16S_X_args, + 1, Iclass_IVP_SVN_2X16S_X_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVN_2X16ST_X_args, + 1, Iclass_IVP_SVN_2X16ST_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SVN_2X16S_XP_args, + 1, Iclass_IVP_SVN_2X16S_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SVN_2X16ST_XP_args, + 1, Iclass_IVP_SVN_2X16ST_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LAN_2X16S_IP_args, + 1, Iclass_IVP_LAN_2X16S_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LAN_2X16U_IP_args, + 1, Iclass_IVP_LAN_2X16U_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LAN_2X16U_XP_args, + 1, Iclass_IVP_LAN_2X16U_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LAN_2X16S_XP_args, + 1, Iclass_IVP_LAN_2X16S_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SAN_2X16U_IP_args, + 1, Iclass_IVP_SAN_2X16U_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SAN_2X16S_IP_args, + 1, Iclass_IVP_SAN_2X16S_IP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LAVN_2X16S_XP_args, + 1, Iclass_IVP_LAVN_2X16S_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LAVN_2X16U_XP_args, + 1, Iclass_IVP_LAVN_2X16U_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SAVN_2X16U_XP_args, + 1, Iclass_IVP_SAVN_2X16U_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SAVN_2X16S_XP_args, + 1, Iclass_IVP_SAVN_2X16S_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSN_2X16S_I_args, + 1, Iclass_IVP_LSN_2X16S_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSN_2X16S_IP_args, + 1, Iclass_IVP_LSN_2X16S_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSN_2X16S_X_args, + 1, Iclass_IVP_LSN_2X16S_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSN_2X16S_XP_args, + 1, Iclass_IVP_LSN_2X16S_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSN_2X16S_I_args, + 1, Iclass_IVP_SSN_2X16S_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSN_2X16S_IP_args, + 1, Iclass_IVP_SSN_2X16S_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSN_2X16S_X_args, + 1, Iclass_IVP_SSN_2X16S_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSN_2X16S_XP_args, + 1, Iclass_IVP_SSN_2X16S_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSN_2X32_I_args, + 1, Iclass_IVP_LSN_2X32_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSN_2X32_IP_args, + 1, Iclass_IVP_LSN_2X32_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSN_2X32_X_args, + 1, Iclass_IVP_LSN_2X32_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSN_2X32_XP_args, + 1, Iclass_IVP_LSN_2X32_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSN_2X32_I_args, + 1, Iclass_IVP_SSN_2X32_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSN_2X32_IP_args, + 1, Iclass_IVP_SSN_2X32_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSN_2X32_X_args, + 1, Iclass_IVP_SSN_2X32_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SSN_2X32_XP_args, + 1, Iclass_IVP_SSN_2X32_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMAXUNX16_args, + 1, Iclass_IVP_BMAXUNX16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMINUNX16_args, + 1, Iclass_IVP_BMINUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RBMINUNX16_args, + 1, Iclass_IVP_RBMINUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RBMAXUNX16_args, + 1, Iclass_IVP_RBMAXUNX16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMAX2NX8_args, + 1, Iclass_IVP_BMAX2NX8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMIN2NX8_args, + 1, Iclass_IVP_BMIN2NX8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMAXU2NX8_args, + 1, Iclass_IVP_BMAXU2NX8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMINU2NX8_args, + 1, Iclass_IVP_BMINU2NX8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMAXN_2X32_args, + 1, Iclass_IVP_BMAXN_2X32_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMINN_2X32_args, + 1, Iclass_IVP_BMINN_2X32_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMAXUN_2X32_args, + 1, Iclass_IVP_BMAXUN_2X32_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BMINUN_2X32_args, + 1, Iclass_IVP_BMINUN_2X32_stateArgs, 0, 0 }, + { 4, Iclass_IVP_ADDN_2X32T_args, + 1, Iclass_IVP_ADDN_2X32T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SUBN_2X32T_args, + 1, Iclass_IVP_SUBN_2X32T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADD2NX8_args, + 1, Iclass_IVP_ADD2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUB2NX8_args, + 1, Iclass_IVP_SUB2NX8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NEG2NX8_args, + 1, Iclass_IVP_NEG2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MIN2NX8_args, + 1, Iclass_IVP_MIN2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MINU2NX8_args, + 1, Iclass_IVP_MINU2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MAX2NX8_args, + 1, Iclass_IVP_MAX2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MAXU2NX8_args, + 1, Iclass_IVP_MAXU2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LT2NX8_args, + 1, Iclass_IVP_LT2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LE2NX8_args, + 1, Iclass_IVP_LE2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_EQ2NX8_args, + 1, Iclass_IVP_EQ2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_NEQ2NX8_args, + 1, Iclass_IVP_NEQ2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LTU2NX8_args, + 1, Iclass_IVP_LTU2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LEU2NX8_args, + 1, Iclass_IVP_LEU2NX8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_ADD2NX8T_args, + 1, Iclass_IVP_ADD2NX8T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SUB2NX8T_args, + 1, Iclass_IVP_SUB2NX8T_stateArgs, 0, 0 }, + { 5, Iclass_IVP_SELNX16T_args, + 1, Iclass_IVP_SELNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SELN_2X32_args, + 1, Iclass_IVP_SELN_2X32_stateArgs, 0, 0 }, + { 5, Iclass_IVP_SELN_2X32T_args, + 1, Iclass_IVP_SELN_2X32T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SHFLN_2X32_args, + 1, Iclass_IVP_SHFLN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLLIN_2X32_args, + 1, Iclass_IVP_SLLIN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLSIN_2X32_args, + 1, Iclass_IVP_SLSIN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRAIN_2X32_args, + 1, Iclass_IVP_SRAIN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRLIN_2X32_args, + 1, Iclass_IVP_SRLIN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLLN_2X32_args, + 1, Iclass_IVP_SLLN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRLN_2X32_args, + 1, Iclass_IVP_SRLN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLAN_2X32_args, + 1, Iclass_IVP_SLAN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRAN_2X32_args, + 1, Iclass_IVP_SRAN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLSN_2X32_args, + 1, Iclass_IVP_SLSN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRSN_2X32_args, + 1, Iclass_IVP_SRSN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RADDN_2X32_args, + 1, Iclass_IVP_RADDN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RMAXN_2X32_args, + 1, Iclass_IVP_RMAXN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RMINN_2X32_args, + 1, Iclass_IVP_RMINN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RMAXUN_2X32_args, + 1, Iclass_IVP_RMAXUN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RMINUN_2X32_args, + 1, Iclass_IVP_RMINUN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RADDN_2X32T_args, + 1, Iclass_IVP_RADDN_2X32T_stateArgs, 0, 0 }, + { 2, Iclass_IVP_ABS2NX8_args, + 1, Iclass_IVP_ABS2NX8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_ABSN_2X32_args, + 1, Iclass_IVP_ABSN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSGNSNX16_args, + 1, Iclass_IVP_MULSGNSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ROTRI2NX8_args, + 1, Iclass_IVP_ROTRI2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ROTRINX16_args, + 1, Iclass_IVP_ROTRINX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ROTRIN_2X32_args, + 1, Iclass_IVP_ROTRIN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ROTRNX16_args, + 1, Iclass_IVP_ROTRNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ROTRN_2X32_args, + 1, Iclass_IVP_ROTRN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDN_2X32_args, + 1, Iclass_IVP_ADDN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBN_2X32_args, + 1, Iclass_IVP_SUBN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NEGN_2X32_args, + 1, Iclass_IVP_NEGN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MINN_2X32_args, + 1, Iclass_IVP_MINN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MINUN_2X32_args, + 1, Iclass_IVP_MINUN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MAXN_2X32_args, + 1, Iclass_IVP_MAXN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MAXUN_2X32_args, + 1, Iclass_IVP_MAXUN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSGNN_2X32_args, + 1, Iclass_IVP_MULSGNN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NSAN_2X32_args, + 1, Iclass_IVP_NSAN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_NSAUN_2X32_args, + 1, Iclass_IVP_NSAUN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LTN_2X32_args, + 1, Iclass_IVP_LTN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LEN_2X32_args, + 1, Iclass_IVP_LEN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_EQN_2X32_args, + 1, Iclass_IVP_EQN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_NEQN_2X32_args, + 1, Iclass_IVP_NEQN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LTUN_2X32_args, + 1, Iclass_IVP_LTUN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LEUN_2X32_args, + 1, Iclass_IVP_LEUN_2X32_stateArgs, 0, 0 }, + { 5, Iclass_IVP_LAT2NX8_XP_args, + 1, Iclass_IVP_LAT2NX8_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUU2NX8_args, + 1, Iclass_IVP_MULUU2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUA2NX8_args, + 1, Iclass_IVP_MULUUA2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUS2NX8_args, + 1, Iclass_IVP_MULUS2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSA2NX8_args, + 1, Iclass_IVP_MULUSA2NX8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULI2NX8X16_args, + 1, Iclass_IVP_MULI2NX8X16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULAI2NX8X16_args, + 1, Iclass_IVP_MULAI2NX8X16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUSI2NX8X16_args, + 1, Iclass_IVP_MULUSI2NX8X16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUSAI2NX8X16_args, + 1, Iclass_IVP_MULUSAI2NX8X16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULI2NR8X16_args, + 1, Iclass_IVP_MULI2NR8X16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULAI2NR8X16_args, + 1, Iclass_IVP_MULAI2NR8X16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUSI2NR8X16_args, + 1, Iclass_IVP_MULUSI2NR8X16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUSAI2NR8X16_args, + 1, Iclass_IVP_MULUSAI2NR8X16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSA2N8XR16_args, + 1, Iclass_IVP_MULUSA2N8XR16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUS2N8XR16_args, + 1, Iclass_IVP_MULUS2N8XR16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULA2N8XR16_args, + 1, Iclass_IVP_MULA2N8XR16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MUL2N8XR16_args, + 1, Iclass_IVP_MUL2N8XR16_stateArgs, 0, 0 }, + { 5, Iclass_IVP_DSEL2NX8I_args, + 1, Iclass_IVP_DSEL2NX8I_stateArgs, 0, 0 }, + { 5, Iclass_IVP_DSEL2NX8I_H_args, + 1, Iclass_IVP_DSEL2NX8I_H_stateArgs, 0, 0 }, + { 5, Iclass_IVP_DSELNX16_args, + 1, Iclass_IVP_DSELNX16_stateArgs, 0, 0 }, + { 6, Iclass_IVP_DSELNX16T_args, + 1, Iclass_IVP_DSELNX16T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_INJBI2NX8_args, + 1, Iclass_IVP_INJBI2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_EXTBI2NX8_args, + 1, Iclass_IVP_EXTBI2NX8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVVA32_args, + 1, Iclass_IVP_MOVVA32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVAV32_args, + 1, Iclass_IVP_MOVAV32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVWW_args, + 1, Iclass_IVP_MOVWW_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LS2NX8_I_args, + 1, Iclass_IVP_LS2NX8_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LS2NX8_IP_args, + 1, Iclass_IVP_LS2NX8_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LS2NX8_X_args, + 1, Iclass_IVP_LS2NX8_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LS2NX8_XP_args, + 1, Iclass_IVP_LS2NX8_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SS2NX8_I_args, + 1, Iclass_IVP_SS2NX8_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SS2NX8_IP_args, + 1, Iclass_IVP_SS2NX8_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SS2NX8_X_args, + 1, Iclass_IVP_SS2NX8_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SS2NX8_XP_args, + 1, Iclass_IVP_SS2NX8_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LANX8S_XP_args, + 1, Iclass_IVP_LANX8S_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LANX8U_XP_args, + 1, Iclass_IVP_LANX8U_XP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_LA2NX8_XP_args, + 1, Iclass_IVP_LA2NX8_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ABSSUBU2NX8_args, + 1, Iclass_IVP_ABSSUBU2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ABSSUB2NX8_args, + 1, Iclass_IVP_ABSSUB2NX8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVVINT8_args, + 1, Iclass_IVP_MOVVINT8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVVA8_args, + 1, Iclass_IVP_MOVVA8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVAVU8_args, + 1, Iclass_IVP_MOVAVU8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SLLI2NX8_args, + 1, Iclass_IVP_SLLI2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRAI2NX8_args, + 1, Iclass_IVP_SRAI2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SRLI2NX8_args, + 1, Iclass_IVP_SRLI2NX8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_PACKL2NX24_args, + 1, Iclass_IVP_PACKL2NX24_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVR2NX24_args, + 1, Iclass_IVP_PACKVR2NX24_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRU2NX24_args, + 1, Iclass_IVP_PACKVRU2NX24_stateArgs, 0, 0 }, + { 2, Iclass_IVP_PACKLNX48_args, + 1, Iclass_IVP_PACKLNX48_stateArgs, 0, 0 }, + { 2, Iclass_IVP_PACKL2NX24_1_args, + 1, Iclass_IVP_PACKL2NX24_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVR2NX24_0_args, + 1, Iclass_IVP_PACKVR2NX24_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVR2NX24_1_args, + 1, Iclass_IVP_PACKVR2NX24_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRU2NX24_0_args, + 1, Iclass_IVP_PACKVRU2NX24_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRU2NX24_1_args, + 1, Iclass_IVP_PACKVRU2NX24_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNR2NX24_0_args, + 1, Iclass_IVP_PACKVRNR2NX24_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNR2NX24_1_args, + 1, Iclass_IVP_PACKVRNR2NX24_1_stateArgs, 0, 0 }, + { 2, Iclass_IVP_PACKMNX48_args, + 1, Iclass_IVP_PACKMNX48_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNX48_args, + 1, Iclass_IVP_PACKVRNX48_stateArgs, 0, 0 }, + { 2, Iclass_IVP_UNPKS2NX8_0_args, + 1, Iclass_IVP_UNPKS2NX8_0_stateArgs, 0, 0 }, + { 2, Iclass_IVP_UNPKS2NX8_1_args, + 1, Iclass_IVP_UNPKS2NX8_1_stateArgs, 0, 0 }, + { 2, Iclass_IVP_UNPKSNX16_L_args, + 1, Iclass_IVP_UNPKSNX16_L_stateArgs, 0, 0 }, + { 2, Iclass_IVP_UNPKSNX16_H_args, + 1, Iclass_IVP_UNPKSNX16_H_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SEL2NX8I_args, + 1, Iclass_IVP_SEL2NX8I_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SEL2NX8I_S0_args, + 1, Iclass_IVP_SEL2NX8I_S0_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SEL2NX8I_S2_args, + 1, Iclass_IVP_SEL2NX8I_S2_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SEL2NX8I_S4_args, + 1, Iclass_IVP_SEL2NX8I_S4_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SHFL2NX8I_args, + 1, Iclass_IVP_SHFL2NX8I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SHFL2NX8I_S0_args, + 1, Iclass_IVP_SHFL2NX8I_S0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SHFL2NX8I_S2_args, + 1, Iclass_IVP_SHFL2NX8I_S2_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SHFL2NX8I_S4_args, + 1, Iclass_IVP_SHFL2NX8I_S4_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SEL2NX8_args, + 1, Iclass_IVP_SEL2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SHFL2NX8_args, + 1, Iclass_IVP_SHFL2NX8_stateArgs, 0, 0 }, + { 5, Iclass_IVP_SEL2NX8T_args, + 1, Iclass_IVP_SEL2NX8T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SQZN_args, + 1, Iclass_IVP_SQZN_stateArgs, 0, 0 }, + { 3, Iclass_IVP_UNSQZN_args, + 1, Iclass_IVP_UNSQZN_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULNX16_args, + 1, Iclass_IVP_MULNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULANX16_args, + 1, Iclass_IVP_MULANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUNX16_args, + 1, Iclass_IVP_MULUUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUANX16_args, + 1, Iclass_IVP_MULUUANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSNX16_args, + 1, Iclass_IVP_MULUSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSANX16_args, + 1, Iclass_IVP_MULUSANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MUL2NX8_args, + 1, Iclass_IVP_MUL2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULA2NX8_args, + 1, Iclass_IVP_MULA2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDW2NX8_args, + 1, Iclass_IVP_ADDW2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWA2NX8_args, + 1, Iclass_IVP_ADDWA2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWS2NX8_args, + 1, Iclass_IVP_ADDWS2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWU2NX8_args, + 1, Iclass_IVP_ADDWU2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWUA2NX8_args, + 1, Iclass_IVP_ADDWUA2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWUS2NX8_args, + 1, Iclass_IVP_ADDWUS2NX8_stateArgs, 0, 0 }, + { 5, Iclass_IVP_DIVN_2X32X16S_4STEP0_args, + 1, Iclass_IVP_DIVN_2X32X16S_4STEP0_stateArgs, 0, 0 }, + { 4, Iclass_IVP_DIVN_2X32X16S_4STEP_args, + 1, Iclass_IVP_DIVN_2X32X16S_4STEP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_DIVN_2X32X16S_4STEPN_args, + 1, Iclass_IVP_DIVN_2X32X16S_4STEPN_stateArgs, 0, 0 }, + { 5, Iclass_IVP_DIVN_2X32X16U_4STEP0_args, + 1, Iclass_IVP_DIVN_2X32X16U_4STEP0_stateArgs, 0, 0 }, + { 4, Iclass_IVP_DIVN_2X32X16U_4STEP_args, + 1, Iclass_IVP_DIVN_2X32X16U_4STEP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_DIVN_2X32X16U_4STEPN_args, + 1, Iclass_IVP_DIVN_2X32X16U_4STEPN_stateArgs, 0, 0 }, + { 5, Iclass_IVP_DIVNX16S_4STEP0_args, + 1, Iclass_IVP_DIVNX16S_4STEP0_stateArgs, 0, 0 }, + { 4, Iclass_IVP_DIVNX16S_4STEP_args, + 1, Iclass_IVP_DIVNX16S_4STEP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_DIVNX16S_4STEPN_args, + 1, Iclass_IVP_DIVNX16S_4STEPN_stateArgs, 0, 0 }, + { 5, Iclass_IVP_DIVNX16U_4STEP0_args, + 1, Iclass_IVP_DIVNX16U_4STEP0_stateArgs, 0, 0 }, + { 4, Iclass_IVP_DIVNX16U_4STEP_args, + 1, Iclass_IVP_DIVNX16U_4STEP_stateArgs, 0, 0 }, + { 4, Iclass_IVP_DIVNX16U_4STEPN_args, + 1, Iclass_IVP_DIVNX16U_4STEPN_stateArgs, 0, 0 }, + { 5, Iclass_IVP_DIVNX16SQ_4STEP0_args, + 1, Iclass_IVP_DIVNX16SQ_4STEP0_stateArgs, 0, 0 }, + { 5, Iclass_IVP_DIVNX16Q_4STEP0_args, + 1, Iclass_IVP_DIVNX16Q_4STEP0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSNX16_args, + 1, Iclass_IVP_MULSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUSNX16_args, + 1, Iclass_IVP_MULUUSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSSNX16_args, + 1, Iclass_IVP_MULUSSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULN_2X16X32_0_args, + 1, Iclass_IVP_MULN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUN_2X16X32_0_args, + 1, Iclass_IVP_MULUUN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSN_2X16X32_0_args, + 1, Iclass_IVP_MULUSN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSUN_2X16X32_0_args, + 1, Iclass_IVP_MULSUN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULN_2X16X32_1_args, + 1, Iclass_IVP_MULN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUN_2X16X32_1_args, + 1, Iclass_IVP_MULUUN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSN_2X16X32_1_args, + 1, Iclass_IVP_MULUSN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSUN_2X16X32_1_args, + 1, Iclass_IVP_MULSUN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULHN_2X16X32_1_args, + 1, Iclass_IVP_MULHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUHN_2X16X32_1_args, + 1, Iclass_IVP_MULUUHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSHN_2X16X32_1_args, + 1, Iclass_IVP_MULUSHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSUHN_2X16X32_1_args, + 1, Iclass_IVP_MULSUHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULAN_2X16X32_0_args, + 1, Iclass_IVP_MULAN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUAN_2X16X32_0_args, + 1, Iclass_IVP_MULUUAN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSAN_2X16X32_0_args, + 1, Iclass_IVP_MULUSAN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSUAN_2X16X32_0_args, + 1, Iclass_IVP_MULSUAN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULAHN_2X16X32_1_args, + 1, Iclass_IVP_MULAHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUAHN_2X16X32_1_args, + 1, Iclass_IVP_MULUUAHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSAHN_2X16X32_1_args, + 1, Iclass_IVP_MULUSAHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSUAHN_2X16X32_1_args, + 1, Iclass_IVP_MULSUAHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULAN_2X16X32_1_args, + 1, Iclass_IVP_MULAN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUAN_2X16X32_1_args, + 1, Iclass_IVP_MULUUAN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSAN_2X16X32_1_args, + 1, Iclass_IVP_MULUSAN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSUAN_2X16X32_1_args, + 1, Iclass_IVP_MULSUAN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSHN_2X16X32_1_args, + 1, Iclass_IVP_MULSHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUSHN_2X16X32_1_args, + 1, Iclass_IVP_MULUUSHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSSHN_2X16X32_1_args, + 1, Iclass_IVP_MULUSSHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSUSHN_2X16X32_1_args, + 1, Iclass_IVP_MULSUSHN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSN_2X16X32_0_args, + 1, Iclass_IVP_MULSN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUSN_2X16X32_0_args, + 1, Iclass_IVP_MULUUSN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSSN_2X16X32_0_args, + 1, Iclass_IVP_MULUSSN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSUSN_2X16X32_0_args, + 1, Iclass_IVP_MULSUSN_2X16X32_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSN_2X16X32_1_args, + 1, Iclass_IVP_MULSN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUUSN_2X16X32_1_args, + 1, Iclass_IVP_MULUUSN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULUSSN_2X16X32_1_args, + 1, Iclass_IVP_MULUSSN_2X16X32_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_MULSUSN_2X16X32_1_args, + 1, Iclass_IVP_MULSUSN_2X16X32_1_stateArgs, 0, 0 }, + { 2, Iclass_IVP_PACKLN_2X96_args, + 1, Iclass_IVP_PACKLN_2X96_stateArgs, 0, 0 }, + { 2, Iclass_IVP_PACKHN_2X64W_args, + 1, Iclass_IVP_PACKHN_2X64W_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRN_2X64W_args, + 1, Iclass_IVP_PACKVRN_2X64W_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNRN_2X64W_args, + 1, Iclass_IVP_PACKVRNRN_2X64W_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNX48_0_args, + 1, Iclass_IVP_PACKVRNX48_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNX48_1_args, + 1, Iclass_IVP_PACKVRNX48_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNRNX48_0_args, + 1, Iclass_IVP_PACKVRNRNX48_0_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNRNX48_1_args, + 1, Iclass_IVP_PACKVRNRNX48_1_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNRNX48_args, + 1, Iclass_IVP_PACKVRNRNX48_stateArgs, 0, 0 }, + { 3, Iclass_IVP_PACKVRNR2NX24_args, + 1, Iclass_IVP_PACKVRNR2NX24_stateArgs, 0, 0 }, + { 4, Iclass_IVP_L2A4NX8_IP_args, + 1, Iclass_IVP_L2A4NX8_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_L2AU2NX8_IP_args, + 1, Iclass_IVP_L2AU2NX8_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_L2U2NX8_XP_args, + 1, Iclass_IVP_L2U2NX8_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_AVGU2NX8_args, + 1, Iclass_IVP_AVGU2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_AVGRU2NX8_args, + 1, Iclass_IVP_AVGRU2NX8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RADD2NX8_args, + 1, Iclass_IVP_RADD2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RADD2NX8T_args, + 1, Iclass_IVP_RADD2NX8T_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RADDUNX16_args, + 1, Iclass_IVP_RADDUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RADDUNX16T_args, + 1, Iclass_IVP_RADDUNX16T_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RADDU2NX8_args, + 1, Iclass_IVP_RADDU2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RADDU2NX8T_args, + 1, Iclass_IVP_RADDU2NX8T_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LTRS2N_args, + 1, Iclass_IVP_LTRS2N_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LTRSN_args, + 1, Iclass_IVP_LTRSN_stateArgs, 0, 0 }, + { 2, Iclass_IVP_LTRSN_2_args, + 1, Iclass_IVP_LTRSN_2_stateArgs, 0, 0 }, + { 1, Iclass_IVP_SEQ2NX8_args, + 1, Iclass_IVP_SEQ2NX8_stateArgs, 0, 0 }, + { 1, Iclass_IVP_SEQN_2X32_args, + 1, Iclass_IVP_SEQN_2X32_stateArgs, 0, 0 }, + { 3, Iclass_IVP_EXTRN_2X32_args, + 1, Iclass_IVP_EXTRN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_UNPKU2NX8_0_args, + 1, Iclass_IVP_UNPKU2NX8_0_stateArgs, 0, 0 }, + { 2, Iclass_IVP_UNPKU2NX8_1_args, + 1, Iclass_IVP_UNPKU2NX8_1_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BADDNORMNX16_args, + 1, Iclass_IVP_BADDNORMNX16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_BSUBNORMNX16_args, + 1, Iclass_IVP_BSUBNORMNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RADDSNX16_args, + 1, Iclass_IVP_RADDSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_RADDSNX16T_args, + 1, Iclass_IVP_RADDSNX16T_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ORNOTB_args, + 1, Iclass_IVP_ORNOTB_stateArgs, 0, 0 }, + { 3, Iclass_IVP_EXTR2NX8_args, + 1, Iclass_IVP_EXTR2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_EXTRVRN_2X32_args, + 1, Iclass_IVP_EXTRVRN_2X32_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVAV8_args, + 1, Iclass_IVP_MOVAV8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULPN16XR16_args, + 1, Iclass_IVP_MULPN16XR16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULPAN16XR16_args, + 1, Iclass_IVP_MULPAN16XR16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUSPN16XR16_args, + 1, Iclass_IVP_MULUSPN16XR16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUSPAN16XR16_args, + 1, Iclass_IVP_MULUSPAN16XR16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULP2N8XR16_args, + 1, Iclass_IVP_MULP2N8XR16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULPA2N8XR16_args, + 1, Iclass_IVP_MULPA2N8XR16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUSP2N8XR16_args, + 1, Iclass_IVP_MULUSP2N8XR16_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUSPA2N8XR16_args, + 1, Iclass_IVP_MULUSPA2N8XR16_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULPNX16_args, + 1, Iclass_IVP_MULPNX16_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULPANX16_args, + 1, Iclass_IVP_MULPANX16_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULUSPNX16_args, + 1, Iclass_IVP_MULUSPNX16_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULUSPANX16_args, + 1, Iclass_IVP_MULUSPANX16_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULUUPNX16_args, + 1, Iclass_IVP_MULUUPNX16_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULUUPANX16_args, + 1, Iclass_IVP_MULUUPANX16_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULP2NX8_args, + 1, Iclass_IVP_MULP2NX8_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULPA2NX8_args, + 1, Iclass_IVP_MULPA2NX8_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULUSP2NX8_args, + 1, Iclass_IVP_MULUSP2NX8_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULUSPA2NX8_args, + 1, Iclass_IVP_MULUSPA2NX8_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULUUP2NX8_args, + 1, Iclass_IVP_MULUUP2NX8_stateArgs, 0, 0 }, + { 5, Iclass_IVP_MULUUPA2NX8_args, + 1, Iclass_IVP_MULUUPA2NX8_stateArgs, 0, 0 }, + { 6, Iclass_IVP_MULPI2NR8X16_args, + 1, Iclass_IVP_MULPI2NR8X16_stateArgs, 0, 0 }, + { 6, Iclass_IVP_MULPAI2NR8X16_args, + 1, Iclass_IVP_MULPAI2NR8X16_stateArgs, 0, 0 }, + { 6, Iclass_IVP_MULUSPI2NR8X16_args, + 1, Iclass_IVP_MULUSPI2NR8X16_stateArgs, 0, 0 }, + { 6, Iclass_IVP_MULUSPAI2NR8X16_args, + 1, Iclass_IVP_MULUSPAI2NR8X16_stateArgs, 0, 0 }, + { 6, Iclass_IVP_MULQ2N8XR8_args, + 1, Iclass_IVP_MULQ2N8XR8_stateArgs, 0, 0 }, + { 6, Iclass_IVP_MULQA2N8XR8_args, + 1, Iclass_IVP_MULQA2N8XR8_stateArgs, 0, 0 }, + { 6, Iclass_IVP_MULUSQ2N8XR8_args, + 1, Iclass_IVP_MULUSQ2N8XR8_stateArgs, 0, 0 }, + { 6, Iclass_IVP_MULUSQA2N8XR8_args, + 1, Iclass_IVP_MULUSQA2N8XR8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MUL4T2N8XR8_args, + 1, Iclass_IVP_MUL4T2N8XR8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MUL4TA2N8XR8_args, + 1, Iclass_IVP_MUL4TA2N8XR8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUS4T2N8XR8_args, + 1, Iclass_IVP_MULUS4T2N8XR8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_MULUS4TA2N8XR8_args, + 1, Iclass_IVP_MULUS4TA2N8XR8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWNX16_args, + 1, Iclass_IVP_ADDWNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWANX16_args, + 1, Iclass_IVP_ADDWANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWSNX16_args, + 1, Iclass_IVP_ADDWSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWUNX16_args, + 1, Iclass_IVP_ADDWUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWUANX16_args, + 1, Iclass_IVP_ADDWUANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ADDWUSNX16_args, + 1, Iclass_IVP_ADDWUSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBWNX16_args, + 1, Iclass_IVP_SUBWNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBWANX16_args, + 1, Iclass_IVP_SUBWANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBWUNX16_args, + 1, Iclass_IVP_SUBWUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBWUANX16_args, + 1, Iclass_IVP_SUBWUANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBW2NX8_args, + 1, Iclass_IVP_SUBW2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBWA2NX8_args, + 1, Iclass_IVP_SUBWA2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBWU2NX8_args, + 1, Iclass_IVP_SUBWU2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SUBWUA2NX8_args, + 1, Iclass_IVP_SUBWUA2NX8_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RANDB2N_args, + 1, Iclass_IVP_RANDB2N_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RORB2N_args, + 1, Iclass_IVP_RORB2N_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RANDBN_args, + 1, Iclass_IVP_RANDBN_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RORBN_args, + 1, Iclass_IVP_RORBN_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RANDBN_2_args, + 1, Iclass_IVP_RANDBN_2_stateArgs, 0, 0 }, + { 2, Iclass_IVP_RORBN_2_args, + 1, Iclass_IVP_RORBN_2_stateArgs, 0, 0 }, + { 3, Iclass_IVP_AVGNX16_args, + 1, Iclass_IVP_AVGNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_AVGUNX16_args, + 1, Iclass_IVP_AVGUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_AVG2NX8_args, + 1, Iclass_IVP_AVG2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_AVGR2NX8_args, + 1, Iclass_IVP_AVGR2NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_AVGRNX16_args, + 1, Iclass_IVP_AVGRNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_AVGRUNX16_args, + 1, Iclass_IVP_AVGRUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_GATHERANX8U_args, + 1, Iclass_IVP_GATHERANX8U_stateArgs, 0, 0 }, + { 3, Iclass_IVP_GATHERANX16_args, + 1, Iclass_IVP_GATHERANX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_GATHERAN_2X32_args, + 1, Iclass_IVP_GATHERAN_2X32_stateArgs, 0, 0 }, + { 4, Iclass_IVP_GATHERANX8UT_args, + 1, Iclass_IVP_GATHERANX8UT_stateArgs, 0, 0 }, + { 4, Iclass_IVP_GATHERANX16T_args, + 1, Iclass_IVP_GATHERANX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_GATHERAN_2X32T_args, + 1, Iclass_IVP_GATHERAN_2X32T_stateArgs, 0, 0 }, + { 2, Iclass_IVP_GATHERDNX16_args, + 1, Iclass_IVP_GATHERDNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_GATHERDNX8S_args, + 1, Iclass_IVP_GATHERDNX8S_stateArgs, 0, 0 }, + { 2, Iclass_IVP_GATHERD2NX8_L_args, + 1, Iclass_IVP_GATHERD2NX8_L_stateArgs, 0, 0 }, + { 2, Iclass_IVP_GATHERD2NX8_H_args, + 1, Iclass_IVP_GATHERD2NX8_H_stateArgs, 0, 0 }, + { 2, Iclass_IVP_MOVGATHERD_args, + 1, Iclass_IVP_MOVGATHERD_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SCATTERNX8U_args, + 1, Iclass_IVP_SCATTERNX8U_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SCATTER2NX8_L_args, + 1, Iclass_IVP_SCATTER2NX8_L_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SCATTER2NX8_H_args, + 1, Iclass_IVP_SCATTER2NX8_H_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SCATTERNX16_args, + 1, Iclass_IVP_SCATTERNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_SCATTERN_2X32_args, + 1, Iclass_IVP_SCATTERN_2X32_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SCATTERNX8UT_args, + 1, Iclass_IVP_SCATTERNX8UT_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SCATTER2NX8T_L_args, + 1, Iclass_IVP_SCATTER2NX8T_L_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SCATTER2NX8T_H_args, + 1, Iclass_IVP_SCATTER2NX8T_H_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SCATTERNX16T_args, + 1, Iclass_IVP_SCATTERNX16T_stateArgs, 0, 0 }, + { 4, Iclass_IVP_SCATTERN_2X32T_args, + 1, Iclass_IVP_SCATTERN_2X32T_stateArgs, 0, 0 }, + { 0, 0 /* IVP_SCATTERW */, + 0, 0, 0, 0 }, + { 4, Iclass_IVP_COUNTEQZ4NX8_args, + 1, Iclass_IVP_COUNTEQZ4NX8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_COUNTEQ4NX8_args, + 1, Iclass_IVP_COUNTEQ4NX8_stateArgs, 0, 0 }, + { 6, Iclass_IVP_COUNTEQMZ4NX8_args, + 1, Iclass_IVP_COUNTEQMZ4NX8_stateArgs, 0, 0 }, + { 6, Iclass_IVP_COUNTEQM4NX8_args, + 1, Iclass_IVP_COUNTEQM4NX8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_COUNTLEZ4NX8_args, + 1, Iclass_IVP_COUNTLEZ4NX8_stateArgs, 0, 0 }, + { 4, Iclass_IVP_COUNTLE4NX8_args, + 1, Iclass_IVP_COUNTLE4NX8_stateArgs, 0, 0 }, + { 6, Iclass_IVP_COUNTLEMZ4NX8_args, + 1, Iclass_IVP_COUNTLEMZ4NX8_stateArgs, 0, 0 }, + { 6, Iclass_IVP_COUNTLEM4NX8_args, + 1, Iclass_IVP_COUNTLEM4NX8_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSR2NX8_I_args, + 1, Iclass_IVP_LSR2NX8_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSR2NX8_IP_args, + 1, Iclass_IVP_LSR2NX8_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSR2NX8_X_args, + 1, Iclass_IVP_LSR2NX8_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSR2NX8_XP_args, + 1, Iclass_IVP_LSR2NX8_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSRNX16_I_args, + 1, Iclass_IVP_LSRNX16_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSRNX16_IP_args, + 1, Iclass_IVP_LSRNX16_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSRNX16_X_args, + 1, Iclass_IVP_LSRNX16_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSRNX16_XP_args, + 1, Iclass_IVP_LSRNX16_XP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSRN_2X32_I_args, + 1, Iclass_IVP_LSRN_2X32_I_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSRN_2X32_IP_args, + 1, Iclass_IVP_LSRN_2X32_IP_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSRN_2X32_X_args, + 1, Iclass_IVP_LSRN_2X32_X_stateArgs, 0, 0 }, + { 3, Iclass_IVP_LSRN_2X32_XP_args, + 1, Iclass_IVP_LSRN_2X32_XP_stateArgs, 0, 0 }, + { 2, Iclass_IVP_ABSNX16_args, + 1, Iclass_IVP_ABSNX16_stateArgs, 0, 0 }, + { 2, Iclass_IVP_ABSSNX16_args, + 1, Iclass_IVP_ABSSNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ABSSUBNX16_args, + 1, Iclass_IVP_ABSSUBNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ABSSUBUNX16_args, + 1, Iclass_IVP_ABSSUBUNX16_stateArgs, 0, 0 }, + { 3, Iclass_IVP_ABSSSUBNX16_args, + 1, Iclass_IVP_ABSSSUBNX16_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_threadptr_args, + 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, + { 1, Iclass_wur_threadptr_args, + 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_const16_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32ex_args, + 1, Iclass_xt_iclass_l32ex_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_s32ex_args, + 1, Iclass_xt_iclass_s32ex_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_getex_args, + 1, Iclass_xt_iclass_getex_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_clrex */, + 1, Iclass_xt_iclass_clrex_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_simcall */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32nb_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_memctl_args, + 1, Iclass_xt_iclass_rsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_memctl_args, + 1, Iclass_xt_iclass_wsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_memctl_args, + 1, Iclass_xt_iclass_xsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid0_args, + 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_configid0_args, + 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid1_args, + 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_mpucfg_args, + 3, Iclass_xt_iclass_rsr_mpucfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mpucfg_args, + 3, Iclass_xt_iclass_wsr_mpucfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_gserr_args, + 3, Iclass_xt_iclass_rsr_gserr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_gserr_args, + 3, Iclass_xt_iclass_wsr_gserr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_gserr_args, + 3, Iclass_xt_iclass_xsr_gserr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_salt_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul16_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32h_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 15, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 4, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 5, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 5, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_lddr32_p_args, + 5, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sddr32_p_args, + 4, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_bbool1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbranch_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bmove_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_RSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_WSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_XSR_BR_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_lock_args, + 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cacheadrdis_args, + 4, Iclass_xt_iclass_wsr_cacheadrdis_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cacheadrdis_args, + 3, Iclass_xt_iclass_rsr_cacheadrdis_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cacheadrdis_args, + 4, Iclass_xt_iclass_xsr_cacheadrdis_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rptlb0_args, + 3, Iclass_xt_iclass_rptlb0_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rptlb_args, + 2, Iclass_xt_iclass_rptlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_wptlb_args, + 4, Iclass_xt_iclass_wptlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_mpuenb_args, + 3, Iclass_xt_iclass_rsr_mpuenb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mpuenb_args, + 4, Iclass_xt_iclass_wsr_mpuenb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_mpuenb_args, + 4, Iclass_xt_iclass_xsr_mpuenb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cpenable_args, + 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cpenable_args, + 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cpenable_args, + 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_clamp_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_atomctl_args, + 4, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_atomctl_args, + 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_atomctl_args, + 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_div_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eraccess_args, + 3, Iclass_xt_iclass_rsr_eraccess_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eraccess_args, + 3, Iclass_xt_iclass_wsr_eraccess_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eraccess_args, + 3, Iclass_xt_iclass_xsr_eraccess_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rer_args, + 4, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs }, + { 2, Iclass_xt_iclass_wer_args, + 4, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs }, + { 2, Iclass_xt_iclass_wb15_0_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_1_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_2_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_3_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_4_args, + 0, 0, 0, 0 }, + { 4, Iclass_MTK_AndPOPC_args, + 1, Iclass_MTK_AndPOPC_stateArgs, 0, 0 }, + { 1, Iclass_iq_tie2apb_inq0_pop_args, + 1, Iclass_iq_tie2apb_inq0_pop_stateArgs, 1, Iclass_iq_tie2apb_inq0_pop_intfArgs }, + { 1, Iclass_iq_tie2apb_inq0_is_ready_args, + 0, 0, 1, Iclass_iq_tie2apb_inq0_is_ready_intfArgs }, + { 2, Iclass_iq_tie2apb_inq0_nonblocking_peek_args, + 0, 0, 3, Iclass_iq_tie2apb_inq0_nonblocking_peek_intfArgs }, + { 2, Iclass_iq_tie2apb_inq0_nonblocking_pop_args, + 1, Iclass_iq_tie2apb_inq0_nonblocking_pop_stateArgs, 3, Iclass_iq_tie2apb_inq0_nonblocking_pop_intfArgs }, + { 1, Iclass_iq_tie2apb_inq0_blocking_peek_args, + 0, 0, 3, Iclass_iq_tie2apb_inq0_blocking_peek_intfArgs }, + { 2, Iclass_oq_tie2apb_outq0_push_read_args, + 1, Iclass_oq_tie2apb_outq0_push_read_stateArgs, 1, Iclass_oq_tie2apb_outq0_push_read_intfArgs }, + { 2, Iclass_oq_tie2apb_outq0_push_write_args, + 1, Iclass_oq_tie2apb_outq0_push_write_stateArgs, 1, Iclass_oq_tie2apb_outq0_push_write_intfArgs }, + { 1, Iclass_oq_tie2apb_outq0_is_ready_args, + 0, 0, 1, Iclass_oq_tie2apb_outq0_is_ready_intfArgs }, + { 3, Iclass_oq_tie2apb_outq0_nonblocking_push_read_args, + 1, Iclass_oq_tie2apb_outq0_nonblocking_push_read_stateArgs, 3, Iclass_oq_tie2apb_outq0_nonblocking_push_read_intfArgs }, + { 3, Iclass_oq_tie2apb_outq0_nonblocking_push_write_args, + 1, Iclass_oq_tie2apb_outq0_nonblocking_push_write_stateArgs, 3, Iclass_oq_tie2apb_outq0_nonblocking_push_write_intfArgs }, + { 1, Iclass_rur_apb_pipe_args, + 1, Iclass_rur_apb_pipe_stateArgs, 0, 0 }, + { 1, Iclass_wur_apb_pipe_args, + 1, Iclass_wur_apb_pipe_stateArgs, 0, 0 } +}; + +enum xtensa_iclass_id { + ICLASS_IVP_REPNX16, + ICLASS_IVP_SELSNX16, + ICLASS_IVP_REP2NX8, + ICLASS_IVP_SELS2NX8, + ICLASS_IVP_REPN_2X32, + ICLASS_IVP_SELSN_2X32, + ICLASS_IVP_EXT0IB, + ICLASS_IVP_NOTB, + ICLASS_IVP_ANDB, + ICLASS_IVP_ORB, + ICLASS_IVP_XORB, + ICLASS_IVP_ANDNOTB, + ICLASS_IVP_MB, + ICLASS_IVP_LTRN, + ICLASS_IVP_LTRNI, + ICLASS_IVP_LBN_I, + ICLASS_IVP_LBN_IP, + ICLASS_IVP_SBN_I, + ICLASS_IVP_SBN_IP, + ICLASS_IVP_LSNX16_I, + ICLASS_IVP_LSNX16_IP, + ICLASS_IVP_LSNX16_X, + ICLASS_IVP_LSNX16_XP, + ICLASS_IVP_MOVBRBV, + ICLASS_IVP_MOVBVBR, + ICLASS_IVP_JOINB, + ICLASS_IVP_LTRN_2, + ICLASS_IVP_LTRN_2I, + ICLASS_IVP_LBN_2_I, + ICLASS_IVP_LBN_2_IP, + ICLASS_IVP_SBN_2_I, + ICLASS_IVP_SBN_2_IP, + ICLASS_IVP_LV2NX8_I, + ICLASS_IVP_LV2NX8_IP, + ICLASS_IVP_LV2NX8_X, + ICLASS_IVP_LV2NX8_XP, + ICLASS_IVP_SV2NX8_I, + ICLASS_IVP_SV2NX8_IP, + ICLASS_IVP_SV2NX8_X, + ICLASS_IVP_SV2NX8_XP, + ICLASS_IVP_SSNX16_I, + ICLASS_IVP_SSNX16_IP, + ICLASS_IVP_SSNX16_X, + ICLASS_IVP_SSNX16_XP, + ICLASS_IVP_MOVVA16, + ICLASS_IVP_MOVVV, + ICLASS_IVP_SLLINX16, + ICLASS_IVP_SLSINX16, + ICLASS_IVP_SRAINX16, + ICLASS_IVP_SRLINX16, + ICLASS_IVP_SLLNX16, + ICLASS_IVP_SRLNX16, + ICLASS_IVP_SLANX16, + ICLASS_IVP_SRANX16, + ICLASS_IVP_SLSNX16, + ICLASS_IVP_SRSNX16, + ICLASS_IVP_XOR2NX8, + ICLASS_IVP_AND2NX8, + ICLASS_IVP_OR2NX8, + ICLASS_IVP_NOT2NX8, + ICLASS_IVP_ADDNX16, + ICLASS_IVP_SUBNX16, + ICLASS_IVP_NEGNX16, + ICLASS_IVP_MINNX16, + ICLASS_IVP_MINUNX16, + ICLASS_IVP_MAXNX16, + ICLASS_IVP_MAXUNX16, + ICLASS_IVP_MULSGNNX16, + ICLASS_IVP_NSANX16, + ICLASS_IVP_NSAUNX16, + ICLASS_IVP_LTNX16, + ICLASS_IVP_LENX16, + ICLASS_IVP_EQNX16, + ICLASS_IVP_NEQNX16, + ICLASS_IVP_LTUNX16, + ICLASS_IVP_LEUNX16, + ICLASS_IVP_RADDNX16, + ICLASS_IVP_RMAXNX16, + ICLASS_IVP_RMINNX16, + ICLASS_IVP_RMAXUNX16, + ICLASS_IVP_RMINUNX16, + ICLASS_IVP_RBMINNX16, + ICLASS_IVP_RBMAXNX16, + ICLASS_IVP_BMAXNX16, + ICLASS_IVP_BMINNX16, + ICLASS_IVP_MOV2NX8T, + ICLASS_IVP_MULANX16PACKL, + ICLASS_IVP_MULANX16PACKQ, + ICLASS_IVP_MULSNX16PACKL, + ICLASS_IVP_MULSNX16PACKQ, + ICLASS_IVP_ADDSNX16, + ICLASS_IVP_SUBSNX16, + ICLASS_IVP_NEGSNX16, + ICLASS_IVP_LV2NX8T_I, + ICLASS_IVP_LV2NX8T_IP, + ICLASS_IVP_LV2NX8T_X, + ICLASS_IVP_LV2NX8T_XP, + ICLASS_IVP_SV2NX8T_I, + ICLASS_IVP_SV2NX8T_IP, + ICLASS_IVP_SV2NX8T_X, + ICLASS_IVP_SV2NX8T_XP, + ICLASS_IVP_RADDNX16T, + ICLASS_IVP_RMAXNX16T, + ICLASS_IVP_RMINNX16T, + ICLASS_IVP_RMAXUNX16T, + ICLASS_IVP_RMINUNX16T, + ICLASS_IVP_ADDNX16T, + ICLASS_IVP_SUBNX16T, + ICLASS_IVP_NEGNX16T, + ICLASS_IVP_MAXNX16T, + ICLASS_IVP_MINNX16T, + ICLASS_IVP_MAXUNX16T, + ICLASS_IVP_MINUNX16T, + ICLASS_IVP_MULANX16PACKLT, + ICLASS_IVP_MULANX16PACKQT, + ICLASS_IVP_ADDSNX16T, + ICLASS_IVP_SUBSNX16T, + ICLASS_IVP_NEGSNX16T, + ICLASS_IVP_LALIGN_I, + ICLASS_IVP_LALIGN_IP, + ICLASS_IVP_SALIGN_I, + ICLASS_IVP_SALIGN_IP, + ICLASS_IVP_LA_PP, + ICLASS_IVP_SAPOS_FP, + ICLASS_IVP_MALIGN, + ICLASS_IVP_ZALIGN, + ICLASS_IVP_LA2NX8_IP, + ICLASS_IVP_SA2NX8_IP, + ICLASS_IVP_LAV2NX8_XP, + ICLASS_IVP_SAV2NX8_XP, + ICLASS_IVP_SELNX16, + ICLASS_IVP_SHFLNX16, + ICLASS_IVP_MOVPINT16, + ICLASS_IVP_MOVPA16, + ICLASS_IVP_MULNX16PACKP, + ICLASS_IVP_MULANX16PACKP, + ICLASS_IVP_MULSNX16PACKP, + ICLASS_IVP_MULANX16PACKPT, + ICLASS_IVP_ADDMOD16U, + ICLASS_IVP_LVNX8S_I, + ICLASS_IVP_LVNX8S_IP, + ICLASS_IVP_LVNX8S_X, + ICLASS_IVP_LVNX8S_XP, + ICLASS_IVP_LVNX8U_I, + ICLASS_IVP_LVNX8U_IP, + ICLASS_IVP_LVNX8U_X, + ICLASS_IVP_LVNX8U_XP, + ICLASS_IVP_SVNX8U_I, + ICLASS_IVP_SVNX8U_IP, + ICLASS_IVP_SVNX8U_X, + ICLASS_IVP_SVNX8U_XP, + ICLASS_IVP_LVNX8ST_I, + ICLASS_IVP_LVNX8ST_IP, + ICLASS_IVP_LVNX8ST_X, + ICLASS_IVP_LVNX8ST_XP, + ICLASS_IVP_LVNX8UT_I, + ICLASS_IVP_LVNX8UT_IP, + ICLASS_IVP_LVNX8UT_X, + ICLASS_IVP_LVNX8UT_XP, + ICLASS_IVP_SVNX8UT_I, + ICLASS_IVP_SVNX8UT_IP, + ICLASS_IVP_SVNX8UT_X, + ICLASS_IVP_SVNX8UT_XP, + ICLASS_IVP_LAVNX8S_XP, + ICLASS_IVP_LAVNX8U_XP, + ICLASS_IVP_SAVNX8U_XP, + ICLASS_IVP_LANX8S_IP, + ICLASS_IVP_LANX8U_IP, + ICLASS_IVP_SANX8U_IP, + ICLASS_IVP_EXTRACTBL, + ICLASS_IVP_EXTRACTBH, + ICLASS_IVP_MOVVINT16, + ICLASS_IVP_MOVQINT16, + ICLASS_IVP_MOVQA16, + ICLASS_IVP_MOVVINX16, + ICLASS_IVP_SEQNX16, + ICLASS_IVP_MULNX16PACKL, + ICLASS_IVP_MULNX16PACKQ, + ICLASS_IVP_MOVAV16, + ICLASS_IVP_MOVAVU16, + ICLASS_IVP_EXTRNX16, + ICLASS_IVP_LSNX8S_I, + ICLASS_IVP_LSNX8S_IP, + ICLASS_IVP_LSNX8S_X, + ICLASS_IVP_LSNX8S_XP, + ICLASS_IVP_SVNX8S_I, + ICLASS_IVP_SVNX8S_IP, + ICLASS_IVP_SVNX8S_X, + ICLASS_IVP_SVNX8S_XP, + ICLASS_IVP_SSNX8S_I, + ICLASS_IVP_SSNX8S_IP, + ICLASS_IVP_SSNX8S_X, + ICLASS_IVP_SSNX8S_XP, + ICLASS_IVP_SAVNX8S_XP, + ICLASS_IVP_SANX8S_IP, + ICLASS_IVP_SVNX8ST_I, + ICLASS_IVP_SVNX8ST_IP, + ICLASS_IVP_SVNX8ST_X, + ICLASS_IVP_SVNX8ST_XP, + ICLASS_IVP_MOVBA1, + ICLASS_IVP_MOVAB1, + ICLASS_IVP_NOTB1, + ICLASS_IVP_ANDNOTB1, + ICLASS_IVP_ORNOTB1, + ICLASS_IVP_CVT32S2NX24LL, + ICLASS_IVP_CVT32S2NX24LH, + ICLASS_IVP_CVT32S2NX24HL, + ICLASS_IVP_CVT32S2NX24HH, + ICLASS_IVP_CVT64SNX48LL, + ICLASS_IVP_CVT64SNX48LH, + ICLASS_IVP_CVT64SNX48HL, + ICLASS_IVP_CVT64SNX48HH, + ICLASS_IVP_CVT16S2NX24L, + ICLASS_IVP_CVT16S2NX24H, + ICLASS_IVP_CVT32SNX48L, + ICLASS_IVP_CVT32SNX48H, + ICLASS_IVP_CVT16U2NX24H, + ICLASS_IVP_CVT32UNX48H, + ICLASS_IVP_CVT64UN_2X96H, + ICLASS_IVP_CVT16U2NX24L, + ICLASS_IVP_CVT24U2NX16, + ICLASS_IVP_CVT24S2NX16, + ICLASS_IVP_CVT32S24, + ICLASS_IVP_CVT24U32, + ICLASS_IVP_CVT24UNX32L, + ICLASS_IVP_CVT24UNX32H, + ICLASS_IVP_CVT32UNX48L, + ICLASS_IVP_CVT48UNX32L, + ICLASS_IVP_CVT48UNX32, + ICLASS_IVP_CVT48SNX32L, + ICLASS_IVP_CVT48SNX32, + ICLASS_IVP_CVT64S48, + ICLASS_IVP_CVT48U64, + ICLASS_IVP_CVT48UN_2X64L, + ICLASS_IVP_CVT48UN_2X64H, + ICLASS_IVP_CVT64UN_2X96L, + ICLASS_IVP_CVT96UN_2X64, + ICLASS_IVP_CVT96U64, + ICLASS_IVP_CVT64U96, + ICLASS_IVP_LB2N_I, + ICLASS_IVP_LB2N_IP, + ICLASS_IVP_SB2N_I, + ICLASS_IVP_SB2N_IP, + ICLASS_IVP_LTR2N, + ICLASS_IVP_LTR2NI, + ICLASS_IVP_LVN_2X16U_I, + ICLASS_IVP_LVN_2X16U_IP, + ICLASS_IVP_LVN_2X16U_X, + ICLASS_IVP_LVN_2X16U_XP, + ICLASS_IVP_LVN_2X16UT_I, + ICLASS_IVP_LVN_2X16UT_IP, + ICLASS_IVP_LVN_2X16UT_X, + ICLASS_IVP_LVN_2X16UT_XP, + ICLASS_IVP_LVN_2X16S_I, + ICLASS_IVP_LVN_2X16S_IP, + ICLASS_IVP_LVN_2X16S_X, + ICLASS_IVP_LVN_2X16S_XP, + ICLASS_IVP_LVN_2X16ST_I, + ICLASS_IVP_LVN_2X16ST_IP, + ICLASS_IVP_LVN_2X16ST_X, + ICLASS_IVP_LVN_2X16ST_XP, + ICLASS_IVP_SVN_2X16U_I, + ICLASS_IVP_SVN_2X16UT_I, + ICLASS_IVP_SVN_2X16U_IP, + ICLASS_IVP_SVN_2X16UT_IP, + ICLASS_IVP_SVN_2X16U_X, + ICLASS_IVP_SVN_2X16UT_X, + ICLASS_IVP_SVN_2X16U_XP, + ICLASS_IVP_SVN_2X16UT_XP, + ICLASS_IVP_SVN_2X16S_I, + ICLASS_IVP_SVN_2X16ST_I, + ICLASS_IVP_SVN_2X16S_IP, + ICLASS_IVP_SVN_2X16ST_IP, + ICLASS_IVP_SVN_2X16S_X, + ICLASS_IVP_SVN_2X16ST_X, + ICLASS_IVP_SVN_2X16S_XP, + ICLASS_IVP_SVN_2X16ST_XP, + ICLASS_IVP_LAN_2X16S_IP, + ICLASS_IVP_LAN_2X16U_IP, + ICLASS_IVP_LAN_2X16U_XP, + ICLASS_IVP_LAN_2X16S_XP, + ICLASS_IVP_SAN_2X16U_IP, + ICLASS_IVP_SAN_2X16S_IP, + ICLASS_IVP_LAVN_2X16S_XP, + ICLASS_IVP_LAVN_2X16U_XP, + ICLASS_IVP_SAVN_2X16U_XP, + ICLASS_IVP_SAVN_2X16S_XP, + ICLASS_IVP_LSN_2X16S_I, + ICLASS_IVP_LSN_2X16S_IP, + ICLASS_IVP_LSN_2X16S_X, + ICLASS_IVP_LSN_2X16S_XP, + ICLASS_IVP_SSN_2X16S_I, + ICLASS_IVP_SSN_2X16S_IP, + ICLASS_IVP_SSN_2X16S_X, + ICLASS_IVP_SSN_2X16S_XP, + ICLASS_IVP_LSN_2X32_I, + ICLASS_IVP_LSN_2X32_IP, + ICLASS_IVP_LSN_2X32_X, + ICLASS_IVP_LSN_2X32_XP, + ICLASS_IVP_SSN_2X32_I, + ICLASS_IVP_SSN_2X32_IP, + ICLASS_IVP_SSN_2X32_X, + ICLASS_IVP_SSN_2X32_XP, + ICLASS_IVP_BMAXUNX16, + ICLASS_IVP_BMINUNX16, + ICLASS_IVP_RBMINUNX16, + ICLASS_IVP_RBMAXUNX16, + ICLASS_IVP_BMAX2NX8, + ICLASS_IVP_BMIN2NX8, + ICLASS_IVP_BMAXU2NX8, + ICLASS_IVP_BMINU2NX8, + ICLASS_IVP_BMAXN_2X32, + ICLASS_IVP_BMINN_2X32, + ICLASS_IVP_BMAXUN_2X32, + ICLASS_IVP_BMINUN_2X32, + ICLASS_IVP_ADDN_2X32T, + ICLASS_IVP_SUBN_2X32T, + ICLASS_IVP_ADD2NX8, + ICLASS_IVP_SUB2NX8, + ICLASS_IVP_NEG2NX8, + ICLASS_IVP_MIN2NX8, + ICLASS_IVP_MINU2NX8, + ICLASS_IVP_MAX2NX8, + ICLASS_IVP_MAXU2NX8, + ICLASS_IVP_LT2NX8, + ICLASS_IVP_LE2NX8, + ICLASS_IVP_EQ2NX8, + ICLASS_IVP_NEQ2NX8, + ICLASS_IVP_LTU2NX8, + ICLASS_IVP_LEU2NX8, + ICLASS_IVP_ADD2NX8T, + ICLASS_IVP_SUB2NX8T, + ICLASS_IVP_SELNX16T, + ICLASS_IVP_SELN_2X32, + ICLASS_IVP_SELN_2X32T, + ICLASS_IVP_SHFLN_2X32, + ICLASS_IVP_SLLIN_2X32, + ICLASS_IVP_SLSIN_2X32, + ICLASS_IVP_SRAIN_2X32, + ICLASS_IVP_SRLIN_2X32, + ICLASS_IVP_SLLN_2X32, + ICLASS_IVP_SRLN_2X32, + ICLASS_IVP_SLAN_2X32, + ICLASS_IVP_SRAN_2X32, + ICLASS_IVP_SLSN_2X32, + ICLASS_IVP_SRSN_2X32, + ICLASS_IVP_RADDN_2X32, + ICLASS_IVP_RMAXN_2X32, + ICLASS_IVP_RMINN_2X32, + ICLASS_IVP_RMAXUN_2X32, + ICLASS_IVP_RMINUN_2X32, + ICLASS_IVP_RADDN_2X32T, + ICLASS_IVP_ABS2NX8, + ICLASS_IVP_ABSN_2X32, + ICLASS_IVP_MULSGNSNX16, + ICLASS_IVP_ROTRI2NX8, + ICLASS_IVP_ROTRINX16, + ICLASS_IVP_ROTRIN_2X32, + ICLASS_IVP_ROTRNX16, + ICLASS_IVP_ROTRN_2X32, + ICLASS_IVP_ADDN_2X32, + ICLASS_IVP_SUBN_2X32, + ICLASS_IVP_NEGN_2X32, + ICLASS_IVP_MINN_2X32, + ICLASS_IVP_MINUN_2X32, + ICLASS_IVP_MAXN_2X32, + ICLASS_IVP_MAXUN_2X32, + ICLASS_IVP_MULSGNN_2X32, + ICLASS_IVP_NSAN_2X32, + ICLASS_IVP_NSAUN_2X32, + ICLASS_IVP_LTN_2X32, + ICLASS_IVP_LEN_2X32, + ICLASS_IVP_EQN_2X32, + ICLASS_IVP_NEQN_2X32, + ICLASS_IVP_LTUN_2X32, + ICLASS_IVP_LEUN_2X32, + ICLASS_IVP_LAT2NX8_XP, + ICLASS_IVP_MULUU2NX8, + ICLASS_IVP_MULUUA2NX8, + ICLASS_IVP_MULUS2NX8, + ICLASS_IVP_MULUSA2NX8, + ICLASS_IVP_MULI2NX8X16, + ICLASS_IVP_MULAI2NX8X16, + ICLASS_IVP_MULUSI2NX8X16, + ICLASS_IVP_MULUSAI2NX8X16, + ICLASS_IVP_MULI2NR8X16, + ICLASS_IVP_MULAI2NR8X16, + ICLASS_IVP_MULUSI2NR8X16, + ICLASS_IVP_MULUSAI2NR8X16, + ICLASS_IVP_MULUSA2N8XR16, + ICLASS_IVP_MULUS2N8XR16, + ICLASS_IVP_MULA2N8XR16, + ICLASS_IVP_MUL2N8XR16, + ICLASS_IVP_DSEL2NX8I, + ICLASS_IVP_DSEL2NX8I_H, + ICLASS_IVP_DSELNX16, + ICLASS_IVP_DSELNX16T, + ICLASS_IVP_INJBI2NX8, + ICLASS_IVP_EXTBI2NX8, + ICLASS_IVP_MOVVA32, + ICLASS_IVP_MOVAV32, + ICLASS_IVP_MOVWW, + ICLASS_IVP_LS2NX8_I, + ICLASS_IVP_LS2NX8_IP, + ICLASS_IVP_LS2NX8_X, + ICLASS_IVP_LS2NX8_XP, + ICLASS_IVP_SS2NX8_I, + ICLASS_IVP_SS2NX8_IP, + ICLASS_IVP_SS2NX8_X, + ICLASS_IVP_SS2NX8_XP, + ICLASS_IVP_LANX8S_XP, + ICLASS_IVP_LANX8U_XP, + ICLASS_IVP_LA2NX8_XP, + ICLASS_IVP_ABSSUBU2NX8, + ICLASS_IVP_ABSSUB2NX8, + ICLASS_IVP_MOVVINT8, + ICLASS_IVP_MOVVA8, + ICLASS_IVP_MOVAVU8, + ICLASS_IVP_SLLI2NX8, + ICLASS_IVP_SRAI2NX8, + ICLASS_IVP_SRLI2NX8, + ICLASS_IVP_PACKL2NX24, + ICLASS_IVP_PACKVR2NX24, + ICLASS_IVP_PACKVRU2NX24, + ICLASS_IVP_PACKLNX48, + ICLASS_IVP_PACKL2NX24_1, + ICLASS_IVP_PACKVR2NX24_0, + ICLASS_IVP_PACKVR2NX24_1, + ICLASS_IVP_PACKVRU2NX24_0, + ICLASS_IVP_PACKVRU2NX24_1, + ICLASS_IVP_PACKVRNR2NX24_0, + ICLASS_IVP_PACKVRNR2NX24_1, + ICLASS_IVP_PACKMNX48, + ICLASS_IVP_PACKVRNX48, + ICLASS_IVP_UNPKS2NX8_0, + ICLASS_IVP_UNPKS2NX8_1, + ICLASS_IVP_UNPKSNX16_L, + ICLASS_IVP_UNPKSNX16_H, + ICLASS_IVP_SEL2NX8I, + ICLASS_IVP_SEL2NX8I_S0, + ICLASS_IVP_SEL2NX8I_S2, + ICLASS_IVP_SEL2NX8I_S4, + ICLASS_IVP_SHFL2NX8I, + ICLASS_IVP_SHFL2NX8I_S0, + ICLASS_IVP_SHFL2NX8I_S2, + ICLASS_IVP_SHFL2NX8I_S4, + ICLASS_IVP_SEL2NX8, + ICLASS_IVP_SHFL2NX8, + ICLASS_IVP_SEL2NX8T, + ICLASS_IVP_SQZN, + ICLASS_IVP_UNSQZN, + ICLASS_IVP_MULNX16, + ICLASS_IVP_MULANX16, + ICLASS_IVP_MULUUNX16, + ICLASS_IVP_MULUUANX16, + ICLASS_IVP_MULUSNX16, + ICLASS_IVP_MULUSANX16, + ICLASS_IVP_MUL2NX8, + ICLASS_IVP_MULA2NX8, + ICLASS_IVP_ADDW2NX8, + ICLASS_IVP_ADDWA2NX8, + ICLASS_IVP_ADDWS2NX8, + ICLASS_IVP_ADDWU2NX8, + ICLASS_IVP_ADDWUA2NX8, + ICLASS_IVP_ADDWUS2NX8, + ICLASS_IVP_DIVN_2X32X16S_4STEP0, + ICLASS_IVP_DIVN_2X32X16S_4STEP, + ICLASS_IVP_DIVN_2X32X16S_4STEPN, + ICLASS_IVP_DIVN_2X32X16U_4STEP0, + ICLASS_IVP_DIVN_2X32X16U_4STEP, + ICLASS_IVP_DIVN_2X32X16U_4STEPN, + ICLASS_IVP_DIVNX16S_4STEP0, + ICLASS_IVP_DIVNX16S_4STEP, + ICLASS_IVP_DIVNX16S_4STEPN, + ICLASS_IVP_DIVNX16U_4STEP0, + ICLASS_IVP_DIVNX16U_4STEP, + ICLASS_IVP_DIVNX16U_4STEPN, + ICLASS_IVP_DIVNX16SQ_4STEP0, + ICLASS_IVP_DIVNX16Q_4STEP0, + ICLASS_IVP_MULSNX16, + ICLASS_IVP_MULUUSNX16, + ICLASS_IVP_MULUSSNX16, + ICLASS_IVP_MULN_2X16X32_0, + ICLASS_IVP_MULUUN_2X16X32_0, + ICLASS_IVP_MULUSN_2X16X32_0, + ICLASS_IVP_MULSUN_2X16X32_0, + ICLASS_IVP_MULN_2X16X32_1, + ICLASS_IVP_MULUUN_2X16X32_1, + ICLASS_IVP_MULUSN_2X16X32_1, + ICLASS_IVP_MULSUN_2X16X32_1, + ICLASS_IVP_MULHN_2X16X32_1, + ICLASS_IVP_MULUUHN_2X16X32_1, + ICLASS_IVP_MULUSHN_2X16X32_1, + ICLASS_IVP_MULSUHN_2X16X32_1, + ICLASS_IVP_MULAN_2X16X32_0, + ICLASS_IVP_MULUUAN_2X16X32_0, + ICLASS_IVP_MULUSAN_2X16X32_0, + ICLASS_IVP_MULSUAN_2X16X32_0, + ICLASS_IVP_MULAHN_2X16X32_1, + ICLASS_IVP_MULUUAHN_2X16X32_1, + ICLASS_IVP_MULUSAHN_2X16X32_1, + ICLASS_IVP_MULSUAHN_2X16X32_1, + ICLASS_IVP_MULAN_2X16X32_1, + ICLASS_IVP_MULUUAN_2X16X32_1, + ICLASS_IVP_MULUSAN_2X16X32_1, + ICLASS_IVP_MULSUAN_2X16X32_1, + ICLASS_IVP_MULSHN_2X16X32_1, + ICLASS_IVP_MULUUSHN_2X16X32_1, + ICLASS_IVP_MULUSSHN_2X16X32_1, + ICLASS_IVP_MULSUSHN_2X16X32_1, + ICLASS_IVP_MULSN_2X16X32_0, + ICLASS_IVP_MULUUSN_2X16X32_0, + ICLASS_IVP_MULUSSN_2X16X32_0, + ICLASS_IVP_MULSUSN_2X16X32_0, + ICLASS_IVP_MULSN_2X16X32_1, + ICLASS_IVP_MULUUSN_2X16X32_1, + ICLASS_IVP_MULUSSN_2X16X32_1, + ICLASS_IVP_MULSUSN_2X16X32_1, + ICLASS_IVP_PACKLN_2X96, + ICLASS_IVP_PACKHN_2X64W, + ICLASS_IVP_PACKVRN_2X64W, + ICLASS_IVP_PACKVRNRN_2X64W, + ICLASS_IVP_PACKVRNX48_0, + ICLASS_IVP_PACKVRNX48_1, + ICLASS_IVP_PACKVRNRNX48_0, + ICLASS_IVP_PACKVRNRNX48_1, + ICLASS_IVP_PACKVRNRNX48, + ICLASS_IVP_PACKVRNR2NX24, + ICLASS_IVP_L2A4NX8_IP, + ICLASS_IVP_L2AU2NX8_IP, + ICLASS_IVP_L2U2NX8_XP, + ICLASS_IVP_AVGU2NX8, + ICLASS_IVP_AVGRU2NX8, + ICLASS_IVP_RADD2NX8, + ICLASS_IVP_RADD2NX8T, + ICLASS_IVP_RADDUNX16, + ICLASS_IVP_RADDUNX16T, + ICLASS_IVP_RADDU2NX8, + ICLASS_IVP_RADDU2NX8T, + ICLASS_IVP_LTRS2N, + ICLASS_IVP_LTRSN, + ICLASS_IVP_LTRSN_2, + ICLASS_IVP_SEQ2NX8, + ICLASS_IVP_SEQN_2X32, + ICLASS_IVP_EXTRN_2X32, + ICLASS_IVP_UNPKU2NX8_0, + ICLASS_IVP_UNPKU2NX8_1, + ICLASS_IVP_BADDNORMNX16, + ICLASS_IVP_BSUBNORMNX16, + ICLASS_IVP_RADDSNX16, + ICLASS_IVP_RADDSNX16T, + ICLASS_IVP_ORNOTB, + ICLASS_IVP_EXTR2NX8, + ICLASS_IVP_EXTRVRN_2X32, + ICLASS_IVP_MOVAV8, + ICLASS_IVP_MULPN16XR16, + ICLASS_IVP_MULPAN16XR16, + ICLASS_IVP_MULUSPN16XR16, + ICLASS_IVP_MULUSPAN16XR16, + ICLASS_IVP_MULP2N8XR16, + ICLASS_IVP_MULPA2N8XR16, + ICLASS_IVP_MULUSP2N8XR16, + ICLASS_IVP_MULUSPA2N8XR16, + ICLASS_IVP_MULPNX16, + ICLASS_IVP_MULPANX16, + ICLASS_IVP_MULUSPNX16, + ICLASS_IVP_MULUSPANX16, + ICLASS_IVP_MULUUPNX16, + ICLASS_IVP_MULUUPANX16, + ICLASS_IVP_MULP2NX8, + ICLASS_IVP_MULPA2NX8, + ICLASS_IVP_MULUSP2NX8, + ICLASS_IVP_MULUSPA2NX8, + ICLASS_IVP_MULUUP2NX8, + ICLASS_IVP_MULUUPA2NX8, + ICLASS_IVP_MULPI2NR8X16, + ICLASS_IVP_MULPAI2NR8X16, + ICLASS_IVP_MULUSPI2NR8X16, + ICLASS_IVP_MULUSPAI2NR8X16, + ICLASS_IVP_MULQ2N8XR8, + ICLASS_IVP_MULQA2N8XR8, + ICLASS_IVP_MULUSQ2N8XR8, + ICLASS_IVP_MULUSQA2N8XR8, + ICLASS_IVP_MUL4T2N8XR8, + ICLASS_IVP_MUL4TA2N8XR8, + ICLASS_IVP_MULUS4T2N8XR8, + ICLASS_IVP_MULUS4TA2N8XR8, + ICLASS_IVP_ADDWNX16, + ICLASS_IVP_ADDWANX16, + ICLASS_IVP_ADDWSNX16, + ICLASS_IVP_ADDWUNX16, + ICLASS_IVP_ADDWUANX16, + ICLASS_IVP_ADDWUSNX16, + ICLASS_IVP_SUBWNX16, + ICLASS_IVP_SUBWANX16, + ICLASS_IVP_SUBWUNX16, + ICLASS_IVP_SUBWUANX16, + ICLASS_IVP_SUBW2NX8, + ICLASS_IVP_SUBWA2NX8, + ICLASS_IVP_SUBWU2NX8, + ICLASS_IVP_SUBWUA2NX8, + ICLASS_IVP_RANDB2N, + ICLASS_IVP_RORB2N, + ICLASS_IVP_RANDBN, + ICLASS_IVP_RORBN, + ICLASS_IVP_RANDBN_2, + ICLASS_IVP_RORBN_2, + ICLASS_IVP_AVGNX16, + ICLASS_IVP_AVGUNX16, + ICLASS_IVP_AVG2NX8, + ICLASS_IVP_AVGR2NX8, + ICLASS_IVP_AVGRNX16, + ICLASS_IVP_AVGRUNX16, + ICLASS_IVP_GATHERANX8U, + ICLASS_IVP_GATHERANX16, + ICLASS_IVP_GATHERAN_2X32, + ICLASS_IVP_GATHERANX8UT, + ICLASS_IVP_GATHERANX16T, + ICLASS_IVP_GATHERAN_2X32T, + ICLASS_IVP_GATHERDNX16, + ICLASS_IVP_GATHERDNX8S, + ICLASS_IVP_GATHERD2NX8_L, + ICLASS_IVP_GATHERD2NX8_H, + ICLASS_IVP_MOVGATHERD, + ICLASS_IVP_SCATTERNX8U, + ICLASS_IVP_SCATTER2NX8_L, + ICLASS_IVP_SCATTER2NX8_H, + ICLASS_IVP_SCATTERNX16, + ICLASS_IVP_SCATTERN_2X32, + ICLASS_IVP_SCATTERNX8UT, + ICLASS_IVP_SCATTER2NX8T_L, + ICLASS_IVP_SCATTER2NX8T_H, + ICLASS_IVP_SCATTERNX16T, + ICLASS_IVP_SCATTERN_2X32T, + ICLASS_IVP_SCATTERW, + ICLASS_IVP_COUNTEQZ4NX8, + ICLASS_IVP_COUNTEQ4NX8, + ICLASS_IVP_COUNTEQMZ4NX8, + ICLASS_IVP_COUNTEQM4NX8, + ICLASS_IVP_COUNTLEZ4NX8, + ICLASS_IVP_COUNTLE4NX8, + ICLASS_IVP_COUNTLEMZ4NX8, + ICLASS_IVP_COUNTLEM4NX8, + ICLASS_IVP_LSR2NX8_I, + ICLASS_IVP_LSR2NX8_IP, + ICLASS_IVP_LSR2NX8_X, + ICLASS_IVP_LSR2NX8_XP, + ICLASS_IVP_LSRNX16_I, + ICLASS_IVP_LSRNX16_IP, + ICLASS_IVP_LSRNX16_X, + ICLASS_IVP_LSRNX16_XP, + ICLASS_IVP_LSRN_2X32_I, + ICLASS_IVP_LSRN_2X32_IP, + ICLASS_IVP_LSRN_2X32_X, + ICLASS_IVP_LSRN_2X32_XP, + ICLASS_IVP_ABSNX16, + ICLASS_IVP_ABSSNX16, + ICLASS_IVP_ABSSUBNX16, + ICLASS_IVP_ABSSUBUNX16, + ICLASS_IVP_ABSSSUBNX16, + ICLASS_xt_iclass_excw, + ICLASS_xt_iclass_rfe, + ICLASS_xt_iclass_rfde, + ICLASS_xt_iclass_syscall, + ICLASS_xt_iclass_call12, + ICLASS_xt_iclass_call8, + ICLASS_xt_iclass_call4, + ICLASS_xt_iclass_callx12, + ICLASS_xt_iclass_callx8, + ICLASS_xt_iclass_callx4, + ICLASS_xt_iclass_entry, + ICLASS_xt_iclass_movsp, + ICLASS_xt_iclass_rotw, + ICLASS_xt_iclass_retw, + ICLASS_xt_iclass_rfwou, + ICLASS_xt_iclass_l32e, + ICLASS_xt_iclass_s32e, + ICLASS_xt_iclass_rsr_windowbase, + ICLASS_xt_iclass_wsr_windowbase, + ICLASS_xt_iclass_xsr_windowbase, + ICLASS_xt_iclass_rsr_windowstart, + ICLASS_xt_iclass_wsr_windowstart, + ICLASS_xt_iclass_xsr_windowstart, + ICLASS_xt_iclass_add_n, + ICLASS_xt_iclass_addi_n, + ICLASS_xt_iclass_bz6, + ICLASS_xt_iclass_ill_n, + ICLASS_xt_iclass_loadi4, + ICLASS_xt_iclass_mov_n, + ICLASS_xt_iclass_movi_n, + ICLASS_xt_iclass_nopn, + ICLASS_xt_iclass_retn, + ICLASS_xt_iclass_storei4, + ICLASS_rur_threadptr, + ICLASS_wur_threadptr, + ICLASS_xt_iclass_addi, + ICLASS_xt_iclass_addmi, + ICLASS_xt_iclass_addsub, + ICLASS_xt_iclass_bit, + ICLASS_xt_iclass_bsi8, + ICLASS_xt_iclass_bsi8b, + ICLASS_xt_iclass_bsi8u, + ICLASS_xt_iclass_bst8, + ICLASS_xt_iclass_bsz12, + ICLASS_xt_iclass_call0, + ICLASS_xt_iclass_callx0, + ICLASS_xt_iclass_const16, + ICLASS_xt_iclass_exti, + ICLASS_xt_iclass_ill, + ICLASS_xt_iclass_jump, + ICLASS_xt_iclass_jumpx, + ICLASS_xt_iclass_l16ui, + ICLASS_xt_iclass_l16si, + ICLASS_xt_iclass_l32i, + ICLASS_xt_iclass_l32r, + ICLASS_xt_iclass_l8i, + ICLASS_xt_iclass_loop, + ICLASS_xt_iclass_loopz, + ICLASS_xt_iclass_movi, + ICLASS_xt_iclass_movz, + ICLASS_xt_iclass_neg, + ICLASS_xt_iclass_nop, + ICLASS_xt_iclass_l32ex, + ICLASS_xt_iclass_s32ex, + ICLASS_xt_iclass_getex, + ICLASS_xt_iclass_clrex, + ICLASS_xt_iclass_return, + ICLASS_xt_iclass_simcall, + ICLASS_xt_iclass_s16i, + ICLASS_xt_iclass_s32i, + ICLASS_xt_iclass_s32nb, + ICLASS_xt_iclass_s8i, + ICLASS_xt_iclass_sar, + ICLASS_xt_iclass_sari, + ICLASS_xt_iclass_shifts, + ICLASS_xt_iclass_shiftst, + ICLASS_xt_iclass_shiftt, + ICLASS_xt_iclass_slli, + ICLASS_xt_iclass_srai, + ICLASS_xt_iclass_srli, + ICLASS_xt_iclass_memw, + ICLASS_xt_iclass_extw, + ICLASS_xt_iclass_isync, + ICLASS_xt_iclass_sync, + ICLASS_xt_iclass_rsil, + ICLASS_xt_iclass_rsr_lend, + ICLASS_xt_iclass_wsr_lend, + ICLASS_xt_iclass_xsr_lend, + ICLASS_xt_iclass_rsr_lcount, + ICLASS_xt_iclass_wsr_lcount, + ICLASS_xt_iclass_xsr_lcount, + ICLASS_xt_iclass_rsr_lbeg, + ICLASS_xt_iclass_wsr_lbeg, + ICLASS_xt_iclass_xsr_lbeg, + ICLASS_xt_iclass_rsr_sar, + ICLASS_xt_iclass_wsr_sar, + ICLASS_xt_iclass_xsr_sar, + ICLASS_xt_iclass_rsr_memctl, + ICLASS_xt_iclass_wsr_memctl, + ICLASS_xt_iclass_xsr_memctl, + ICLASS_xt_iclass_rsr_litbase, + ICLASS_xt_iclass_wsr_litbase, + ICLASS_xt_iclass_xsr_litbase, + ICLASS_xt_iclass_rsr_configid0, + ICLASS_xt_iclass_wsr_configid0, + ICLASS_xt_iclass_rsr_configid1, + ICLASS_xt_iclass_rsr_ps, + ICLASS_xt_iclass_wsr_ps, + ICLASS_xt_iclass_xsr_ps, + ICLASS_xt_iclass_rsr_epc1, + ICLASS_xt_iclass_wsr_epc1, + ICLASS_xt_iclass_xsr_epc1, + ICLASS_xt_iclass_rsr_excsave1, + ICLASS_xt_iclass_wsr_excsave1, + ICLASS_xt_iclass_xsr_excsave1, + ICLASS_xt_iclass_rsr_epc2, + ICLASS_xt_iclass_wsr_epc2, + ICLASS_xt_iclass_xsr_epc2, + ICLASS_xt_iclass_rsr_excsave2, + ICLASS_xt_iclass_wsr_excsave2, + ICLASS_xt_iclass_xsr_excsave2, + ICLASS_xt_iclass_rsr_epc3, + ICLASS_xt_iclass_wsr_epc3, + ICLASS_xt_iclass_xsr_epc3, + ICLASS_xt_iclass_rsr_excsave3, + ICLASS_xt_iclass_wsr_excsave3, + ICLASS_xt_iclass_xsr_excsave3, + ICLASS_xt_iclass_rsr_epc4, + ICLASS_xt_iclass_wsr_epc4, + ICLASS_xt_iclass_xsr_epc4, + ICLASS_xt_iclass_rsr_excsave4, + ICLASS_xt_iclass_wsr_excsave4, + ICLASS_xt_iclass_xsr_excsave4, + ICLASS_xt_iclass_rsr_eps2, + ICLASS_xt_iclass_wsr_eps2, + ICLASS_xt_iclass_xsr_eps2, + ICLASS_xt_iclass_rsr_eps3, + ICLASS_xt_iclass_wsr_eps3, + ICLASS_xt_iclass_xsr_eps3, + ICLASS_xt_iclass_rsr_eps4, + ICLASS_xt_iclass_wsr_eps4, + ICLASS_xt_iclass_xsr_eps4, + ICLASS_xt_iclass_rsr_excvaddr, + ICLASS_xt_iclass_wsr_excvaddr, + ICLASS_xt_iclass_xsr_excvaddr, + ICLASS_xt_iclass_rsr_depc, + ICLASS_xt_iclass_wsr_depc, + ICLASS_xt_iclass_xsr_depc, + ICLASS_xt_iclass_rsr_exccause, + ICLASS_xt_iclass_wsr_exccause, + ICLASS_xt_iclass_xsr_exccause, + ICLASS_xt_iclass_rsr_prid, + ICLASS_xt_iclass_rsr_vecbase, + ICLASS_xt_iclass_wsr_vecbase, + ICLASS_xt_iclass_xsr_vecbase, + ICLASS_xt_iclass_rsr_mpucfg, + ICLASS_xt_iclass_wsr_mpucfg, + ICLASS_xt_iclass_rsr_gserr, + ICLASS_xt_iclass_wsr_gserr, + ICLASS_xt_iclass_xsr_gserr, + ICLASS_xt_iclass_salt, + ICLASS_xt_mul16, + ICLASS_xt_mul32, + ICLASS_xt_mul32h, + ICLASS_xt_iclass_rfi, + ICLASS_xt_iclass_wait, + ICLASS_xt_iclass_rsr_interrupt, + ICLASS_xt_iclass_wsr_intset, + ICLASS_xt_iclass_wsr_intclear, + ICLASS_xt_iclass_rsr_intenable, + ICLASS_xt_iclass_wsr_intenable, + ICLASS_xt_iclass_xsr_intenable, + ICLASS_xt_iclass_break, + ICLASS_xt_iclass_break_n, + ICLASS_xt_iclass_rsr_dbreaka0, + ICLASS_xt_iclass_wsr_dbreaka0, + ICLASS_xt_iclass_xsr_dbreaka0, + ICLASS_xt_iclass_rsr_dbreakc0, + ICLASS_xt_iclass_wsr_dbreakc0, + ICLASS_xt_iclass_xsr_dbreakc0, + ICLASS_xt_iclass_rsr_ibreaka0, + ICLASS_xt_iclass_wsr_ibreaka0, + ICLASS_xt_iclass_xsr_ibreaka0, + ICLASS_xt_iclass_rsr_ibreakenable, + ICLASS_xt_iclass_wsr_ibreakenable, + ICLASS_xt_iclass_xsr_ibreakenable, + ICLASS_xt_iclass_rsr_debugcause, + ICLASS_xt_iclass_wsr_debugcause, + ICLASS_xt_iclass_xsr_debugcause, + ICLASS_xt_iclass_rsr_icount, + ICLASS_xt_iclass_wsr_icount, + ICLASS_xt_iclass_xsr_icount, + ICLASS_xt_iclass_rsr_icountlevel, + ICLASS_xt_iclass_wsr_icountlevel, + ICLASS_xt_iclass_xsr_icountlevel, + ICLASS_xt_iclass_rsr_ddr, + ICLASS_xt_iclass_wsr_ddr, + ICLASS_xt_iclass_xsr_ddr, + ICLASS_xt_iclass_lddr32_p, + ICLASS_xt_iclass_sddr32_p, + ICLASS_xt_iclass_rfdo, + ICLASS_xt_iclass_rfdd, + ICLASS_xt_iclass_wsr_mmid, + ICLASS_xt_iclass_bbool1, + ICLASS_xt_iclass_bbool4, + ICLASS_xt_iclass_bbool8, + ICLASS_xt_iclass_bbranch, + ICLASS_xt_iclass_bmove, + ICLASS_xt_iclass_RSR_BR, + ICLASS_xt_iclass_WSR_BR, + ICLASS_xt_iclass_XSR_BR, + ICLASS_xt_iclass_rsr_ccount, + ICLASS_xt_iclass_wsr_ccount, + ICLASS_xt_iclass_xsr_ccount, + ICLASS_xt_iclass_rsr_ccompare0, + ICLASS_xt_iclass_wsr_ccompare0, + ICLASS_xt_iclass_xsr_ccompare0, + ICLASS_xt_iclass_rsr_ccompare1, + ICLASS_xt_iclass_wsr_ccompare1, + ICLASS_xt_iclass_xsr_ccompare1, + ICLASS_xt_iclass_icache, + ICLASS_xt_iclass_icache_lock, + ICLASS_xt_iclass_icache_inv, + ICLASS_xt_iclass_licx, + ICLASS_xt_iclass_sicx, + ICLASS_xt_iclass_wsr_cacheadrdis, + ICLASS_xt_iclass_rsr_cacheadrdis, + ICLASS_xt_iclass_xsr_cacheadrdis, + ICLASS_xt_iclass_rptlb0, + ICLASS_xt_iclass_rptlb, + ICLASS_xt_iclass_wptlb, + ICLASS_xt_iclass_rsr_mpuenb, + ICLASS_xt_iclass_wsr_mpuenb, + ICLASS_xt_iclass_xsr_mpuenb, + ICLASS_xt_iclass_rsr_cpenable, + ICLASS_xt_iclass_wsr_cpenable, + ICLASS_xt_iclass_xsr_cpenable, + ICLASS_xt_iclass_clamp, + ICLASS_xt_iclass_minmax, + ICLASS_xt_iclass_nsa, + ICLASS_xt_iclass_sx, + ICLASS_xt_iclass_l32ai, + ICLASS_xt_iclass_s32ri, + ICLASS_xt_iclass_rsr_atomctl, + ICLASS_xt_iclass_wsr_atomctl, + ICLASS_xt_iclass_xsr_atomctl, + ICLASS_xt_iclass_div, + ICLASS_xt_iclass_rsr_eraccess, + ICLASS_xt_iclass_wsr_eraccess, + ICLASS_xt_iclass_xsr_eraccess, + ICLASS_xt_iclass_rer, + ICLASS_xt_iclass_wer, + ICLASS_xt_iclass_wb15_0, + ICLASS_xt_iclass_wb15_1, + ICLASS_xt_iclass_wb15_2, + ICLASS_xt_iclass_wb15_3, + ICLASS_xt_iclass_wb15_4, + ICLASS_MTK_AndPOPC, + ICLASS_iq_tie2apb_inq0_pop, + ICLASS_iq_tie2apb_inq0_is_ready, + ICLASS_iq_tie2apb_inq0_nonblocking_peek, + ICLASS_iq_tie2apb_inq0_nonblocking_pop, + ICLASS_iq_tie2apb_inq0_blocking_peek, + ICLASS_oq_tie2apb_outq0_push_read, + ICLASS_oq_tie2apb_outq0_push_write, + ICLASS_oq_tie2apb_outq0_is_ready, + ICLASS_oq_tie2apb_outq0_nonblocking_push_read, + ICLASS_oq_tie2apb_outq0_nonblocking_push_write, + ICLASS_rur_apb_pipe, + ICLASS_wur_apb_pipe +}; + + +/* Opcode encodings. */ + +static void +Opcode_ivp_repnx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8200070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_repnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30502020; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_repnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100020; +} + +static void +Opcode_ivp_repnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe60000; +} + +static void +Opcode_ivp_repnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000020; +} + +static void +Opcode_ivp_repnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c03400; +} + +static void +Opcode_ivp_repnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800320; +} + +static void +Opcode_ivp_repnx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800020; +} + +static void +Opcode_ivp_repnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400020; +} + +static void +Opcode_ivp_repnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c204020; +} + +static void +Opcode_ivp_repnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce0000; +} + +static void +Opcode_ivp_repnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800182; +} + +static void +Opcode_ivp_selsnx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_selsnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30502030; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_selsnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100030; +} + +static void +Opcode_ivp_selsnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe68000; +} + +static void +Opcode_ivp_selsnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000030; +} + +static void +Opcode_ivp_selsnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d03400; +} + +static void +Opcode_ivp_selsnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800330; +} + +static void +Opcode_ivp_selsnx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800030; +} + +static void +Opcode_ivp_selsnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400030; +} + +static void +Opcode_ivp_selsnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c204030; +} + +static void +Opcode_ivp_selsnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce8000; +} + +static void +Opcode_ivp_selsnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800183; +} + +static void +Opcode_ivp_rep2nx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rep2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30502000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rep2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ivp_rep2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_ivp_rep2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000000; +} + +static void +Opcode_ivp_rep2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c03800; +} + +static void +Opcode_ivp_rep2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800300; +} + +static void +Opcode_ivp_rep2nx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ivp_rep2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400000; +} + +static void +Opcode_ivp_rep2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c204000; +} + +static void +Opcode_ivp_rep2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae0000; +} + +static void +Opcode_ivp_rep2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800180; +} + +static void +Opcode_ivp_sels2nx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8100070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sels2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30502010; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sels2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100010; +} + +static void +Opcode_ivp_sels2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_ivp_sels2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000010; +} + +static void +Opcode_ivp_sels2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d03800; +} + +static void +Opcode_ivp_sels2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800310; +} + +static void +Opcode_ivp_sels2nx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800010; +} + +static void +Opcode_ivp_sels2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400010; +} + +static void +Opcode_ivp_sels2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c204010; +} + +static void +Opcode_ivp_sels2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf0000; +} + +static void +Opcode_ivp_sels2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800181; +} + +static void +Opcode_ivp_repn_2x32_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8300070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_repn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34502020; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_repn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180020; +} + +static void +Opcode_ivp_repn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe88000; +} + +static void +Opcode_ivp_repn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000024; +} + +static void +Opcode_ivp_repn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c84400; +} + +static void +Opcode_ivp_repn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800324; +} + +static void +Opcode_ivp_repn_2x32_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880020; +} + +static void +Opcode_ivp_repn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9500020; +} + +static void +Opcode_ivp_repn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c304020; +} + +static void +Opcode_ivp_repn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd18000; +} + +static void +Opcode_ivp_repn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001c2; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8340070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34502030; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180030; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80008; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000034; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04400; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800334; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880030; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9500030; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c304030; +} + +static void +Opcode_ivp_selsn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd1c000; +} + +static void +Opcode_ivp_selsn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001c3; +} + +static void +Opcode_ivp_ext0ib_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1708c0; +} + +static void +Opcode_ivp_ext0ib_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ext0ib_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261840; +} + +static void +Opcode_ivp_ext0ib_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000100; +} + +static void +Opcode_ivp_ext0ib_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261800; +} + +static void +Opcode_ivp_ext0ib_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800000; +} + +static void +Opcode_ivp_ext0ib_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8808; +} + +static void +Opcode_ivp_ext0ib_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9810008; +} + +static void +Opcode_ivp_ext0ib_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0810; +} + +static void +Opcode_ivp_ext0ib_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd820e0; +} + +static void +Opcode_ivp_ext0ib_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6808; +} + +static void +Opcode_ivp_notb_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1708d3; +} + +static void +Opcode_ivp_notb_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0032; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_notb_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261851; +} + +static void +Opcode_ivp_notb_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30001b0; +} + +static void +Opcode_ivp_notb_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261813; +} + +static void +Opcode_ivp_notb_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000b0; +} + +static void +Opcode_ivp_notb_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1803; +} + +static void +Opcode_ivp_notb_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98100b8; +} + +static void +Opcode_ivp_notb_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8819; +} + +static void +Opcode_ivp_notb_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0160c2; +} + +static void +Opcode_ivp_notb_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0410; +} + +static void +Opcode_ivp_notb_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd828e2; +} + +static void +Opcode_ivp_notb_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3813; +} + +static void +Opcode_ivp_andb_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x171078; +} + +static void +Opcode_ivp_andb_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260840; +} + +static void +Opcode_ivp_andb_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260800; +} + +static void +Opcode_ivp_andb_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19f800; +} + +static void +Opcode_ivp_andb_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab800; +} + +static void +Opcode_ivp_andb_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cb810; +} + +static void +Opcode_ivp_orb_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1718c0; +} + +static void +Opcode_ivp_orb_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261848; +} + +static void +Opcode_ivp_orb_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261808; +} + +static void +Opcode_ivp_orb_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9808; +} + +static void +Opcode_ivp_orb_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab010; +} + +static void +Opcode_ivp_orb_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c7808; +} + +static void +Opcode_ivp_xorb_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1710c8; +} + +static void +Opcode_ivp_xorb_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261050; +} + +static void +Opcode_ivp_xorb_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261010; +} + +static void +Opcode_ivp_xorb_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9018; +} + +static void +Opcode_ivp_xorb_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa818; +} + +static void +Opcode_ivp_xorb_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c7018; +} + +static void +Opcode_ivp_andnotb_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x171878; +} + +static void +Opcode_ivp_andnotb_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260848; +} + +static void +Opcode_ivp_andnotb_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260808; +} + +static void +Opcode_ivp_andnotb_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19f808; +} + +static void +Opcode_ivp_andnotb_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab808; +} + +static void +Opcode_ivp_andnotb_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cb818; +} + +static void +Opcode_ivp_mb_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1708d2; +} + +static void +Opcode_ivp_mb_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0022; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mb_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261850; +} + +static void +Opcode_ivp_mb_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30001a0; +} + +static void +Opcode_ivp_mb_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261812; +} + +static void +Opcode_ivp_mb_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000a0; +} + +static void +Opcode_ivp_mb_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1003; +} + +static void +Opcode_ivp_mb_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98100a8; +} + +static void +Opcode_ivp_mb_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8019; +} + +static void +Opcode_ivp_mb_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c016082; +} + +static void +Opcode_ivp_mb_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0410; +} + +static void +Opcode_ivp_mb_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd828e0; +} + +static void +Opcode_ivp_mb_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800281; +} + +static void +Opcode_ivp_mb_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3013; +} + +static void +Opcode_ivp_ltrn_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1701e0; +} + +static void +Opcode_ivp_ltrn_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260760; +} + +static void +Opcode_ivp_ltrn_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260720; +} + +static void +Opcode_ivp_ltrn_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0710; +} + +static void +Opcode_ivp_ltrn_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae700; +} + +static void +Opcode_ivp_ltrn_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0110; +} + +static void +Opcode_ivp_ltrn_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc710; +} + +static void +Opcode_ivp_ltrni_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1718c8; +} + +static void +Opcode_ivp_ltrni_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260060; +} + +static void +Opcode_ivp_ltrni_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260020; +} + +static void +Opcode_ivp_ltrni_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0400; +} + +static void +Opcode_ivp_ltrni_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae000; +} + +static void +Opcode_ivp_ltrni_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c10; +} + +static void +Opcode_ivp_ltrni_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc010; +} + +static void +Opcode_ivp_lbn_i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170040; +} + +static void +Opcode_ivp_lbn_i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a000; +} + +static void +Opcode_ivp_lbn_i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a000; +} + +static void +Opcode_ivp_lbn_i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a000; +} + +static void +Opcode_ivp_lbn_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x171060; +} + +static void +Opcode_ivp_lbn_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19d000; +} + +static void +Opcode_ivp_lbn_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa000; +} + +static void +Opcode_ivp_lbn_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca010; +} + +static void +Opcode_ivp_sbn_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a20080; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sbn_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1120060; +} + +static void +Opcode_ivp_sbn_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0800; +} + +static void +Opcode_ivp_sbn_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e0020; +} + +static void +Opcode_ivp_sbn_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800080; +} + +static void +Opcode_ivp_sbn_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f1080; +} + +static void +Opcode_ivp_sbn_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a200e0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sbn_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100d0; +} + +static void +Opcode_ivp_sbn_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0e00; +} + +static void +Opcode_ivp_sbn_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8300d0; +} + +static void +Opcode_ivp_sbn_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000e0; +} + +static void +Opcode_ivp_sbn_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f10e0; +} + +static void +Opcode_ivp_lsnx16_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10860000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsnx16_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0000; +} + +static void +Opcode_ivp_lsnx16_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18e000; +} + +static void +Opcode_ivp_lsnx16_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18e000; +} + +static void +Opcode_ivp_lsnx16_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x960000; +} + +static void +Opcode_ivp_lsnx16_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10548000; +} + +static void +Opcode_ivp_lsnx16_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10972000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsnx16_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1392000; +} + +static void +Opcode_ivp_lsnx16_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_ivp_lsnx16_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_ivp_lsnx16_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa72000; +} + +static void +Opcode_ivp_lsnx16_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b0000; +} + +static void +Opcode_ivp_lsnx16_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108cc000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsnx16_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf4000; +} + +static void +Opcode_ivp_lsnx16_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fa000; +} + +static void +Opcode_ivp_lsnx16_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea000; +} + +static void +Opcode_ivp_lsnx16_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9cc000; +} + +static void +Opcode_ivp_lsnx16_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057c000; +} + +static void +Opcode_ivp_lsnx16_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108ce000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsnx16_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdfc000; +} + +static void +Opcode_ivp_lsnx16_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc000; +} + +static void +Opcode_ivp_lsnx16_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fa000; +} + +static void +Opcode_ivp_lsnx16_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ce000; +} + +static void +Opcode_ivp_lsnx16_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057e000; +} + +static void +Opcode_ivp_movbrbv_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a45000d; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movbrbv_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100500; +} + +static void +Opcode_ivp_movbrbv_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3900400; +} + +static void +Opcode_ivp_movbrbv_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9810108; +} + +static void +Opcode_ivp_movbrbv_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c016000; +} + +static void +Opcode_ivp_movbrbv_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcfc00d; +} + +static void +Opcode_ivp_movbrbv_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e88010; +} + +static void +Opcode_ivp_movbvbr_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x217c0c80; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movbvbr_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28f838c; +} + +static void +Opcode_ivp_movbvbr_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28f828c; +} + +static void +Opcode_ivp_movbvbr_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9882200; +} + +static void +Opcode_ivp_movbvbr_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606e0e; +} + +static void +Opcode_ivp_movbvbr_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0200; +} + +static void +Opcode_ivp_movbvbr_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800080; +} + +static void +Opcode_ivp_joinb_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1710c0; +} + +static void +Opcode_ivp_joinb_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261048; +} + +static void +Opcode_ivp_joinb_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261008; +} + +static void +Opcode_ivp_joinb_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9008; +} + +static void +Opcode_ivp_joinb_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa810; +} + +static void +Opcode_ivp_joinb_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c7008; +} + +static void +Opcode_ivp_ltrn_2_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1702e0; +} + +static void +Opcode_ivp_ltrn_2_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260860; +} + +static void +Opcode_ivp_ltrn_2_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260820; +} + +static void +Opcode_ivp_ltrn_2_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2400; +} + +static void +Opcode_ivp_ltrn_2_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae800; +} + +static void +Opcode_ivp_ltrn_2_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0210; +} + +static void +Opcode_ivp_ltrn_2_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc500; +} + +static void +Opcode_ivp_ltrn_2i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700d0; +} + +static void +Opcode_ivp_ltrn_2i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260460; +} + +static void +Opcode_ivp_ltrn_2i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260420; +} + +static void +Opcode_ivp_ltrn_2i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0410; +} + +static void +Opcode_ivp_ltrn_2i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae400; +} + +static void +Opcode_ivp_ltrn_2i_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0010; +} + +static void +Opcode_ivp_ltrn_2i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc410; +} + +static void +Opcode_ivp_lbn_2_i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x171000; +} + +static void +Opcode_ivp_lbn_2_i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_ivp_lbn_2_i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_ivp_lbn_2_i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_ivp_lbn_2_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x171050; +} + +static void +Opcode_ivp_lbn_2_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19b000; +} + +static void +Opcode_ivp_lbn_2_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193010; +} + +static void +Opcode_ivp_lbn_2_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9010; +} + +static void +Opcode_ivp_sbn_2_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a20040; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sbn_2_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1110060; +} + +static void +Opcode_ivp_sbn_2_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0400; +} + +static void +Opcode_ivp_sbn_2_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d0020; +} + +static void +Opcode_ivp_sbn_2_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800040; +} + +static void +Opcode_ivp_sbn_2_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f1040; +} + +static void +Opcode_ivp_sbn_2_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a200d0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sbn_2_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11110c0; +} + +static void +Opcode_ivp_sbn_2_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0d00; +} + +static void +Opcode_ivp_sbn_2_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8310c0; +} + +static void +Opcode_ivp_sbn_2_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000d0; +} + +static void +Opcode_ivp_sbn_2_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f10d0; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba0000; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0000; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0000; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ivp_lv2nx8_i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1098e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x164000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138c000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22e000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22e000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8e000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105be000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e2000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa26000; +} + +static void +Opcode_ivp_lv2nx8_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108f8000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1452000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20a000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x208000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f8000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x152000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10598000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x152000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a8000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96c000; +} + +static void +Opcode_ivp_lv2nx8_x_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x172000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108fa000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x152000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145a000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20a000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9fa000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1059a000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7aa000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96e000; +} + +static void +Opcode_ivp_lv2nx8_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174000; +} + +static void +Opcode_ivp_sv2nx8_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sv2nx8_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc60000; +} + +static void +Opcode_ivp_sv2nx8_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0000; +} + +static void +Opcode_ivp_sv2nx8_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0000; +} + +static void +Opcode_ivp_sv2nx8_i_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ivp_sv2nx8_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_ivp_sv2nx8_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x520000; +} + +static void +Opcode_ivp_sv2nx8_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109b6000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sv2nx8_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139e000; +} + +static void +Opcode_ivp_sv2nx8_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x588000; +} + +static void +Opcode_ivp_sv2nx8_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab6000; +} + +static void +Opcode_ivp_sv2nx8_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4000; +} + +static void +Opcode_ivp_sv2nx8_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7ec000; +} + +static void +Opcode_ivp_sv2nx8_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_ivp_sv2nx8_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10942000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sv2nx8_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14f2000; +} + +static void +Opcode_ivp_sv2nx8_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x568000; +} + +static void +Opcode_ivp_sv2nx8_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa42000; +} + +static void +Opcode_ivp_sv2nx8_x_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c000; +} + +static void +Opcode_ivp_sv2nx8_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7cc000; +} + +static void +Opcode_ivp_sv2nx8_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_ivp_sv2nx8_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10946000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sv2nx8_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14fa000; +} + +static void +Opcode_ivp_sv2nx8_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56a000; +} + +static void +Opcode_ivp_sv2nx8_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa46000; +} + +static void +Opcode_ivp_sv2nx8_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18e000; +} + +static void +Opcode_ivp_sv2nx8_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7ce000; +} + +static void +Opcode_ivp_sv2nx8_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa12000; +} + +static void +Opcode_ivp_ssnx16_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10898000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssnx16_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1218000; +} + +static void +Opcode_ivp_ssnx16_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x520000; +} + +static void +Opcode_ivp_ssnx16_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x998000; +} + +static void +Opcode_ivp_ssnx16_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109a6000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssnx16_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13bc000; +} + +static void +Opcode_ivp_ssnx16_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ivp_ssnx16_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa6000; +} + +static void +Opcode_ivp_ssnx16_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10922000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssnx16_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14b2000; +} + +static void +Opcode_ivp_ssnx16_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x558000; +} + +static void +Opcode_ivp_ssnx16_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa22000; +} + +static void +Opcode_ivp_ssnx16_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10926000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssnx16_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14ba000; +} + +static void +Opcode_ivp_ssnx16_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x55a000; +} + +static void +Opcode_ivp_ssnx16_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa26000; +} + +static void +Opcode_ivp_movva16_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc006; +} + +static void +Opcode_ivp_movva16_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282004; +} + +static void +Opcode_ivp_movva16_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282004; +} + +static void +Opcode_ivp_movva16_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8004; +} + +static void +Opcode_ivp_movva16_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8004; +} + +static void +Opcode_ivp_movva16_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6006; +} + +static void +Opcode_ivp_movvv_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a300a0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movvv_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27500c0e; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movvv_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11080e0; +} + +static void +Opcode_ivp_movvv_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf70060; +} + +static void +Opcode_ivp_movvv_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330700e; +} + +static void +Opcode_ivp_movvv_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f60006; +} + +static void +Opcode_ivp_movvv_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f07208; +} + +static void +Opcode_ivp_movvv_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8340e0; +} + +static void +Opcode_ivp_movvv_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94801c9; +} + +static void +Opcode_ivp_movvv_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a80c0; +} + +static void +Opcode_ivp_movvv_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606c0a; +} + +static void +Opcode_ivp_movvv_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20204; +} + +static void +Opcode_ivp_movvv_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8080; +} + +static void +Opcode_ivp_movvv_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d20c0; +} + +static void +Opcode_ivp_movvv_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2707140; +} + +static void +Opcode_ivp_movvv_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220c0; +} + +static void +Opcode_ivp_movvv_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500009; +} + +static void +Opcode_ivp_movvv_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa602c0; +} + +static void +Opcode_ivp_sllinx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21500c08; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sllinx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe78000; +} + +static void +Opcode_ivp_sllinx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300400e; +} + +static void +Opcode_ivp_sllinx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c84000; +} + +static void +Opcode_ivp_sllinx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04208; +} + +static void +Opcode_ivp_sllinx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940008e; +} + +static void +Opcode_ivp_sllinx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606008; +} + +static void +Opcode_ivp_sllinx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00200; +} + +static void +Opcode_ivp_sllinx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2404140; +} + +static void +Opcode_ivp_slsinx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23500c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_slsinx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe70008; +} + +static void +Opcode_ivp_slsinx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x310000e; +} + +static void +Opcode_ivp_slsinx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04000; +} + +static void +Opcode_ivp_slsinx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00208; +} + +static void +Opcode_ivp_slsinx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940000f; +} + +static void +Opcode_ivp_slsinx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606400; +} + +static void +Opcode_ivp_slsinx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd08000; +} + +static void +Opcode_ivp_slsinx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500140; +} + +static void +Opcode_ivp_srainx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srainx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23500c08; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srainx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1378000; +} + +static void +Opcode_ivp_srainx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe78008; +} + +static void +Opcode_ivp_srainx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x310400e; +} + +static void +Opcode_ivp_srainx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d84000; +} + +static void +Opcode_ivp_srainx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04208; +} + +static void +Opcode_ivp_srainx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0000; +} + +static void +Opcode_ivp_srainx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940008f; +} + +static void +Opcode_ivp_srainx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606408; +} + +static void +Opcode_ivp_srainx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd08200; +} + +static void +Opcode_ivp_srainx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2504140; +} + +static void +Opcode_ivp_srlinx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108c4000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srlinx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25500c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srlinx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1378200; +} + +static void +Opcode_ivp_srlinx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ivp_srlinx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000e; +} + +static void +Opcode_ivp_srlinx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04400; +} + +static void +Opcode_ivp_srlinx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00208; +} + +static void +Opcode_ivp_srlinx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c4000; +} + +static void +Opcode_ivp_srlinx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9480008; +} + +static void +Opcode_ivp_srlinx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606800; +} + +static void +Opcode_ivp_srlinx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_ivp_srlinx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2600140; +} + +static void +Opcode_ivp_sllnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e503800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sllnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500008; +} + +static void +Opcode_ivp_sllnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0030e; +} + +static void +Opcode_ivp_sllnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9700005; +} + +static void +Opcode_ivp_sllnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e406c00; +} + +static void +Opcode_ivp_sllnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc78000; +} + +static void +Opcode_ivp_sllnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29003e0; +} + +static void +Opcode_ivp_srlnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srlnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360000a; +} + +static void +Opcode_ivp_srlnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00202; +} + +static void +Opcode_ivp_srlnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9780006; +} + +static void +Opcode_ivp_srlnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e507000; +} + +static void +Opcode_ivp_srlnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ivp_srlnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2600000; +} + +static void +Opcode_ivp_slanx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38503800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_slanx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200008; +} + +static void +Opcode_ivp_slanx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0030e; +} + +static void +Opcode_ivp_slanx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9700002; +} + +static void +Opcode_ivp_slanx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e406000; +} + +static void +Opcode_ivp_slanx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc60000; +} + +static void +Opcode_ivp_slanx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e003c0; +} + +static void +Opcode_ivp_sranx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sranx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000a; +} + +static void +Opcode_ivp_sranx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00200; +} + +static void +Opcode_ivp_sranx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9780003; +} + +static void +Opcode_ivp_sranx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e506400; +} + +static void +Opcode_ivp_sranx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca8000; +} + +static void +Opcode_ivp_sranx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f003e0; +} + +static void +Opcode_ivp_slsnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c503c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_slsnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000a; +} + +static void +Opcode_ivp_slsnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00200; +} + +static void +Opcode_ivp_slsnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9780000; +} + +static void +Opcode_ivp_slsnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e407800; +} + +static void +Opcode_ivp_slsnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90000; +} + +static void +Opcode_ivp_slsnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c003e0; +} + +static void +Opcode_ivp_srsnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srsnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000c; +} + +static void +Opcode_ivp_srsnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00204; +} + +static void +Opcode_ivp_srsnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400008; +} + +static void +Opcode_ivp_srsnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e507800; +} + +static void +Opcode_ivp_srsnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd0000; +} + +static void +Opcode_ivp_srsnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400020; +} + +static void +Opcode_ivp_xor2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38502000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_xor2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1360000; +} + +static void +Opcode_ivp_xor2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda0000; +} + +static void +Opcode_ivp_xor2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100304; +} + +static void +Opcode_ivp_xor2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000b; +} + +static void +Opcode_ivp_xor2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00308; +} + +static void +Opcode_ivp_xor2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f0000e; +} + +static void +Opcode_ivp_xor2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0000; +} + +static void +Opcode_ivp_xor2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e307000; +} + +static void +Opcode_ivp_xor2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ivp_xor2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0000; +} + +static void +Opcode_ivp_xor2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a003a0; +} + +static void +Opcode_ivp_and2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a402c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_and2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1278000; +} + +static void +Opcode_ivp_and2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc78000; +} + +static void +Opcode_ivp_and2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0020a; +} + +static void +Opcode_ivp_and2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00016; +} + +static void +Opcode_ivp_and2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0010a; +} + +static void +Opcode_ivp_and2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e8000b; +} + +static void +Opcode_ivp_and2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c8000; +} + +static void +Opcode_ivp_and2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e007400; +} + +static void +Opcode_ivp_and2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb58000; +} + +static void +Opcode_ivp_and2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c8000; +} + +static void +Opcode_ivp_and2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d00280; +} + +static void +Opcode_ivp_or2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e403800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_or2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338000; +} + +static void +Opcode_ivp_or2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd78000; +} + +static void +Opcode_ivp_or2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x310020a; +} + +static void +Opcode_ivp_or2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0001a; +} + +static void +Opcode_ivp_or2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0020c; +} + +static void +Opcode_ivp_or2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e8000d; +} + +static void +Opcode_ivp_or2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x578000; +} + +static void +Opcode_ivp_or2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e207c00; +} + +static void +Opcode_ivp_or2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc18000; +} + +static void +Opcode_ivp_or2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x478000; +} + +static void +Opcode_ivp_or2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d00380; +} + +static void +Opcode_ivp_not2nx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a34010; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_not2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30602c02; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_not2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500210; +} + +static void +Opcode_ivp_not2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf480c0; +} + +static void +Opcode_ivp_not2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801106; +} + +static void +Opcode_ivp_not2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f68010; +} + +static void +Opcode_ivp_not2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001106; +} + +static void +Opcode_ivp_not2nx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb08010; +} + +static void +Opcode_ivp_not2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9580023; +} + +static void +Opcode_ivp_not2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8160; +} + +static void +Opcode_ivp_not2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606d0c; +} + +static void +Opcode_ivp_not2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20308; +} + +static void +Opcode_ivp_not2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8120; +} + +static void +Opcode_ivp_not2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000f00; +} + +static void +Opcode_ivp_addnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c402800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_addnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1260000; +} + +static void +Opcode_ivp_addnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc60000; +} + +static void +Opcode_ivp_addnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0020a; +} + +static void +Opcode_ivp_addnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00005; +} + +static void +Opcode_ivp_addnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0010a; +} + +static void +Opcode_ivp_addnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d0000b; +} + +static void +Opcode_ivp_addnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0000; +} + +static void +Opcode_ivp_addnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e006800; +} + +static void +Opcode_ivp_addnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb40000; +} + +static void +Opcode_ivp_addnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0000; +} + +static void +Opcode_ivp_addnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00280; +} + +static void +Opcode_ivp_subnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a403c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_subnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1348000; +} + +static void +Opcode_ivp_subnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd88000; +} + +static void +Opcode_ivp_subnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x310020e; +} + +static void +Opcode_ivp_subnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0001a; +} + +static void +Opcode_ivp_subnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0020e; +} + +static void +Opcode_ivp_subnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e8000f; +} + +static void +Opcode_ivp_subnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x588000; +} + +static void +Opcode_ivp_subnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e306400; +} + +static void +Opcode_ivp_subnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc28000; +} + +static void +Opcode_ivp_subnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x488000; +} + +static void +Opcode_ivp_subnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f00380; +} + +static void +Opcode_ivp_negnx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a300c0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27500e0e; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11082c0; +} + +static void +Opcode_ivp_negnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40080; +} + +static void +Opcode_ivp_negnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330780e; +} + +static void +Opcode_ivp_negnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f60007; +} + +static void +Opcode_ivp_negnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f07a08; +} + +static void +Opcode_ivp_negnx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8380e0; +} + +static void +Opcode_ivp_negnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94801e9; +} + +static void +Opcode_ivp_negnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8100; +} + +static void +Opcode_ivp_negnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606e0a; +} + +static void +Opcode_ivp_negnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20206; +} + +static void +Opcode_ivp_negnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a80c0; +} + +static void +Opcode_ivp_negnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2707940; +} + +static void +Opcode_ivp_minnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a403000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_minnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f8000; +} + +static void +Opcode_ivp_minnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd28000; +} + +static void +Opcode_ivp_minnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0020e; +} + +static void +Opcode_ivp_minnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190001f; +} + +static void +Opcode_ivp_minnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00202; +} + +static void +Opcode_ivp_minnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d0000f; +} + +static void +Opcode_ivp_minnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x538000; +} + +static void +Opcode_ivp_minnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e107c00; +} + +static void +Opcode_ivp_minnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd8000; +} + +static void +Opcode_ivp_minnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x438000; +} + +static void +Opcode_ivp_minnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b002e0; +} + +static void +Opcode_ivp_minunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c403400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_minunx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1310000; +} + +static void +Opcode_ivp_minunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd50000; +} + +static void +Opcode_ivp_minunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100200; +} + +static void +Opcode_ivp_minunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00009; +} + +static void +Opcode_ivp_minunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00208; +} + +static void +Opcode_ivp_minunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e0000c; +} + +static void +Opcode_ivp_minunx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x550000; +} + +static void +Opcode_ivp_minunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e206800; +} + +static void +Opcode_ivp_minunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf0000; +} + +static void +Opcode_ivp_minunx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x450000; +} + +static void +Opcode_ivp_minunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800380; +} + +static void +Opcode_ivp_maxnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_maxnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c8000; +} + +static void +Opcode_ivp_maxnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd8000; +} + +static void +Opcode_ivp_maxnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290020c; +} + +static void +Opcode_ivp_maxnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190001a; +} + +static void +Opcode_ivp_maxnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290010e; +} + +static void +Opcode_ivp_maxnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000d; +} + +static void +Opcode_ivp_maxnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x508000; +} + +static void +Opcode_ivp_maxnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e106400; +} + +static void +Opcode_ivp_maxnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba8000; +} + +static void +Opcode_ivp_maxnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_ivp_maxnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29002c0; +} + +static void +Opcode_ivp_maxunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c401800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_maxunx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e0000; +} + +static void +Opcode_ivp_maxunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ivp_maxunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0020c; +} + +static void +Opcode_ivp_maxunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000d; +} + +static void +Opcode_ivp_maxunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0010e; +} + +static void +Opcode_ivp_maxunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c8000e; +} + +static void +Opcode_ivp_maxunx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x520000; +} + +static void +Opcode_ivp_maxunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e107000; +} + +static void +Opcode_ivp_maxunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc0000; +} + +static void +Opcode_ivp_maxunx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_ivp_maxunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e002c0; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38403800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1320000; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd60000; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100204; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00009; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0020a; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e0000e; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560000; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e207000; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x460000; +} + +static void +Opcode_ivp_mulsgnnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00380; +} + +static void +Opcode_ivp_nsanx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30603802; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_nsanx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380110c; +} + +static void +Opcode_ivp_nsanx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300110c; +} + +static void +Opcode_ivp_nsanx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9580026; +} + +static void +Opcode_ivp_nsanx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606e0c; +} + +static void +Opcode_ivp_nsanx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2020a; +} + +static void +Opcode_ivp_nsanx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000e20; +} + +static void +Opcode_ivp_nsaunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30602102; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_nsaunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801500; +} + +static void +Opcode_ivp_nsaunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001500; +} + +static void +Opcode_ivp_nsaunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9580030; +} + +static void +Opcode_ivp_nsaunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606c0e; +} + +static void +Opcode_ivp_nsaunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2020c; +} + +static void +Opcode_ivp_nsaunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000c40; +} + +static void +Opcode_ivp_ltnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x338000; +} + +static void +Opcode_ivp_ltnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b0400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ltnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400800; +} + +static void +Opcode_ivp_ltnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec1400; +} + +static void +Opcode_ivp_ltnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a0308; +} + +static void +Opcode_ivp_ltnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04808; +} + +static void +Opcode_ivp_ltnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a0208; +} + +static void +Opcode_ivp_ltnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000; +} + +static void +Opcode_ivp_ltnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9050008; +} + +static void +Opcode_ivp_ltnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c2800; +} + +static void +Opcode_ivp_ltnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c424000; +} + +static void +Opcode_ivp_ltnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000; +} + +static void +Opcode_ivp_ltnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd42800; +} + +static void +Opcode_ivp_ltnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3820000; +} + +static void +Opcode_ivp_ltnx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x738000; +} + +static void +Opcode_ivp_ltnx16_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x981800; +} + +static void +Opcode_ivp_lenx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x234008; +} + +static void +Opcode_ivp_lenx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305a9000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lenx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1481800; +} + +static void +Opcode_ivp_lenx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0800; +} + +static void +Opcode_ivp_lenx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0302; +} + +static void +Opcode_ivp_lenx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04c00; +} + +static void +Opcode_ivp_lenx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0202; +} + +static void +Opcode_ivp_lenx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0008; +} + +static void +Opcode_ivp_lenx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9904008; +} + +static void +Opcode_ivp_lenx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c1000; +} + +static void +Opcode_ivp_lenx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c415000; +} + +static void +Opcode_ivp_lenx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0008; +} + +static void +Opcode_ivp_lenx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd41000; +} + +static void +Opcode_ivp_lenx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3810020; +} + +static void +Opcode_ivp_lenx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x634008; +} + +static void +Opcode_ivp_lenx16_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x971000; +} + +static void +Opcode_ivp_eqnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b4000; +} + +static void +Opcode_ivp_eqnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305a8400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_eqnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c0400; +} + +static void +Opcode_ivp_eqnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec4000; +} + +static void +Opcode_ivp_eqnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a8306; +} + +static void +Opcode_ivp_eqnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04810; +} + +static void +Opcode_ivp_eqnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a8206; +} + +static void +Opcode_ivp_eqnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000; +} + +static void +Opcode_ivp_eqnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b84000; +} + +static void +Opcode_ivp_eqnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0400; +} + +static void +Opcode_ivp_eqnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c50d000; +} + +static void +Opcode_ivp_eqnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000; +} + +static void +Opcode_ivp_eqnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40400; +} + +static void +Opcode_ivp_eqnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3808060; +} + +static void +Opcode_ivp_eqnx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b4000; +} + +static void +Opcode_ivp_eqnx16_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970400; +} + +static void +Opcode_ivp_neqnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23c000; +} + +static void +Opcode_ivp_neqnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b1000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_neqnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c0800; +} + +static void +Opcode_ivp_neqnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec2000; +} + +static void +Opcode_ivp_neqnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b030a; +} + +static void +Opcode_ivp_neqnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05000; +} + +static void +Opcode_ivp_neqnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b020a; +} + +static void +Opcode_ivp_neqnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_ivp_neqnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90d8008; +} + +static void +Opcode_ivp_neqnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c4000; +} + +static void +Opcode_ivp_neqnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c435000; +} + +static void +Opcode_ivp_neqnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_ivp_neqnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd44000; +} + +static void +Opcode_ivp_neqnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3830020; +} + +static void +Opcode_ivp_neqnx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63c000; +} + +static void +Opcode_ivp_neqnx16_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a0000; +} + +static void +Opcode_ivp_ltunx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b8008; +} + +static void +Opcode_ivp_ltunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b8800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ltunx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1440c00; +} + +static void +Opcode_ivp_ltunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec5800; +} + +static void +Opcode_ivp_ltunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8308; +} + +static void +Opcode_ivp_ltunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04c18; +} + +static void +Opcode_ivp_ltunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8208; +} + +static void +Opcode_ivp_ltunx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4008; +} + +static void +Opcode_ivp_ltunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x905c008; +} + +static void +Opcode_ivp_ltunx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c3400; +} + +static void +Opcode_ivp_ltunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c43c000; +} + +static void +Opcode_ivp_ltunx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4008; +} + +static void +Opcode_ivp_ltunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd43400; +} + +static void +Opcode_ivp_ltunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3838000; +} + +static void +Opcode_ivp_ltunx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b8008; +} + +static void +Opcode_ivp_ltunx16_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x991400; +} + +static void +Opcode_ivp_leunx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b4008; +} + +static void +Opcode_ivp_leunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305a9c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_leunx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c1400; +} + +static void +Opcode_ivp_leunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec4c00; +} + +static void +Opcode_ivp_leunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8304; +} + +static void +Opcode_ivp_leunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04c10; +} + +static void +Opcode_ivp_leunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8204; +} + +static void +Opcode_ivp_leunx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc008; +} + +static void +Opcode_ivp_leunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a84008; +} + +static void +Opcode_ivp_leunx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c1c00; +} + +static void +Opcode_ivp_leunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c51c000; +} + +static void +Opcode_ivp_leunx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc008; +} + +static void +Opcode_ivp_leunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd41c00; +} + +static void +Opcode_ivp_leunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3818040; +} + +static void +Opcode_ivp_leunx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b4008; +} + +static void +Opcode_ivp_leunx16_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x971c00; +} + +static void +Opcode_ivp_raddnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502020; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000045; +} + +static void +Opcode_ivp_raddnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800345; +} + +static void +Opcode_ivp_raddnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c02800; +} + +static void +Opcode_ivp_raddnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607850; +} + +static void +Opcode_ivp_raddnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd880f0; +} + +static void +Opcode_ivp_raddnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c001b6; +} + +static void +Opcode_ivp_rmaxnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502430; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rmaxnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100055; +} + +static void +Opcode_ivp_rmaxnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900355; +} + +static void +Opcode_ivp_rmaxnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c82a00; +} + +static void +Opcode_ivp_rmaxnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607c60; +} + +static void +Opcode_ivp_rmaxnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb00f0; +} + +static void +Opcode_ivp_rmaxnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e001b7; +} + +static void +Opcode_ivp_rminnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502830; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rminnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200055; +} + +static void +Opcode_ivp_rminnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00355; +} + +static void +Opcode_ivp_rminnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d02a00; +} + +static void +Opcode_ivp_rminnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607861; +} + +static void +Opcode_ivp_rminnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30010; +} + +static void +Opcode_ivp_rminnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001c5; +} + +static void +Opcode_ivp_rmaxunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502431; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rmaxunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100075; +} + +static void +Opcode_ivp_rmaxunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900375; +} + +static void +Opcode_ivp_rmaxunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c82e00; +} + +static void +Opcode_ivp_rmaxunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607841; +} + +static void +Opcode_ivp_rmaxunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30000; +} + +static void +Opcode_ivp_rmaxunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f001b7; +} + +static void +Opcode_ivp_rminunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502831; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rminunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200075; +} + +static void +Opcode_ivp_rminunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00375; +} + +static void +Opcode_ivp_rminunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d02e00; +} + +static void +Opcode_ivp_rminunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607c41; +} + +static void +Opcode_ivp_rminunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30020; +} + +static void +Opcode_ivp_rminunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001c7; +} + +static void +Opcode_ivp_rbminnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800c01; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rbminnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000043; +} + +static void +Opcode_ivp_rbminnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800343; +} + +static void +Opcode_ivp_rbminnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9500408; +} + +static void +Opcode_ivp_rbminnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607080; +} + +static void +Opcode_ivp_rbminnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80080; +} + +static void +Opcode_ivp_rbminnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800197; +} + +static void +Opcode_ivp_rbmaxnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800ce0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rbmaxnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000062; +} + +static void +Opcode_ivp_rbmaxnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800362; +} + +static void +Opcode_ivp_rbmaxnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9500008; +} + +static void +Opcode_ivp_rbmaxnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607040; +} + +static void +Opcode_ivp_rbmaxnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80060; +} + +static void +Opcode_ivp_rbmaxnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800195; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800004; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00008; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800304; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8700000; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c302000; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ivp_bmaxnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_bmaxnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800340; +} + +static void +Opcode_ivp_bminnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20800c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bminnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780000; +} + +static void +Opcode_ivp_bminnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_bminnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800100; +} + +static void +Opcode_ivp_bminnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00008; +} + +static void +Opcode_ivp_bminnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800000; +} + +static void +Opcode_ivp_bminnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000000; +} + +static void +Opcode_ivp_bminnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ivp_bminnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c600000; +} + +static void +Opcode_ivp_bminnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ivp_bminnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_bminnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800380; +} + +static void +Opcode_ivp_mov2nx8t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38306000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mov2nx8t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ivp_mov2nx8t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880000; +} + +static void +Opcode_ivp_mov2nx8t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00200; +} + +static void +Opcode_ivp_mov2nx8t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300008; +} + +static void +Opcode_ivp_mov2nx8t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400300; +} + +static void +Opcode_ivp_mov2nx8t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00000; +} + +static void +Opcode_ivp_mov2nx8t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c702000; +} + +static void +Opcode_ivp_mov2nx8t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980000; +} + +static void +Opcode_ivp_mov2nx8t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800340; +} + +static void +Opcode_ivp_mulanx16packl_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0001d; +} + +static void +Opcode_ivp_mulanx16packl_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380008; +} + +static void +Opcode_ivp_mulanx16packq_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0001e; +} + +static void +Opcode_ivp_mulanx16packq_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000a; +} + +static void +Opcode_ivp_mulsnx16packl_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0001f; +} + +static void +Opcode_ivp_mulsnx16packl_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000e; +} + +static void +Opcode_ivp_mulsnx16packq_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0001f; +} + +static void +Opcode_ivp_mulsnx16packq_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400004; +} + +static void +Opcode_ivp_addsnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38402c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_addsnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1270000; +} + +static void +Opcode_ivp_addsnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc70000; +} + +static void +Opcode_ivp_addsnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0020a; +} + +static void +Opcode_ivp_addsnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00006; +} + +static void +Opcode_ivp_addsnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0010a; +} + +static void +Opcode_ivp_addsnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e0000b; +} + +static void +Opcode_ivp_addsnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ivp_addsnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e007000; +} + +static void +Opcode_ivp_addsnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb50000; +} + +static void +Opcode_ivp_addsnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ivp_addsnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c00280; +} + +static void +Opcode_ivp_subsnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e403c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_subsnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1358000; +} + +static void +Opcode_ivp_subsnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd98000; +} + +static void +Opcode_ivp_subsnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100302; +} + +static void +Opcode_ivp_subsnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0001b; +} + +static void +Opcode_ivp_subsnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900308; +} + +static void +Opcode_ivp_subsnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f0000d; +} + +static void +Opcode_ivp_subsnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x598000; +} + +static void +Opcode_ivp_subsnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e306c00; +} + +static void +Opcode_ivp_subsnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc38000; +} + +static void +Opcode_ivp_subsnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x498000; +} + +static void +Opcode_ivp_subsnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29003a0; +} + +static void +Opcode_ivp_negsnx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a34000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negsnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30602802; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negsnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500200; +} + +static void +Opcode_ivp_negsnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf400c0; +} + +static void +Opcode_ivp_negsnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801104; +} + +static void +Opcode_ivp_negsnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f68000; +} + +static void +Opcode_ivp_negsnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001104; +} + +static void +Opcode_ivp_negsnx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb08000; +} + +static void +Opcode_ivp_negsnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9580022; +} + +static void +Opcode_ivp_negsnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8140; +} + +static void +Opcode_ivp_negsnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606c0c; +} + +static void +Opcode_ivp_negsnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20208; +} + +static void +Opcode_ivp_negsnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8100; +} + +static void +Opcode_ivp_negsnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000e00; +} + +static void +Opcode_ivp_lv2nx8t_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10100000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lv2nx8t_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_lv2nx8t_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_lv2nx8t_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10100000; +} + +static void +Opcode_ivp_lv2nx8t_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_lv2nx8t_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_lv2nx8t_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10730000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lv2nx8t_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfb0000; +} + +static void +Opcode_ivp_lv2nx8t_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_ivp_lv2nx8t_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10490000; +} + +static void +Opcode_ivp_lv2nx8t_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ivp_lv2nx8t_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_ivp_lv2nx8t_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10580000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lv2nx8t_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ivp_lv2nx8t_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ivp_lv2nx8t_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10380000; +} + +static void +Opcode_ivp_lv2nx8t_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ivp_lv2nx8t_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0000; +} + +static void +Opcode_ivp_lv2nx8t_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10590000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lv2nx8t_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe10000; +} + +static void +Opcode_ivp_lv2nx8t_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_ivp_lv2nx8t_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10390000; +} + +static void +Opcode_ivp_lv2nx8t_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510000; +} + +static void +Opcode_ivp_lv2nx8t_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0000; +} + +static void +Opcode_ivp_sv2nx8t_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10240000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sv2nx8t_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ivp_sv2nx8t_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_sv2nx8t_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ivp_sv2nx8t_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ivp_sv2nx8t_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ivp_sv2nx8t_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sv2nx8t_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ivp_sv2nx8t_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_ivp_sv2nx8t_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780000; +} + +static void +Opcode_ivp_sv2nx8t_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0000; +} + +static void +Opcode_ivp_sv2nx8t_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880000; +} + +static void +Opcode_ivp_sv2nx8t_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10620000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sv2nx8t_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0000; +} + +static void +Opcode_ivp_sv2nx8t_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ivp_sv2nx8t_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620000; +} + +static void +Opcode_ivp_sv2nx8t_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0000; +} + +static void +Opcode_ivp_sv2nx8t_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740000; +} + +static void +Opcode_ivp_sv2nx8t_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10630000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sv2nx8t_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0000; +} + +static void +Opcode_ivp_sv2nx8t_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x390000; +} + +static void +Opcode_ivp_sv2nx8t_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_ivp_sv2nx8t_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0000; +} + +static void +Opcode_ivp_sv2nx8t_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750000; +} + +static void +Opcode_ivp_raddnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800c90; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000051; +} + +static void +Opcode_ivp_raddnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800351; +} + +static void +Opcode_ivp_raddnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01200; +} + +static void +Opcode_ivp_raddnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e304820; +} + +static void +Opcode_ivp_raddnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80010; +} + +static void +Opcode_ivp_raddnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800184; +} + +static void +Opcode_ivp_rmaxnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800c21; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rmaxnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000063; +} + +static void +Opcode_ivp_rmaxnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800363; +} + +static void +Opcode_ivp_rmaxnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01c00; +} + +static void +Opcode_ivp_rmaxnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6070c0; +} + +static void +Opcode_ivp_rmaxnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd800a0; +} + +static void +Opcode_ivp_rmaxnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001a5; +} + +static void +Opcode_ivp_rminnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800c41; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rminnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000044; +} + +static void +Opcode_ivp_rminnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800344; +} + +static void +Opcode_ivp_rminnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c02000; +} + +static void +Opcode_ivp_rminnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607800; +} + +static void +Opcode_ivp_rminnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd800c0; +} + +static void +Opcode_ivp_rminnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001a7; +} + +static void +Opcode_ivp_rmaxunx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800c31; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rmaxunx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000073; +} + +static void +Opcode_ivp_rmaxunx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800373; +} + +static void +Opcode_ivp_rmaxunx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01e00; +} + +static void +Opcode_ivp_rmaxunx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6070e0; +} + +static void +Opcode_ivp_rmaxunx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd800b0; +} + +static void +Opcode_ivp_rmaxunx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001a6; +} + +static void +Opcode_ivp_rminunx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800c51; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rminunx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000054; +} + +static void +Opcode_ivp_rminunx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800354; +} + +static void +Opcode_ivp_rminunx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c02200; +} + +static void +Opcode_ivp_rminunx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607820; +} + +static void +Opcode_ivp_rminunx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd800d0; +} + +static void +Opcode_ivp_rminunx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001b4; +} + +static void +Opcode_ivp_addnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36402000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_addnx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ivp_addnx16t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_addnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700000; +} + +static void +Opcode_ivp_addnx16t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00010; +} + +static void +Opcode_ivp_addnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300100; +} + +static void +Opcode_ivp_addnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8800001; +} + +static void +Opcode_ivp_addnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c201000; +} + +static void +Opcode_ivp_addnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ivp_addnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800220; +} + +static void +Opcode_ivp_subnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c306000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_subnx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa80000; +} + +static void +Opcode_ivp_subnx16t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ivp_subnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00200; +} + +static void +Opcode_ivp_subnx16t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ivp_subnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2600300; +} + +static void +Opcode_ivp_subnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00002; +} + +static void +Opcode_ivp_subnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c004000; +} + +static void +Opcode_ivp_subnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ivp_subnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800080; +} + +static void +Opcode_ivp_negnx16t_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a04000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30600002; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negnx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0220; +} + +static void +Opcode_ivp_negnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801000; +} + +static void +Opcode_ivp_negnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001000; +} + +static void +Opcode_ivp_negnx16t_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x808080; +} + +static void +Opcode_ivp_negnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c00101; +} + +static void +Opcode_ivp_negnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c604000; +} + +static void +Opcode_ivp_negnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ivp_negnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801100; +} + +static void +Opcode_ivp_maxnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34304000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_maxnx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ivp_maxnx16t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ivp_maxnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2600200; +} + +static void +Opcode_ivp_maxnx16t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000008; +} + +static void +Opcode_ivp_maxnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2600000; +} + +static void +Opcode_ivp_maxnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8800006; +} + +static void +Opcode_ivp_maxnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c502000; +} + +static void +Opcode_ivp_maxnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880000; +} + +static void +Opcode_ivp_maxnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800100; +} + +static void +Opcode_ivp_minnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30306000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_minnx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980000; +} + +static void +Opcode_ivp_minnx16t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780000; +} + +static void +Opcode_ivp_minnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800200; +} + +static void +Opcode_ivp_minnx16t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ivp_minnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400200; +} + +static void +Opcode_ivp_minnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880000c; +} + +static void +Opcode_ivp_minnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c602000; +} + +static void +Opcode_ivp_minnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ivp_minnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800240; +} + +static void +Opcode_ivp_maxunx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a304000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_maxunx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940000; +} + +static void +Opcode_ivp_maxunx16t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ivp_maxunx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500300; +} + +static void +Opcode_ivp_maxunx16t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100018; +} + +static void +Opcode_ivp_maxunx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500100; +} + +static void +Opcode_ivp_maxunx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8800009; +} + +static void +Opcode_ivp_maxunx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c503000; +} + +static void +Opcode_ivp_maxunx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000; +} + +static void +Opcode_ivp_maxunx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800160; +} + +static void +Opcode_ivp_minunx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36306000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_minunx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0000; +} + +static void +Opcode_ivp_minunx16t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840000; +} + +static void +Opcode_ivp_minunx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00200; +} + +static void +Opcode_ivp_minunx16t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200018; +} + +static void +Opcode_ivp_minunx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700200; +} + +static void +Opcode_ivp_minunx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880000f; +} + +static void +Opcode_ivp_minunx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c603000; +} + +static void +Opcode_ivp_minunx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940000; +} + +static void +Opcode_ivp_minunx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800320; +} + +static void +Opcode_ivp_mulanx16packlt_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500010; +} + +static void +Opcode_ivp_mulanx16packqt_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400018; +} + +static void +Opcode_ivp_addsnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36406000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_addsnx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ivp_addsnx16t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ivp_addsnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700100; +} + +static void +Opcode_ivp_addsnx16t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00010; +} + +static void +Opcode_ivp_addsnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300300; +} + +static void +Opcode_ivp_addsnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8800003; +} + +static void +Opcode_ivp_addsnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c301000; +} + +static void +Opcode_ivp_addsnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ivp_addsnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800260; +} + +static void +Opcode_ivp_subsnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38400000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_subsnx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_ivp_subsnx16t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980000; +} + +static void +Opcode_ivp_subsnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800300; +} + +static void +Opcode_ivp_subsnx16t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ivp_subsnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800200; +} + +static void +Opcode_ivp_subsnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00004; +} + +static void +Opcode_ivp_subsnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c104000; +} + +static void +Opcode_ivp_subsnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa80000; +} + +static void +Opcode_ivp_subsnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000c0; +} + +static void +Opcode_ivp_negsnx16t_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a08080; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negsnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30600302; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negsnx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100050; +} + +static void +Opcode_ivp_negsnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801c00; +} + +static void +Opcode_ivp_negsnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001c00; +} + +static void +Opcode_ivp_negsnx16t_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x814080; +} + +static void +Opcode_ivp_negsnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c00131; +} + +static void +Opcode_ivp_negsnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c604100; +} + +static void +Opcode_ivp_negsnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0100; +} + +static void +Opcode_ivp_negsnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801d00; +} + +static void +Opcode_ivp_lalign_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a40000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lalign_i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4000; +} + +static void +Opcode_ivp_lalign_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ivp_lalign_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_lalign_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ivp_lalign_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_lalign_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_ivp_lalign_i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198000; +} + +static void +Opcode_ivp_lalign_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600000; +} + +static void +Opcode_ivp_lalign_i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198000; +} + +static void +Opcode_ivp_lalign_i_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9000; +} + +static void +Opcode_ivp_lalign_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840000; +} + +static void +Opcode_ivp_lalign_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa80000; +} + +static void +Opcode_ivp_lalign_i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8000; +} + +static void +Opcode_ivp_lalign_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a40200; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lalign_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4400; +} + +static void +Opcode_ivp_lalign_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500400; +} + +static void +Opcode_ivp_lalign_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280400; +} + +static void +Opcode_ivp_lalign_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0f00; +} + +static void +Opcode_ivp_lalign_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280400; +} + +static void +Opcode_ivp_lalign_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d9800; +} + +static void +Opcode_ivp_lalign_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_ivp_lalign_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600100; +} + +static void +Opcode_ivp_lalign_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198400; +} + +static void +Opcode_ivp_lalign_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8000; +} + +static void +Opcode_ivp_lalign_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840200; +} + +static void +Opcode_ivp_lalign_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f8800; +} + +static void +Opcode_ivp_lalign_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8400; +} + +static void +Opcode_ivp_salign_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a40100; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_salign_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500100; +} + +static void +Opcode_ivp_salign_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_ivp_salign_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00100; +} + +static void +Opcode_ivp_salign_i_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9040; +} + +static void +Opcode_ivp_salign_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840100; +} + +static void +Opcode_ivp_salign_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa80400; +} + +static void +Opcode_ivp_salign_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a40300; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_salign_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500500; +} + +static void +Opcode_ivp_salign_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8f00; +} + +static void +Opcode_ivp_salign_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d9900; +} + +static void +Opcode_ivp_salign_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8100; +} + +static void +Opcode_ivp_salign_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840300; +} + +static void +Opcode_ivp_salign_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f8a00; +} + +static void +Opcode_ivp_la_pp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a200f0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_la_pp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4600; +} + +static void +Opcode_ivp_la_pp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500250; +} + +static void +Opcode_ivp_la_pp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280500; +} + +static void +Opcode_ivp_la_pp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600300; +} + +static void +Opcode_ivp_la_pp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280500; +} + +static void +Opcode_ivp_la_pp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8310d0; +} + +static void +Opcode_ivp_la_pp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0100; +} + +static void +Opcode_ivp_la_pp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f1070; +} + +static void +Opcode_ivp_la_pp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198500; +} + +static void +Opcode_ivp_la_pp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8200; +} + +static void +Opcode_ivp_la_pp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x850300; +} + +static void +Opcode_ivp_la_pp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa602e0; +} + +static void +Opcode_ivp_la_pp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8600; +} + +static void +Opcode_ivp_sapos_fp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a201f0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sapos_fp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500350; +} + +static void +Opcode_ivp_sapos_fp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600310; +} + +static void +Opcode_ivp_sapos_fp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8311d0; +} + +static void +Opcode_ivp_sapos_fp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8210; +} + +static void +Opcode_ivp_sapos_fp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x850310; +} + +static void +Opcode_ivp_sapos_fp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa606e0; +} + +static void +Opcode_ivp_malign_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a202f0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_malign_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4700; +} + +static void +Opcode_ivp_malign_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500650; +} + +static void +Opcode_ivp_malign_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280510; +} + +static void +Opcode_ivp_malign_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600330; +} + +static void +Opcode_ivp_malign_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280510; +} + +static void +Opcode_ivp_malign_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8318d0; +} + +static void +Opcode_ivp_malign_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0110; +} + +static void +Opcode_ivp_malign_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f1470; +} + +static void +Opcode_ivp_malign_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198510; +} + +static void +Opcode_ivp_malign_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b020; +} + +static void +Opcode_ivp_malign_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000; +} + +static void +Opcode_ivp_malign_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8220; +} + +static void +Opcode_ivp_malign_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x850320; +} + +static void +Opcode_ivp_malign_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f90f0; +} + +static void +Opcode_ivp_malign_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8700; +} + +static void +Opcode_ivp_zalign_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a202f4; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_zalign_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500654; +} + +static void +Opcode_ivp_zalign_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600334; +} + +static void +Opcode_ivp_zalign_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8318d1; +} + +static void +Opcode_ivp_zalign_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f1474; +} + +static void +Opcode_ivp_zalign_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b030; +} + +static void +Opcode_ivp_zalign_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8224; +} + +static void +Opcode_ivp_zalign_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x850324; +} + +static void +Opcode_ivp_zalign_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f90f1; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83b0070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce000; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1110090; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x284000; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x284000; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830090; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198010; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0030; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60000; +} + +static void +Opcode_ivp_la2nx8_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_ivp_sa2nx8_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83d8070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sa2nx8_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11180b0; +} + +static void +Opcode_ivp_sa2nx8_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0030; +} + +static void +Opcode_ivp_sa2nx8_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8380b0; +} + +static void +Opcode_ivp_sa2nx8_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0050; +} + +static void +Opcode_ivp_sa2nx8_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820050; +} + +static void +Opcode_ivp_sa2nx8_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60050; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10808000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x186000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1088000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x182000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x182000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x908000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10518000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x758000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x908000; +} + +static void +Opcode_ivp_lav2nx8_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ivp_sav2nx8_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10830000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sav2nx8_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0000; +} + +static void +Opcode_ivp_sav2nx8_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f0000; +} + +static void +Opcode_ivp_sav2nx8_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_ivp_sav2nx8_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ivp_sav2nx8_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780000; +} + +static void +Opcode_ivp_sav2nx8_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_ivp_selnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32400000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_selnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2100000; +} + +static void +Opcode_ivp_selnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2100000; +} + +static void +Opcode_ivp_selnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2100000; +} + +static void +Opcode_ivp_shflnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30600100; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_shflnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800400; +} + +static void +Opcode_ivp_shflnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000400; +} + +static void +Opcode_ivp_shflnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000400; +} + +static void +Opcode_ivp_movpint16_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea000; +} + +static void +Opcode_ivp_movpint16_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x252000; +} + +static void +Opcode_ivp_movpint16_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x252000; +} + +static void +Opcode_ivp_movpint16_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x194000; +} + +static void +Opcode_ivp_movpint16_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x194000; +} + +static void +Opcode_ivp_movpint16_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2000; +} + +static void +Opcode_ivp_movpa16_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc004; +} + +static void +Opcode_ivp_movpa16_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6004; +} + +static void +Opcode_ivp_mulnx16packp_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf0000; +} + +static void +Opcode_ivp_mulnx16packp_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0001e; +} + +static void +Opcode_ivp_mulnx16packp_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000c; +} + +static void +Opcode_ivp_mulanx16packp_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000e; +} + +static void +Opcode_ivp_mulanx16packp_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380009; +} + +static void +Opcode_ivp_mulsnx16packp_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000f; +} + +static void +Opcode_ivp_mulsnx16packp_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000f; +} + +static void +Opcode_ivp_mulanx16packpt_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400008; +} + +static void +Opcode_ivp_addmod16u_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cb000; +} + +static void +Opcode_ivp_addmod16u_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23f000; +} + +static void +Opcode_ivp_addmod16u_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d000; +} + +static void +Opcode_ivp_addmod16u_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10400000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc0000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0000; +} + +static void +Opcode_ivp_lvnx8s_i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10992000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x166000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1394000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa92000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16e000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c0000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16e000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e4000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa28000; +} + +static void +Opcode_ivp_lvnx8s_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18e000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108fc000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1462000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20e000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9fc000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x156000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1059c000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x156000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7ac000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ivp_lvnx8s_x_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x176000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108fe000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x156000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x146a000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20e000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9fe000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1059e000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7ae000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa02000; +} + +static void +Opcode_ivp_lvnx8s_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10420000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe0000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ivp_lvnx8u_i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10996000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139c000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x232000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x232000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa96000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c2000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e6000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2a000; +} + +static void +Opcode_ivp_lvnx8u_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10902000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1472000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x212000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa02000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a0000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa04000; +} + +static void +Opcode_ivp_lvnx8u_x_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10906000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x147a000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x214000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x212000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa06000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a2000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c2000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa06000; +} + +static void +Opcode_ivp_lvnx8u_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c000; +} + +static void +Opcode_ivp_svnx8u_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8u_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca0000; +} + +static void +Opcode_ivp_svnx8u_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0000; +} + +static void +Opcode_ivp_svnx8u_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e0000; +} + +static void +Opcode_ivp_svnx8u_i_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ivp_svnx8u_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x460000; +} + +static void +Opcode_ivp_svnx8u_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560000; +} + +static void +Opcode_ivp_svnx8u_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109be000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8u_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ae000; +} + +static void +Opcode_ivp_svnx8u_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58c000; +} + +static void +Opcode_ivp_svnx8u_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabe000; +} + +static void +Opcode_ivp_svnx8u_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8000; +} + +static void +Opcode_ivp_svnx8u_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f0000; +} + +static void +Opcode_ivp_svnx8u_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa34000; +} + +static void +Opcode_ivp_svnx8u_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10952000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8u_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1390000; +} + +static void +Opcode_ivp_svnx8u_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x570000; +} + +static void +Opcode_ivp_svnx8u_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa52000; +} + +static void +Opcode_ivp_svnx8u_x_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x194000; +} + +static void +Opcode_ivp_svnx8u_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d4000; +} + +static void +Opcode_ivp_svnx8u_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa18000; +} + +static void +Opcode_ivp_svnx8u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10956000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1398000; +} + +static void +Opcode_ivp_svnx8u_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x572000; +} + +static void +Opcode_ivp_svnx8u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa56000; +} + +static void +Opcode_ivp_svnx8u_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x196000; +} + +static void +Opcode_ivp_svnx8u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d6000; +} + +static void +Opcode_ivp_svnx8u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1a000; +} + +static void +Opcode_ivp_lvnx8st_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10140000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8st_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ivp_lvnx8st_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_lvnx8st_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10140000; +} + +static void +Opcode_ivp_lvnx8st_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_lvnx8st_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ivp_lvnx8st_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8st_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ivp_lvnx8st_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740000; +} + +static void +Opcode_ivp_lvnx8st_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104a0000; +} + +static void +Opcode_ivp_lvnx8st_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690000; +} + +static void +Opcode_ivp_lvnx8st_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840000; +} + +static void +Opcode_ivp_lvnx8st_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8st_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20000; +} + +static void +Opcode_ivp_lvnx8st_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0000; +} + +static void +Opcode_ivp_lvnx8st_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103a0000; +} + +static void +Opcode_ivp_lvnx8st_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x520000; +} + +static void +Opcode_ivp_lvnx8st_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ivp_lvnx8st_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8st_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30000; +} + +static void +Opcode_ivp_lvnx8st_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0000; +} + +static void +Opcode_ivp_lvnx8st_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103b0000; +} + +static void +Opcode_ivp_lvnx8st_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_ivp_lvnx8st_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0000; +} + +static void +Opcode_ivp_lvnx8ut_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10180000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8ut_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_lvnx8ut_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_lvnx8ut_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10180000; +} + +static void +Opcode_ivp_lvnx8ut_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_lvnx8ut_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_lvnx8ut_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10750000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8ut_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfd0000; +} + +static void +Opcode_ivp_lvnx8ut_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750000; +} + +static void +Opcode_ivp_lvnx8ut_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104b0000; +} + +static void +Opcode_ivp_lvnx8ut_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0000; +} + +static void +Opcode_ivp_lvnx8ut_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x850000; +} + +static void +Opcode_ivp_lvnx8ut_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8ut_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40000; +} + +static void +Opcode_ivp_lvnx8ut_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ivp_lvnx8ut_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103c0000; +} + +static void +Opcode_ivp_lvnx8ut_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ivp_lvnx8ut_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_ivp_lvnx8ut_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvnx8ut_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50000; +} + +static void +Opcode_ivp_lvnx8ut_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d0000; +} + +static void +Opcode_ivp_lvnx8ut_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103d0000; +} + +static void +Opcode_ivp_lvnx8ut_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x550000; +} + +static void +Opcode_ivp_lvnx8ut_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_ivp_svnx8ut_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8ut_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ivp_svnx8ut_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_svnx8ut_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ivp_svnx8ut_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ivp_svnx8ut_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ivp_svnx8ut_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8ut_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1020000; +} + +static void +Opcode_ivp_svnx8ut_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0000; +} + +static void +Opcode_ivp_svnx8ut_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0000; +} + +static void +Opcode_ivp_svnx8ut_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_ivp_svnx8ut_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a0000; +} + +static void +Opcode_ivp_svnx8ut_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10660000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8ut_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee0000; +} + +static void +Opcode_ivp_svnx8ut_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ivp_svnx8ut_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660000; +} + +static void +Opcode_ivp_svnx8ut_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e0000; +} + +static void +Opcode_ivp_svnx8ut_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780000; +} + +static void +Opcode_ivp_svnx8ut_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10670000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8ut_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xef0000; +} + +static void +Opcode_ivp_svnx8ut_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0000; +} + +static void +Opcode_ivp_svnx8ut_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x670000; +} + +static void +Opcode_ivp_svnx8ut_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f0000; +} + +static void +Opcode_ivp_svnx8ut_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x790000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10810000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x184000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x184000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10520000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x760000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_ivp_lavnx8s_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10818000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1098000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x186000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x186000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x918000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10528000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x768000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x918000; +} + +static void +Opcode_ivp_lavnx8u_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_ivp_savnx8u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10840000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_savnx8u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ivp_savnx8u_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ivp_savnx8u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940000; +} + +static void +Opcode_ivp_savnx8u_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ivp_savnx8u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x790000; +} + +static void +Opcode_ivp_savnx8u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940000; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83b8070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce010; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1118090; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x286000; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x286000; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x838090; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198030; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f8030; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0020; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0010; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820010; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60010; +} + +static void +Opcode_ivp_lanx8s_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8020; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83c0070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce020; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100a0; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x284010; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x284010; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8300a0; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198050; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0040; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0040; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0020; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820020; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60020; +} + +static void +Opcode_ivp_lanx8u_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8040; +} + +static void +Opcode_ivp_sanx8u_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83e8070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sanx8u_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1108090; +} + +static void +Opcode_ivp_sanx8u_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0040; +} + +static void +Opcode_ivp_sanx8u_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x828090; +} + +static void +Opcode_ivp_sanx8u_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0070; +} + +static void +Opcode_ivp_sanx8u_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820070; +} + +static void +Opcode_ivp_sanx8u_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60070; +} + +static void +Opcode_ivp_extractbl_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1708d1; +} + +static void +Opcode_ivp_extractbl_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0012; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extractbl_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000190; +} + +static void +Opcode_ivp_extractbl_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261811; +} + +static void +Opcode_ivp_extractbl_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800090; +} + +static void +Opcode_ivp_extractbl_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1802; +} + +static void +Opcode_ivp_extractbl_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9810098; +} + +static void +Opcode_ivp_extractbl_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8809; +} + +static void +Opcode_ivp_extractbl_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c016042; +} + +static void +Opcode_ivp_extractbl_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800181; +} + +static void +Opcode_ivp_extractbl_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3803; +} + +static void +Opcode_ivp_extractbh_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1708d0; +} + +static void +Opcode_ivp_extractbh_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0002; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extractbh_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000180; +} + +static void +Opcode_ivp_extractbh_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261810; +} + +static void +Opcode_ivp_extractbh_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800080; +} + +static void +Opcode_ivp_extractbh_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1002; +} + +static void +Opcode_ivp_extractbh_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9810088; +} + +static void +Opcode_ivp_extractbh_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8009; +} + +static void +Opcode_ivp_extractbh_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c016002; +} + +static void +Opcode_ivp_extractbh_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800081; +} + +static void +Opcode_ivp_extractbh_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3003; +} + +static void +Opcode_ivp_movvint16_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea080; +} + +static void +Opcode_ivp_movvint16_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254000; +} + +static void +Opcode_ivp_movvint16_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254000; +} + +static void +Opcode_ivp_movvint16_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x196000; +} + +static void +Opcode_ivp_movvint16_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x196000; +} + +static void +Opcode_ivp_movvint16_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b4000; +} + +static void +Opcode_ivp_movqint16_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fa000; +} + +static void +Opcode_ivp_movqint16_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x252080; +} + +static void +Opcode_ivp_movqint16_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x252080; +} + +static void +Opcode_ivp_movqint16_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x194010; +} + +static void +Opcode_ivp_movqint16_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x194080; +} + +static void +Opcode_ivp_movqint16_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2080; +} + +static void +Opcode_ivp_movqa16_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc005; +} + +static void +Opcode_ivp_movqa16_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6005; +} + +static void +Opcode_ivp_movvinx16_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc000; +} + +static void +Opcode_ivp_movvinx16_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254080; +} + +static void +Opcode_ivp_movvinx16_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254080; +} + +static void +Opcode_ivp_movvinx16_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa000; +} + +static void +Opcode_ivp_movvinx16_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac000; +} + +static void +Opcode_ivp_movvinx16_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000; +} + +static void +Opcode_ivp_seqnx16_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1760de; +} + +static void +Opcode_ivp_seqnx16_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a05e; +} + +static void +Opcode_ivp_seqnx16_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2820de; +} + +static void +Opcode_ivp_seqnx16_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a0fa; +} + +static void +Opcode_ivp_seqnx16_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b60a5; +} + +static void +Opcode_ivp_seqnx16_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce0ad; +} + +static void +Opcode_ivp_mulnx16packl_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde8000; +} + +static void +Opcode_ivp_mulnx16packl_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000e; +} + +static void +Opcode_ivp_mulnx16packl_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000b; +} + +static void +Opcode_ivp_mulnx16packq_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf8000; +} + +static void +Opcode_ivp_mulnx16packq_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000f; +} + +static void +Opcode_ivp_mulnx16packq_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000d; +} + +static void +Opcode_ivp_movav16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d7800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movav16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a450001; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movav16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1459200; +} + +static void +Opcode_ivp_movav16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3038201; +} + +static void +Opcode_ivp_movav16_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54600c; +} + +static void +Opcode_ivp_movav16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28f820d; +} + +static void +Opcode_ivp_movav16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d9a00; +} + +static void +Opcode_ivp_movav16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980e008; +} + +static void +Opcode_ivp_movav16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c20e000; +} + +static void +Opcode_ivp_movav16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcfc001; +} + +static void +Opcode_ivp_movav16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3888010; +} + +static void +Opcode_ivp_movavu16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d7e00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movavu16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a450007; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movavu16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1459e00; +} + +static void +Opcode_ivp_movavu16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3038207; +} + +static void +Opcode_ivp_movavu16_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54600f; +} + +static void +Opcode_ivp_movavu16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2bf820d; +} + +static void +Opcode_ivp_movavu16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9dfa00; +} + +static void +Opcode_ivp_movavu16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980e00b; +} + +static void +Opcode_ivp_movavu16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c30e001; +} + +static void +Opcode_ivp_movavu16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcfc007; +} + +static void +Opcode_ivp_movavu16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b88010; +} + +static void +Opcode_ivp_extrnx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10900200; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extrnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x385a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extrnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400400; +} + +static void +Opcode_ivp_extrnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a8300; +} + +static void +Opcode_ivp_extrnx16_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x550000; +} + +static void +Opcode_ivp_extrnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a8200; +} + +static void +Opcode_ivp_extrnx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00200; +} + +static void +Opcode_ivp_extrnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a04000; +} + +static void +Opcode_ivp_extrnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c40c000; +} + +static void +Opcode_ivp_extrnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf0001; +} + +static void +Opcode_ivp_extrnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3808000; +} + +static void +Opcode_ivp_lsnx8s_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10868000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsnx8s_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e8000; +} + +static void +Opcode_ivp_lsnx8s_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ivp_lsnx8s_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ivp_lsnx8s_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x968000; +} + +static void +Opcode_ivp_lsnx8s_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10550000; +} + +static void +Opcode_ivp_lsnx8s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10976000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsnx8s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139a000; +} + +static void +Opcode_ivp_lsnx8s_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x222000; +} + +static void +Opcode_ivp_lsnx8s_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x222000; +} + +static void +Opcode_ivp_lsnx8s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa76000; +} + +static void +Opcode_ivp_lsnx8s_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b2000; +} + +static void +Opcode_ivp_lsnx8s_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsnx8s_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf6000; +} + +static void +Opcode_ivp_lsnx8s_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce000; +} + +static void +Opcode_ivp_lsnx8s_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc000; +} + +static void +Opcode_ivp_lsnx8s_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e0000; +} + +static void +Opcode_ivp_lsnx8s_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10580000; +} + +static void +Opcode_ivp_lsnx8s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108e2000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsnx8s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdfe000; +} + +static void +Opcode_ivp_lsnx8s_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc000; +} + +static void +Opcode_ivp_lsnx8s_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce000; +} + +static void +Opcode_ivp_lsnx8s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e2000; +} + +static void +Opcode_ivp_lsnx8s_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10582000; +} + +static void +Opcode_ivp_svnx8s_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8s_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ivp_svnx8s_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ivp_svnx8s_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ivp_svnx8s_i_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_svnx8s_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ivp_svnx8s_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ivp_svnx8s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109ba000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a6000; +} + +static void +Opcode_ivp_svnx8s_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58a000; +} + +static void +Opcode_ivp_svnx8s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaba000; +} + +static void +Opcode_ivp_svnx8s_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6000; +} + +static void +Opcode_ivp_svnx8s_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7ee000; +} + +static void +Opcode_ivp_svnx8s_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa32000; +} + +static void +Opcode_ivp_svnx8s_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1094a000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8s_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380000; +} + +static void +Opcode_ivp_svnx8s_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56c000; +} + +static void +Opcode_ivp_svnx8s_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4a000; +} + +static void +Opcode_ivp_svnx8s_x_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_ivp_svnx8s_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d0000; +} + +static void +Opcode_ivp_svnx8s_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa14000; +} + +static void +Opcode_ivp_svnx8s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1094e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1388000; +} + +static void +Opcode_ivp_svnx8s_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56e000; +} + +static void +Opcode_ivp_svnx8s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4e000; +} + +static void +Opcode_ivp_svnx8s_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192000; +} + +static void +Opcode_ivp_svnx8s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d2000; +} + +static void +Opcode_ivp_svnx8s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa16000; +} + +static void +Opcode_ivp_ssnx8s_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssnx8s_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1220000; +} + +static void +Opcode_ivp_ssnx8s_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x528000; +} + +static void +Opcode_ivp_ssnx8s_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a0000; +} + +static void +Opcode_ivp_ssnx8s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109aa000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssnx8s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1386000; +} + +static void +Opcode_ivp_ssnx8s_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x582000; +} + +static void +Opcode_ivp_ssnx8s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaaa000; +} + +static void +Opcode_ivp_ssnx8s_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1092a000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssnx8s_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c2000; +} + +static void +Opcode_ivp_ssnx8s_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x55c000; +} + +static void +Opcode_ivp_ssnx8s_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2a000; +} + +static void +Opcode_ivp_ssnx8s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1092e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssnx8s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14ca000; +} + +static void +Opcode_ivp_ssnx8s_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x55e000; +} + +static void +Opcode_ivp_ssnx8s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2e000; +} + +static void +Opcode_ivp_savnx8s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10838000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_savnx8s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b8000; +} + +static void +Opcode_ivp_savnx8s_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f8000; +} + +static void +Opcode_ivp_savnx8s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x938000; +} + +static void +Opcode_ivp_savnx8s_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_ivp_savnx8s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x788000; +} + +static void +Opcode_ivp_savnx8s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x938000; +} + +static void +Opcode_ivp_sanx8s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83e0070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sanx8s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1108080; +} + +static void +Opcode_ivp_sanx8s_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c8030; +} + +static void +Opcode_ivp_sanx8s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x828080; +} + +static void +Opcode_ivp_sanx8s_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0060; +} + +static void +Opcode_ivp_sanx8s_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820060; +} + +static void +Opcode_ivp_sanx8s_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60060; +} + +static void +Opcode_ivp_svnx8st_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8st_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ivp_svnx8st_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_svnx8st_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_svnx8st_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_svnx8st_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ivp_svnx8st_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10790000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8st_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1010000; +} + +static void +Opcode_ivp_svnx8st_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0000; +} + +static void +Opcode_ivp_svnx8st_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x790000; +} + +static void +Opcode_ivp_svnx8st_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_ivp_svnx8st_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x890000; +} + +static void +Opcode_ivp_svnx8st_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8st_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ivp_svnx8st_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0000; +} + +static void +Opcode_ivp_svnx8st_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ivp_svnx8st_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ivp_svnx8st_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x760000; +} + +static void +Opcode_ivp_svnx8st_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10650000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svnx8st_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed0000; +} + +static void +Opcode_ivp_svnx8st_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0000; +} + +static void +Opcode_ivp_svnx8st_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650000; +} + +static void +Opcode_ivp_svnx8st_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d0000; +} + +static void +Opcode_ivp_svnx8st_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x770000; +} + +static void +Opcode_ivp_movba1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1706e0; +} + +static void +Opcode_ivp_movba1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260c60; +} + +static void +Opcode_ivp_movba1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260c20; +} + +static void +Opcode_ivp_movba1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2410; +} + +static void +Opcode_ivp_movba1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aec00; +} + +static void +Opcode_ivp_movba1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc810; +} + +static void +Opcode_ivp_movab1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dd040; +} + +static void +Opcode_ivp_movab1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x287020; +} + +static void +Opcode_ivp_movab1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x287020; +} + +static void +Opcode_ivp_movab1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab080; +} + +static void +Opcode_ivp_movab1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ad040; +} + +static void +Opcode_ivp_movab1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cd030; +} + +static void +Opcode_ivp_notb1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1710d0; +} + +static void +Opcode_ivp_notb1_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0042; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_notb1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261852; +} + +static void +Opcode_ivp_notb1_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30001c0; +} + +static void +Opcode_ivp_notb1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261814; +} + +static void +Opcode_ivp_notb1_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000c0; +} + +static void +Opcode_ivp_notb1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1012; +} + +static void +Opcode_ivp_notb1_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98100c8; +} + +static void +Opcode_ivp_notb1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a800a; +} + +static void +Opcode_ivp_notb1_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01e002; +} + +static void +Opcode_ivp_notb1_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0418; +} + +static void +Opcode_ivp_notb1_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd828e4; +} + +static void +Opcode_ivp_notb1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c7818; +} + +static void +Opcode_ivp_andnotb1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700c0; +} + +static void +Opcode_ivp_andnotb1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261040; +} + +static void +Opcode_ivp_andnotb1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261000; +} + +static void +Opcode_ivp_andnotb1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8008; +} + +static void +Opcode_ivp_andnotb1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa010; +} + +static void +Opcode_ivp_andnotb1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6008; +} + +static void +Opcode_ivp_ornotb1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1708c8; +} + +static void +Opcode_ivp_ornotb1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260850; +} + +static void +Opcode_ivp_ornotb1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260810; +} + +static void +Opcode_ivp_ornotb1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8818; +} + +static void +Opcode_ivp_ornotb1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa018; +} + +static void +Opcode_ivp_ornotb1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6818; +} + +static void +Opcode_ivp_cvt32s2nx24ll_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc070; +} + +static void +Opcode_ivp_cvt32s2nx24ll_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6020; +} + +static void +Opcode_ivp_cvt32s2nx24ll_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6020; +} + +static void +Opcode_ivp_cvt32s2nx24ll_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0c8; +} + +static void +Opcode_ivp_cvt32s2nx24ll_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac058; +} + +static void +Opcode_ivp_cvt32s2nx24ll_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2014; +} + +static void +Opcode_ivp_cvt32s2nx24lh_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc06c; +} + +static void +Opcode_ivp_cvt32s2nx24lh_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a602c; +} + +static void +Opcode_ivp_cvt32s2nx24lh_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a602c; +} + +static void +Opcode_ivp_cvt32s2nx24lh_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0e4; +} + +static void +Opcode_ivp_cvt32s2nx24lh_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac074; +} + +static void +Opcode_ivp_cvt32s2nx24lh_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d20e4; +} + +static void +Opcode_ivp_cvt32s2nx24hl_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc068; +} + +static void +Opcode_ivp_cvt32s2nx24hl_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6028; +} + +static void +Opcode_ivp_cvt32s2nx24hl_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6028; +} + +static void +Opcode_ivp_cvt32s2nx24hl_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0c4; +} + +static void +Opcode_ivp_cvt32s2nx24hl_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac054; +} + +static void +Opcode_ivp_cvt32s2nx24hl_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d20c4; +} + +static void +Opcode_ivp_cvt32s2nx24hh_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc064; +} + +static void +Opcode_ivp_cvt32s2nx24hh_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6024; +} + +static void +Opcode_ivp_cvt32s2nx24hh_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6024; +} + +static void +Opcode_ivp_cvt32s2nx24hh_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0e0; +} + +static void +Opcode_ivp_cvt32s2nx24hh_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac070; +} + +static void +Opcode_ivp_cvt32s2nx24hh_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d20a4; +} + +static void +Opcode_ivp_cvt64snx48ll_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a0d4; +} + +static void +Opcode_ivp_cvt64snx48ll_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80a4; +} + +static void +Opcode_ivp_cvt64snx48lh_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1780d4; +} + +static void +Opcode_ivp_cvt64snx48lh_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80a0; +} + +static void +Opcode_ivp_cvt64snx48hl_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1760d4; +} + +static void +Opcode_ivp_cvt64snx48hl_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d20f4; +} + +static void +Opcode_ivp_cvt64snx48hh_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1740d4; +} + +static void +Opcode_ivp_cvt64snx48hh_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d20d4; +} + +static void +Opcode_ivp_cvt16s2nx24l_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc054; +} + +static void +Opcode_ivp_cvt16s2nx24l_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x296024; +} + +static void +Opcode_ivp_cvt16s2nx24l_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x296024; +} + +static void +Opcode_ivp_cvt16s2nx24l_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0a4; +} + +static void +Opcode_ivp_cvt16s2nx24l_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac064; +} + +static void +Opcode_ivp_cvt16s2nx24l_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2024; +} + +static void +Opcode_ivp_cvt16s2nx24h_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc050; +} + +static void +Opcode_ivp_cvt16s2nx24h_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x296020; +} + +static void +Opcode_ivp_cvt16s2nx24h_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x296020; +} + +static void +Opcode_ivp_cvt16s2nx24h_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0a0; +} + +static void +Opcode_ivp_cvt16s2nx24h_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac060; +} + +static void +Opcode_ivp_cvt16s2nx24h_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2004; +} + +static void +Opcode_ivp_cvt32snx48l_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc078; +} + +static void +Opcode_ivp_cvt32snx48l_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6028; +} + +static void +Opcode_ivp_cvt32snx48l_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6028; +} + +static void +Opcode_ivp_cvt32snx48l_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0cc; +} + +static void +Opcode_ivp_cvt32snx48l_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac05c; +} + +static void +Opcode_ivp_cvt32snx48l_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2054; +} + +static void +Opcode_ivp_cvt32snx48h_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc074; +} + +static void +Opcode_ivp_cvt32snx48h_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6024; +} + +static void +Opcode_ivp_cvt32snx48h_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6024; +} + +static void +Opcode_ivp_cvt32snx48h_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0e8; +} + +static void +Opcode_ivp_cvt32snx48h_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac078; +} + +static void +Opcode_ivp_cvt32snx48h_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2034; +} + +static void +Opcode_ivp_cvt16u2nx24h_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc058; +} + +static void +Opcode_ivp_cvt16u2nx24h_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x296028; +} + +static void +Opcode_ivp_cvt16u2nx24h_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x296028; +} + +static void +Opcode_ivp_cvt16u2nx24h_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0a8; +} + +static void +Opcode_ivp_cvt16u2nx24h_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac068; +} + +static void +Opcode_ivp_cvt16u2nx24h_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2044; +} + +static void +Opcode_ivp_cvt32unx48h_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc07c; +} + +static void +Opcode_ivp_cvt32unx48h_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b602c; +} + +static void +Opcode_ivp_cvt32unx48h_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b602c; +} + +static void +Opcode_ivp_cvt32unx48h_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0ec; +} + +static void +Opcode_ivp_cvt32unx48h_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac07c; +} + +static void +Opcode_ivp_cvt32unx48h_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2074; +} + +static void +Opcode_ivp_cvt64un_2x96h_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e0d4; +} + +static void +Opcode_ivp_cvt64un_2x96h_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80ac; +} + +static void +Opcode_ivp_cvt16u2nx24l_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc05c; +} + +static void +Opcode_ivp_cvt16u2nx24l_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29602c; +} + +static void +Opcode_ivp_cvt16u2nx24l_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29602c; +} + +static void +Opcode_ivp_cvt16u2nx24l_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0ac; +} + +static void +Opcode_ivp_cvt16u2nx24l_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac06c; +} + +static void +Opcode_ivp_cvt16u2nx24l_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2064; +} + +static void +Opcode_ivp_cvt24u2nx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268000; +} + +static void +Opcode_ivp_cvt24u2nx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13400; +} + +static void +Opcode_ivp_cvt24u2nx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0600c; +} + +static void +Opcode_ivp_cvt24u2nx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_ivp_cvt24u2nx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_ivp_cvt24u2nx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x654001; +} + +static void +Opcode_ivp_cvt24s2nx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26400f; +} + +static void +Opcode_ivp_cvt24s2nx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03400; +} + +static void +Opcode_ivp_cvt24s2nx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c0b; +} + +static void +Opcode_ivp_cvt24s2nx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000f; +} + +static void +Opcode_ivp_cvt24s2nx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000f; +} + +static void +Opcode_ivp_cvt32s24_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc060; +} + +static void +Opcode_ivp_cvt32s24_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6020; +} + +static void +Opcode_ivp_cvt32s24_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6020; +} + +static void +Opcode_ivp_cvt32s24_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa0c0; +} + +static void +Opcode_ivp_cvt32s24_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac050; +} + +static void +Opcode_ivp_cvt32s24_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2084; +} + +static void +Opcode_ivp_cvt24u32_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268008; +} + +static void +Opcode_ivp_cvt24u32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf500e0; +} + +static void +Opcode_ivp_cvt24u32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e68003; +} + +static void +Opcode_ivp_cvt24u32_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0008; +} + +static void +Opcode_ivp_cvt24u32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150008; +} + +static void +Opcode_ivp_cvt24u32_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65b000; +} + +static void +Opcode_ivp_cvt24unx32l_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268002; +} + +static void +Opcode_ivp_cvt24unx32l_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33400; +} + +static void +Opcode_ivp_cvt24unx32l_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0680c; +} + +static void +Opcode_ivp_cvt24unx32l_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0002; +} + +static void +Opcode_ivp_cvt24unx32l_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150002; +} + +static void +Opcode_ivp_cvt24unx32l_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x654003; +} + +static void +Opcode_ivp_cvt24unx32h_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268001; +} + +static void +Opcode_ivp_cvt24unx32h_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf23400; +} + +static void +Opcode_ivp_cvt24unx32h_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0640c; +} + +static void +Opcode_ivp_cvt24unx32h_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0001; +} + +static void +Opcode_ivp_cvt24unx32h_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150001; +} + +static void +Opcode_ivp_cvt24unx32h_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x654002; +} + +static void +Opcode_ivp_cvt32unx48l_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700d4; +} + +static void +Opcode_ivp_cvt32unx48l_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260058; +} + +static void +Opcode_ivp_cvt32unx48l_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28200c; +} + +static void +Opcode_ivp_cvt32unx48l_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980d0; +} + +static void +Opcode_ivp_cvt32unx48l_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00a0; +} + +static void +Opcode_ivp_cvt32unx48l_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2094; +} + +static void +Opcode_ivp_cvt48unx32l_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800b; +} + +static void +Opcode_ivp_cvt48unx32l_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf50ce0; +} + +static void +Opcode_ivp_cvt48unx32l_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e68c03; +} + +static void +Opcode_ivp_cvt48unx32l_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000b; +} + +static void +Opcode_ivp_cvt48unx32l_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150019; +} + +static void +Opcode_ivp_cvt48unx32l_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65b002; +} + +static void +Opcode_ivp_cvt48unx32_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268004; +} + +static void +Opcode_ivp_cvt48unx32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03c00; +} + +static void +Opcode_ivp_cvt48unx32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0700c; +} + +static void +Opcode_ivp_cvt48unx32_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0004; +} + +static void +Opcode_ivp_cvt48unx32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150004; +} + +static void +Opcode_ivp_cvt48unx32_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x654004; +} + +static void +Opcode_ivp_cvt48snx32l_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268009; +} + +static void +Opcode_ivp_cvt48snx32l_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf504e0; +} + +static void +Opcode_ivp_cvt48snx32l_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e68403; +} + +static void +Opcode_ivp_cvt48snx32l_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0009; +} + +static void +Opcode_ivp_cvt48snx32l_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150018; +} + +static void +Opcode_ivp_cvt48snx32_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268003; +} + +static void +Opcode_ivp_cvt48snx32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03800; +} + +static void +Opcode_ivp_cvt48snx32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c0c; +} + +static void +Opcode_ivp_cvt48snx32_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0003; +} + +static void +Opcode_ivp_cvt48snx32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150003; +} + +static void +Opcode_ivp_cvt64s48_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1720d4; +} + +static void +Opcode_ivp_cvt64s48_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262058; +} + +static void +Opcode_ivp_cvt64s48_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28201c; +} + +static void +Opcode_ivp_cvt64s48_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980f0; +} + +static void +Opcode_ivp_cvt64s48_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00a4; +} + +static void +Opcode_ivp_cvt64s48_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d20b4; +} + +static void +Opcode_ivp_cvt48u64_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800a; +} + +static void +Opcode_ivp_cvt48u64_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf508e0; +} + +static void +Opcode_ivp_cvt48u64_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e68803; +} + +static void +Opcode_ivp_cvt48u64_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000a; +} + +static void +Opcode_ivp_cvt48u64_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150009; +} + +static void +Opcode_ivp_cvt48u64_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65b001; +} + +static void +Opcode_ivp_cvt48un_2x64l_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268006; +} + +static void +Opcode_ivp_cvt48un_2x64l_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13c00; +} + +static void +Opcode_ivp_cvt48un_2x64l_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0780c; +} + +static void +Opcode_ivp_cvt48un_2x64l_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0006; +} + +static void +Opcode_ivp_cvt48un_2x64l_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150006; +} + +static void +Opcode_ivp_cvt48un_2x64l_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x654006; +} + +static void +Opcode_ivp_cvt48un_2x64h_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268005; +} + +static void +Opcode_ivp_cvt48un_2x64h_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13800; +} + +static void +Opcode_ivp_cvt48un_2x64h_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0740c; +} + +static void +Opcode_ivp_cvt48un_2x64h_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0005; +} + +static void +Opcode_ivp_cvt48un_2x64h_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150005; +} + +static void +Opcode_ivp_cvt48un_2x64h_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x654005; +} + +static void +Opcode_ivp_cvt64un_2x96l_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700d8; +} + +static void +Opcode_ivp_cvt64un_2x96l_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca0a0; +} + +static void +Opcode_ivp_cvt96un_2x64_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268007; +} + +static void +Opcode_ivp_cvt96un_2x64_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf23800; +} + +static void +Opcode_ivp_cvt96un_2x64_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c0c; +} + +static void +Opcode_ivp_cvt96un_2x64_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0007; +} + +static void +Opcode_ivp_cvt96un_2x64_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150007; +} + +static void +Opcode_ivp_cvt96un_2x64_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x654007; +} + +static void +Opcode_ivp_cvt96u64_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800c; +} + +static void +Opcode_ivp_cvt96u64_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf510e0; +} + +static void +Opcode_ivp_cvt96u64_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e69003; +} + +static void +Opcode_ivp_cvt96u64_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000c; +} + +static void +Opcode_ivp_cvt96u64_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000a; +} + +static void +Opcode_ivp_cvt96u64_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65b003; +} + +static void +Opcode_ivp_cvt64u96_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c0d4; +} + +static void +Opcode_ivp_cvt64u96_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264058; +} + +static void +Opcode_ivp_cvt64u96_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28202c; +} + +static void +Opcode_ivp_cvt64u96_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980d4; +} + +static void +Opcode_ivp_cvt64u96_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00a8; +} + +static void +Opcode_ivp_cvt64u96_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80a8; +} + +static void +Opcode_ivp_lb2n_i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ivp_lb2n_i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x166000; +} + +static void +Opcode_ivp_lb2n_i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x166000; +} + +static void +Opcode_ivp_lb2n_i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x186000; +} + +static void +Opcode_ivp_lb2n_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x171040; +} + +static void +Opcode_ivp_lb2n_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x199000; +} + +static void +Opcode_ivp_lb2n_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193000; +} + +static void +Opcode_ivp_lb2n_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8010; +} + +static void +Opcode_ivp_sb2n_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a20000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sb2n_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100060; +} + +static void +Opcode_ivp_sb2n_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0000; +} + +static void +Opcode_ivp_sb2n_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0020; +} + +static void +Opcode_ivp_sb2n_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ivp_sb2n_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f1000; +} + +static void +Opcode_ivp_sb2n_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a200c0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sb2n_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100c0; +} + +static void +Opcode_ivp_sb2n_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0c00; +} + +static void +Opcode_ivp_sb2n_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8300c0; +} + +static void +Opcode_ivp_sb2n_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000c0; +} + +static void +Opcode_ivp_sb2n_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f10c0; +} + +static void +Opcode_ivp_ltr2n_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700e0; +} + +static void +Opcode_ivp_ltr2n_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260660; +} + +static void +Opcode_ivp_ltr2n_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260620; +} + +static void +Opcode_ivp_ltr2n_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0610; +} + +static void +Opcode_ivp_ltr2n_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae600; +} + +static void +Opcode_ivp_ltr2n_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0010; +} + +static void +Opcode_ivp_ltr2n_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc610; +} + +static void +Opcode_ivp_ltr2ni_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x171070; +} + +static void +Opcode_ivp_ltr2ni_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260040; +} + +static void +Opcode_ivp_ltr2ni_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260000; +} + +static void +Opcode_ivp_ltr2ni_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19f000; +} + +static void +Opcode_ivp_ltr2ni_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab000; +} + +static void +Opcode_ivp_ltr2ni_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0010; +} + +static void +Opcode_ivp_ltr2ni_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cb010; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10460000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x460000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10320000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ivp_lvn_2x16u_i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1099e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ac000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x236000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x236000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9e000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c6000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7ea000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2e000; +} + +static void +Opcode_ivp_lvn_2x16u_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x194000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10912000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1492000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21a000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x218000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa12000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x162000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a8000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x162000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c8000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0c000; +} + +static void +Opcode_ivp_lvn_2x16u_x_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x182000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10916000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x162000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x149a000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21c000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21a000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa16000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x164000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x164000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7ca000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0e000; +} + +static void +Opcode_ivp_lvn_2x16u_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x184000; +} + +static void +Opcode_ivp_lvn_2x16ut_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16ut_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ivp_lvn_2x16ut_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_lvn_2x16ut_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200000; +} + +static void +Opcode_ivp_lvn_2x16ut_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_lvn_2x16ut_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ivp_lvn_2x16ut_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10770000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16ut_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff0000; +} + +static void +Opcode_ivp_lvn_2x16ut_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x770000; +} + +static void +Opcode_ivp_lvn_2x16ut_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d0000; +} + +static void +Opcode_ivp_lvn_2x16ut_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ivp_lvn_2x16ut_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x870000; +} + +static void +Opcode_ivp_lvn_2x16ut_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16ut_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ivp_lvn_2x16ut_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ivp_lvn_2x16ut_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10400000; +} + +static void +Opcode_ivp_lvn_2x16ut_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ivp_lvn_2x16ut_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720000; +} + +static void +Opcode_ivp_lvn_2x16ut_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10610000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16ut_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe90000; +} + +static void +Opcode_ivp_lvn_2x16ut_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_ivp_lvn_2x16ut_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10410000; +} + +static void +Opcode_ivp_lvn_2x16ut_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_ivp_lvn_2x16ut_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10440000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e0000; +} + +static void +Opcode_ivp_lvn_2x16s_i_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1099a000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a4000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x234000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x234000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9a000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x172000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c4000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x172000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e8000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2c000; +} + +static void +Opcode_ivp_lvn_2x16s_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090a000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1482000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x216000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x214000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0a000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a4000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c4000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08000; +} + +static void +Opcode_ivp_lvn_2x16s_x_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148a000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x218000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x216000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0e000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a6000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c6000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0a000; +} + +static void +Opcode_ivp_lvn_2x16s_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_lvn_2x16st_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16st_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ivp_lvn_2x16st_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ivp_lvn_2x16st_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101c0000; +} + +static void +Opcode_ivp_lvn_2x16st_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ivp_lvn_2x16st_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ivp_lvn_2x16st_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10760000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16st_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe0000; +} + +static void +Opcode_ivp_lvn_2x16st_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x760000; +} + +static void +Opcode_ivp_lvn_2x16st_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0000; +} + +static void +Opcode_ivp_lvn_2x16st_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0000; +} + +static void +Opcode_ivp_lvn_2x16st_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x860000; +} + +static void +Opcode_ivp_lvn_2x16st_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16st_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe60000; +} + +static void +Opcode_ivp_lvn_2x16st_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e0000; +} + +static void +Opcode_ivp_lvn_2x16st_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103e0000; +} + +static void +Opcode_ivp_lvn_2x16st_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560000; +} + +static void +Opcode_ivp_lvn_2x16st_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ivp_lvn_2x16st_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lvn_2x16st_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe70000; +} + +static void +Opcode_ivp_lvn_2x16st_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f0000; +} + +static void +Opcode_ivp_lvn_2x16st_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103f0000; +} + +static void +Opcode_ivp_lvn_2x16st_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x570000; +} + +static void +Opcode_ivp_lvn_2x16st_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x710000; +} + +static void +Opcode_ivp_svn_2x16u_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10520000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16u_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce0000; +} + +static void +Opcode_ivp_svn_2x16u_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000; +} + +static void +Opcode_ivp_svn_2x16u_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x520000; +} + +static void +Opcode_ivp_svn_2x16u_i_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ivp_svn_2x16u_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0000; +} + +static void +Opcode_ivp_svn_2x16u_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0000; +} + +static void +Opcode_ivp_svn_2x16ut_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16ut_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ivp_svn_2x16ut_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_svn_2x16ut_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ivp_svn_2x16ut_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ivp_svn_2x16ut_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ivp_svn_2x16u_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109c6000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16u_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13be000; +} + +static void +Opcode_ivp_svn_2x16u_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_ivp_svn_2x16u_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac6000; +} + +static void +Opcode_ivp_svn_2x16u_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac000; +} + +static void +Opcode_ivp_svn_2x16u_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f4000; +} + +static void +Opcode_ivp_svn_2x16u_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa38000; +} + +static void +Opcode_ivp_svn_2x16ut_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16ut_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ivp_svn_2x16ut_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d0000; +} + +static void +Opcode_ivp_svn_2x16ut_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0000; +} + +static void +Opcode_ivp_svn_2x16ut_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x710000; +} + +static void +Opcode_ivp_svn_2x16ut_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000; +} + +static void +Opcode_ivp_svn_2x16u_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10962000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16u_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b0000; +} + +static void +Opcode_ivp_svn_2x16u_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x578000; +} + +static void +Opcode_ivp_svn_2x16u_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa62000; +} + +static void +Opcode_ivp_svn_2x16u_x_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19c000; +} + +static void +Opcode_ivp_svn_2x16u_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7dc000; +} + +static void +Opcode_ivp_svn_2x16u_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa20000; +} + +static void +Opcode_ivp_svn_2x16ut_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16ut_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf20000; +} + +static void +Opcode_ivp_svn_2x16ut_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_svn_2x16ut_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0000; +} + +static void +Opcode_ivp_svn_2x16ut_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620000; +} + +static void +Opcode_ivp_svn_2x16ut_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0000; +} + +static void +Opcode_ivp_svn_2x16u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10966000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b8000; +} + +static void +Opcode_ivp_svn_2x16u_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57a000; +} + +static void +Opcode_ivp_svn_2x16u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa66000; +} + +static void +Opcode_ivp_svn_2x16u_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19e000; +} + +static void +Opcode_ivp_svn_2x16u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7de000; +} + +static void +Opcode_ivp_svn_2x16u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa22000; +} + +static void +Opcode_ivp_svn_2x16ut_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16ut_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30000; +} + +static void +Opcode_ivp_svn_2x16ut_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_ivp_svn_2x16ut_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0000; +} + +static void +Opcode_ivp_svn_2x16ut_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_ivp_svn_2x16ut_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d0000; +} + +static void +Opcode_ivp_svn_2x16s_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16s_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ivp_svn_2x16s_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ivp_svn_2x16s_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ivp_svn_2x16s_i_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_svn_2x16s_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ivp_svn_2x16s_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ivp_svn_2x16st_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16st_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_svn_2x16st_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ivp_svn_2x16st_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ivp_svn_2x16st_i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ivp_svn_2x16st_i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_svn_2x16s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109c2000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b6000; +} + +static void +Opcode_ivp_svn_2x16s_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58e000; +} + +static void +Opcode_ivp_svn_2x16s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac2000; +} + +static void +Opcode_ivp_svn_2x16s_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa000; +} + +static void +Opcode_ivp_svn_2x16s_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f2000; +} + +static void +Opcode_ivp_svn_2x16s_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa36000; +} + +static void +Opcode_ivp_svn_2x16st_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16st_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1030000; +} + +static void +Opcode_ivp_svn_2x16st_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ivp_svn_2x16st_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0000; +} + +static void +Opcode_ivp_svn_2x16st_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ivp_svn_2x16st_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b0000; +} + +static void +Opcode_ivp_svn_2x16s_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1095a000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16s_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a0000; +} + +static void +Opcode_ivp_svn_2x16s_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x574000; +} + +static void +Opcode_ivp_svn_2x16s_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5a000; +} + +static void +Opcode_ivp_svn_2x16s_x_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198000; +} + +static void +Opcode_ivp_svn_2x16s_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d8000; +} + +static void +Opcode_ivp_svn_2x16s_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1c000; +} + +static void +Opcode_ivp_svn_2x16st_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16st_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ivp_svn_2x16st_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0000; +} + +static void +Opcode_ivp_svn_2x16st_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ivp_svn_2x16st_x_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ivp_svn_2x16st_x_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0000; +} + +static void +Opcode_ivp_svn_2x16s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1095e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a8000; +} + +static void +Opcode_ivp_svn_2x16s_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x576000; +} + +static void +Opcode_ivp_svn_2x16s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5e000; +} + +static void +Opcode_ivp_svn_2x16s_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a000; +} + +static void +Opcode_ivp_svn_2x16s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7da000; +} + +static void +Opcode_ivp_svn_2x16s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1e000; +} + +static void +Opcode_ivp_svn_2x16st_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_svn_2x16st_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10000; +} + +static void +Opcode_ivp_svn_2x16st_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0000; +} + +static void +Opcode_ivp_svn_2x16st_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690000; +} + +static void +Opcode_ivp_svn_2x16st_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_ivp_svn_2x16st_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0000; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83c8070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce030; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100b0; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x286010; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x286010; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8300b0; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198070; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0050; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0060; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0030; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820030; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60030; +} + +static void +Opcode_ivp_lan_2x16s_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8060; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83d0070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce040; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11180a0; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x284020; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x284020; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8380a0; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198090; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0060; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0080; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0040; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820040; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60040; +} + +static void +Opcode_ivp_lan_2x16u_ip_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8080; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10800000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x184000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10510000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ivp_lan_2x16u_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107f8000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x182000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1078000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14e000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14e000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f8000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10508000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x748000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f8000; +} + +static void +Opcode_ivp_lan_2x16s_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_ivp_san_2x16u_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83f8070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_san_2x16u_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11080b0; +} + +static void +Opcode_ivp_san_2x16u_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0060; +} + +static void +Opcode_ivp_san_2x16u_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280b0; +} + +static void +Opcode_ivp_san_2x16u_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0090; +} + +static void +Opcode_ivp_san_2x16u_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820090; +} + +static void +Opcode_ivp_san_2x16u_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60090; +} + +static void +Opcode_ivp_san_2x16s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83f0070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_san_2x16s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11080a0; +} + +static void +Opcode_ivp_san_2x16s_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0050; +} + +static void +Opcode_ivp_san_2x16s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280a0; +} + +static void +Opcode_ivp_san_2x16s_ip_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0080; +} + +static void +Opcode_ivp_san_2x16s_ip_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820080; +} + +static void +Opcode_ivp_san_2x16s_ip_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60080; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10820000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x920000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10530000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x770000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x920000; +} + +static void +Opcode_ivp_lavn_2x16s_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10828000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18e000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a8000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x928000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10538000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x778000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x928000; +} + +static void +Opcode_ivp_lavn_2x16u_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_ivp_savn_2x16u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10850000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_savn_2x16u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0000; +} + +static void +Opcode_ivp_savn_2x16u_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510000; +} + +static void +Opcode_ivp_savn_2x16u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x950000; +} + +static void +Opcode_ivp_savn_2x16u_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_savn_2x16u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0000; +} + +static void +Opcode_ivp_savn_2x16u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x950000; +} + +static void +Opcode_ivp_savn_2x16s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10848000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_savn_2x16s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c8000; +} + +static void +Opcode_ivp_savn_2x16s_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x508000; +} + +static void +Opcode_ivp_savn_2x16s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x948000; +} + +static void +Opcode_ivp_savn_2x16s_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000; +} + +static void +Opcode_ivp_savn_2x16s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x798000; +} + +static void +Opcode_ivp_savn_2x16s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x948000; +} + +static void +Opcode_ivp_lsn_2x16s_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10870000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsn_2x16s_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0000; +} + +static void +Opcode_ivp_lsn_2x16s_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c2000; +} + +static void +Opcode_ivp_lsn_2x16s_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c2000; +} + +static void +Opcode_ivp_lsn_2x16s_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970000; +} + +static void +Opcode_ivp_lsn_2x16s_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10558000; +} + +static void +Opcode_ivp_lsn_2x16s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1097a000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsn_2x16s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a2000; +} + +static void +Opcode_ivp_lsn_2x16s_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x224000; +} + +static void +Opcode_ivp_lsn_2x16s_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x224000; +} + +static void +Opcode_ivp_lsn_2x16s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7a000; +} + +static void +Opcode_ivp_lsn_2x16s_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b4000; +} + +static void +Opcode_ivp_lsn_2x16s_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108e4000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsn_2x16s_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1402000; +} + +static void +Opcode_ivp_lsn_2x16s_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1de000; +} + +static void +Opcode_ivp_lsn_2x16s_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc000; +} + +static void +Opcode_ivp_lsn_2x16s_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e4000; +} + +static void +Opcode_ivp_lsn_2x16s_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10584000; +} + +static void +Opcode_ivp_lsn_2x16s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108e6000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsn_2x16s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140a000; +} + +static void +Opcode_ivp_lsn_2x16s_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec000; +} + +static void +Opcode_ivp_lsn_2x16s_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1de000; +} + +static void +Opcode_ivp_lsn_2x16s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e6000; +} + +static void +Opcode_ivp_lsn_2x16s_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10586000; +} + +static void +Opcode_ivp_ssn_2x16s_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108a8000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssn_2x16s_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1228000; +} + +static void +Opcode_ivp_ssn_2x16s_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_ivp_ssn_2x16s_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a8000; +} + +static void +Opcode_ivp_ssn_2x16s_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109ae000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssn_2x16s_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138e000; +} + +static void +Opcode_ivp_ssn_2x16s_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x584000; +} + +static void +Opcode_ivp_ssn_2x16s_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaae000; +} + +static void +Opcode_ivp_ssn_2x16s_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10932000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssn_2x16s_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d2000; +} + +static void +Opcode_ivp_ssn_2x16s_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560000; +} + +static void +Opcode_ivp_ssn_2x16s_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa32000; +} + +static void +Opcode_ivp_ssn_2x16s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10936000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssn_2x16s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14da000; +} + +static void +Opcode_ivp_ssn_2x16s_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x562000; +} + +static void +Opcode_ivp_ssn_2x16s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa36000; +} + +static void +Opcode_ivp_lsn_2x32_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsn_2x32_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb80000; +} + +static void +Opcode_ivp_lsn_2x32_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_lsn_2x32_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_lsn_2x32_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ivp_lsn_2x32_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280000; +} + +static void +Opcode_ivp_lsn_2x32_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1097e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsn_2x32_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13aa000; +} + +static void +Opcode_ivp_lsn_2x32_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x226000; +} + +static void +Opcode_ivp_lsn_2x32_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x226000; +} + +static void +Opcode_ivp_lsn_2x32_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7e000; +} + +static void +Opcode_ivp_lsn_2x32_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b6000; +} + +static void +Opcode_ivp_lsn_2x32_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108e8000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsn_2x32_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1412000; +} + +static void +Opcode_ivp_lsn_2x32_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee000; +} + +static void +Opcode_ivp_lsn_2x32_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec000; +} + +static void +Opcode_ivp_lsn_2x32_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e8000; +} + +static void +Opcode_ivp_lsn_2x32_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10588000; +} + +static void +Opcode_ivp_lsn_2x32_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108ea000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsn_2x32_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x141a000; +} + +static void +Opcode_ivp_lsn_2x32_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fc000; +} + +static void +Opcode_ivp_lsn_2x32_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee000; +} + +static void +Opcode_ivp_lsn_2x32_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ea000; +} + +static void +Opcode_ivp_lsn_2x32_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058a000; +} + +static void +Opcode_ivp_ssn_2x32_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssn_2x32_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ivp_ssn_2x32_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_ssn_2x32_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ivp_ssn_2x32_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109b2000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssn_2x32_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1396000; +} + +static void +Opcode_ivp_ssn_2x32_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x586000; +} + +static void +Opcode_ivp_ssn_2x32_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab2000; +} + +static void +Opcode_ivp_ssn_2x32_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1093a000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssn_2x32_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14e2000; +} + +static void +Opcode_ivp_ssn_2x32_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x564000; +} + +static void +Opcode_ivp_ssn_2x32_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3a000; +} + +static void +Opcode_ivp_ssn_2x32_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1093e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ssn_2x32_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14ea000; +} + +static void +Opcode_ivp_ssn_2x32_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x566000; +} + +static void +Opcode_ivp_ssn_2x32_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3e000; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20500c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000a; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00010; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180030a; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8680008; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c401000; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ivp_bmaxunx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_bmaxunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18002a0; +} + +static void +Opcode_ivp_bminunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20b00c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bminunx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840000; +} + +static void +Opcode_ivp_bminunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ivp_bminunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800106; +} + +static void +Opcode_ivp_bminunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00018; +} + +static void +Opcode_ivp_bminunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800006; +} + +static void +Opcode_ivp_bminunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9180000; +} + +static void +Opcode_ivp_bminunx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ivp_bminunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c701000; +} + +static void +Opcode_ivp_bminunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0000; +} + +static void +Opcode_ivp_bminunx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ivp_bminunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18003e0; +} + +static void +Opcode_ivp_rbminunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800c11; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rbminunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000053; +} + +static void +Opcode_ivp_rbminunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800353; +} + +static void +Opcode_ivp_rbminunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9500608; +} + +static void +Opcode_ivp_rbminunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6070a0; +} + +static void +Opcode_ivp_rbminunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80090; +} + +static void +Opcode_ivp_rbminunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001a4; +} + +static void +Opcode_ivp_rbmaxunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800cf0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rbmaxunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000072; +} + +static void +Opcode_ivp_rbmaxunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800372; +} + +static void +Opcode_ivp_rbmaxunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9500208; +} + +static void +Opcode_ivp_rbmaxunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607060; +} + +static void +Opcode_ivp_rbmaxunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80070; +} + +static void +Opcode_ivp_rbmaxunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800196; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20100c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800002; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00018; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800302; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8680000; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c203000; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ivp_bmax2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_bmax2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800320; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20700c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740000; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000e; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00010; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180030e; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8780008; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c501000; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ivp_bmin2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ivp_bmin2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18002e0; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800008; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800308; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8600008; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c400000; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_bmaxu2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800280; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20a00c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800104; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00008; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800004; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9100000; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c700000; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780000; +} + +static void +Opcode_ivp_bminu2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_bminu2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18003c0; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20300c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800006; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00018; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800306; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8780000; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c303000; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ivp_bmaxn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800360; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20900c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0000; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800102; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00018; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800002; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9080000; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c601000; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740000; +} + +static void +Opcode_ivp_bminn_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ivp_bminn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18003a0; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20600c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000c; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180030c; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8700008; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c500000; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_bmaxun_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18002c0; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c00c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880000; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800108; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800008; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9200000; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c402000; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ivp_bminun_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ivp_bminun_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800000; +} + +static void +Opcode_ivp_addn_2x32t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36404000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_addn_2x32t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ivp_addn_2x32t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_addn_2x32t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2600100; +} + +static void +Opcode_ivp_addn_2x32t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ivp_addn_2x32t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300200; +} + +static void +Opcode_ivp_addn_2x32t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8800002; +} + +static void +Opcode_ivp_addn_2x32t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c300000; +} + +static void +Opcode_ivp_addn_2x32t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ivp_addn_2x32t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800240; +} + +static void +Opcode_ivp_subn_2x32t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e306000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_subn_2x32t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac0000; +} + +static void +Opcode_ivp_subn_2x32t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940000; +} + +static void +Opcode_ivp_subn_2x32t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00200; +} + +static void +Opcode_ivp_subn_2x32t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400010; +} + +static void +Opcode_ivp_subn_2x32t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700300; +} + +static void +Opcode_ivp_subn_2x32t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00003; +} + +static void +Opcode_ivp_subn_2x32t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c005000; +} + +static void +Opcode_ivp_subn_2x32t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa40000; +} + +static void +Opcode_ivp_subn_2x32t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000a0; +} + +static void +Opcode_ivp_add2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a402800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_add2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1258000; +} + +static void +Opcode_ivp_add2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc58000; +} + +static void +Opcode_ivp_add2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290020a; +} + +static void +Opcode_ivp_add2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00015; +} + +static void +Opcode_ivp_add2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290010a; +} + +static void +Opcode_ivp_add2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c8000b; +} + +static void +Opcode_ivp_add2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8000; +} + +static void +Opcode_ivp_add2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e006400; +} + +static void +Opcode_ivp_add2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb38000; +} + +static void +Opcode_ivp_add2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a8000; +} + +static void +Opcode_ivp_add2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900280; +} + +static void +Opcode_ivp_sub2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38403c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sub2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340000; +} + +static void +Opcode_ivp_sub2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ivp_sub2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x310020c; +} + +static void +Opcode_ivp_sub2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000a; +} + +static void +Opcode_ivp_sub2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0020e; +} + +static void +Opcode_ivp_sub2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e8000e; +} + +static void +Opcode_ivp_sub2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ivp_sub2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e306000; +} + +static void +Opcode_ivp_sub2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_ivp_sub2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ivp_sub2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e00380; +} + +static void +Opcode_ivp_neg2nx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a300b0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_neg2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27500d0e; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_neg2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11080f0; +} + +static void +Opcode_ivp_neg2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf78060; +} + +static void +Opcode_ivp_neg2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330740e; +} + +static void +Opcode_ivp_neg2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f60016; +} + +static void +Opcode_ivp_neg2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f07608; +} + +static void +Opcode_ivp_neg2nx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8340f0; +} + +static void +Opcode_ivp_neg2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94801d9; +} + +static void +Opcode_ivp_neg2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a80e0; +} + +static void +Opcode_ivp_neg2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606d0a; +} + +static void +Opcode_ivp_neg2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20304; +} + +static void +Opcode_ivp_neg2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a80a0; +} + +static void +Opcode_ivp_neg2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2707540; +} + +static void +Opcode_ivp_min2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c401c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_min2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f0000; +} + +static void +Opcode_ivp_min2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_ivp_min2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280020e; +} + +static void +Opcode_ivp_min2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000e; +} + +static void +Opcode_ivp_min2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00200; +} + +static void +Opcode_ivp_min2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d0000c; +} + +static void +Opcode_ivp_min2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_ivp_min2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e107800; +} + +static void +Opcode_ivp_min2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd0000; +} + +static void +Opcode_ivp_min2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_ivp_min2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28002e0; +} + +static void +Opcode_ivp_minu2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a403400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_minu2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308000; +} + +static void +Opcode_ivp_minu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd48000; +} + +static void +Opcode_ivp_minu2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0020e; +} + +static void +Opcode_ivp_minu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00018; +} + +static void +Opcode_ivp_minu2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00206; +} + +static void +Opcode_ivp_minu2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d8000f; +} + +static void +Opcode_ivp_minu2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x548000; +} + +static void +Opcode_ivp_minu2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e206400; +} + +static void +Opcode_ivp_minu2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe8000; +} + +static void +Opcode_ivp_minu2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x448000; +} + +static void +Opcode_ivp_minu2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f002e0; +} + +static void +Opcode_ivp_max2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_max2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ivp_max2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ivp_max2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190030c; +} + +static void +Opcode_ivp_max2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900009; +} + +static void +Opcode_ivp_max2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0010c; +} + +static void +Opcode_ivp_max2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9380006; +} + +static void +Opcode_ivp_max2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ivp_max2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e106000; +} + +static void +Opcode_ivp_max2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba0000; +} + +static void +Opcode_ivp_max2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_max2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e002a0; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e401400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12d8000; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf8000; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0020c; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190001c; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0010e; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c8000d; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x518000; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e106c00; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb8000; +} + +static void +Opcode_ivp_maxu2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x418000; +} + +static void +Opcode_ivp_maxu2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d002c0; +} + +static void +Opcode_ivp_lt2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b8000; +} + +static void +Opcode_ivp_lt2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b8000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lt2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c1c00; +} + +static void +Opcode_ivp_lt2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec5000; +} + +static void +Opcode_ivp_lt2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8306; +} + +static void +Opcode_ivp_lt2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04818; +} + +static void +Opcode_ivp_lt2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8206; +} + +static void +Opcode_ivp_lt2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000; +} + +static void +Opcode_ivp_lt2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b84008; +} + +static void +Opcode_ivp_lt2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c2400; +} + +static void +Opcode_ivp_lt2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c51d000; +} + +static void +Opcode_ivp_lt2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000; +} + +static void +Opcode_ivp_lt2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd42400; +} + +static void +Opcode_ivp_lt2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3818060; +} + +static void +Opcode_ivp_lt2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b8000; +} + +static void +Opcode_ivp_lt2nx8_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x981400; +} + +static void +Opcode_ivp_le2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b4000; +} + +static void +Opcode_ivp_le2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305a8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_le2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1481400; +} + +static void +Opcode_ivp_le2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec4400; +} + +static void +Opcode_ivp_le2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8300; +} + +static void +Opcode_ivp_le2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04810; +} + +static void +Opcode_ivp_le2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8200; +} + +static void +Opcode_ivp_le2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000; +} + +static void +Opcode_ivp_le2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9884008; +} + +static void +Opcode_ivp_le2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0c00; +} + +static void +Opcode_ivp_le2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c41c000; +} + +static void +Opcode_ivp_le2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000; +} + +static void +Opcode_ivp_le2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40c00; +} + +static void +Opcode_ivp_le2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3818000; +} + +static void +Opcode_ivp_le2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b4000; +} + +static void +Opcode_ivp_le2nx8_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970c00; +} + +static void +Opcode_ivp_eq2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x234000; +} + +static void +Opcode_ivp_eq2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305a8000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_eq2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1480400; +} + +static void +Opcode_ivp_eq2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ivp_eq2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a8304; +} + +static void +Opcode_ivp_eq2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04800; +} + +static void +Opcode_ivp_eq2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a8204; +} + +static void +Opcode_ivp_eq2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_ivp_eq2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b04000; +} + +static void +Opcode_ivp_eq2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ivp_eq2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c50c000; +} + +static void +Opcode_ivp_eq2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_ivp_eq2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ivp_eq2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3808040; +} + +static void +Opcode_ivp_eq2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x634000; +} + +static void +Opcode_ivp_eq2nx8_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970000; +} + +static void +Opcode_ivp_neq2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b8008; +} + +static void +Opcode_ivp_neq2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_neq2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1480c00; +} + +static void +Opcode_ivp_neq2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec5c00; +} + +static void +Opcode_ivp_neq2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a830a; +} + +static void +Opcode_ivp_neq2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04c18; +} + +static void +Opcode_ivp_neq2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a820a; +} + +static void +Opcode_ivp_neq2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec008; +} + +static void +Opcode_ivp_neq2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90d4008; +} + +static void +Opcode_ivp_neq2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c3c00; +} + +static void +Opcode_ivp_neq2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c42d000; +} + +static void +Opcode_ivp_neq2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec008; +} + +static void +Opcode_ivp_neq2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd43c00; +} + +static void +Opcode_ivp_neq2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3828020; +} + +static void +Opcode_ivp_neq2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b8008; +} + +static void +Opcode_ivp_neq2nx8_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x991c00; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x238008; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b0800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1440800; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec1800; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0308; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04c08; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0208; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0008; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9058008; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c3000; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c434000; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0008; +} + +static void +Opcode_ivp_ltu2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd43000; +} + +static void +Opcode_ivp_ltu2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3830000; +} + +static void +Opcode_ivp_ltu2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x638008; +} + +static void +Opcode_ivp_ltu2nx8_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x991000; +} + +static void +Opcode_ivp_leu2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x334008; +} + +static void +Opcode_ivp_leu2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305a9800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_leu2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c1000; +} + +static void +Opcode_ivp_leu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0c00; +} + +static void +Opcode_ivp_leu2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0304; +} + +static void +Opcode_ivp_leu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04c00; +} + +static void +Opcode_ivp_leu2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0204; +} + +static void +Opcode_ivp_leu2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8008; +} + +static void +Opcode_ivp_leu2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a04008; +} + +static void +Opcode_ivp_leu2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c1800; +} + +static void +Opcode_ivp_leu2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c514000; +} + +static void +Opcode_ivp_leu2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8008; +} + +static void +Opcode_ivp_leu2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd41800; +} + +static void +Opcode_ivp_leu2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3810040; +} + +static void +Opcode_ivp_leu2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x734008; +} + +static void +Opcode_ivp_leu2nx8_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x971800; +} + +static void +Opcode_ivp_add2nx8t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36400000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_add2nx8t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ivp_add2nx8t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_add2nx8t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2600000; +} + +static void +Opcode_ivp_add2nx8t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ivp_add2nx8t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300000; +} + +static void +Opcode_ivp_add2nx8t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8800000; +} + +static void +Opcode_ivp_add2nx8t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c200000; +} + +static void +Opcode_ivp_add2nx8t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_add2nx8t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800200; +} + +static void +Opcode_ivp_sub2nx8t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a306000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sub2nx8t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa40000; +} + +static void +Opcode_ivp_sub2nx8t_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000; +} + +static void +Opcode_ivp_sub2nx8t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00200; +} + +static void +Opcode_ivp_sub2nx8t_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300018; +} + +static void +Opcode_ivp_sub2nx8t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500300; +} + +static void +Opcode_ivp_sub2nx8t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00001; +} + +static void +Opcode_ivp_sub2nx8t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c703000; +} + +static void +Opcode_ivp_sub2nx8t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0000; +} + +static void +Opcode_ivp_sub2nx8t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800360; +} + +static void +Opcode_ivp_selnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_selnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ivp_selnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ivp_selnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ivp_seln_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34400000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_seln_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200000; +} + +static void +Opcode_ivp_seln_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200000; +} + +static void +Opcode_ivp_seln_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200000; +} + +static void +Opcode_ivp_seln_2x32t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_seln_2x32t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ivp_seln_2x32t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ivp_seln_2x32t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ivp_shfln_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30600200; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_shfln_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800800; +} + +static void +Opcode_ivp_shfln_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000800; +} + +static void +Opcode_ivp_shfln_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000800; +} + +static void +Opcode_ivp_sllin_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c503800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sllin_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400008; +} + +static void +Opcode_ivp_sllin_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0030e; +} + +static void +Opcode_ivp_sllin_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9700004; +} + +static void +Opcode_ivp_sllin_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e406800; +} + +static void +Opcode_ivp_sllin_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc70000; +} + +static void +Opcode_ivp_sllin_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28003e0; +} + +static void +Opcode_ivp_slsin_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a503c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_slsin_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3700008; +} + +static void +Opcode_ivp_slsin_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0030e; +} + +static void +Opcode_ivp_slsin_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9700007; +} + +static void +Opcode_ivp_slsin_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e407400; +} + +static void +Opcode_ivp_slsin_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc88000; +} + +static void +Opcode_ivp_slsin_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b003e0; +} + +static void +Opcode_ivp_srain_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srain_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000a; +} + +static void +Opcode_ivp_srain_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00200; +} + +static void +Opcode_ivp_srain_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9780002; +} + +static void +Opcode_ivp_srain_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e506000; +} + +static void +Opcode_ivp_srain_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca0000; +} + +static void +Opcode_ivp_srain_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e003e0; +} + +static void +Opcode_ivp_srlin_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srlin_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350000a; +} + +static void +Opcode_ivp_srlin_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00202; +} + +static void +Opcode_ivp_srlin_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9780005; +} + +static void +Opcode_ivp_srlin_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e506c00; +} + +static void +Opcode_ivp_srlin_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb8000; +} + +static void +Opcode_ivp_srlin_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500000; +} + +static void +Opcode_ivp_slln_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38503c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_slln_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3600008; +} + +static void +Opcode_ivp_slln_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0030e; +} + +static void +Opcode_ivp_slln_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9700006; +} + +static void +Opcode_ivp_slln_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e407000; +} + +static void +Opcode_ivp_slln_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ivp_slln_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a003e0; +} + +static void +Opcode_ivp_srln_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srln_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370000a; +} + +static void +Opcode_ivp_srln_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00202; +} + +static void +Opcode_ivp_srln_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9780007; +} + +static void +Opcode_ivp_srln_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e507400; +} + +static void +Opcode_ivp_srln_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc8000; +} + +static void +Opcode_ivp_srln_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700000; +} + +static void +Opcode_ivp_slan_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a503800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_slan_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3300008; +} + +static void +Opcode_ivp_slan_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0030e; +} + +static void +Opcode_ivp_slan_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9700003; +} + +static void +Opcode_ivp_slan_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e406400; +} + +static void +Opcode_ivp_slan_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc68000; +} + +static void +Opcode_ivp_slan_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f003c0; +} + +static void +Opcode_ivp_sran_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sran_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000a; +} + +static void +Opcode_ivp_sran_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00202; +} + +static void +Opcode_ivp_sran_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9780004; +} + +static void +Opcode_ivp_sran_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e506800; +} + +static void +Opcode_ivp_sran_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb0000; +} + +static void +Opcode_ivp_sran_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400000; +} + +static void +Opcode_ivp_slsn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e503c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_slsn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x310000a; +} + +static void +Opcode_ivp_slsn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00200; +} + +static void +Opcode_ivp_slsn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9780001; +} + +static void +Opcode_ivp_slsn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e407c00; +} + +static void +Opcode_ivp_slsn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc98000; +} + +static void +Opcode_ivp_slsn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d003e0; +} + +static void +Opcode_ivp_srsn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f400c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srsn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x310000c; +} + +static void +Opcode_ivp_srsn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00204; +} + +static void +Opcode_ivp_srsn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400009; +} + +static void +Opcode_ivp_srsn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e507c00; +} + +static void +Opcode_ivp_srsn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd8000; +} + +static void +Opcode_ivp_srsn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500020; +} + +static void +Opcode_ivp_raddn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502030; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000055; +} + +static void +Opcode_ivp_raddn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800355; +} + +static void +Opcode_ivp_raddn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c02a00; +} + +static void +Opcode_ivp_raddn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607860; +} + +static void +Opcode_ivp_raddn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd900f0; +} + +static void +Opcode_ivp_raddn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c001b7; +} + +static void +Opcode_ivp_rmaxn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502421; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rmaxn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100065; +} + +static void +Opcode_ivp_rmaxn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900365; +} + +static void +Opcode_ivp_rmaxn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c82c00; +} + +static void +Opcode_ivp_rmaxn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607c70; +} + +static void +Opcode_ivp_rmaxn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb80f0; +} + +static void +Opcode_ivp_rmaxn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f001b6; +} + +static void +Opcode_ivp_rminn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502821; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rminn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200065; +} + +static void +Opcode_ivp_rminn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00365; +} + +static void +Opcode_ivp_rminn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d02c00; +} + +static void +Opcode_ivp_rminn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607871; +} + +static void +Opcode_ivp_rminn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd38010; +} + +static void +Opcode_ivp_rminn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001c6; +} + +static void +Opcode_ivp_rmaxun_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502820; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rmaxun_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200045; +} + +static void +Opcode_ivp_rmaxun_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00345; +} + +static void +Opcode_ivp_rmaxun_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d02800; +} + +static void +Opcode_ivp_rmaxun_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607851; +} + +static void +Opcode_ivp_rmaxun_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd38000; +} + +static void +Opcode_ivp_rmaxun_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001c4; +} + +static void +Opcode_ivp_rminun_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502c20; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rminun_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3300045; +} + +static void +Opcode_ivp_rminun_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b00345; +} + +static void +Opcode_ivp_rminun_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d82800; +} + +static void +Opcode_ivp_rminun_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607c51; +} + +static void +Opcode_ivp_rminun_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd38020; +} + +static void +Opcode_ivp_rminun_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001d4; +} + +static void +Opcode_ivp_raddn_2x32t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800ca0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddn_2x32t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000061; +} + +static void +Opcode_ivp_raddn_2x32t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800361; +} + +static void +Opcode_ivp_raddn_2x32t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01400; +} + +static void +Opcode_ivp_raddn_2x32t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e305020; +} + +static void +Opcode_ivp_raddn_2x32t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80020; +} + +static void +Opcode_ivp_raddn_2x32t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800185; +} + +static void +Opcode_ivp_abs2nx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a30040; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_abs2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27500c0a; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_abs2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11180e0; +} + +static void +Opcode_ivp_abs2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf50060; +} + +static void +Opcode_ivp_abs2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330500e; +} + +static void +Opcode_ivp_abs2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f60002; +} + +static void +Opcode_ivp_abs2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f05208; +} + +static void +Opcode_ivp_abs2nx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82c0c0; +} + +static void +Opcode_ivp_abs2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94800c9; +} + +static void +Opcode_ivp_abs2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8040; +} + +static void +Opcode_ivp_abs2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606c08; +} + +static void +Opcode_ivp_abs2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20200; +} + +static void +Opcode_ivp_abs2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8000; +} + +static void +Opcode_ivp_abs2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2705140; +} + +static void +Opcode_ivp_absn_2x32_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a30070; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_absn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27500f0a; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_absn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11182f0; +} + +static void +Opcode_ivp_absn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf68040; +} + +static void +Opcode_ivp_absn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3305c0e; +} + +static void +Opcode_ivp_absn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f60013; +} + +static void +Opcode_ivp_absn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f05e08; +} + +static void +Opcode_ivp_absn_2x32_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82c0f0; +} + +static void +Opcode_ivp_absn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94800f9; +} + +static void +Opcode_ivp_absn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8080; +} + +static void +Opcode_ivp_absn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606e08; +} + +static void +Opcode_ivp_absn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20202; +} + +static void +Opcode_ivp_absn_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8040; +} + +static void +Opcode_ivp_absn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2705d40; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c403800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330000; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd70000; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100208; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000a; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0020c; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e8000c; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x570000; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e207800; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x470000; +} + +static void +Opcode_ivp_mulsgnsnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c00380; +} + +static void +Opcode_ivp_rotri2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25500c08; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rotri2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe88008; +} + +static void +Opcode_ivp_rotri2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320400e; +} + +static void +Opcode_ivp_rotri2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d84400; +} + +static void +Opcode_ivp_rotri2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e04208; +} + +static void +Opcode_ivp_rotri2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9480088; +} + +static void +Opcode_ivp_rotri2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606808; +} + +static void +Opcode_ivp_rotri2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10200; +} + +static void +Opcode_ivp_rotri2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2604140; +} + +static void +Opcode_ivp_rotrinx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21500c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rotrinx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe70000; +} + +static void +Opcode_ivp_rotrinx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000e; +} + +static void +Opcode_ivp_rotrinx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04000; +} + +static void +Opcode_ivp_rotrinx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00208; +} + +static void +Opcode_ivp_rotrinx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940000e; +} + +static void +Opcode_ivp_rotrinx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606000; +} + +static void +Opcode_ivp_rotrinx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ivp_rotrinx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400140; +} + +static void +Opcode_ivp_rotrin_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a503400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rotrin_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0030e; +} + +static void +Opcode_ivp_rotrin_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0030c; +} + +static void +Opcode_ivp_rotrin_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9680007; +} + +static void +Opcode_ivp_rotrin_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e307400; +} + +static void +Opcode_ivp_rotrin_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc48000; +} + +static void +Opcode_ivp_rotrin_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b003c0; +} + +static void +Opcode_ivp_rotrnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c503400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rotrnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000008; +} + +static void +Opcode_ivp_rotrnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280030e; +} + +static void +Opcode_ivp_rotrnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9700000; +} + +static void +Opcode_ivp_rotrnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e307800; +} + +static void +Opcode_ivp_rotrnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc50000; +} + +static void +Opcode_ivp_rotrnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c003c0; +} + +static void +Opcode_ivp_rotrn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e503400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rotrn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100008; +} + +static void +Opcode_ivp_rotrn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290030e; +} + +static void +Opcode_ivp_rotrn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9700001; +} + +static void +Opcode_ivp_rotrn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e307c00; +} + +static void +Opcode_ivp_rotrn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc58000; +} + +static void +Opcode_ivp_rotrn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d003c0; +} + +static void +Opcode_ivp_addn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e402800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_addn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1268000; +} + +static void +Opcode_ivp_addn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc68000; +} + +static void +Opcode_ivp_addn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0020a; +} + +static void +Opcode_ivp_addn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00015; +} + +static void +Opcode_ivp_addn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0010a; +} + +static void +Opcode_ivp_addn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d8000b; +} + +static void +Opcode_ivp_addn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b8000; +} + +static void +Opcode_ivp_addn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e006c00; +} + +static void +Opcode_ivp_addn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb48000; +} + +static void +Opcode_ivp_addn_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b8000; +} + +static void +Opcode_ivp_addn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b00280; +} + +static void +Opcode_ivp_subn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c403c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_subn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1350000; +} + +static void +Opcode_ivp_subn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd90000; +} + +static void +Opcode_ivp_subn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100300; +} + +static void +Opcode_ivp_subn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000b; +} + +static void +Opcode_ivp_subn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800308; +} + +static void +Opcode_ivp_subn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f0000c; +} + +static void +Opcode_ivp_subn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_ivp_subn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e306800; +} + +static void +Opcode_ivp_subn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30000; +} + +static void +Opcode_ivp_subn_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_ivp_subn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28003a0; +} + +static void +Opcode_ivp_negn_2x32_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a300e0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30602002; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_negn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11082e0; +} + +static void +Opcode_ivp_negn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf400a0; +} + +static void +Opcode_ivp_negn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801100; +} + +static void +Opcode_ivp_negn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e68000; +} + +static void +Opcode_ivp_negn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001100; +} + +static void +Opcode_ivp_negn_2x32_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83c0e0; +} + +static void +Opcode_ivp_negn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9580020; +} + +static void +Opcode_ivp_negn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8120; +} + +static void +Opcode_ivp_negn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606f0a; +} + +static void +Opcode_ivp_negn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20306; +} + +static void +Opcode_ivp_negn_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a80e0; +} + +static void +Opcode_ivp_negn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000c00; +} + +static void +Opcode_ivp_minn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e403000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_minn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ivp_minn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd38000; +} + +static void +Opcode_ivp_minn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0020e; +} + +static void +Opcode_ivp_minn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00018; +} + +static void +Opcode_ivp_minn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00204; +} + +static void +Opcode_ivp_minn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d8000d; +} + +static void +Opcode_ivp_minn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ivp_minn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e206000; +} + +static void +Opcode_ivp_minn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe0000; +} + +static void +Opcode_ivp_minn_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ivp_minn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d002e0; +} + +static void +Opcode_ivp_minun_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e403400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_minun_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318000; +} + +static void +Opcode_ivp_minun_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd58000; +} + +static void +Opcode_ivp_minun_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100202; +} + +static void +Opcode_ivp_minun_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00019; +} + +static void +Opcode_ivp_minun_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00208; +} + +static void +Opcode_ivp_minun_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e0000d; +} + +static void +Opcode_ivp_minun_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x558000; +} + +static void +Opcode_ivp_minun_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e206c00; +} + +static void +Opcode_ivp_minun_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf8000; +} + +static void +Opcode_ivp_minun_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x458000; +} + +static void +Opcode_ivp_minun_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900380; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e401000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12d0000; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce8000; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0020c; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190001b; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0010e; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000f; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510000; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e106800; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb0000; +} + +static void +Opcode_ivp_maxn_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_ivp_maxn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b002c0; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e401800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e8000; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd08000; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0020c; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190001d; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0010e; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c8000f; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x528000; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e107400; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc8000; +} + +static void +Opcode_ivp_maxun_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x428000; +} + +static void +Opcode_ivp_maxun_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f002c0; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a403800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1328000; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd68000; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100206; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00019; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0020a; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e0000f; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x568000; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e207400; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc08000; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x468000; +} + +static void +Opcode_ivp_mulsgnn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b00380; +} + +static void +Opcode_ivp_nsan_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30603c02; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_nsan_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380110e; +} + +static void +Opcode_ivp_nsan_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300110e; +} + +static void +Opcode_ivp_nsan_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9580027; +} + +static void +Opcode_ivp_nsan_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606f0c; +} + +static void +Opcode_ivp_nsan_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2030a; +} + +static void +Opcode_ivp_nsan_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000f20; +} + +static void +Opcode_ivp_nsaun_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30602502; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_nsaun_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801502; +} + +static void +Opcode_ivp_nsaun_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001502; +} + +static void +Opcode_ivp_nsaun_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9580031; +} + +static void +Opcode_ivp_nsaun_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606d0e; +} + +static void +Opcode_ivp_nsaun_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2030c; +} + +static void +Opcode_ivp_nsaun_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000d40; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b8000; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b8400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400c00; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec5400; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a8308; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04818; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a8208; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9054008; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c2c00; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c42c000; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000; +} + +static void +Opcode_ivp_ltn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd42c00; +} + +static void +Opcode_ivp_ltn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3828000; +} + +static void +Opcode_ivp_ltn_2x32_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b8000; +} + +static void +Opcode_ivp_ltn_2x32_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x981c00; +} + +static void +Opcode_ivp_len_2x32_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b4008; +} + +static void +Opcode_ivp_len_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305a9400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_len_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1481c00; +} + +static void +Opcode_ivp_len_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec4800; +} + +static void +Opcode_ivp_len_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8302; +} + +static void +Opcode_ivp_len_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04c10; +} + +static void +Opcode_ivp_len_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b8202; +} + +static void +Opcode_ivp_len_2x32_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4008; +} + +static void +Opcode_ivp_len_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9984008; +} + +static void +Opcode_ivp_len_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c1400; +} + +static void +Opcode_ivp_len_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c41d000; +} + +static void +Opcode_ivp_len_2x32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4008; +} + +static void +Opcode_ivp_len_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd41400; +} + +static void +Opcode_ivp_len_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3818020; +} + +static void +Opcode_ivp_len_2x32_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b4008; +} + +static void +Opcode_ivp_len_2x32_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x971400; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x334000; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305a8800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1481000; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0400; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0300; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04800; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0200; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9804008; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0800; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c414000; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000; +} + +static void +Opcode_ivp_eqn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40800; +} + +static void +Opcode_ivp_eqn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3810000; +} + +static void +Opcode_ivp_eqn_2x32_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x734000; +} + +static void +Opcode_ivp_eqn_2x32_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970800; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2bc000; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b9000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c0c00; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec6000; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b830a; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05010; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b820a; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90dc008; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c4400; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c43d000; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000; +} + +static void +Opcode_ivp_neqn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd44400; +} + +static void +Opcode_ivp_neqn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3838020; +} + +static void +Opcode_ivp_neqn_2x32_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6bc000; +} + +static void +Opcode_ivp_neqn_2x32_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a0400; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x338008; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1480800; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec1c00; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a030a; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04c08; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a020a; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8008; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90d0008; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c3800; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c425000; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8008; +} + +static void +Opcode_ivp_ltun_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd43800; +} + +static void +Opcode_ivp_ltun_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3820020; +} + +static void +Opcode_ivp_ltun_2x32_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x738008; +} + +static void +Opcode_ivp_ltun_2x32_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x991800; +} + +static void +Opcode_ivp_leun_2x32_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x238000; +} + +static void +Opcode_ivp_leun_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_leun_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c1800; +} + +static void +Opcode_ivp_leun_2x32_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec1000; +} + +static void +Opcode_ivp_leun_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0306; +} + +static void +Opcode_ivp_leun_2x32_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04808; +} + +static void +Opcode_ivp_leun_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28b0206; +} + +static void +Opcode_ivp_leun_2x32_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_ivp_leun_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b04008; +} + +static void +Opcode_ivp_leun_2x32_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c2000; +} + +static void +Opcode_ivp_leun_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c515000; +} + +static void +Opcode_ivp_leun_2x32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_ivp_leun_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd42000; +} + +static void +Opcode_ivp_leun_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3810060; +} + +static void +Opcode_ivp_leun_2x32_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x638000; +} + +static void +Opcode_ivp_leun_2x32_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x981000; +} + +static void +Opcode_ivp_lat2nx8_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_lat2nx8_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_lat2nx8_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_lat2nx8_xp_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_muluu2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260009; +} + +static void +Opcode_ivp_muluu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80005; +} + +static void +Opcode_ivp_muluu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06409; +} + +static void +Opcode_ivp_muluu2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180009; +} + +static void +Opcode_ivp_muluu2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130009; +} + +static void +Opcode_ivp_muluu2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650003; +} + +static void +Opcode_ivp_muluua2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26000a; +} + +static void +Opcode_ivp_muluua2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80006; +} + +static void +Opcode_ivp_muluua2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06809; +} + +static void +Opcode_ivp_muluua2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000a; +} + +static void +Opcode_ivp_muluua2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000a; +} + +static void +Opcode_ivp_muluua2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650004; +} + +static void +Opcode_ivp_mulus2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c00b; +} + +static void +Opcode_ivp_mulus2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0007; +} + +static void +Opcode_ivp_mulus2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c06; +} + +static void +Opcode_ivp_mulus2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000b; +} + +static void +Opcode_ivp_mulus2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000b; +} + +static void +Opcode_ivp_mulus2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c005; +} + +static void +Opcode_ivp_mulusa2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c00c; +} + +static void +Opcode_ivp_mulusa2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0008; +} + +static void +Opcode_ivp_mulusa2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07007; +} + +static void +Opcode_ivp_mulusa2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000c; +} + +static void +Opcode_ivp_mulusa2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000c; +} + +static void +Opcode_ivp_mulusa2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c006; +} + +static void +Opcode_ivp_muli2nx8x16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_ivp_muli2nx8x16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00001; +} + +static void +Opcode_ivp_muli2nx8x16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400001; +} + +static void +Opcode_ivp_mulai2nx8x16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_mulai2nx8x16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00000; +} + +static void +Opcode_ivp_mulai2nx8x16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_mulusi2nx8x16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_ivp_mulusi2nx8x16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00003; +} + +static void +Opcode_ivp_mulusi2nx8x16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400003; +} + +static void +Opcode_ivp_mulusai2nx8x16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_ivp_mulusai2nx8x16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00002; +} + +static void +Opcode_ivp_mulusai2nx8x16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400002; +} + +static void +Opcode_ivp_muli2nr8x16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400020; +} + +static void +Opcode_ivp_muli2nr8x16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e08000; +} + +static void +Opcode_ivp_muli2nr8x16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800200; +} + +static void +Opcode_ivp_mulai2nr8x16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_mulai2nr8x16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00000; +} + +static void +Opcode_ivp_mulai2nr8x16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ivp_mulusi2nr8x16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400060; +} + +static void +Opcode_ivp_mulusi2nr8x16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e18000; +} + +static void +Opcode_ivp_mulusi2nr8x16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800600; +} + +static void +Opcode_ivp_mulusai2nr8x16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400040; +} + +static void +Opcode_ivp_mulusai2nr8x16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e10000; +} + +static void +Opcode_ivp_mulusai2nr8x16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800400; +} + +static void +Opcode_ivp_mulusa2n8xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c300; +} + +static void +Opcode_ivp_mulusa2n8xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33810; +} + +static void +Opcode_ivp_mulusa2n8xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200060; +} + +static void +Opcode_ivp_mulusa2n8xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0060; +} + +static void +Opcode_ivp_mulusa2n8xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x161060; +} + +static void +Opcode_ivp_mulusa2n8xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65c030; +} + +static void +Opcode_ivp_mulus2n8xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c200; +} + +static void +Opcode_ivp_mulus2n8xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33800; +} + +static void +Opcode_ivp_mulus2n8xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200040; +} + +static void +Opcode_ivp_mulus2n8xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0040; +} + +static void +Opcode_ivp_mulus2n8xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x161040; +} + +static void +Opcode_ivp_mulus2n8xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65c020; +} + +static void +Opcode_ivp_mula2n8xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c100; +} + +static void +Opcode_ivp_mula2n8xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf23c10; +} + +static void +Opcode_ivp_mula2n8xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200020; +} + +static void +Opcode_ivp_mula2n8xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0020; +} + +static void +Opcode_ivp_mula2n8xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x161020; +} + +static void +Opcode_ivp_mula2n8xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65c010; +} + +static void +Opcode_ivp_mul2n8xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c000; +} + +static void +Opcode_ivp_mul2n8xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf23c00; +} + +static void +Opcode_ivp_mul2n8xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200000; +} + +static void +Opcode_ivp_mul2n8xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_ivp_mul2n8xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x161000; +} + +static void +Opcode_ivp_mul2n8xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65c000; +} + +static void +Opcode_ivp_dsel2nx8i_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_dsel2nx8i_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000000; +} + +static void +Opcode_ivp_dsel2nx8i_h_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_dsel2nx8i_h_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a004000; +} + +static void +Opcode_ivp_dselnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_dselnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000000; +} + +static void +Opcode_ivp_dselnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_dselnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_injbi2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a450000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_injbi2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3038200; +} + +static void +Opcode_ivp_injbi2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1958200; +} + +static void +Opcode_ivp_injbi2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c03000; +} + +static void +Opcode_ivp_injbi2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c444000; +} + +static void +Opcode_ivp_extbi2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x217c0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extbi2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28f830c; +} + +static void +Opcode_ivp_extbi2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28f820c; +} + +static void +Opcode_ivp_extbi2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980c008; +} + +static void +Opcode_ivp_extbi2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c444010; +} + +static void +Opcode_ivp_extbi2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd800e0; +} + +static void +Opcode_ivp_extbi2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3888000; +} + +static void +Opcode_ivp_movva32_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc007; +} + +static void +Opcode_ivp_movva32_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282005; +} + +static void +Opcode_ivp_movva32_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282005; +} + +static void +Opcode_ivp_movva32_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8005; +} + +static void +Opcode_ivp_movva32_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8005; +} + +static void +Opcode_ivp_movva32_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6007; +} + +static void +Opcode_ivp_movav32_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d7a00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movav32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a450003; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movav32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1459600; +} + +static void +Opcode_ivp_movav32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3038203; +} + +static void +Opcode_ivp_movav32_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54600d; +} + +static void +Opcode_ivp_movav32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29f820d; +} + +static void +Opcode_ivp_movav32_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9dba00; +} + +static void +Opcode_ivp_movav32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980e009; +} + +static void +Opcode_ivp_movav32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c30e000; +} + +static void +Opcode_ivp_movav32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcfc003; +} + +static void +Opcode_ivp_movav32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3988010; +} + +static void +Opcode_ivp_movww_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800d; +} + +static void +Opcode_ivp_movww_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf518e0; +} + +static void +Opcode_ivp_movww_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e69803; +} + +static void +Opcode_ivp_movww_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000e; +} + +static void +Opcode_ivp_movww_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15100b; +} + +static void +Opcode_ivp_movww_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65b004; +} + +static void +Opcode_ivp_ls2nx8_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10858000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ls2nx8_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d8000; +} + +static void +Opcode_ivp_ls2nx8_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c000; +} + +static void +Opcode_ivp_ls2nx8_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c000; +} + +static void +Opcode_ivp_ls2nx8_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x958000; +} + +static void +Opcode_ivp_ls2nx8_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10540000; +} + +static void +Opcode_ivp_ls2nx8_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1096e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ls2nx8_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138a000; +} + +static void +Opcode_ivp_ls2nx8_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21e000; +} + +static void +Opcode_ivp_ls2nx8_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21e000; +} + +static void +Opcode_ivp_ls2nx8_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6e000; +} + +static void +Opcode_ivp_ls2nx8_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae000; +} + +static void +Opcode_ivp_ls2nx8_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108c8000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ls2nx8_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdec000; +} + +static void +Opcode_ivp_ls2nx8_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1da000; +} + +static void +Opcode_ivp_ls2nx8_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca000; +} + +static void +Opcode_ivp_ls2nx8_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c8000; +} + +static void +Opcode_ivp_ls2nx8_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10578000; +} + +static void +Opcode_ivp_ls2nx8_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108ca000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ls2nx8_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdee000; +} + +static void +Opcode_ivp_ls2nx8_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea000; +} + +static void +Opcode_ivp_ls2nx8_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1da000; +} + +static void +Opcode_ivp_ls2nx8_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ca000; +} + +static void +Opcode_ivp_ls2nx8_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057a000; +} + +static void +Opcode_ivp_ss2nx8_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10890000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ss2nx8_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1210000; +} + +static void +Opcode_ivp_ss2nx8_i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x518000; +} + +static void +Opcode_ivp_ss2nx8_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x990000; +} + +static void +Opcode_ivp_ss2nx8_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109a2000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ss2nx8_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b4000; +} + +static void +Opcode_ivp_ss2nx8_ip_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57e000; +} + +static void +Opcode_ivp_ss2nx8_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa2000; +} + +static void +Opcode_ivp_ss2nx8_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1091a000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ss2nx8_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14a2000; +} + +static void +Opcode_ivp_ss2nx8_x_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x554000; +} + +static void +Opcode_ivp_ss2nx8_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1a000; +} + +static void +Opcode_ivp_ss2nx8_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1091e000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_ss2nx8_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14aa000; +} + +static void +Opcode_ivp_ss2nx8_xp_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x556000; +} + +static void +Opcode_ivp_ss2nx8_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1e000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107e8000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1068000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14a000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14a000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e8000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f8000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x738000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e8000; +} + +static void +Opcode_ivp_lanx8s_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107f0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f0000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f0000; +} + +static void +Opcode_ivp_lanx8u_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e0000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f0000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e0000; +} + +static void +Opcode_ivp_la2nx8_xp_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e402400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1248000; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc48000; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f00208; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00014; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f00108; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9300007; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x498000; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e105c00; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb28000; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x398000; +} + +static void +Opcode_ivp_abssubu2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f000e0; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a402400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1238000; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc38000; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d00208; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00014; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d00108; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9300005; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x488000; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e105800; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb18000; +} + +static void +Opcode_ivp_abssub2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x388000; +} + +static void +Opcode_ivp_abssub2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d000e0; +} + +static void +Opcode_ivp_movvint8_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fa080; +} + +static void +Opcode_ivp_movvint8_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x256000; +} + +static void +Opcode_ivp_movvint8_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x256000; +} + +static void +Opcode_ivp_movvint8_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x196010; +} + +static void +Opcode_ivp_movvint8_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x196080; +} + +static void +Opcode_ivp_movvint8_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b4080; +} + +static void +Opcode_ivp_movva8_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc008; +} + +static void +Opcode_ivp_movva8_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282006; +} + +static void +Opcode_ivp_movva8_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282006; +} + +static void +Opcode_ivp_movva8_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8006; +} + +static void +Opcode_ivp_movva8_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8006; +} + +static void +Opcode_ivp_movva8_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2000; +} + +static void +Opcode_ivp_movavu8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a50200; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movavu8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a450009; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movavu8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510400; +} + +static void +Opcode_ivp_movavu8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3038209; +} + +static void +Opcode_ivp_movavu8_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54800c; +} + +static void +Opcode_ivp_movavu8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2cf820d; +} + +static void +Opcode_ivp_movavu8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d7800; +} + +static void +Opcode_ivp_movavu8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980e00c; +} + +static void +Opcode_ivp_movavu8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c20e002; +} + +static void +Opcode_ivp_movavu8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcfc009; +} + +static void +Opcode_ivp_movavu8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c88010; +} + +static void +Opcode_ivp_slli2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25500c0c; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_slli2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8800c; +} + +static void +Opcode_ivp_slli2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320600e; +} + +static void +Opcode_ivp_slli2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc4400; +} + +static void +Opcode_ivp_slli2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e06208; +} + +static void +Opcode_ivp_slli2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94800c8; +} + +static void +Opcode_ivp_slli2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e60680c; +} + +static void +Opcode_ivp_slli2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10300; +} + +static void +Opcode_ivp_slli2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2606140; +} + +static void +Opcode_ivp_srai2nx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a10000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srai2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27500c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srai2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100080; +} + +static void +Opcode_ivp_srai2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe90000; +} + +static void +Opcode_ivp_srai2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000e; +} + +static void +Opcode_ivp_srai2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e80000; +} + +static void +Opcode_ivp_srai2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00208; +} + +static void +Opcode_ivp_srai2nx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820080; +} + +static void +Opcode_ivp_srai2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9480009; +} + +static void +Opcode_ivp_srai2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606c00; +} + +static void +Opcode_ivp_srai2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_ivp_srai2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700140; +} + +static void +Opcode_ivp_srli2nx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a10080; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srli2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27500c04; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_srli2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100280; +} + +static void +Opcode_ivp_srli2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe98000; +} + +static void +Opcode_ivp_srli2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330200e; +} + +static void +Opcode_ivp_srli2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f80000; +} + +static void +Opcode_ivp_srli2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f02208; +} + +static void +Opcode_ivp_srli2nx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x824080; +} + +static void +Opcode_ivp_srli2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9480049; +} + +static void +Opcode_ivp_srli2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606c04; +} + +static void +Opcode_ivp_srli2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20100; +} + +static void +Opcode_ivp_srli2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2702140; +} + +static void +Opcode_ivp_packl2nx24_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1740d8; +} + +static void +Opcode_ivp_packl2nx24_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268058; +} + +static void +Opcode_ivp_packl2nx24_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28204c; +} + +static void +Opcode_ivp_packl2nx24_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980d8; +} + +static void +Opcode_ivp_packl2nx24_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b20a0; +} + +static void +Opcode_ivp_packl2nx24_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca0a8; +} + +static void +Opcode_ivp_packvr2nx24_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6000; +} + +static void +Opcode_ivp_packvr2nx24_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258000; +} + +static void +Opcode_ivp_packvr2nx24_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258000; +} + +static void +Opcode_ivp_packvr2nx24_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_ivp_packvr2nx24_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_ivp_packvr2nx24_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6000; +} + +static void +Opcode_ivp_packvru2nx24_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f6008; +} + +static void +Opcode_ivp_packvru2nx24_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e008; +} + +static void +Opcode_ivp_packvru2nx24_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e008; +} + +static void +Opcode_ivp_packvru2nx24_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6008; +} + +static void +Opcode_ivp_packvru2nx24_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6008; +} + +static void +Opcode_ivp_packvru2nx24_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4008; +} + +static void +Opcode_ivp_packlnx48_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1780d8; +} + +static void +Opcode_ivp_packlnx48_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c058; +} + +static void +Opcode_ivp_packlnx48_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28206c; +} + +static void +Opcode_ivp_packlnx48_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980dc; +} + +static void +Opcode_ivp_packlnx48_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b20a8; +} + +static void +Opcode_ivp_packlnx48_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc0a0; +} + +static void +Opcode_ivp_packl2nx24_1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1760d8; +} + +static void +Opcode_ivp_packl2nx24_1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a058; +} + +static void +Opcode_ivp_packl2nx24_1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28205c; +} + +static void +Opcode_ivp_packl2nx24_1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980f8; +} + +static void +Opcode_ivp_packl2nx24_1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b20a4; +} + +static void +Opcode_ivp_packl2nx24_1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca0ac; +} + +static void +Opcode_ivp_packvr2nx24_0_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6004; +} + +static void +Opcode_ivp_packvr2nx24_0_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258004; +} + +static void +Opcode_ivp_packvr2nx24_0_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258004; +} + +static void +Opcode_ivp_packvr2nx24_0_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0004; +} + +static void +Opcode_ivp_packvr2nx24_0_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0004; +} + +static void +Opcode_ivp_packvr2nx24_0_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6004; +} + +static void +Opcode_ivp_packvr2nx24_1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6008; +} + +static void +Opcode_ivp_packvr2nx24_1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a000; +} + +static void +Opcode_ivp_packvr2nx24_1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a000; +} + +static void +Opcode_ivp_packvr2nx24_1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0008; +} + +static void +Opcode_ivp_packvr2nx24_1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0008; +} + +static void +Opcode_ivp_packvr2nx24_1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6008; +} + +static void +Opcode_ivp_packvru2nx24_0_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f600c; +} + +static void +Opcode_ivp_packvru2nx24_0_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e00c; +} + +static void +Opcode_ivp_packvru2nx24_0_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e00c; +} + +static void +Opcode_ivp_packvru2nx24_0_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a600c; +} + +static void +Opcode_ivp_packvru2nx24_0_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a600c; +} + +static void +Opcode_ivp_packvru2nx24_0_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c400c; +} + +static void +Opcode_ivp_packvru2nx24_1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc000; +} + +static void +Opcode_ivp_packvru2nx24_1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282000; +} + +static void +Opcode_ivp_packvru2nx24_1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282000; +} + +static void +Opcode_ivp_packvru2nx24_1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8000; +} + +static void +Opcode_ivp_packvru2nx24_1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8000; +} + +static void +Opcode_ivp_packvru2nx24_1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6000; +} + +static void +Opcode_ivp_packvrnr2nx24_0_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6000; +} + +static void +Opcode_ivp_packvrnr2nx24_0_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c000; +} + +static void +Opcode_ivp_packvrnr2nx24_0_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c000; +} + +static void +Opcode_ivp_packvrnr2nx24_0_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2000; +} + +static void +Opcode_ivp_packvrnr2nx24_0_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2000; +} + +static void +Opcode_ivp_packvrnr2nx24_0_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ivp_packvrnr2nx24_1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6004; +} + +static void +Opcode_ivp_packvrnr2nx24_1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c004; +} + +static void +Opcode_ivp_packvrnr2nx24_1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c004; +} + +static void +Opcode_ivp_packvrnr2nx24_1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2004; +} + +static void +Opcode_ivp_packvrnr2nx24_1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2004; +} + +static void +Opcode_ivp_packvrnr2nx24_1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0004; +} + +static void +Opcode_ivp_packmnx48_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c0d8; +} + +static void +Opcode_ivp_packmnx48_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26005c; +} + +static void +Opcode_ivp_packmnx48_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28208c; +} + +static void +Opcode_ivp_packmnx48_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a0d0; +} + +static void +Opcode_ivp_packmnx48_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b40a0; +} + +static void +Opcode_ivp_packmnx48_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc0a8; +} + +static void +Opcode_ivp_packvrnx48_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6008; +} + +static void +Opcode_ivp_packvrnx48_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a008; +} + +static void +Opcode_ivp_packvrnx48_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a008; +} + +static void +Opcode_ivp_packvrnx48_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4008; +} + +static void +Opcode_ivp_packvrnx48_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4008; +} + +static void +Opcode_ivp_packvrnx48_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c2008; +} + +static void +Opcode_ivp_unpks2nx8_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf50080; +} + +static void +Opcode_ivp_unpks2nx8_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f68001; +} + +static void +Opcode_ivp_unpks2nx8_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf58080; +} + +static void +Opcode_ivp_unpks2nx8_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f68011; +} + +static void +Opcode_ivp_unpksnx16_l_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf580a0; +} + +static void +Opcode_ivp_unpksnx16_l_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e68012; +} + +static void +Opcode_ivp_unpksnx16_h_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf500a0; +} + +static void +Opcode_ivp_unpksnx16_h_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e68002; +} + +static void +Opcode_ivp_sel2nx8i_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sel2nx8i_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; +} + +static void +Opcode_ivp_sel2nx8i_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; +} + +static void +Opcode_ivp_sel2nx8i_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_ivp_sel2nx8i_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a005000; +} + +static void +Opcode_ivp_sel2nx8i_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_sel2nx8i_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; +} + +static void +Opcode_ivp_sel2nx8i_s0_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_sel2nx8i_s0_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_sel2nx8i_s2_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_sel2nx8i_s4_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_shfl2nx8i_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38402000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_shfl2nx8i_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800208; +} + +static void +Opcode_ivp_shfl2nx8i_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800108; +} + +static void +Opcode_ivp_shfl2nx8i_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9300000; +} + +static void +Opcode_ivp_shfl2nx8i_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c105000; +} + +static void +Opcode_ivp_shfl2nx8i_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac0000; +} + +static void +Opcode_ivp_shfl2nx8i_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000e0; +} + +static void +Opcode_ivp_shfl2nx8i_s0_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a30000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_shfl2nx8i_s0_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100e0; +} + +static void +Opcode_ivp_shfl2nx8i_s0_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280c0; +} + +static void +Opcode_ivp_shfl2nx8i_s0_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00c0; +} + +static void +Opcode_ivp_shfl2nx8i_s0_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8200c0; +} + +static void +Opcode_ivp_shfl2nx8i_s0_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa600c0; +} + +static void +Opcode_ivp_shfl2nx8i_s2_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40040; +} + +static void +Opcode_ivp_shfl2nx8i_s4_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8000; +} + +static void +Opcode_ivp_sel2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30400000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sel2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ivp_sel2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ivp_sel2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ivp_shfl2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30600000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_shfl2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800000; +} + +static void +Opcode_ivp_shfl2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000000; +} + +static void +Opcode_ivp_shfl2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000000; +} + +static void +Opcode_ivp_sel2nx8t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_sel2nx8t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_sel2nx8t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_sel2nx8t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_sqzn_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700a0; +} + +static void +Opcode_ivp_sqzn_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260020; +} + +static void +Opcode_ivp_sqzn_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_ivp_sqzn_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191000; +} + +static void +Opcode_ivp_sqzn_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_ivp_unsqzn_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1710a0; +} + +static void +Opcode_ivp_unsqzn_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261020; +} + +static void +Opcode_ivp_unsqzn_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191000; +} + +static void +Opcode_ivp_unsqzn_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192000; +} + +static void +Opcode_ivp_unsqzn_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1000; +} + +static void +Opcode_ivp_mulnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25800b; +} + +static void +Opcode_ivp_mulnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0007; +} + +static void +Opcode_ivp_mulnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c02; +} + +static void +Opcode_ivp_mulnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000b; +} + +static void +Opcode_ivp_mulnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000b; +} + +static void +Opcode_ivp_mulnx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648005; +} + +static void +Opcode_ivp_mulanx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258007; +} + +static void +Opcode_ivp_mulanx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0003; +} + +static void +Opcode_ivp_mulanx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c01; +} + +static void +Opcode_ivp_mulanx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160007; +} + +static void +Opcode_ivp_mulanx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110007; +} + +static void +Opcode_ivp_mulanx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648001; +} + +static void +Opcode_ivp_muluunx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264000; +} + +static void +Opcode_ivp_muluunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000c; +} + +static void +Opcode_ivp_muluunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0600a; +} + +static void +Opcode_ivp_muluunx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_ivp_muluunx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ivp_muluunx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65000a; +} + +static void +Opcode_ivp_muluuanx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26000c; +} + +static void +Opcode_ivp_muluuanx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80008; +} + +static void +Opcode_ivp_muluuanx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07009; +} + +static void +Opcode_ivp_muluuanx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000c; +} + +static void +Opcode_ivp_muluuanx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000c; +} + +static void +Opcode_ivp_muluuanx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650006; +} + +static void +Opcode_ivp_mulusnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260002; +} + +static void +Opcode_ivp_mulusnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000e; +} + +static void +Opcode_ivp_mulusnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06808; +} + +static void +Opcode_ivp_mulusnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180002; +} + +static void +Opcode_ivp_mulusnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130002; +} + +static void +Opcode_ivp_mulusnx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c00c; +} + +static void +Opcode_ivp_mulusanx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c00e; +} + +static void +Opcode_ivp_mulusanx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000a; +} + +static void +Opcode_ivp_mulusanx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07807; +} + +static void +Opcode_ivp_mulusanx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000e; +} + +static void +Opcode_ivp_mulusanx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000e; +} + +static void +Opcode_ivp_mulusanx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c008; +} + +static void +Opcode_ivp_mul2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258004; +} + +static void +Opcode_ivp_mul2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0000; +} + +static void +Opcode_ivp_mul2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07001; +} + +static void +Opcode_ivp_mul2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160004; +} + +static void +Opcode_ivp_mul2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110004; +} + +static void +Opcode_ivp_mul2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000e; +} + +static void +Opcode_ivp_mula2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258005; +} + +static void +Opcode_ivp_mula2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0001; +} + +static void +Opcode_ivp_mula2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07401; +} + +static void +Opcode_ivp_mula2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160005; +} + +static void +Opcode_ivp_mula2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110005; +} + +static void +Opcode_ivp_mula2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000f; +} + +static void +Opcode_ivp_addw2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250008; +} + +static void +Opcode_ivp_addw2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe90004; +} + +static void +Opcode_ivp_addw2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c00; +} + +static void +Opcode_ivp_addw2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140008; +} + +static void +Opcode_ivp_addw2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0008; +} + +static void +Opcode_ivp_addw2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640008; +} + +static void +Opcode_ivp_addwa2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250009; +} + +static void +Opcode_ivp_addwa2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe90005; +} + +static void +Opcode_ivp_addwa2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c01; +} + +static void +Opcode_ivp_addwa2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140009; +} + +static void +Opcode_ivp_addwa2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0009; +} + +static void +Opcode_ivp_addwa2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640009; +} + +static void +Opcode_ivp_addws2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000c; +} + +static void +Opcode_ivp_addws2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe90008; +} + +static void +Opcode_ivp_addws2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c04; +} + +static void +Opcode_ivp_addws2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000c; +} + +static void +Opcode_ivp_addws2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000c; +} + +static void +Opcode_ivp_addws2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000a; +} + +static void +Opcode_ivp_addwu2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000e; +} + +static void +Opcode_ivp_addwu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000a; +} + +static void +Opcode_ivp_addwu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c06; +} + +static void +Opcode_ivp_addwu2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000e; +} + +static void +Opcode_ivp_addwu2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000e; +} + +static void +Opcode_ivp_addwu2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000b; +} + +static void +Opcode_ivp_addwua2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000f; +} + +static void +Opcode_ivp_addwua2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000b; +} + +static void +Opcode_ivp_addwua2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c07; +} + +static void +Opcode_ivp_addwua2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000f; +} + +static void +Opcode_ivp_addwua2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000f; +} + +static void +Opcode_ivp_addwua2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000c; +} + +static void +Opcode_ivp_addwus2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258002; +} + +static void +Opcode_ivp_addwus2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000e; +} + +static void +Opcode_ivp_addwus2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07800; +} + +static void +Opcode_ivp_addwus2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160002; +} + +static void +Opcode_ivp_addwus2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110002; +} + +static void +Opcode_ivp_addwus2nx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000d; +} + +static void +Opcode_ivp_divn_2x32x16s_4step0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ivp_divn_2x32x16s_4step_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e40000; +} + +static void +Opcode_ivp_divn_2x32x16s_4stepn_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e48000; +} + +static void +Opcode_ivp_divn_2x32x16u_4step0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ivp_divn_2x32x16u_4step_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e50000; +} + +static void +Opcode_ivp_divn_2x32x16u_4stepn_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e58000; +} + +static void +Opcode_ivp_divnx16s_4step0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ivp_divnx16s_4step_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e20000; +} + +static void +Opcode_ivp_divnx16s_4stepn_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e28000; +} + +static void +Opcode_ivp_divnx16u_4step0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ivp_divnx16u_4step_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e30000; +} + +static void +Opcode_ivp_divnx16u_4stepn_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e38000; +} + +static void +Opcode_ivp_divnx16sq_4step0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_divnx16q_4step0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_mulsnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25800f; +} + +static void +Opcode_ivp_mulsnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000b; +} + +static void +Opcode_ivp_mulsnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c03; +} + +static void +Opcode_ivp_mulsnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000f; +} + +static void +Opcode_ivp_mulsnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000f; +} + +static void +Opcode_ivp_mulsnx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648009; +} + +static void +Opcode_ivp_muluusnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264004; +} + +static void +Opcode_ivp_muluusnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90000; +} + +static void +Opcode_ivp_muluusnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0700a; +} + +static void +Opcode_ivp_muluusnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190004; +} + +static void +Opcode_ivp_muluusnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140004; +} + +static void +Opcode_ivp_muluusnx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65000e; +} + +static void +Opcode_ivp_mulussnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260006; +} + +static void +Opcode_ivp_mulussnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80002; +} + +static void +Opcode_ivp_mulussnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07808; +} + +static void +Opcode_ivp_mulussnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180006; +} + +static void +Opcode_ivp_mulussnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130006; +} + +static void +Opcode_ivp_mulussnx16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650000; +} + +static void +Opcode_ivp_muln_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25800c; +} + +static void +Opcode_ivp_muln_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0008; +} + +static void +Opcode_ivp_muln_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07003; +} + +static void +Opcode_ivp_muln_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000c; +} + +static void +Opcode_ivp_muln_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000c; +} + +static void +Opcode_ivp_muln_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648006; +} + +static void +Opcode_ivp_muluun_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264001; +} + +static void +Opcode_ivp_muluun_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000d; +} + +static void +Opcode_ivp_muluun_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0640a; +} + +static void +Opcode_ivp_muluun_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190001; +} + +static void +Opcode_ivp_muluun_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140001; +} + +static void +Opcode_ivp_muluun_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65000b; +} + +static void +Opcode_ivp_mulusn_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260003; +} + +static void +Opcode_ivp_mulusn_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000f; +} + +static void +Opcode_ivp_mulusn_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c08; +} + +static void +Opcode_ivp_mulusn_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180003; +} + +static void +Opcode_ivp_mulusn_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130003; +} + +static void +Opcode_ivp_mulusn_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c00d; +} + +static void +Opcode_ivp_mulsun_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c006; +} + +static void +Opcode_ivp_mulsun_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0002; +} + +static void +Opcode_ivp_mulsun_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07805; +} + +static void +Opcode_ivp_mulsun_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170006; +} + +static void +Opcode_ivp_mulsun_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120006; +} + +static void +Opcode_ivp_mulsun_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c000; +} + +static void +Opcode_ivp_muln_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25800d; +} + +static void +Opcode_ivp_muln_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0009; +} + +static void +Opcode_ivp_muln_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07403; +} + +static void +Opcode_ivp_muln_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000d; +} + +static void +Opcode_ivp_muln_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000d; +} + +static void +Opcode_ivp_muln_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648007; +} + +static void +Opcode_ivp_muluun_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264002; +} + +static void +Opcode_ivp_muluun_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000e; +} + +static void +Opcode_ivp_muluun_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0680a; +} + +static void +Opcode_ivp_muluun_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190002; +} + +static void +Opcode_ivp_muluun_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140002; +} + +static void +Opcode_ivp_muluun_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65000c; +} + +static void +Opcode_ivp_mulusn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260004; +} + +static void +Opcode_ivp_mulusn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ivp_mulusn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07008; +} + +static void +Opcode_ivp_mulusn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180004; +} + +static void +Opcode_ivp_mulusn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130004; +} + +static void +Opcode_ivp_mulusn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c00e; +} + +static void +Opcode_ivp_mulsun_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c007; +} + +static void +Opcode_ivp_mulsun_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0003; +} + +static void +Opcode_ivp_mulsun_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c05; +} + +static void +Opcode_ivp_mulsun_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170007; +} + +static void +Opcode_ivp_mulsun_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120007; +} + +static void +Opcode_ivp_mulsun_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c001; +} + +static void +Opcode_ivp_mulhn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25800a; +} + +static void +Opcode_ivp_mulhn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0006; +} + +static void +Opcode_ivp_mulhn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07802; +} + +static void +Opcode_ivp_mulhn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000a; +} + +static void +Opcode_ivp_mulhn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000a; +} + +static void +Opcode_ivp_mulhn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648004; +} + +static void +Opcode_ivp_muluuhn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26000f; +} + +static void +Opcode_ivp_muluuhn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000b; +} + +static void +Opcode_ivp_muluuhn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c09; +} + +static void +Opcode_ivp_muluuhn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000f; +} + +static void +Opcode_ivp_muluuhn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000f; +} + +static void +Opcode_ivp_muluuhn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650009; +} + +static void +Opcode_ivp_mulushn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260001; +} + +static void +Opcode_ivp_mulushn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000d; +} + +static void +Opcode_ivp_mulushn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06408; +} + +static void +Opcode_ivp_mulushn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180001; +} + +static void +Opcode_ivp_mulushn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130001; +} + +static void +Opcode_ivp_mulushn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c00b; +} + +static void +Opcode_ivp_mulsuhn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c005; +} + +static void +Opcode_ivp_mulsuhn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0001; +} + +static void +Opcode_ivp_mulsuhn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07405; +} + +static void +Opcode_ivp_mulsuhn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170005; +} + +static void +Opcode_ivp_mulsuhn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120005; +} + +static void +Opcode_ivp_mulsuhn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64800f; +} + +static void +Opcode_ivp_mulan_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258008; +} + +static void +Opcode_ivp_mulan_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0004; +} + +static void +Opcode_ivp_mulan_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07002; +} + +static void +Opcode_ivp_mulan_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160008; +} + +static void +Opcode_ivp_mulan_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110008; +} + +static void +Opcode_ivp_mulan_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648002; +} + +static void +Opcode_ivp_muluuan_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26000d; +} + +static void +Opcode_ivp_muluuan_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80009; +} + +static void +Opcode_ivp_muluuan_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07409; +} + +static void +Opcode_ivp_muluuan_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000d; +} + +static void +Opcode_ivp_muluuan_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000d; +} + +static void +Opcode_ivp_muluuan_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650007; +} + +static void +Opcode_ivp_mulusan_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c00f; +} + +static void +Opcode_ivp_mulusan_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000b; +} + +static void +Opcode_ivp_mulusan_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c07; +} + +static void +Opcode_ivp_mulusan_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000f; +} + +static void +Opcode_ivp_mulusan_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000f; +} + +static void +Opcode_ivp_mulusan_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c009; +} + +static void +Opcode_ivp_mulsuan_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c003; +} + +static void +Opcode_ivp_mulsuan_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000f; +} + +static void +Opcode_ivp_mulsuan_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c04; +} + +static void +Opcode_ivp_mulsuan_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170003; +} + +static void +Opcode_ivp_mulsuan_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120003; +} + +static void +Opcode_ivp_mulsuan_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64800d; +} + +static void +Opcode_ivp_mulahn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258006; +} + +static void +Opcode_ivp_mulahn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0002; +} + +static void +Opcode_ivp_mulahn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07801; +} + +static void +Opcode_ivp_mulahn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160006; +} + +static void +Opcode_ivp_mulahn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110006; +} + +static void +Opcode_ivp_mulahn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648000; +} + +static void +Opcode_ivp_muluuahn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26000b; +} + +static void +Opcode_ivp_muluuahn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80007; +} + +static void +Opcode_ivp_muluuahn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c09; +} + +static void +Opcode_ivp_muluuahn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000b; +} + +static void +Opcode_ivp_muluuahn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000b; +} + +static void +Opcode_ivp_muluuahn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650005; +} + +static void +Opcode_ivp_mulusahn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c00d; +} + +static void +Opcode_ivp_mulusahn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0009; +} + +static void +Opcode_ivp_mulusahn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07407; +} + +static void +Opcode_ivp_mulusahn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000d; +} + +static void +Opcode_ivp_mulusahn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000d; +} + +static void +Opcode_ivp_mulusahn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c007; +} + +static void +Opcode_ivp_mulsuahn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c002; +} + +static void +Opcode_ivp_mulsuahn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000e; +} + +static void +Opcode_ivp_mulsuahn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07804; +} + +static void +Opcode_ivp_mulsuahn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170002; +} + +static void +Opcode_ivp_mulsuahn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120002; +} + +static void +Opcode_ivp_mulsuahn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64800c; +} + +static void +Opcode_ivp_mulan_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258009; +} + +static void +Opcode_ivp_mulan_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0005; +} + +static void +Opcode_ivp_mulan_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07402; +} + +static void +Opcode_ivp_mulan_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160009; +} + +static void +Opcode_ivp_mulan_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110009; +} + +static void +Opcode_ivp_mulan_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648003; +} + +static void +Opcode_ivp_muluuan_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26000e; +} + +static void +Opcode_ivp_muluuan_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000a; +} + +static void +Opcode_ivp_muluuan_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07809; +} + +static void +Opcode_ivp_muluuan_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000e; +} + +static void +Opcode_ivp_muluuan_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000e; +} + +static void +Opcode_ivp_muluuan_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650008; +} + +static void +Opcode_ivp_mulusan_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260000; +} + +static void +Opcode_ivp_mulusan_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000c; +} + +static void +Opcode_ivp_mulusan_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06008; +} + +static void +Opcode_ivp_mulusan_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ivp_mulusan_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ivp_mulusan_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c00a; +} + +static void +Opcode_ivp_mulsuan_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c004; +} + +static void +Opcode_ivp_mulsuan_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0000; +} + +static void +Opcode_ivp_mulsuan_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07005; +} + +static void +Opcode_ivp_mulsuan_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170004; +} + +static void +Opcode_ivp_mulsuan_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120004; +} + +static void +Opcode_ivp_mulsuan_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64800e; +} + +static void +Opcode_ivp_mulshn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25800e; +} + +static void +Opcode_ivp_mulshn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000a; +} + +static void +Opcode_ivp_mulshn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07803; +} + +static void +Opcode_ivp_mulshn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000e; +} + +static void +Opcode_ivp_mulshn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000e; +} + +static void +Opcode_ivp_mulshn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x648008; +} + +static void +Opcode_ivp_muluushn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264003; +} + +static void +Opcode_ivp_muluushn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000f; +} + +static void +Opcode_ivp_muluushn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c0a; +} + +static void +Opcode_ivp_muluushn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190003; +} + +static void +Opcode_ivp_muluushn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140003; +} + +static void +Opcode_ivp_muluushn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65000d; +} + +static void +Opcode_ivp_mulusshn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260005; +} + +static void +Opcode_ivp_mulusshn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80001; +} + +static void +Opcode_ivp_mulusshn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07408; +} + +static void +Opcode_ivp_mulusshn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180005; +} + +static void +Opcode_ivp_mulusshn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130005; +} + +static void +Opcode_ivp_mulusshn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c00f; +} + +static void +Opcode_ivp_mulsushn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c008; +} + +static void +Opcode_ivp_mulsushn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0004; +} + +static void +Opcode_ivp_mulsushn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07006; +} + +static void +Opcode_ivp_mulsushn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170008; +} + +static void +Opcode_ivp_mulsushn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120008; +} + +static void +Opcode_ivp_mulsushn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c002; +} + +static void +Opcode_ivp_mulsn_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c000; +} + +static void +Opcode_ivp_mulsn_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000c; +} + +static void +Opcode_ivp_mulsn_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07004; +} + +static void +Opcode_ivp_mulsn_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ivp_mulsn_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ivp_mulsn_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64800a; +} + +static void +Opcode_ivp_muluusn_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264005; +} + +static void +Opcode_ivp_muluusn_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90001; +} + +static void +Opcode_ivp_muluusn_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0740a; +} + +static void +Opcode_ivp_muluusn_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190005; +} + +static void +Opcode_ivp_muluusn_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140005; +} + +static void +Opcode_ivp_muluusn_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65000f; +} + +static void +Opcode_ivp_mulussn_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260007; +} + +static void +Opcode_ivp_mulussn_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80003; +} + +static void +Opcode_ivp_mulussn_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c08; +} + +static void +Opcode_ivp_mulussn_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180007; +} + +static void +Opcode_ivp_mulussn_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130007; +} + +static void +Opcode_ivp_mulussn_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650001; +} + +static void +Opcode_ivp_mulsusn_2x16x32_0_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c009; +} + +static void +Opcode_ivp_mulsusn_2x16x32_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0005; +} + +static void +Opcode_ivp_mulsusn_2x16x32_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07406; +} + +static void +Opcode_ivp_mulsusn_2x16x32_0_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170009; +} + +static void +Opcode_ivp_mulsusn_2x16x32_0_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120009; +} + +static void +Opcode_ivp_mulsusn_2x16x32_0_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c003; +} + +static void +Opcode_ivp_mulsn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c001; +} + +static void +Opcode_ivp_mulsn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000d; +} + +static void +Opcode_ivp_mulsn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07404; +} + +static void +Opcode_ivp_mulsn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170001; +} + +static void +Opcode_ivp_mulsn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120001; +} + +static void +Opcode_ivp_mulsn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64800b; +} + +static void +Opcode_ivp_muluusn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264006; +} + +static void +Opcode_ivp_muluusn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90002; +} + +static void +Opcode_ivp_muluusn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0780a; +} + +static void +Opcode_ivp_muluusn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190006; +} + +static void +Opcode_ivp_muluusn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140006; +} + +static void +Opcode_ivp_muluusn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x654000; +} + +static void +Opcode_ivp_mulussn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260008; +} + +static void +Opcode_ivp_mulussn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80004; +} + +static void +Opcode_ivp_mulussn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06009; +} + +static void +Opcode_ivp_mulussn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180008; +} + +static void +Opcode_ivp_mulussn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130008; +} + +static void +Opcode_ivp_mulussn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650002; +} + +static void +Opcode_ivp_mulsusn_2x16x32_1_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c00a; +} + +static void +Opcode_ivp_mulsusn_2x16x32_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0006; +} + +static void +Opcode_ivp_mulsusn_2x16x32_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07806; +} + +static void +Opcode_ivp_mulsusn_2x16x32_1_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000a; +} + +static void +Opcode_ivp_mulsusn_2x16x32_1_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000a; +} + +static void +Opcode_ivp_mulsusn_2x16x32_1_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64c004; +} + +static void +Opcode_ivp_packln_2x96_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a0d8; +} + +static void +Opcode_ivp_packln_2x96_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e058; +} + +static void +Opcode_ivp_packln_2x96_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28207c; +} + +static void +Opcode_ivp_packln_2x96_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980fc; +} + +static void +Opcode_ivp_packln_2x96_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b20ac; +} + +static void +Opcode_ivp_packln_2x96_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc0a4; +} + +static void +Opcode_ivp_packhn_2x64w_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1720d8; +} + +static void +Opcode_ivp_packhn_2x64w_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x266058; +} + +static void +Opcode_ivp_packhn_2x64w_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28203c; +} + +static void +Opcode_ivp_packhn_2x64w_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980f4; +} + +static void +Opcode_ivp_packhn_2x64w_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00ac; +} + +static void +Opcode_ivp_packhn_2x64w_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca0a4; +} + +static void +Opcode_ivp_packvrn_2x64w_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f6004; +} + +static void +Opcode_ivp_packvrn_2x64w_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c00c; +} + +static void +Opcode_ivp_packvrn_2x64w_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c00c; +} + +static void +Opcode_ivp_packvrn_2x64w_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6004; +} + +static void +Opcode_ivp_packvrn_2x64w_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6004; +} + +static void +Opcode_ivp_packvrn_2x64w_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4004; +} + +static void +Opcode_ivp_packvrnrn_2x64w_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6004; +} + +static void +Opcode_ivp_packvrnrn_2x64w_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25800c; +} + +static void +Opcode_ivp_packvrnrn_2x64w_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25800c; +} + +static void +Opcode_ivp_packvrnrn_2x64w_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4004; +} + +static void +Opcode_ivp_packvrnrn_2x64w_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4004; +} + +static void +Opcode_ivp_packvrnrn_2x64w_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c2004; +} + +static void +Opcode_ivp_packvrnx48_0_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e600c; +} + +static void +Opcode_ivp_packvrnx48_0_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a00c; +} + +static void +Opcode_ivp_packvrnx48_0_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a00c; +} + +static void +Opcode_ivp_packvrnx48_0_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a400c; +} + +static void +Opcode_ivp_packvrnx48_0_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a400c; +} + +static void +Opcode_ivp_packvrnx48_0_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c200c; +} + +static void +Opcode_ivp_packvrnx48_1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f6000; +} + +static void +Opcode_ivp_packvrnx48_1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c008; +} + +static void +Opcode_ivp_packvrnx48_1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c008; +} + +static void +Opcode_ivp_packvrnx48_1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6000; +} + +static void +Opcode_ivp_packvrnx48_1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6000; +} + +static void +Opcode_ivp_packvrnx48_1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4000; +} + +static void +Opcode_ivp_packvrnrnx48_0_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d600c; +} + +static void +Opcode_ivp_packvrnrnx48_0_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e004; +} + +static void +Opcode_ivp_packvrnrnx48_0_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e004; +} + +static void +Opcode_ivp_packvrnrnx48_0_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a200c; +} + +static void +Opcode_ivp_packvrnrnx48_0_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a200c; +} + +static void +Opcode_ivp_packvrnrnx48_0_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000c; +} + +static void +Opcode_ivp_packvrnrnx48_1_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6000; +} + +static void +Opcode_ivp_packvrnrnx48_1_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258008; +} + +static void +Opcode_ivp_packvrnrnx48_1_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258008; +} + +static void +Opcode_ivp_packvrnrnx48_1_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4000; +} + +static void +Opcode_ivp_packvrnrnx48_1_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4000; +} + +static void +Opcode_ivp_packvrnrnx48_1_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c2000; +} + +static void +Opcode_ivp_packvrnrnx48_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6008; +} + +static void +Opcode_ivp_packvrnrnx48_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e000; +} + +static void +Opcode_ivp_packvrnrnx48_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e000; +} + +static void +Opcode_ivp_packvrnrnx48_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2008; +} + +static void +Opcode_ivp_packvrnrnx48_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2008; +} + +static void +Opcode_ivp_packvrnrnx48_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0008; +} + +static void +Opcode_ivp_packvrnr2nx24_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c600c; +} + +static void +Opcode_ivp_packvrnr2nx24_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a004; +} + +static void +Opcode_ivp_packvrnr2nx24_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a004; +} + +static void +Opcode_ivp_packvrnr2nx24_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000c; +} + +static void +Opcode_ivp_packvrnr2nx24_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000c; +} + +static void +Opcode_ivp_packvrnr2nx24_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b600c; +} + +static void +Opcode_ivp_l2a4nx8_ip_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000; +} + +static void +Opcode_ivp_l2au2nx8_ip_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ivp_l2u2nx8_xp_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ivp_avgu2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_avgu2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b0000; +} + +static void +Opcode_ivp_avgu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb0000; +} + +static void +Opcode_ivp_avgu2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900308; +} + +static void +Opcode_ivp_avgu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900008; +} + +static void +Opcode_ivp_avgu2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0010c; +} + +static void +Opcode_ivp_avgu2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9380004; +} + +static void +Opcode_ivp_avgu2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e007c00; +} + +static void +Opcode_ivp_avgu2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb90000; +} + +static void +Opcode_ivp_avgu2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c002a0; +} + +static void +Opcode_ivp_avgru2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_avgru2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a0000; +} + +static void +Opcode_ivp_avgru2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca0000; +} + +static void +Opcode_ivp_avgru2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900304; +} + +static void +Opcode_ivp_avgru2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00007; +} + +static void +Opcode_ivp_avgru2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0010c; +} + +static void +Opcode_ivp_avgru2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9380002; +} + +static void +Opcode_ivp_avgru2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e007800; +} + +static void +Opcode_ivp_avgru2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb80000; +} + +static void +Opcode_ivp_avgru2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a002a0; +} + +static void +Opcode_ivp_radd2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f800c71; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_radd2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3700074; +} + +static void +Opcode_ivp_radd2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f00374; +} + +static void +Opcode_ivp_radd2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f82600; +} + +static void +Opcode_ivp_radd2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607840; +} + +static void +Opcode_ivp_radd2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd800f0; +} + +static void +Opcode_ivp_radd2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b001b7; +} + +static void +Opcode_ivp_radd2nx8t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800c80; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_radd2nx8t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000041; +} + +static void +Opcode_ivp_radd2nx8t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800341; +} + +static void +Opcode_ivp_radd2nx8t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01000; +} + +static void +Opcode_ivp_radd2nx8t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e304020; +} + +static void +Opcode_ivp_radd2nx8t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ivp_radd2nx8t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001f3; +} + +static void +Opcode_ivp_raddunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502420; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3100045; +} + +static void +Opcode_ivp_raddunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900345; +} + +static void +Opcode_ivp_raddunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c82800; +} + +static void +Opcode_ivp_raddunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607c50; +} + +static void +Opcode_ivp_raddunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda80f0; +} + +static void +Opcode_ivp_raddunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e001b6; +} + +static void +Opcode_ivp_raddunx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800cd0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddunx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000052; +} + +static void +Opcode_ivp_raddunx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800352; +} + +static void +Opcode_ivp_raddunx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01a00; +} + +static void +Opcode_ivp_raddunx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607020; +} + +static void +Opcode_ivp_raddunx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80050; +} + +static void +Opcode_ivp_raddunx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800194; +} + +static void +Opcode_ivp_raddu2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502031; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddu2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000075; +} + +static void +Opcode_ivp_raddu2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800375; +} + +static void +Opcode_ivp_raddu2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c02e00; +} + +static void +Opcode_ivp_raddu2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607c40; +} + +static void +Opcode_ivp_raddu2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda00f0; +} + +static void +Opcode_ivp_raddu2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d001b7; +} + +static void +Opcode_ivp_raddu2nx8t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800cc0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddu2nx8t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000042; +} + +static void +Opcode_ivp_raddu2nx8t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800342; +} + +static void +Opcode_ivp_raddu2nx8t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01800; +} + +static void +Opcode_ivp_raddu2nx8t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607000; +} + +static void +Opcode_ivp_raddu2nx8t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80040; +} + +static void +Opcode_ivp_raddu2nx8t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800187; +} + +static void +Opcode_ivp_ltrs2n_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1703e0; +} + +static void +Opcode_ivp_ltrs2n_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260960; +} + +static void +Opcode_ivp_ltrs2n_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260920; +} + +static void +Opcode_ivp_ltrs2n_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2500; +} + +static void +Opcode_ivp_ltrs2n_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae900; +} + +static void +Opcode_ivp_ltrs2n_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0210; +} + +static void +Opcode_ivp_ltrs2n_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be500; +} + +static void +Opcode_ivp_ltrsn_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1704e0; +} + +static void +Opcode_ivp_ltrsn_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260a60; +} + +static void +Opcode_ivp_ltrsn_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260a20; +} + +static void +Opcode_ivp_ltrsn_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2600; +} + +static void +Opcode_ivp_ltrsn_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aea00; +} + +static void +Opcode_ivp_ltrsn_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0310; +} + +static void +Opcode_ivp_ltrsn_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc510; +} + +static void +Opcode_ivp_ltrsn_2_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1705e0; +} + +static void +Opcode_ivp_ltrsn_2_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260b60; +} + +static void +Opcode_ivp_ltrsn_2_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260b20; +} + +static void +Opcode_ivp_ltrsn_2_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2700; +} + +static void +Opcode_ivp_ltrsn_2_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aeb00; +} + +static void +Opcode_ivp_ltrsn_2_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0310; +} + +static void +Opcode_ivp_ltrsn_2_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be510; +} + +static void +Opcode_ivp_seq2nx8_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1760dd; +} + +static void +Opcode_ivp_seq2nx8_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a05d; +} + +static void +Opcode_ivp_seq2nx8_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2820dd; +} + +static void +Opcode_ivp_seq2nx8_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a0f9; +} + +static void +Opcode_ivp_seq2nx8_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b60a4; +} + +static void +Opcode_ivp_seq2nx8_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce0ac; +} + +static void +Opcode_ivp_seqn_2x32_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1760df; +} + +static void +Opcode_ivp_seqn_2x32_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a05f; +} + +static void +Opcode_ivp_seqn_2x32_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2820df; +} + +static void +Opcode_ivp_seqn_2x32_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a0fb; +} + +static void +Opcode_ivp_seqn_2x32_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b60a6; +} + +static void +Opcode_ivp_seqn_2x32_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce0ae; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10980200; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a440000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1444000; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28f030c; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x594000; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28f020c; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa80200; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9808008; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00e000; +} + +static void +Opcode_ivp_extrn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf8001; +} + +static void +Opcode_ivp_extrn_2x32_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3880000; +} + +static void +Opcode_ivp_unpku2nx8_0_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf500c0; +} + +static void +Opcode_ivp_unpku2nx8_0_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f68002; +} + +static void +Opcode_ivp_unpku2nx8_1_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf580c0; +} + +static void +Opcode_ivp_unpku2nx8_1_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f68012; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800000; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00008; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800300; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8600000; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c202000; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ivp_baddnormnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_baddnormnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800300; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d00c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280010a; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000010; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000a; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9280000; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c403000; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840000; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ivp_bsubnormnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800020; +} + +static void +Opcode_ivp_raddsnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36502021; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddsnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000065; +} + +static void +Opcode_ivp_raddsnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800365; +} + +static void +Opcode_ivp_raddsnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c02c00; +} + +static void +Opcode_ivp_raddsnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e607870; +} + +static void +Opcode_ivp_raddsnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd980f0; +} + +static void +Opcode_ivp_raddsnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d001b6; +} + +static void +Opcode_ivp_raddsnx16t_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21800cb0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_raddsnx16t_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000071; +} + +static void +Opcode_ivp_raddsnx16t_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800371; +} + +static void +Opcode_ivp_raddsnx16t_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01600; +} + +static void +Opcode_ivp_raddsnx16t_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e305820; +} + +static void +Opcode_ivp_raddsnx16t_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80030; +} + +static void +Opcode_ivp_raddsnx16t_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800186; +} + +static void +Opcode_ivp_ornotb_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700c8; +} + +static void +Opcode_ivp_ornotb_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260050; +} + +static void +Opcode_ivp_ornotb_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260010; +} + +static void +Opcode_ivp_ornotb_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8018; +} + +static void +Opcode_ivp_ornotb_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab810; +} + +static void +Opcode_ivp_ornotb_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6018; +} + +static void +Opcode_ivp_extr2nx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10900000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extr2nx8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extr2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ivp_extr2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a0300; +} + +static void +Opcode_ivp_extr2nx8_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x538000; +} + +static void +Opcode_ivp_extr2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28a0200; +} + +static void +Opcode_ivp_extr2nx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ivp_extr2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9804000; +} + +static void +Opcode_ivp_extr2nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c404000; +} + +static void +Opcode_ivp_extr2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf0000; +} + +static void +Opcode_ivp_extr2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800000; +} + +static void +Opcode_ivp_extrvrn_2x32_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a448000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_extrvrn_2x32_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3030200; +} + +static void +Opcode_ivp_extrvrn_2x32_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1950200; +} + +static void +Opcode_ivp_extrvrn_2x32_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9802000; +} + +static void +Opcode_ivp_extrvrn_2x32_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c10e000; +} + +static void +Opcode_ivp_extrvrn_2x32_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104000; +} + +static void +Opcode_ivp_extrvrn_2x32_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd28000; +} + +static void +Opcode_ivp_extrvrn_2x32_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x644000; +} + +static void +Opcode_ivp_movav8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d7c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movav8_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a450005; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movav8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1459a00; +} + +static void +Opcode_ivp_movav8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3038205; +} + +static void +Opcode_ivp_movav8_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54600e; +} + +static void +Opcode_ivp_movav8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2af820d; +} + +static void +Opcode_ivp_movav8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9dda00; +} + +static void +Opcode_ivp_movav8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980e00a; +} + +static void +Opcode_ivp_movav8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c20e001; +} + +static void +Opcode_ivp_movav8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcfc005; +} + +static void +Opcode_ivp_movav8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a88010; +} + +static void +Opcode_ivp_mulpn16xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x214000; +} + +static void +Opcode_ivp_mulpn16xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb90000; +} + +static void +Opcode_ivp_mulpn16xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01400; +} + +static void +Opcode_ivp_mulpn16xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_ivp_mulpn16xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_ivp_mulpn16xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614000; +} + +static void +Opcode_ivp_mulpan16xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_ivp_mulpan16xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb80000; +} + +static void +Opcode_ivp_mulpan16xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01000; +} + +static void +Opcode_ivp_mulpan16xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_mulpan16xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ivp_mulpan16xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_ivp_muluspn16xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22c000; +} + +static void +Opcode_ivp_muluspn16xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf0000; +} + +static void +Opcode_ivp_muluspn16xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c02c00; +} + +static void +Opcode_ivp_muluspn16xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_ivp_muluspn16xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_ivp_muluspn16xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62c000; +} + +static void +Opcode_ivp_muluspan16xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x228000; +} + +static void +Opcode_ivp_muluspan16xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe0000; +} + +static void +Opcode_ivp_muluspan16xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c02800; +} + +static void +Opcode_ivp_muluspan16xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ivp_muluspan16xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ivp_muluspan16xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x628000; +} + +static void +Opcode_ivp_mulp2n8xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x208000; +} + +static void +Opcode_ivp_mulp2n8xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb60000; +} + +static void +Opcode_ivp_mulp2n8xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00800; +} + +static void +Opcode_ivp_mulp2n8xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ivp_mulp2n8xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ivp_mulp2n8xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x608000; +} + +static void +Opcode_ivp_mulpa2n8xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c000; +} + +static void +Opcode_ivp_mulpa2n8xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb70000; +} + +static void +Opcode_ivp_mulpa2n8xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00c00; +} + +static void +Opcode_ivp_mulpa2n8xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_ivp_mulpa2n8xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_ivp_mulpa2n8xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60c000; +} + +static void +Opcode_ivp_mulusp2n8xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_ivp_mulusp2n8xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc0000; +} + +static void +Opcode_ivp_mulusp2n8xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c02000; +} + +static void +Opcode_ivp_mulusp2n8xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_mulusp2n8xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ivp_mulusp2n8xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620000; +} + +static void +Opcode_ivp_muluspa2n8xr16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x224000; +} + +static void +Opcode_ivp_muluspa2n8xr16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd0000; +} + +static void +Opcode_ivp_muluspa2n8xr16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c02400; +} + +static void +Opcode_ivp_muluspa2n8xr16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_ivp_muluspa2n8xr16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_ivp_muluspa2n8xr16_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x624000; +} + +static void +Opcode_ivp_mulpnx16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000003; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulpanx16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000002; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_muluspnx16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000007; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_muluspanx16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000006; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_muluupnx16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000b; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_muluupanx16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000a; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulp2nx8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulpa2nx8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000001; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulusp2nx8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000004; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_muluspa2nx8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000005; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_muluup2nx8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000008; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_muluupa2nx8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000009; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulpi2nr8x16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulpai2nr8x16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_muluspi2nr8x16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_muluspai2nr8x16_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulq2n8xr8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulqa2n8xr8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulusq2n8xr8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mulusqa2n8xr8_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_mul4t2n8xr8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_mul4t2n8xr8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb40000; +} + +static void +Opcode_ivp_mul4t2n8xr8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00000; +} + +static void +Opcode_ivp_mul4t2n8xr8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_mul4t2n8xr8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_mul4t2n8xr8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ivp_mul4ta2n8xr8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x204000; +} + +static void +Opcode_ivp_mul4ta2n8xr8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb50000; +} + +static void +Opcode_ivp_mul4ta2n8xr8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00400; +} + +static void +Opcode_ivp_mul4ta2n8xr8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ivp_mul4ta2n8xr8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ivp_mul4ta2n8xr8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x604000; +} + +static void +Opcode_ivp_mulus4t2n8xr8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x218000; +} + +static void +Opcode_ivp_mulus4t2n8xr8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba0000; +} + +static void +Opcode_ivp_mulus4t2n8xr8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01800; +} + +static void +Opcode_ivp_mulus4t2n8xr8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ivp_mulus4t2n8xr8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ivp_mulus4t2n8xr8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_ivp_mulus4ta2n8xr8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21c000; +} + +static void +Opcode_ivp_mulus4ta2n8xr8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb0000; +} + +static void +Opcode_ivp_mulus4ta2n8xr8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01c00; +} + +static void +Opcode_ivp_mulus4ta2n8xr8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_ivp_mulus4ta2n8xr8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_ivp_mulus4ta2n8xr8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_ivp_addwnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000b; +} + +static void +Opcode_ivp_addwnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe90007; +} + +static void +Opcode_ivp_addwnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c03; +} + +static void +Opcode_ivp_addwnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000b; +} + +static void +Opcode_ivp_addwnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000b; +} + +static void +Opcode_ivp_addwanx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000a; +} + +static void +Opcode_ivp_addwanx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe90006; +} + +static void +Opcode_ivp_addwanx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c02; +} + +static void +Opcode_ivp_addwanx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000a; +} + +static void +Opcode_ivp_addwanx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000a; +} + +static void +Opcode_ivp_addwsnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000d; +} + +static void +Opcode_ivp_addwsnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe90009; +} + +static void +Opcode_ivp_addwsnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c05; +} + +static void +Opcode_ivp_addwsnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000d; +} + +static void +Opcode_ivp_addwsnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000d; +} + +static void +Opcode_ivp_addwunx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258001; +} + +static void +Opcode_ivp_addwunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000d; +} + +static void +Opcode_ivp_addwunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07400; +} + +static void +Opcode_ivp_addwunx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160001; +} + +static void +Opcode_ivp_addwunx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110001; +} + +static void +Opcode_ivp_addwuanx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258000; +} + +static void +Opcode_ivp_addwuanx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000c; +} + +static void +Opcode_ivp_addwuanx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07000; +} + +static void +Opcode_ivp_addwuanx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ivp_addwuanx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ivp_addwusnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258003; +} + +static void +Opcode_ivp_addwusnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000f; +} + +static void +Opcode_ivp_addwusnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c00; +} + +static void +Opcode_ivp_addwusnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160003; +} + +static void +Opcode_ivp_addwusnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110003; +} + +static void +Opcode_ivp_subwnx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26400a; +} + +static void +Opcode_ivp_subwnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90006; +} + +static void +Opcode_ivp_subwnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0680b; +} + +static void +Opcode_ivp_subwnx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000a; +} + +static void +Opcode_ivp_subwnx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000a; +} + +static void +Opcode_ivp_subwanx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264009; +} + +static void +Opcode_ivp_subwanx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90005; +} + +static void +Opcode_ivp_subwanx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0640b; +} + +static void +Opcode_ivp_subwanx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190009; +} + +static void +Opcode_ivp_subwanx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140009; +} + +static void +Opcode_ivp_subwunx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26400e; +} + +static void +Opcode_ivp_subwunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf9000a; +} + +static void +Opcode_ivp_subwunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0780b; +} + +static void +Opcode_ivp_subwunx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000e; +} + +static void +Opcode_ivp_subwunx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000e; +} + +static void +Opcode_ivp_subwuanx16_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26400d; +} + +static void +Opcode_ivp_subwuanx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90009; +} + +static void +Opcode_ivp_subwuanx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0740b; +} + +static void +Opcode_ivp_subwuanx16_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000d; +} + +static void +Opcode_ivp_subwuanx16_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000d; +} + +static void +Opcode_ivp_subw2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264007; +} + +static void +Opcode_ivp_subw2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90003; +} + +static void +Opcode_ivp_subw2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c0a; +} + +static void +Opcode_ivp_subw2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190007; +} + +static void +Opcode_ivp_subw2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140007; +} + +static void +Opcode_ivp_subwa2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264008; +} + +static void +Opcode_ivp_subwa2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90004; +} + +static void +Opcode_ivp_subwa2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0600b; +} + +static void +Opcode_ivp_subwa2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190008; +} + +static void +Opcode_ivp_subwa2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140008; +} + +static void +Opcode_ivp_subwu2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26400b; +} + +static void +Opcode_ivp_subwu2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90007; +} + +static void +Opcode_ivp_subwu2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c0b; +} + +static void +Opcode_ivp_subwu2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000b; +} + +static void +Opcode_ivp_subwu2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000b; +} + +static void +Opcode_ivp_subwua2nx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26400c; +} + +static void +Opcode_ivp_subwua2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90008; +} + +static void +Opcode_ivp_subwua2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0700b; +} + +static void +Opcode_ivp_subwua2nx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000c; +} + +static void +Opcode_ivp_subwua2nx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000c; +} + +static void +Opcode_ivp_randb2n_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1718d0; +} + +static void +Opcode_ivp_randb2n_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0052; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_randb2n_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261853; +} + +static void +Opcode_ivp_randb2n_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30001d0; +} + +static void +Opcode_ivp_randb2n_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261815; +} + +static void +Opcode_ivp_randb2n_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000d0; +} + +static void +Opcode_ivp_randb2n_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1812; +} + +static void +Opcode_ivp_randb2n_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98100d8; +} + +static void +Opcode_ivp_randb2n_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0418; +} + +static void +Opcode_ivp_randb2n_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd828e6; +} + +static void +Opcode_ivp_randb2n_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c7819; +} + +static void +Opcode_ivp_rorb2n_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1710d2; +} + +static void +Opcode_ivp_rorb2n_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0004; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rorb2n_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261856; +} + +static void +Opcode_ivp_rorb2n_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000101; +} + +static void +Opcode_ivp_rorb2n_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261020; +} + +static void +Opcode_ivp_rorb2n_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800001; +} + +static void +Opcode_ivp_rorb2n_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9818; +} + +static void +Opcode_ivp_rorb2n_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9810208; +} + +static void +Opcode_ivp_rorb2n_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0518; +} + +static void +Opcode_ivp_rorb2n_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd828ec; +} + +static void +Opcode_ivp_rorb2n_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c781c; +} + +static void +Opcode_ivp_randbn_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1710d1; +} + +static void +Opcode_ivp_randbn_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0062; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_randbn_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261854; +} + +static void +Opcode_ivp_randbn_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30001e0; +} + +static void +Opcode_ivp_randbn_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261816; +} + +static void +Opcode_ivp_randbn_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000e0; +} + +static void +Opcode_ivp_randbn_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1013; +} + +static void +Opcode_ivp_randbn_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98100e8; +} + +static void +Opcode_ivp_randbn_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0510; +} + +static void +Opcode_ivp_randbn_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd828e8; +} + +static void +Opcode_ivp_randbn_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c781a; +} + +static void +Opcode_ivp_rorbn_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1718d2; +} + +static void +Opcode_ivp_rorbn_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0006; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rorbn_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261857; +} + +static void +Opcode_ivp_rorbn_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000111; +} + +static void +Opcode_ivp_rorbn_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261820; +} + +static void +Opcode_ivp_rorbn_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800011; +} + +static void +Opcode_ivp_rorbn_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9819; +} + +static void +Opcode_ivp_rorbn_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9810218; +} + +static void +Opcode_ivp_rorbn_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0518; +} + +static void +Opcode_ivp_rorbn_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd828ee; +} + +static void +Opcode_ivp_rorbn_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c781d; +} + +static void +Opcode_ivp_randbn_2_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1718d1; +} + +static void +Opcode_ivp_randbn_2_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0072; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_randbn_2_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261855; +} + +static void +Opcode_ivp_randbn_2_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30001f0; +} + +static void +Opcode_ivp_randbn_2_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261817; +} + +static void +Opcode_ivp_randbn_2_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000f0; +} + +static void +Opcode_ivp_randbn_2_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1813; +} + +static void +Opcode_ivp_randbn_2_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98100f8; +} + +static void +Opcode_ivp_randbn_2_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0510; +} + +static void +Opcode_ivp_randbn_2_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd828ea; +} + +static void +Opcode_ivp_randbn_2_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c781b; +} + +static void +Opcode_ivp_rorbn_2_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1710d3; +} + +static void +Opcode_ivp_rorbn_2_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0014; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_rorbn_2_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261060; +} + +static void +Opcode_ivp_rorbn_2_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000121; +} + +static void +Opcode_ivp_rorbn_2_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261021; +} + +static void +Opcode_ivp_rorbn_2_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800021; +} + +static void +Opcode_ivp_rorbn_2_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a981a; +} + +static void +Opcode_ivp_rorbn_2_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9810228; +} + +static void +Opcode_ivp_rorbn_2_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0610; +} + +static void +Opcode_ivp_rorbn_2_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd830e0; +} + +static void +Opcode_ivp_rorbn_2_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c781e; +} + +static void +Opcode_ivp_avgnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c402c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_avgnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1288000; +} + +static void +Opcode_ivp_avgnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc88000; +} + +static void +Opcode_ivp_avgnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0020a; +} + +static void +Opcode_ivp_avgnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00016; +} + +static void +Opcode_ivp_avgnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0010a; +} + +static void +Opcode_ivp_avgnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f8000b; +} + +static void +Opcode_ivp_avgnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d8000; +} + +static void +Opcode_ivp_avgnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb68000; +} + +static void +Opcode_ivp_avgnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d8000; +} + +static void +Opcode_ivp_avgnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f00280; +} + +static void +Opcode_ivp_avgunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_avgunx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b8000; +} + +static void +Opcode_ivp_avgunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb8000; +} + +static void +Opcode_ivp_avgunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190030a; +} + +static void +Opcode_ivp_avgunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900018; +} + +static void +Opcode_ivp_avgunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0010c; +} + +static void +Opcode_ivp_avgunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9380005; +} + +static void +Opcode_ivp_avgunx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f8000; +} + +static void +Opcode_ivp_avgunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb98000; +} + +static void +Opcode_ivp_avgunx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f8000; +} + +static void +Opcode_ivp_avgunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d002a0; +} + +static void +Opcode_ivp_avg2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ivp_avg2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ivp_avg2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0020a; +} + +static void +Opcode_ivp_avg2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00006; +} + +static void +Opcode_ivp_avg2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0010a; +} + +static void +Opcode_ivp_avg2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f0000b; +} + +static void +Opcode_ivp_avg2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d0000; +} + +static void +Opcode_ivp_avg2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb60000; +} + +static void +Opcode_ivp_avg2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0000; +} + +static void +Opcode_ivp_avg2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e00280; +} + +static void +Opcode_ivp_avgr2nx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1290000; +} + +static void +Opcode_ivp_avgr2nx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90000; +} + +static void +Opcode_ivp_avgr2nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900300; +} + +static void +Opcode_ivp_avgr2nx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00007; +} + +static void +Opcode_ivp_avgr2nx8_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280010c; +} + +static void +Opcode_ivp_avgr2nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9380000; +} + +static void +Opcode_ivp_avgr2nx8_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e0000; +} + +static void +Opcode_ivp_avgr2nx8_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb70000; +} + +static void +Opcode_ivp_avgr2nx8_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0000; +} + +static void +Opcode_ivp_avgr2nx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28002a0; +} + +static void +Opcode_ivp_avgrnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e402c00; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_avgrnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1298000; +} + +static void +Opcode_ivp_avgrnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc98000; +} + +static void +Opcode_ivp_avgrnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900302; +} + +static void +Opcode_ivp_avgrnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00017; +} + +static void +Opcode_ivp_avgrnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290010c; +} + +static void +Opcode_ivp_avgrnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9380001; +} + +static void +Opcode_ivp_avgrnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e8000; +} + +static void +Opcode_ivp_avgrnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb78000; +} + +static void +Opcode_ivp_avgrnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e8000; +} + +static void +Opcode_ivp_avgrnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29002a0; +} + +static void +Opcode_ivp_avgrunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_avgrunx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a8000; +} + +static void +Opcode_ivp_avgrunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca8000; +} + +static void +Opcode_ivp_avgrunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900306; +} + +static void +Opcode_ivp_avgrunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00017; +} + +static void +Opcode_ivp_avgrunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0010c; +} + +static void +Opcode_ivp_avgrunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9380003; +} + +static void +Opcode_ivp_avgrunx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f0000; +} + +static void +Opcode_ivp_avgrunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb88000; +} + +static void +Opcode_ivp_avgrunx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0000; +} + +static void +Opcode_ivp_avgrunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b002a0; +} + +static void +Opcode_ivp_gatheranx8u_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d3800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_gatheranx8u_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1449200; +} + +static void +Opcode_ivp_gatheranx8u_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54200c; +} + +static void +Opcode_ivp_gatheranx8u_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d3800; +} + +static void +Opcode_ivp_gatheranx8u_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b200c; +} + +static void +Opcode_ivp_gatheranx8u_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f2800; +} + +static void +Opcode_ivp_gatheranx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d1800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_gatheranx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1441200; +} + +static void +Opcode_ivp_gatheranx16_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54000c; +} + +static void +Opcode_ivp_gatheranx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d1800; +} + +static void +Opcode_ivp_gatheranx16_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b000c; +} + +static void +Opcode_ivp_gatheranx16_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f0800; +} + +static void +Opcode_ivp_gatheran_2x32_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d5800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_gatheran_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1451200; +} + +static void +Opcode_ivp_gatheran_2x32_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54400c; +} + +static void +Opcode_ivp_gatheran_2x32_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d5800; +} + +static void +Opcode_ivp_gatheran_2x32_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b400c; +} + +static void +Opcode_ivp_gatheran_2x32_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f4800; +} + +static void +Opcode_ivp_gatheranx8ut_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d0800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_gatheranx8ut_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1401200; +} + +static void +Opcode_ivp_gatheranx8ut_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540004; +} + +static void +Opcode_ivp_gatheranx8ut_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d0800; +} + +static void +Opcode_ivp_gatheranx8ut_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0004; +} + +static void +Opcode_ivp_gatheranx8ut_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980800; +} + +static void +Opcode_ivp_gatheranx16t_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_gatheranx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1401000; +} + +static void +Opcode_ivp_gatheranx16t_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ivp_gatheranx16t_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d0000; +} + +static void +Opcode_ivp_gatheranx16t_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0000; +} + +static void +Opcode_ivp_gatheranx16t_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980000; +} + +static void +Opcode_ivp_gatheran_2x32t_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108d1000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_gatheran_2x32t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1441000; +} + +static void +Opcode_ivp_gatheran_2x32t_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540008; +} + +static void +Opcode_ivp_gatheran_2x32t_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d1000; +} + +static void +Opcode_ivp_gatheran_2x32t_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0008; +} + +static void +Opcode_ivp_gatheran_2x32t_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x982000; +} + +static void +Opcode_ivp_gatherdnx16_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1720dc; +} + +static void +Opcode_ivp_gatherdnx16_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26605c; +} + +static void +Opcode_ivp_gatherdnx16_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2820bc; +} + +static void +Opcode_ivp_gatherdnx16_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a0f4; +} + +static void +Opcode_ivp_gatherdnx16_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b40ac; +} + +static void +Opcode_ivp_gatherdnx16_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce0a4; +} + +static void +Opcode_ivp_gatherdnx8s_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1740dc; +} + +static void +Opcode_ivp_gatherdnx8s_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26805c; +} + +static void +Opcode_ivp_gatherdnx8s_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2820cc; +} + +static void +Opcode_ivp_gatherdnx8s_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a0d8; +} + +static void +Opcode_ivp_gatherdnx8s_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b60a0; +} + +static void +Opcode_ivp_gatherdnx8s_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce0a8; +} + +static void +Opcode_ivp_gatherd2nx8_l_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700dc; +} + +static void +Opcode_ivp_gatherd2nx8_l_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26405c; +} + +static void +Opcode_ivp_gatherd2nx8_l_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2820ac; +} + +static void +Opcode_ivp_gatherd2nx8_l_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a0d4; +} + +static void +Opcode_ivp_gatherd2nx8_l_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b40a8; +} + +static void +Opcode_ivp_gatherd2nx8_l_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce0a0; +} + +static void +Opcode_ivp_gatherd2nx8_h_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e0d8; +} + +static void +Opcode_ivp_gatherd2nx8_h_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26205c; +} + +static void +Opcode_ivp_gatherd2nx8_h_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28209c; +} + +static void +Opcode_ivp_gatherd2nx8_h_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a0f0; +} + +static void +Opcode_ivp_gatherd2nx8_h_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b40a4; +} + +static void +Opcode_ivp_gatherd2nx8_h_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc0ac; +} + +static void +Opcode_ivp_movgatherd_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a36050; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_movgatherd_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11130d0; +} + +static void +Opcode_ivp_movgatherd_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54a00c; +} + +static void +Opcode_ivp_movgatherd_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0a050; +} + +static void +Opcode_ivp_movgatherd_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220f0; +} + +static void +Opcode_ivp_movgatherd_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f30f0; +} + +static void +Opcode_ivp_scatternx8u_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xddc000; +} + +static void +Opcode_ivp_scatternx8u_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x964000; +} + +static void +Opcode_ivp_scatter2nx8_l_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdcc000; +} + +static void +Opcode_ivp_scatter2nx8_l_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x95c000; +} + +static void +Opcode_ivp_scatter2nx8_h_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc4000; +} + +static void +Opcode_ivp_scatter2nx8_h_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x958000; +} + +static void +Opcode_ivp_scatternx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd4000; +} + +static void +Opcode_ivp_scatternx16_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x960000; +} + +static void +Opcode_ivp_scattern_2x32_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde4000; +} + +static void +Opcode_ivp_scattern_2x32_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x968000; +} + +static void +Opcode_ivp_scatternx8ut_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd84000; +} + +static void +Opcode_ivp_scatternx8ut_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ivp_scatter2nx8t_l_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd44000; +} + +static void +Opcode_ivp_scatter2nx8t_l_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ivp_scatter2nx8t_h_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ivp_scatter2nx8t_h_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e0000; +} + +static void +Opcode_ivp_scatternx16t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ivp_scatternx16t_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620000; +} + +static void +Opcode_ivp_scattern_2x32t_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ivp_scattern_2x32t_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660000; +} + +static void +Opcode_ivp_scatterw_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a202f5; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_scatterw_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500655; +} + +static void +Opcode_ivp_scatterw_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600335; +} + +static void +Opcode_ivp_scatterw_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x831ad1; +} + +static void +Opcode_ivp_scatterw_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f1475; +} + +static void +Opcode_ivp_scatterw_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x850325; +} + +static void +Opcode_ivp_scatterw_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f92f1; +} + +static void +Opcode_ivp_counteqz4nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300200; +} + +static void +Opcode_ivp_counteqz4nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8480000; +} + +static void +Opcode_ivp_counteqz4nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000000; +} + +static void +Opcode_ivp_counteq4nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300000; +} + +static void +Opcode_ivp_counteq4nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8400000; +} + +static void +Opcode_ivp_counteq4nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000000; +} + +static void +Opcode_ivp_counteqmz4nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ivp_counteqmz4nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000000; +} + +static void +Opcode_ivp_counteqm4nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ivp_counteqm4nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; +} + +static void +Opcode_ivp_countlez4nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500000; +} + +static void +Opcode_ivp_countlez4nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8580000; +} + +static void +Opcode_ivp_countlez4nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e100000; +} + +static void +Opcode_ivp_countle4nx8_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400000; +} + +static void +Opcode_ivp_countle4nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8500000; +} + +static void +Opcode_ivp_countle4nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c100000; +} + +static void +Opcode_ivp_countlemz4nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; +} + +static void +Opcode_ivp_countlemz4nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000000; +} + +static void +Opcode_ivp_countlem4nx8_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; +} + +static void +Opcode_ivp_countlem4nx8_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; +} + +static void +Opcode_ivp_lsr2nx8_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10878000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsr2nx8_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f8000; +} + +static void +Opcode_ivp_lsr2nx8_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4000; +} + +static void +Opcode_ivp_lsr2nx8_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4000; +} + +static void +Opcode_ivp_lsr2nx8_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x978000; +} + +static void +Opcode_ivp_lsr2nx8_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10560000; +} + +static void +Opcode_ivp_lsr2nx8_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10982000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsr2nx8_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b2000; +} + +static void +Opcode_ivp_lsr2nx8_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x228000; +} + +static void +Opcode_ivp_lsr2nx8_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x228000; +} + +static void +Opcode_ivp_lsr2nx8_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa82000; +} + +static void +Opcode_ivp_lsr2nx8_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b8000; +} + +static void +Opcode_ivp_lsr2nx8_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108ec000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsr2nx8_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1422000; +} + +static void +Opcode_ivp_lsr2nx8_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fe000; +} + +static void +Opcode_ivp_lsr2nx8_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fc000; +} + +static void +Opcode_ivp_lsr2nx8_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ec000; +} + +static void +Opcode_ivp_lsr2nx8_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058c000; +} + +static void +Opcode_ivp_lsr2nx8_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108ee000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsr2nx8_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142a000; +} + +static void +Opcode_ivp_lsr2nx8_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_lsr2nx8_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fe000; +} + +static void +Opcode_ivp_lsr2nx8_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ee000; +} + +static void +Opcode_ivp_lsr2nx8_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058e000; +} + +static void +Opcode_ivp_lsrnx16_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10880000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsrnx16_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ivp_lsrnx16_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6000; +} + +static void +Opcode_ivp_lsrnx16_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6000; +} + +static void +Opcode_ivp_lsrnx16_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980000; +} + +static void +Opcode_ivp_lsrnx16_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10568000; +} + +static void +Opcode_ivp_lsrnx16_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10986000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsrnx16_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ba000; +} + +static void +Opcode_ivp_lsrnx16_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22a000; +} + +static void +Opcode_ivp_lsrnx16_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22a000; +} + +static void +Opcode_ivp_lsrnx16_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa86000; +} + +static void +Opcode_ivp_lsrnx16_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ba000; +} + +static void +Opcode_ivp_lsrnx16_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108f0000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsrnx16_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1432000; +} + +static void +Opcode_ivp_lsrnx16_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x202000; +} + +static void +Opcode_ivp_lsrnx16_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ivp_lsrnx16_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f0000; +} + +static void +Opcode_ivp_lsrnx16_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10590000; +} + +static void +Opcode_ivp_lsrnx16_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108f2000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsrnx16_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143a000; +} + +static void +Opcode_ivp_lsrnx16_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x204000; +} + +static void +Opcode_ivp_lsrnx16_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x202000; +} + +static void +Opcode_ivp_lsrnx16_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f2000; +} + +static void +Opcode_ivp_lsrnx16_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10592000; +} + +static void +Opcode_ivp_lsrn_2x32_i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10888000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsrn_2x32_i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1208000; +} + +static void +Opcode_ivp_lsrn_2x32_i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_ivp_lsrn_2x32_i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_ivp_lsrn_2x32_i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x988000; +} + +static void +Opcode_ivp_lsrn_2x32_i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10570000; +} + +static void +Opcode_ivp_lsrn_2x32_ip_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1098a000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsrn_2x32_ip_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1384000; +} + +static void +Opcode_ivp_lsrn_2x32_ip_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22c000; +} + +static void +Opcode_ivp_lsrn_2x32_ip_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22c000; +} + +static void +Opcode_ivp_lsrn_2x32_ip_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8a000; +} + +static void +Opcode_ivp_lsrn_2x32_ip_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105bc000; +} + +static void +Opcode_ivp_lsrn_2x32_x_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108f4000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsrn_2x32_x_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1442000; +} + +static void +Opcode_ivp_lsrn_2x32_x_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x206000; +} + +static void +Opcode_ivp_lsrn_2x32_x_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x204000; +} + +static void +Opcode_ivp_lsrn_2x32_x_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f4000; +} + +static void +Opcode_ivp_lsrn_2x32_x_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10594000; +} + +static void +Opcode_ivp_lsrn_2x32_xp_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108f6000; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_lsrn_2x32_xp_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144a000; +} + +static void +Opcode_ivp_lsrn_2x32_xp_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x208000; +} + +static void +Opcode_ivp_lsrn_2x32_xp_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x206000; +} + +static void +Opcode_ivp_lsrn_2x32_xp_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f6000; +} + +static void +Opcode_ivp_lsrn_2x32_xp_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10596000; +} + +static void +Opcode_ivp_absnx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a30050; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_absnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27500d0a; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_absnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11180f0; +} + +static void +Opcode_ivp_absnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf58060; +} + +static void +Opcode_ivp_absnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330540e; +} + +static void +Opcode_ivp_absnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f60012; +} + +static void +Opcode_ivp_absnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f05608; +} + +static void +Opcode_ivp_absnx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82c0d0; +} + +static void +Opcode_ivp_absnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94800d9; +} + +static void +Opcode_ivp_absnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8060; +} + +static void +Opcode_ivp_absnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606d08; +} + +static void +Opcode_ivp_absnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20300; +} + +static void +Opcode_ivp_absnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8020; +} + +static void +Opcode_ivp_absnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2705540; +} + +static void +Opcode_ivp_abssnx16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a30090; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_abssnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27500d0c; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_abssnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11080d0; +} + +static void +Opcode_ivp_abssnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf68060; +} + +static void +Opcode_ivp_abssnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330640e; +} + +static void +Opcode_ivp_abssnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f60014; +} + +static void +Opcode_ivp_abssnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f06608; +} + +static void +Opcode_ivp_abssnx16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8300f0; +} + +static void +Opcode_ivp_abssnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9480199; +} + +static void +Opcode_ivp_abssnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a80a0; +} + +static void +Opcode_ivp_abssnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e606f08; +} + +static void +Opcode_ivp_abssnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20302; +} + +static void +Opcode_ivp_abssnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8060; +} + +static void +Opcode_ivp_abssnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2706540; +} + +static void +Opcode_ivp_abssubnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c402400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_abssubnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_ivp_abssubnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ivp_abssubnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e00208; +} + +static void +Opcode_ivp_abssubnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00004; +} + +static void +Opcode_ivp_abssubnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e00108; +} + +static void +Opcode_ivp_abssubnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9300006; +} + +static void +Opcode_ivp_abssubnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_ivp_abssubnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c105c00; +} + +static void +Opcode_ivp_abssubnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb20000; +} + +static void +Opcode_ivp_abssubnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x390000; +} + +static void +Opcode_ivp_abssubnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e000e0; +} + +static void +Opcode_ivp_abssubunx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38402800; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_abssubunx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1250000; +} + +static void +Opcode_ivp_abssubunx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc50000; +} + +static void +Opcode_ivp_abssubunx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280020a; +} + +static void +Opcode_ivp_abssubunx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00005; +} + +static void +Opcode_ivp_abssubunx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280010a; +} + +static void +Opcode_ivp_abssubunx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000b; +} + +static void +Opcode_ivp_abssubunx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0000; +} + +static void +Opcode_ivp_abssubunx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e006000; +} + +static void +Opcode_ivp_abssubunx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_ivp_abssubunx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0000; +} + +static void +Opcode_ivp_abssubunx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800280; +} + +static void +Opcode_ivp_absssubnx16_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38402400; + slotbuf[1] = 0; +} + +static void +Opcode_ivp_absssubnx16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1230000; +} + +static void +Opcode_ivp_absssubnx16_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30000; +} + +static void +Opcode_ivp_absssubnx16_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c00208; +} + +static void +Opcode_ivp_absssubnx16_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00004; +} + +static void +Opcode_ivp_absssubnx16_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c00108; +} + +static void +Opcode_ivp_absssubnx16_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9300004; +} + +static void +Opcode_ivp_absssubnx16_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ivp_absssubnx16_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c105800; +} + +static void +Opcode_ivp_absssubnx16_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_ivp_absssubnx16_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ivp_absssubnx16_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c000e0; +} + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01d; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134800; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614800; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34900; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134900; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614900; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf06d; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_l32i_n_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b3000; +} + +static void +Opcode_l32i_n_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80b000; +} + +static void +Opcode_l32i_n_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa42000; +} + +static void +Opcode_l32i_n_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae000; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_mov_n_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0100; + slotbuf[1] = 0; +} + +static void +Opcode_mov_n_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000500; +} + +static void +Opcode_mov_n_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800400; +} + +static void +Opcode_mov_n_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9882000; +} + +static void +Opcode_mov_n_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c40e000; +} + +static void +Opcode_mov_n_Slot_f5_s3_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_mov_n_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2a000; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03d; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00d; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_s32i_n_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf000; +} + +static void +Opcode_s32i_n_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x811000; +} + +static void +Opcode_s32i_n_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa50000; +} + +static void +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e70; +} + +static void +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e700; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addi_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10560000; + slotbuf[1] = 0; +} + +static void +Opcode_addi_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_addi_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_addi_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a400000; + slotbuf[1] = 0; +} + +static void +Opcode_addi_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_addi_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_addi_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_addi_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000200; +} + +static void +Opcode_addi_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360000; +} + +static void +Opcode_addi_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_addi_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c03000; +} + +static void +Opcode_addi_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900200; +} + +static void +Opcode_addi_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560000; +} + +static void +Opcode_addi_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_addi_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_addi_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9800000; +} + +static void +Opcode_addi_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10360000; +} + +static void +Opcode_addi_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_addi_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c006000; +} + +static void +Opcode_addi_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10160000; + slotbuf[1] = 0; +} + +static void +Opcode_addi_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_addi_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_addi_Slot_f5_s3_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_addi_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_addi_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_addi_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_addi_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_addi_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_addi_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300000; +} + +static void +Opcode_addi_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e0000; +} + +static void +Opcode_addi_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_addi_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_addi_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_addmi_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10570000; + slotbuf[1] = 0; +} + +static void +Opcode_addmi_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_addmi_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30000; +} + +static void +Opcode_addmi_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c000; +} + +static void +Opcode_addmi_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370000; +} + +static void +Opcode_addmi_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c000; +} + +static void +Opcode_addmi_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x570000; +} + +static void +Opcode_addmi_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_addmi_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10370000; +} + +static void +Opcode_addmi_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_addmi_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10170000; + slotbuf[1] = 0; +} + +static void +Opcode_addmi_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_addmi_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_addmi_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_addmi_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_addmi_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_addmi_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f0000; +} + +static void +Opcode_addmi_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690000; +} + +static void +Opcode_addmi_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_add_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109ce000; + slotbuf[1] = 0; +} + +static void +Opcode_add_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000; +} + +static void +Opcode_add_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d6000; +} + +static void +Opcode_add_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c8000; +} + +static void +Opcode_add_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23a000; +} + +static void +Opcode_add_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0000; +} + +static void +Opcode_add_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x596000; +} + +static void +Opcode_add_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23a000; +} + +static void +Opcode_add_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e81000; +} + +static void +Opcode_add_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xace000; +} + +static void +Opcode_add_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000; +} + +static void +Opcode_add_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x156000; +} + +static void +Opcode_add_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ca000; +} + +static void +Opcode_add_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000; +} + +static void +Opcode_add_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10204000; + slotbuf[1] = 0; +} + +static void +Opcode_add_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94000; +} + +static void +Opcode_add_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34000; +} + +static void +Opcode_add_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154000; +} + +static void +Opcode_add_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5000; +} + +static void +Opcode_add_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109000; +} + +static void +Opcode_add_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_add_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2310000; +} + +static void +Opcode_add_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x801000; +} + +static void +Opcode_add_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c4000; +} + +static void +Opcode_add_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3c000; +} + +static void +Opcode_add_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198000; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_sub_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a21000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d9000; +} + +static void +Opcode_sub_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d7000; +} + +static void +Opcode_sub_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1445000; +} + +static void +Opcode_sub_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24a000; +} + +static void +Opcode_sub_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa3000; +} + +static void +Opcode_sub_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b1000; +} + +static void +Opcode_sub_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24b000; +} + +static void +Opcode_sub_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e99000; +} + +static void +Opcode_sub_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xafa000; +} + +static void +Opcode_sub_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x189000; +} + +static void +Opcode_sub_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f000; +} + +static void +Opcode_sub_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e0000; +} + +static void +Opcode_sub_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x189000; +} + +static void +Opcode_sub_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1021a000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5000; +} + +static void +Opcode_sub_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46000; +} + +static void +Opcode_sub_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x165000; +} + +static void +Opcode_sub_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc000; +} + +static void +Opcode_sub_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107000; +} + +static void +Opcode_sub_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4000; +} + +static void +Opcode_sub_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2316000; +} + +static void +Opcode_sub_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x818000; +} + +static void +Opcode_sub_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x659000; +} + +static void +Opcode_sub_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa51000; +} + +static void +Opcode_sub_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8000; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addx2_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109cf000; + slotbuf[1] = 0; +} + +static void +Opcode_addx2_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e2000; +} + +static void +Opcode_addx2_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d7000; +} + +static void +Opcode_addx2_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c9000; +} + +static void +Opcode_addx2_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23b000; +} + +static void +Opcode_addx2_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa4000; +} + +static void +Opcode_addx2_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x597000; +} + +static void +Opcode_addx2_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23b000; +} + +static void +Opcode_addx2_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f81000; +} + +static void +Opcode_addx2_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xacf000; +} + +static void +Opcode_addx2_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000; +} + +static void +Opcode_addx2_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x157000; +} + +static void +Opcode_addx2_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105cb000; +} + +static void +Opcode_addx2_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000; +} + +static void +Opcode_addx2_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10205000; + slotbuf[1] = 0; +} + +static void +Opcode_addx2_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x95000; +} + +static void +Opcode_addx2_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35000; +} + +static void +Opcode_addx2_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x155000; +} + +static void +Opcode_addx2_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7000; +} + +static void +Opcode_addx2_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d000; +} + +static void +Opcode_addx2_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2000; +} + +static void +Opcode_addx2_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2311000; +} + +static void +Opcode_addx2_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x803000; +} + +static void +Opcode_addx2_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c5000; +} + +static void +Opcode_addx2_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3e000; +} + +static void +Opcode_addx2_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x199000; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_addx4_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a14000; + slotbuf[1] = 0; +} + +static void +Opcode_addx4_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1000; +} + +static void +Opcode_addx4_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x354000; +} + +static void +Opcode_addx4_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d0000; +} + +static void +Opcode_addx4_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23c000; +} + +static void +Opcode_addx4_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa1000; +} + +static void +Opcode_addx4_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x598000; +} + +static void +Opcode_addx4_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23c000; +} + +static void +Opcode_addx4_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e89000; +} + +static void +Opcode_addx4_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad2000; +} + +static void +Opcode_addx4_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000; +} + +static void +Opcode_addx4_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_addx4_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105cc000; +} + +static void +Opcode_addx4_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000; +} + +static void +Opcode_addx4_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10206000; + slotbuf[1] = 0; +} + +static void +Opcode_addx4_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96000; +} + +static void +Opcode_addx4_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_addx4_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x156000; +} + +static void +Opcode_addx4_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000; +} + +static void +Opcode_addx4_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102000; +} + +static void +Opcode_addx4_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b4000; +} + +static void +Opcode_addx4_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2312000; +} + +static void +Opcode_addx4_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x805000; +} + +static void +Opcode_addx4_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c6000; +} + +static void +Opcode_addx4_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3d000; +} + +static void +Opcode_addx4_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a000; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_addx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a16000; + slotbuf[1] = 0; +} + +static void +Opcode_addx8_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9000; +} + +static void +Opcode_addx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d4000; +} + +static void +Opcode_addx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d1000; +} + +static void +Opcode_addx8_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23d000; +} + +static void +Opcode_addx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa5000; +} + +static void +Opcode_addx8_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59a000; +} + +static void +Opcode_addx8_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23d000; +} + +static void +Opcode_addx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f89000; +} + +static void +Opcode_addx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad3000; +} + +static void +Opcode_addx8_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000; +} + +static void +Opcode_addx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c000; +} + +static void +Opcode_addx8_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ce000; +} + +static void +Opcode_addx8_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000; +} + +static void +Opcode_addx8_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10207000; + slotbuf[1] = 0; +} + +static void +Opcode_addx8_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x97000; +} + +static void +Opcode_addx8_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37000; +} + +static void +Opcode_addx8_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x157000; +} + +static void +Opcode_addx8_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000; +} + +static void +Opcode_addx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106000; +} + +static void +Opcode_addx8_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6000; +} + +static void +Opcode_addx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2313000; +} + +static void +Opcode_addx8_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x807000; +} + +static void +Opcode_addx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c7000; +} + +static void +Opcode_addx8_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3f000; +} + +static void +Opcode_addx8_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19b000; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_subx2_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a23000; + slotbuf[1] = 0; +} + +static void +Opcode_subx2_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1da000; +} + +static void +Opcode_subx2_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x255000; +} + +static void +Opcode_subx2_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1447000; +} + +static void +Opcode_subx2_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24b000; +} + +static void +Opcode_subx2_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa7000; +} + +static void +Opcode_subx2_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b3000; +} + +static void +Opcode_subx2_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24c000; +} + +static void +Opcode_subx2_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f99000; +} + +static void +Opcode_subx2_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xafb000; +} + +static void +Opcode_subx2_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a000; +} + +static void +Opcode_subx2_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000; +} + +static void +Opcode_subx2_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e2000; +} + +static void +Opcode_subx2_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a000; +} + +static void +Opcode_subx2_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1021b000; + slotbuf[1] = 0; +} + +static void +Opcode_subx2_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6000; +} + +static void +Opcode_subx2_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47000; +} + +static void +Opcode_subx2_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x166000; +} + +static void +Opcode_subx2_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe000; +} + +static void +Opcode_subx2_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b000; +} + +static void +Opcode_subx2_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6000; +} + +static void +Opcode_subx2_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2317000; +} + +static void +Opcode_subx2_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81a000; +} + +static void +Opcode_subx2_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d9000; +} + +static void +Opcode_subx2_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa53000; +} + +static void +Opcode_subx2_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9000; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_subx4_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a25000; + slotbuf[1] = 0; +} + +static void +Opcode_subx4_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1db000; +} + +static void +Opcode_subx4_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d5000; +} + +static void +Opcode_subx4_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144d000; +} + +static void +Opcode_subx4_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24c000; +} + +static void +Opcode_subx4_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa8000; +} + +static void +Opcode_subx4_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b5000; +} + +static void +Opcode_subx4_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24d000; +} + +static void +Opcode_subx4_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea1000; +} + +static void +Opcode_subx4_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xafe000; +} + +static void +Opcode_subx4_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b000; +} + +static void +Opcode_subx4_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x155000; +} + +static void +Opcode_subx4_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e4000; +} + +static void +Opcode_subx4_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b000; +} + +static void +Opcode_subx4_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1021c000; + slotbuf[1] = 0; +} + +static void +Opcode_subx4_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7000; +} + +static void +Opcode_subx4_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000; +} + +static void +Opcode_subx4_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x167000; +} + +static void +Opcode_subx4_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb1000; +} + +static void +Opcode_subx4_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f000; +} + +static void +Opcode_subx4_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c1000; +} + +static void +Opcode_subx4_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2318000; +} + +static void +Opcode_subx4_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81c000; +} + +static void +Opcode_subx4_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x759000; +} + +static void +Opcode_subx4_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa55000; +} + +static void +Opcode_subx4_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa000; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_subx8_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a27000; + slotbuf[1] = 0; +} + +static void +Opcode_subx8_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c1000; +} + +static void +Opcode_subx8_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x355000; +} + +static void +Opcode_subx8_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144f000; +} + +static void +Opcode_subx8_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24d000; +} + +static void +Opcode_subx8_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfac000; +} + +static void +Opcode_subx8_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b7000; +} + +static void +Opcode_subx8_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24e000; +} + +static void +Opcode_subx8_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fa1000; +} + +static void +Opcode_subx8_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaff000; +} + +static void +Opcode_subx8_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c000; +} + +static void +Opcode_subx8_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000; +} + +static void +Opcode_subx8_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e6000; +} + +static void +Opcode_subx8_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c000; +} + +static void +Opcode_subx8_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1021d000; + slotbuf[1] = 0; +} + +static void +Opcode_subx8_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000; +} + +static void +Opcode_subx8_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x49000; +} + +static void +Opcode_subx8_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_subx8_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3000; +} + +static void +Opcode_subx8_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_subx8_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c3000; +} + +static void +Opcode_subx8_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2319000; +} + +static void +Opcode_subx8_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81e000; +} + +static void +Opcode_subx8_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d9000; +} + +static void +Opcode_subx8_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa57000; +} + +static void +Opcode_subx8_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab000; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_and_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a15000; + slotbuf[1] = 0; +} + +static void +Opcode_and_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e3000; +} + +static void +Opcode_and_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x356000; +} + +static void +Opcode_and_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d8000; +} + +static void +Opcode_and_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23e000; +} + +static void +Opcode_and_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa2000; +} + +static void +Opcode_and_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59c000; +} + +static void +Opcode_and_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23e000; +} + +static void +Opcode_and_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e91000; +} + +static void +Opcode_and_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad6000; +} + +static void +Opcode_and_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c000; +} + +static void +Opcode_and_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000; +} + +static void +Opcode_and_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105cd000; +} + +static void +Opcode_and_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c000; +} + +static void +Opcode_and_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10208000; + slotbuf[1] = 0; +} + +static void +Opcode_and_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98000; +} + +static void +Opcode_and_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_and_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_and_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000; +} + +static void +Opcode_and_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a000; +} + +static void +Opcode_and_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1000; +} + +static void +Opcode_and_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2314000; +} + +static void +Opcode_and_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x809000; +} + +static void +Opcode_and_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x744000; +} + +static void +Opcode_and_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa40000; +} + +static void +Opcode_and_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19c000; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_or_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a1c000; + slotbuf[1] = 0; +} + +static void +Opcode_or_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2000; +} + +static void +Opcode_or_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d6000; +} + +static void +Opcode_or_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f0000; +} + +static void +Opcode_or_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x247000; +} + +static void +Opcode_or_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa6000; +} + +static void +Opcode_or_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0000; +} + +static void +Opcode_or_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x248000; +} + +static void +Opcode_or_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f91000; +} + +static void +Opcode_or_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf2000; +} + +static void +Opcode_or_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x186000; +} + +static void +Opcode_or_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e000; +} + +static void +Opcode_or_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d9000; +} + +static void +Opcode_or_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x186000; +} + +static void +Opcode_or_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10216000; + slotbuf[1] = 0; +} + +static void +Opcode_or_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1000; +} + +static void +Opcode_or_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41000; +} + +static void +Opcode_or_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x161000; +} + +static void +Opcode_or_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6000; +} + +static void +Opcode_or_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e000; +} + +static void +Opcode_or_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bd000; +} + +static void +Opcode_or_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2315000; +} + +static void +Opcode_or_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x816000; +} + +static void +Opcode_or_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d8000; +} + +static void +Opcode_or_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4f000; +} + +static void +Opcode_or_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a5000; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_xor_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a29000; + slotbuf[1] = 0; +} + +static void +Opcode_xor_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_xor_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d5000; +} + +static void +Opcode_xor_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1455000; +} + +static void +Opcode_xor_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24e000; +} + +static void +Opcode_xor_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa9000; +} + +static void +Opcode_xor_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b8000; +} + +static void +Opcode_xor_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24f000; +} + +static void +Opcode_xor_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea9000; +} + +static void +Opcode_xor_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa01000; +} + +static void +Opcode_xor_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18d000; +} + +static void +Opcode_xor_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d000; +} + +static void +Opcode_xor_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e1000; +} + +static void +Opcode_xor_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18d000; +} + +static void +Opcode_xor_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1021e000; + slotbuf[1] = 0; +} + +static void +Opcode_xor_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9000; +} + +static void +Opcode_xor_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a000; +} + +static void +Opcode_xor_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x169000; +} + +static void +Opcode_xor_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb5000; +} + +static void +Opcode_xor_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x164000; +} + +static void +Opcode_xor_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c5000; +} + +static void +Opcode_xor_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x231a000; +} + +static void +Opcode_xor_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x819000; +} + +static void +Opcode_xor_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65a000; +} + +static void +Opcode_xor_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa58000; +} + +static void +Opcode_xor_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac000; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6007; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe007; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1007; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9007; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa007; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2007; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb007; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3007; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc007; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5007; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd007; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_const16_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4; +} + +static void +Opcode_const16_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0; +} + +static void +Opcode_const16_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_const16_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_const16_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_const16_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; +} + +static void +Opcode_const16_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0; +} + +static void +Opcode_const16_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_const16_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_const16_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_extui_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10540000; + slotbuf[1] = 0; +} + +static void +Opcode_extui_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_extui_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_extui_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_extui_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_extui_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_extui_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_extui_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_extui_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340000; +} + +static void +Opcode_extui_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_extui_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10140000; + slotbuf[1] = 0; +} + +static void +Opcode_extui_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_extui_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_extui_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_extui_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_extui_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_extui_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_extui_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_j_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10380000; + slotbuf[1] = 0; +} + +static void +Opcode_j_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb40000; +} + +static void +Opcode_j_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_j_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_j_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10240000; +} + +static void +Opcode_j_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10100000; + slotbuf[1] = 0; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_l16ui_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d0000; + slotbuf[1] = 0; +} + +static void +Opcode_l16ui_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf50000; +} + +static void +Opcode_l16ui_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_l16ui_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0000; +} + +static void +Opcode_l16ui_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10430000; +} + +static void +Opcode_l16ui_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10190000; + slotbuf[1] = 0; +} + +static void +Opcode_l16ui_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_l16ui_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650000; +} + +static void +Opcode_l16ui_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f0000; +} + +static void +Opcode_l16ui_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9002; +} + +static void +Opcode_l16si_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c0000; + slotbuf[1] = 0; +} + +static void +Opcode_l16si_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_l16si_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_l16si_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_l16si_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10420000; +} + +static void +Opcode_l16si_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10180000; + slotbuf[1] = 0; +} + +static void +Opcode_l16si_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_l16si_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_l16si_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e0000; +} + +static void +Opcode_l16si_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_l32i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e0000; + slotbuf[1] = 0; +} + +static void +Opcode_l32i_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_l32i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf60000; +} + +static void +Opcode_l32i_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_l32i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_l32i_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_l32i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_l32i_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_l32i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10440000; +} + +static void +Opcode_l32i_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_l32i_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101a0000; + slotbuf[1] = 0; +} + +static void +Opcode_l32i_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_l8ui_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f0000; + slotbuf[1] = 0; +} + +static void +Opcode_l8ui_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf70000; +} + +static void +Opcode_l8ui_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x450000; +} + +static void +Opcode_l8ui_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_l8ui_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10450000; +} + +static void +Opcode_l8ui_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101b0000; + slotbuf[1] = 0; +} + +static void +Opcode_l8ui_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_l8ui_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660000; +} + +static void +Opcode_l8ui_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_l8ui_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8076; +} + +static void +Opcode_loop_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8380070; + slotbuf[1] = 0; +} + +static void +Opcode_loop_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1130060; +} + +static void +Opcode_loop_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_loop_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f0020; +} + +static void +Opcode_loop_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0000; +} + +static void +Opcode_loop_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230000; + slotbuf[1] = 0; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9076; +} + +static void +Opcode_loopnez_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a0070; + slotbuf[1] = 0; +} + +static void +Opcode_loopnez_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1110080; +} + +static void +Opcode_loopnez_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0020; +} + +static void +Opcode_loopnez_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830080; +} + +static void +Opcode_loopnez_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0020; +} + +static void +Opcode_loopnez_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230002; + slotbuf[1] = 0; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa076; +} + +static void +Opcode_loopgtz_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8390070; + slotbuf[1] = 0; +} + +static void +Opcode_loopgtz_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1130070; +} + +static void +Opcode_loopgtz_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0010; +} + +static void +Opcode_loopgtz_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f0030; +} + +static void +Opcode_loopgtz_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0010; +} + +static void +Opcode_loopgtz_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230001; + slotbuf[1] = 0; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_movi_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107d0000; + slotbuf[1] = 0; +} + +static void +Opcode_movi_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_movi_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050000; +} + +static void +Opcode_movi_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144000; +} + +static void +Opcode_movi_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e0000; +} + +static void +Opcode_movi_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144000; +} + +static void +Opcode_movi_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d0000; +} + +static void +Opcode_movi_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_movi_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0000; +} + +static void +Opcode_movi_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_movi_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101f0000; + slotbuf[1] = 0; +} + +static void +Opcode_movi_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_movi_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_movi_Slot_f5_s3_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_movi_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_movi_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c000; +} + +static void +Opcode_movi_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_movi_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720000; +} + +static void +Opcode_movi_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d0000; +} + +static void +Opcode_movi_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_moveqz_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109d7000; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d1000; +} + +static void +Opcode_moveqz_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145e000; +} + +static void +Opcode_moveqz_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x243000; +} + +static void +Opcode_moveqz_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59f000; +} + +static void +Opcode_moveqz_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x244000; +} + +static void +Opcode_moveqz_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xadf000; +} + +static void +Opcode_moveqz_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x182000; +} + +static void +Opcode_moveqz_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d6000; +} + +static void +Opcode_moveqz_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x182000; +} + +static void +Opcode_moveqz_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1020d000; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d000; +} + +static void +Opcode_moveqz_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_moveqz_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d000; +} + +static void +Opcode_moveqz_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf000; +} + +static void +Opcode_moveqz_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc000; +} + +static void +Opcode_moveqz_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7fc000; +} + +static void +Opcode_moveqz_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c6000; +} + +static void +Opcode_moveqz_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa45000; +} + +static void +Opcode_moveqz_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a1000; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_movnez_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109de000; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f3000; +} + +static void +Opcode_movnez_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1476000; +} + +static void +Opcode_movnez_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x246000; +} + +static void +Opcode_movnez_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a5000; +} + +static void +Opcode_movnez_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x247000; +} + +static void +Opcode_movnez_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae6000; +} + +static void +Opcode_movnez_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x185000; +} + +static void +Opcode_movnez_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d5000; +} + +static void +Opcode_movnez_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x185000; +} + +static void +Opcode_movnez_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10210000; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_movnez_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_movnez_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_movnez_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb4000; +} + +static void +Opcode_movnez_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb000; +} + +static void +Opcode_movnez_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7fb000; +} + +static void +Opcode_movnez_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x658000; +} + +static void +Opcode_movnez_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4a000; +} + +static void +Opcode_movnez_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4000; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_movltz_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109db000; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3000; +} + +static void +Opcode_movltz_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x146e000; +} + +static void +Opcode_movltz_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x245000; +} + +static void +Opcode_movltz_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a3000; +} + +static void +Opcode_movltz_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x246000; +} + +static void +Opcode_movltz_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae3000; +} + +static void +Opcode_movltz_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x184000; +} + +static void +Opcode_movltz_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d3000; +} + +static void +Opcode_movltz_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x184000; +} + +static void +Opcode_movltz_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1020f000; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f000; +} + +static void +Opcode_movltz_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_movltz_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f000; +} + +static void +Opcode_movltz_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb2000; +} + +static void +Opcode_movltz_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b9000; +} + +static void +Opcode_movltz_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f9000; +} + +static void +Opcode_movltz_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c7000; +} + +static void +Opcode_movltz_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa48000; +} + +static void +Opcode_movltz_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a3000; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_movgez_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109da000; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f1000; +} + +static void +Opcode_movgez_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1466000; +} + +static void +Opcode_movgez_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x244000; +} + +static void +Opcode_movgez_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a1000; +} + +static void +Opcode_movgez_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x245000; +} + +static void +Opcode_movgez_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae2000; +} + +static void +Opcode_movgez_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x183000; +} + +static void +Opcode_movgez_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d1000; +} + +static void +Opcode_movgez_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x183000; +} + +static void +Opcode_movgez_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1020e000; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e000; +} + +static void +Opcode_movgez_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_movgez_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e000; +} + +static void +Opcode_movgez_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_movgez_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be000; +} + +static void +Opcode_movgez_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7fe000; +} + +static void +Opcode_movgez_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x747000; +} + +static void +Opcode_movgez_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa47000; +} + +static void +Opcode_movgez_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2000; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_neg_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a38001; + slotbuf[1] = 0; +} + +static void +Opcode_neg_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc00a; +} + +static void +Opcode_neg_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1465001; +} + +static void +Opcode_neg_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54800f; +} + +static void +Opcode_neg_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0c001; +} + +static void +Opcode_neg_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e8001; +} + +static void +Opcode_neg_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10222010; + slotbuf[1] = 0; +} + +static void +Opcode_neg_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b000; +} + +static void +Opcode_neg_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b600d; +} + +static void +Opcode_neg_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa59001; +} + +static void +Opcode_neg_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2002; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_abs_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a38000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c010; +} + +static void +Opcode_abs_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1465000; +} + +static void +Opcode_abs_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54800e; +} + +static void +Opcode_abs_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0c000; +} + +static void +Opcode_abs_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e8000; +} + +static void +Opcode_abs_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8007; +} + +static void +Opcode_abs_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10222000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000; +} + +static void +Opcode_abs_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c000; +} + +static void +Opcode_abs_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b600c; +} + +static void +Opcode_abs_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa59000; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f0; +} + +static void +Opcode_nop_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a222f5; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4704; +} + +static void +Opcode_nop_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26820d; +} + +static void +Opcode_nop_Slot_f0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305c0016; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1502655; +} + +static void +Opcode_nop_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280514; +} + +static void +Opcode_nop_Slot_f1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf518e4; +} + +static void +Opcode_nop_Slot_f1_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000131; +} + +static void +Opcode_nop_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x602335; +} + +static void +Opcode_nop_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280514; +} + +static void +Opcode_nop_Slot_f2_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e69883; +} + +static void +Opcode_nop_Slot_f2_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800031; +} + +static void +Opcode_nop_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x833ad1; +} + +static void +Opcode_nop_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0114; +} + +static void +Opcode_nop_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000f; +} + +static void +Opcode_nop_Slot_f3_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9810238; +} + +static void +Opcode_nop_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a8180; +} + +static void +Opcode_nop_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f3475; +} + +static void +Opcode_nop_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198514; +} + +static void +Opcode_nop_Slot_f4_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000c; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_f4_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01e042; +} + +static void +Opcode_nop_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10223205; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac030; +} + +static void +Opcode_nop_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d001; +} + +static void +Opcode_nop_Slot_f5_s3_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20100; +} + +static void +Opcode_nop_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b031; +} + +static void +Opcode_nop_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2004; +} + +static void +Opcode_nop_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15400b; +} + +static void +Opcode_nop_Slot_f11_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd830e2; +} + +static void +Opcode_nop_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8140; +} + +static void +Opcode_nop_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x852325; +} + +static void +Opcode_nop_Slot_n1_s1_none_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_nop_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65b005; +} + +static void +Opcode_nop_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9fb2f1; +} + +static void +Opcode_nop_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8704; +} + +static void +Opcode_nop_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8225; +} + +static void +Opcode_nop_Slot_n0_s1_none_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_nop_Slot_n0_s2_none_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_nop_Slot_n0_s3_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800381; +} + +static void +Opcode_l32ex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf14000; +} + +static void +Opcode_s32ex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf15000; +} + +static void +Opcode_getex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40a000; +} + +static void +Opcode_clrex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3120; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002; +} + +static void +Opcode_s16i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700000; + slotbuf[1] = 0; +} + +static void +Opcode_s16i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_s16i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x460000; +} + +static void +Opcode_s16i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_s16i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10460000; +} + +static void +Opcode_s16i_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101c0000; + slotbuf[1] = 0; +} + +static void +Opcode_s16i_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x670000; +} + +static void +Opcode_s16i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_s32i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10710000; + slotbuf[1] = 0; +} + +static void +Opcode_s32i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf90000; +} + +static void +Opcode_s32i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x470000; +} + +static void +Opcode_s32i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x710000; +} + +static void +Opcode_s32i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10470000; +} + +static void +Opcode_s32i_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101d0000; + slotbuf[1] = 0; +} + +static void +Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_s8i_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10720000; + slotbuf[1] = 0; +} + +static void +Opcode_s8i_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0000; +} + +static void +Opcode_s8i_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_s8i_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720000; +} + +static void +Opcode_s8i_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480000; +} + +static void +Opcode_s8i_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101e0000; + slotbuf[1] = 0; +} + +static void +Opcode_s8i_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ssr_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a36c50; + slotbuf[1] = 0; +} + +static void +Opcode_ssr_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1113ad0; +} + +static void +Opcode_ssr_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x604320; +} + +static void +Opcode_ssr_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0ac50; +} + +static void +Opcode_ssr_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f1170; +} + +static void +Opcode_ssr_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10223204; + slotbuf[1] = 0; +} + +static void +Opcode_ssr_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000b; +} + +static void +Opcode_ssr_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8234e0; +} + +static void +Opcode_ssr_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f39f0; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401000; +} + +static void +Opcode_ssl_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a36b50; + slotbuf[1] = 0; +} + +static void +Opcode_ssl_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11137d0; +} + +static void +Opcode_ssl_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x602320; +} + +static void +Opcode_ssl_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0ab50; +} + +static void +Opcode_ssl_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f3370; +} + +static void +Opcode_ssl_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10223203; + slotbuf[1] = 0; +} + +static void +Opcode_ssl_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8233e0; +} + +static void +Opcode_ssl_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f3ef0; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402000; +} + +static void +Opcode_ssa8l_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a36a50; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8l_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11136d0; +} + +static void +Opcode_ssa8l_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600320; +} + +static void +Opcode_ssa8l_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0aa50; +} + +static void +Opcode_ssa8l_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f3270; +} + +static void +Opcode_ssa8l_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10223202; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8l_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8232e0; +} + +static void +Opcode_ssa8l_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f3cf0; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403000; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_ssai_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a36850; + slotbuf[1] = 0; +} + +static void +Opcode_ssai_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11132d0; +} + +static void +Opcode_ssai_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54a01c; +} + +static void +Opcode_ssai_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0a850; +} + +static void +Opcode_ssai_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f1270; +} + +static void +Opcode_ssai_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10223200; + slotbuf[1] = 0; +} + +static void +Opcode_ssai_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8230e0; +} + +static void +Opcode_ssai_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f38f0; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_sll_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a34050; + slotbuf[1] = 0; +} + +static void +Opcode_sll_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc040; +} + +static void +Opcode_sll_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350000; +} + +static void +Opcode_sll_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11110d0; +} + +static void +Opcode_sll_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x286020; +} + +static void +Opcode_sll_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0070; +} + +static void +Opcode_sll_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x286020; +} + +static void +Opcode_sll_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb08050; +} + +static void +Opcode_sll_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa080; +} + +static void +Opcode_sll_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1000; +} + +static void +Opcode_sll_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0070; +} + +static void +Opcode_sll_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac040; +} + +static void +Opcode_sll_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230003; + slotbuf[1] = 0; +} + +static void +Opcode_sll_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad000; +} + +static void +Opcode_sll_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d000; +} + +static void +Opcode_sll_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c000; +} + +static void +Opcode_sll_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0010; +} + +static void +Opcode_sll_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000; +} + +static void +Opcode_sll_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d20e0; +} + +static void +Opcode_sll_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220e0; +} + +static void +Opcode_sll_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75a000; +} + +static void +Opcode_sll_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f10f0; +} + +static void +Opcode_sll_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cd010; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_src_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a1f000; + slotbuf[1] = 0; +} + +static void +Opcode_src_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f9000; +} + +static void +Opcode_src_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b6000; +} + +static void +Opcode_src_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf7000; +} + +static void +Opcode_src_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105df000; +} + +static void +Opcode_src_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10219000; + slotbuf[1] = 0; +} + +static void +Opcode_src_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000; +} + +static void +Opcode_src_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103000; +} + +static void +Opcode_src_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x817000; +} + +static void +Opcode_src_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa56000; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_srl_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a38003; + slotbuf[1] = 0; +} + +static void +Opcode_srl_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cd00a; +} + +static void +Opcode_srl_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36c010; +} + +static void +Opcode_srl_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1465003; +} + +static void +Opcode_srl_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x251001; +} + +static void +Opcode_srl_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54900f; +} + +static void +Opcode_srl_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282009; +} + +static void +Opcode_srl_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0c003; +} + +static void +Opcode_srl_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1001; +} + +static void +Opcode_srl_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00a0; +} + +static void +Opcode_srl_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e8003; +} + +static void +Opcode_srl_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8008; +} + +static void +Opcode_srl_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10222030; + slotbuf[1] = 0; +} + +static void +Opcode_srl_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac020; +} + +static void +Opcode_srl_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b020; +} + +static void +Opcode_srl_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b010; +} + +static void +Opcode_srl_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb001; +} + +static void +Opcode_srl_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c040; +} + +static void +Opcode_srl_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca001; +} + +static void +Opcode_srl_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b600f; +} + +static void +Opcode_srl_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65c040; +} + +static void +Opcode_srl_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa59003; +} + +static void +Opcode_srl_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3002; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_sra_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a38002; + slotbuf[1] = 0; +} + +static void +Opcode_sra_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc00b; +} + +static void +Opcode_sra_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ec010; +} + +static void +Opcode_sra_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1465002; +} + +static void +Opcode_sra_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x251000; +} + +static void +Opcode_sra_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54900e; +} + +static void +Opcode_sra_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x282008; +} + +static void +Opcode_sra_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0c002; +} + +static void +Opcode_sra_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1000; +} + +static void +Opcode_sra_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0080; +} + +static void +Opcode_sra_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e8002; +} + +static void +Opcode_sra_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9007; +} + +static void +Opcode_sra_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10222020; + slotbuf[1] = 0; +} + +static void +Opcode_sra_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac010; +} + +static void +Opcode_sra_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b010; +} + +static void +Opcode_sra_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b000; +} + +static void +Opcode_sra_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb000; +} + +static void +Opcode_sra_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c020; +} + +static void +Opcode_sra_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca000; +} + +static void +Opcode_sra_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b600e; +} + +static void +Opcode_sra_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa59002; +} + +static void +Opcode_sra_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2003; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_slli_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1096a000; + slotbuf[1] = 0; +} + +static void +Opcode_slli_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_slli_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x256000; +} + +static void +Opcode_slli_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1382000; +} + +static void +Opcode_slli_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca000; +} + +static void +Opcode_slli_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57c000; +} + +static void +Opcode_slli_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21c000; +} + +static void +Opcode_slli_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6a000; +} + +static void +Opcode_slli_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_slli_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x152000; +} + +static void +Opcode_slli_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ac000; +} + +static void +Opcode_slli_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_slli_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200000; + slotbuf[1] = 0; +} + +static void +Opcode_slli_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x92000; +} + +static void +Opcode_slli_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32000; +} + +static void +Opcode_slli_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x152000; +} + +static void +Opcode_slli_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000; +} + +static void +Opcode_slli_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_slli_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_slli_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e0000; +} + +static void +Opcode_slli_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa24000; +} + +static void +Opcode_slli_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_srai_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109ca000; + slotbuf[1] = 0; +} + +static void +Opcode_srai_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16e000; +} + +static void +Opcode_srai_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254000; +} + +static void +Opcode_srai_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c0000; +} + +static void +Opcode_srai_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x238000; +} + +static void +Opcode_srai_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x592000; +} + +static void +Opcode_srai_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x238000; +} + +static void +Opcode_srai_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaca000; +} + +static void +Opcode_srai_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x176000; +} + +static void +Opcode_srai_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_srai_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c8000; +} + +static void +Opcode_srai_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x176000; +} + +static void +Opcode_srai_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10202000; + slotbuf[1] = 0; +} + +static void +Opcode_srai_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_srai_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_srai_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_srai_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2000; +} + +static void +Opcode_srai_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_srai_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae000; +} + +static void +Opcode_srai_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f6000; +} + +static void +Opcode_srai_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3a000; +} + +static void +Opcode_srai_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x196000; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_srli_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a2f000; + slotbuf[1] = 0; +} + +static void +Opcode_srli_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca000; +} + +static void +Opcode_srli_Slot_f0_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x357000; +} + +static void +Opcode_srli_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145f000; +} + +static void +Opcode_srli_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250000; +} + +static void +Opcode_srli_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5be000; +} + +static void +Opcode_srli_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x251000; +} + +static void +Opcode_srli_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0d000; +} + +static void +Opcode_srli_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18f000; +} + +static void +Opcode_srli_Slot_f3_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000; +} + +static void +Opcode_srli_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e7000; +} + +static void +Opcode_srli_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_srli_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10221000; + slotbuf[1] = 0; +} + +static void +Opcode_srli_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000; +} + +static void +Opcode_srli_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x45000; +} + +static void +Opcode_srli_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x164000; +} + +static void +Opcode_srli_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9000; +} + +static void +Opcode_srli_Slot_f11_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_srli_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_srli_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81f000; +} + +static void +Opcode_srli_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5e000; +} + +static void +Opcode_srli_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1af000; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d0; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2010; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610100; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610200; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610300; +} + +static void +Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36100; +} + +static void +Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136100; +} + +static void +Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616100; +} + +static void +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30500; +} + +static void +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130500; +} + +static void +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610500; +} + +static void +Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e600; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e600; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e600; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b100; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b100; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b100; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d100; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d100; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d100; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b200; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b200; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b200; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d200; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d200; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d200; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b300; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b300; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b300; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d300; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d300; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d300; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b400; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b400; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b400; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d400; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d400; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c200; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c200; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c300; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c300; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c300; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c400; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c400; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ee00; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee00; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ee00; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e800; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e800; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e800; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3eb00; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e700; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e700; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e700; +} + +static void +Opcode_rsr_mpucfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35c00; +} + +static void +Opcode_wsr_mpucfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135c00; +} + +static void +Opcode_rsr_gserr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37400; +} + +static void +Opcode_wsr_gserr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137400; +} + +static void +Opcode_xsr_gserr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x617400; +} + +static void +Opcode_salt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720000; +} + +static void +Opcode_salt_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a1e000; + slotbuf[1] = 0; +} + +static void +Opcode_salt_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f2000; +} + +static void +Opcode_salt_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f1000; +} + +static void +Opcode_salt_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x248000; +} + +static void +Opcode_salt_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b2000; +} + +static void +Opcode_salt_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x249000; +} + +static void +Opcode_salt_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf3000; +} + +static void +Opcode_salt_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187000; +} + +static void +Opcode_salt_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105db000; +} + +static void +Opcode_salt_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187000; +} + +static void +Opcode_salt_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10217000; + slotbuf[1] = 0; +} + +static void +Opcode_salt_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2000; +} + +static void +Opcode_salt_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000; +} + +static void +Opcode_salt_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x162000; +} + +static void +Opcode_salt_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb8000; +} + +static void +Opcode_salt_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_salt_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x813000; +} + +static void +Opcode_salt_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x758000; +} + +static void +Opcode_salt_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa52000; +} + +static void +Opcode_salt_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6000; +} + +static void +Opcode_saltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620000; +} + +static void +Opcode_saltu_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a1d000; + slotbuf[1] = 0; +} + +static void +Opcode_saltu_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8000; +} + +static void +Opcode_saltu_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f8000; +} + +static void +Opcode_saltu_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x249000; +} + +static void +Opcode_saltu_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b4000; +} + +static void +Opcode_saltu_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24a000; +} + +static void +Opcode_saltu_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf6000; +} + +static void +Opcode_saltu_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_saltu_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105dd000; +} + +static void +Opcode_saltu_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_saltu_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10218000; + slotbuf[1] = 0; +} + +static void +Opcode_saltu_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3000; +} + +static void +Opcode_saltu_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x43000; +} + +static void +Opcode_saltu_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x163000; +} + +static void +Opcode_saltu_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba000; +} + +static void +Opcode_saltu_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c2000; +} + +static void +Opcode_saltu_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x815000; +} + +static void +Opcode_saltu_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d8000; +} + +static void +Opcode_saltu_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa54000; +} + +static void +Opcode_saltu_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a7000; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_mul16u_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a18000; + slotbuf[1] = 0; +} + +static void +Opcode_mul16u_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0000; +} + +static void +Opcode_mul16u_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e0000; +} + +static void +Opcode_mul16u_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a9000; +} + +static void +Opcode_mul16u_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaea000; +} + +static void +Opcode_mul16u_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d8000; +} + +static void +Opcode_mul16u_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10212000; + slotbuf[1] = 0; +} + +static void +Opcode_mul16u_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7ff000; +} + +static void +Opcode_mul16u_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4e000; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_mul16s_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109df000; + slotbuf[1] = 0; +} + +static void +Opcode_mul16s_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000; +} + +static void +Opcode_mul16s_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x147e000; +} + +static void +Opcode_mul16s_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a7000; +} + +static void +Opcode_mul16s_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae7000; +} + +static void +Opcode_mul16s_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d7000; +} + +static void +Opcode_mul16s_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10211000; + slotbuf[1] = 0; +} + +static void +Opcode_mul16s_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7fd000; +} + +static void +Opcode_mul16s_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4c000; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_mull_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a1a000; + slotbuf[1] = 0; +} + +static void +Opcode_mull_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e1000; +} + +static void +Opcode_mull_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5ab000; +} + +static void +Opcode_mull_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaeb000; +} + +static void +Opcode_mull_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105da000; +} + +static void +Opcode_mull_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10213000; + slotbuf[1] = 0; +} + +static void +Opcode_mull_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_mull_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa49000; +} + +static void +Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa20000; +} + +static void +Opcode_muluh_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a1b000; + slotbuf[1] = 0; +} + +static void +Opcode_muluh_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e9000; +} + +static void +Opcode_muluh_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5af000; +} + +static void +Opcode_muluh_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaef000; +} + +static void +Opcode_muluh_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105de000; +} + +static void +Opcode_muluh_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10215000; + slotbuf[1] = 0; +} + +static void +Opcode_muluh_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x814000; +} + +static void +Opcode_muluh_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4d000; +} + +static void +Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb20000; +} + +static void +Opcode_mulsh_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a19000; + slotbuf[1] = 0; +} + +static void +Opcode_mulsh_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e8000; +} + +static void +Opcode_mulsh_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5ad000; +} + +static void +Opcode_mulsh_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaee000; +} + +static void +Opcode_mulsh_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105dc000; +} + +static void +Opcode_mulsh_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10214000; + slotbuf[1] = 0; +} + +static void +Opcode_mulsh_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x812000; +} + +static void +Opcode_mulsh_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4b000; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3010; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e200; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e200; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e300; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e400; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e400; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02d; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619000; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a000; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616000; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e900; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e900; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e900; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ec00; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec00; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ec00; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed00; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ed00; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ed00; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36800; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136800; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616800; +} + +static void +Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e0; +} + +static void +Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f0; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e000; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e010; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135900; +} + +static void +Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000; +} + +static void +Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76; +} + +static void +Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1076; +} + +static void +Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30000; +} + +static void +Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30000; +} + +static void +Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30400; +} + +static void +Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130400; +} + +static void +Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610400; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ea00; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea00; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ea00; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f000; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f100; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f100; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f100; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c2; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e2; +} + +static void +Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70d2; +} + +static void +Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270d2; +} + +static void +Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370d2; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f2; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10000; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf12000; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf11000; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13000; +} + +static void +Opcode_wsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136200; +} + +static void +Opcode_rsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36200; +} + +static void +Opcode_xsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616200; +} + +static void +Opcode_rptlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50b000; +} + +static void +Opcode_pptlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50d000; +} + +static void +Opcode_rptlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50f000; +} + +static void +Opcode_wptlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50e000; +} + +static void +Opcode_rsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35a00; +} + +static void +Opcode_wsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135a00; +} + +static void +Opcode_xsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615a00; +} + +static void +Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e000; +} + +static void +Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_clamps_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a2b000; + slotbuf[1] = 0; +} + +static void +Opcode_clamps_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1457000; +} + +static void +Opcode_clamps_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5ba000; +} + +static void +Opcode_clamps_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa05000; +} + +static void +Opcode_clamps_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e3000; +} + +static void +Opcode_clamps_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18e000; +} + +static void +Opcode_clamps_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1021f000; + slotbuf[1] = 0; +} + +static void +Opcode_clamps_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000; +} + +static void +Opcode_clamps_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81b000; +} + +static void +Opcode_clamps_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6da000; +} + +static void +Opcode_clamps_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5a000; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_min_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109d3000; + slotbuf[1] = 0; +} + +static void +Opcode_min_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f8000; +} + +static void +Opcode_min_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144e000; +} + +static void +Opcode_min_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x241000; +} + +static void +Opcode_min_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59b000; +} + +static void +Opcode_min_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x242000; +} + +static void +Opcode_min_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xadb000; +} + +static void +Opcode_min_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_min_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d2000; +} + +static void +Opcode_min_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_min_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1020b000; + slotbuf[1] = 0; +} + +static void +Opcode_min_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b000; +} + +static void +Opcode_min_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_min_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000; +} + +static void +Opcode_min_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab000; +} + +static void +Opcode_min_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8000; +} + +static void +Opcode_min_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f8000; +} + +static void +Opcode_min_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c5000; +} + +static void +Opcode_min_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa41000; +} + +static void +Opcode_min_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19f000; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_max_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a17000; + slotbuf[1] = 0; +} + +static void +Opcode_max_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e8000; +} + +static void +Opcode_max_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d9000; +} + +static void +Opcode_max_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23f000; +} + +static void +Opcode_max_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59e000; +} + +static void +Opcode_max_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_max_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad7000; +} + +static void +Opcode_max_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e000; +} + +static void +Opcode_max_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105cf000; +} + +static void +Opcode_max_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e000; +} + +static void +Opcode_max_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10209000; + slotbuf[1] = 0; +} + +static void +Opcode_max_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x99000; +} + +static void +Opcode_max_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_max_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000; +} + +static void +Opcode_max_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae000; +} + +static void +Opcode_max_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b5000; +} + +static void +Opcode_max_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80d000; +} + +static void +Opcode_max_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c4000; +} + +static void +Opcode_max_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa44000; +} + +static void +Opcode_max_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19d000; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_minu_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109d6000; + slotbuf[1] = 0; +} + +static void +Opcode_minu_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f9000; +} + +static void +Opcode_minu_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1456000; +} + +static void +Opcode_minu_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x242000; +} + +static void +Opcode_minu_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59d000; +} + +static void +Opcode_minu_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x243000; +} + +static void +Opcode_minu_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xade000; +} + +static void +Opcode_minu_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x181000; +} + +static void +Opcode_minu_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d4000; +} + +static void +Opcode_minu_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x181000; +} + +static void +Opcode_minu_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1020c000; + slotbuf[1] = 0; +} + +static void +Opcode_minu_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000; +} + +static void +Opcode_minu_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_minu_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c000; +} + +static void +Opcode_minu_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad000; +} + +static void +Opcode_minu_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba000; +} + +static void +Opcode_minu_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7fa000; +} + +static void +Opcode_minu_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x746000; +} + +static void +Opcode_minu_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa43000; +} + +static void +Opcode_minu_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_maxu_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109d2000; + slotbuf[1] = 0; +} + +static void +Opcode_maxu_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e9000; +} + +static void +Opcode_maxu_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1446000; +} + +static void +Opcode_maxu_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_maxu_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x599000; +} + +static void +Opcode_maxu_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x241000; +} + +static void +Opcode_maxu_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xada000; +} + +static void +Opcode_maxu_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f000; +} + +static void +Opcode_maxu_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d0000; +} + +static void +Opcode_maxu_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f000; +} + +static void +Opcode_maxu_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1020a000; + slotbuf[1] = 0; +} + +static void +Opcode_maxu_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a000; +} + +static void +Opcode_maxu_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_maxu_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000; +} + +static void +Opcode_maxu_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9000; +} + +static void +Opcode_maxu_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7000; +} + +static void +Opcode_maxu_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80f000; +} + +static void +Opcode_maxu_Slot_n1_s2_mul_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x745000; +} + +static void +Opcode_maxu_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa46000; +} + +static void +Opcode_maxu_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19e000; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e000; +} + +static void +Opcode_nsa_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a54200; + slotbuf[1] = 0; +} + +static void +Opcode_nsa_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4500; +} + +static void +Opcode_nsa_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514400; +} + +static void +Opcode_nsa_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600200; +} + +static void +Opcode_nsa_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d7c00; +} + +static void +Opcode_nsa_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10610100; +} + +static void +Opcode_nsa_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10223000; + slotbuf[1] = 0; +} + +static void +Opcode_nsa_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c000; +} + +static void +Opcode_nsa_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x850200; +} + +static void +Opcode_nsa_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f8c00; +} + +static void +Opcode_nsa_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8500; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f000; +} + +static void +Opcode_nsau_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a56200; + slotbuf[1] = 0; +} + +static void +Opcode_nsau_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d4500; +} + +static void +Opcode_nsau_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516400; +} + +static void +Opcode_nsau_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x602200; +} + +static void +Opcode_nsau_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d7d00; +} + +static void +Opcode_nsau_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10612100; +} + +static void +Opcode_nsau_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10223100; + slotbuf[1] = 0; +} + +static void +Opcode_nsau_Slot_f5_s2_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c100; +} + +static void +Opcode_nsau_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x852200; +} + +static void +Opcode_nsau_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f8e00; +} + +static void +Opcode_nsau_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba500; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_sext_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a2d000; + slotbuf[1] = 0; +} + +static void +Opcode_sext_Slot_f0_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c3000; +} + +static void +Opcode_sext_Slot_f1_s0_ldstalu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145d000; +} + +static void +Opcode_sext_Slot_f1_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24f000; +} + +static void +Opcode_sext_Slot_f2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5bc000; +} + +static void +Opcode_sext_Slot_f2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250000; +} + +static void +Opcode_sext_Slot_f3_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa09000; +} + +static void +Opcode_sext_Slot_f3_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18e000; +} + +static void +Opcode_sext_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e5000; +} + +static void +Opcode_sext_Slot_f4_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18f000; +} + +static void +Opcode_sext_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10220000; + slotbuf[1] = 0; +} + +static void +Opcode_sext_Slot_f5_s1_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab000; +} + +static void +Opcode_sext_Slot_f11_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a000; +} + +static void +Opcode_sext_Slot_f11_s1_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb7000; +} + +static void +Opcode_sext_Slot_n0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c7000; +} + +static void +Opcode_sext_Slot_n1_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81d000; +} + +static void +Opcode_sext_Slot_n2_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5c000; +} + +static void +Opcode_sext_Slot_n2_s1_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ad000; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb002; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36300; +} + +static void +Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136300; +} + +static void +Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616300; +} + +static void +Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20000; +} + +static void +Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf20000; +} + +static void +Opcode_rsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35f00; +} + +static void +Opcode_wsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135f00; +} + +static void +Opcode_xsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615f00; +} + +static void +Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x406000; +} + +static void +Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x407000; +} + +static void +Opcode_beqz_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000060; + slotbuf[1] = 0; +} + +static void +Opcode_beqz_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000060; +} + +static void +Opcode_beqz_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000006; + slotbuf[1] = 0; +} + +static void +Opcode_bnez_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000360; + slotbuf[1] = 0; +} + +static void +Opcode_bnez_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000360; +} + +static void +Opcode_bnez_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000306; + slotbuf[1] = 0; +} + +static void +Opcode_bgez_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000160; + slotbuf[1] = 0; +} + +static void +Opcode_bgez_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000160; +} + +static void +Opcode_bgez_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000106; + slotbuf[1] = 0; +} + +static void +Opcode_bltz_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000260; + slotbuf[1] = 0; +} + +static void +Opcode_bltz_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000260; +} + +static void +Opcode_bltz_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000206; + slotbuf[1] = 0; +} + +static void +Opcode_beqi_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0; +} + +static void +Opcode_beqi_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_beqi_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0; +} + +static void +Opcode_bnei_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000050; + slotbuf[1] = 0; +} + +static void +Opcode_bnei_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000050; +} + +static void +Opcode_bnei_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000005; + slotbuf[1] = 0; +} + +static void +Opcode_bgei_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000010; + slotbuf[1] = 0; +} + +static void +Opcode_bgei_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000010; +} + +static void +Opcode_bgei_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000001; + slotbuf[1] = 0; +} + +static void +Opcode_blti_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000030; + slotbuf[1] = 0; +} + +static void +Opcode_blti_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000030; +} + +static void +Opcode_blti_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000003; + slotbuf[1] = 0; +} + +static void +Opcode_bgeui_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; + slotbuf[1] = 0; +} + +static void +Opcode_bgeui_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; +} + +static void +Opcode_bgeui_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002; + slotbuf[1] = 0; +} + +static void +Opcode_bltui_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000040; + slotbuf[1] = 0; +} + +static void +Opcode_bltui_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000040; +} + +static void +Opcode_bltui_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000004; + slotbuf[1] = 0; +} + +static void +Opcode_bbci_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_bbci_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_bbci_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_bbsi_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; + slotbuf[1] = 0; +} + +static void +Opcode_bbsi_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_bbsi_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; + slotbuf[1] = 0; +} + +static void +Opcode_beq_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; + slotbuf[1] = 0; +} + +static void +Opcode_beq_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; +} + +static void +Opcode_beq_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; + slotbuf[1] = 0; +} + +static void +Opcode_bne_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00; + slotbuf[1] = 0; +} + +static void +Opcode_bne_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00; +} + +static void +Opcode_bne_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00; + slotbuf[1] = 0; +} + +static void +Opcode_bge_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00; + slotbuf[1] = 0; +} + +static void +Opcode_bge_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00; +} + +static void +Opcode_bge_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00; + slotbuf[1] = 0; +} + +static void +Opcode_blt_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00; + slotbuf[1] = 0; +} + +static void +Opcode_blt_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00; +} + +static void +Opcode_blt_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00; + slotbuf[1] = 0; +} + +static void +Opcode_bgeu_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900; + slotbuf[1] = 0; +} + +static void +Opcode_bgeu_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900; +} + +static void +Opcode_bgeu_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900; + slotbuf[1] = 0; +} + +static void +Opcode_bltu_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00; + slotbuf[1] = 0; +} + +static void +Opcode_bltu_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00; +} + +static void +Opcode_bltu_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00; + slotbuf[1] = 0; +} + +static void +Opcode_bany_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500; + slotbuf[1] = 0; +} + +static void +Opcode_bany_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500; +} + +static void +Opcode_bany_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500; + slotbuf[1] = 0; +} + +static void +Opcode_bnone_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00; + slotbuf[1] = 0; +} + +static void +Opcode_bnone_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00; +} + +static void +Opcode_bnone_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00; + slotbuf[1] = 0; +} + +static void +Opcode_ball_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; + slotbuf[1] = 0; +} + +static void +Opcode_ball_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; +} + +static void +Opcode_ball_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; + slotbuf[1] = 0; +} + +static void +Opcode_bnall_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00; + slotbuf[1] = 0; +} + +static void +Opcode_bnall_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00; +} + +static void +Opcode_bnall_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00; + slotbuf[1] = 0; +} + +static void +Opcode_bbc_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; + slotbuf[1] = 0; +} + +static void +Opcode_bbc_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; +} + +static void +Opcode_bbc_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; + slotbuf[1] = 0; +} + +static void +Opcode_bbs_w15_Slot_f0_s0_ldst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; + slotbuf[1] = 0; +} + +static void +Opcode_bbs_w15_Slot_f4_s0_ld_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; +} + +static void +Opcode_bbs_w15_Slot_f5_s0_base_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; + slotbuf[1] = 0; +} + +static void +Opcode_mtk_andpopc_Slot_f3_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_mtk_andpopc_Slot_f11_s4_alu_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0000; +} + +static void +Opcode_iq_tie2apb_inq0_pop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x362200; +} + +static void +Opcode_iq_tie2apb_inq0_is_ready_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x362100; +} + +static void +Opcode_iq_tie2apb_inq0_nonblocking_peek_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260000; +} + +static void +Opcode_iq_tie2apb_inq0_nonblocking_pop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260100; +} + +static void +Opcode_iq_tie2apb_inq0_blocking_peek_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x362000; +} + +static void +Opcode_oq_tie2apb_outq0_push_read_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360000; +} + +static void +Opcode_oq_tie2apb_outq0_push_write_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x361000; +} + +static void +Opcode_oq_tie2apb_outq0_is_ready_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x362300; +} + +static void +Opcode_oq_tie2apb_outq0_nonblocking_push_read_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_oq_tie2apb_outq0_nonblocking_push_write_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_rur_apb_pipe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30000; +} + +static void +Opcode_wur_apb_pipe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30000; +} + +xtensa_opcode_encode_fn Opcode_ivp_repnx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_repnx16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_repnx16_Slot_f0_s3_alu_encode, Opcode_ivp_repnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_repnx16_Slot_f1_s2_mul_encode, Opcode_ivp_repnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_repnx16_Slot_f2_s2_mul_encode, Opcode_ivp_repnx16_Slot_f2_s3_alu_encode, Opcode_ivp_repnx16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_repnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_repnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_repnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_repnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_selsnx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_selsnx16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_selsnx16_Slot_f0_s3_alu_encode, Opcode_ivp_selsnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_selsnx16_Slot_f1_s2_mul_encode, Opcode_ivp_selsnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_selsnx16_Slot_f2_s2_mul_encode, Opcode_ivp_selsnx16_Slot_f2_s3_alu_encode, Opcode_ivp_selsnx16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_selsnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_selsnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_selsnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_selsnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rep2nx8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_rep2nx8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_rep2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_rep2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_rep2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_rep2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_rep2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_rep2nx8_Slot_f2_s3_alu_encode, Opcode_ivp_rep2nx8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_rep2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rep2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rep2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rep2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sels2nx8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sels2nx8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_sels2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_sels2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_sels2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_sels2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_sels2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_sels2nx8_Slot_f2_s3_alu_encode, Opcode_ivp_sels2nx8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_sels2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_sels2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sels2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sels2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_repn_2x32_encode_fns[] = { + 0, 0, 0, Opcode_ivp_repn_2x32_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_repn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_repn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_repn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_repn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_repn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_repn_2x32_Slot_f2_s3_alu_encode, Opcode_ivp_repn_2x32_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_repn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_repn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_repn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_repn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_selsn_2x32_encode_fns[] = { + 0, 0, 0, Opcode_ivp_selsn_2x32_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_selsn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_selsn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_selsn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_selsn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_selsn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_selsn_2x32_Slot_f2_s3_alu_encode, Opcode_ivp_selsn_2x32_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_selsn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_selsn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_selsn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_selsn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_ext0ib_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ext0ib_Slot_f0_s1_ld_encode, 0, Opcode_ivp_ext0ib_Slot_f0_s3_alu_encode, 0, Opcode_ivp_ext0ib_Slot_f1_s1_ld_encode, 0, Opcode_ivp_ext0ib_Slot_f1_s3_alu_encode, 0, Opcode_ivp_ext0ib_Slot_f2_s1_ld_encode, 0, Opcode_ivp_ext0ib_Slot_f2_s3_alu_encode, 0, Opcode_ivp_ext0ib_Slot_f3_s1_ld_encode, 0, Opcode_ivp_ext0ib_Slot_f3_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ext0ib_Slot_f11_s1_alu_encode, 0, Opcode_ivp_ext0ib_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_ext0ib_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_notb_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_notb_Slot_f0_s1_ld_encode, 0, Opcode_ivp_notb_Slot_f0_s3_alu_encode, 0, Opcode_ivp_notb_Slot_f1_s1_ld_encode, 0, Opcode_ivp_notb_Slot_f1_s3_alu_encode, 0, Opcode_ivp_notb_Slot_f2_s1_ld_encode, 0, Opcode_ivp_notb_Slot_f2_s3_alu_encode, 0, Opcode_ivp_notb_Slot_f3_s1_ld_encode, 0, Opcode_ivp_notb_Slot_f3_s3_alu_encode, 0, 0, Opcode_ivp_notb_Slot_f4_s1_ld_encode, 0, Opcode_ivp_notb_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_notb_Slot_f11_s1_alu_encode, 0, Opcode_ivp_notb_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_notb_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_andb_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_andb_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_andb_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_andb_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_andb_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_andb_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_andb_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_orb_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_orb_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_orb_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_orb_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_orb_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_orb_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_orb_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_xorb_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_xorb_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_xorb_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_xorb_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_xorb_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_xorb_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_xorb_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_andnotb_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_andnotb_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_andnotb_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_andnotb_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_andnotb_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_andnotb_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_andnotb_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mb_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_mb_Slot_f0_s1_ld_encode, 0, Opcode_ivp_mb_Slot_f0_s3_alu_encode, 0, Opcode_ivp_mb_Slot_f1_s1_ld_encode, 0, Opcode_ivp_mb_Slot_f1_s3_alu_encode, 0, Opcode_ivp_mb_Slot_f2_s1_ld_encode, 0, Opcode_ivp_mb_Slot_f2_s3_alu_encode, 0, Opcode_ivp_mb_Slot_f3_s1_ld_encode, 0, Opcode_ivp_mb_Slot_f3_s3_alu_encode, 0, 0, Opcode_ivp_mb_Slot_f4_s1_ld_encode, 0, Opcode_ivp_mb_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_mb_Slot_f11_s1_alu_encode, 0, Opcode_ivp_mb_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_mb_Slot_n2_s1_ld_encode, 0, 0, 0, Opcode_ivp_mb_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltrn_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ltrn_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrn_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrn_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrn_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ltrn_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrn_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrn_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltrni_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ltrni_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrni_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrni_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrni_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ltrni_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrni_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrni_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lbn_i_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_lbn_i_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lbn_i_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_lbn_i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lbn_i_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lbn_ip_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_lbn_ip_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lbn_ip_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_lbn_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lbn_ip_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sbn_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sbn_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sbn_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sbn_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sbn_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sbn_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sbn_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sbn_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sbn_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sbn_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sbn_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sbn_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sbn_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sbn_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsnx16_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsnx16_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsnx16_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsnx16_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsnx16_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsnx16_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsnx16_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsnx16_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsnx16_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsnx16_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsnx16_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsnx16_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsnx16_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsnx16_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsnx16_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsnx16_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsnx16_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsnx16_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsnx16_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsnx16_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsnx16_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsnx16_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsnx16_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsnx16_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsnx16_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsnx16_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsnx16_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsnx16_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movbrbv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_movbrbv_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_movbrbv_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_movbrbv_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_movbrbv_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_movbrbv_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movbrbv_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movbrbv_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_movbvbr_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_movbvbr_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_movbvbr_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_movbvbr_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_movbvbr_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_movbvbr_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movbvbr_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movbvbr_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_joinb_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_joinb_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_joinb_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_joinb_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_joinb_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_joinb_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_joinb_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltrn_2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ltrn_2_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrn_2_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrn_2_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrn_2_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ltrn_2_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrn_2_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrn_2_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltrn_2i_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ltrn_2i_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrn_2i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrn_2i_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrn_2i_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ltrn_2i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrn_2i_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrn_2i_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lbn_2_i_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_lbn_2_i_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lbn_2_i_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_lbn_2_i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lbn_2_i_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lbn_2_ip_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_lbn_2_ip_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lbn_2_ip_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_lbn_2_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lbn_2_ip_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sbn_2_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sbn_2_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sbn_2_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sbn_2_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sbn_2_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sbn_2_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sbn_2_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sbn_2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sbn_2_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sbn_2_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sbn_2_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sbn_2_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sbn_2_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sbn_2_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lv2nx8_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lv2nx8_i_Slot_f0_s0_ldst_encode, Opcode_ivp_lv2nx8_i_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lv2nx8_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lv2nx8_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lv2nx8_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lv2nx8_i_Slot_f3_s0_ldst_encode, Opcode_ivp_lv2nx8_i_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lv2nx8_i_Slot_f4_s0_ld_encode, Opcode_ivp_lv2nx8_i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lv2nx8_i_Slot_n2_s0_ldst_encode, Opcode_ivp_lv2nx8_i_Slot_n2_s1_ld_encode, Opcode_ivp_lv2nx8_i_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lv2nx8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lv2nx8_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lv2nx8_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lv2nx8_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lv2nx8_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lv2nx8_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lv2nx8_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lv2nx8_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lv2nx8_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lv2nx8_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lv2nx8_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lv2nx8_ip_Slot_n2_s1_ld_encode, Opcode_ivp_lv2nx8_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lv2nx8_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lv2nx8_x_Slot_f0_s0_ldst_encode, Opcode_ivp_lv2nx8_x_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lv2nx8_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lv2nx8_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lv2nx8_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lv2nx8_x_Slot_f3_s0_ldst_encode, Opcode_ivp_lv2nx8_x_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lv2nx8_x_Slot_f4_s0_ld_encode, Opcode_ivp_lv2nx8_x_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lv2nx8_x_Slot_n2_s0_ldst_encode, Opcode_ivp_lv2nx8_x_Slot_n2_s1_ld_encode, Opcode_ivp_lv2nx8_x_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lv2nx8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lv2nx8_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lv2nx8_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lv2nx8_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lv2nx8_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lv2nx8_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lv2nx8_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lv2nx8_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lv2nx8_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lv2nx8_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lv2nx8_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lv2nx8_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lv2nx8_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sv2nx8_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sv2nx8_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sv2nx8_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sv2nx8_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sv2nx8_i_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_sv2nx8_i_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sv2nx8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sv2nx8_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sv2nx8_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sv2nx8_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sv2nx8_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_sv2nx8_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sv2nx8_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sv2nx8_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sv2nx8_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sv2nx8_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sv2nx8_x_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_sv2nx8_x_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sv2nx8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sv2nx8_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sv2nx8_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sv2nx8_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sv2nx8_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_sv2nx8_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssnx16_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssnx16_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx16_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssnx16_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx16_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssnx16_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssnx16_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx16_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssnx16_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx16_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssnx16_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssnx16_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx16_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssnx16_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx16_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssnx16_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssnx16_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx16_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssnx16_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx16_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movva16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movva16_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movva16_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movva16_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movva16_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movva16_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movva16_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movvv_encode_fns[] = { + 0, 0, 0, Opcode_ivp_movvv_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_movvv_Slot_f0_s3_alu_encode, Opcode_ivp_movvv_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_movvv_Slot_f1_s2_mul_encode, Opcode_ivp_movvv_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_movvv_Slot_f2_s2_mul_encode, Opcode_ivp_movvv_Slot_f2_s3_alu_encode, Opcode_ivp_movvv_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_movvv_Slot_f3_s3_alu_encode, Opcode_ivp_movvv_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_movvv_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movvv_Slot_f11_s3_alu_encode, Opcode_ivp_movvv_Slot_f11_s4_alu_encode, Opcode_ivp_movvv_Slot_n1_s0_ldst_encode, 0, Opcode_ivp_movvv_Slot_n1_s2_mul_encode, Opcode_ivp_movvv_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_movvv_Slot_n0_s0_ldst_encode, 0, 0, Opcode_ivp_movvv_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sllinx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sllinx16_Slot_f0_s3_alu_encode, 0, 0, Opcode_ivp_sllinx16_Slot_f1_s2_mul_encode, Opcode_ivp_sllinx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_sllinx16_Slot_f2_s2_mul_encode, Opcode_ivp_sllinx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_sllinx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_sllinx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sllinx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sllinx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_slsinx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_slsinx16_Slot_f0_s3_alu_encode, 0, 0, Opcode_ivp_slsinx16_Slot_f1_s2_mul_encode, Opcode_ivp_slsinx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_slsinx16_Slot_f2_s2_mul_encode, Opcode_ivp_slsinx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsinx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_slsinx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slsinx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slsinx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srainx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_srainx16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_srainx16_Slot_f0_s3_alu_encode, Opcode_ivp_srainx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_srainx16_Slot_f1_s2_mul_encode, Opcode_ivp_srainx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_srainx16_Slot_f2_s2_mul_encode, Opcode_ivp_srainx16_Slot_f2_s3_alu_encode, Opcode_ivp_srainx16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_srainx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srainx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srainx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srainx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srlinx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_srlinx16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_srlinx16_Slot_f0_s3_alu_encode, Opcode_ivp_srlinx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_srlinx16_Slot_f1_s2_mul_encode, Opcode_ivp_srlinx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_srlinx16_Slot_f2_s2_mul_encode, Opcode_ivp_srlinx16_Slot_f2_s3_alu_encode, Opcode_ivp_srlinx16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_srlinx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srlinx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srlinx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srlinx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sllnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sllnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_sllnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_sllnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_sllnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_sllnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sllnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sllnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srlnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_srlnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_srlnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_srlnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_srlnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srlnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srlnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srlnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_slanx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_slanx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_slanx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_slanx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_slanx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_slanx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slanx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slanx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sranx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sranx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_sranx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_sranx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_sranx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_sranx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sranx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sranx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_slsnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_slsnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_slsnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slsnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slsnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srsnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_srsnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_srsnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_srsnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_srsnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srsnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srsnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srsnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_xor2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_xor2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_xor2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_xor2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_xor2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_xor2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_xor2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_xor2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_xor2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_xor2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_xor2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_xor2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_xor2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_and2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_and2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_and2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_and2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_and2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_and2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_and2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_and2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_and2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_and2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_and2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_and2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_and2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_or2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_or2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_or2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_or2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_or2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_or2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_or2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_or2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_or2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_or2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_or2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_or2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_or2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_not2nx8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_not2nx8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_not2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_not2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_not2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_not2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_not2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_not2nx8_Slot_f2_s3_alu_encode, Opcode_ivp_not2nx8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_not2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_not2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_not2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_not2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_not2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_not2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_addnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_addnx16_Slot_f0_s3_alu_encode, Opcode_ivp_addnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_addnx16_Slot_f1_s2_mul_encode, Opcode_ivp_addnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_addnx16_Slot_f2_s2_mul_encode, Opcode_ivp_addnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_addnx16_Slot_f3_s3_alu_encode, Opcode_ivp_addnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_addnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addnx16_Slot_f11_s3_alu_encode, Opcode_ivp_addnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_subnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_subnx16_Slot_f0_s3_alu_encode, Opcode_ivp_subnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_subnx16_Slot_f1_s2_mul_encode, Opcode_ivp_subnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_subnx16_Slot_f2_s2_mul_encode, Opcode_ivp_subnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_subnx16_Slot_f3_s3_alu_encode, Opcode_ivp_subnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_subnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subnx16_Slot_f11_s3_alu_encode, Opcode_ivp_subnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_negnx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_negnx16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_negnx16_Slot_f0_s3_alu_encode, Opcode_ivp_negnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_negnx16_Slot_f1_s2_mul_encode, Opcode_ivp_negnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_negnx16_Slot_f2_s2_mul_encode, Opcode_ivp_negnx16_Slot_f2_s3_alu_encode, Opcode_ivp_negnx16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_negnx16_Slot_f3_s3_alu_encode, Opcode_ivp_negnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_negnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negnx16_Slot_f11_s3_alu_encode, Opcode_ivp_negnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_minnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_minnx16_Slot_f0_s3_alu_encode, Opcode_ivp_minnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_minnx16_Slot_f1_s2_mul_encode, Opcode_ivp_minnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_minnx16_Slot_f2_s2_mul_encode, Opcode_ivp_minnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_minnx16_Slot_f3_s3_alu_encode, Opcode_ivp_minnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_minnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minnx16_Slot_f11_s3_alu_encode, Opcode_ivp_minnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_minunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_minunx16_Slot_f0_s3_alu_encode, Opcode_ivp_minunx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_minunx16_Slot_f1_s2_mul_encode, Opcode_ivp_minunx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_minunx16_Slot_f2_s2_mul_encode, Opcode_ivp_minunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_minunx16_Slot_f3_s3_alu_encode, Opcode_ivp_minunx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_minunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minunx16_Slot_f11_s3_alu_encode, Opcode_ivp_minunx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_maxnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_maxnx16_Slot_f0_s3_alu_encode, Opcode_ivp_maxnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_maxnx16_Slot_f1_s2_mul_encode, Opcode_ivp_maxnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_maxnx16_Slot_f2_s2_mul_encode, Opcode_ivp_maxnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_maxnx16_Slot_f3_s3_alu_encode, Opcode_ivp_maxnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_maxnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxnx16_Slot_f11_s3_alu_encode, Opcode_ivp_maxnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_maxunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_maxunx16_Slot_f0_s3_alu_encode, Opcode_ivp_maxunx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_maxunx16_Slot_f1_s2_mul_encode, Opcode_ivp_maxunx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_maxunx16_Slot_f2_s2_mul_encode, Opcode_ivp_maxunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_maxunx16_Slot_f3_s3_alu_encode, Opcode_ivp_maxunx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_maxunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxunx16_Slot_f11_s3_alu_encode, Opcode_ivp_maxunx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsgnnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsgnnx16_Slot_f0_s3_alu_encode, Opcode_ivp_mulsgnnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_mulsgnnx16_Slot_f1_s2_mul_encode, Opcode_ivp_mulsgnnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_mulsgnnx16_Slot_f2_s2_mul_encode, Opcode_ivp_mulsgnnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_mulsgnnx16_Slot_f3_s3_alu_encode, Opcode_ivp_mulsgnnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_mulsgnnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsgnnx16_Slot_f11_s3_alu_encode, Opcode_ivp_mulsgnnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsgnnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_nsanx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_nsanx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsanx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsanx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsanx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_nsanx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_nsanx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_nsanx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_nsaunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_nsaunx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsaunx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsaunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsaunx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_nsaunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_nsaunx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_nsaunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_ltnx16_Slot_f0_s2_mul_encode, Opcode_ivp_ltnx16_Slot_f0_s3_alu_encode, Opcode_ivp_ltnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_ltnx16_Slot_f1_s2_mul_encode, Opcode_ivp_ltnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_ltnx16_Slot_f2_s2_mul_encode, Opcode_ivp_ltnx16_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_ltnx16_Slot_f3_s2_mul_encode, Opcode_ivp_ltnx16_Slot_f3_s3_alu_encode, Opcode_ivp_ltnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_ltnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltnx16_Slot_f11_s2_mul_encode, Opcode_ivp_ltnx16_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_ltnx16_Slot_n1_s2_mul_encode, Opcode_ivp_ltnx16_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_ltnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_lenx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_lenx16_Slot_f0_s2_mul_encode, Opcode_ivp_lenx16_Slot_f0_s3_alu_encode, Opcode_ivp_lenx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_lenx16_Slot_f1_s2_mul_encode, Opcode_ivp_lenx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_lenx16_Slot_f2_s2_mul_encode, Opcode_ivp_lenx16_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_lenx16_Slot_f3_s2_mul_encode, Opcode_ivp_lenx16_Slot_f3_s3_alu_encode, Opcode_ivp_lenx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_lenx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_lenx16_Slot_f11_s2_mul_encode, Opcode_ivp_lenx16_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_lenx16_Slot_n1_s2_mul_encode, Opcode_ivp_lenx16_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lenx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_eqnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_eqnx16_Slot_f0_s2_mul_encode, Opcode_ivp_eqnx16_Slot_f0_s3_alu_encode, Opcode_ivp_eqnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_eqnx16_Slot_f1_s2_mul_encode, Opcode_ivp_eqnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_eqnx16_Slot_f2_s2_mul_encode, Opcode_ivp_eqnx16_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_eqnx16_Slot_f3_s2_mul_encode, Opcode_ivp_eqnx16_Slot_f3_s3_alu_encode, Opcode_ivp_eqnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_eqnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_eqnx16_Slot_f11_s2_mul_encode, Opcode_ivp_eqnx16_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_eqnx16_Slot_n1_s2_mul_encode, Opcode_ivp_eqnx16_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_eqnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_neqnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_neqnx16_Slot_f0_s2_mul_encode, Opcode_ivp_neqnx16_Slot_f0_s3_alu_encode, Opcode_ivp_neqnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_neqnx16_Slot_f1_s2_mul_encode, Opcode_ivp_neqnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_neqnx16_Slot_f2_s2_mul_encode, Opcode_ivp_neqnx16_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_neqnx16_Slot_f3_s2_mul_encode, Opcode_ivp_neqnx16_Slot_f3_s3_alu_encode, Opcode_ivp_neqnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_neqnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_neqnx16_Slot_f11_s2_mul_encode, Opcode_ivp_neqnx16_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_neqnx16_Slot_n1_s2_mul_encode, Opcode_ivp_neqnx16_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_neqnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltunx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_ltunx16_Slot_f0_s2_mul_encode, Opcode_ivp_ltunx16_Slot_f0_s3_alu_encode, Opcode_ivp_ltunx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_ltunx16_Slot_f1_s2_mul_encode, Opcode_ivp_ltunx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_ltunx16_Slot_f2_s2_mul_encode, Opcode_ivp_ltunx16_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_ltunx16_Slot_f3_s2_mul_encode, Opcode_ivp_ltunx16_Slot_f3_s3_alu_encode, Opcode_ivp_ltunx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_ltunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltunx16_Slot_f11_s2_mul_encode, Opcode_ivp_ltunx16_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_ltunx16_Slot_n1_s2_mul_encode, Opcode_ivp_ltunx16_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_ltunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_leunx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_leunx16_Slot_f0_s2_mul_encode, Opcode_ivp_leunx16_Slot_f0_s3_alu_encode, Opcode_ivp_leunx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_leunx16_Slot_f1_s2_mul_encode, Opcode_ivp_leunx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_leunx16_Slot_f2_s2_mul_encode, Opcode_ivp_leunx16_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_leunx16_Slot_f3_s2_mul_encode, Opcode_ivp_leunx16_Slot_f3_s3_alu_encode, Opcode_ivp_leunx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_leunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_leunx16_Slot_f11_s2_mul_encode, Opcode_ivp_leunx16_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_leunx16_Slot_n1_s2_mul_encode, Opcode_ivp_leunx16_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_leunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rmaxnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rmaxnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rminnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rminnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rminnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rmaxunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxunx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxunx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxunx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rmaxunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxunx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rminunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rminunx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminunx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminunx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rminunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminunx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rbminnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rbminnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbminnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbminnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbminnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rbminnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rbminnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rbminnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rbmaxnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rbmaxnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbmaxnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbmaxnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbmaxnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rbmaxnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rbmaxnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rbmaxnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bmaxnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxnx16_Slot_f0_s3_alu_encode, Opcode_ivp_bmaxnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bmaxnx16_Slot_f1_s2_mul_encode, Opcode_ivp_bmaxnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bmaxnx16_Slot_f2_s2_mul_encode, Opcode_ivp_bmaxnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bmaxnx16_Slot_f3_s3_alu_encode, Opcode_ivp_bmaxnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bmaxnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxnx16_Slot_f11_s3_alu_encode, Opcode_ivp_bmaxnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bminnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bminnx16_Slot_f0_s3_alu_encode, Opcode_ivp_bminnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bminnx16_Slot_f1_s2_mul_encode, Opcode_ivp_bminnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bminnx16_Slot_f2_s2_mul_encode, Opcode_ivp_bminnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bminnx16_Slot_f3_s3_alu_encode, Opcode_ivp_bminnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bminnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminnx16_Slot_f11_s3_alu_encode, Opcode_ivp_bminnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_mov2nx8t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_mov2nx8t_Slot_f0_s3_alu_encode, Opcode_ivp_mov2nx8t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_mov2nx8t_Slot_f1_s2_mul_encode, Opcode_ivp_mov2nx8t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_mov2nx8t_Slot_f2_s2_mul_encode, Opcode_ivp_mov2nx8t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_mov2nx8t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_mov2nx8t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mov2nx8t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mov2nx8t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulanx16packl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16packl_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16packl_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulanx16packq_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16packq_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16packq_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsnx16packl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsnx16packl_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsnx16packl_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsnx16packq_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsnx16packq_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsnx16packq_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addsnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_addsnx16_Slot_f0_s3_alu_encode, Opcode_ivp_addsnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_addsnx16_Slot_f1_s2_mul_encode, Opcode_ivp_addsnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_addsnx16_Slot_f2_s2_mul_encode, Opcode_ivp_addsnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_addsnx16_Slot_f3_s3_alu_encode, Opcode_ivp_addsnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_addsnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addsnx16_Slot_f11_s3_alu_encode, Opcode_ivp_addsnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addsnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_subsnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_subsnx16_Slot_f0_s3_alu_encode, Opcode_ivp_subsnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_subsnx16_Slot_f1_s2_mul_encode, Opcode_ivp_subsnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_subsnx16_Slot_f2_s2_mul_encode, Opcode_ivp_subsnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_subsnx16_Slot_f3_s3_alu_encode, Opcode_ivp_subsnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_subsnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subsnx16_Slot_f11_s3_alu_encode, Opcode_ivp_subsnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subsnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_negsnx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_negsnx16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_negsnx16_Slot_f0_s3_alu_encode, Opcode_ivp_negsnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_negsnx16_Slot_f1_s2_mul_encode, Opcode_ivp_negsnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_negsnx16_Slot_f2_s2_mul_encode, Opcode_ivp_negsnx16_Slot_f2_s3_alu_encode, Opcode_ivp_negsnx16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_negsnx16_Slot_f3_s3_alu_encode, Opcode_ivp_negsnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_negsnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negsnx16_Slot_f11_s3_alu_encode, Opcode_ivp_negsnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negsnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_lv2nx8t_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lv2nx8t_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lv2nx8t_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lv2nx8t_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lv2nx8t_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lv2nx8t_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lv2nx8t_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lv2nx8t_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lv2nx8t_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lv2nx8t_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lv2nx8t_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lv2nx8t_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lv2nx8t_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lv2nx8t_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lv2nx8t_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lv2nx8t_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lv2nx8t_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sv2nx8t_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sv2nx8t_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sv2nx8t_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sv2nx8t_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sv2nx8t_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sv2nx8t_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sv2nx8t_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sv2nx8t_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sv2nx8t_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sv2nx8t_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sv2nx8t_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sv2nx8t_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sv2nx8t_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sv2nx8t_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sv2nx8t_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sv2nx8t_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sv2nx8t_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddnx16t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddnx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rmaxnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxnx16t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxnx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rmaxnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rminnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rminnx16t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminnx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rminnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rmaxunx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxunx16t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxunx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxunx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxunx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rmaxunx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxunx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxunx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rminunx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rminunx16t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminunx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminunx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminunx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rminunx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminunx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminunx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_addnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_addnx16t_Slot_f0_s3_alu_encode, Opcode_ivp_addnx16t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_addnx16t_Slot_f1_s2_mul_encode, Opcode_ivp_addnx16t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_addnx16t_Slot_f2_s2_mul_encode, Opcode_ivp_addnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_addnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_addnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_subnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_subnx16t_Slot_f0_s3_alu_encode, Opcode_ivp_subnx16t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_subnx16t_Slot_f1_s2_mul_encode, Opcode_ivp_subnx16t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_subnx16t_Slot_f2_s2_mul_encode, Opcode_ivp_subnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_subnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_subnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_negnx16t_encode_fns[] = { + 0, 0, 0, Opcode_ivp_negnx16t_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_negnx16t_Slot_f0_s3_alu_encode, Opcode_ivp_negnx16t_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_negnx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_negnx16t_Slot_f2_s3_alu_encode, Opcode_ivp_negnx16t_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_negnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_negnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_maxnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_maxnx16t_Slot_f0_s3_alu_encode, Opcode_ivp_maxnx16t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_maxnx16t_Slot_f1_s2_mul_encode, Opcode_ivp_maxnx16t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_maxnx16t_Slot_f2_s2_mul_encode, Opcode_ivp_maxnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_maxnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_maxnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_minnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_minnx16t_Slot_f0_s3_alu_encode, Opcode_ivp_minnx16t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_minnx16t_Slot_f1_s2_mul_encode, Opcode_ivp_minnx16t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_minnx16t_Slot_f2_s2_mul_encode, Opcode_ivp_minnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_minnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_minnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_maxunx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_maxunx16t_Slot_f0_s3_alu_encode, Opcode_ivp_maxunx16t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_maxunx16t_Slot_f1_s2_mul_encode, Opcode_ivp_maxunx16t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_maxunx16t_Slot_f2_s2_mul_encode, Opcode_ivp_maxunx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_maxunx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_maxunx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxunx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxunx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_minunx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_minunx16t_Slot_f0_s3_alu_encode, Opcode_ivp_minunx16t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_minunx16t_Slot_f1_s2_mul_encode, Opcode_ivp_minunx16t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_minunx16t_Slot_f2_s2_mul_encode, Opcode_ivp_minunx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_minunx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_minunx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minunx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minunx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulanx16packlt_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16packlt_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulanx16packqt_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16packqt_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addsnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_addsnx16t_Slot_f0_s3_alu_encode, Opcode_ivp_addsnx16t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_addsnx16t_Slot_f1_s2_mul_encode, Opcode_ivp_addsnx16t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_addsnx16t_Slot_f2_s2_mul_encode, Opcode_ivp_addsnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_addsnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_addsnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addsnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addsnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_subsnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_subsnx16t_Slot_f0_s3_alu_encode, Opcode_ivp_subsnx16t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_subsnx16t_Slot_f1_s2_mul_encode, Opcode_ivp_subsnx16t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_subsnx16t_Slot_f2_s2_mul_encode, Opcode_ivp_subsnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_subsnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_subsnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subsnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subsnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_negsnx16t_encode_fns[] = { + 0, 0, 0, Opcode_ivp_negsnx16t_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_negsnx16t_Slot_f0_s3_alu_encode, Opcode_ivp_negsnx16t_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_negsnx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_negsnx16t_Slot_f2_s3_alu_encode, Opcode_ivp_negsnx16t_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_negsnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_negsnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negsnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negsnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_lalign_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lalign_i_Slot_f0_s0_ldst_encode, Opcode_ivp_lalign_i_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lalign_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lalign_i_Slot_f1_s1_ld_encode, 0, 0, Opcode_ivp_lalign_i_Slot_f2_s0_ldst_encode, Opcode_ivp_lalign_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lalign_i_Slot_f3_s0_ldst_encode, Opcode_ivp_lalign_i_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lalign_i_Slot_f4_s0_ld_encode, Opcode_ivp_lalign_i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lalign_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lalign_i_Slot_n2_s0_ldst_encode, Opcode_ivp_lalign_i_Slot_n2_s1_ld_encode, Opcode_ivp_lalign_i_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lalign_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lalign_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lalign_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lalign_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lalign_ip_Slot_f1_s1_ld_encode, 0, 0, Opcode_ivp_lalign_ip_Slot_f2_s0_ldst_encode, Opcode_ivp_lalign_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lalign_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lalign_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lalign_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lalign_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lalign_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lalign_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lalign_ip_Slot_n2_s1_ld_encode, Opcode_ivp_lalign_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_salign_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_salign_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_salign_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_salign_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_salign_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_salign_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_salign_i_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_salign_i_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_salign_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_salign_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_salign_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_salign_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_salign_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_salign_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_salign_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_salign_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_la_pp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_la_pp_Slot_f0_s0_ldst_encode, Opcode_ivp_la_pp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_la_pp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_la_pp_Slot_f1_s1_ld_encode, 0, 0, Opcode_ivp_la_pp_Slot_f2_s0_ldst_encode, Opcode_ivp_la_pp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_la_pp_Slot_f3_s0_ldst_encode, Opcode_ivp_la_pp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_la_pp_Slot_f4_s0_ld_encode, Opcode_ivp_la_pp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_la_pp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_la_pp_Slot_n2_s0_ldst_encode, Opcode_ivp_la_pp_Slot_n2_s1_ld_encode, Opcode_ivp_la_pp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sapos_fp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sapos_fp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sapos_fp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sapos_fp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sapos_fp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sapos_fp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sapos_fp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_sapos_fp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_malign_encode_fns[] = { + 0, 0, 0, Opcode_ivp_malign_Slot_f0_s0_ldst_encode, Opcode_ivp_malign_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_malign_Slot_f1_s0_ldstalu_encode, Opcode_ivp_malign_Slot_f1_s1_ld_encode, 0, 0, Opcode_ivp_malign_Slot_f2_s0_ldst_encode, Opcode_ivp_malign_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_malign_Slot_f3_s0_ldst_encode, Opcode_ivp_malign_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_malign_Slot_f4_s0_ld_encode, Opcode_ivp_malign_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_malign_Slot_f11_s0_ld_encode, Opcode_ivp_malign_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_ivp_malign_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_malign_Slot_n2_s0_ldst_encode, Opcode_ivp_malign_Slot_n2_s1_ld_encode, Opcode_ivp_malign_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_zalign_encode_fns[] = { + 0, 0, 0, Opcode_ivp_zalign_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_zalign_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_zalign_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_zalign_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_zalign_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_zalign_Slot_f11_s0_ld_encode, 0, 0, 0, 0, Opcode_ivp_zalign_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_zalign_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_zalign_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_la2nx8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_la2nx8_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_la2nx8_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_la2nx8_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_la2nx8_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_la2nx8_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_la2nx8_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_la2nx8_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_la2nx8_ip_Slot_f4_s0_ld_encode, Opcode_ivp_la2nx8_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_la2nx8_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_la2nx8_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_la2nx8_ip_Slot_n2_s1_ld_encode, Opcode_ivp_la2nx8_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sa2nx8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sa2nx8_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sa2nx8_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sa2nx8_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sa2nx8_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sa2nx8_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sa2nx8_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_sa2nx8_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lav2nx8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lav2nx8_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lav2nx8_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lav2nx8_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lav2nx8_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lav2nx8_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lav2nx8_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lav2nx8_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lav2nx8_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lav2nx8_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lav2nx8_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lav2nx8_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lav2nx8_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lav2nx8_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sav2nx8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sav2nx8_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sav2nx8_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sav2nx8_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sav2nx8_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sav2nx8_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sav2nx8_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_sav2nx8_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_selnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_selnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_selnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_selnx16_Slot_f2_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_selnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_shflnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_shflnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_shflnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_shflnx16_Slot_f2_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_shflnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_movpint16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movpint16_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movpint16_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movpint16_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movpint16_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movpint16_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movpint16_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movpa16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movpa16_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movpa16_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulnx16packp_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulnx16packp_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulnx16packp_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulnx16packp_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulanx16packp_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16packp_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16packp_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsnx16packp_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsnx16packp_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsnx16packp_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulanx16packpt_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16packpt_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addmod16u_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_addmod16u_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addmod16u_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_addmod16u_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_addmod16u_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8s_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8s_i_Slot_f0_s0_ldst_encode, Opcode_ivp_lvnx8s_i_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8s_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvnx8s_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8s_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8s_i_Slot_f3_s0_ldst_encode, Opcode_ivp_lvnx8s_i_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8s_i_Slot_f4_s0_ld_encode, Opcode_ivp_lvnx8s_i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8s_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8s_i_Slot_n2_s0_ldst_encode, Opcode_ivp_lvnx8s_i_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8s_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lvnx8s_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8s_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvnx8s_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8s_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8s_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lvnx8s_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8s_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lvnx8s_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8s_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8s_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lvnx8s_ip_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8s_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8s_x_Slot_f0_s0_ldst_encode, Opcode_ivp_lvnx8s_x_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8s_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvnx8s_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8s_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8s_x_Slot_f3_s0_ldst_encode, Opcode_ivp_lvnx8s_x_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8s_x_Slot_f4_s0_ld_encode, Opcode_ivp_lvnx8s_x_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8s_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8s_x_Slot_n2_s0_ldst_encode, Opcode_ivp_lvnx8s_x_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8s_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lvnx8s_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8s_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvnx8s_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8s_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8s_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lvnx8s_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8s_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lvnx8s_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8s_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lvnx8s_xp_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8u_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8u_i_Slot_f0_s0_ldst_encode, Opcode_ivp_lvnx8u_i_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8u_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvnx8u_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8u_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8u_i_Slot_f3_s0_ldst_encode, Opcode_ivp_lvnx8u_i_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8u_i_Slot_f4_s0_ld_encode, Opcode_ivp_lvnx8u_i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8u_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8u_i_Slot_n2_s0_ldst_encode, Opcode_ivp_lvnx8u_i_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8u_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lvnx8u_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8u_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvnx8u_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8u_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8u_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lvnx8u_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8u_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lvnx8u_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8u_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8u_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lvnx8u_ip_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8u_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8u_x_Slot_f0_s0_ldst_encode, Opcode_ivp_lvnx8u_x_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8u_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvnx8u_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8u_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8u_x_Slot_f3_s0_ldst_encode, Opcode_ivp_lvnx8u_x_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8u_x_Slot_f4_s0_ld_encode, Opcode_ivp_lvnx8u_x_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8u_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8u_x_Slot_n2_s0_ldst_encode, Opcode_ivp_lvnx8u_x_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8u_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lvnx8u_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8u_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvnx8u_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8u_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvnx8u_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lvnx8u_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvnx8u_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lvnx8u_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8u_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lvnx8u_xp_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8u_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8u_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8u_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8u_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8u_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8u_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8u_i_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svnx8u_i_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8u_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8u_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8u_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8u_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8u_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8u_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svnx8u_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8u_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8u_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8u_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8u_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8u_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8u_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8u_x_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svnx8u_x_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8u_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8u_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8u_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8u_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8u_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svnx8u_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8st_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8st_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvnx8st_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8st_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvnx8st_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8st_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8st_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8st_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8st_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvnx8st_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8st_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvnx8st_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8st_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8st_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8st_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8st_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvnx8st_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8st_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvnx8st_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8st_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8st_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8st_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8st_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvnx8st_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8st_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvnx8st_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8st_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8st_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8ut_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8ut_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvnx8ut_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8ut_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8ut_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8ut_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvnx8ut_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8ut_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8ut_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8ut_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvnx8ut_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8ut_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvnx8ut_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvnx8ut_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvnx8ut_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvnx8ut_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvnx8ut_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8ut_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8ut_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8ut_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8ut_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8ut_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8ut_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8ut_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8ut_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8ut_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8ut_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8ut_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8ut_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8ut_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8ut_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8ut_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8ut_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8ut_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8ut_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8ut_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8ut_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8ut_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8ut_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8ut_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8ut_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8ut_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8ut_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8ut_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8ut_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lavnx8s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lavnx8s_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lavnx8s_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lavnx8s_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lavnx8s_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lavnx8s_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lavnx8s_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lavnx8s_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lavnx8s_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lavnx8s_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lavnx8s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lavnx8s_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lavnx8s_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lavnx8s_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lavnx8u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lavnx8u_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lavnx8u_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lavnx8u_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lavnx8u_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lavnx8u_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lavnx8u_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lavnx8u_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lavnx8u_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lavnx8u_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lavnx8u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lavnx8u_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lavnx8u_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lavnx8u_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_savnx8u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_savnx8u_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_savnx8u_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_savnx8u_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_savnx8u_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_savnx8u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_savnx8u_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_savnx8u_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lanx8s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lanx8s_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lanx8s_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lanx8s_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lanx8s_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lanx8s_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lanx8s_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lanx8s_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lanx8s_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lanx8s_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lanx8s_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lanx8s_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lanx8s_ip_Slot_n2_s1_ld_encode, Opcode_ivp_lanx8s_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lanx8u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lanx8u_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lanx8u_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lanx8u_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lanx8u_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lanx8u_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lanx8u_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lanx8u_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lanx8u_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lanx8u_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lanx8u_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lanx8u_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lanx8u_ip_Slot_n2_s1_ld_encode, Opcode_ivp_lanx8u_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sanx8u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sanx8u_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sanx8u_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sanx8u_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sanx8u_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sanx8u_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sanx8u_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_sanx8u_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_extractbl_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_extractbl_Slot_f0_s1_ld_encode, 0, Opcode_ivp_extractbl_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_extractbl_Slot_f1_s3_alu_encode, 0, Opcode_ivp_extractbl_Slot_f2_s1_ld_encode, 0, Opcode_ivp_extractbl_Slot_f2_s3_alu_encode, 0, Opcode_ivp_extractbl_Slot_f3_s1_ld_encode, 0, Opcode_ivp_extractbl_Slot_f3_s3_alu_encode, 0, 0, Opcode_ivp_extractbl_Slot_f4_s1_ld_encode, 0, Opcode_ivp_extractbl_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extractbl_Slot_n2_s1_ld_encode, 0, 0, 0, Opcode_ivp_extractbl_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_extractbh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_extractbh_Slot_f0_s1_ld_encode, 0, Opcode_ivp_extractbh_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_extractbh_Slot_f1_s3_alu_encode, 0, Opcode_ivp_extractbh_Slot_f2_s1_ld_encode, 0, Opcode_ivp_extractbh_Slot_f2_s3_alu_encode, 0, Opcode_ivp_extractbh_Slot_f3_s1_ld_encode, 0, Opcode_ivp_extractbh_Slot_f3_s3_alu_encode, 0, 0, Opcode_ivp_extractbh_Slot_f4_s1_ld_encode, 0, Opcode_ivp_extractbh_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extractbh_Slot_n2_s1_ld_encode, 0, 0, 0, Opcode_ivp_extractbh_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_movvint16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movvint16_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movvint16_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movvint16_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movvint16_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movvint16_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movvint16_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movqint16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movqint16_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movqint16_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movqint16_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movqint16_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movqint16_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movqint16_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movqa16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movqa16_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movqa16_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movvinx16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movvinx16_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movvinx16_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movvinx16_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movvinx16_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movvinx16_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movvinx16_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_seqnx16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_seqnx16_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_seqnx16_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_seqnx16_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_seqnx16_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_seqnx16_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_seqnx16_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulnx16packl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulnx16packl_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulnx16packl_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulnx16packl_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulnx16packq_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulnx16packq_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulnx16packq_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulnx16packq_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movav16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_movav16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_movav16_Slot_f0_s3_alu_encode, Opcode_ivp_movav16_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_movav16_Slot_f1_s3_alu_encode, Opcode_ivp_movav16_Slot_f2_s0_ldst_encode, 0, 0, Opcode_ivp_movav16_Slot_f2_s3_alu_encode, Opcode_ivp_movav16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_movav16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_movav16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movav16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movav16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_movavu16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_movavu16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_movavu16_Slot_f0_s3_alu_encode, Opcode_ivp_movavu16_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_movavu16_Slot_f1_s3_alu_encode, Opcode_ivp_movavu16_Slot_f2_s0_ldst_encode, 0, 0, Opcode_ivp_movavu16_Slot_f2_s3_alu_encode, Opcode_ivp_movavu16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_movavu16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_movavu16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movavu16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movavu16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_extrnx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_extrnx16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_extrnx16_Slot_f0_s3_alu_encode, Opcode_ivp_extrnx16_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_extrnx16_Slot_f1_s3_alu_encode, Opcode_ivp_extrnx16_Slot_f2_s0_ldst_encode, 0, 0, Opcode_ivp_extrnx16_Slot_f2_s3_alu_encode, Opcode_ivp_extrnx16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_extrnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_extrnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extrnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extrnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsnx8s_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsnx8s_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsnx8s_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsnx8s_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsnx8s_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsnx8s_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsnx8s_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsnx8s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsnx8s_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsnx8s_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsnx8s_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsnx8s_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsnx8s_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsnx8s_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsnx8s_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsnx8s_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsnx8s_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsnx8s_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsnx8s_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsnx8s_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsnx8s_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsnx8s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsnx8s_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsnx8s_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsnx8s_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsnx8s_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsnx8s_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsnx8s_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8s_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8s_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8s_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8s_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8s_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8s_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8s_i_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svnx8s_i_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8s_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8s_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8s_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8s_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8s_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8s_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svnx8s_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8s_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8s_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8s_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8s_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8s_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8s_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8s_x_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svnx8s_x_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8s_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8s_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8s_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8s_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8s_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svnx8s_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssnx8s_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssnx8s_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx8s_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssnx8s_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx8s_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssnx8s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssnx8s_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx8s_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssnx8s_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx8s_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssnx8s_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssnx8s_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx8s_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssnx8s_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx8s_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssnx8s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssnx8s_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx8s_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssnx8s_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssnx8s_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_savnx8s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_savnx8s_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_savnx8s_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_savnx8s_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_savnx8s_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_savnx8s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_savnx8s_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_savnx8s_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sanx8s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sanx8s_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sanx8s_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sanx8s_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sanx8s_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sanx8s_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sanx8s_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_sanx8s_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8st_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8st_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8st_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8st_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8st_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8st_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8st_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8st_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8st_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8st_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8st_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8st_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8st_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8st_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8st_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8st_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8st_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8st_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8st_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8st_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8st_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svnx8st_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svnx8st_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8st_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svnx8st_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svnx8st_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svnx8st_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svnx8st_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movba1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movba1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movba1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movba1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movba1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movba1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movba1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movab1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movab1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movab1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movab1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movab1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movab1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movab1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_notb1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_notb1_Slot_f0_s1_ld_encode, 0, Opcode_ivp_notb1_Slot_f0_s3_alu_encode, 0, Opcode_ivp_notb1_Slot_f1_s1_ld_encode, 0, Opcode_ivp_notb1_Slot_f1_s3_alu_encode, 0, Opcode_ivp_notb1_Slot_f2_s1_ld_encode, 0, Opcode_ivp_notb1_Slot_f2_s3_alu_encode, 0, Opcode_ivp_notb1_Slot_f3_s1_ld_encode, 0, Opcode_ivp_notb1_Slot_f3_s3_alu_encode, 0, 0, Opcode_ivp_notb1_Slot_f4_s1_ld_encode, 0, Opcode_ivp_notb1_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_notb1_Slot_f11_s1_alu_encode, 0, Opcode_ivp_notb1_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_notb1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_andnotb1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_andnotb1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_andnotb1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_andnotb1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_andnotb1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_andnotb1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_andnotb1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ornotb1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ornotb1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ornotb1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ornotb1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ornotb1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ornotb1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ornotb1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt32s2nx24ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24ll_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24ll_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24ll_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24ll_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24ll_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24ll_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt32s2nx24lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24lh_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24lh_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24lh_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24lh_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24lh_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24lh_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt32s2nx24hl_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24hl_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24hl_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24hl_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24hl_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24hl_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24hl_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt32s2nx24hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24hh_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24hh_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24hh_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s2nx24hh_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24hh_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt32s2nx24hh_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt64snx48ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt64snx48ll_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt64snx48ll_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt64snx48lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt64snx48lh_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt64snx48lh_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt64snx48hl_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt64snx48hl_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt64snx48hl_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt64snx48hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt64snx48hh_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt64snx48hh_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt16s2nx24l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt16s2nx24l_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16s2nx24l_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16s2nx24l_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16s2nx24l_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt16s2nx24l_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt16s2nx24l_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt16s2nx24h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt16s2nx24h_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16s2nx24h_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16s2nx24h_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16s2nx24h_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt16s2nx24h_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt16s2nx24h_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt32snx48l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt32snx48l_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32snx48l_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32snx48l_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32snx48l_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt32snx48l_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt32snx48l_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt32snx48h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt32snx48h_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32snx48h_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32snx48h_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32snx48h_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt32snx48h_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt32snx48h_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt16u2nx24h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt16u2nx24h_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16u2nx24h_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16u2nx24h_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16u2nx24h_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt16u2nx24h_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt16u2nx24h_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt32unx48h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt32unx48h_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32unx48h_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32unx48h_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32unx48h_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt32unx48h_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt32unx48h_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt64un_2x96h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt64un_2x96h_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt64un_2x96h_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt16u2nx24l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt16u2nx24l_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16u2nx24l_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16u2nx24l_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt16u2nx24l_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt16u2nx24l_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt16u2nx24l_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt24u2nx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt24u2nx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24u2nx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24u2nx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24u2nx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt24u2nx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt24u2nx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt24s2nx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt24s2nx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24s2nx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24s2nx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24s2nx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt24s2nx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt32s24_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt32s24_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s24_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s24_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32s24_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt32s24_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt32s24_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt24u32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt24u32_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24u32_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24u32_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24u32_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt24u32_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt24u32_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt24unx32l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt24unx32l_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24unx32l_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24unx32l_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24unx32l_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt24unx32l_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt24unx32l_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt24unx32h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt24unx32h_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24unx32h_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24unx32h_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt24unx32h_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt24unx32h_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt24unx32h_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt32unx48l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt32unx48l_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32unx48l_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32unx48l_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt32unx48l_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt32unx48l_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt32unx48l_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt48unx32l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt48unx32l_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48unx32l_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48unx32l_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48unx32l_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt48unx32l_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt48unx32l_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt48unx32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt48unx32_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48unx32_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48unx32_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48unx32_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt48unx32_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt48unx32_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt48snx32l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt48snx32l_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48snx32l_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48snx32l_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48snx32l_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt48snx32l_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt48snx32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt48snx32_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48snx32_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48snx32_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48snx32_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt48snx32_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt64s48_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt64s48_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt64s48_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt64s48_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt64s48_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt64s48_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt64s48_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt48u64_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt48u64_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48u64_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48u64_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48u64_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt48u64_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt48u64_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt48un_2x64l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt48un_2x64l_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48un_2x64l_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48un_2x64l_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48un_2x64l_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt48un_2x64l_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt48un_2x64l_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt48un_2x64h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt48un_2x64h_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48un_2x64h_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48un_2x64h_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt48un_2x64h_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt48un_2x64h_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt48un_2x64h_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt64un_2x96l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt64un_2x96l_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt64un_2x96l_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt96un_2x64_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt96un_2x64_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt96un_2x64_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt96un_2x64_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt96un_2x64_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt96un_2x64_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt96un_2x64_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt96u64_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_cvt96u64_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt96u64_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt96u64_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_cvt96u64_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt96u64_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_cvt96u64_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_cvt64u96_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_cvt64u96_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt64u96_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt64u96_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_cvt64u96_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_cvt64u96_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_cvt64u96_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lb2n_i_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_lb2n_i_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lb2n_i_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_lb2n_i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lb2n_i_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lb2n_ip_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_lb2n_ip_Slot_f0_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lb2n_ip_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_lb2n_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lb2n_ip_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sb2n_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sb2n_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sb2n_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sb2n_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sb2n_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sb2n_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sb2n_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sb2n_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_sb2n_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sb2n_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_sb2n_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_sb2n_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sb2n_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_sb2n_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltr2n_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ltr2n_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltr2n_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltr2n_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltr2n_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ltr2n_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltr2n_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltr2n_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltr2ni_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ltr2ni_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltr2ni_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltr2ni_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltr2ni_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ltr2ni_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltr2ni_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltr2ni_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16u_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16u_i_Slot_f0_s0_ldst_encode, Opcode_ivp_lvn_2x16u_i_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16u_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvn_2x16u_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16u_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16u_i_Slot_f3_s0_ldst_encode, Opcode_ivp_lvn_2x16u_i_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16u_i_Slot_f4_s0_ld_encode, Opcode_ivp_lvn_2x16u_i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16u_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16u_i_Slot_n2_s0_ldst_encode, Opcode_ivp_lvn_2x16u_i_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16u_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lvn_2x16u_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16u_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvn_2x16u_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16u_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16u_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lvn_2x16u_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16u_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lvn_2x16u_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16u_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16u_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lvn_2x16u_ip_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16u_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16u_x_Slot_f0_s0_ldst_encode, Opcode_ivp_lvn_2x16u_x_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16u_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvn_2x16u_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16u_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16u_x_Slot_f3_s0_ldst_encode, Opcode_ivp_lvn_2x16u_x_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16u_x_Slot_f4_s0_ld_encode, Opcode_ivp_lvn_2x16u_x_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16u_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16u_x_Slot_n2_s0_ldst_encode, Opcode_ivp_lvn_2x16u_x_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16u_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lvn_2x16u_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16u_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvn_2x16u_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16u_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16u_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lvn_2x16u_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16u_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lvn_2x16u_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16u_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lvn_2x16u_xp_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16ut_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16ut_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvn_2x16ut_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16ut_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16ut_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16ut_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvn_2x16ut_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16ut_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16ut_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16ut_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvn_2x16ut_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16ut_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16ut_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16ut_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvn_2x16ut_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16ut_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16ut_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16s_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16s_i_Slot_f0_s0_ldst_encode, Opcode_ivp_lvn_2x16s_i_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16s_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvn_2x16s_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16s_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16s_i_Slot_f3_s0_ldst_encode, Opcode_ivp_lvn_2x16s_i_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16s_i_Slot_f4_s0_ld_encode, Opcode_ivp_lvn_2x16s_i_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16s_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16s_i_Slot_n2_s0_ldst_encode, Opcode_ivp_lvn_2x16s_i_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16s_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lvn_2x16s_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16s_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvn_2x16s_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16s_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16s_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lvn_2x16s_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16s_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lvn_2x16s_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16s_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16s_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lvn_2x16s_ip_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16s_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16s_x_Slot_f0_s0_ldst_encode, Opcode_ivp_lvn_2x16s_x_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16s_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvn_2x16s_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16s_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16s_x_Slot_f3_s0_ldst_encode, Opcode_ivp_lvn_2x16s_x_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16s_x_Slot_f4_s0_ld_encode, Opcode_ivp_lvn_2x16s_x_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16s_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16s_x_Slot_n2_s0_ldst_encode, Opcode_ivp_lvn_2x16s_x_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16s_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lvn_2x16s_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16s_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lvn_2x16s_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16s_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lvn_2x16s_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lvn_2x16s_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lvn_2x16s_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lvn_2x16s_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16s_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lvn_2x16s_xp_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16st_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16st_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvn_2x16st_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16st_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16st_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16st_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvn_2x16st_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16st_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16st_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16st_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvn_2x16st_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16st_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lvn_2x16st_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lvn_2x16st_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lvn_2x16st_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lvn_2x16st_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lvn_2x16st_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16u_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16u_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16u_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16u_i_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svn_2x16u_i_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16ut_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16ut_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16ut_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16ut_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16u_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16u_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16u_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svn_2x16u_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16ut_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16ut_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16ut_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16ut_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16u_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16u_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16u_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16u_x_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svn_2x16u_x_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16ut_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16ut_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16ut_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16ut_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16u_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16u_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16u_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svn_2x16u_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16ut_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16ut_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16ut_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16ut_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16ut_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16s_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16s_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16s_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16s_i_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svn_2x16s_i_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16st_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16st_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16st_i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16st_i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16s_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16s_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16s_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svn_2x16s_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16st_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16st_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16st_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16st_ip_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16s_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16s_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16s_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16s_x_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svn_2x16s_x_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16st_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16st_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16st_x_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16st_x_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16s_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16s_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16s_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_svn_2x16s_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_svn_2x16st_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_svn_2x16st_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_svn_2x16st_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_svn_2x16st_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_svn_2x16st_xp_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lan_2x16s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lan_2x16s_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lan_2x16s_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lan_2x16s_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lan_2x16s_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lan_2x16s_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lan_2x16s_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lan_2x16s_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lan_2x16s_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lan_2x16s_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lan_2x16s_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lan_2x16s_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lan_2x16s_ip_Slot_n2_s1_ld_encode, Opcode_ivp_lan_2x16s_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lan_2x16u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lan_2x16u_ip_Slot_f0_s0_ldst_encode, Opcode_ivp_lan_2x16u_ip_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lan_2x16u_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lan_2x16u_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lan_2x16u_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lan_2x16u_ip_Slot_f3_s0_ldst_encode, Opcode_ivp_lan_2x16u_ip_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lan_2x16u_ip_Slot_f4_s0_ld_encode, Opcode_ivp_lan_2x16u_ip_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lan_2x16u_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lan_2x16u_ip_Slot_n2_s0_ldst_encode, Opcode_ivp_lan_2x16u_ip_Slot_n2_s1_ld_encode, Opcode_ivp_lan_2x16u_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lan_2x16u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lan_2x16u_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lan_2x16u_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lan_2x16u_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lan_2x16u_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lan_2x16u_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lan_2x16u_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lan_2x16u_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lan_2x16u_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lan_2x16u_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lan_2x16u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lan_2x16u_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lan_2x16u_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lan_2x16u_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lan_2x16s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lan_2x16s_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lan_2x16s_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lan_2x16s_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lan_2x16s_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lan_2x16s_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lan_2x16s_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lan_2x16s_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lan_2x16s_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lan_2x16s_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lan_2x16s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lan_2x16s_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lan_2x16s_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lan_2x16s_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_san_2x16u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_san_2x16u_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_san_2x16u_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_san_2x16u_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_san_2x16u_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_san_2x16u_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_san_2x16u_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_san_2x16u_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_san_2x16s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_san_2x16s_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_san_2x16s_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_san_2x16s_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_san_2x16s_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_san_2x16s_ip_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_san_2x16s_ip_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_san_2x16s_ip_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lavn_2x16s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lavn_2x16s_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lavn_2x16s_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lavn_2x16s_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lavn_2x16s_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lavn_2x16s_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lavn_2x16s_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lavn_2x16s_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lavn_2x16s_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lavn_2x16s_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lavn_2x16s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lavn_2x16s_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lavn_2x16s_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lavn_2x16s_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lavn_2x16u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lavn_2x16u_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lavn_2x16u_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lavn_2x16u_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lavn_2x16u_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lavn_2x16u_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lavn_2x16u_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lavn_2x16u_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lavn_2x16u_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lavn_2x16u_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lavn_2x16u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lavn_2x16u_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lavn_2x16u_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lavn_2x16u_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_savn_2x16u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_savn_2x16u_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_savn_2x16u_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_savn_2x16u_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_savn_2x16u_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_savn_2x16u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_savn_2x16u_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_savn_2x16u_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_savn_2x16s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_savn_2x16s_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_savn_2x16s_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_savn_2x16s_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_savn_2x16s_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_savn_2x16s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_savn_2x16s_xp_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_savn_2x16s_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsn_2x16s_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsn_2x16s_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsn_2x16s_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsn_2x16s_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsn_2x16s_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsn_2x16s_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsn_2x16s_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsn_2x16s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsn_2x16s_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsn_2x16s_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsn_2x16s_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsn_2x16s_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsn_2x16s_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsn_2x16s_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsn_2x16s_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsn_2x16s_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsn_2x16s_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsn_2x16s_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsn_2x16s_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsn_2x16s_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsn_2x16s_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsn_2x16s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsn_2x16s_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsn_2x16s_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsn_2x16s_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsn_2x16s_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsn_2x16s_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsn_2x16s_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssn_2x16s_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssn_2x16s_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssn_2x16s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssn_2x16s_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssn_2x16s_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssn_2x16s_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssn_2x16s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssn_2x16s_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x16s_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsn_2x32_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsn_2x32_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsn_2x32_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsn_2x32_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsn_2x32_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsn_2x32_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsn_2x32_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsn_2x32_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsn_2x32_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsn_2x32_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsn_2x32_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsn_2x32_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsn_2x32_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsn_2x32_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsn_2x32_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsn_2x32_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsn_2x32_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsn_2x32_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsn_2x32_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsn_2x32_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsn_2x32_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsn_2x32_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsn_2x32_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsn_2x32_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsn_2x32_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsn_2x32_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsn_2x32_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsn_2x32_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssn_2x32_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssn_2x32_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssn_2x32_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssn_2x32_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssn_2x32_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssn_2x32_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ssn_2x32_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ssn_2x32_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ssn_2x32_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_bmaxunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxunx16_Slot_f0_s3_alu_encode, Opcode_ivp_bmaxunx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bmaxunx16_Slot_f1_s2_mul_encode, Opcode_ivp_bmaxunx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bmaxunx16_Slot_f2_s2_mul_encode, Opcode_ivp_bmaxunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bmaxunx16_Slot_f3_s3_alu_encode, Opcode_ivp_bmaxunx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bmaxunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxunx16_Slot_f11_s3_alu_encode, Opcode_ivp_bmaxunx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bminunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bminunx16_Slot_f0_s3_alu_encode, Opcode_ivp_bminunx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bminunx16_Slot_f1_s2_mul_encode, Opcode_ivp_bminunx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bminunx16_Slot_f2_s2_mul_encode, Opcode_ivp_bminunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bminunx16_Slot_f3_s3_alu_encode, Opcode_ivp_bminunx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bminunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminunx16_Slot_f11_s3_alu_encode, Opcode_ivp_bminunx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rbminunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rbminunx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbminunx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbminunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbminunx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rbminunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rbminunx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rbminunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rbmaxunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rbmaxunx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbmaxunx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbmaxunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rbmaxunx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rbmaxunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rbmaxunx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rbmaxunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bmax2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bmax2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_bmax2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bmax2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_bmax2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bmax2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_bmax2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bmax2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_bmax2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bmax2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmax2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_bmax2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmax2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bmin2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bmin2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_bmin2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bmin2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_bmin2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bmin2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_bmin2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bmin2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_bmin2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bmin2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmin2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_bmin2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmin2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bmaxu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxu2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_bmaxu2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bmaxu2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_bmaxu2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bmaxu2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_bmaxu2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bmaxu2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_bmaxu2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bmaxu2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxu2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_bmaxu2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxu2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bminu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bminu2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_bminu2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bminu2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_bminu2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bminu2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_bminu2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bminu2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_bminu2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bminu2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminu2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_bminu2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminu2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bmaxn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_bmaxn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bmaxn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_bmaxn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bmaxn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_bmaxn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bmaxn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_bmaxn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bmaxn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxn_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_bmaxn_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bminn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bminn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_bminn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bminn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_bminn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bminn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_bminn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bminn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_bminn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bminn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminn_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_bminn_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bmaxun_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxun_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_bmaxun_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bmaxun_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_bmaxun_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bmaxun_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_bmaxun_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bmaxun_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_bmaxun_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bmaxun_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxun_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_bmaxun_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bmaxun_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bminun_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bminun_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_bminun_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bminun_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_bminun_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bminun_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_bminun_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bminun_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_bminun_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bminun_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminun_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_bminun_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bminun_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_addn_2x32t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_addn_2x32t_Slot_f0_s3_alu_encode, Opcode_ivp_addn_2x32t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_addn_2x32t_Slot_f1_s2_mul_encode, Opcode_ivp_addn_2x32t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_addn_2x32t_Slot_f2_s2_mul_encode, Opcode_ivp_addn_2x32t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_addn_2x32t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_addn_2x32t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addn_2x32t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addn_2x32t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_subn_2x32t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_subn_2x32t_Slot_f0_s3_alu_encode, Opcode_ivp_subn_2x32t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_subn_2x32t_Slot_f1_s2_mul_encode, Opcode_ivp_subn_2x32t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_subn_2x32t_Slot_f2_s2_mul_encode, Opcode_ivp_subn_2x32t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_subn_2x32t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_subn_2x32t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subn_2x32t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subn_2x32t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_add2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_add2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_add2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_add2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_add2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_add2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_add2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_add2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_add2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_add2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_add2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_add2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_add2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sub2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sub2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_sub2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_sub2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_sub2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_sub2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_sub2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_sub2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_sub2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_sub2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sub2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_sub2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sub2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_neg2nx8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_neg2nx8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_neg2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_neg2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_neg2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_neg2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_neg2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_neg2nx8_Slot_f2_s3_alu_encode, Opcode_ivp_neg2nx8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_neg2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_neg2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_neg2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_neg2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_neg2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_neg2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_min2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_min2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_min2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_min2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_min2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_min2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_min2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_min2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_min2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_min2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_min2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_min2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_min2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_minu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_minu2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_minu2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_minu2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_minu2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_minu2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_minu2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_minu2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_minu2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_minu2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minu2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_minu2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minu2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_max2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_max2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_max2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_max2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_max2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_max2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_max2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_max2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_max2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_max2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_max2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_max2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_max2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_maxu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_maxu2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_maxu2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_maxu2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_maxu2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_maxu2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_maxu2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_maxu2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_maxu2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_maxu2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxu2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_maxu2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxu2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_lt2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_lt2nx8_Slot_f0_s2_mul_encode, Opcode_ivp_lt2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_lt2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_lt2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_lt2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_lt2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_lt2nx8_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_lt2nx8_Slot_f3_s2_mul_encode, Opcode_ivp_lt2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_lt2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_lt2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_lt2nx8_Slot_f11_s2_mul_encode, Opcode_ivp_lt2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_lt2nx8_Slot_n1_s2_mul_encode, Opcode_ivp_lt2nx8_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lt2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_le2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_le2nx8_Slot_f0_s2_mul_encode, Opcode_ivp_le2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_le2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_le2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_le2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_le2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_le2nx8_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_le2nx8_Slot_f3_s2_mul_encode, Opcode_ivp_le2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_le2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_le2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_le2nx8_Slot_f11_s2_mul_encode, Opcode_ivp_le2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_le2nx8_Slot_n1_s2_mul_encode, Opcode_ivp_le2nx8_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_le2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_eq2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_eq2nx8_Slot_f0_s2_mul_encode, Opcode_ivp_eq2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_eq2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_eq2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_eq2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_eq2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_eq2nx8_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_eq2nx8_Slot_f3_s2_mul_encode, Opcode_ivp_eq2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_eq2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_eq2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_eq2nx8_Slot_f11_s2_mul_encode, Opcode_ivp_eq2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_eq2nx8_Slot_n1_s2_mul_encode, Opcode_ivp_eq2nx8_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_eq2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_neq2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_neq2nx8_Slot_f0_s2_mul_encode, Opcode_ivp_neq2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_neq2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_neq2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_neq2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_neq2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_neq2nx8_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_neq2nx8_Slot_f3_s2_mul_encode, Opcode_ivp_neq2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_neq2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_neq2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_neq2nx8_Slot_f11_s2_mul_encode, Opcode_ivp_neq2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_neq2nx8_Slot_n1_s2_mul_encode, Opcode_ivp_neq2nx8_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_neq2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_ltu2nx8_Slot_f0_s2_mul_encode, Opcode_ivp_ltu2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_ltu2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_ltu2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_ltu2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_ltu2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_ltu2nx8_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_ltu2nx8_Slot_f3_s2_mul_encode, Opcode_ivp_ltu2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_ltu2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_ltu2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltu2nx8_Slot_f11_s2_mul_encode, Opcode_ivp_ltu2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_ltu2nx8_Slot_n1_s2_mul_encode, Opcode_ivp_ltu2nx8_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_ltu2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_leu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_leu2nx8_Slot_f0_s2_mul_encode, Opcode_ivp_leu2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_leu2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_leu2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_leu2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_leu2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_leu2nx8_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_leu2nx8_Slot_f3_s2_mul_encode, Opcode_ivp_leu2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_leu2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_leu2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_leu2nx8_Slot_f11_s2_mul_encode, Opcode_ivp_leu2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_leu2nx8_Slot_n1_s2_mul_encode, Opcode_ivp_leu2nx8_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_leu2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_add2nx8t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_add2nx8t_Slot_f0_s3_alu_encode, Opcode_ivp_add2nx8t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_add2nx8t_Slot_f1_s2_mul_encode, Opcode_ivp_add2nx8t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_add2nx8t_Slot_f2_s2_mul_encode, Opcode_ivp_add2nx8t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_add2nx8t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_add2nx8t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_add2nx8t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_add2nx8t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sub2nx8t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sub2nx8t_Slot_f0_s3_alu_encode, Opcode_ivp_sub2nx8t_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_sub2nx8t_Slot_f1_s2_mul_encode, Opcode_ivp_sub2nx8t_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_sub2nx8t_Slot_f2_s2_mul_encode, Opcode_ivp_sub2nx8t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_sub2nx8t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_sub2nx8t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sub2nx8t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sub2nx8t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_selnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_selnx16t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_selnx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_selnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_selnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_seln_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_seln_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_seln_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_seln_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_seln_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_seln_2x32t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_seln_2x32t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_seln_2x32t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_seln_2x32t_Slot_f2_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_seln_2x32t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_shfln_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_shfln_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_shfln_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_shfln_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_shfln_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sllin_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sllin_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_sllin_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_sllin_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_sllin_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_sllin_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sllin_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sllin_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_slsin_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_slsin_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsin_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsin_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsin_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_slsin_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slsin_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slsin_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srain_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_srain_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_srain_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_srain_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_srain_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srain_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srain_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srain_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srlin_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_srlin_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_srlin_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_srlin_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_srlin_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srlin_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srlin_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srlin_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_slln_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_slln_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_slln_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_slln_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_slln_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_slln_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slln_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slln_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srln_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_srln_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_srln_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_srln_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_srln_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srln_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srln_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srln_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_slan_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_slan_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_slan_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_slan_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_slan_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_slan_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slan_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slan_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sran_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sran_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_sran_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_sran_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_sran_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_sran_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sran_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sran_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_slsn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_slsn_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsn_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_slsn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_slsn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slsn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slsn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srsn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_srsn_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_srsn_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_srsn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_srsn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srsn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srsn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srsn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddn_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddn_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rmaxn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxn_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxn_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rmaxn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rminn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rminn_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminn_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rminn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rmaxun_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxun_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxun_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxun_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rmaxun_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rmaxun_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxun_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rmaxun_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rminun_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rminun_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminun_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminun_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rminun_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rminun_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminun_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rminun_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddn_2x32t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddn_2x32t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddn_2x32t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddn_2x32t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddn_2x32t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddn_2x32t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddn_2x32t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddn_2x32t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_abs2nx8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_abs2nx8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_abs2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_abs2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_abs2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_abs2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_abs2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_abs2nx8_Slot_f2_s3_alu_encode, Opcode_ivp_abs2nx8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_abs2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_abs2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_abs2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abs2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_abs2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abs2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_absn_2x32_encode_fns[] = { + 0, 0, 0, Opcode_ivp_absn_2x32_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_absn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_absn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_absn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_absn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_absn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_absn_2x32_Slot_f2_s3_alu_encode, Opcode_ivp_absn_2x32_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_absn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_absn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_absn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_absn_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_absn_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_absn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsgnsnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsgnsnx16_Slot_f0_s3_alu_encode, Opcode_ivp_mulsgnsnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_mulsgnsnx16_Slot_f1_s2_mul_encode, Opcode_ivp_mulsgnsnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_mulsgnsnx16_Slot_f2_s2_mul_encode, Opcode_ivp_mulsgnsnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_mulsgnsnx16_Slot_f3_s3_alu_encode, Opcode_ivp_mulsgnsnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_mulsgnsnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsgnsnx16_Slot_f11_s3_alu_encode, Opcode_ivp_mulsgnsnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsgnsnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rotri2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rotri2nx8_Slot_f0_s3_alu_encode, 0, 0, Opcode_ivp_rotri2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_rotri2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_rotri2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_rotri2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotri2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rotri2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotri2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotri2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rotrinx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrinx16_Slot_f0_s3_alu_encode, 0, 0, Opcode_ivp_rotrinx16_Slot_f1_s2_mul_encode, Opcode_ivp_rotrinx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_rotrinx16_Slot_f2_s2_mul_encode, Opcode_ivp_rotrinx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrinx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rotrinx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrinx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrinx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rotrin_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrin_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrin_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrin_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrin_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rotrin_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrin_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrin_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rotrnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rotrnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_rotrn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrn_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrn_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_rotrn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_rotrn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rotrn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_addn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_addn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_addn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_addn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_addn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_addn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_addn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_addn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_addn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_addn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addn_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_addn_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_subn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_subn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_subn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_subn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_subn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_subn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_subn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_subn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_subn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_subn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subn_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_subn_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_negn_2x32_encode_fns[] = { + 0, 0, 0, Opcode_ivp_negn_2x32_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_negn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_negn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_negn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_negn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_negn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_negn_2x32_Slot_f2_s3_alu_encode, Opcode_ivp_negn_2x32_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_negn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_negn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_negn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negn_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_negn_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_negn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_minn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_minn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_minn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_minn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_minn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_minn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_minn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_minn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_minn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_minn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minn_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_minn_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_minun_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_minun_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_minun_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_minun_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_minun_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_minun_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_minun_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_minun_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_minun_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_minun_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minun_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_minun_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_minun_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_maxn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_maxn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_maxn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_maxn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_maxn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_maxn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_maxn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_maxn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_maxn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_maxn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxn_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_maxn_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_maxun_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_maxun_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_maxun_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_maxun_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_maxun_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_maxun_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_maxun_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_maxun_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_maxun_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_maxun_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxun_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_maxun_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_maxun_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsgnn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsgnn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_mulsgnn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_mulsgnn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_mulsgnn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_mulsgnn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_mulsgnn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_mulsgnn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_mulsgnn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_mulsgnn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsgnn_2x32_Slot_f11_s3_alu_encode, Opcode_ivp_mulsgnn_2x32_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsgnn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_nsan_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_nsan_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsan_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsan_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsan_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_nsan_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_nsan_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_nsan_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_nsaun_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_nsaun_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsaun_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsaun_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_nsaun_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_nsaun_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_nsaun_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_nsaun_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_ltn_2x32_Slot_f0_s2_mul_encode, Opcode_ivp_ltn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_ltn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_ltn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_ltn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_ltn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_ltn_2x32_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_ltn_2x32_Slot_f3_s2_mul_encode, Opcode_ivp_ltn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_ltn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_ltn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltn_2x32_Slot_f11_s2_mul_encode, Opcode_ivp_ltn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_ltn_2x32_Slot_n1_s2_mul_encode, Opcode_ivp_ltn_2x32_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_ltn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_len_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_len_2x32_Slot_f0_s2_mul_encode, Opcode_ivp_len_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_len_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_len_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_len_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_len_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_len_2x32_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_len_2x32_Slot_f3_s2_mul_encode, Opcode_ivp_len_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_len_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_len_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_len_2x32_Slot_f11_s2_mul_encode, Opcode_ivp_len_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_len_2x32_Slot_n1_s2_mul_encode, Opcode_ivp_len_2x32_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_len_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_eqn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_eqn_2x32_Slot_f0_s2_mul_encode, Opcode_ivp_eqn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_eqn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_eqn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_eqn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_eqn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_eqn_2x32_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_eqn_2x32_Slot_f3_s2_mul_encode, Opcode_ivp_eqn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_eqn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_eqn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_eqn_2x32_Slot_f11_s2_mul_encode, Opcode_ivp_eqn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_eqn_2x32_Slot_n1_s2_mul_encode, Opcode_ivp_eqn_2x32_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_eqn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_neqn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_neqn_2x32_Slot_f0_s2_mul_encode, Opcode_ivp_neqn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_neqn_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_neqn_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_neqn_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_neqn_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_neqn_2x32_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_neqn_2x32_Slot_f3_s2_mul_encode, Opcode_ivp_neqn_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_neqn_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_neqn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_neqn_2x32_Slot_f11_s2_mul_encode, Opcode_ivp_neqn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_neqn_2x32_Slot_n1_s2_mul_encode, Opcode_ivp_neqn_2x32_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_neqn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltun_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_ltun_2x32_Slot_f0_s2_mul_encode, Opcode_ivp_ltun_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_ltun_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_ltun_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_ltun_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_ltun_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_ltun_2x32_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_ltun_2x32_Slot_f3_s2_mul_encode, Opcode_ivp_ltun_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_ltun_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_ltun_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltun_2x32_Slot_f11_s2_mul_encode, Opcode_ivp_ltun_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_ltun_2x32_Slot_n1_s2_mul_encode, Opcode_ivp_ltun_2x32_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_ltun_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_leun_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_leun_2x32_Slot_f0_s2_mul_encode, Opcode_ivp_leun_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_leun_2x32_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_leun_2x32_Slot_f1_s2_mul_encode, Opcode_ivp_leun_2x32_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_leun_2x32_Slot_f2_s2_mul_encode, Opcode_ivp_leun_2x32_Slot_f2_s3_alu_encode, 0, 0, Opcode_ivp_leun_2x32_Slot_f3_s2_mul_encode, Opcode_ivp_leun_2x32_Slot_f3_s3_alu_encode, Opcode_ivp_leun_2x32_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_leun_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_leun_2x32_Slot_f11_s2_mul_encode, Opcode_ivp_leun_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_leun_2x32_Slot_n1_s2_mul_encode, Opcode_ivp_leun_2x32_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_leun_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_lat2nx8_xp_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_lat2nx8_xp_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_lat2nx8_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lat2nx8_xp_Slot_f2_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lat2nx8_xp_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluu2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluu2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluu2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluu2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluu2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluu2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluua2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluua2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluua2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluua2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluua2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluua2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluua2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulus2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulus2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulus2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulus2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusa2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusa2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusa2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusa2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusa2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusa2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusa2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muli2nx8x16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muli2nx8x16_Slot_f0_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muli2nx8x16_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muli2nx8x16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulai2nx8x16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulai2nx8x16_Slot_f0_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulai2nx8x16_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulai2nx8x16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusi2nx8x16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusi2nx8x16_Slot_f0_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusi2nx8x16_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusi2nx8x16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusai2nx8x16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusai2nx8x16_Slot_f0_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusai2nx8x16_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusai2nx8x16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muli2nr8x16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muli2nr8x16_Slot_f0_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muli2nr8x16_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muli2nr8x16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulai2nr8x16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulai2nr8x16_Slot_f0_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulai2nr8x16_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulai2nr8x16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusi2nr8x16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusi2nr8x16_Slot_f0_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusi2nr8x16_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusi2nr8x16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusai2nr8x16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusai2nr8x16_Slot_f0_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusai2nr8x16_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusai2nr8x16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusa2n8xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusa2n8xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusa2n8xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusa2n8xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusa2n8xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusa2n8xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusa2n8xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulus2n8xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulus2n8xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus2n8xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus2n8xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus2n8xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulus2n8xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulus2n8xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mula2n8xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mula2n8xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mula2n8xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mula2n8xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mula2n8xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mula2n8xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mula2n8xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mul2n8xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mul2n8xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul2n8xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul2n8xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul2n8xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mul2n8xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mul2n8xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_dsel2nx8i_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_dsel2nx8i_Slot_f0_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_dsel2nx8i_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_dsel2nx8i_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_dsel2nx8i_h_Slot_f0_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_dsel2nx8i_h_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_dselnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_dselnx16_Slot_f0_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_dselnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_dselnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_dselnx16t_Slot_f0_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_dselnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_injbi2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_injbi2nx8_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_injbi2nx8_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_injbi2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_injbi2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_injbi2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_extbi2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_extbi2nx8_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_extbi2nx8_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_extbi2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_extbi2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_extbi2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extbi2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extbi2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_movva32_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movva32_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movva32_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movva32_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movva32_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movva32_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movva32_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movav32_encode_fns[] = { + 0, 0, 0, Opcode_ivp_movav32_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_movav32_Slot_f0_s3_alu_encode, Opcode_ivp_movav32_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_movav32_Slot_f1_s3_alu_encode, Opcode_ivp_movav32_Slot_f2_s0_ldst_encode, 0, 0, Opcode_ivp_movav32_Slot_f2_s3_alu_encode, Opcode_ivp_movav32_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_movav32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_movav32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movav32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movav32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_movww_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_movww_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_movww_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_movww_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_movww_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movww_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_movww_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ls2nx8_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ls2nx8_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ls2nx8_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_ls2nx8_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ls2nx8_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_ls2nx8_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_ls2nx8_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ls2nx8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ls2nx8_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ls2nx8_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_ls2nx8_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ls2nx8_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_ls2nx8_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_ls2nx8_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ls2nx8_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ls2nx8_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ls2nx8_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_ls2nx8_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ls2nx8_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_ls2nx8_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_ls2nx8_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ls2nx8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ls2nx8_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ls2nx8_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_ls2nx8_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ls2nx8_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_ls2nx8_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_ls2nx8_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ss2nx8_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ss2nx8_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ss2nx8_i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ss2nx8_i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ss2nx8_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ss2nx8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ss2nx8_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ss2nx8_ip_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ss2nx8_ip_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ss2nx8_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ss2nx8_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ss2nx8_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ss2nx8_x_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ss2nx8_x_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ss2nx8_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ss2nx8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_ss2nx8_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ss2nx8_xp_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_ss2nx8_xp_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_ss2nx8_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lanx8s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lanx8s_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lanx8s_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lanx8s_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lanx8s_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lanx8s_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lanx8s_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lanx8s_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lanx8s_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lanx8s_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lanx8s_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lanx8s_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lanx8s_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lanx8s_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lanx8u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lanx8u_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_lanx8u_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_lanx8u_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lanx8u_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lanx8u_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lanx8u_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_lanx8u_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_lanx8u_xp_Slot_f4_s0_ld_encode, Opcode_ivp_lanx8u_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_lanx8u_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_lanx8u_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_lanx8u_xp_Slot_n2_s1_ld_encode, Opcode_ivp_lanx8u_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_la2nx8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_la2nx8_xp_Slot_f0_s0_ldst_encode, Opcode_ivp_la2nx8_xp_Slot_f0_s1_ld_encode, 0, 0, Opcode_ivp_la2nx8_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_la2nx8_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_la2nx8_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_la2nx8_xp_Slot_f3_s0_ldst_encode, Opcode_ivp_la2nx8_xp_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_ivp_la2nx8_xp_Slot_f4_s0_ld_encode, Opcode_ivp_la2nx8_xp_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_la2nx8_xp_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_la2nx8_xp_Slot_n2_s0_ldst_encode, Opcode_ivp_la2nx8_xp_Slot_n2_s1_ld_encode, Opcode_ivp_la2nx8_xp_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_abssubu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_abssubu2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_abssubu2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_abssubu2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_abssubu2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_abssubu2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_abssubu2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_abssubu2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_abssubu2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_abssubu2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssubu2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_abssubu2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssubu2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_abssub2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_abssub2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_abssub2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_abssub2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_abssub2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_abssub2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_abssub2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_abssub2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_abssub2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_abssub2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssub2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_abssub2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssub2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_movvint8_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movvint8_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movvint8_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movvint8_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movvint8_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movvint8_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movvint8_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movva8_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_movva8_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_movva8_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_movva8_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_movva8_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_movva8_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movva8_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movavu8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_movavu8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_movavu8_Slot_f0_s3_alu_encode, Opcode_ivp_movavu8_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_movavu8_Slot_f1_s3_alu_encode, Opcode_ivp_movavu8_Slot_f2_s0_ldst_encode, 0, 0, Opcode_ivp_movavu8_Slot_f2_s3_alu_encode, Opcode_ivp_movavu8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_movavu8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_movavu8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movavu8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movavu8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_slli2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_slli2nx8_Slot_f0_s3_alu_encode, 0, 0, Opcode_ivp_slli2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_slli2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_slli2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_slli2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_slli2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_slli2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slli2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_slli2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srai2nx8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_srai2nx8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_srai2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_srai2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_srai2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_srai2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_srai2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_srai2nx8_Slot_f2_s3_alu_encode, Opcode_ivp_srai2nx8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_srai2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srai2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srai2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srai2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_srli2nx8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_srli2nx8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_srli2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_srli2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_srli2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_srli2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_srli2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_srli2nx8_Slot_f2_s3_alu_encode, Opcode_ivp_srli2nx8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_srli2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_srli2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srli2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_srli2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_packl2nx24_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packl2nx24_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packl2nx24_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packl2nx24_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packl2nx24_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packl2nx24_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packl2nx24_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvr2nx24_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvr2nx24_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvr2nx24_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvr2nx24_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvr2nx24_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvr2nx24_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvr2nx24_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvru2nx24_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvru2nx24_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvru2nx24_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvru2nx24_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvru2nx24_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvru2nx24_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvru2nx24_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packlnx48_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packlnx48_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packlnx48_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packlnx48_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packlnx48_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packlnx48_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packlnx48_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packl2nx24_1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packl2nx24_1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packl2nx24_1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packl2nx24_1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packl2nx24_1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packl2nx24_1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packl2nx24_1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvr2nx24_0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvr2nx24_0_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvr2nx24_0_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvr2nx24_0_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvr2nx24_0_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvr2nx24_0_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvr2nx24_0_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvr2nx24_1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvr2nx24_1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvr2nx24_1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvr2nx24_1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvr2nx24_1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvr2nx24_1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvr2nx24_1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvru2nx24_0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvru2nx24_0_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvru2nx24_0_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvru2nx24_0_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvru2nx24_0_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvru2nx24_0_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvru2nx24_0_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvru2nx24_1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvru2nx24_1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvru2nx24_1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvru2nx24_1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvru2nx24_1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvru2nx24_1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvru2nx24_1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnr2nx24_0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnr2nx24_0_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnr2nx24_0_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnr2nx24_0_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnr2nx24_0_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnr2nx24_0_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnr2nx24_0_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnr2nx24_1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnr2nx24_1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnr2nx24_1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnr2nx24_1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnr2nx24_1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnr2nx24_1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnr2nx24_1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packmnx48_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packmnx48_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packmnx48_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packmnx48_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packmnx48_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packmnx48_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packmnx48_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnx48_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnx48_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnx48_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnx48_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnx48_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnx48_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnx48_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_unpks2nx8_0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_unpks2nx8_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_unpks2nx8_0_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_unpks2nx8_1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_unpks2nx8_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_unpks2nx8_1_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_unpksnx16_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_unpksnx16_l_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_unpksnx16_l_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_unpksnx16_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_unpksnx16_h_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_unpksnx16_h_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sel2nx8i_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8i_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_sel2nx8i_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_sel2nx8i_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_sel2nx8i_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_sel2nx8i_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8i_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8i_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sel2nx8i_s0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8i_s0_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8i_s0_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sel2nx8i_s2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8i_s2_Slot_f1_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sel2nx8i_s4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8i_s4_Slot_f3_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_shfl2nx8i_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_shfl2nx8i_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_shfl2nx8i_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_shfl2nx8i_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_shfl2nx8i_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_shfl2nx8i_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_shfl2nx8i_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_shfl2nx8i_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_shfl2nx8i_s0_encode_fns[] = { + 0, 0, 0, Opcode_ivp_shfl2nx8i_s0_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_shfl2nx8i_s0_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_shfl2nx8i_s0_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_shfl2nx8i_s0_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_shfl2nx8i_s0_Slot_n2_s0_ldst_encode, 0, Opcode_ivp_shfl2nx8i_s0_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_shfl2nx8i_s2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_shfl2nx8i_s2_Slot_f1_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_shfl2nx8i_s4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_shfl2nx8i_s4_Slot_f3_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_sel2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_sel2nx8_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_sel2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_shfl2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_shfl2nx8_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_shfl2nx8_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_shfl2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_shfl2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sel2nx8t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_sel2nx8t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_sel2nx8t_Slot_f2_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sel2nx8t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_sqzn_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_sqzn_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_sqzn_Slot_f1_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sqzn_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_sqzn_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_sqzn_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_unsqzn_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_unsqzn_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_unsqzn_Slot_f1_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_unsqzn_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_unsqzn_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_unsqzn_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulnx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulnx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulnx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulnx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulnx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulnx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulanx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulanx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulanx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulanx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulanx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulanx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulanx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluunx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluunx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluunx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluunx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluunx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluunx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluunx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluuanx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluuanx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuanx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuanx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuanx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluuanx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluuanx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusnx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusnx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusnx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusnx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusnx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusnx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusanx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusanx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusanx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusanx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusanx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusanx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusanx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mul2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mul2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mul2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mul2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mula2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mula2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mula2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mula2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mula2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mula2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mula2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addw2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addw2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addw2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addw2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addw2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addw2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_addw2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwa2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwa2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwa2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwa2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwa2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwa2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_addwa2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addws2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addws2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addws2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addws2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addws2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addws2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_addws2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwu2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwu2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwu2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwu2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwu2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_addwu2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwua2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwua2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwua2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwua2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwua2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwua2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_addwua2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwus2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwus2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwus2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwus2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwus2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwus2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_addwus2nx8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divn_2x32x16s_4step0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divn_2x32x16s_4step0_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divn_2x32x16s_4step_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divn_2x32x16s_4step_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divn_2x32x16s_4stepn_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divn_2x32x16s_4stepn_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divn_2x32x16u_4step0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divn_2x32x16u_4step0_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divn_2x32x16u_4step_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divn_2x32x16u_4step_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divn_2x32x16u_4stepn_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divn_2x32x16u_4stepn_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divnx16s_4step0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divnx16s_4step0_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divnx16s_4step_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divnx16s_4step_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divnx16s_4stepn_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divnx16s_4stepn_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divnx16u_4step0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divnx16u_4step0_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divnx16u_4step_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divnx16u_4step_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divnx16u_4stepn_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divnx16u_4stepn_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divnx16sq_4step0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divnx16sq_4step0_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_divnx16q_4step0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_divnx16q_4step0_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsnx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsnx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsnx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsnx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsnx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsnx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluusnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluusnx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluusnx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluusnx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluusnx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluusnx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluusnx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulussnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulussnx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulussnx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulussnx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulussnx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulussnx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulussnx16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muln_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muln_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muln_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muln_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muln_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muln_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muln_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluun_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluun_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluun_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluun_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluun_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluun_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluun_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusn_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsun_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muln_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muln_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muln_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muln_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muln_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muln_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muln_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluun_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluun_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluun_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluun_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluun_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluun_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluun_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsun_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsun_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulhn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulhn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulhn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulhn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulhn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulhn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulhn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluuhn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluuhn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuhn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuhn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuhn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluuhn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluuhn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulushn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulushn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulushn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulushn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulushn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulushn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulushn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsuhn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsuhn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuhn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuhn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuhn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsuhn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsuhn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulan_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulan_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulan_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulan_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulan_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulan_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulan_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluuan_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusan_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsuan_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulahn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulahn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulahn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulahn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulahn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulahn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulahn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluuahn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluuahn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuahn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuahn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuahn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluuahn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluuahn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusahn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusahn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusahn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusahn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusahn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusahn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusahn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsuahn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsuahn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuahn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuahn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuahn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsuahn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsuahn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulan_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulan_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulan_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulan_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulan_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulan_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulan_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluuan_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluuan_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusan_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusan_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsuan_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsuan_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulshn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulshn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulshn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulshn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulshn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulshn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulshn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluushn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluushn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluushn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluushn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluushn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluushn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluushn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusshn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusshn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusshn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusshn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusshn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusshn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusshn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsushn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsushn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsushn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsushn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsushn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsushn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsushn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsn_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluusn_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulussn_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsusn_2x16x32_0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_0_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_0_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_0_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_0_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_0_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluusn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluusn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulussn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulussn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulsusn_2x16x32_1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_1_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_1_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_1_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_1_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulsusn_2x16x32_1_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packln_2x96_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packln_2x96_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packln_2x96_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packln_2x96_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packln_2x96_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packln_2x96_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packln_2x96_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packhn_2x64w_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packhn_2x64w_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packhn_2x64w_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packhn_2x64w_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packhn_2x64w_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packhn_2x64w_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packhn_2x64w_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrn_2x64w_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrn_2x64w_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrn_2x64w_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrn_2x64w_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrn_2x64w_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrn_2x64w_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrn_2x64w_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnrn_2x64w_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnrn_2x64w_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrn_2x64w_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrn_2x64w_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrn_2x64w_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnrn_2x64w_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnrn_2x64w_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnx48_0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnx48_0_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnx48_0_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnx48_0_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnx48_0_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnx48_0_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnx48_0_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnx48_1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnx48_1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnx48_1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnx48_1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnx48_1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnx48_1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnx48_1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnrnx48_0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnrnx48_0_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrnx48_0_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrnx48_0_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrnx48_0_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnrnx48_0_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnrnx48_0_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnrnx48_1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnrnx48_1_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrnx48_1_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrnx48_1_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrnx48_1_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnrnx48_1_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnrnx48_1_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnrnx48_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnrnx48_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrnx48_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrnx48_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnrnx48_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnrnx48_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnrnx48_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_packvrnr2nx24_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_packvrnr2nx24_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnr2nx24_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnr2nx24_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_packvrnr2nx24_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_packvrnr2nx24_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_packvrnr2nx24_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_l2a4nx8_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_l2a4nx8_ip_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_l2au2nx8_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_l2au2nx8_ip_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_l2u2nx8_xp_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_l2u2nx8_xp_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_avgu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_avgu2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_avgu2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_avgu2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_avgu2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_avgu2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_avgu2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_avgu2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_avgu2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgu2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgu2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_avgru2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_avgru2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_avgru2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_avgru2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_avgru2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_avgru2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_avgru2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_avgru2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_avgru2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgru2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgru2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_radd2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_radd2nx8_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_radd2nx8_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_radd2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_radd2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_radd2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_radd2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_radd2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_radd2nx8t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_radd2nx8t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_radd2nx8t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_radd2nx8t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_radd2nx8t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_radd2nx8t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_radd2nx8t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_radd2nx8t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddunx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddunx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddunx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddunx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddunx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddunx16t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddunx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddunx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddunx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddunx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddunx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddunx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddu2nx8_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddu2nx8_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddu2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddu2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddu2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddu2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddu2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddu2nx8t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddu2nx8t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddu2nx8t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddu2nx8t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddu2nx8t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddu2nx8t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddu2nx8t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddu2nx8t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltrs2n_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ltrs2n_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrs2n_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrs2n_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrs2n_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ltrs2n_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrs2n_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrs2n_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltrsn_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ltrsn_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrsn_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrsn_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrsn_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ltrsn_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrsn_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrsn_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_ltrsn_2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ltrsn_2_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrsn_2_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrsn_2_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ltrsn_2_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ltrsn_2_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrsn_2_Slot_f11_s1_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ltrsn_2_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_seq2nx8_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_seq2nx8_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_seq2nx8_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_seq2nx8_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_seq2nx8_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_seq2nx8_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_seq2nx8_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_seqn_2x32_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_seqn_2x32_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_seqn_2x32_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_seqn_2x32_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_seqn_2x32_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_seqn_2x32_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_seqn_2x32_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_extrn_2x32_encode_fns[] = { + 0, 0, 0, Opcode_ivp_extrn_2x32_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_extrn_2x32_Slot_f0_s3_alu_encode, Opcode_ivp_extrn_2x32_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_extrn_2x32_Slot_f1_s3_alu_encode, Opcode_ivp_extrn_2x32_Slot_f2_s0_ldst_encode, 0, 0, Opcode_ivp_extrn_2x32_Slot_f2_s3_alu_encode, Opcode_ivp_extrn_2x32_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_extrn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_extrn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extrn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extrn_2x32_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_unpku2nx8_0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_unpku2nx8_0_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_unpku2nx8_0_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_unpku2nx8_1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_unpku2nx8_1_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_unpku2nx8_1_Slot_f2_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_baddnormnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_baddnormnx16_Slot_f0_s3_alu_encode, Opcode_ivp_baddnormnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_baddnormnx16_Slot_f1_s2_mul_encode, Opcode_ivp_baddnormnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_baddnormnx16_Slot_f2_s2_mul_encode, Opcode_ivp_baddnormnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_baddnormnx16_Slot_f3_s3_alu_encode, Opcode_ivp_baddnormnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_baddnormnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_baddnormnx16_Slot_f11_s3_alu_encode, Opcode_ivp_baddnormnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_baddnormnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_bsubnormnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_bsubnormnx16_Slot_f0_s3_alu_encode, Opcode_ivp_bsubnormnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_bsubnormnx16_Slot_f1_s2_mul_encode, Opcode_ivp_bsubnormnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_bsubnormnx16_Slot_f2_s2_mul_encode, Opcode_ivp_bsubnormnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_bsubnormnx16_Slot_f3_s3_alu_encode, Opcode_ivp_bsubnormnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_bsubnormnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bsubnormnx16_Slot_f11_s3_alu_encode, Opcode_ivp_bsubnormnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_bsubnormnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddsnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddsnx16_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddsnx16_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddsnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddsnx16_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddsnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddsnx16_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddsnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_raddsnx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_raddsnx16t_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddsnx16t_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddsnx16t_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_raddsnx16t_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_raddsnx16t_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddsnx16t_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_raddsnx16t_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_ornotb_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_ornotb_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_ornotb_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_ornotb_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_ornotb_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_ornotb_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_ornotb_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_extr2nx8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_extr2nx8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_extr2nx8_Slot_f0_s3_alu_encode, Opcode_ivp_extr2nx8_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_extr2nx8_Slot_f1_s3_alu_encode, Opcode_ivp_extr2nx8_Slot_f2_s0_ldst_encode, 0, 0, Opcode_ivp_extr2nx8_Slot_f2_s3_alu_encode, Opcode_ivp_extr2nx8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_extr2nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_extr2nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extr2nx8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_extr2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_extrvrn_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_extrvrn_2x32_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_ivp_extrvrn_2x32_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_ivp_extrvrn_2x32_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_extrvrn_2x32_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_extrvrn_2x32_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, Opcode_ivp_extrvrn_2x32_Slot_f11_s2_mul_encode, Opcode_ivp_extrvrn_2x32_Slot_f11_s3_alu_encode, 0, 0, 0, Opcode_ivp_extrvrn_2x32_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movav8_encode_fns[] = { + 0, 0, 0, Opcode_ivp_movav8_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_movav8_Slot_f0_s3_alu_encode, Opcode_ivp_movav8_Slot_f1_s0_ldstalu_encode, 0, 0, Opcode_ivp_movav8_Slot_f1_s3_alu_encode, Opcode_ivp_movav8_Slot_f2_s0_ldst_encode, 0, 0, Opcode_ivp_movav8_Slot_f2_s3_alu_encode, Opcode_ivp_movav8_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_movav8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_movav8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movav8_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movav8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulpn16xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulpn16xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulpn16xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulpn16xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulpn16xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulpn16xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulpn16xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulpan16xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulpan16xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulpan16xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulpan16xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulpan16xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulpan16xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulpan16xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluspn16xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluspn16xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluspn16xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluspn16xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluspn16xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluspn16xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluspn16xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluspan16xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluspan16xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluspan16xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluspan16xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluspan16xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluspan16xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluspan16xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulp2n8xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulp2n8xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulp2n8xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulp2n8xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulp2n8xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulp2n8xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulp2n8xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulpa2n8xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulpa2n8xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulpa2n8xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulpa2n8xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulpa2n8xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulpa2n8xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulpa2n8xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusp2n8xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulusp2n8xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusp2n8xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusp2n8xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulusp2n8xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusp2n8xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulusp2n8xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluspa2n8xr16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_muluspa2n8xr16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluspa2n8xr16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluspa2n8xr16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_muluspa2n8xr16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluspa2n8xr16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_muluspa2n8xr16_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulpnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulpnx16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulpanx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulpanx16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluspnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluspnx16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluspanx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluspanx16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluupnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluupnx16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluupanx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluupanx16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulp2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulp2nx8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulpa2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulpa2nx8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusp2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusp2nx8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluspa2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluspa2nx8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluup2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluup2nx8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluupa2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluupa2nx8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulpi2nr8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulpi2nr8x16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulpai2nr8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulpai2nr8x16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluspi2nr8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluspi2nr8x16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_muluspai2nr8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_muluspai2nr8x16_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulq2n8xr8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulq2n8xr8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulqa2n8xr8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulqa2n8xr8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusq2n8xr8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusq2n8xr8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulusqa2n8xr8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulusqa2n8xr8_Slot_f4_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mul4t2n8xr8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mul4t2n8xr8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul4t2n8xr8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul4t2n8xr8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul4t2n8xr8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mul4t2n8xr8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mul4t2n8xr8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mul4ta2n8xr8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mul4ta2n8xr8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul4ta2n8xr8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul4ta2n8xr8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mul4ta2n8xr8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mul4ta2n8xr8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mul4ta2n8xr8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulus4t2n8xr8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulus4t2n8xr8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus4t2n8xr8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus4t2n8xr8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus4t2n8xr8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulus4t2n8xr8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulus4t2n8xr8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_mulus4ta2n8xr8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_mulus4ta2n8xr8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus4ta2n8xr8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus4ta2n8xr8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_mulus4ta2n8xr8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_mulus4ta2n8xr8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, Opcode_ivp_mulus4ta2n8xr8_Slot_n1_s2_mul_encode, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwnx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwnx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwnx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwnx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwnx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwanx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwanx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwanx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwanx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwanx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwanx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwsnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwsnx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwsnx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwsnx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwsnx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwsnx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwunx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwunx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwunx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwunx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwunx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwunx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwuanx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwuanx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwuanx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwuanx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwuanx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwuanx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_addwusnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_addwusnx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwusnx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwusnx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_addwusnx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_addwusnx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_subwnx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_subwnx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwnx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwnx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwnx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subwnx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_subwanx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_subwanx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwanx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwanx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwanx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subwanx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_subwunx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_subwunx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwunx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwunx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwunx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subwunx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_subwuanx16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_subwuanx16_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwuanx16_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwuanx16_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwuanx16_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subwuanx16_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_subw2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_subw2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_subw2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_subw2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_subw2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subw2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_subwa2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_subwa2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwa2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwa2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwa2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subwa2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_subwu2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_subwu2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwu2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwu2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwu2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subwu2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_subwua2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ivp_subwua2nx8_Slot_f0_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwua2nx8_Slot_f1_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwua2nx8_Slot_f2_s2_mul_encode, 0, 0, 0, Opcode_ivp_subwua2nx8_Slot_f3_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_subwua2nx8_Slot_f11_s2_mul_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_randb2n_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_randb2n_Slot_f0_s1_ld_encode, 0, Opcode_ivp_randb2n_Slot_f0_s3_alu_encode, 0, Opcode_ivp_randb2n_Slot_f1_s1_ld_encode, 0, Opcode_ivp_randb2n_Slot_f1_s3_alu_encode, 0, Opcode_ivp_randb2n_Slot_f2_s1_ld_encode, 0, Opcode_ivp_randb2n_Slot_f2_s3_alu_encode, 0, Opcode_ivp_randb2n_Slot_f3_s1_ld_encode, 0, Opcode_ivp_randb2n_Slot_f3_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_randb2n_Slot_f11_s1_alu_encode, 0, Opcode_ivp_randb2n_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_randb2n_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_rorb2n_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_rorb2n_Slot_f0_s1_ld_encode, 0, Opcode_ivp_rorb2n_Slot_f0_s3_alu_encode, 0, Opcode_ivp_rorb2n_Slot_f1_s1_ld_encode, 0, Opcode_ivp_rorb2n_Slot_f1_s3_alu_encode, 0, Opcode_ivp_rorb2n_Slot_f2_s1_ld_encode, 0, Opcode_ivp_rorb2n_Slot_f2_s3_alu_encode, 0, Opcode_ivp_rorb2n_Slot_f3_s1_ld_encode, 0, Opcode_ivp_rorb2n_Slot_f3_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rorb2n_Slot_f11_s1_alu_encode, 0, Opcode_ivp_rorb2n_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_rorb2n_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_randbn_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_randbn_Slot_f0_s1_ld_encode, 0, Opcode_ivp_randbn_Slot_f0_s3_alu_encode, 0, Opcode_ivp_randbn_Slot_f1_s1_ld_encode, 0, Opcode_ivp_randbn_Slot_f1_s3_alu_encode, 0, Opcode_ivp_randbn_Slot_f2_s1_ld_encode, 0, Opcode_ivp_randbn_Slot_f2_s3_alu_encode, 0, Opcode_ivp_randbn_Slot_f3_s1_ld_encode, 0, Opcode_ivp_randbn_Slot_f3_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_randbn_Slot_f11_s1_alu_encode, 0, Opcode_ivp_randbn_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_randbn_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_rorbn_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_rorbn_Slot_f0_s1_ld_encode, 0, Opcode_ivp_rorbn_Slot_f0_s3_alu_encode, 0, Opcode_ivp_rorbn_Slot_f1_s1_ld_encode, 0, Opcode_ivp_rorbn_Slot_f1_s3_alu_encode, 0, Opcode_ivp_rorbn_Slot_f2_s1_ld_encode, 0, Opcode_ivp_rorbn_Slot_f2_s3_alu_encode, 0, Opcode_ivp_rorbn_Slot_f3_s1_ld_encode, 0, Opcode_ivp_rorbn_Slot_f3_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rorbn_Slot_f11_s1_alu_encode, 0, Opcode_ivp_rorbn_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_rorbn_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_randbn_2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_randbn_2_Slot_f0_s1_ld_encode, 0, Opcode_ivp_randbn_2_Slot_f0_s3_alu_encode, 0, Opcode_ivp_randbn_2_Slot_f1_s1_ld_encode, 0, Opcode_ivp_randbn_2_Slot_f1_s3_alu_encode, 0, Opcode_ivp_randbn_2_Slot_f2_s1_ld_encode, 0, Opcode_ivp_randbn_2_Slot_f2_s3_alu_encode, 0, Opcode_ivp_randbn_2_Slot_f3_s1_ld_encode, 0, Opcode_ivp_randbn_2_Slot_f3_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_randbn_2_Slot_f11_s1_alu_encode, 0, Opcode_ivp_randbn_2_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_randbn_2_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_rorbn_2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_rorbn_2_Slot_f0_s1_ld_encode, 0, Opcode_ivp_rorbn_2_Slot_f0_s3_alu_encode, 0, Opcode_ivp_rorbn_2_Slot_f1_s1_ld_encode, 0, Opcode_ivp_rorbn_2_Slot_f1_s3_alu_encode, 0, Opcode_ivp_rorbn_2_Slot_f2_s1_ld_encode, 0, Opcode_ivp_rorbn_2_Slot_f2_s3_alu_encode, 0, Opcode_ivp_rorbn_2_Slot_f3_s1_ld_encode, 0, Opcode_ivp_rorbn_2_Slot_f3_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_rorbn_2_Slot_f11_s1_alu_encode, 0, Opcode_ivp_rorbn_2_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, Opcode_ivp_rorbn_2_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_avgnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_avgnx16_Slot_f0_s3_alu_encode, Opcode_ivp_avgnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_avgnx16_Slot_f1_s2_mul_encode, Opcode_ivp_avgnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_avgnx16_Slot_f2_s2_mul_encode, Opcode_ivp_avgnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_avgnx16_Slot_f3_s3_alu_encode, Opcode_ivp_avgnx16_Slot_f3_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgnx16_Slot_f11_s3_alu_encode, Opcode_ivp_avgnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_avgunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_avgunx16_Slot_f0_s3_alu_encode, Opcode_ivp_avgunx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_avgunx16_Slot_f1_s2_mul_encode, Opcode_ivp_avgunx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_avgunx16_Slot_f2_s2_mul_encode, Opcode_ivp_avgunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_avgunx16_Slot_f3_s3_alu_encode, Opcode_ivp_avgunx16_Slot_f3_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgunx16_Slot_f11_s3_alu_encode, Opcode_ivp_avgunx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_avg2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avg2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_avg2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_avg2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_avg2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_avg2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_avg2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_avg2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avg2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_avg2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avg2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_avgr2nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgr2nx8_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_avgr2nx8_Slot_f1_s2_mul_encode, Opcode_ivp_avgr2nx8_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_avgr2nx8_Slot_f2_s2_mul_encode, Opcode_ivp_avgr2nx8_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_avgr2nx8_Slot_f3_s3_alu_encode, Opcode_ivp_avgr2nx8_Slot_f3_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgr2nx8_Slot_f11_s3_alu_encode, Opcode_ivp_avgr2nx8_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgr2nx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_avgrnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_avgrnx16_Slot_f0_s3_alu_encode, Opcode_ivp_avgrnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_avgrnx16_Slot_f1_s2_mul_encode, Opcode_ivp_avgrnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_avgrnx16_Slot_f2_s2_mul_encode, Opcode_ivp_avgrnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_avgrnx16_Slot_f3_s3_alu_encode, Opcode_ivp_avgrnx16_Slot_f3_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgrnx16_Slot_f11_s3_alu_encode, Opcode_ivp_avgrnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgrnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_avgrunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_avgrunx16_Slot_f0_s3_alu_encode, Opcode_ivp_avgrunx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_avgrunx16_Slot_f1_s2_mul_encode, Opcode_ivp_avgrunx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_avgrunx16_Slot_f2_s2_mul_encode, Opcode_ivp_avgrunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_avgrunx16_Slot_f3_s3_alu_encode, Opcode_ivp_avgrunx16_Slot_f3_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgrunx16_Slot_f11_s3_alu_encode, Opcode_ivp_avgrunx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_avgrunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatheranx8u_encode_fns[] = { + 0, 0, 0, Opcode_ivp_gatheranx8u_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheranx8u_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_gatheranx8u_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheranx8u_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatheranx8u_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_gatheranx8u_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatheranx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_gatheranx16_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheranx16_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_gatheranx16_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheranx16_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatheranx16_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_gatheranx16_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatheran_2x32_encode_fns[] = { + 0, 0, 0, Opcode_ivp_gatheran_2x32_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheran_2x32_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_gatheran_2x32_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheran_2x32_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatheran_2x32_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_gatheran_2x32_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatheranx8ut_encode_fns[] = { + 0, 0, 0, Opcode_ivp_gatheranx8ut_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheranx8ut_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_gatheranx8ut_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheranx8ut_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatheranx8ut_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_gatheranx8ut_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatheranx16t_encode_fns[] = { + 0, 0, 0, Opcode_ivp_gatheranx16t_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheranx16t_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_gatheranx16t_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheranx16t_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatheranx16t_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_gatheranx16t_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatheran_2x32t_encode_fns[] = { + 0, 0, 0, Opcode_ivp_gatheran_2x32t_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheran_2x32t_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_gatheran_2x32t_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_gatheran_2x32t_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatheran_2x32t_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_gatheran_2x32t_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatherdnx16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_gatherdnx16_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherdnx16_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherdnx16_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherdnx16_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_gatherdnx16_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatherdnx16_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatherdnx8s_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_gatherdnx8s_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherdnx8s_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherdnx8s_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherdnx8s_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_gatherdnx8s_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatherdnx8s_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatherd2nx8_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_gatherd2nx8_l_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherd2nx8_l_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherd2nx8_l_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherd2nx8_l_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_gatherd2nx8_l_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatherd2nx8_l_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_gatherd2nx8_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ivp_gatherd2nx8_h_Slot_f0_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherd2nx8_h_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherd2nx8_h_Slot_f2_s1_ld_encode, 0, 0, 0, Opcode_ivp_gatherd2nx8_h_Slot_f3_s1_ld_encode, 0, 0, 0, 0, Opcode_ivp_gatherd2nx8_h_Slot_f4_s1_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_gatherd2nx8_h_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_movgatherd_encode_fns[] = { + 0, 0, 0, Opcode_ivp_movgatherd_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_movgatherd_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_movgatherd_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_movgatherd_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_movgatherd_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_movgatherd_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scatternx8u_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatternx8u_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatternx8u_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scatter2nx8_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatter2nx8_l_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatter2nx8_l_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scatter2nx8_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatter2nx8_h_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatter2nx8_h_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scatternx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatternx16_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatternx16_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scattern_2x32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scattern_2x32_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scattern_2x32_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scatternx8ut_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatternx8ut_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatternx8ut_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scatter2nx8t_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatter2nx8t_l_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatter2nx8t_l_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scatter2nx8t_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatter2nx8t_h_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatter2nx8t_h_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scatternx16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatternx16t_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatternx16t_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scattern_2x32t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scattern_2x32t_Slot_f1_s0_ldstalu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scattern_2x32t_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_scatterw_encode_fns[] = { + 0, 0, 0, Opcode_ivp_scatterw_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_scatterw_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ivp_scatterw_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ivp_scatterw_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_scatterw_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_scatterw_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ivp_scatterw_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_counteqz4nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_counteqz4nx8_Slot_f1_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_counteqz4nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_counteqz4nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_counteq4nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_counteq4nx8_Slot_f1_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_counteq4nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_counteq4nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_counteqmz4nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_counteqmz4nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_counteqmz4nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_counteqm4nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_counteqm4nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_counteqm4nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_countlez4nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_countlez4nx8_Slot_f1_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_countlez4nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_countlez4nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_countle4nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_countle4nx8_Slot_f1_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_countle4nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_countle4nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_countlemz4nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_countlemz4nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_countlemz4nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_countlem4nx8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_countlem4nx8_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_ivp_countlem4nx8_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsr2nx8_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsr2nx8_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsr2nx8_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsr2nx8_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsr2nx8_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsr2nx8_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsr2nx8_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsr2nx8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsr2nx8_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsr2nx8_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsr2nx8_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsr2nx8_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsr2nx8_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsr2nx8_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsr2nx8_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsr2nx8_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsr2nx8_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsr2nx8_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsr2nx8_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsr2nx8_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsr2nx8_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsr2nx8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsr2nx8_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsr2nx8_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsr2nx8_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsr2nx8_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsr2nx8_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsr2nx8_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsrnx16_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsrnx16_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsrnx16_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsrnx16_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsrnx16_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsrnx16_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsrnx16_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsrnx16_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsrnx16_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsrnx16_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsrnx16_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsrnx16_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsrnx16_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsrnx16_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsrnx16_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsrnx16_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsrnx16_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsrnx16_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsrnx16_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsrnx16_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsrnx16_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsrnx16_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsrnx16_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsrnx16_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsrnx16_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsrnx16_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsrnx16_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsrnx16_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsrn_2x32_i_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsrn_2x32_i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsrn_2x32_i_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsrn_2x32_i_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsrn_2x32_i_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsrn_2x32_i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsrn_2x32_i_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsrn_2x32_ip_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsrn_2x32_ip_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsrn_2x32_ip_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsrn_2x32_ip_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsrn_2x32_ip_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsrn_2x32_ip_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsrn_2x32_ip_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsrn_2x32_x_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsrn_2x32_x_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsrn_2x32_x_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsrn_2x32_x_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsrn_2x32_x_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsrn_2x32_x_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsrn_2x32_x_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_lsrn_2x32_xp_encode_fns[] = { + 0, 0, 0, Opcode_ivp_lsrn_2x32_xp_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ivp_lsrn_2x32_xp_Slot_f1_s0_ldstalu_encode, Opcode_ivp_lsrn_2x32_xp_Slot_f1_s1_ld_encode, 0, 0, 0, Opcode_ivp_lsrn_2x32_xp_Slot_f2_s1_ld_encode, 0, 0, Opcode_ivp_lsrn_2x32_xp_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ivp_lsrn_2x32_xp_Slot_f4_s0_ld_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ivp_absnx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_absnx16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_absnx16_Slot_f0_s3_alu_encode, Opcode_ivp_absnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_absnx16_Slot_f1_s2_mul_encode, Opcode_ivp_absnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_absnx16_Slot_f2_s2_mul_encode, Opcode_ivp_absnx16_Slot_f2_s3_alu_encode, Opcode_ivp_absnx16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_absnx16_Slot_f3_s3_alu_encode, Opcode_ivp_absnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_absnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_absnx16_Slot_f11_s3_alu_encode, Opcode_ivp_absnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_absnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_abssnx16_encode_fns[] = { + 0, 0, 0, Opcode_ivp_abssnx16_Slot_f0_s0_ldst_encode, 0, 0, Opcode_ivp_abssnx16_Slot_f0_s3_alu_encode, Opcode_ivp_abssnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_abssnx16_Slot_f1_s2_mul_encode, Opcode_ivp_abssnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_abssnx16_Slot_f2_s2_mul_encode, Opcode_ivp_abssnx16_Slot_f2_s3_alu_encode, Opcode_ivp_abssnx16_Slot_f3_s0_ldst_encode, 0, 0, Opcode_ivp_abssnx16_Slot_f3_s3_alu_encode, Opcode_ivp_abssnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_abssnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssnx16_Slot_f11_s3_alu_encode, Opcode_ivp_abssnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_abssubnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_abssubnx16_Slot_f0_s3_alu_encode, Opcode_ivp_abssubnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_abssubnx16_Slot_f1_s2_mul_encode, Opcode_ivp_abssubnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_abssubnx16_Slot_f2_s2_mul_encode, Opcode_ivp_abssubnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_abssubnx16_Slot_f3_s3_alu_encode, Opcode_ivp_abssubnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_abssubnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssubnx16_Slot_f11_s3_alu_encode, Opcode_ivp_abssubnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssubnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_abssubunx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_abssubunx16_Slot_f0_s3_alu_encode, Opcode_ivp_abssubunx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_abssubunx16_Slot_f1_s2_mul_encode, Opcode_ivp_abssubunx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_abssubunx16_Slot_f2_s2_mul_encode, Opcode_ivp_abssubunx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_abssubunx16_Slot_f3_s3_alu_encode, Opcode_ivp_abssubunx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_abssubunx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssubunx16_Slot_f11_s3_alu_encode, Opcode_ivp_abssubunx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_abssubunx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_ivp_absssubnx16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ivp_absssubnx16_Slot_f0_s3_alu_encode, Opcode_ivp_absssubnx16_Slot_f1_s0_ldstalu_encode, 0, Opcode_ivp_absssubnx16_Slot_f1_s2_mul_encode, Opcode_ivp_absssubnx16_Slot_f1_s3_alu_encode, 0, 0, Opcode_ivp_absssubnx16_Slot_f2_s2_mul_encode, Opcode_ivp_absssubnx16_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_ivp_absssubnx16_Slot_f3_s3_alu_encode, Opcode_ivp_absssubnx16_Slot_f3_s4_alu_encode, 0, 0, 0, Opcode_ivp_absssubnx16_Slot_f4_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_absssubnx16_Slot_f11_s3_alu_encode, Opcode_ivp_absssubnx16_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ivp_absssubnx16_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l32i_n_Slot_n1_s0_ldst_encode, 0, 0, Opcode_l32i_n_Slot_n2_s0_ldst_encode, Opcode_l32i_n_Slot_n2_s1_ld_encode, Opcode_l32i_n_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0, 0, Opcode_mov_n_Slot_f0_s3_alu_encode, 0, 0, 0, Opcode_mov_n_Slot_f1_s3_alu_encode, 0, 0, 0, Opcode_mov_n_Slot_f2_s3_alu_encode, 0, 0, 0, Opcode_mov_n_Slot_f3_s3_alu_encode, 0, 0, 0, 0, Opcode_mov_n_Slot_f4_s3_alu_encode, 0, 0, 0, Opcode_mov_n_Slot_f5_s3_base_encode, 0, 0, 0, Opcode_mov_n_Slot_f11_s3_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s32i_n_Slot_n1_s0_ldst_encode, 0, 0, Opcode_s32i_n_Slot_n2_s0_ldst_encode, 0, Opcode_s32i_n_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { + Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { + Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0, Opcode_addi_Slot_f0_s0_ldst_encode, Opcode_addi_Slot_f0_s1_ld_encode, Opcode_addi_Slot_f0_s2_mul_encode, Opcode_addi_Slot_f0_s3_alu_encode, Opcode_addi_Slot_f1_s0_ldstalu_encode, Opcode_addi_Slot_f1_s1_ld_encode, Opcode_addi_Slot_f1_s2_mul_encode, Opcode_addi_Slot_f1_s3_alu_encode, Opcode_addi_Slot_f2_s0_ldst_encode, Opcode_addi_Slot_f2_s1_ld_encode, Opcode_addi_Slot_f2_s2_mul_encode, Opcode_addi_Slot_f2_s3_alu_encode, Opcode_addi_Slot_f3_s0_ldst_encode, Opcode_addi_Slot_f3_s1_ld_encode, Opcode_addi_Slot_f3_s2_mul_encode, Opcode_addi_Slot_f3_s3_alu_encode, 0, Opcode_addi_Slot_f4_s0_ld_encode, Opcode_addi_Slot_f4_s1_ld_encode, 0, Opcode_addi_Slot_f4_s3_alu_encode, Opcode_addi_Slot_f5_s0_base_encode, Opcode_addi_Slot_f5_s1_base_encode, Opcode_addi_Slot_f5_s2_base_encode, Opcode_addi_Slot_f5_s3_base_encode, Opcode_addi_Slot_f11_s0_ld_encode, Opcode_addi_Slot_f11_s1_alu_encode, Opcode_addi_Slot_f11_s2_mul_encode, Opcode_addi_Slot_f11_s3_alu_encode, 0, Opcode_addi_Slot_n1_s0_ldst_encode, 0, Opcode_addi_Slot_n1_s2_mul_encode, Opcode_addi_Slot_n2_s0_ldst_encode, Opcode_addi_Slot_n2_s1_ld_encode, Opcode_addi_Slot_n0_s0_ldst_encode, 0, 0, Opcode_addi_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0, Opcode_addmi_Slot_f0_s0_ldst_encode, Opcode_addmi_Slot_f0_s1_ld_encode, 0, 0, Opcode_addmi_Slot_f1_s0_ldstalu_encode, Opcode_addmi_Slot_f1_s1_ld_encode, 0, 0, Opcode_addmi_Slot_f2_s0_ldst_encode, Opcode_addmi_Slot_f2_s1_ld_encode, 0, 0, Opcode_addmi_Slot_f3_s0_ldst_encode, Opcode_addmi_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_addmi_Slot_f4_s0_ld_encode, Opcode_addmi_Slot_f4_s1_ld_encode, 0, 0, Opcode_addmi_Slot_f5_s0_base_encode, Opcode_addmi_Slot_f5_s1_base_encode, Opcode_addmi_Slot_f5_s2_base_encode, 0, Opcode_addmi_Slot_f11_s0_ld_encode, Opcode_addmi_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_addmi_Slot_n1_s0_ldst_encode, 0, 0, Opcode_addmi_Slot_n2_s0_ldst_encode, Opcode_addmi_Slot_n2_s1_ld_encode, Opcode_addmi_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_f0_s0_ldst_encode, Opcode_add_Slot_f0_s1_ld_encode, Opcode_add_Slot_f0_s2_mul_encode, 0, Opcode_add_Slot_f1_s0_ldstalu_encode, Opcode_add_Slot_f1_s1_ld_encode, Opcode_add_Slot_f1_s2_mul_encode, 0, Opcode_add_Slot_f2_s0_ldst_encode, Opcode_add_Slot_f2_s1_ld_encode, Opcode_add_Slot_f2_s2_mul_encode, 0, Opcode_add_Slot_f3_s0_ldst_encode, Opcode_add_Slot_f3_s1_ld_encode, Opcode_add_Slot_f3_s2_mul_encode, 0, 0, Opcode_add_Slot_f4_s0_ld_encode, Opcode_add_Slot_f4_s1_ld_encode, 0, 0, Opcode_add_Slot_f5_s0_base_encode, Opcode_add_Slot_f5_s1_base_encode, Opcode_add_Slot_f5_s2_base_encode, 0, Opcode_add_Slot_f11_s0_ld_encode, Opcode_add_Slot_f11_s1_alu_encode, Opcode_add_Slot_f11_s2_mul_encode, 0, 0, Opcode_add_Slot_n1_s0_ldst_encode, 0, Opcode_add_Slot_n1_s2_mul_encode, Opcode_add_Slot_n2_s0_ldst_encode, Opcode_add_Slot_n2_s1_ld_encode, Opcode_add_Slot_n0_s0_ldst_encode, 0, 0, Opcode_add_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_f0_s0_ldst_encode, Opcode_sub_Slot_f0_s1_ld_encode, Opcode_sub_Slot_f0_s2_mul_encode, 0, Opcode_sub_Slot_f1_s0_ldstalu_encode, Opcode_sub_Slot_f1_s1_ld_encode, Opcode_sub_Slot_f1_s2_mul_encode, 0, Opcode_sub_Slot_f2_s0_ldst_encode, Opcode_sub_Slot_f2_s1_ld_encode, Opcode_sub_Slot_f2_s2_mul_encode, 0, Opcode_sub_Slot_f3_s0_ldst_encode, Opcode_sub_Slot_f3_s1_ld_encode, Opcode_sub_Slot_f3_s2_mul_encode, 0, 0, Opcode_sub_Slot_f4_s0_ld_encode, Opcode_sub_Slot_f4_s1_ld_encode, 0, 0, Opcode_sub_Slot_f5_s0_base_encode, Opcode_sub_Slot_f5_s1_base_encode, Opcode_sub_Slot_f5_s2_base_encode, 0, Opcode_sub_Slot_f11_s0_ld_encode, Opcode_sub_Slot_f11_s1_alu_encode, Opcode_sub_Slot_f11_s2_mul_encode, 0, 0, Opcode_sub_Slot_n1_s0_ldst_encode, 0, Opcode_sub_Slot_n1_s2_mul_encode, Opcode_sub_Slot_n2_s0_ldst_encode, Opcode_sub_Slot_n2_s1_ld_encode, Opcode_sub_Slot_n0_s0_ldst_encode, 0, 0, Opcode_sub_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0, Opcode_addx2_Slot_f0_s0_ldst_encode, Opcode_addx2_Slot_f0_s1_ld_encode, Opcode_addx2_Slot_f0_s2_mul_encode, 0, Opcode_addx2_Slot_f1_s0_ldstalu_encode, Opcode_addx2_Slot_f1_s1_ld_encode, Opcode_addx2_Slot_f1_s2_mul_encode, 0, Opcode_addx2_Slot_f2_s0_ldst_encode, Opcode_addx2_Slot_f2_s1_ld_encode, Opcode_addx2_Slot_f2_s2_mul_encode, 0, Opcode_addx2_Slot_f3_s0_ldst_encode, Opcode_addx2_Slot_f3_s1_ld_encode, Opcode_addx2_Slot_f3_s2_mul_encode, 0, 0, Opcode_addx2_Slot_f4_s0_ld_encode, Opcode_addx2_Slot_f4_s1_ld_encode, 0, 0, Opcode_addx2_Slot_f5_s0_base_encode, Opcode_addx2_Slot_f5_s1_base_encode, Opcode_addx2_Slot_f5_s2_base_encode, 0, Opcode_addx2_Slot_f11_s0_ld_encode, Opcode_addx2_Slot_f11_s1_alu_encode, Opcode_addx2_Slot_f11_s2_mul_encode, 0, 0, Opcode_addx2_Slot_n1_s0_ldst_encode, 0, Opcode_addx2_Slot_n1_s2_mul_encode, Opcode_addx2_Slot_n2_s0_ldst_encode, Opcode_addx2_Slot_n2_s1_ld_encode, Opcode_addx2_Slot_n0_s0_ldst_encode, 0, 0, Opcode_addx2_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0, Opcode_addx4_Slot_f0_s0_ldst_encode, Opcode_addx4_Slot_f0_s1_ld_encode, Opcode_addx4_Slot_f0_s2_mul_encode, 0, Opcode_addx4_Slot_f1_s0_ldstalu_encode, Opcode_addx4_Slot_f1_s1_ld_encode, Opcode_addx4_Slot_f1_s2_mul_encode, 0, Opcode_addx4_Slot_f2_s0_ldst_encode, Opcode_addx4_Slot_f2_s1_ld_encode, Opcode_addx4_Slot_f2_s2_mul_encode, 0, Opcode_addx4_Slot_f3_s0_ldst_encode, Opcode_addx4_Slot_f3_s1_ld_encode, Opcode_addx4_Slot_f3_s2_mul_encode, 0, 0, Opcode_addx4_Slot_f4_s0_ld_encode, Opcode_addx4_Slot_f4_s1_ld_encode, 0, 0, Opcode_addx4_Slot_f5_s0_base_encode, Opcode_addx4_Slot_f5_s1_base_encode, Opcode_addx4_Slot_f5_s2_base_encode, 0, Opcode_addx4_Slot_f11_s0_ld_encode, Opcode_addx4_Slot_f11_s1_alu_encode, Opcode_addx4_Slot_f11_s2_mul_encode, 0, 0, Opcode_addx4_Slot_n1_s0_ldst_encode, 0, Opcode_addx4_Slot_n1_s2_mul_encode, Opcode_addx4_Slot_n2_s0_ldst_encode, Opcode_addx4_Slot_n2_s1_ld_encode, Opcode_addx4_Slot_n0_s0_ldst_encode, 0, 0, Opcode_addx4_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0, Opcode_addx8_Slot_f0_s0_ldst_encode, Opcode_addx8_Slot_f0_s1_ld_encode, Opcode_addx8_Slot_f0_s2_mul_encode, 0, Opcode_addx8_Slot_f1_s0_ldstalu_encode, Opcode_addx8_Slot_f1_s1_ld_encode, Opcode_addx8_Slot_f1_s2_mul_encode, 0, Opcode_addx8_Slot_f2_s0_ldst_encode, Opcode_addx8_Slot_f2_s1_ld_encode, Opcode_addx8_Slot_f2_s2_mul_encode, 0, Opcode_addx8_Slot_f3_s0_ldst_encode, Opcode_addx8_Slot_f3_s1_ld_encode, Opcode_addx8_Slot_f3_s2_mul_encode, 0, 0, Opcode_addx8_Slot_f4_s0_ld_encode, Opcode_addx8_Slot_f4_s1_ld_encode, 0, 0, Opcode_addx8_Slot_f5_s0_base_encode, Opcode_addx8_Slot_f5_s1_base_encode, Opcode_addx8_Slot_f5_s2_base_encode, 0, Opcode_addx8_Slot_f11_s0_ld_encode, Opcode_addx8_Slot_f11_s1_alu_encode, Opcode_addx8_Slot_f11_s2_mul_encode, 0, 0, Opcode_addx8_Slot_n1_s0_ldst_encode, 0, Opcode_addx8_Slot_n1_s2_mul_encode, Opcode_addx8_Slot_n2_s0_ldst_encode, Opcode_addx8_Slot_n2_s1_ld_encode, Opcode_addx8_Slot_n0_s0_ldst_encode, 0, 0, Opcode_addx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0, Opcode_subx2_Slot_f0_s0_ldst_encode, Opcode_subx2_Slot_f0_s1_ld_encode, Opcode_subx2_Slot_f0_s2_mul_encode, 0, Opcode_subx2_Slot_f1_s0_ldstalu_encode, Opcode_subx2_Slot_f1_s1_ld_encode, Opcode_subx2_Slot_f1_s2_mul_encode, 0, Opcode_subx2_Slot_f2_s0_ldst_encode, Opcode_subx2_Slot_f2_s1_ld_encode, Opcode_subx2_Slot_f2_s2_mul_encode, 0, Opcode_subx2_Slot_f3_s0_ldst_encode, Opcode_subx2_Slot_f3_s1_ld_encode, Opcode_subx2_Slot_f3_s2_mul_encode, 0, 0, Opcode_subx2_Slot_f4_s0_ld_encode, Opcode_subx2_Slot_f4_s1_ld_encode, 0, 0, Opcode_subx2_Slot_f5_s0_base_encode, Opcode_subx2_Slot_f5_s1_base_encode, Opcode_subx2_Slot_f5_s2_base_encode, 0, Opcode_subx2_Slot_f11_s0_ld_encode, Opcode_subx2_Slot_f11_s1_alu_encode, Opcode_subx2_Slot_f11_s2_mul_encode, 0, 0, Opcode_subx2_Slot_n1_s0_ldst_encode, 0, Opcode_subx2_Slot_n1_s2_mul_encode, Opcode_subx2_Slot_n2_s0_ldst_encode, Opcode_subx2_Slot_n2_s1_ld_encode, Opcode_subx2_Slot_n0_s0_ldst_encode, 0, 0, Opcode_subx2_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0, Opcode_subx4_Slot_f0_s0_ldst_encode, Opcode_subx4_Slot_f0_s1_ld_encode, Opcode_subx4_Slot_f0_s2_mul_encode, 0, Opcode_subx4_Slot_f1_s0_ldstalu_encode, Opcode_subx4_Slot_f1_s1_ld_encode, Opcode_subx4_Slot_f1_s2_mul_encode, 0, Opcode_subx4_Slot_f2_s0_ldst_encode, Opcode_subx4_Slot_f2_s1_ld_encode, Opcode_subx4_Slot_f2_s2_mul_encode, 0, Opcode_subx4_Slot_f3_s0_ldst_encode, Opcode_subx4_Slot_f3_s1_ld_encode, Opcode_subx4_Slot_f3_s2_mul_encode, 0, 0, Opcode_subx4_Slot_f4_s0_ld_encode, Opcode_subx4_Slot_f4_s1_ld_encode, 0, 0, Opcode_subx4_Slot_f5_s0_base_encode, Opcode_subx4_Slot_f5_s1_base_encode, Opcode_subx4_Slot_f5_s2_base_encode, 0, Opcode_subx4_Slot_f11_s0_ld_encode, Opcode_subx4_Slot_f11_s1_alu_encode, Opcode_subx4_Slot_f11_s2_mul_encode, 0, 0, Opcode_subx4_Slot_n1_s0_ldst_encode, 0, Opcode_subx4_Slot_n1_s2_mul_encode, Opcode_subx4_Slot_n2_s0_ldst_encode, Opcode_subx4_Slot_n2_s1_ld_encode, Opcode_subx4_Slot_n0_s0_ldst_encode, 0, 0, Opcode_subx4_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0, Opcode_subx8_Slot_f0_s0_ldst_encode, Opcode_subx8_Slot_f0_s1_ld_encode, Opcode_subx8_Slot_f0_s2_mul_encode, 0, Opcode_subx8_Slot_f1_s0_ldstalu_encode, Opcode_subx8_Slot_f1_s1_ld_encode, Opcode_subx8_Slot_f1_s2_mul_encode, 0, Opcode_subx8_Slot_f2_s0_ldst_encode, Opcode_subx8_Slot_f2_s1_ld_encode, Opcode_subx8_Slot_f2_s2_mul_encode, 0, Opcode_subx8_Slot_f3_s0_ldst_encode, Opcode_subx8_Slot_f3_s1_ld_encode, Opcode_subx8_Slot_f3_s2_mul_encode, 0, 0, Opcode_subx8_Slot_f4_s0_ld_encode, Opcode_subx8_Slot_f4_s1_ld_encode, 0, 0, Opcode_subx8_Slot_f5_s0_base_encode, Opcode_subx8_Slot_f5_s1_base_encode, Opcode_subx8_Slot_f5_s2_base_encode, 0, Opcode_subx8_Slot_f11_s0_ld_encode, Opcode_subx8_Slot_f11_s1_alu_encode, Opcode_subx8_Slot_f11_s2_mul_encode, 0, 0, Opcode_subx8_Slot_n1_s0_ldst_encode, 0, Opcode_subx8_Slot_n1_s2_mul_encode, Opcode_subx8_Slot_n2_s0_ldst_encode, Opcode_subx8_Slot_n2_s1_ld_encode, Opcode_subx8_Slot_n0_s0_ldst_encode, 0, 0, Opcode_subx8_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_f0_s0_ldst_encode, Opcode_and_Slot_f0_s1_ld_encode, Opcode_and_Slot_f0_s2_mul_encode, 0, Opcode_and_Slot_f1_s0_ldstalu_encode, Opcode_and_Slot_f1_s1_ld_encode, Opcode_and_Slot_f1_s2_mul_encode, 0, Opcode_and_Slot_f2_s0_ldst_encode, Opcode_and_Slot_f2_s1_ld_encode, Opcode_and_Slot_f2_s2_mul_encode, 0, Opcode_and_Slot_f3_s0_ldst_encode, Opcode_and_Slot_f3_s1_ld_encode, Opcode_and_Slot_f3_s2_mul_encode, 0, 0, Opcode_and_Slot_f4_s0_ld_encode, Opcode_and_Slot_f4_s1_ld_encode, 0, 0, Opcode_and_Slot_f5_s0_base_encode, Opcode_and_Slot_f5_s1_base_encode, Opcode_and_Slot_f5_s2_base_encode, 0, Opcode_and_Slot_f11_s0_ld_encode, Opcode_and_Slot_f11_s1_alu_encode, Opcode_and_Slot_f11_s2_mul_encode, 0, 0, Opcode_and_Slot_n1_s0_ldst_encode, 0, Opcode_and_Slot_n1_s2_mul_encode, Opcode_and_Slot_n2_s0_ldst_encode, Opcode_and_Slot_n2_s1_ld_encode, Opcode_and_Slot_n0_s0_ldst_encode, 0, 0, Opcode_and_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_f0_s0_ldst_encode, Opcode_or_Slot_f0_s1_ld_encode, Opcode_or_Slot_f0_s2_mul_encode, 0, Opcode_or_Slot_f1_s0_ldstalu_encode, Opcode_or_Slot_f1_s1_ld_encode, Opcode_or_Slot_f1_s2_mul_encode, 0, Opcode_or_Slot_f2_s0_ldst_encode, Opcode_or_Slot_f2_s1_ld_encode, Opcode_or_Slot_f2_s2_mul_encode, 0, Opcode_or_Slot_f3_s0_ldst_encode, Opcode_or_Slot_f3_s1_ld_encode, Opcode_or_Slot_f3_s2_mul_encode, 0, 0, Opcode_or_Slot_f4_s0_ld_encode, Opcode_or_Slot_f4_s1_ld_encode, 0, 0, Opcode_or_Slot_f5_s0_base_encode, Opcode_or_Slot_f5_s1_base_encode, Opcode_or_Slot_f5_s2_base_encode, 0, Opcode_or_Slot_f11_s0_ld_encode, Opcode_or_Slot_f11_s1_alu_encode, Opcode_or_Slot_f11_s2_mul_encode, 0, 0, Opcode_or_Slot_n1_s0_ldst_encode, 0, Opcode_or_Slot_n1_s2_mul_encode, Opcode_or_Slot_n2_s0_ldst_encode, Opcode_or_Slot_n2_s1_ld_encode, Opcode_or_Slot_n0_s0_ldst_encode, 0, 0, Opcode_or_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_f0_s0_ldst_encode, Opcode_xor_Slot_f0_s1_ld_encode, Opcode_xor_Slot_f0_s2_mul_encode, 0, Opcode_xor_Slot_f1_s0_ldstalu_encode, Opcode_xor_Slot_f1_s1_ld_encode, Opcode_xor_Slot_f1_s2_mul_encode, 0, Opcode_xor_Slot_f2_s0_ldst_encode, Opcode_xor_Slot_f2_s1_ld_encode, Opcode_xor_Slot_f2_s2_mul_encode, 0, Opcode_xor_Slot_f3_s0_ldst_encode, Opcode_xor_Slot_f3_s1_ld_encode, Opcode_xor_Slot_f3_s2_mul_encode, 0, 0, Opcode_xor_Slot_f4_s0_ld_encode, Opcode_xor_Slot_f4_s1_ld_encode, 0, 0, Opcode_xor_Slot_f5_s0_base_encode, Opcode_xor_Slot_f5_s1_base_encode, Opcode_xor_Slot_f5_s2_base_encode, 0, Opcode_xor_Slot_f11_s0_ld_encode, Opcode_xor_Slot_f11_s1_alu_encode, Opcode_xor_Slot_f11_s2_mul_encode, 0, 0, Opcode_xor_Slot_n1_s0_ldst_encode, 0, Opcode_xor_Slot_n1_s2_mul_encode, Opcode_xor_Slot_n2_s0_ldst_encode, Opcode_xor_Slot_n2_s1_ld_encode, Opcode_xor_Slot_n0_s0_ldst_encode, 0, 0, Opcode_xor_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_const16_encode_fns[] = { + Opcode_const16_Slot_inst_encode, 0, 0, Opcode_const16_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_const16_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_const16_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_const16_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_const16_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_const16_Slot_f5_s0_base_encode, 0, 0, 0, Opcode_const16_Slot_f11_s0_ld_encode, 0, 0, 0, 0, Opcode_const16_Slot_n1_s0_ldst_encode, 0, 0, Opcode_const16_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_f0_s0_ldst_encode, Opcode_extui_Slot_f0_s1_ld_encode, 0, 0, Opcode_extui_Slot_f1_s0_ldstalu_encode, Opcode_extui_Slot_f1_s1_ld_encode, 0, 0, Opcode_extui_Slot_f2_s0_ldst_encode, Opcode_extui_Slot_f2_s1_ld_encode, 0, 0, Opcode_extui_Slot_f3_s0_ldst_encode, Opcode_extui_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_extui_Slot_f4_s0_ld_encode, Opcode_extui_Slot_f4_s1_ld_encode, 0, 0, Opcode_extui_Slot_f5_s0_base_encode, Opcode_extui_Slot_f5_s1_base_encode, 0, 0, Opcode_extui_Slot_f11_s0_ld_encode, Opcode_extui_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_extui_Slot_n1_s0_ldst_encode, 0, 0, Opcode_extui_Slot_n2_s0_ldst_encode, Opcode_extui_Slot_n2_s1_ld_encode, Opcode_extui_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0, Opcode_j_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_j_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_j_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_j_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_j_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_j_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0, Opcode_l16ui_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_l16ui_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_l16ui_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_l16ui_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_l16ui_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_l16ui_Slot_f5_s0_base_encode, Opcode_l16ui_Slot_f5_s1_base_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_l16ui_Slot_n1_s0_ldst_encode, 0, 0, Opcode_l16ui_Slot_n2_s0_ldst_encode, Opcode_l16ui_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0, Opcode_l16si_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_l16si_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_l16si_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_l16si_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_l16si_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_l16si_Slot_f5_s0_base_encode, Opcode_l16si_Slot_f5_s1_base_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_l16si_Slot_n1_s0_ldst_encode, 0, 0, Opcode_l16si_Slot_n2_s0_ldst_encode, Opcode_l16si_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0, Opcode_l32i_Slot_f0_s0_ldst_encode, Opcode_l32i_Slot_f0_s1_ld_encode, 0, 0, Opcode_l32i_Slot_f1_s0_ldstalu_encode, Opcode_l32i_Slot_f1_s1_ld_encode, 0, 0, Opcode_l32i_Slot_f2_s0_ldst_encode, Opcode_l32i_Slot_f2_s1_ld_encode, 0, 0, Opcode_l32i_Slot_f3_s0_ldst_encode, Opcode_l32i_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_l32i_Slot_f4_s0_ld_encode, Opcode_l32i_Slot_f4_s1_ld_encode, 0, 0, Opcode_l32i_Slot_f5_s0_base_encode, Opcode_l32i_Slot_f5_s1_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0, Opcode_l8ui_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_l8ui_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_l8ui_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_l8ui_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_l8ui_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_l8ui_Slot_f5_s0_base_encode, Opcode_l8ui_Slot_f5_s1_base_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_l8ui_Slot_n1_s0_ldst_encode, 0, 0, Opcode_l8ui_Slot_n2_s0_ldst_encode, Opcode_l8ui_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0, Opcode_loop_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_loop_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_loop_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_loop_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_loop_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_loop_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0, Opcode_loopnez_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_loopnez_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_loopnez_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_loopnez_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_loopnez_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_loopnez_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0, Opcode_loopgtz_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_loopgtz_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_loopgtz_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_loopgtz_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_loopgtz_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_loopgtz_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0, Opcode_movi_Slot_f0_s0_ldst_encode, Opcode_movi_Slot_f0_s1_ld_encode, 0, 0, Opcode_movi_Slot_f1_s0_ldstalu_encode, Opcode_movi_Slot_f1_s1_ld_encode, 0, 0, Opcode_movi_Slot_f2_s0_ldst_encode, Opcode_movi_Slot_f2_s1_ld_encode, 0, 0, Opcode_movi_Slot_f3_s0_ldst_encode, Opcode_movi_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_movi_Slot_f4_s0_ld_encode, Opcode_movi_Slot_f4_s1_ld_encode, 0, 0, Opcode_movi_Slot_f5_s0_base_encode, Opcode_movi_Slot_f5_s1_base_encode, Opcode_movi_Slot_f5_s2_base_encode, Opcode_movi_Slot_f5_s3_base_encode, Opcode_movi_Slot_f11_s0_ld_encode, Opcode_movi_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_movi_Slot_n1_s0_ldst_encode, 0, 0, Opcode_movi_Slot_n2_s0_ldst_encode, Opcode_movi_Slot_n2_s1_ld_encode, Opcode_movi_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_f0_s0_ldst_encode, Opcode_moveqz_Slot_f0_s1_ld_encode, 0, 0, Opcode_moveqz_Slot_f1_s0_ldstalu_encode, Opcode_moveqz_Slot_f1_s1_ld_encode, 0, 0, Opcode_moveqz_Slot_f2_s0_ldst_encode, Opcode_moveqz_Slot_f2_s1_ld_encode, 0, 0, Opcode_moveqz_Slot_f3_s0_ldst_encode, Opcode_moveqz_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_moveqz_Slot_f4_s0_ld_encode, Opcode_moveqz_Slot_f4_s1_ld_encode, 0, 0, Opcode_moveqz_Slot_f5_s0_base_encode, Opcode_moveqz_Slot_f5_s1_base_encode, Opcode_moveqz_Slot_f5_s2_base_encode, 0, Opcode_moveqz_Slot_f11_s0_ld_encode, Opcode_moveqz_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_moveqz_Slot_n1_s0_ldst_encode, 0, Opcode_moveqz_Slot_n1_s2_mul_encode, Opcode_moveqz_Slot_n2_s0_ldst_encode, Opcode_moveqz_Slot_n2_s1_ld_encode, Opcode_moveqz_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_f0_s0_ldst_encode, Opcode_movnez_Slot_f0_s1_ld_encode, 0, 0, Opcode_movnez_Slot_f1_s0_ldstalu_encode, Opcode_movnez_Slot_f1_s1_ld_encode, 0, 0, Opcode_movnez_Slot_f2_s0_ldst_encode, Opcode_movnez_Slot_f2_s1_ld_encode, 0, 0, Opcode_movnez_Slot_f3_s0_ldst_encode, Opcode_movnez_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_movnez_Slot_f4_s0_ld_encode, Opcode_movnez_Slot_f4_s1_ld_encode, 0, 0, Opcode_movnez_Slot_f5_s0_base_encode, Opcode_movnez_Slot_f5_s1_base_encode, Opcode_movnez_Slot_f5_s2_base_encode, 0, Opcode_movnez_Slot_f11_s0_ld_encode, Opcode_movnez_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_movnez_Slot_n1_s0_ldst_encode, 0, Opcode_movnez_Slot_n1_s2_mul_encode, Opcode_movnez_Slot_n2_s0_ldst_encode, Opcode_movnez_Slot_n2_s1_ld_encode, Opcode_movnez_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_f0_s0_ldst_encode, Opcode_movltz_Slot_f0_s1_ld_encode, 0, 0, Opcode_movltz_Slot_f1_s0_ldstalu_encode, Opcode_movltz_Slot_f1_s1_ld_encode, 0, 0, Opcode_movltz_Slot_f2_s0_ldst_encode, Opcode_movltz_Slot_f2_s1_ld_encode, 0, 0, Opcode_movltz_Slot_f3_s0_ldst_encode, Opcode_movltz_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_movltz_Slot_f4_s0_ld_encode, Opcode_movltz_Slot_f4_s1_ld_encode, 0, 0, Opcode_movltz_Slot_f5_s0_base_encode, Opcode_movltz_Slot_f5_s1_base_encode, Opcode_movltz_Slot_f5_s2_base_encode, 0, Opcode_movltz_Slot_f11_s0_ld_encode, Opcode_movltz_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_movltz_Slot_n1_s0_ldst_encode, 0, Opcode_movltz_Slot_n1_s2_mul_encode, Opcode_movltz_Slot_n2_s0_ldst_encode, Opcode_movltz_Slot_n2_s1_ld_encode, Opcode_movltz_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_f0_s0_ldst_encode, Opcode_movgez_Slot_f0_s1_ld_encode, 0, 0, Opcode_movgez_Slot_f1_s0_ldstalu_encode, Opcode_movgez_Slot_f1_s1_ld_encode, 0, 0, Opcode_movgez_Slot_f2_s0_ldst_encode, Opcode_movgez_Slot_f2_s1_ld_encode, 0, 0, Opcode_movgez_Slot_f3_s0_ldst_encode, Opcode_movgez_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_movgez_Slot_f4_s0_ld_encode, Opcode_movgez_Slot_f4_s1_ld_encode, 0, 0, Opcode_movgez_Slot_f5_s0_base_encode, Opcode_movgez_Slot_f5_s1_base_encode, Opcode_movgez_Slot_f5_s2_base_encode, 0, Opcode_movgez_Slot_f11_s0_ld_encode, Opcode_movgez_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_movgez_Slot_n1_s0_ldst_encode, 0, Opcode_movgez_Slot_n1_s2_mul_encode, Opcode_movgez_Slot_n2_s0_ldst_encode, Opcode_movgez_Slot_n2_s1_ld_encode, Opcode_movgez_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_f0_s0_ldst_encode, Opcode_neg_Slot_f0_s1_ld_encode, 0, 0, Opcode_neg_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_neg_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_neg_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_neg_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_neg_Slot_f5_s0_base_encode, 0, Opcode_neg_Slot_f5_s2_base_encode, 0, 0, 0, 0, 0, 0, Opcode_neg_Slot_n1_s0_ldst_encode, 0, 0, Opcode_neg_Slot_n2_s0_ldst_encode, Opcode_neg_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_f0_s0_ldst_encode, 0, Opcode_abs_Slot_f0_s2_mul_encode, 0, Opcode_abs_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_abs_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_abs_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_abs_Slot_f4_s0_ld_encode, Opcode_abs_Slot_f4_s1_ld_encode, 0, 0, Opcode_abs_Slot_f5_s0_base_encode, Opcode_abs_Slot_f5_s1_base_encode, 0, 0, 0, 0, Opcode_abs_Slot_f11_s2_mul_encode, 0, 0, Opcode_abs_Slot_n1_s0_ldst_encode, 0, 0, Opcode_abs_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_f0_s0_ldst_encode, Opcode_nop_Slot_f0_s1_ld_encode, Opcode_nop_Slot_f0_s2_mul_encode, Opcode_nop_Slot_f0_s3_alu_encode, Opcode_nop_Slot_f1_s0_ldstalu_encode, Opcode_nop_Slot_f1_s1_ld_encode, Opcode_nop_Slot_f1_s2_mul_encode, Opcode_nop_Slot_f1_s3_alu_encode, Opcode_nop_Slot_f2_s0_ldst_encode, Opcode_nop_Slot_f2_s1_ld_encode, Opcode_nop_Slot_f2_s2_mul_encode, Opcode_nop_Slot_f2_s3_alu_encode, Opcode_nop_Slot_f3_s0_ldst_encode, Opcode_nop_Slot_f3_s1_ld_encode, Opcode_nop_Slot_f3_s2_mul_encode, Opcode_nop_Slot_f3_s3_alu_encode, Opcode_nop_Slot_f3_s4_alu_encode, Opcode_nop_Slot_f4_s0_ld_encode, Opcode_nop_Slot_f4_s1_ld_encode, Opcode_nop_Slot_f4_s2_mul_encode, Opcode_nop_Slot_f4_s3_alu_encode, Opcode_nop_Slot_f5_s0_base_encode, Opcode_nop_Slot_f5_s1_base_encode, Opcode_nop_Slot_f5_s2_base_encode, Opcode_nop_Slot_f5_s3_base_encode, Opcode_nop_Slot_f11_s0_ld_encode, Opcode_nop_Slot_f11_s1_alu_encode, Opcode_nop_Slot_f11_s2_mul_encode, Opcode_nop_Slot_f11_s3_alu_encode, Opcode_nop_Slot_f11_s4_alu_encode, Opcode_nop_Slot_n1_s0_ldst_encode, Opcode_nop_Slot_n1_s1_none_encode, Opcode_nop_Slot_n1_s2_mul_encode, Opcode_nop_Slot_n2_s0_ldst_encode, Opcode_nop_Slot_n2_s1_ld_encode, Opcode_nop_Slot_n0_s0_ldst_encode, Opcode_nop_Slot_n0_s1_none_encode, Opcode_nop_Slot_n0_s2_none_encode, Opcode_nop_Slot_n0_s3_alu_encode +}; + +xtensa_opcode_encode_fn Opcode_l32ex_encode_fns[] = { + Opcode_l32ex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s32ex_encode_fns[] = { + Opcode_s32ex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_getex_encode_fns[] = { + Opcode_getex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_clrex_encode_fns[] = { + Opcode_clrex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0, Opcode_s16i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_s16i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_s16i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_s16i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_s16i_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_s16i_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s16i_Slot_n1_s0_ldst_encode, 0, 0, Opcode_s16i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0, Opcode_s32i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_s32i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_s32i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_s32i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_s32i_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_s32i_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { + Opcode_s32nb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0, Opcode_s8i_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_s8i_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_s8i_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_s8i_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_s8i_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_s8i_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s8i_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0, Opcode_ssr_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ssr_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ssr_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ssr_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ssr_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_ssr_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, Opcode_ssr_Slot_f11_s2_mul_encode, 0, 0, Opcode_ssr_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ssr_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0, Opcode_ssl_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ssl_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ssl_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ssl_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ssl_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_ssl_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssl_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ssl_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0, Opcode_ssa8l_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ssa8l_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ssa8l_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ssa8l_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ssa8l_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_ssa8l_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssa8l_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ssa8l_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0, Opcode_ssai_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_ssai_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_ssai_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_ssai_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_ssai_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_ssai_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssai_Slot_n1_s0_ldst_encode, 0, 0, Opcode_ssai_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_f0_s0_ldst_encode, Opcode_sll_Slot_f0_s1_ld_encode, Opcode_sll_Slot_f0_s2_mul_encode, 0, Opcode_sll_Slot_f1_s0_ldstalu_encode, Opcode_sll_Slot_f1_s1_ld_encode, 0, 0, Opcode_sll_Slot_f2_s0_ldst_encode, Opcode_sll_Slot_f2_s1_ld_encode, 0, 0, Opcode_sll_Slot_f3_s0_ldst_encode, Opcode_sll_Slot_f3_s1_ld_encode, Opcode_sll_Slot_f3_s2_mul_encode, 0, 0, Opcode_sll_Slot_f4_s0_ld_encode, Opcode_sll_Slot_f4_s1_ld_encode, 0, 0, Opcode_sll_Slot_f5_s0_base_encode, Opcode_sll_Slot_f5_s1_base_encode, Opcode_sll_Slot_f5_s2_base_encode, 0, Opcode_sll_Slot_f11_s0_ld_encode, Opcode_sll_Slot_f11_s1_alu_encode, Opcode_sll_Slot_f11_s2_mul_encode, 0, 0, Opcode_sll_Slot_n1_s0_ldst_encode, 0, Opcode_sll_Slot_n1_s2_mul_encode, Opcode_sll_Slot_n2_s0_ldst_encode, Opcode_sll_Slot_n2_s1_ld_encode, Opcode_sll_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0, Opcode_src_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_src_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_src_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_src_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_src_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_src_Slot_f5_s0_base_encode, 0, Opcode_src_Slot_f5_s2_base_encode, 0, 0, 0, Opcode_src_Slot_f11_s2_mul_encode, 0, 0, Opcode_src_Slot_n1_s0_ldst_encode, 0, 0, Opcode_src_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0, Opcode_srl_Slot_f0_s0_ldst_encode, Opcode_srl_Slot_f0_s1_ld_encode, Opcode_srl_Slot_f0_s2_mul_encode, 0, Opcode_srl_Slot_f1_s0_ldstalu_encode, Opcode_srl_Slot_f1_s1_ld_encode, 0, 0, Opcode_srl_Slot_f2_s0_ldst_encode, Opcode_srl_Slot_f2_s1_ld_encode, 0, 0, Opcode_srl_Slot_f3_s0_ldst_encode, Opcode_srl_Slot_f3_s1_ld_encode, Opcode_srl_Slot_f3_s2_mul_encode, 0, 0, Opcode_srl_Slot_f4_s0_ld_encode, Opcode_srl_Slot_f4_s1_ld_encode, 0, 0, Opcode_srl_Slot_f5_s0_base_encode, Opcode_srl_Slot_f5_s1_base_encode, Opcode_srl_Slot_f5_s2_base_encode, 0, Opcode_srl_Slot_f11_s0_ld_encode, Opcode_srl_Slot_f11_s1_alu_encode, Opcode_srl_Slot_f11_s2_mul_encode, 0, 0, Opcode_srl_Slot_n1_s0_ldst_encode, 0, Opcode_srl_Slot_n1_s2_mul_encode, Opcode_srl_Slot_n2_s0_ldst_encode, Opcode_srl_Slot_n2_s1_ld_encode, Opcode_srl_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_f0_s0_ldst_encode, Opcode_sra_Slot_f0_s1_ld_encode, Opcode_sra_Slot_f0_s2_mul_encode, 0, Opcode_sra_Slot_f1_s0_ldstalu_encode, Opcode_sra_Slot_f1_s1_ld_encode, 0, 0, Opcode_sra_Slot_f2_s0_ldst_encode, Opcode_sra_Slot_f2_s1_ld_encode, 0, 0, Opcode_sra_Slot_f3_s0_ldst_encode, Opcode_sra_Slot_f3_s1_ld_encode, Opcode_sra_Slot_f3_s2_mul_encode, 0, 0, Opcode_sra_Slot_f4_s0_ld_encode, Opcode_sra_Slot_f4_s1_ld_encode, 0, 0, Opcode_sra_Slot_f5_s0_base_encode, Opcode_sra_Slot_f5_s1_base_encode, Opcode_sra_Slot_f5_s2_base_encode, 0, Opcode_sra_Slot_f11_s0_ld_encode, Opcode_sra_Slot_f11_s1_alu_encode, Opcode_sra_Slot_f11_s2_mul_encode, 0, 0, Opcode_sra_Slot_n1_s0_ldst_encode, 0, 0, Opcode_sra_Slot_n2_s0_ldst_encode, Opcode_sra_Slot_n2_s1_ld_encode, Opcode_sra_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0, Opcode_slli_Slot_f0_s0_ldst_encode, Opcode_slli_Slot_f0_s1_ld_encode, Opcode_slli_Slot_f0_s2_mul_encode, 0, Opcode_slli_Slot_f1_s0_ldstalu_encode, Opcode_slli_Slot_f1_s1_ld_encode, 0, 0, Opcode_slli_Slot_f2_s0_ldst_encode, Opcode_slli_Slot_f2_s1_ld_encode, 0, 0, Opcode_slli_Slot_f3_s0_ldst_encode, Opcode_slli_Slot_f3_s1_ld_encode, Opcode_slli_Slot_f3_s2_mul_encode, 0, 0, Opcode_slli_Slot_f4_s0_ld_encode, Opcode_slli_Slot_f4_s1_ld_encode, 0, 0, Opcode_slli_Slot_f5_s0_base_encode, Opcode_slli_Slot_f5_s1_base_encode, Opcode_slli_Slot_f5_s2_base_encode, 0, Opcode_slli_Slot_f11_s0_ld_encode, Opcode_slli_Slot_f11_s1_alu_encode, Opcode_slli_Slot_f11_s2_mul_encode, 0, 0, Opcode_slli_Slot_n1_s0_ldst_encode, 0, 0, Opcode_slli_Slot_n2_s0_ldst_encode, Opcode_slli_Slot_n2_s1_ld_encode, Opcode_slli_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0, Opcode_srai_Slot_f0_s0_ldst_encode, Opcode_srai_Slot_f0_s1_ld_encode, Opcode_srai_Slot_f0_s2_mul_encode, 0, Opcode_srai_Slot_f1_s0_ldstalu_encode, Opcode_srai_Slot_f1_s1_ld_encode, 0, 0, Opcode_srai_Slot_f2_s0_ldst_encode, Opcode_srai_Slot_f2_s1_ld_encode, 0, 0, Opcode_srai_Slot_f3_s0_ldst_encode, Opcode_srai_Slot_f3_s1_ld_encode, Opcode_srai_Slot_f3_s2_mul_encode, 0, 0, Opcode_srai_Slot_f4_s0_ld_encode, Opcode_srai_Slot_f4_s1_ld_encode, 0, 0, Opcode_srai_Slot_f5_s0_base_encode, Opcode_srai_Slot_f5_s1_base_encode, Opcode_srai_Slot_f5_s2_base_encode, 0, Opcode_srai_Slot_f11_s0_ld_encode, Opcode_srai_Slot_f11_s1_alu_encode, Opcode_srai_Slot_f11_s2_mul_encode, 0, 0, Opcode_srai_Slot_n1_s0_ldst_encode, 0, 0, Opcode_srai_Slot_n2_s0_ldst_encode, Opcode_srai_Slot_n2_s1_ld_encode, Opcode_srai_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0, Opcode_srli_Slot_f0_s0_ldst_encode, Opcode_srli_Slot_f0_s1_ld_encode, Opcode_srli_Slot_f0_s2_mul_encode, 0, Opcode_srli_Slot_f1_s0_ldstalu_encode, Opcode_srli_Slot_f1_s1_ld_encode, 0, 0, Opcode_srli_Slot_f2_s0_ldst_encode, Opcode_srli_Slot_f2_s1_ld_encode, 0, 0, Opcode_srli_Slot_f3_s0_ldst_encode, Opcode_srli_Slot_f3_s1_ld_encode, Opcode_srli_Slot_f3_s2_mul_encode, 0, 0, Opcode_srli_Slot_f4_s0_ld_encode, Opcode_srli_Slot_f4_s1_ld_encode, 0, 0, Opcode_srli_Slot_f5_s0_base_encode, Opcode_srli_Slot_f5_s1_base_encode, Opcode_srli_Slot_f5_s2_base_encode, 0, Opcode_srli_Slot_f11_s0_ld_encode, Opcode_srli_Slot_f11_s1_alu_encode, Opcode_srli_Slot_f11_s2_mul_encode, 0, 0, Opcode_srli_Slot_n1_s0_ldst_encode, 0, 0, Opcode_srli_Slot_n2_s0_ldst_encode, Opcode_srli_Slot_n2_s1_ld_encode, Opcode_srli_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { + Opcode_rsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { + Opcode_wsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { + Opcode_xsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { + Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { + Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { + Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { + Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { + Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { + Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_mpucfg_encode_fns[] = { + Opcode_rsr_mpucfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_mpucfg_encode_fns[] = { + Opcode_wsr_mpucfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_gserr_encode_fns[] = { + Opcode_rsr_gserr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_gserr_encode_fns[] = { + Opcode_wsr_gserr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_gserr_encode_fns[] = { + Opcode_xsr_gserr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_salt_encode_fns[] = { + Opcode_salt_Slot_inst_encode, 0, 0, Opcode_salt_Slot_f0_s0_ldst_encode, Opcode_salt_Slot_f0_s1_ld_encode, 0, 0, Opcode_salt_Slot_f1_s0_ldstalu_encode, Opcode_salt_Slot_f1_s1_ld_encode, 0, 0, Opcode_salt_Slot_f2_s0_ldst_encode, Opcode_salt_Slot_f2_s1_ld_encode, 0, 0, Opcode_salt_Slot_f3_s0_ldst_encode, Opcode_salt_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_salt_Slot_f4_s0_ld_encode, Opcode_salt_Slot_f4_s1_ld_encode, 0, 0, Opcode_salt_Slot_f5_s0_base_encode, Opcode_salt_Slot_f5_s1_base_encode, Opcode_salt_Slot_f5_s2_base_encode, 0, Opcode_salt_Slot_f11_s0_ld_encode, Opcode_salt_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_salt_Slot_n1_s0_ldst_encode, 0, Opcode_salt_Slot_n1_s2_mul_encode, Opcode_salt_Slot_n2_s0_ldst_encode, Opcode_salt_Slot_n2_s1_ld_encode, Opcode_salt_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_saltu_encode_fns[] = { + Opcode_saltu_Slot_inst_encode, 0, 0, Opcode_saltu_Slot_f0_s0_ldst_encode, Opcode_saltu_Slot_f0_s1_ld_encode, 0, 0, Opcode_saltu_Slot_f1_s0_ldstalu_encode, Opcode_saltu_Slot_f1_s1_ld_encode, 0, 0, Opcode_saltu_Slot_f2_s0_ldst_encode, Opcode_saltu_Slot_f2_s1_ld_encode, 0, 0, Opcode_saltu_Slot_f3_s0_ldst_encode, Opcode_saltu_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_saltu_Slot_f4_s0_ld_encode, Opcode_saltu_Slot_f4_s1_ld_encode, 0, 0, Opcode_saltu_Slot_f5_s0_base_encode, Opcode_saltu_Slot_f5_s1_base_encode, Opcode_saltu_Slot_f5_s2_base_encode, 0, Opcode_saltu_Slot_f11_s0_ld_encode, Opcode_saltu_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_saltu_Slot_n1_s0_ldst_encode, 0, Opcode_saltu_Slot_n1_s2_mul_encode, Opcode_saltu_Slot_n2_s0_ldst_encode, Opcode_saltu_Slot_n2_s1_ld_encode, Opcode_saltu_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0, Opcode_mul16u_Slot_f0_s0_ldst_encode, Opcode_mul16u_Slot_f0_s1_ld_encode, 0, 0, Opcode_mul16u_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_mul16u_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_mul16u_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_mul16u_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_mul16u_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul16u_Slot_n1_s0_ldst_encode, 0, 0, Opcode_mul16u_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0, Opcode_mul16s_Slot_f0_s0_ldst_encode, Opcode_mul16s_Slot_f0_s1_ld_encode, 0, 0, Opcode_mul16s_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_mul16s_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_mul16s_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_mul16s_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_mul16s_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul16s_Slot_n1_s0_ldst_encode, 0, 0, Opcode_mul16s_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0, Opcode_mull_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_mull_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_mull_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_mull_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_mull_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_mull_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mull_Slot_n1_s0_ldst_encode, 0, 0, Opcode_mull_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = { + Opcode_muluh_Slot_inst_encode, 0, 0, Opcode_muluh_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_muluh_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_muluh_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_muluh_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_muluh_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_muluh_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_muluh_Slot_n1_s0_ldst_encode, 0, 0, Opcode_muluh_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = { + Opcode_mulsh_Slot_inst_encode, 0, 0, Opcode_mulsh_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_mulsh_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_mulsh_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_mulsh_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_mulsh_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_mulsh_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulsh_Slot_n1_s0_ldst_encode, 0, 0, Opcode_mulsh_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { + Opcode_lddr32_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { + Opcode_sddr32_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { + Opcode_andb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { + Opcode_andbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { + Opcode_orb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { + Opcode_orbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { + Opcode_xorb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { + Opcode_any4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { + Opcode_all4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { + Opcode_any8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { + Opcode_all8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { + Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { + Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { + Opcode_movf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { + Opcode_movt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { + Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { + Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { + Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { + Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { + Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { + Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_cacheadrdis_encode_fns[] = { + Opcode_wsr_cacheadrdis_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_cacheadrdis_encode_fns[] = { + Opcode_rsr_cacheadrdis_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_cacheadrdis_encode_fns[] = { + Opcode_xsr_cacheadrdis_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rptlb0_encode_fns[] = { + Opcode_rptlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_pptlb_encode_fns[] = { + Opcode_pptlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rptlb1_encode_fns[] = { + Opcode_rptlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wptlb_encode_fns[] = { + Opcode_wptlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_mpuenb_encode_fns[] = { + Opcode_rsr_mpuenb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_mpuenb_encode_fns[] = { + Opcode_wsr_mpuenb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_mpuenb_encode_fns[] = { + Opcode_xsr_mpuenb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { + Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { + Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { + Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { + Opcode_clamps_Slot_inst_encode, 0, 0, Opcode_clamps_Slot_f0_s0_ldst_encode, 0, 0, 0, Opcode_clamps_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_clamps_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_clamps_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_clamps_Slot_f4_s0_ld_encode, Opcode_clamps_Slot_f4_s1_ld_encode, 0, 0, Opcode_clamps_Slot_f5_s0_base_encode, Opcode_clamps_Slot_f5_s1_base_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_clamps_Slot_n1_s0_ldst_encode, 0, Opcode_clamps_Slot_n1_s2_mul_encode, Opcode_clamps_Slot_n2_s0_ldst_encode, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0, Opcode_min_Slot_f0_s0_ldst_encode, Opcode_min_Slot_f0_s1_ld_encode, 0, 0, Opcode_min_Slot_f1_s0_ldstalu_encode, Opcode_min_Slot_f1_s1_ld_encode, 0, 0, Opcode_min_Slot_f2_s0_ldst_encode, Opcode_min_Slot_f2_s1_ld_encode, 0, 0, Opcode_min_Slot_f3_s0_ldst_encode, Opcode_min_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_min_Slot_f4_s0_ld_encode, Opcode_min_Slot_f4_s1_ld_encode, 0, 0, Opcode_min_Slot_f5_s0_base_encode, Opcode_min_Slot_f5_s1_base_encode, Opcode_min_Slot_f5_s2_base_encode, 0, Opcode_min_Slot_f11_s0_ld_encode, Opcode_min_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_min_Slot_n1_s0_ldst_encode, 0, Opcode_min_Slot_n1_s2_mul_encode, Opcode_min_Slot_n2_s0_ldst_encode, Opcode_min_Slot_n2_s1_ld_encode, Opcode_min_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0, Opcode_max_Slot_f0_s0_ldst_encode, Opcode_max_Slot_f0_s1_ld_encode, 0, 0, Opcode_max_Slot_f1_s0_ldstalu_encode, Opcode_max_Slot_f1_s1_ld_encode, 0, 0, Opcode_max_Slot_f2_s0_ldst_encode, Opcode_max_Slot_f2_s1_ld_encode, 0, 0, Opcode_max_Slot_f3_s0_ldst_encode, Opcode_max_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_max_Slot_f4_s0_ld_encode, Opcode_max_Slot_f4_s1_ld_encode, 0, 0, Opcode_max_Slot_f5_s0_base_encode, Opcode_max_Slot_f5_s1_base_encode, Opcode_max_Slot_f5_s2_base_encode, 0, Opcode_max_Slot_f11_s0_ld_encode, Opcode_max_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_max_Slot_n1_s0_ldst_encode, 0, Opcode_max_Slot_n1_s2_mul_encode, Opcode_max_Slot_n2_s0_ldst_encode, Opcode_max_Slot_n2_s1_ld_encode, Opcode_max_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0, Opcode_minu_Slot_f0_s0_ldst_encode, Opcode_minu_Slot_f0_s1_ld_encode, 0, 0, Opcode_minu_Slot_f1_s0_ldstalu_encode, Opcode_minu_Slot_f1_s1_ld_encode, 0, 0, Opcode_minu_Slot_f2_s0_ldst_encode, Opcode_minu_Slot_f2_s1_ld_encode, 0, 0, Opcode_minu_Slot_f3_s0_ldst_encode, Opcode_minu_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_minu_Slot_f4_s0_ld_encode, Opcode_minu_Slot_f4_s1_ld_encode, 0, 0, Opcode_minu_Slot_f5_s0_base_encode, Opcode_minu_Slot_f5_s1_base_encode, Opcode_minu_Slot_f5_s2_base_encode, 0, Opcode_minu_Slot_f11_s0_ld_encode, Opcode_minu_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_minu_Slot_n1_s0_ldst_encode, 0, Opcode_minu_Slot_n1_s2_mul_encode, Opcode_minu_Slot_n2_s0_ldst_encode, Opcode_minu_Slot_n2_s1_ld_encode, Opcode_minu_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0, Opcode_maxu_Slot_f0_s0_ldst_encode, Opcode_maxu_Slot_f0_s1_ld_encode, 0, 0, Opcode_maxu_Slot_f1_s0_ldstalu_encode, Opcode_maxu_Slot_f1_s1_ld_encode, 0, 0, Opcode_maxu_Slot_f2_s0_ldst_encode, Opcode_maxu_Slot_f2_s1_ld_encode, 0, 0, Opcode_maxu_Slot_f3_s0_ldst_encode, Opcode_maxu_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_maxu_Slot_f4_s0_ld_encode, Opcode_maxu_Slot_f4_s1_ld_encode, 0, 0, Opcode_maxu_Slot_f5_s0_base_encode, Opcode_maxu_Slot_f5_s1_base_encode, Opcode_maxu_Slot_f5_s2_base_encode, 0, Opcode_maxu_Slot_f11_s0_ld_encode, Opcode_maxu_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_maxu_Slot_n1_s0_ldst_encode, 0, Opcode_maxu_Slot_n1_s2_mul_encode, Opcode_maxu_Slot_n2_s0_ldst_encode, Opcode_maxu_Slot_n2_s1_ld_encode, Opcode_maxu_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0, Opcode_nsa_Slot_f0_s0_ldst_encode, Opcode_nsa_Slot_f0_s1_ld_encode, 0, 0, Opcode_nsa_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_nsa_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_nsa_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_nsa_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_nsa_Slot_f5_s0_base_encode, 0, Opcode_nsa_Slot_f5_s2_base_encode, 0, 0, 0, 0, 0, 0, Opcode_nsa_Slot_n1_s0_ldst_encode, 0, 0, Opcode_nsa_Slot_n2_s0_ldst_encode, Opcode_nsa_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0, Opcode_nsau_Slot_f0_s0_ldst_encode, Opcode_nsau_Slot_f0_s1_ld_encode, 0, 0, Opcode_nsau_Slot_f1_s0_ldstalu_encode, 0, 0, 0, Opcode_nsau_Slot_f2_s0_ldst_encode, 0, 0, 0, Opcode_nsau_Slot_f3_s0_ldst_encode, 0, 0, 0, 0, Opcode_nsau_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_nsau_Slot_f5_s0_base_encode, 0, Opcode_nsau_Slot_f5_s2_base_encode, 0, 0, 0, 0, 0, 0, Opcode_nsau_Slot_n1_s0_ldst_encode, 0, 0, Opcode_nsau_Slot_n2_s0_ldst_encode, Opcode_nsau_Slot_n2_s1_ld_encode, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0, Opcode_sext_Slot_f0_s0_ldst_encode, Opcode_sext_Slot_f0_s1_ld_encode, 0, 0, Opcode_sext_Slot_f1_s0_ldstalu_encode, Opcode_sext_Slot_f1_s1_ld_encode, 0, 0, Opcode_sext_Slot_f2_s0_ldst_encode, Opcode_sext_Slot_f2_s1_ld_encode, 0, 0, Opcode_sext_Slot_f3_s0_ldst_encode, Opcode_sext_Slot_f3_s1_ld_encode, 0, 0, 0, Opcode_sext_Slot_f4_s0_ld_encode, Opcode_sext_Slot_f4_s1_ld_encode, 0, 0, Opcode_sext_Slot_f5_s0_base_encode, Opcode_sext_Slot_f5_s1_base_encode, 0, 0, Opcode_sext_Slot_f11_s0_ld_encode, Opcode_sext_Slot_f11_s1_alu_encode, 0, 0, 0, Opcode_sext_Slot_n1_s0_ldst_encode, 0, 0, Opcode_sext_Slot_n2_s0_ldst_encode, Opcode_sext_Slot_n2_s1_ld_encode, Opcode_sext_Slot_n0_s0_ldst_encode, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { + Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { + Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { + Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { + Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { + Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { + Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { + Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_eraccess_encode_fns[] = { + Opcode_rsr_eraccess_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_eraccess_encode_fns[] = { + Opcode_wsr_eraccess_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_eraccess_encode_fns[] = { + Opcode_xsr_eraccess_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { + Opcode_rer_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { + Opcode_wer_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_beqz_w15_encode_fns[] = { + 0, 0, 0, Opcode_beqz_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_beqz_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnez_w15_encode_fns[] = { + 0, 0, 0, Opcode_bnez_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bnez_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgez_w15_encode_fns[] = { + 0, 0, 0, Opcode_bgez_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bgez_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bltz_w15_encode_fns[] = { + 0, 0, 0, Opcode_bltz_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bltz_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_beqi_w15_encode_fns[] = { + 0, 0, 0, Opcode_beqi_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_beqi_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnei_w15_encode_fns[] = { + 0, 0, 0, Opcode_bnei_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bnei_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgei_w15_encode_fns[] = { + 0, 0, 0, Opcode_bgei_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bgei_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_blti_w15_encode_fns[] = { + 0, 0, 0, Opcode_blti_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_blti_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_blti_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgeui_w15_encode_fns[] = { + 0, 0, 0, Opcode_bgeui_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bgeui_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bltui_w15_encode_fns[] = { + 0, 0, 0, Opcode_bltui_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bltui_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbci_w15_encode_fns[] = { + 0, 0, 0, Opcode_bbci_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bbci_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbsi_w15_encode_fns[] = { + 0, 0, 0, Opcode_bbsi_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bbsi_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_beq_w15_encode_fns[] = { + 0, 0, 0, Opcode_beq_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_beq_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_beq_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bne_w15_encode_fns[] = { + 0, 0, 0, Opcode_bne_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bne_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bne_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bge_w15_encode_fns[] = { + 0, 0, 0, Opcode_bge_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bge_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bge_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_blt_w15_encode_fns[] = { + 0, 0, 0, Opcode_blt_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_blt_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_blt_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgeu_w15_encode_fns[] = { + 0, 0, 0, Opcode_bgeu_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bgeu_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bltu_w15_encode_fns[] = { + 0, 0, 0, Opcode_bltu_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bltu_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bany_w15_encode_fns[] = { + 0, 0, 0, Opcode_bany_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bany_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bany_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnone_w15_encode_fns[] = { + 0, 0, 0, Opcode_bnone_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bnone_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ball_w15_encode_fns[] = { + 0, 0, 0, Opcode_ball_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ball_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_ball_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnall_w15_encode_fns[] = { + 0, 0, 0, Opcode_bnall_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bnall_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbc_w15_encode_fns[] = { + 0, 0, 0, Opcode_bbc_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bbc_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbs_w15_encode_fns[] = { + 0, 0, 0, Opcode_bbs_w15_Slot_f0_s0_ldst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w15_Slot_f4_s0_ld_encode, 0, 0, 0, Opcode_bbs_w15_Slot_f5_s0_base_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_mtk_andpopc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mtk_andpopc_Slot_f3_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mtk_andpopc_Slot_f11_s4_alu_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_iq_tie2apb_inq0_pop_encode_fns[] = { + Opcode_iq_tie2apb_inq0_pop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_iq_tie2apb_inq0_is_ready_encode_fns[] = { + Opcode_iq_tie2apb_inq0_is_ready_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_iq_tie2apb_inq0_nonblocking_peek_encode_fns[] = { + Opcode_iq_tie2apb_inq0_nonblocking_peek_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_iq_tie2apb_inq0_nonblocking_pop_encode_fns[] = { + Opcode_iq_tie2apb_inq0_nonblocking_pop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_iq_tie2apb_inq0_blocking_peek_encode_fns[] = { + Opcode_iq_tie2apb_inq0_blocking_peek_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_oq_tie2apb_outq0_push_read_encode_fns[] = { + Opcode_oq_tie2apb_outq0_push_read_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_oq_tie2apb_outq0_push_write_encode_fns[] = { + Opcode_oq_tie2apb_outq0_push_write_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_oq_tie2apb_outq0_is_ready_encode_fns[] = { + Opcode_oq_tie2apb_outq0_is_ready_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_oq_tie2apb_outq0_nonblocking_push_read_encode_fns[] = { + Opcode_oq_tie2apb_outq0_nonblocking_push_read_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_oq_tie2apb_outq0_nonblocking_push_write_encode_fns[] = { + Opcode_oq_tie2apb_outq0_nonblocking_push_write_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rur_apb_pipe_encode_fns[] = { + Opcode_rur_apb_pipe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wur_apb_pipe_encode_fns[] = { + Opcode_wur_apb_pipe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +int num_bypass_groups() { + return 0; +} + +int num_bypass_group_chunks() { + return 0; +} + +uint32 *bypass_entry(int i) { + return 0; +} + + +/* Opcode table. */ + +static xtensa_opcode_internal opcodes[] = { + { "ivp_repnx16", ICLASS_IVP_REPNX16, + 0, + Opcode_ivp_repnx16_encode_fns, 0, 0 }, + { "ivp_selsnx16", ICLASS_IVP_SELSNX16, + 0, + Opcode_ivp_selsnx16_encode_fns, 0, 0 }, + { "ivp_rep2nx8", ICLASS_IVP_REP2NX8, + 0, + Opcode_ivp_rep2nx8_encode_fns, 0, 0 }, + { "ivp_sels2nx8", ICLASS_IVP_SELS2NX8, + 0, + Opcode_ivp_sels2nx8_encode_fns, 0, 0 }, + { "ivp_repn_2x32", ICLASS_IVP_REPN_2X32, + 0, + Opcode_ivp_repn_2x32_encode_fns, 0, 0 }, + { "ivp_selsn_2x32", ICLASS_IVP_SELSN_2X32, + 0, + Opcode_ivp_selsn_2x32_encode_fns, 0, 0 }, + { "ivp_ext0ib", ICLASS_IVP_EXT0IB, + 0, + Opcode_ivp_ext0ib_encode_fns, 0, 0 }, + { "ivp_notb", ICLASS_IVP_NOTB, + 0, + Opcode_ivp_notb_encode_fns, 0, 0 }, + { "ivp_andb", ICLASS_IVP_ANDB, + 0, + Opcode_ivp_andb_encode_fns, 0, 0 }, + { "ivp_orb", ICLASS_IVP_ORB, + 0, + Opcode_ivp_orb_encode_fns, 0, 0 }, + { "ivp_xorb", ICLASS_IVP_XORB, + 0, + Opcode_ivp_xorb_encode_fns, 0, 0 }, + { "ivp_andnotb", ICLASS_IVP_ANDNOTB, + 0, + Opcode_ivp_andnotb_encode_fns, 0, 0 }, + { "ivp_mb", ICLASS_IVP_MB, + 0, + Opcode_ivp_mb_encode_fns, 0, 0 }, + { "ivp_ltrn", ICLASS_IVP_LTRN, + 0, + Opcode_ivp_ltrn_encode_fns, 0, 0 }, + { "ivp_ltrni", ICLASS_IVP_LTRNI, + 0, + Opcode_ivp_ltrni_encode_fns, 0, 0 }, + { "ivp_lbn_i", ICLASS_IVP_LBN_I, + 0, + Opcode_ivp_lbn_i_encode_fns, 0, 0 }, + { "ivp_lbn_ip", ICLASS_IVP_LBN_IP, + 0, + Opcode_ivp_lbn_ip_encode_fns, 0, 0 }, + { "ivp_sbn_i", ICLASS_IVP_SBN_I, + 0, + Opcode_ivp_sbn_i_encode_fns, 0, 0 }, + { "ivp_sbn_ip", ICLASS_IVP_SBN_IP, + 0, + Opcode_ivp_sbn_ip_encode_fns, 0, 0 }, + { "ivp_lsnx16_i", ICLASS_IVP_LSNX16_I, + 0, + Opcode_ivp_lsnx16_i_encode_fns, 0, 0 }, + { "ivp_lsnx16_ip", ICLASS_IVP_LSNX16_IP, + 0, + Opcode_ivp_lsnx16_ip_encode_fns, 0, 0 }, + { "ivp_lsnx16_x", ICLASS_IVP_LSNX16_X, + 0, + Opcode_ivp_lsnx16_x_encode_fns, 0, 0 }, + { "ivp_lsnx16_xp", ICLASS_IVP_LSNX16_XP, + 0, + Opcode_ivp_lsnx16_xp_encode_fns, 0, 0 }, + { "ivp_movbrbv", ICLASS_IVP_MOVBRBV, + 0, + Opcode_ivp_movbrbv_encode_fns, 0, 0 }, + { "ivp_movbvbr", ICLASS_IVP_MOVBVBR, + 0, + Opcode_ivp_movbvbr_encode_fns, 0, 0 }, + { "ivp_joinb", ICLASS_IVP_JOINB, + 0, + Opcode_ivp_joinb_encode_fns, 0, 0 }, + { "ivp_ltrn_2", ICLASS_IVP_LTRN_2, + 0, + Opcode_ivp_ltrn_2_encode_fns, 0, 0 }, + { "ivp_ltrn_2i", ICLASS_IVP_LTRN_2I, + 0, + Opcode_ivp_ltrn_2i_encode_fns, 0, 0 }, + { "ivp_lbn_2_i", ICLASS_IVP_LBN_2_I, + 0, + Opcode_ivp_lbn_2_i_encode_fns, 0, 0 }, + { "ivp_lbn_2_ip", ICLASS_IVP_LBN_2_IP, + 0, + Opcode_ivp_lbn_2_ip_encode_fns, 0, 0 }, + { "ivp_sbn_2_i", ICLASS_IVP_SBN_2_I, + 0, + Opcode_ivp_sbn_2_i_encode_fns, 0, 0 }, + { "ivp_sbn_2_ip", ICLASS_IVP_SBN_2_IP, + 0, + Opcode_ivp_sbn_2_ip_encode_fns, 0, 0 }, + { "ivp_lv2nx8_i", ICLASS_IVP_LV2NX8_I, + 0, + Opcode_ivp_lv2nx8_i_encode_fns, 0, 0 }, + { "ivp_lv2nx8_ip", ICLASS_IVP_LV2NX8_IP, + 0, + Opcode_ivp_lv2nx8_ip_encode_fns, 0, 0 }, + { "ivp_lv2nx8_x", ICLASS_IVP_LV2NX8_X, + 0, + Opcode_ivp_lv2nx8_x_encode_fns, 0, 0 }, + { "ivp_lv2nx8_xp", ICLASS_IVP_LV2NX8_XP, + 0, + Opcode_ivp_lv2nx8_xp_encode_fns, 0, 0 }, + { "ivp_sv2nx8_i", ICLASS_IVP_SV2NX8_I, + 0, + Opcode_ivp_sv2nx8_i_encode_fns, 0, 0 }, + { "ivp_sv2nx8_ip", ICLASS_IVP_SV2NX8_IP, + 0, + Opcode_ivp_sv2nx8_ip_encode_fns, 0, 0 }, + { "ivp_sv2nx8_x", ICLASS_IVP_SV2NX8_X, + 0, + Opcode_ivp_sv2nx8_x_encode_fns, 0, 0 }, + { "ivp_sv2nx8_xp", ICLASS_IVP_SV2NX8_XP, + 0, + Opcode_ivp_sv2nx8_xp_encode_fns, 0, 0 }, + { "ivp_ssnx16_i", ICLASS_IVP_SSNX16_I, + 0, + Opcode_ivp_ssnx16_i_encode_fns, 0, 0 }, + { "ivp_ssnx16_ip", ICLASS_IVP_SSNX16_IP, + 0, + Opcode_ivp_ssnx16_ip_encode_fns, 0, 0 }, + { "ivp_ssnx16_x", ICLASS_IVP_SSNX16_X, + 0, + Opcode_ivp_ssnx16_x_encode_fns, 0, 0 }, + { "ivp_ssnx16_xp", ICLASS_IVP_SSNX16_XP, + 0, + Opcode_ivp_ssnx16_xp_encode_fns, 0, 0 }, + { "ivp_movva16", ICLASS_IVP_MOVVA16, + 0, + Opcode_ivp_movva16_encode_fns, 0, 0 }, + { "ivp_movvv", ICLASS_IVP_MOVVV, + 0, + Opcode_ivp_movvv_encode_fns, 0, 0 }, + { "ivp_sllinx16", ICLASS_IVP_SLLINX16, + 0, + Opcode_ivp_sllinx16_encode_fns, 0, 0 }, + { "ivp_slsinx16", ICLASS_IVP_SLSINX16, + 0, + Opcode_ivp_slsinx16_encode_fns, 0, 0 }, + { "ivp_srainx16", ICLASS_IVP_SRAINX16, + 0, + Opcode_ivp_srainx16_encode_fns, 0, 0 }, + { "ivp_srlinx16", ICLASS_IVP_SRLINX16, + 0, + Opcode_ivp_srlinx16_encode_fns, 0, 0 }, + { "ivp_sllnx16", ICLASS_IVP_SLLNX16, + 0, + Opcode_ivp_sllnx16_encode_fns, 0, 0 }, + { "ivp_srlnx16", ICLASS_IVP_SRLNX16, + 0, + Opcode_ivp_srlnx16_encode_fns, 0, 0 }, + { "ivp_slanx16", ICLASS_IVP_SLANX16, + 0, + Opcode_ivp_slanx16_encode_fns, 0, 0 }, + { "ivp_sranx16", ICLASS_IVP_SRANX16, + 0, + Opcode_ivp_sranx16_encode_fns, 0, 0 }, + { "ivp_slsnx16", ICLASS_IVP_SLSNX16, + 0, + Opcode_ivp_slsnx16_encode_fns, 0, 0 }, + { "ivp_srsnx16", ICLASS_IVP_SRSNX16, + 0, + Opcode_ivp_srsnx16_encode_fns, 0, 0 }, + { "ivp_xor2nx8", ICLASS_IVP_XOR2NX8, + 0, + Opcode_ivp_xor2nx8_encode_fns, 0, 0 }, + { "ivp_and2nx8", ICLASS_IVP_AND2NX8, + 0, + Opcode_ivp_and2nx8_encode_fns, 0, 0 }, + { "ivp_or2nx8", ICLASS_IVP_OR2NX8, + 0, + Opcode_ivp_or2nx8_encode_fns, 0, 0 }, + { "ivp_not2nx8", ICLASS_IVP_NOT2NX8, + 0, + Opcode_ivp_not2nx8_encode_fns, 0, 0 }, + { "ivp_addnx16", ICLASS_IVP_ADDNX16, + 0, + Opcode_ivp_addnx16_encode_fns, 0, 0 }, + { "ivp_subnx16", ICLASS_IVP_SUBNX16, + 0, + Opcode_ivp_subnx16_encode_fns, 0, 0 }, + { "ivp_negnx16", ICLASS_IVP_NEGNX16, + 0, + Opcode_ivp_negnx16_encode_fns, 0, 0 }, + { "ivp_minnx16", ICLASS_IVP_MINNX16, + 0, + Opcode_ivp_minnx16_encode_fns, 0, 0 }, + { "ivp_minunx16", ICLASS_IVP_MINUNX16, + 0, + Opcode_ivp_minunx16_encode_fns, 0, 0 }, + { "ivp_maxnx16", ICLASS_IVP_MAXNX16, + 0, + Opcode_ivp_maxnx16_encode_fns, 0, 0 }, + { "ivp_maxunx16", ICLASS_IVP_MAXUNX16, + 0, + Opcode_ivp_maxunx16_encode_fns, 0, 0 }, + { "ivp_mulsgnnx16", ICLASS_IVP_MULSGNNX16, + 0, + Opcode_ivp_mulsgnnx16_encode_fns, 0, 0 }, + { "ivp_nsanx16", ICLASS_IVP_NSANX16, + 0, + Opcode_ivp_nsanx16_encode_fns, 0, 0 }, + { "ivp_nsaunx16", ICLASS_IVP_NSAUNX16, + 0, + Opcode_ivp_nsaunx16_encode_fns, 0, 0 }, + { "ivp_ltnx16", ICLASS_IVP_LTNX16, + 0, + Opcode_ivp_ltnx16_encode_fns, 0, 0 }, + { "ivp_lenx16", ICLASS_IVP_LENX16, + 0, + Opcode_ivp_lenx16_encode_fns, 0, 0 }, + { "ivp_eqnx16", ICLASS_IVP_EQNX16, + 0, + Opcode_ivp_eqnx16_encode_fns, 0, 0 }, + { "ivp_neqnx16", ICLASS_IVP_NEQNX16, + 0, + Opcode_ivp_neqnx16_encode_fns, 0, 0 }, + { "ivp_ltunx16", ICLASS_IVP_LTUNX16, + 0, + Opcode_ivp_ltunx16_encode_fns, 0, 0 }, + { "ivp_leunx16", ICLASS_IVP_LEUNX16, + 0, + Opcode_ivp_leunx16_encode_fns, 0, 0 }, + { "ivp_raddnx16", ICLASS_IVP_RADDNX16, + 0, + Opcode_ivp_raddnx16_encode_fns, 0, 0 }, + { "ivp_rmaxnx16", ICLASS_IVP_RMAXNX16, + 0, + Opcode_ivp_rmaxnx16_encode_fns, 0, 0 }, + { "ivp_rminnx16", ICLASS_IVP_RMINNX16, + 0, + Opcode_ivp_rminnx16_encode_fns, 0, 0 }, + { "ivp_rmaxunx16", ICLASS_IVP_RMAXUNX16, + 0, + Opcode_ivp_rmaxunx16_encode_fns, 0, 0 }, + { "ivp_rminunx16", ICLASS_IVP_RMINUNX16, + 0, + Opcode_ivp_rminunx16_encode_fns, 0, 0 }, + { "ivp_rbminnx16", ICLASS_IVP_RBMINNX16, + 0, + Opcode_ivp_rbminnx16_encode_fns, 0, 0 }, + { "ivp_rbmaxnx16", ICLASS_IVP_RBMAXNX16, + 0, + Opcode_ivp_rbmaxnx16_encode_fns, 0, 0 }, + { "ivp_bmaxnx16", ICLASS_IVP_BMAXNX16, + 0, + Opcode_ivp_bmaxnx16_encode_fns, 0, 0 }, + { "ivp_bminnx16", ICLASS_IVP_BMINNX16, + 0, + Opcode_ivp_bminnx16_encode_fns, 0, 0 }, + { "ivp_mov2nx8t", ICLASS_IVP_MOV2NX8T, + 0, + Opcode_ivp_mov2nx8t_encode_fns, 0, 0 }, + { "ivp_mulanx16packl", ICLASS_IVP_MULANX16PACKL, + 0, + Opcode_ivp_mulanx16packl_encode_fns, 0, 0 }, + { "ivp_mulanx16packq", ICLASS_IVP_MULANX16PACKQ, + 0, + Opcode_ivp_mulanx16packq_encode_fns, 0, 0 }, + { "ivp_mulsnx16packl", ICLASS_IVP_MULSNX16PACKL, + 0, + Opcode_ivp_mulsnx16packl_encode_fns, 0, 0 }, + { "ivp_mulsnx16packq", ICLASS_IVP_MULSNX16PACKQ, + 0, + Opcode_ivp_mulsnx16packq_encode_fns, 0, 0 }, + { "ivp_addsnx16", ICLASS_IVP_ADDSNX16, + 0, + Opcode_ivp_addsnx16_encode_fns, 0, 0 }, + { "ivp_subsnx16", ICLASS_IVP_SUBSNX16, + 0, + Opcode_ivp_subsnx16_encode_fns, 0, 0 }, + { "ivp_negsnx16", ICLASS_IVP_NEGSNX16, + 0, + Opcode_ivp_negsnx16_encode_fns, 0, 0 }, + { "ivp_lv2nx8t_i", ICLASS_IVP_LV2NX8T_I, + 0, + Opcode_ivp_lv2nx8t_i_encode_fns, 0, 0 }, + { "ivp_lv2nx8t_ip", ICLASS_IVP_LV2NX8T_IP, + 0, + Opcode_ivp_lv2nx8t_ip_encode_fns, 0, 0 }, + { "ivp_lv2nx8t_x", ICLASS_IVP_LV2NX8T_X, + 0, + Opcode_ivp_lv2nx8t_x_encode_fns, 0, 0 }, + { "ivp_lv2nx8t_xp", ICLASS_IVP_LV2NX8T_XP, + 0, + Opcode_ivp_lv2nx8t_xp_encode_fns, 0, 0 }, + { "ivp_sv2nx8t_i", ICLASS_IVP_SV2NX8T_I, + 0, + Opcode_ivp_sv2nx8t_i_encode_fns, 0, 0 }, + { "ivp_sv2nx8t_ip", ICLASS_IVP_SV2NX8T_IP, + 0, + Opcode_ivp_sv2nx8t_ip_encode_fns, 0, 0 }, + { "ivp_sv2nx8t_x", ICLASS_IVP_SV2NX8T_X, + 0, + Opcode_ivp_sv2nx8t_x_encode_fns, 0, 0 }, + { "ivp_sv2nx8t_xp", ICLASS_IVP_SV2NX8T_XP, + 0, + Opcode_ivp_sv2nx8t_xp_encode_fns, 0, 0 }, + { "ivp_raddnx16t", ICLASS_IVP_RADDNX16T, + 0, + Opcode_ivp_raddnx16t_encode_fns, 0, 0 }, + { "ivp_rmaxnx16t", ICLASS_IVP_RMAXNX16T, + 0, + Opcode_ivp_rmaxnx16t_encode_fns, 0, 0 }, + { "ivp_rminnx16t", ICLASS_IVP_RMINNX16T, + 0, + Opcode_ivp_rminnx16t_encode_fns, 0, 0 }, + { "ivp_rmaxunx16t", ICLASS_IVP_RMAXUNX16T, + 0, + Opcode_ivp_rmaxunx16t_encode_fns, 0, 0 }, + { "ivp_rminunx16t", ICLASS_IVP_RMINUNX16T, + 0, + Opcode_ivp_rminunx16t_encode_fns, 0, 0 }, + { "ivp_addnx16t", ICLASS_IVP_ADDNX16T, + 0, + Opcode_ivp_addnx16t_encode_fns, 0, 0 }, + { "ivp_subnx16t", ICLASS_IVP_SUBNX16T, + 0, + Opcode_ivp_subnx16t_encode_fns, 0, 0 }, + { "ivp_negnx16t", ICLASS_IVP_NEGNX16T, + 0, + Opcode_ivp_negnx16t_encode_fns, 0, 0 }, + { "ivp_maxnx16t", ICLASS_IVP_MAXNX16T, + 0, + Opcode_ivp_maxnx16t_encode_fns, 0, 0 }, + { "ivp_minnx16t", ICLASS_IVP_MINNX16T, + 0, + Opcode_ivp_minnx16t_encode_fns, 0, 0 }, + { "ivp_maxunx16t", ICLASS_IVP_MAXUNX16T, + 0, + Opcode_ivp_maxunx16t_encode_fns, 0, 0 }, + { "ivp_minunx16t", ICLASS_IVP_MINUNX16T, + 0, + Opcode_ivp_minunx16t_encode_fns, 0, 0 }, + { "ivp_mulanx16packlt", ICLASS_IVP_MULANX16PACKLT, + 0, + Opcode_ivp_mulanx16packlt_encode_fns, 0, 0 }, + { "ivp_mulanx16packqt", ICLASS_IVP_MULANX16PACKQT, + 0, + Opcode_ivp_mulanx16packqt_encode_fns, 0, 0 }, + { "ivp_addsnx16t", ICLASS_IVP_ADDSNX16T, + 0, + Opcode_ivp_addsnx16t_encode_fns, 0, 0 }, + { "ivp_subsnx16t", ICLASS_IVP_SUBSNX16T, + 0, + Opcode_ivp_subsnx16t_encode_fns, 0, 0 }, + { "ivp_negsnx16t", ICLASS_IVP_NEGSNX16T, + 0, + Opcode_ivp_negsnx16t_encode_fns, 0, 0 }, + { "ivp_lalign_i", ICLASS_IVP_LALIGN_I, + 0, + Opcode_ivp_lalign_i_encode_fns, 0, 0 }, + { "ivp_lalign_ip", ICLASS_IVP_LALIGN_IP, + 0, + Opcode_ivp_lalign_ip_encode_fns, 0, 0 }, + { "ivp_salign_i", ICLASS_IVP_SALIGN_I, + 0, + Opcode_ivp_salign_i_encode_fns, 0, 0 }, + { "ivp_salign_ip", ICLASS_IVP_SALIGN_IP, + 0, + Opcode_ivp_salign_ip_encode_fns, 0, 0 }, + { "ivp_la_pp", ICLASS_IVP_LA_PP, + 0, + Opcode_ivp_la_pp_encode_fns, 0, 0 }, + { "ivp_sapos_fp", ICLASS_IVP_SAPOS_FP, + 0, + Opcode_ivp_sapos_fp_encode_fns, 0, 0 }, + { "ivp_malign", ICLASS_IVP_MALIGN, + 0, + Opcode_ivp_malign_encode_fns, 0, 0 }, + { "ivp_zalign", ICLASS_IVP_ZALIGN, + 0, + Opcode_ivp_zalign_encode_fns, 0, 0 }, + { "ivp_la2nx8_ip", ICLASS_IVP_LA2NX8_IP, + 0, + Opcode_ivp_la2nx8_ip_encode_fns, 0, 0 }, + { "ivp_sa2nx8_ip", ICLASS_IVP_SA2NX8_IP, + 0, + Opcode_ivp_sa2nx8_ip_encode_fns, 0, 0 }, + { "ivp_lav2nx8_xp", ICLASS_IVP_LAV2NX8_XP, + 0, + Opcode_ivp_lav2nx8_xp_encode_fns, 0, 0 }, + { "ivp_sav2nx8_xp", ICLASS_IVP_SAV2NX8_XP, + 0, + Opcode_ivp_sav2nx8_xp_encode_fns, 0, 0 }, + { "ivp_selnx16", ICLASS_IVP_SELNX16, + 0, + Opcode_ivp_selnx16_encode_fns, 0, 0 }, + { "ivp_shflnx16", ICLASS_IVP_SHFLNX16, + 0, + Opcode_ivp_shflnx16_encode_fns, 0, 0 }, + { "ivp_movpint16", ICLASS_IVP_MOVPINT16, + 0, + Opcode_ivp_movpint16_encode_fns, 0, 0 }, + { "ivp_movpa16", ICLASS_IVP_MOVPA16, + 0, + Opcode_ivp_movpa16_encode_fns, 0, 0 }, + { "ivp_mulnx16packp", ICLASS_IVP_MULNX16PACKP, + 0, + Opcode_ivp_mulnx16packp_encode_fns, 0, 0 }, + { "ivp_mulanx16packp", ICLASS_IVP_MULANX16PACKP, + 0, + Opcode_ivp_mulanx16packp_encode_fns, 0, 0 }, + { "ivp_mulsnx16packp", ICLASS_IVP_MULSNX16PACKP, + 0, + Opcode_ivp_mulsnx16packp_encode_fns, 0, 0 }, + { "ivp_mulanx16packpt", ICLASS_IVP_MULANX16PACKPT, + 0, + Opcode_ivp_mulanx16packpt_encode_fns, 0, 0 }, + { "ivp_addmod16u", ICLASS_IVP_ADDMOD16U, + 0, + Opcode_ivp_addmod16u_encode_fns, 0, 0 }, + { "ivp_lvnx8s_i", ICLASS_IVP_LVNX8S_I, + 0, + Opcode_ivp_lvnx8s_i_encode_fns, 0, 0 }, + { "ivp_lvnx8s_ip", ICLASS_IVP_LVNX8S_IP, + 0, + Opcode_ivp_lvnx8s_ip_encode_fns, 0, 0 }, + { "ivp_lvnx8s_x", ICLASS_IVP_LVNX8S_X, + 0, + Opcode_ivp_lvnx8s_x_encode_fns, 0, 0 }, + { "ivp_lvnx8s_xp", ICLASS_IVP_LVNX8S_XP, + 0, + Opcode_ivp_lvnx8s_xp_encode_fns, 0, 0 }, + { "ivp_lvnx8u_i", ICLASS_IVP_LVNX8U_I, + 0, + Opcode_ivp_lvnx8u_i_encode_fns, 0, 0 }, + { "ivp_lvnx8u_ip", ICLASS_IVP_LVNX8U_IP, + 0, + Opcode_ivp_lvnx8u_ip_encode_fns, 0, 0 }, + { "ivp_lvnx8u_x", ICLASS_IVP_LVNX8U_X, + 0, + Opcode_ivp_lvnx8u_x_encode_fns, 0, 0 }, + { "ivp_lvnx8u_xp", ICLASS_IVP_LVNX8U_XP, + 0, + Opcode_ivp_lvnx8u_xp_encode_fns, 0, 0 }, + { "ivp_svnx8u_i", ICLASS_IVP_SVNX8U_I, + 0, + Opcode_ivp_svnx8u_i_encode_fns, 0, 0 }, + { "ivp_svnx8u_ip", ICLASS_IVP_SVNX8U_IP, + 0, + Opcode_ivp_svnx8u_ip_encode_fns, 0, 0 }, + { "ivp_svnx8u_x", ICLASS_IVP_SVNX8U_X, + 0, + Opcode_ivp_svnx8u_x_encode_fns, 0, 0 }, + { "ivp_svnx8u_xp", ICLASS_IVP_SVNX8U_XP, + 0, + Opcode_ivp_svnx8u_xp_encode_fns, 0, 0 }, + { "ivp_lvnx8st_i", ICLASS_IVP_LVNX8ST_I, + 0, + Opcode_ivp_lvnx8st_i_encode_fns, 0, 0 }, + { "ivp_lvnx8st_ip", ICLASS_IVP_LVNX8ST_IP, + 0, + Opcode_ivp_lvnx8st_ip_encode_fns, 0, 0 }, + { "ivp_lvnx8st_x", ICLASS_IVP_LVNX8ST_X, + 0, + Opcode_ivp_lvnx8st_x_encode_fns, 0, 0 }, + { "ivp_lvnx8st_xp", ICLASS_IVP_LVNX8ST_XP, + 0, + Opcode_ivp_lvnx8st_xp_encode_fns, 0, 0 }, + { "ivp_lvnx8ut_i", ICLASS_IVP_LVNX8UT_I, + 0, + Opcode_ivp_lvnx8ut_i_encode_fns, 0, 0 }, + { "ivp_lvnx8ut_ip", ICLASS_IVP_LVNX8UT_IP, + 0, + Opcode_ivp_lvnx8ut_ip_encode_fns, 0, 0 }, + { "ivp_lvnx8ut_x", ICLASS_IVP_LVNX8UT_X, + 0, + Opcode_ivp_lvnx8ut_x_encode_fns, 0, 0 }, + { "ivp_lvnx8ut_xp", ICLASS_IVP_LVNX8UT_XP, + 0, + Opcode_ivp_lvnx8ut_xp_encode_fns, 0, 0 }, + { "ivp_svnx8ut_i", ICLASS_IVP_SVNX8UT_I, + 0, + Opcode_ivp_svnx8ut_i_encode_fns, 0, 0 }, + { "ivp_svnx8ut_ip", ICLASS_IVP_SVNX8UT_IP, + 0, + Opcode_ivp_svnx8ut_ip_encode_fns, 0, 0 }, + { "ivp_svnx8ut_x", ICLASS_IVP_SVNX8UT_X, + 0, + Opcode_ivp_svnx8ut_x_encode_fns, 0, 0 }, + { "ivp_svnx8ut_xp", ICLASS_IVP_SVNX8UT_XP, + 0, + Opcode_ivp_svnx8ut_xp_encode_fns, 0, 0 }, + { "ivp_lavnx8s_xp", ICLASS_IVP_LAVNX8S_XP, + 0, + Opcode_ivp_lavnx8s_xp_encode_fns, 0, 0 }, + { "ivp_lavnx8u_xp", ICLASS_IVP_LAVNX8U_XP, + 0, + Opcode_ivp_lavnx8u_xp_encode_fns, 0, 0 }, + { "ivp_savnx8u_xp", ICLASS_IVP_SAVNX8U_XP, + 0, + Opcode_ivp_savnx8u_xp_encode_fns, 0, 0 }, + { "ivp_lanx8s_ip", ICLASS_IVP_LANX8S_IP, + 0, + Opcode_ivp_lanx8s_ip_encode_fns, 0, 0 }, + { "ivp_lanx8u_ip", ICLASS_IVP_LANX8U_IP, + 0, + Opcode_ivp_lanx8u_ip_encode_fns, 0, 0 }, + { "ivp_sanx8u_ip", ICLASS_IVP_SANX8U_IP, + 0, + Opcode_ivp_sanx8u_ip_encode_fns, 0, 0 }, + { "ivp_extractbl", ICLASS_IVP_EXTRACTBL, + 0, + Opcode_ivp_extractbl_encode_fns, 0, 0 }, + { "ivp_extractbh", ICLASS_IVP_EXTRACTBH, + 0, + Opcode_ivp_extractbh_encode_fns, 0, 0 }, + { "ivp_movvint16", ICLASS_IVP_MOVVINT16, + 0, + Opcode_ivp_movvint16_encode_fns, 0, 0 }, + { "ivp_movqint16", ICLASS_IVP_MOVQINT16, + 0, + Opcode_ivp_movqint16_encode_fns, 0, 0 }, + { "ivp_movqa16", ICLASS_IVP_MOVQA16, + 0, + Opcode_ivp_movqa16_encode_fns, 0, 0 }, + { "ivp_movvinx16", ICLASS_IVP_MOVVINX16, + 0, + Opcode_ivp_movvinx16_encode_fns, 0, 0 }, + { "ivp_seqnx16", ICLASS_IVP_SEQNX16, + 0, + Opcode_ivp_seqnx16_encode_fns, 0, 0 }, + { "ivp_mulnx16packl", ICLASS_IVP_MULNX16PACKL, + 0, + Opcode_ivp_mulnx16packl_encode_fns, 0, 0 }, + { "ivp_mulnx16packq", ICLASS_IVP_MULNX16PACKQ, + 0, + Opcode_ivp_mulnx16packq_encode_fns, 0, 0 }, + { "ivp_movav16", ICLASS_IVP_MOVAV16, + 0, + Opcode_ivp_movav16_encode_fns, 0, 0 }, + { "ivp_movavu16", ICLASS_IVP_MOVAVU16, + 0, + Opcode_ivp_movavu16_encode_fns, 0, 0 }, + { "ivp_extrnx16", ICLASS_IVP_EXTRNX16, + 0, + Opcode_ivp_extrnx16_encode_fns, 0, 0 }, + { "ivp_lsnx8s_i", ICLASS_IVP_LSNX8S_I, + 0, + Opcode_ivp_lsnx8s_i_encode_fns, 0, 0 }, + { "ivp_lsnx8s_ip", ICLASS_IVP_LSNX8S_IP, + 0, + Opcode_ivp_lsnx8s_ip_encode_fns, 0, 0 }, + { "ivp_lsnx8s_x", ICLASS_IVP_LSNX8S_X, + 0, + Opcode_ivp_lsnx8s_x_encode_fns, 0, 0 }, + { "ivp_lsnx8s_xp", ICLASS_IVP_LSNX8S_XP, + 0, + Opcode_ivp_lsnx8s_xp_encode_fns, 0, 0 }, + { "ivp_svnx8s_i", ICLASS_IVP_SVNX8S_I, + 0, + Opcode_ivp_svnx8s_i_encode_fns, 0, 0 }, + { "ivp_svnx8s_ip", ICLASS_IVP_SVNX8S_IP, + 0, + Opcode_ivp_svnx8s_ip_encode_fns, 0, 0 }, + { "ivp_svnx8s_x", ICLASS_IVP_SVNX8S_X, + 0, + Opcode_ivp_svnx8s_x_encode_fns, 0, 0 }, + { "ivp_svnx8s_xp", ICLASS_IVP_SVNX8S_XP, + 0, + Opcode_ivp_svnx8s_xp_encode_fns, 0, 0 }, + { "ivp_ssnx8s_i", ICLASS_IVP_SSNX8S_I, + 0, + Opcode_ivp_ssnx8s_i_encode_fns, 0, 0 }, + { "ivp_ssnx8s_ip", ICLASS_IVP_SSNX8S_IP, + 0, + Opcode_ivp_ssnx8s_ip_encode_fns, 0, 0 }, + { "ivp_ssnx8s_x", ICLASS_IVP_SSNX8S_X, + 0, + Opcode_ivp_ssnx8s_x_encode_fns, 0, 0 }, + { "ivp_ssnx8s_xp", ICLASS_IVP_SSNX8S_XP, + 0, + Opcode_ivp_ssnx8s_xp_encode_fns, 0, 0 }, + { "ivp_savnx8s_xp", ICLASS_IVP_SAVNX8S_XP, + 0, + Opcode_ivp_savnx8s_xp_encode_fns, 0, 0 }, + { "ivp_sanx8s_ip", ICLASS_IVP_SANX8S_IP, + 0, + Opcode_ivp_sanx8s_ip_encode_fns, 0, 0 }, + { "ivp_svnx8st_i", ICLASS_IVP_SVNX8ST_I, + 0, + Opcode_ivp_svnx8st_i_encode_fns, 0, 0 }, + { "ivp_svnx8st_ip", ICLASS_IVP_SVNX8ST_IP, + 0, + Opcode_ivp_svnx8st_ip_encode_fns, 0, 0 }, + { "ivp_svnx8st_x", ICLASS_IVP_SVNX8ST_X, + 0, + Opcode_ivp_svnx8st_x_encode_fns, 0, 0 }, + { "ivp_svnx8st_xp", ICLASS_IVP_SVNX8ST_XP, + 0, + Opcode_ivp_svnx8st_xp_encode_fns, 0, 0 }, + { "ivp_movba1", ICLASS_IVP_MOVBA1, + 0, + Opcode_ivp_movba1_encode_fns, 0, 0 }, + { "ivp_movab1", ICLASS_IVP_MOVAB1, + 0, + Opcode_ivp_movab1_encode_fns, 0, 0 }, + { "ivp_notb1", ICLASS_IVP_NOTB1, + 0, + Opcode_ivp_notb1_encode_fns, 0, 0 }, + { "ivp_andnotb1", ICLASS_IVP_ANDNOTB1, + 0, + Opcode_ivp_andnotb1_encode_fns, 0, 0 }, + { "ivp_ornotb1", ICLASS_IVP_ORNOTB1, + 0, + Opcode_ivp_ornotb1_encode_fns, 0, 0 }, + { "ivp_cvt32s2nx24ll", ICLASS_IVP_CVT32S2NX24LL, + 0, + Opcode_ivp_cvt32s2nx24ll_encode_fns, 0, 0 }, + { "ivp_cvt32s2nx24lh", ICLASS_IVP_CVT32S2NX24LH, + 0, + Opcode_ivp_cvt32s2nx24lh_encode_fns, 0, 0 }, + { "ivp_cvt32s2nx24hl", ICLASS_IVP_CVT32S2NX24HL, + 0, + Opcode_ivp_cvt32s2nx24hl_encode_fns, 0, 0 }, + { "ivp_cvt32s2nx24hh", ICLASS_IVP_CVT32S2NX24HH, + 0, + Opcode_ivp_cvt32s2nx24hh_encode_fns, 0, 0 }, + { "ivp_cvt64snx48ll", ICLASS_IVP_CVT64SNX48LL, + 0, + Opcode_ivp_cvt64snx48ll_encode_fns, 0, 0 }, + { "ivp_cvt64snx48lh", ICLASS_IVP_CVT64SNX48LH, + 0, + Opcode_ivp_cvt64snx48lh_encode_fns, 0, 0 }, + { "ivp_cvt64snx48hl", ICLASS_IVP_CVT64SNX48HL, + 0, + Opcode_ivp_cvt64snx48hl_encode_fns, 0, 0 }, + { "ivp_cvt64snx48hh", ICLASS_IVP_CVT64SNX48HH, + 0, + Opcode_ivp_cvt64snx48hh_encode_fns, 0, 0 }, + { "ivp_cvt16s2nx24l", ICLASS_IVP_CVT16S2NX24L, + 0, + Opcode_ivp_cvt16s2nx24l_encode_fns, 0, 0 }, + { "ivp_cvt16s2nx24h", ICLASS_IVP_CVT16S2NX24H, + 0, + Opcode_ivp_cvt16s2nx24h_encode_fns, 0, 0 }, + { "ivp_cvt32snx48l", ICLASS_IVP_CVT32SNX48L, + 0, + Opcode_ivp_cvt32snx48l_encode_fns, 0, 0 }, + { "ivp_cvt32snx48h", ICLASS_IVP_CVT32SNX48H, + 0, + Opcode_ivp_cvt32snx48h_encode_fns, 0, 0 }, + { "ivp_cvt16u2nx24h", ICLASS_IVP_CVT16U2NX24H, + 0, + Opcode_ivp_cvt16u2nx24h_encode_fns, 0, 0 }, + { "ivp_cvt32unx48h", ICLASS_IVP_CVT32UNX48H, + 0, + Opcode_ivp_cvt32unx48h_encode_fns, 0, 0 }, + { "ivp_cvt64un_2x96h", ICLASS_IVP_CVT64UN_2X96H, + 0, + Opcode_ivp_cvt64un_2x96h_encode_fns, 0, 0 }, + { "ivp_cvt16u2nx24l", ICLASS_IVP_CVT16U2NX24L, + 0, + Opcode_ivp_cvt16u2nx24l_encode_fns, 0, 0 }, + { "ivp_cvt24u2nx16", ICLASS_IVP_CVT24U2NX16, + 0, + Opcode_ivp_cvt24u2nx16_encode_fns, 0, 0 }, + { "ivp_cvt24s2nx16", ICLASS_IVP_CVT24S2NX16, + 0, + Opcode_ivp_cvt24s2nx16_encode_fns, 0, 0 }, + { "ivp_cvt32s24", ICLASS_IVP_CVT32S24, + 0, + Opcode_ivp_cvt32s24_encode_fns, 0, 0 }, + { "ivp_cvt24u32", ICLASS_IVP_CVT24U32, + 0, + Opcode_ivp_cvt24u32_encode_fns, 0, 0 }, + { "ivp_cvt24unx32l", ICLASS_IVP_CVT24UNX32L, + 0, + Opcode_ivp_cvt24unx32l_encode_fns, 0, 0 }, + { "ivp_cvt24unx32h", ICLASS_IVP_CVT24UNX32H, + 0, + Opcode_ivp_cvt24unx32h_encode_fns, 0, 0 }, + { "ivp_cvt32unx48l", ICLASS_IVP_CVT32UNX48L, + 0, + Opcode_ivp_cvt32unx48l_encode_fns, 0, 0 }, + { "ivp_cvt48unx32l", ICLASS_IVP_CVT48UNX32L, + 0, + Opcode_ivp_cvt48unx32l_encode_fns, 0, 0 }, + { "ivp_cvt48unx32", ICLASS_IVP_CVT48UNX32, + 0, + Opcode_ivp_cvt48unx32_encode_fns, 0, 0 }, + { "ivp_cvt48snx32l", ICLASS_IVP_CVT48SNX32L, + 0, + Opcode_ivp_cvt48snx32l_encode_fns, 0, 0 }, + { "ivp_cvt48snx32", ICLASS_IVP_CVT48SNX32, + 0, + Opcode_ivp_cvt48snx32_encode_fns, 0, 0 }, + { "ivp_cvt64s48", ICLASS_IVP_CVT64S48, + 0, + Opcode_ivp_cvt64s48_encode_fns, 0, 0 }, + { "ivp_cvt48u64", ICLASS_IVP_CVT48U64, + 0, + Opcode_ivp_cvt48u64_encode_fns, 0, 0 }, + { "ivp_cvt48un_2x64l", ICLASS_IVP_CVT48UN_2X64L, + 0, + Opcode_ivp_cvt48un_2x64l_encode_fns, 0, 0 }, + { "ivp_cvt48un_2x64h", ICLASS_IVP_CVT48UN_2X64H, + 0, + Opcode_ivp_cvt48un_2x64h_encode_fns, 0, 0 }, + { "ivp_cvt64un_2x96l", ICLASS_IVP_CVT64UN_2X96L, + 0, + Opcode_ivp_cvt64un_2x96l_encode_fns, 0, 0 }, + { "ivp_cvt96un_2x64", ICLASS_IVP_CVT96UN_2X64, + 0, + Opcode_ivp_cvt96un_2x64_encode_fns, 0, 0 }, + { "ivp_cvt96u64", ICLASS_IVP_CVT96U64, + 0, + Opcode_ivp_cvt96u64_encode_fns, 0, 0 }, + { "ivp_cvt64u96", ICLASS_IVP_CVT64U96, + 0, + Opcode_ivp_cvt64u96_encode_fns, 0, 0 }, + { "ivp_lb2n_i", ICLASS_IVP_LB2N_I, + 0, + Opcode_ivp_lb2n_i_encode_fns, 0, 0 }, + { "ivp_lb2n_ip", ICLASS_IVP_LB2N_IP, + 0, + Opcode_ivp_lb2n_ip_encode_fns, 0, 0 }, + { "ivp_sb2n_i", ICLASS_IVP_SB2N_I, + 0, + Opcode_ivp_sb2n_i_encode_fns, 0, 0 }, + { "ivp_sb2n_ip", ICLASS_IVP_SB2N_IP, + 0, + Opcode_ivp_sb2n_ip_encode_fns, 0, 0 }, + { "ivp_ltr2n", ICLASS_IVP_LTR2N, + 0, + Opcode_ivp_ltr2n_encode_fns, 0, 0 }, + { "ivp_ltr2ni", ICLASS_IVP_LTR2NI, + 0, + Opcode_ivp_ltr2ni_encode_fns, 0, 0 }, + { "ivp_lvn_2x16u_i", ICLASS_IVP_LVN_2X16U_I, + 0, + Opcode_ivp_lvn_2x16u_i_encode_fns, 0, 0 }, + { "ivp_lvn_2x16u_ip", ICLASS_IVP_LVN_2X16U_IP, + 0, + Opcode_ivp_lvn_2x16u_ip_encode_fns, 0, 0 }, + { "ivp_lvn_2x16u_x", ICLASS_IVP_LVN_2X16U_X, + 0, + Opcode_ivp_lvn_2x16u_x_encode_fns, 0, 0 }, + { "ivp_lvn_2x16u_xp", ICLASS_IVP_LVN_2X16U_XP, + 0, + Opcode_ivp_lvn_2x16u_xp_encode_fns, 0, 0 }, + { "ivp_lvn_2x16ut_i", ICLASS_IVP_LVN_2X16UT_I, + 0, + Opcode_ivp_lvn_2x16ut_i_encode_fns, 0, 0 }, + { "ivp_lvn_2x16ut_ip", ICLASS_IVP_LVN_2X16UT_IP, + 0, + Opcode_ivp_lvn_2x16ut_ip_encode_fns, 0, 0 }, + { "ivp_lvn_2x16ut_x", ICLASS_IVP_LVN_2X16UT_X, + 0, + Opcode_ivp_lvn_2x16ut_x_encode_fns, 0, 0 }, + { "ivp_lvn_2x16ut_xp", ICLASS_IVP_LVN_2X16UT_XP, + 0, + Opcode_ivp_lvn_2x16ut_xp_encode_fns, 0, 0 }, + { "ivp_lvn_2x16s_i", ICLASS_IVP_LVN_2X16S_I, + 0, + Opcode_ivp_lvn_2x16s_i_encode_fns, 0, 0 }, + { "ivp_lvn_2x16s_ip", ICLASS_IVP_LVN_2X16S_IP, + 0, + Opcode_ivp_lvn_2x16s_ip_encode_fns, 0, 0 }, + { "ivp_lvn_2x16s_x", ICLASS_IVP_LVN_2X16S_X, + 0, + Opcode_ivp_lvn_2x16s_x_encode_fns, 0, 0 }, + { "ivp_lvn_2x16s_xp", ICLASS_IVP_LVN_2X16S_XP, + 0, + Opcode_ivp_lvn_2x16s_xp_encode_fns, 0, 0 }, + { "ivp_lvn_2x16st_i", ICLASS_IVP_LVN_2X16ST_I, + 0, + Opcode_ivp_lvn_2x16st_i_encode_fns, 0, 0 }, + { "ivp_lvn_2x16st_ip", ICLASS_IVP_LVN_2X16ST_IP, + 0, + Opcode_ivp_lvn_2x16st_ip_encode_fns, 0, 0 }, + { "ivp_lvn_2x16st_x", ICLASS_IVP_LVN_2X16ST_X, + 0, + Opcode_ivp_lvn_2x16st_x_encode_fns, 0, 0 }, + { "ivp_lvn_2x16st_xp", ICLASS_IVP_LVN_2X16ST_XP, + 0, + Opcode_ivp_lvn_2x16st_xp_encode_fns, 0, 0 }, + { "ivp_svn_2x16u_i", ICLASS_IVP_SVN_2X16U_I, + 0, + Opcode_ivp_svn_2x16u_i_encode_fns, 0, 0 }, + { "ivp_svn_2x16ut_i", ICLASS_IVP_SVN_2X16UT_I, + 0, + Opcode_ivp_svn_2x16ut_i_encode_fns, 0, 0 }, + { "ivp_svn_2x16u_ip", ICLASS_IVP_SVN_2X16U_IP, + 0, + Opcode_ivp_svn_2x16u_ip_encode_fns, 0, 0 }, + { "ivp_svn_2x16ut_ip", ICLASS_IVP_SVN_2X16UT_IP, + 0, + Opcode_ivp_svn_2x16ut_ip_encode_fns, 0, 0 }, + { "ivp_svn_2x16u_x", ICLASS_IVP_SVN_2X16U_X, + 0, + Opcode_ivp_svn_2x16u_x_encode_fns, 0, 0 }, + { "ivp_svn_2x16ut_x", ICLASS_IVP_SVN_2X16UT_X, + 0, + Opcode_ivp_svn_2x16ut_x_encode_fns, 0, 0 }, + { "ivp_svn_2x16u_xp", ICLASS_IVP_SVN_2X16U_XP, + 0, + Opcode_ivp_svn_2x16u_xp_encode_fns, 0, 0 }, + { "ivp_svn_2x16ut_xp", ICLASS_IVP_SVN_2X16UT_XP, + 0, + Opcode_ivp_svn_2x16ut_xp_encode_fns, 0, 0 }, + { "ivp_svn_2x16s_i", ICLASS_IVP_SVN_2X16S_I, + 0, + Opcode_ivp_svn_2x16s_i_encode_fns, 0, 0 }, + { "ivp_svn_2x16st_i", ICLASS_IVP_SVN_2X16ST_I, + 0, + Opcode_ivp_svn_2x16st_i_encode_fns, 0, 0 }, + { "ivp_svn_2x16s_ip", ICLASS_IVP_SVN_2X16S_IP, + 0, + Opcode_ivp_svn_2x16s_ip_encode_fns, 0, 0 }, + { "ivp_svn_2x16st_ip", ICLASS_IVP_SVN_2X16ST_IP, + 0, + Opcode_ivp_svn_2x16st_ip_encode_fns, 0, 0 }, + { "ivp_svn_2x16s_x", ICLASS_IVP_SVN_2X16S_X, + 0, + Opcode_ivp_svn_2x16s_x_encode_fns, 0, 0 }, + { "ivp_svn_2x16st_x", ICLASS_IVP_SVN_2X16ST_X, + 0, + Opcode_ivp_svn_2x16st_x_encode_fns, 0, 0 }, + { "ivp_svn_2x16s_xp", ICLASS_IVP_SVN_2X16S_XP, + 0, + Opcode_ivp_svn_2x16s_xp_encode_fns, 0, 0 }, + { "ivp_svn_2x16st_xp", ICLASS_IVP_SVN_2X16ST_XP, + 0, + Opcode_ivp_svn_2x16st_xp_encode_fns, 0, 0 }, + { "ivp_lan_2x16s_ip", ICLASS_IVP_LAN_2X16S_IP, + 0, + Opcode_ivp_lan_2x16s_ip_encode_fns, 0, 0 }, + { "ivp_lan_2x16u_ip", ICLASS_IVP_LAN_2X16U_IP, + 0, + Opcode_ivp_lan_2x16u_ip_encode_fns, 0, 0 }, + { "ivp_lan_2x16u_xp", ICLASS_IVP_LAN_2X16U_XP, + 0, + Opcode_ivp_lan_2x16u_xp_encode_fns, 0, 0 }, + { "ivp_lan_2x16s_xp", ICLASS_IVP_LAN_2X16S_XP, + 0, + Opcode_ivp_lan_2x16s_xp_encode_fns, 0, 0 }, + { "ivp_san_2x16u_ip", ICLASS_IVP_SAN_2X16U_IP, + 0, + Opcode_ivp_san_2x16u_ip_encode_fns, 0, 0 }, + { "ivp_san_2x16s_ip", ICLASS_IVP_SAN_2X16S_IP, + 0, + Opcode_ivp_san_2x16s_ip_encode_fns, 0, 0 }, + { "ivp_lavn_2x16s_xp", ICLASS_IVP_LAVN_2X16S_XP, + 0, + Opcode_ivp_lavn_2x16s_xp_encode_fns, 0, 0 }, + { "ivp_lavn_2x16u_xp", ICLASS_IVP_LAVN_2X16U_XP, + 0, + Opcode_ivp_lavn_2x16u_xp_encode_fns, 0, 0 }, + { "ivp_savn_2x16u_xp", ICLASS_IVP_SAVN_2X16U_XP, + 0, + Opcode_ivp_savn_2x16u_xp_encode_fns, 0, 0 }, + { "ivp_savn_2x16s_xp", ICLASS_IVP_SAVN_2X16S_XP, + 0, + Opcode_ivp_savn_2x16s_xp_encode_fns, 0, 0 }, + { "ivp_lsn_2x16s_i", ICLASS_IVP_LSN_2X16S_I, + 0, + Opcode_ivp_lsn_2x16s_i_encode_fns, 0, 0 }, + { "ivp_lsn_2x16s_ip", ICLASS_IVP_LSN_2X16S_IP, + 0, + Opcode_ivp_lsn_2x16s_ip_encode_fns, 0, 0 }, + { "ivp_lsn_2x16s_x", ICLASS_IVP_LSN_2X16S_X, + 0, + Opcode_ivp_lsn_2x16s_x_encode_fns, 0, 0 }, + { "ivp_lsn_2x16s_xp", ICLASS_IVP_LSN_2X16S_XP, + 0, + Opcode_ivp_lsn_2x16s_xp_encode_fns, 0, 0 }, + { "ivp_ssn_2x16s_i", ICLASS_IVP_SSN_2X16S_I, + 0, + Opcode_ivp_ssn_2x16s_i_encode_fns, 0, 0 }, + { "ivp_ssn_2x16s_ip", ICLASS_IVP_SSN_2X16S_IP, + 0, + Opcode_ivp_ssn_2x16s_ip_encode_fns, 0, 0 }, + { "ivp_ssn_2x16s_x", ICLASS_IVP_SSN_2X16S_X, + 0, + Opcode_ivp_ssn_2x16s_x_encode_fns, 0, 0 }, + { "ivp_ssn_2x16s_xp", ICLASS_IVP_SSN_2X16S_XP, + 0, + Opcode_ivp_ssn_2x16s_xp_encode_fns, 0, 0 }, + { "ivp_lsn_2x32_i", ICLASS_IVP_LSN_2X32_I, + 0, + Opcode_ivp_lsn_2x32_i_encode_fns, 0, 0 }, + { "ivp_lsn_2x32_ip", ICLASS_IVP_LSN_2X32_IP, + 0, + Opcode_ivp_lsn_2x32_ip_encode_fns, 0, 0 }, + { "ivp_lsn_2x32_x", ICLASS_IVP_LSN_2X32_X, + 0, + Opcode_ivp_lsn_2x32_x_encode_fns, 0, 0 }, + { "ivp_lsn_2x32_xp", ICLASS_IVP_LSN_2X32_XP, + 0, + Opcode_ivp_lsn_2x32_xp_encode_fns, 0, 0 }, + { "ivp_ssn_2x32_i", ICLASS_IVP_SSN_2X32_I, + 0, + Opcode_ivp_ssn_2x32_i_encode_fns, 0, 0 }, + { "ivp_ssn_2x32_ip", ICLASS_IVP_SSN_2X32_IP, + 0, + Opcode_ivp_ssn_2x32_ip_encode_fns, 0, 0 }, + { "ivp_ssn_2x32_x", ICLASS_IVP_SSN_2X32_X, + 0, + Opcode_ivp_ssn_2x32_x_encode_fns, 0, 0 }, + { "ivp_ssn_2x32_xp", ICLASS_IVP_SSN_2X32_XP, + 0, + Opcode_ivp_ssn_2x32_xp_encode_fns, 0, 0 }, + { "ivp_bmaxunx16", ICLASS_IVP_BMAXUNX16, + 0, + Opcode_ivp_bmaxunx16_encode_fns, 0, 0 }, + { "ivp_bminunx16", ICLASS_IVP_BMINUNX16, + 0, + Opcode_ivp_bminunx16_encode_fns, 0, 0 }, + { "ivp_rbminunx16", ICLASS_IVP_RBMINUNX16, + 0, + Opcode_ivp_rbminunx16_encode_fns, 0, 0 }, + { "ivp_rbmaxunx16", ICLASS_IVP_RBMAXUNX16, + 0, + Opcode_ivp_rbmaxunx16_encode_fns, 0, 0 }, + { "ivp_bmax2nx8", ICLASS_IVP_BMAX2NX8, + 0, + Opcode_ivp_bmax2nx8_encode_fns, 0, 0 }, + { "ivp_bmin2nx8", ICLASS_IVP_BMIN2NX8, + 0, + Opcode_ivp_bmin2nx8_encode_fns, 0, 0 }, + { "ivp_bmaxu2nx8", ICLASS_IVP_BMAXU2NX8, + 0, + Opcode_ivp_bmaxu2nx8_encode_fns, 0, 0 }, + { "ivp_bminu2nx8", ICLASS_IVP_BMINU2NX8, + 0, + Opcode_ivp_bminu2nx8_encode_fns, 0, 0 }, + { "ivp_bmaxn_2x32", ICLASS_IVP_BMAXN_2X32, + 0, + Opcode_ivp_bmaxn_2x32_encode_fns, 0, 0 }, + { "ivp_bminn_2x32", ICLASS_IVP_BMINN_2X32, + 0, + Opcode_ivp_bminn_2x32_encode_fns, 0, 0 }, + { "ivp_bmaxun_2x32", ICLASS_IVP_BMAXUN_2X32, + 0, + Opcode_ivp_bmaxun_2x32_encode_fns, 0, 0 }, + { "ivp_bminun_2x32", ICLASS_IVP_BMINUN_2X32, + 0, + Opcode_ivp_bminun_2x32_encode_fns, 0, 0 }, + { "ivp_addn_2x32t", ICLASS_IVP_ADDN_2X32T, + 0, + Opcode_ivp_addn_2x32t_encode_fns, 0, 0 }, + { "ivp_subn_2x32t", ICLASS_IVP_SUBN_2X32T, + 0, + Opcode_ivp_subn_2x32t_encode_fns, 0, 0 }, + { "ivp_add2nx8", ICLASS_IVP_ADD2NX8, + 0, + Opcode_ivp_add2nx8_encode_fns, 0, 0 }, + { "ivp_sub2nx8", ICLASS_IVP_SUB2NX8, + 0, + Opcode_ivp_sub2nx8_encode_fns, 0, 0 }, + { "ivp_neg2nx8", ICLASS_IVP_NEG2NX8, + 0, + Opcode_ivp_neg2nx8_encode_fns, 0, 0 }, + { "ivp_min2nx8", ICLASS_IVP_MIN2NX8, + 0, + Opcode_ivp_min2nx8_encode_fns, 0, 0 }, + { "ivp_minu2nx8", ICLASS_IVP_MINU2NX8, + 0, + Opcode_ivp_minu2nx8_encode_fns, 0, 0 }, + { "ivp_max2nx8", ICLASS_IVP_MAX2NX8, + 0, + Opcode_ivp_max2nx8_encode_fns, 0, 0 }, + { "ivp_maxu2nx8", ICLASS_IVP_MAXU2NX8, + 0, + Opcode_ivp_maxu2nx8_encode_fns, 0, 0 }, + { "ivp_lt2nx8", ICLASS_IVP_LT2NX8, + 0, + Opcode_ivp_lt2nx8_encode_fns, 0, 0 }, + { "ivp_le2nx8", ICLASS_IVP_LE2NX8, + 0, + Opcode_ivp_le2nx8_encode_fns, 0, 0 }, + { "ivp_eq2nx8", ICLASS_IVP_EQ2NX8, + 0, + Opcode_ivp_eq2nx8_encode_fns, 0, 0 }, + { "ivp_neq2nx8", ICLASS_IVP_NEQ2NX8, + 0, + Opcode_ivp_neq2nx8_encode_fns, 0, 0 }, + { "ivp_ltu2nx8", ICLASS_IVP_LTU2NX8, + 0, + Opcode_ivp_ltu2nx8_encode_fns, 0, 0 }, + { "ivp_leu2nx8", ICLASS_IVP_LEU2NX8, + 0, + Opcode_ivp_leu2nx8_encode_fns, 0, 0 }, + { "ivp_add2nx8t", ICLASS_IVP_ADD2NX8T, + 0, + Opcode_ivp_add2nx8t_encode_fns, 0, 0 }, + { "ivp_sub2nx8t", ICLASS_IVP_SUB2NX8T, + 0, + Opcode_ivp_sub2nx8t_encode_fns, 0, 0 }, + { "ivp_selnx16t", ICLASS_IVP_SELNX16T, + 0, + Opcode_ivp_selnx16t_encode_fns, 0, 0 }, + { "ivp_seln_2x32", ICLASS_IVP_SELN_2X32, + 0, + Opcode_ivp_seln_2x32_encode_fns, 0, 0 }, + { "ivp_seln_2x32t", ICLASS_IVP_SELN_2X32T, + 0, + Opcode_ivp_seln_2x32t_encode_fns, 0, 0 }, + { "ivp_shfln_2x32", ICLASS_IVP_SHFLN_2X32, + 0, + Opcode_ivp_shfln_2x32_encode_fns, 0, 0 }, + { "ivp_sllin_2x32", ICLASS_IVP_SLLIN_2X32, + 0, + Opcode_ivp_sllin_2x32_encode_fns, 0, 0 }, + { "ivp_slsin_2x32", ICLASS_IVP_SLSIN_2X32, + 0, + Opcode_ivp_slsin_2x32_encode_fns, 0, 0 }, + { "ivp_srain_2x32", ICLASS_IVP_SRAIN_2X32, + 0, + Opcode_ivp_srain_2x32_encode_fns, 0, 0 }, + { "ivp_srlin_2x32", ICLASS_IVP_SRLIN_2X32, + 0, + Opcode_ivp_srlin_2x32_encode_fns, 0, 0 }, + { "ivp_slln_2x32", ICLASS_IVP_SLLN_2X32, + 0, + Opcode_ivp_slln_2x32_encode_fns, 0, 0 }, + { "ivp_srln_2x32", ICLASS_IVP_SRLN_2X32, + 0, + Opcode_ivp_srln_2x32_encode_fns, 0, 0 }, + { "ivp_slan_2x32", ICLASS_IVP_SLAN_2X32, + 0, + Opcode_ivp_slan_2x32_encode_fns, 0, 0 }, + { "ivp_sran_2x32", ICLASS_IVP_SRAN_2X32, + 0, + Opcode_ivp_sran_2x32_encode_fns, 0, 0 }, + { "ivp_slsn_2x32", ICLASS_IVP_SLSN_2X32, + 0, + Opcode_ivp_slsn_2x32_encode_fns, 0, 0 }, + { "ivp_srsn_2x32", ICLASS_IVP_SRSN_2X32, + 0, + Opcode_ivp_srsn_2x32_encode_fns, 0, 0 }, + { "ivp_raddn_2x32", ICLASS_IVP_RADDN_2X32, + 0, + Opcode_ivp_raddn_2x32_encode_fns, 0, 0 }, + { "ivp_rmaxn_2x32", ICLASS_IVP_RMAXN_2X32, + 0, + Opcode_ivp_rmaxn_2x32_encode_fns, 0, 0 }, + { "ivp_rminn_2x32", ICLASS_IVP_RMINN_2X32, + 0, + Opcode_ivp_rminn_2x32_encode_fns, 0, 0 }, + { "ivp_rmaxun_2x32", ICLASS_IVP_RMAXUN_2X32, + 0, + Opcode_ivp_rmaxun_2x32_encode_fns, 0, 0 }, + { "ivp_rminun_2x32", ICLASS_IVP_RMINUN_2X32, + 0, + Opcode_ivp_rminun_2x32_encode_fns, 0, 0 }, + { "ivp_raddn_2x32t", ICLASS_IVP_RADDN_2X32T, + 0, + Opcode_ivp_raddn_2x32t_encode_fns, 0, 0 }, + { "ivp_abs2nx8", ICLASS_IVP_ABS2NX8, + 0, + Opcode_ivp_abs2nx8_encode_fns, 0, 0 }, + { "ivp_absn_2x32", ICLASS_IVP_ABSN_2X32, + 0, + Opcode_ivp_absn_2x32_encode_fns, 0, 0 }, + { "ivp_mulsgnsnx16", ICLASS_IVP_MULSGNSNX16, + 0, + Opcode_ivp_mulsgnsnx16_encode_fns, 0, 0 }, + { "ivp_rotri2nx8", ICLASS_IVP_ROTRI2NX8, + 0, + Opcode_ivp_rotri2nx8_encode_fns, 0, 0 }, + { "ivp_rotrinx16", ICLASS_IVP_ROTRINX16, + 0, + Opcode_ivp_rotrinx16_encode_fns, 0, 0 }, + { "ivp_rotrin_2x32", ICLASS_IVP_ROTRIN_2X32, + 0, + Opcode_ivp_rotrin_2x32_encode_fns, 0, 0 }, + { "ivp_rotrnx16", ICLASS_IVP_ROTRNX16, + 0, + Opcode_ivp_rotrnx16_encode_fns, 0, 0 }, + { "ivp_rotrn_2x32", ICLASS_IVP_ROTRN_2X32, + 0, + Opcode_ivp_rotrn_2x32_encode_fns, 0, 0 }, + { "ivp_addn_2x32", ICLASS_IVP_ADDN_2X32, + 0, + Opcode_ivp_addn_2x32_encode_fns, 0, 0 }, + { "ivp_subn_2x32", ICLASS_IVP_SUBN_2X32, + 0, + Opcode_ivp_subn_2x32_encode_fns, 0, 0 }, + { "ivp_negn_2x32", ICLASS_IVP_NEGN_2X32, + 0, + Opcode_ivp_negn_2x32_encode_fns, 0, 0 }, + { "ivp_minn_2x32", ICLASS_IVP_MINN_2X32, + 0, + Opcode_ivp_minn_2x32_encode_fns, 0, 0 }, + { "ivp_minun_2x32", ICLASS_IVP_MINUN_2X32, + 0, + Opcode_ivp_minun_2x32_encode_fns, 0, 0 }, + { "ivp_maxn_2x32", ICLASS_IVP_MAXN_2X32, + 0, + Opcode_ivp_maxn_2x32_encode_fns, 0, 0 }, + { "ivp_maxun_2x32", ICLASS_IVP_MAXUN_2X32, + 0, + Opcode_ivp_maxun_2x32_encode_fns, 0, 0 }, + { "ivp_mulsgnn_2x32", ICLASS_IVP_MULSGNN_2X32, + 0, + Opcode_ivp_mulsgnn_2x32_encode_fns, 0, 0 }, + { "ivp_nsan_2x32", ICLASS_IVP_NSAN_2X32, + 0, + Opcode_ivp_nsan_2x32_encode_fns, 0, 0 }, + { "ivp_nsaun_2x32", ICLASS_IVP_NSAUN_2X32, + 0, + Opcode_ivp_nsaun_2x32_encode_fns, 0, 0 }, + { "ivp_ltn_2x32", ICLASS_IVP_LTN_2X32, + 0, + Opcode_ivp_ltn_2x32_encode_fns, 0, 0 }, + { "ivp_len_2x32", ICLASS_IVP_LEN_2X32, + 0, + Opcode_ivp_len_2x32_encode_fns, 0, 0 }, + { "ivp_eqn_2x32", ICLASS_IVP_EQN_2X32, + 0, + Opcode_ivp_eqn_2x32_encode_fns, 0, 0 }, + { "ivp_neqn_2x32", ICLASS_IVP_NEQN_2X32, + 0, + Opcode_ivp_neqn_2x32_encode_fns, 0, 0 }, + { "ivp_ltun_2x32", ICLASS_IVP_LTUN_2X32, + 0, + Opcode_ivp_ltun_2x32_encode_fns, 0, 0 }, + { "ivp_leun_2x32", ICLASS_IVP_LEUN_2X32, + 0, + Opcode_ivp_leun_2x32_encode_fns, 0, 0 }, + { "ivp_lat2nx8_xp", ICLASS_IVP_LAT2NX8_XP, + 0, + Opcode_ivp_lat2nx8_xp_encode_fns, 0, 0 }, + { "ivp_muluu2nx8", ICLASS_IVP_MULUU2NX8, + 0, + Opcode_ivp_muluu2nx8_encode_fns, 0, 0 }, + { "ivp_muluua2nx8", ICLASS_IVP_MULUUA2NX8, + 0, + Opcode_ivp_muluua2nx8_encode_fns, 0, 0 }, + { "ivp_mulus2nx8", ICLASS_IVP_MULUS2NX8, + 0, + Opcode_ivp_mulus2nx8_encode_fns, 0, 0 }, + { "ivp_mulusa2nx8", ICLASS_IVP_MULUSA2NX8, + 0, + Opcode_ivp_mulusa2nx8_encode_fns, 0, 0 }, + { "ivp_muli2nx8x16", ICLASS_IVP_MULI2NX8X16, + 0, + Opcode_ivp_muli2nx8x16_encode_fns, 0, 0 }, + { "ivp_mulai2nx8x16", ICLASS_IVP_MULAI2NX8X16, + 0, + Opcode_ivp_mulai2nx8x16_encode_fns, 0, 0 }, + { "ivp_mulusi2nx8x16", ICLASS_IVP_MULUSI2NX8X16, + 0, + Opcode_ivp_mulusi2nx8x16_encode_fns, 0, 0 }, + { "ivp_mulusai2nx8x16", ICLASS_IVP_MULUSAI2NX8X16, + 0, + Opcode_ivp_mulusai2nx8x16_encode_fns, 0, 0 }, + { "ivp_muli2nr8x16", ICLASS_IVP_MULI2NR8X16, + 0, + Opcode_ivp_muli2nr8x16_encode_fns, 0, 0 }, + { "ivp_mulai2nr8x16", ICLASS_IVP_MULAI2NR8X16, + 0, + Opcode_ivp_mulai2nr8x16_encode_fns, 0, 0 }, + { "ivp_mulusi2nr8x16", ICLASS_IVP_MULUSI2NR8X16, + 0, + Opcode_ivp_mulusi2nr8x16_encode_fns, 0, 0 }, + { "ivp_mulusai2nr8x16", ICLASS_IVP_MULUSAI2NR8X16, + 0, + Opcode_ivp_mulusai2nr8x16_encode_fns, 0, 0 }, + { "ivp_mulusa2n8xr16", ICLASS_IVP_MULUSA2N8XR16, + 0, + Opcode_ivp_mulusa2n8xr16_encode_fns, 0, 0 }, + { "ivp_mulus2n8xr16", ICLASS_IVP_MULUS2N8XR16, + 0, + Opcode_ivp_mulus2n8xr16_encode_fns, 0, 0 }, + { "ivp_mula2n8xr16", ICLASS_IVP_MULA2N8XR16, + 0, + Opcode_ivp_mula2n8xr16_encode_fns, 0, 0 }, + { "ivp_mul2n8xr16", ICLASS_IVP_MUL2N8XR16, + 0, + Opcode_ivp_mul2n8xr16_encode_fns, 0, 0 }, + { "ivp_dsel2nx8i", ICLASS_IVP_DSEL2NX8I, + 0, + Opcode_ivp_dsel2nx8i_encode_fns, 0, 0 }, + { "ivp_dsel2nx8i_h", ICLASS_IVP_DSEL2NX8I_H, + 0, + Opcode_ivp_dsel2nx8i_h_encode_fns, 0, 0 }, + { "ivp_dselnx16", ICLASS_IVP_DSELNX16, + 0, + Opcode_ivp_dselnx16_encode_fns, 0, 0 }, + { "ivp_dselnx16t", ICLASS_IVP_DSELNX16T, + 0, + Opcode_ivp_dselnx16t_encode_fns, 0, 0 }, + { "ivp_injbi2nx8", ICLASS_IVP_INJBI2NX8, + 0, + Opcode_ivp_injbi2nx8_encode_fns, 0, 0 }, + { "ivp_extbi2nx8", ICLASS_IVP_EXTBI2NX8, + 0, + Opcode_ivp_extbi2nx8_encode_fns, 0, 0 }, + { "ivp_movva32", ICLASS_IVP_MOVVA32, + 0, + Opcode_ivp_movva32_encode_fns, 0, 0 }, + { "ivp_movav32", ICLASS_IVP_MOVAV32, + 0, + Opcode_ivp_movav32_encode_fns, 0, 0 }, + { "ivp_movww", ICLASS_IVP_MOVWW, + 0, + Opcode_ivp_movww_encode_fns, 0, 0 }, + { "ivp_ls2nx8_i", ICLASS_IVP_LS2NX8_I, + 0, + Opcode_ivp_ls2nx8_i_encode_fns, 0, 0 }, + { "ivp_ls2nx8_ip", ICLASS_IVP_LS2NX8_IP, + 0, + Opcode_ivp_ls2nx8_ip_encode_fns, 0, 0 }, + { "ivp_ls2nx8_x", ICLASS_IVP_LS2NX8_X, + 0, + Opcode_ivp_ls2nx8_x_encode_fns, 0, 0 }, + { "ivp_ls2nx8_xp", ICLASS_IVP_LS2NX8_XP, + 0, + Opcode_ivp_ls2nx8_xp_encode_fns, 0, 0 }, + { "ivp_ss2nx8_i", ICLASS_IVP_SS2NX8_I, + 0, + Opcode_ivp_ss2nx8_i_encode_fns, 0, 0 }, + { "ivp_ss2nx8_ip", ICLASS_IVP_SS2NX8_IP, + 0, + Opcode_ivp_ss2nx8_ip_encode_fns, 0, 0 }, + { "ivp_ss2nx8_x", ICLASS_IVP_SS2NX8_X, + 0, + Opcode_ivp_ss2nx8_x_encode_fns, 0, 0 }, + { "ivp_ss2nx8_xp", ICLASS_IVP_SS2NX8_XP, + 0, + Opcode_ivp_ss2nx8_xp_encode_fns, 0, 0 }, + { "ivp_lanx8s_xp", ICLASS_IVP_LANX8S_XP, + 0, + Opcode_ivp_lanx8s_xp_encode_fns, 0, 0 }, + { "ivp_lanx8u_xp", ICLASS_IVP_LANX8U_XP, + 0, + Opcode_ivp_lanx8u_xp_encode_fns, 0, 0 }, + { "ivp_la2nx8_xp", ICLASS_IVP_LA2NX8_XP, + 0, + Opcode_ivp_la2nx8_xp_encode_fns, 0, 0 }, + { "ivp_abssubu2nx8", ICLASS_IVP_ABSSUBU2NX8, + 0, + Opcode_ivp_abssubu2nx8_encode_fns, 0, 0 }, + { "ivp_abssub2nx8", ICLASS_IVP_ABSSUB2NX8, + 0, + Opcode_ivp_abssub2nx8_encode_fns, 0, 0 }, + { "ivp_movvint8", ICLASS_IVP_MOVVINT8, + 0, + Opcode_ivp_movvint8_encode_fns, 0, 0 }, + { "ivp_movva8", ICLASS_IVP_MOVVA8, + 0, + Opcode_ivp_movva8_encode_fns, 0, 0 }, + { "ivp_movavu8", ICLASS_IVP_MOVAVU8, + 0, + Opcode_ivp_movavu8_encode_fns, 0, 0 }, + { "ivp_slli2nx8", ICLASS_IVP_SLLI2NX8, + 0, + Opcode_ivp_slli2nx8_encode_fns, 0, 0 }, + { "ivp_srai2nx8", ICLASS_IVP_SRAI2NX8, + 0, + Opcode_ivp_srai2nx8_encode_fns, 0, 0 }, + { "ivp_srli2nx8", ICLASS_IVP_SRLI2NX8, + 0, + Opcode_ivp_srli2nx8_encode_fns, 0, 0 }, + { "ivp_packl2nx24", ICLASS_IVP_PACKL2NX24, + 0, + Opcode_ivp_packl2nx24_encode_fns, 0, 0 }, + { "ivp_packvr2nx24", ICLASS_IVP_PACKVR2NX24, + 0, + Opcode_ivp_packvr2nx24_encode_fns, 0, 0 }, + { "ivp_packvru2nx24", ICLASS_IVP_PACKVRU2NX24, + 0, + Opcode_ivp_packvru2nx24_encode_fns, 0, 0 }, + { "ivp_packlnx48", ICLASS_IVP_PACKLNX48, + 0, + Opcode_ivp_packlnx48_encode_fns, 0, 0 }, + { "ivp_packl2nx24_1", ICLASS_IVP_PACKL2NX24_1, + 0, + Opcode_ivp_packl2nx24_1_encode_fns, 0, 0 }, + { "ivp_packvr2nx24_0", ICLASS_IVP_PACKVR2NX24_0, + 0, + Opcode_ivp_packvr2nx24_0_encode_fns, 0, 0 }, + { "ivp_packvr2nx24_1", ICLASS_IVP_PACKVR2NX24_1, + 0, + Opcode_ivp_packvr2nx24_1_encode_fns, 0, 0 }, + { "ivp_packvru2nx24_0", ICLASS_IVP_PACKVRU2NX24_0, + 0, + Opcode_ivp_packvru2nx24_0_encode_fns, 0, 0 }, + { "ivp_packvru2nx24_1", ICLASS_IVP_PACKVRU2NX24_1, + 0, + Opcode_ivp_packvru2nx24_1_encode_fns, 0, 0 }, + { "ivp_packvrnr2nx24_0", ICLASS_IVP_PACKVRNR2NX24_0, + 0, + Opcode_ivp_packvrnr2nx24_0_encode_fns, 0, 0 }, + { "ivp_packvrnr2nx24_1", ICLASS_IVP_PACKVRNR2NX24_1, + 0, + Opcode_ivp_packvrnr2nx24_1_encode_fns, 0, 0 }, + { "ivp_packmnx48", ICLASS_IVP_PACKMNX48, + 0, + Opcode_ivp_packmnx48_encode_fns, 0, 0 }, + { "ivp_packvrnx48", ICLASS_IVP_PACKVRNX48, + 0, + Opcode_ivp_packvrnx48_encode_fns, 0, 0 }, + { "ivp_unpks2nx8_0", ICLASS_IVP_UNPKS2NX8_0, + 0, + Opcode_ivp_unpks2nx8_0_encode_fns, 0, 0 }, + { "ivp_unpks2nx8_1", ICLASS_IVP_UNPKS2NX8_1, + 0, + Opcode_ivp_unpks2nx8_1_encode_fns, 0, 0 }, + { "ivp_unpksnx16_l", ICLASS_IVP_UNPKSNX16_L, + 0, + Opcode_ivp_unpksnx16_l_encode_fns, 0, 0 }, + { "ivp_unpksnx16_h", ICLASS_IVP_UNPKSNX16_H, + 0, + Opcode_ivp_unpksnx16_h_encode_fns, 0, 0 }, + { "ivp_sel2nx8i", ICLASS_IVP_SEL2NX8I, + 0, + Opcode_ivp_sel2nx8i_encode_fns, 0, 0 }, + { "ivp_sel2nx8i_s0", ICLASS_IVP_SEL2NX8I_S0, + 0, + Opcode_ivp_sel2nx8i_s0_encode_fns, 0, 0 }, + { "ivp_sel2nx8i_s2", ICLASS_IVP_SEL2NX8I_S2, + 0, + Opcode_ivp_sel2nx8i_s2_encode_fns, 0, 0 }, + { "ivp_sel2nx8i_s4", ICLASS_IVP_SEL2NX8I_S4, + 0, + Opcode_ivp_sel2nx8i_s4_encode_fns, 0, 0 }, + { "ivp_shfl2nx8i", ICLASS_IVP_SHFL2NX8I, + 0, + Opcode_ivp_shfl2nx8i_encode_fns, 0, 0 }, + { "ivp_shfl2nx8i_s0", ICLASS_IVP_SHFL2NX8I_S0, + 0, + Opcode_ivp_shfl2nx8i_s0_encode_fns, 0, 0 }, + { "ivp_shfl2nx8i_s2", ICLASS_IVP_SHFL2NX8I_S2, + 0, + Opcode_ivp_shfl2nx8i_s2_encode_fns, 0, 0 }, + { "ivp_shfl2nx8i_s4", ICLASS_IVP_SHFL2NX8I_S4, + 0, + Opcode_ivp_shfl2nx8i_s4_encode_fns, 0, 0 }, + { "ivp_sel2nx8", ICLASS_IVP_SEL2NX8, + 0, + Opcode_ivp_sel2nx8_encode_fns, 0, 0 }, + { "ivp_shfl2nx8", ICLASS_IVP_SHFL2NX8, + 0, + Opcode_ivp_shfl2nx8_encode_fns, 0, 0 }, + { "ivp_sel2nx8t", ICLASS_IVP_SEL2NX8T, + 0, + Opcode_ivp_sel2nx8t_encode_fns, 0, 0 }, + { "ivp_sqzn", ICLASS_IVP_SQZN, + 0, + Opcode_ivp_sqzn_encode_fns, 0, 0 }, + { "ivp_unsqzn", ICLASS_IVP_UNSQZN, + 0, + Opcode_ivp_unsqzn_encode_fns, 0, 0 }, + { "ivp_mulnx16", ICLASS_IVP_MULNX16, + 0, + Opcode_ivp_mulnx16_encode_fns, 0, 0 }, + { "ivp_mulanx16", ICLASS_IVP_MULANX16, + 0, + Opcode_ivp_mulanx16_encode_fns, 0, 0 }, + { "ivp_muluunx16", ICLASS_IVP_MULUUNX16, + 0, + Opcode_ivp_muluunx16_encode_fns, 0, 0 }, + { "ivp_muluuanx16", ICLASS_IVP_MULUUANX16, + 0, + Opcode_ivp_muluuanx16_encode_fns, 0, 0 }, + { "ivp_mulusnx16", ICLASS_IVP_MULUSNX16, + 0, + Opcode_ivp_mulusnx16_encode_fns, 0, 0 }, + { "ivp_mulusanx16", ICLASS_IVP_MULUSANX16, + 0, + Opcode_ivp_mulusanx16_encode_fns, 0, 0 }, + { "ivp_mul2nx8", ICLASS_IVP_MUL2NX8, + 0, + Opcode_ivp_mul2nx8_encode_fns, 0, 0 }, + { "ivp_mula2nx8", ICLASS_IVP_MULA2NX8, + 0, + Opcode_ivp_mula2nx8_encode_fns, 0, 0 }, + { "ivp_addw2nx8", ICLASS_IVP_ADDW2NX8, + 0, + Opcode_ivp_addw2nx8_encode_fns, 0, 0 }, + { "ivp_addwa2nx8", ICLASS_IVP_ADDWA2NX8, + 0, + Opcode_ivp_addwa2nx8_encode_fns, 0, 0 }, + { "ivp_addws2nx8", ICLASS_IVP_ADDWS2NX8, + 0, + Opcode_ivp_addws2nx8_encode_fns, 0, 0 }, + { "ivp_addwu2nx8", ICLASS_IVP_ADDWU2NX8, + 0, + Opcode_ivp_addwu2nx8_encode_fns, 0, 0 }, + { "ivp_addwua2nx8", ICLASS_IVP_ADDWUA2NX8, + 0, + Opcode_ivp_addwua2nx8_encode_fns, 0, 0 }, + { "ivp_addwus2nx8", ICLASS_IVP_ADDWUS2NX8, + 0, + Opcode_ivp_addwus2nx8_encode_fns, 0, 0 }, + { "ivp_divn_2x32x16s_4step0", ICLASS_IVP_DIVN_2X32X16S_4STEP0, + 0, + Opcode_ivp_divn_2x32x16s_4step0_encode_fns, 0, 0 }, + { "ivp_divn_2x32x16s_4step", ICLASS_IVP_DIVN_2X32X16S_4STEP, + 0, + Opcode_ivp_divn_2x32x16s_4step_encode_fns, 0, 0 }, + { "ivp_divn_2x32x16s_4stepn", ICLASS_IVP_DIVN_2X32X16S_4STEPN, + 0, + Opcode_ivp_divn_2x32x16s_4stepn_encode_fns, 0, 0 }, + { "ivp_divn_2x32x16u_4step0", ICLASS_IVP_DIVN_2X32X16U_4STEP0, + 0, + Opcode_ivp_divn_2x32x16u_4step0_encode_fns, 0, 0 }, + { "ivp_divn_2x32x16u_4step", ICLASS_IVP_DIVN_2X32X16U_4STEP, + 0, + Opcode_ivp_divn_2x32x16u_4step_encode_fns, 0, 0 }, + { "ivp_divn_2x32x16u_4stepn", ICLASS_IVP_DIVN_2X32X16U_4STEPN, + 0, + Opcode_ivp_divn_2x32x16u_4stepn_encode_fns, 0, 0 }, + { "ivp_divnx16s_4step0", ICLASS_IVP_DIVNX16S_4STEP0, + 0, + Opcode_ivp_divnx16s_4step0_encode_fns, 0, 0 }, + { "ivp_divnx16s_4step", ICLASS_IVP_DIVNX16S_4STEP, + 0, + Opcode_ivp_divnx16s_4step_encode_fns, 0, 0 }, + { "ivp_divnx16s_4stepn", ICLASS_IVP_DIVNX16S_4STEPN, + 0, + Opcode_ivp_divnx16s_4stepn_encode_fns, 0, 0 }, + { "ivp_divnx16u_4step0", ICLASS_IVP_DIVNX16U_4STEP0, + 0, + Opcode_ivp_divnx16u_4step0_encode_fns, 0, 0 }, + { "ivp_divnx16u_4step", ICLASS_IVP_DIVNX16U_4STEP, + 0, + Opcode_ivp_divnx16u_4step_encode_fns, 0, 0 }, + { "ivp_divnx16u_4stepn", ICLASS_IVP_DIVNX16U_4STEPN, + 0, + Opcode_ivp_divnx16u_4stepn_encode_fns, 0, 0 }, + { "ivp_divnx16sq_4step0", ICLASS_IVP_DIVNX16SQ_4STEP0, + 0, + Opcode_ivp_divnx16sq_4step0_encode_fns, 0, 0 }, + { "ivp_divnx16q_4step0", ICLASS_IVP_DIVNX16Q_4STEP0, + 0, + Opcode_ivp_divnx16q_4step0_encode_fns, 0, 0 }, + { "ivp_mulsnx16", ICLASS_IVP_MULSNX16, + 0, + Opcode_ivp_mulsnx16_encode_fns, 0, 0 }, + { "ivp_muluusnx16", ICLASS_IVP_MULUUSNX16, + 0, + Opcode_ivp_muluusnx16_encode_fns, 0, 0 }, + { "ivp_mulussnx16", ICLASS_IVP_MULUSSNX16, + 0, + Opcode_ivp_mulussnx16_encode_fns, 0, 0 }, + { "ivp_muln_2x16x32_0", ICLASS_IVP_MULN_2X16X32_0, + 0, + Opcode_ivp_muln_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_muluun_2x16x32_0", ICLASS_IVP_MULUUN_2X16X32_0, + 0, + Opcode_ivp_muluun_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_mulusn_2x16x32_0", ICLASS_IVP_MULUSN_2X16X32_0, + 0, + Opcode_ivp_mulusn_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_mulsun_2x16x32_0", ICLASS_IVP_MULSUN_2X16X32_0, + 0, + Opcode_ivp_mulsun_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_muln_2x16x32_1", ICLASS_IVP_MULN_2X16X32_1, + 0, + Opcode_ivp_muln_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_muluun_2x16x32_1", ICLASS_IVP_MULUUN_2X16X32_1, + 0, + Opcode_ivp_muluun_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulusn_2x16x32_1", ICLASS_IVP_MULUSN_2X16X32_1, + 0, + Opcode_ivp_mulusn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulsun_2x16x32_1", ICLASS_IVP_MULSUN_2X16X32_1, + 0, + Opcode_ivp_mulsun_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulhn_2x16x32_1", ICLASS_IVP_MULHN_2X16X32_1, + 0, + Opcode_ivp_mulhn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_muluuhn_2x16x32_1", ICLASS_IVP_MULUUHN_2X16X32_1, + 0, + Opcode_ivp_muluuhn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulushn_2x16x32_1", ICLASS_IVP_MULUSHN_2X16X32_1, + 0, + Opcode_ivp_mulushn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulsuhn_2x16x32_1", ICLASS_IVP_MULSUHN_2X16X32_1, + 0, + Opcode_ivp_mulsuhn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulan_2x16x32_0", ICLASS_IVP_MULAN_2X16X32_0, + 0, + Opcode_ivp_mulan_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_muluuan_2x16x32_0", ICLASS_IVP_MULUUAN_2X16X32_0, + 0, + Opcode_ivp_muluuan_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_mulusan_2x16x32_0", ICLASS_IVP_MULUSAN_2X16X32_0, + 0, + Opcode_ivp_mulusan_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_mulsuan_2x16x32_0", ICLASS_IVP_MULSUAN_2X16X32_0, + 0, + Opcode_ivp_mulsuan_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_mulahn_2x16x32_1", ICLASS_IVP_MULAHN_2X16X32_1, + 0, + Opcode_ivp_mulahn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_muluuahn_2x16x32_1", ICLASS_IVP_MULUUAHN_2X16X32_1, + 0, + Opcode_ivp_muluuahn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulusahn_2x16x32_1", ICLASS_IVP_MULUSAHN_2X16X32_1, + 0, + Opcode_ivp_mulusahn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulsuahn_2x16x32_1", ICLASS_IVP_MULSUAHN_2X16X32_1, + 0, + Opcode_ivp_mulsuahn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulan_2x16x32_1", ICLASS_IVP_MULAN_2X16X32_1, + 0, + Opcode_ivp_mulan_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_muluuan_2x16x32_1", ICLASS_IVP_MULUUAN_2X16X32_1, + 0, + Opcode_ivp_muluuan_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulusan_2x16x32_1", ICLASS_IVP_MULUSAN_2X16X32_1, + 0, + Opcode_ivp_mulusan_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulsuan_2x16x32_1", ICLASS_IVP_MULSUAN_2X16X32_1, + 0, + Opcode_ivp_mulsuan_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulshn_2x16x32_1", ICLASS_IVP_MULSHN_2X16X32_1, + 0, + Opcode_ivp_mulshn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_muluushn_2x16x32_1", ICLASS_IVP_MULUUSHN_2X16X32_1, + 0, + Opcode_ivp_muluushn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulusshn_2x16x32_1", ICLASS_IVP_MULUSSHN_2X16X32_1, + 0, + Opcode_ivp_mulusshn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulsushn_2x16x32_1", ICLASS_IVP_MULSUSHN_2X16X32_1, + 0, + Opcode_ivp_mulsushn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulsn_2x16x32_0", ICLASS_IVP_MULSN_2X16X32_0, + 0, + Opcode_ivp_mulsn_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_muluusn_2x16x32_0", ICLASS_IVP_MULUUSN_2X16X32_0, + 0, + Opcode_ivp_muluusn_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_mulussn_2x16x32_0", ICLASS_IVP_MULUSSN_2X16X32_0, + 0, + Opcode_ivp_mulussn_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_mulsusn_2x16x32_0", ICLASS_IVP_MULSUSN_2X16X32_0, + 0, + Opcode_ivp_mulsusn_2x16x32_0_encode_fns, 0, 0 }, + { "ivp_mulsn_2x16x32_1", ICLASS_IVP_MULSN_2X16X32_1, + 0, + Opcode_ivp_mulsn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_muluusn_2x16x32_1", ICLASS_IVP_MULUUSN_2X16X32_1, + 0, + Opcode_ivp_muluusn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulussn_2x16x32_1", ICLASS_IVP_MULUSSN_2X16X32_1, + 0, + Opcode_ivp_mulussn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_mulsusn_2x16x32_1", ICLASS_IVP_MULSUSN_2X16X32_1, + 0, + Opcode_ivp_mulsusn_2x16x32_1_encode_fns, 0, 0 }, + { "ivp_packln_2x96", ICLASS_IVP_PACKLN_2X96, + 0, + Opcode_ivp_packln_2x96_encode_fns, 0, 0 }, + { "ivp_packhn_2x64w", ICLASS_IVP_PACKHN_2X64W, + 0, + Opcode_ivp_packhn_2x64w_encode_fns, 0, 0 }, + { "ivp_packvrn_2x64w", ICLASS_IVP_PACKVRN_2X64W, + 0, + Opcode_ivp_packvrn_2x64w_encode_fns, 0, 0 }, + { "ivp_packvrnrn_2x64w", ICLASS_IVP_PACKVRNRN_2X64W, + 0, + Opcode_ivp_packvrnrn_2x64w_encode_fns, 0, 0 }, + { "ivp_packvrnx48_0", ICLASS_IVP_PACKVRNX48_0, + 0, + Opcode_ivp_packvrnx48_0_encode_fns, 0, 0 }, + { "ivp_packvrnx48_1", ICLASS_IVP_PACKVRNX48_1, + 0, + Opcode_ivp_packvrnx48_1_encode_fns, 0, 0 }, + { "ivp_packvrnrnx48_0", ICLASS_IVP_PACKVRNRNX48_0, + 0, + Opcode_ivp_packvrnrnx48_0_encode_fns, 0, 0 }, + { "ivp_packvrnrnx48_1", ICLASS_IVP_PACKVRNRNX48_1, + 0, + Opcode_ivp_packvrnrnx48_1_encode_fns, 0, 0 }, + { "ivp_packvrnrnx48", ICLASS_IVP_PACKVRNRNX48, + 0, + Opcode_ivp_packvrnrnx48_encode_fns, 0, 0 }, + { "ivp_packvrnr2nx24", ICLASS_IVP_PACKVRNR2NX24, + 0, + Opcode_ivp_packvrnr2nx24_encode_fns, 0, 0 }, + { "ivp_l2a4nx8_ip", ICLASS_IVP_L2A4NX8_IP, + 0, + Opcode_ivp_l2a4nx8_ip_encode_fns, 0, 0 }, + { "ivp_l2au2nx8_ip", ICLASS_IVP_L2AU2NX8_IP, + 0, + Opcode_ivp_l2au2nx8_ip_encode_fns, 0, 0 }, + { "ivp_l2u2nx8_xp", ICLASS_IVP_L2U2NX8_XP, + 0, + Opcode_ivp_l2u2nx8_xp_encode_fns, 0, 0 }, + { "ivp_avgu2nx8", ICLASS_IVP_AVGU2NX8, + 0, + Opcode_ivp_avgu2nx8_encode_fns, 0, 0 }, + { "ivp_avgru2nx8", ICLASS_IVP_AVGRU2NX8, + 0, + Opcode_ivp_avgru2nx8_encode_fns, 0, 0 }, + { "ivp_radd2nx8", ICLASS_IVP_RADD2NX8, + 0, + Opcode_ivp_radd2nx8_encode_fns, 0, 0 }, + { "ivp_radd2nx8t", ICLASS_IVP_RADD2NX8T, + 0, + Opcode_ivp_radd2nx8t_encode_fns, 0, 0 }, + { "ivp_raddunx16", ICLASS_IVP_RADDUNX16, + 0, + Opcode_ivp_raddunx16_encode_fns, 0, 0 }, + { "ivp_raddunx16t", ICLASS_IVP_RADDUNX16T, + 0, + Opcode_ivp_raddunx16t_encode_fns, 0, 0 }, + { "ivp_raddu2nx8", ICLASS_IVP_RADDU2NX8, + 0, + Opcode_ivp_raddu2nx8_encode_fns, 0, 0 }, + { "ivp_raddu2nx8t", ICLASS_IVP_RADDU2NX8T, + 0, + Opcode_ivp_raddu2nx8t_encode_fns, 0, 0 }, + { "ivp_ltrs2n", ICLASS_IVP_LTRS2N, + 0, + Opcode_ivp_ltrs2n_encode_fns, 0, 0 }, + { "ivp_ltrsn", ICLASS_IVP_LTRSN, + 0, + Opcode_ivp_ltrsn_encode_fns, 0, 0 }, + { "ivp_ltrsn_2", ICLASS_IVP_LTRSN_2, + 0, + Opcode_ivp_ltrsn_2_encode_fns, 0, 0 }, + { "ivp_seq2nx8", ICLASS_IVP_SEQ2NX8, + 0, + Opcode_ivp_seq2nx8_encode_fns, 0, 0 }, + { "ivp_seqn_2x32", ICLASS_IVP_SEQN_2X32, + 0, + Opcode_ivp_seqn_2x32_encode_fns, 0, 0 }, + { "ivp_extrn_2x32", ICLASS_IVP_EXTRN_2X32, + 0, + Opcode_ivp_extrn_2x32_encode_fns, 0, 0 }, + { "ivp_unpku2nx8_0", ICLASS_IVP_UNPKU2NX8_0, + 0, + Opcode_ivp_unpku2nx8_0_encode_fns, 0, 0 }, + { "ivp_unpku2nx8_1", ICLASS_IVP_UNPKU2NX8_1, + 0, + Opcode_ivp_unpku2nx8_1_encode_fns, 0, 0 }, + { "ivp_baddnormnx16", ICLASS_IVP_BADDNORMNX16, + 0, + Opcode_ivp_baddnormnx16_encode_fns, 0, 0 }, + { "ivp_bsubnormnx16", ICLASS_IVP_BSUBNORMNX16, + 0, + Opcode_ivp_bsubnormnx16_encode_fns, 0, 0 }, + { "ivp_raddsnx16", ICLASS_IVP_RADDSNX16, + 0, + Opcode_ivp_raddsnx16_encode_fns, 0, 0 }, + { "ivp_raddsnx16t", ICLASS_IVP_RADDSNX16T, + 0, + Opcode_ivp_raddsnx16t_encode_fns, 0, 0 }, + { "ivp_ornotb", ICLASS_IVP_ORNOTB, + 0, + Opcode_ivp_ornotb_encode_fns, 0, 0 }, + { "ivp_extr2nx8", ICLASS_IVP_EXTR2NX8, + 0, + Opcode_ivp_extr2nx8_encode_fns, 0, 0 }, + { "ivp_extrvrn_2x32", ICLASS_IVP_EXTRVRN_2X32, + 0, + Opcode_ivp_extrvrn_2x32_encode_fns, 0, 0 }, + { "ivp_movav8", ICLASS_IVP_MOVAV8, + 0, + Opcode_ivp_movav8_encode_fns, 0, 0 }, + { "ivp_mulpn16xr16", ICLASS_IVP_MULPN16XR16, + 0, + Opcode_ivp_mulpn16xr16_encode_fns, 0, 0 }, + { "ivp_mulpan16xr16", ICLASS_IVP_MULPAN16XR16, + 0, + Opcode_ivp_mulpan16xr16_encode_fns, 0, 0 }, + { "ivp_muluspn16xr16", ICLASS_IVP_MULUSPN16XR16, + 0, + Opcode_ivp_muluspn16xr16_encode_fns, 0, 0 }, + { "ivp_muluspan16xr16", ICLASS_IVP_MULUSPAN16XR16, + 0, + Opcode_ivp_muluspan16xr16_encode_fns, 0, 0 }, + { "ivp_mulp2n8xr16", ICLASS_IVP_MULP2N8XR16, + 0, + Opcode_ivp_mulp2n8xr16_encode_fns, 0, 0 }, + { "ivp_mulpa2n8xr16", ICLASS_IVP_MULPA2N8XR16, + 0, + Opcode_ivp_mulpa2n8xr16_encode_fns, 0, 0 }, + { "ivp_mulusp2n8xr16", ICLASS_IVP_MULUSP2N8XR16, + 0, + Opcode_ivp_mulusp2n8xr16_encode_fns, 0, 0 }, + { "ivp_muluspa2n8xr16", ICLASS_IVP_MULUSPA2N8XR16, + 0, + Opcode_ivp_muluspa2n8xr16_encode_fns, 0, 0 }, + { "ivp_mulpnx16", ICLASS_IVP_MULPNX16, + 0, + Opcode_ivp_mulpnx16_encode_fns, 0, 0 }, + { "ivp_mulpanx16", ICLASS_IVP_MULPANX16, + 0, + Opcode_ivp_mulpanx16_encode_fns, 0, 0 }, + { "ivp_muluspnx16", ICLASS_IVP_MULUSPNX16, + 0, + Opcode_ivp_muluspnx16_encode_fns, 0, 0 }, + { "ivp_muluspanx16", ICLASS_IVP_MULUSPANX16, + 0, + Opcode_ivp_muluspanx16_encode_fns, 0, 0 }, + { "ivp_muluupnx16", ICLASS_IVP_MULUUPNX16, + 0, + Opcode_ivp_muluupnx16_encode_fns, 0, 0 }, + { "ivp_muluupanx16", ICLASS_IVP_MULUUPANX16, + 0, + Opcode_ivp_muluupanx16_encode_fns, 0, 0 }, + { "ivp_mulp2nx8", ICLASS_IVP_MULP2NX8, + 0, + Opcode_ivp_mulp2nx8_encode_fns, 0, 0 }, + { "ivp_mulpa2nx8", ICLASS_IVP_MULPA2NX8, + 0, + Opcode_ivp_mulpa2nx8_encode_fns, 0, 0 }, + { "ivp_mulusp2nx8", ICLASS_IVP_MULUSP2NX8, + 0, + Opcode_ivp_mulusp2nx8_encode_fns, 0, 0 }, + { "ivp_muluspa2nx8", ICLASS_IVP_MULUSPA2NX8, + 0, + Opcode_ivp_muluspa2nx8_encode_fns, 0, 0 }, + { "ivp_muluup2nx8", ICLASS_IVP_MULUUP2NX8, + 0, + Opcode_ivp_muluup2nx8_encode_fns, 0, 0 }, + { "ivp_muluupa2nx8", ICLASS_IVP_MULUUPA2NX8, + 0, + Opcode_ivp_muluupa2nx8_encode_fns, 0, 0 }, + { "ivp_mulpi2nr8x16", ICLASS_IVP_MULPI2NR8X16, + 0, + Opcode_ivp_mulpi2nr8x16_encode_fns, 0, 0 }, + { "ivp_mulpai2nr8x16", ICLASS_IVP_MULPAI2NR8X16, + 0, + Opcode_ivp_mulpai2nr8x16_encode_fns, 0, 0 }, + { "ivp_muluspi2nr8x16", ICLASS_IVP_MULUSPI2NR8X16, + 0, + Opcode_ivp_muluspi2nr8x16_encode_fns, 0, 0 }, + { "ivp_muluspai2nr8x16", ICLASS_IVP_MULUSPAI2NR8X16, + 0, + Opcode_ivp_muluspai2nr8x16_encode_fns, 0, 0 }, + { "ivp_mulq2n8xr8", ICLASS_IVP_MULQ2N8XR8, + 0, + Opcode_ivp_mulq2n8xr8_encode_fns, 0, 0 }, + { "ivp_mulqa2n8xr8", ICLASS_IVP_MULQA2N8XR8, + 0, + Opcode_ivp_mulqa2n8xr8_encode_fns, 0, 0 }, + { "ivp_mulusq2n8xr8", ICLASS_IVP_MULUSQ2N8XR8, + 0, + Opcode_ivp_mulusq2n8xr8_encode_fns, 0, 0 }, + { "ivp_mulusqa2n8xr8", ICLASS_IVP_MULUSQA2N8XR8, + 0, + Opcode_ivp_mulusqa2n8xr8_encode_fns, 0, 0 }, + { "ivp_mul4t2n8xr8", ICLASS_IVP_MUL4T2N8XR8, + 0, + Opcode_ivp_mul4t2n8xr8_encode_fns, 0, 0 }, + { "ivp_mul4ta2n8xr8", ICLASS_IVP_MUL4TA2N8XR8, + 0, + Opcode_ivp_mul4ta2n8xr8_encode_fns, 0, 0 }, + { "ivp_mulus4t2n8xr8", ICLASS_IVP_MULUS4T2N8XR8, + 0, + Opcode_ivp_mulus4t2n8xr8_encode_fns, 0, 0 }, + { "ivp_mulus4ta2n8xr8", ICLASS_IVP_MULUS4TA2N8XR8, + 0, + Opcode_ivp_mulus4ta2n8xr8_encode_fns, 0, 0 }, + { "ivp_addwnx16", ICLASS_IVP_ADDWNX16, + 0, + Opcode_ivp_addwnx16_encode_fns, 0, 0 }, + { "ivp_addwanx16", ICLASS_IVP_ADDWANX16, + 0, + Opcode_ivp_addwanx16_encode_fns, 0, 0 }, + { "ivp_addwsnx16", ICLASS_IVP_ADDWSNX16, + 0, + Opcode_ivp_addwsnx16_encode_fns, 0, 0 }, + { "ivp_addwunx16", ICLASS_IVP_ADDWUNX16, + 0, + Opcode_ivp_addwunx16_encode_fns, 0, 0 }, + { "ivp_addwuanx16", ICLASS_IVP_ADDWUANX16, + 0, + Opcode_ivp_addwuanx16_encode_fns, 0, 0 }, + { "ivp_addwusnx16", ICLASS_IVP_ADDWUSNX16, + 0, + Opcode_ivp_addwusnx16_encode_fns, 0, 0 }, + { "ivp_subwnx16", ICLASS_IVP_SUBWNX16, + 0, + Opcode_ivp_subwnx16_encode_fns, 0, 0 }, + { "ivp_subwanx16", ICLASS_IVP_SUBWANX16, + 0, + Opcode_ivp_subwanx16_encode_fns, 0, 0 }, + { "ivp_subwunx16", ICLASS_IVP_SUBWUNX16, + 0, + Opcode_ivp_subwunx16_encode_fns, 0, 0 }, + { "ivp_subwuanx16", ICLASS_IVP_SUBWUANX16, + 0, + Opcode_ivp_subwuanx16_encode_fns, 0, 0 }, + { "ivp_subw2nx8", ICLASS_IVP_SUBW2NX8, + 0, + Opcode_ivp_subw2nx8_encode_fns, 0, 0 }, + { "ivp_subwa2nx8", ICLASS_IVP_SUBWA2NX8, + 0, + Opcode_ivp_subwa2nx8_encode_fns, 0, 0 }, + { "ivp_subwu2nx8", ICLASS_IVP_SUBWU2NX8, + 0, + Opcode_ivp_subwu2nx8_encode_fns, 0, 0 }, + { "ivp_subwua2nx8", ICLASS_IVP_SUBWUA2NX8, + 0, + Opcode_ivp_subwua2nx8_encode_fns, 0, 0 }, + { "ivp_randb2n", ICLASS_IVP_RANDB2N, + 0, + Opcode_ivp_randb2n_encode_fns, 0, 0 }, + { "ivp_rorb2n", ICLASS_IVP_RORB2N, + 0, + Opcode_ivp_rorb2n_encode_fns, 0, 0 }, + { "ivp_randbn", ICLASS_IVP_RANDBN, + 0, + Opcode_ivp_randbn_encode_fns, 0, 0 }, + { "ivp_rorbn", ICLASS_IVP_RORBN, + 0, + Opcode_ivp_rorbn_encode_fns, 0, 0 }, + { "ivp_randbn_2", ICLASS_IVP_RANDBN_2, + 0, + Opcode_ivp_randbn_2_encode_fns, 0, 0 }, + { "ivp_rorbn_2", ICLASS_IVP_RORBN_2, + 0, + Opcode_ivp_rorbn_2_encode_fns, 0, 0 }, + { "ivp_avgnx16", ICLASS_IVP_AVGNX16, + 0, + Opcode_ivp_avgnx16_encode_fns, 0, 0 }, + { "ivp_avgunx16", ICLASS_IVP_AVGUNX16, + 0, + Opcode_ivp_avgunx16_encode_fns, 0, 0 }, + { "ivp_avg2nx8", ICLASS_IVP_AVG2NX8, + 0, + Opcode_ivp_avg2nx8_encode_fns, 0, 0 }, + { "ivp_avgr2nx8", ICLASS_IVP_AVGR2NX8, + 0, + Opcode_ivp_avgr2nx8_encode_fns, 0, 0 }, + { "ivp_avgrnx16", ICLASS_IVP_AVGRNX16, + 0, + Opcode_ivp_avgrnx16_encode_fns, 0, 0 }, + { "ivp_avgrunx16", ICLASS_IVP_AVGRUNX16, + 0, + Opcode_ivp_avgrunx16_encode_fns, 0, 0 }, + { "ivp_gatheranx8u", ICLASS_IVP_GATHERANX8U, + 0, + Opcode_ivp_gatheranx8u_encode_fns, 0, 0 }, + { "ivp_gatheranx16", ICLASS_IVP_GATHERANX16, + 0, + Opcode_ivp_gatheranx16_encode_fns, 0, 0 }, + { "ivp_gatheran_2x32", ICLASS_IVP_GATHERAN_2X32, + 0, + Opcode_ivp_gatheran_2x32_encode_fns, 0, 0 }, + { "ivp_gatheranx8ut", ICLASS_IVP_GATHERANX8UT, + 0, + Opcode_ivp_gatheranx8ut_encode_fns, 0, 0 }, + { "ivp_gatheranx16t", ICLASS_IVP_GATHERANX16T, + 0, + Opcode_ivp_gatheranx16t_encode_fns, 0, 0 }, + { "ivp_gatheran_2x32t", ICLASS_IVP_GATHERAN_2X32T, + 0, + Opcode_ivp_gatheran_2x32t_encode_fns, 0, 0 }, + { "ivp_gatherdnx16", ICLASS_IVP_GATHERDNX16, + 0, + Opcode_ivp_gatherdnx16_encode_fns, 0, 0 }, + { "ivp_gatherdnx8s", ICLASS_IVP_GATHERDNX8S, + 0, + Opcode_ivp_gatherdnx8s_encode_fns, 0, 0 }, + { "ivp_gatherd2nx8_l", ICLASS_IVP_GATHERD2NX8_L, + 0, + Opcode_ivp_gatherd2nx8_l_encode_fns, 0, 0 }, + { "ivp_gatherd2nx8_h", ICLASS_IVP_GATHERD2NX8_H, + 0, + Opcode_ivp_gatherd2nx8_h_encode_fns, 0, 0 }, + { "ivp_movgatherd", ICLASS_IVP_MOVGATHERD, + 0, + Opcode_ivp_movgatherd_encode_fns, 0, 0 }, + { "ivp_scatternx8u", ICLASS_IVP_SCATTERNX8U, + 0, + Opcode_ivp_scatternx8u_encode_fns, 0, 0 }, + { "ivp_scatter2nx8_l", ICLASS_IVP_SCATTER2NX8_L, + 0, + Opcode_ivp_scatter2nx8_l_encode_fns, 0, 0 }, + { "ivp_scatter2nx8_h", ICLASS_IVP_SCATTER2NX8_H, + 0, + Opcode_ivp_scatter2nx8_h_encode_fns, 0, 0 }, + { "ivp_scatternx16", ICLASS_IVP_SCATTERNX16, + 0, + Opcode_ivp_scatternx16_encode_fns, 0, 0 }, + { "ivp_scattern_2x32", ICLASS_IVP_SCATTERN_2X32, + 0, + Opcode_ivp_scattern_2x32_encode_fns, 0, 0 }, + { "ivp_scatternx8ut", ICLASS_IVP_SCATTERNX8UT, + 0, + Opcode_ivp_scatternx8ut_encode_fns, 0, 0 }, + { "ivp_scatter2nx8t_l", ICLASS_IVP_SCATTER2NX8T_L, + 0, + Opcode_ivp_scatter2nx8t_l_encode_fns, 0, 0 }, + { "ivp_scatter2nx8t_h", ICLASS_IVP_SCATTER2NX8T_H, + 0, + Opcode_ivp_scatter2nx8t_h_encode_fns, 0, 0 }, + { "ivp_scatternx16t", ICLASS_IVP_SCATTERNX16T, + 0, + Opcode_ivp_scatternx16t_encode_fns, 0, 0 }, + { "ivp_scattern_2x32t", ICLASS_IVP_SCATTERN_2X32T, + 0, + Opcode_ivp_scattern_2x32t_encode_fns, 0, 0 }, + { "ivp_scatterw", ICLASS_IVP_SCATTERW, + 0, + Opcode_ivp_scatterw_encode_fns, 0, 0 }, + { "ivp_counteqz4nx8", ICLASS_IVP_COUNTEQZ4NX8, + 0, + Opcode_ivp_counteqz4nx8_encode_fns, 0, 0 }, + { "ivp_counteq4nx8", ICLASS_IVP_COUNTEQ4NX8, + 0, + Opcode_ivp_counteq4nx8_encode_fns, 0, 0 }, + { "ivp_counteqmz4nx8", ICLASS_IVP_COUNTEQMZ4NX8, + 0, + Opcode_ivp_counteqmz4nx8_encode_fns, 0, 0 }, + { "ivp_counteqm4nx8", ICLASS_IVP_COUNTEQM4NX8, + 0, + Opcode_ivp_counteqm4nx8_encode_fns, 0, 0 }, + { "ivp_countlez4nx8", ICLASS_IVP_COUNTLEZ4NX8, + 0, + Opcode_ivp_countlez4nx8_encode_fns, 0, 0 }, + { "ivp_countle4nx8", ICLASS_IVP_COUNTLE4NX8, + 0, + Opcode_ivp_countle4nx8_encode_fns, 0, 0 }, + { "ivp_countlemz4nx8", ICLASS_IVP_COUNTLEMZ4NX8, + 0, + Opcode_ivp_countlemz4nx8_encode_fns, 0, 0 }, + { "ivp_countlem4nx8", ICLASS_IVP_COUNTLEM4NX8, + 0, + Opcode_ivp_countlem4nx8_encode_fns, 0, 0 }, + { "ivp_lsr2nx8_i", ICLASS_IVP_LSR2NX8_I, + 0, + Opcode_ivp_lsr2nx8_i_encode_fns, 0, 0 }, + { "ivp_lsr2nx8_ip", ICLASS_IVP_LSR2NX8_IP, + 0, + Opcode_ivp_lsr2nx8_ip_encode_fns, 0, 0 }, + { "ivp_lsr2nx8_x", ICLASS_IVP_LSR2NX8_X, + 0, + Opcode_ivp_lsr2nx8_x_encode_fns, 0, 0 }, + { "ivp_lsr2nx8_xp", ICLASS_IVP_LSR2NX8_XP, + 0, + Opcode_ivp_lsr2nx8_xp_encode_fns, 0, 0 }, + { "ivp_lsrnx16_i", ICLASS_IVP_LSRNX16_I, + 0, + Opcode_ivp_lsrnx16_i_encode_fns, 0, 0 }, + { "ivp_lsrnx16_ip", ICLASS_IVP_LSRNX16_IP, + 0, + Opcode_ivp_lsrnx16_ip_encode_fns, 0, 0 }, + { "ivp_lsrnx16_x", ICLASS_IVP_LSRNX16_X, + 0, + Opcode_ivp_lsrnx16_x_encode_fns, 0, 0 }, + { "ivp_lsrnx16_xp", ICLASS_IVP_LSRNX16_XP, + 0, + Opcode_ivp_lsrnx16_xp_encode_fns, 0, 0 }, + { "ivp_lsrn_2x32_i", ICLASS_IVP_LSRN_2X32_I, + 0, + Opcode_ivp_lsrn_2x32_i_encode_fns, 0, 0 }, + { "ivp_lsrn_2x32_ip", ICLASS_IVP_LSRN_2X32_IP, + 0, + Opcode_ivp_lsrn_2x32_ip_encode_fns, 0, 0 }, + { "ivp_lsrn_2x32_x", ICLASS_IVP_LSRN_2X32_X, + 0, + Opcode_ivp_lsrn_2x32_x_encode_fns, 0, 0 }, + { "ivp_lsrn_2x32_xp", ICLASS_IVP_LSRN_2X32_XP, + 0, + Opcode_ivp_lsrn_2x32_xp_encode_fns, 0, 0 }, + { "ivp_absnx16", ICLASS_IVP_ABSNX16, + 0, + Opcode_ivp_absnx16_encode_fns, 0, 0 }, + { "ivp_abssnx16", ICLASS_IVP_ABSSNX16, + 0, + Opcode_ivp_abssnx16_encode_fns, 0, 0 }, + { "ivp_abssubnx16", ICLASS_IVP_ABSSUBNX16, + 0, + Opcode_ivp_abssubnx16_encode_fns, 0, 0 }, + { "ivp_abssubunx16", ICLASS_IVP_ABSSUBUNX16, + 0, + Opcode_ivp_abssubunx16_encode_fns, 0, 0 }, + { "ivp_absssubnx16", ICLASS_IVP_ABSSSUBNX16, + 0, + Opcode_ivp_absssubnx16_encode_fns, 0, 0 }, + { "excw", ICLASS_xt_iclass_excw, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", ICLASS_xt_iclass_rfe, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", ICLASS_xt_iclass_rfde, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", ICLASS_xt_iclass_syscall, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "call12", ICLASS_xt_iclass_call12, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", ICLASS_xt_iclass_call8, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", ICLASS_xt_iclass_call4, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", ICLASS_xt_iclass_callx12, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", ICLASS_xt_iclass_callx8, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", ICLASS_xt_iclass_callx4, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", ICLASS_xt_iclass_entry, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", ICLASS_xt_iclass_movsp, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", ICLASS_xt_iclass_rotw, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", ICLASS_xt_iclass_l32e, + 0, + Opcode_l32e_encode_fns, 0, 0 }, + { "s32e", ICLASS_xt_iclass_s32e, + 0, + Opcode_s32e_encode_fns, 0, 0 }, + { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", ICLASS_xt_iclass_add_n, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", ICLASS_xt_iclass_addi_n, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", ICLASS_xt_iclass_ill_n, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", ICLASS_xt_iclass_loadi4, + 0, + Opcode_l32i_n_encode_fns, 0, 0 }, + { "mov.n", ICLASS_xt_iclass_mov_n, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", ICLASS_xt_iclass_movi_n, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", ICLASS_xt_iclass_nopn, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", ICLASS_xt_iclass_retn, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", ICLASS_xt_iclass_storei4, + 0, + Opcode_s32i_n_encode_fns, 0, 0 }, + { "rur.threadptr", ICLASS_rur_threadptr, + 0, + Opcode_rur_threadptr_encode_fns, 0, 0 }, + { "wur.threadptr", ICLASS_wur_threadptr, + 0, + Opcode_wur_threadptr_encode_fns, 0, 0 }, + { "addi", ICLASS_xt_iclass_addi, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", ICLASS_xt_iclass_addmi, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", ICLASS_xt_iclass_addsub, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "sub", ICLASS_xt_iclass_addsub, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "addx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "subx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", ICLASS_xt_iclass_bit, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", ICLASS_xt_iclass_bit, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", ICLASS_xt_iclass_bit, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bnei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bgei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bbci", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "beq", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bne", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bge", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "blt", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bgeu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "bltu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bany", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bnone", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "ball", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bnall", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bbc", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beqz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bnez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "bgez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "call0", ICLASS_xt_iclass_call0, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", ICLASS_xt_iclass_callx0, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "const16", ICLASS_xt_iclass_const16, + 0, + Opcode_const16_encode_fns, 0, 0 }, + { "extui", ICLASS_xt_iclass_exti, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", ICLASS_xt_iclass_ill, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", ICLASS_xt_iclass_jump, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", ICLASS_xt_iclass_jumpx, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", ICLASS_xt_iclass_l16ui, + 0, + Opcode_l16ui_encode_fns, 0, 0 }, + { "l16si", ICLASS_xt_iclass_l16si, + 0, + Opcode_l16si_encode_fns, 0, 0 }, + { "l32i", ICLASS_xt_iclass_l32i, + 0, + Opcode_l32i_encode_fns, 0, 0 }, + { "l32r", ICLASS_xt_iclass_l32r, + 0, + Opcode_l32r_encode_fns, 0, 0 }, + { "l8ui", ICLASS_xt_iclass_l8i, + 0, + Opcode_l8ui_encode_fns, 0, 0 }, + { "loop", ICLASS_xt_iclass_loop, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopnez", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "loopgtz", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "movi", ICLASS_xt_iclass_movi, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", ICLASS_xt_iclass_movz, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movnez", ICLASS_xt_iclass_movz, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "movltz", ICLASS_xt_iclass_movz, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movgez", ICLASS_xt_iclass_movz, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "neg", ICLASS_xt_iclass_neg, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "abs", ICLASS_xt_iclass_neg, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "nop", ICLASS_xt_iclass_nop, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "l32ex", ICLASS_xt_iclass_l32ex, + 0, + Opcode_l32ex_encode_fns, 0, 0 }, + { "s32ex", ICLASS_xt_iclass_s32ex, + 0, + Opcode_s32ex_encode_fns, 0, 0 }, + { "getex", ICLASS_xt_iclass_getex, + 0, + Opcode_getex_encode_fns, 0, 0 }, + { "clrex", ICLASS_xt_iclass_clrex, + 0, + Opcode_clrex_encode_fns, 0, 0 }, + { "ret", ICLASS_xt_iclass_return, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "simcall", ICLASS_xt_iclass_simcall, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "s16i", ICLASS_xt_iclass_s16i, + 0, + Opcode_s16i_encode_fns, 0, 0 }, + { "s32i", ICLASS_xt_iclass_s32i, + 0, + Opcode_s32i_encode_fns, 0, 0 }, + { "s32nb", ICLASS_xt_iclass_s32nb, + 0, + Opcode_s32nb_encode_fns, 0, 0 }, + { "s8i", ICLASS_xt_iclass_s8i, + 0, + Opcode_s8i_encode_fns, 0, 0 }, + { "ssr", ICLASS_xt_iclass_sar, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssl", ICLASS_xt_iclass_sar, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssa8l", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssa8b", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssai", ICLASS_xt_iclass_sari, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", ICLASS_xt_iclass_shifts, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", ICLASS_xt_iclass_shiftst, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "srl", ICLASS_xt_iclass_shiftt, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "sra", ICLASS_xt_iclass_shiftt, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "slli", ICLASS_xt_iclass_slli, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", ICLASS_xt_iclass_srai, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", ICLASS_xt_iclass_srli, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", ICLASS_xt_iclass_memw, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", ICLASS_xt_iclass_extw, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", ICLASS_xt_iclass_isync, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "rsync", ICLASS_xt_iclass_sync, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "esync", ICLASS_xt_iclass_sync, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "dsync", ICLASS_xt_iclass_sync, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "rsil", ICLASS_xt_iclass_rsil, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", ICLASS_xt_iclass_rsr_lend, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", ICLASS_xt_iclass_wsr_lend, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", ICLASS_xt_iclass_xsr_lend, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", ICLASS_xt_iclass_rsr_sar, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", ICLASS_xt_iclass_wsr_sar, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", ICLASS_xt_iclass_xsr_sar, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, + 0, + Opcode_rsr_memctl_encode_fns, 0, 0 }, + { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, + 0, + Opcode_wsr_memctl_encode_fns, 0, 0 }, + { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, + 0, + Opcode_xsr_memctl_encode_fns, 0, 0 }, + { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, + 0, + Opcode_rsr_litbase_encode_fns, 0, 0 }, + { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, + 0, + Opcode_wsr_litbase_encode_fns, 0, 0 }, + { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, + 0, + Opcode_xsr_litbase_encode_fns, 0, 0 }, + { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, + 0, + Opcode_rsr_configid0_encode_fns, 0, 0 }, + { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, + 0, + Opcode_wsr_configid0_encode_fns, 0, 0 }, + { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, + 0, + Opcode_rsr_configid1_encode_fns, 0, 0 }, + { "rsr.ps", ICLASS_xt_iclass_rsr_ps, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", ICLASS_xt_iclass_wsr_ps, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", ICLASS_xt_iclass_xsr_ps, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", ICLASS_xt_iclass_rsr_depc, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", ICLASS_xt_iclass_wsr_depc, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", ICLASS_xt_iclass_xsr_depc, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.prid", ICLASS_xt_iclass_rsr_prid, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "rsr.mpucfg", ICLASS_xt_iclass_rsr_mpucfg, + 0, + Opcode_rsr_mpucfg_encode_fns, 0, 0 }, + { "wsr.mpucfg", ICLASS_xt_iclass_wsr_mpucfg, + 0, + Opcode_wsr_mpucfg_encode_fns, 0, 0 }, + { "rsr.gserr", ICLASS_xt_iclass_rsr_gserr, + 0, + Opcode_rsr_gserr_encode_fns, 0, 0 }, + { "wsr.gserr", ICLASS_xt_iclass_wsr_gserr, + 0, + Opcode_wsr_gserr_encode_fns, 0, 0 }, + { "xsr.gserr", ICLASS_xt_iclass_xsr_gserr, + 0, + Opcode_xsr_gserr_encode_fns, 0, 0 }, + { "salt", ICLASS_xt_iclass_salt, + 0, + Opcode_salt_encode_fns, 0, 0 }, + { "saltu", ICLASS_xt_iclass_salt, + 0, + Opcode_saltu_encode_fns, 0, 0 }, + { "mul16u", ICLASS_xt_mul16, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mul16s", ICLASS_xt_mul16, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "mull", ICLASS_xt_mul32, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "muluh", ICLASS_xt_mul32h, + 0, + Opcode_muluh_encode_fns, 0, 0 }, + { "mulsh", ICLASS_xt_mul32h, + 0, + Opcode_mulsh_encode_fns, 0, 0 }, + { "rfi", ICLASS_xt_iclass_rfi, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", ICLASS_xt_iclass_wait, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", ICLASS_xt_iclass_wsr_intset, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", ICLASS_xt_iclass_break, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", ICLASS_xt_iclass_break_n, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", ICLASS_xt_iclass_rsr_icount, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", ICLASS_xt_iclass_wsr_icount, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", ICLASS_xt_iclass_xsr_icount, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "lddr32.p", ICLASS_xt_iclass_lddr32_p, + 0, + Opcode_lddr32_p_encode_fns, 0, 0 }, + { "sddr32.p", ICLASS_xt_iclass_sddr32_p, + 0, + Opcode_sddr32_p_encode_fns, 0, 0 }, + { "rfdo", ICLASS_xt_iclass_rfdo, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", ICLASS_xt_iclass_rfdd, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "andb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andb_encode_fns, 0, 0 }, + { "andbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andbc_encode_fns, 0, 0 }, + { "orb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orb_encode_fns, 0, 0 }, + { "orbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orbc_encode_fns, 0, 0 }, + { "xorb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_xorb_encode_fns, 0, 0 }, + { "any4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_any4_encode_fns, 0, 0 }, + { "all4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_all4_encode_fns, 0, 0 }, + { "any8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_any8_encode_fns, 0, 0 }, + { "all8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_all8_encode_fns, 0, 0 }, + { "bf", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bf_encode_fns, 0, 0 }, + { "bt", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bt_encode_fns, 0, 0 }, + { "movf", ICLASS_xt_iclass_bmove, + 0, + Opcode_movf_encode_fns, 0, 0 }, + { "movt", ICLASS_xt_iclass_bmove, + 0, + Opcode_movt_encode_fns, 0, 0 }, + { "rsr.br", ICLASS_xt_iclass_RSR_BR, + 0, + Opcode_rsr_br_encode_fns, 0, 0 }, + { "wsr.br", ICLASS_xt_iclass_WSR_BR, + 0, + Opcode_wsr_br_encode_fns, 0, 0 }, + { "xsr.br", ICLASS_xt_iclass_XSR_BR, + 0, + Opcode_xsr_br_encode_fns, 0, 0 }, + { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "ipf", ICLASS_xt_iclass_icache, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihi", ICLASS_xt_iclass_icache, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "ipfl", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ipfl_encode_fns, 0, 0 }, + { "ihu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ihu_encode_fns, 0, 0 }, + { "iiu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_iiu_encode_fns, 0, 0 }, + { "iii", ICLASS_xt_iclass_icache_inv, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", ICLASS_xt_iclass_licx, + 0, + Opcode_lict_encode_fns, 0, 0 }, + { "licw", ICLASS_xt_iclass_licx, + 0, + Opcode_licw_encode_fns, 0, 0 }, + { "sict", ICLASS_xt_iclass_sicx, + 0, + Opcode_sict_encode_fns, 0, 0 }, + { "sicw", ICLASS_xt_iclass_sicx, + 0, + Opcode_sicw_encode_fns, 0, 0 }, + { "wsr.cacheadrdis", ICLASS_xt_iclass_wsr_cacheadrdis, + 0, + Opcode_wsr_cacheadrdis_encode_fns, 0, 0 }, + { "rsr.cacheadrdis", ICLASS_xt_iclass_rsr_cacheadrdis, + 0, + Opcode_rsr_cacheadrdis_encode_fns, 0, 0 }, + { "xsr.cacheadrdis", ICLASS_xt_iclass_xsr_cacheadrdis, + 0, + Opcode_xsr_cacheadrdis_encode_fns, 0, 0 }, + { "rptlb0", ICLASS_xt_iclass_rptlb0, + 0, + Opcode_rptlb0_encode_fns, 0, 0 }, + { "pptlb", ICLASS_xt_iclass_rptlb, + 0, + Opcode_pptlb_encode_fns, 0, 0 }, + { "rptlb1", ICLASS_xt_iclass_rptlb, + 0, + Opcode_rptlb1_encode_fns, 0, 0 }, + { "wptlb", ICLASS_xt_iclass_wptlb, + 0, + Opcode_wptlb_encode_fns, 0, 0 }, + { "rsr.mpuenb", ICLASS_xt_iclass_rsr_mpuenb, + 0, + Opcode_rsr_mpuenb_encode_fns, 0, 0 }, + { "wsr.mpuenb", ICLASS_xt_iclass_wsr_mpuenb, + 0, + Opcode_wsr_mpuenb_encode_fns, 0, 0 }, + { "xsr.mpuenb", ICLASS_xt_iclass_xsr_mpuenb, + 0, + Opcode_xsr_mpuenb_encode_fns, 0, 0 }, + { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, + 0, + Opcode_rsr_cpenable_encode_fns, 0, 0 }, + { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, + 0, + Opcode_wsr_cpenable_encode_fns, 0, 0 }, + { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, + 0, + Opcode_xsr_cpenable_encode_fns, 0, 0 }, + { "clamps", ICLASS_xt_iclass_clamp, + 0, + Opcode_clamps_encode_fns, 0, 0 }, + { "min", ICLASS_xt_iclass_minmax, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "max", ICLASS_xt_iclass_minmax, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "minu", ICLASS_xt_iclass_minmax, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "maxu", ICLASS_xt_iclass_minmax, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "nsa", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", ICLASS_xt_iclass_sx, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", ICLASS_xt_iclass_l32ai, + 0, + Opcode_l32ai_encode_fns, 0, 0 }, + { "s32ri", ICLASS_xt_iclass_s32ri, + 0, + Opcode_s32ri_encode_fns, 0, 0 }, + { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, + 0, + Opcode_rsr_atomctl_encode_fns, 0, 0 }, + { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, + 0, + Opcode_wsr_atomctl_encode_fns, 0, 0 }, + { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, + 0, + Opcode_xsr_atomctl_encode_fns, 0, 0 }, + { "quou", ICLASS_xt_iclass_div, + 0, + Opcode_quou_encode_fns, 0, 0 }, + { "quos", ICLASS_xt_iclass_div, + 0, + Opcode_quos_encode_fns, 0, 0 }, + { "remu", ICLASS_xt_iclass_div, + 0, + Opcode_remu_encode_fns, 0, 0 }, + { "rems", ICLASS_xt_iclass_div, + 0, + Opcode_rems_encode_fns, 0, 0 }, + { "rsr.eraccess", ICLASS_xt_iclass_rsr_eraccess, + 0, + Opcode_rsr_eraccess_encode_fns, 0, 0 }, + { "wsr.eraccess", ICLASS_xt_iclass_wsr_eraccess, + 0, + Opcode_wsr_eraccess_encode_fns, 0, 0 }, + { "xsr.eraccess", ICLASS_xt_iclass_xsr_eraccess, + 0, + Opcode_xsr_eraccess_encode_fns, 0, 0 }, + { "rer", ICLASS_xt_iclass_rer, + 0, + Opcode_rer_encode_fns, 0, 0 }, + { "wer", ICLASS_xt_iclass_wer, + 0, + Opcode_wer_encode_fns, 0, 0 }, + { "beqz.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_w15_encode_fns, 0, 0 }, + { "bnez.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_w15_encode_fns, 0, 0 }, + { "bgez.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_w15_encode_fns, 0, 0 }, + { "bltz.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_w15_encode_fns, 0, 0 }, + { "beqi.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_w15_encode_fns, 0, 0 }, + { "bnei.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_w15_encode_fns, 0, 0 }, + { "bgei.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_w15_encode_fns, 0, 0 }, + { "blti.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_w15_encode_fns, 0, 0 }, + { "bgeui.w15", ICLASS_xt_iclass_wb15_2, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_w15_encode_fns, 0, 0 }, + { "bltui.w15", ICLASS_xt_iclass_wb15_2, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_w15_encode_fns, 0, 0 }, + { "bbci.w15", ICLASS_xt_iclass_wb15_3, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_w15_encode_fns, 0, 0 }, + { "bbsi.w15", ICLASS_xt_iclass_wb15_3, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_w15_encode_fns, 0, 0 }, + { "beq.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_w15_encode_fns, 0, 0 }, + { "bne.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_w15_encode_fns, 0, 0 }, + { "bge.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_w15_encode_fns, 0, 0 }, + { "blt.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_w15_encode_fns, 0, 0 }, + { "bgeu.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_w15_encode_fns, 0, 0 }, + { "bltu.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_w15_encode_fns, 0, 0 }, + { "bany.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_w15_encode_fns, 0, 0 }, + { "bnone.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_w15_encode_fns, 0, 0 }, + { "ball.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_w15_encode_fns, 0, 0 }, + { "bnall.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_w15_encode_fns, 0, 0 }, + { "bbc.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_w15_encode_fns, 0, 0 }, + { "bbs.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_w15_encode_fns, 0, 0 }, + { "mtk_andpopc", ICLASS_MTK_AndPOPC, + 0, + Opcode_mtk_andpopc_encode_fns, 0, 0 }, + { "iq_tie2apb_inq0_pop", ICLASS_iq_tie2apb_inq0_pop, + 0, + Opcode_iq_tie2apb_inq0_pop_encode_fns, 0, 0 }, + { "iq_tie2apb_inq0_is_ready", ICLASS_iq_tie2apb_inq0_is_ready, + 0, + Opcode_iq_tie2apb_inq0_is_ready_encode_fns, 0, 0 }, + { "iq_tie2apb_inq0_nonblocking_peek", ICLASS_iq_tie2apb_inq0_nonblocking_peek, + 0, + Opcode_iq_tie2apb_inq0_nonblocking_peek_encode_fns, 0, 0 }, + { "iq_tie2apb_inq0_nonblocking_pop", ICLASS_iq_tie2apb_inq0_nonblocking_pop, + 0, + Opcode_iq_tie2apb_inq0_nonblocking_pop_encode_fns, 0, 0 }, + { "iq_tie2apb_inq0_blocking_peek", ICLASS_iq_tie2apb_inq0_blocking_peek, + 0, + Opcode_iq_tie2apb_inq0_blocking_peek_encode_fns, 0, 0 }, + { "oq_tie2apb_outq0_push_read", ICLASS_oq_tie2apb_outq0_push_read, + 0, + Opcode_oq_tie2apb_outq0_push_read_encode_fns, 0, 0 }, + { "oq_tie2apb_outq0_push_write", ICLASS_oq_tie2apb_outq0_push_write, + 0, + Opcode_oq_tie2apb_outq0_push_write_encode_fns, 0, 0 }, + { "oq_tie2apb_outq0_is_ready", ICLASS_oq_tie2apb_outq0_is_ready, + 0, + Opcode_oq_tie2apb_outq0_is_ready_encode_fns, 0, 0 }, + { "oq_tie2apb_outq0_nonblocking_push_read", ICLASS_oq_tie2apb_outq0_nonblocking_push_read, + 0, + Opcode_oq_tie2apb_outq0_nonblocking_push_read_encode_fns, 0, 0 }, + { "oq_tie2apb_outq0_nonblocking_push_write", ICLASS_oq_tie2apb_outq0_nonblocking_push_write, + 0, + Opcode_oq_tie2apb_outq0_nonblocking_push_write_encode_fns, 0, 0 }, + { "rur.apb_pipe", ICLASS_rur_apb_pipe, + 0, + Opcode_rur_apb_pipe_encode_fns, 0, 0 }, + { "wur.apb_pipe", ICLASS_wur_apb_pipe, + 0, + Opcode_wur_apb_pipe_encode_fns, 0, 0 } +}; + +enum xtensa_opcode_id { + OPCODE_IVP_REPNX16, + OPCODE_IVP_SELSNX16, + OPCODE_IVP_REP2NX8, + OPCODE_IVP_SELS2NX8, + OPCODE_IVP_REPN_2X32, + OPCODE_IVP_SELSN_2X32, + OPCODE_IVP_EXT0IB, + OPCODE_IVP_NOTB, + OPCODE_IVP_ANDB, + OPCODE_IVP_ORB, + OPCODE_IVP_XORB, + OPCODE_IVP_ANDNOTB, + OPCODE_IVP_MB, + OPCODE_IVP_LTRN, + OPCODE_IVP_LTRNI, + OPCODE_IVP_LBN_I, + OPCODE_IVP_LBN_IP, + OPCODE_IVP_SBN_I, + OPCODE_IVP_SBN_IP, + OPCODE_IVP_LSNX16_I, + OPCODE_IVP_LSNX16_IP, + OPCODE_IVP_LSNX16_X, + OPCODE_IVP_LSNX16_XP, + OPCODE_IVP_MOVBRBV, + OPCODE_IVP_MOVBVBR, + OPCODE_IVP_JOINB, + OPCODE_IVP_LTRN_2, + OPCODE_IVP_LTRN_2I, + OPCODE_IVP_LBN_2_I, + OPCODE_IVP_LBN_2_IP, + OPCODE_IVP_SBN_2_I, + OPCODE_IVP_SBN_2_IP, + OPCODE_IVP_LV2NX8_I, + OPCODE_IVP_LV2NX8_IP, + OPCODE_IVP_LV2NX8_X, + OPCODE_IVP_LV2NX8_XP, + OPCODE_IVP_SV2NX8_I, + OPCODE_IVP_SV2NX8_IP, + OPCODE_IVP_SV2NX8_X, + OPCODE_IVP_SV2NX8_XP, + OPCODE_IVP_SSNX16_I, + OPCODE_IVP_SSNX16_IP, + OPCODE_IVP_SSNX16_X, + OPCODE_IVP_SSNX16_XP, + OPCODE_IVP_MOVVA16, + OPCODE_IVP_MOVVV, + OPCODE_IVP_SLLINX16, + OPCODE_IVP_SLSINX16, + OPCODE_IVP_SRAINX16, + OPCODE_IVP_SRLINX16, + OPCODE_IVP_SLLNX16, + OPCODE_IVP_SRLNX16, + OPCODE_IVP_SLANX16, + OPCODE_IVP_SRANX16, + OPCODE_IVP_SLSNX16, + OPCODE_IVP_SRSNX16, + OPCODE_IVP_XOR2NX8, + OPCODE_IVP_AND2NX8, + OPCODE_IVP_OR2NX8, + OPCODE_IVP_NOT2NX8, + OPCODE_IVP_ADDNX16, + OPCODE_IVP_SUBNX16, + OPCODE_IVP_NEGNX16, + OPCODE_IVP_MINNX16, + OPCODE_IVP_MINUNX16, + OPCODE_IVP_MAXNX16, + OPCODE_IVP_MAXUNX16, + OPCODE_IVP_MULSGNNX16, + OPCODE_IVP_NSANX16, + OPCODE_IVP_NSAUNX16, + OPCODE_IVP_LTNX16, + OPCODE_IVP_LENX16, + OPCODE_IVP_EQNX16, + OPCODE_IVP_NEQNX16, + OPCODE_IVP_LTUNX16, + OPCODE_IVP_LEUNX16, + OPCODE_IVP_RADDNX16, + OPCODE_IVP_RMAXNX16, + OPCODE_IVP_RMINNX16, + OPCODE_IVP_RMAXUNX16, + OPCODE_IVP_RMINUNX16, + OPCODE_IVP_RBMINNX16, + OPCODE_IVP_RBMAXNX16, + OPCODE_IVP_BMAXNX16, + OPCODE_IVP_BMINNX16, + OPCODE_IVP_MOV2NX8T, + OPCODE_IVP_MULANX16PACKL, + OPCODE_IVP_MULANX16PACKQ, + OPCODE_IVP_MULSNX16PACKL, + OPCODE_IVP_MULSNX16PACKQ, + OPCODE_IVP_ADDSNX16, + OPCODE_IVP_SUBSNX16, + OPCODE_IVP_NEGSNX16, + OPCODE_IVP_LV2NX8T_I, + OPCODE_IVP_LV2NX8T_IP, + OPCODE_IVP_LV2NX8T_X, + OPCODE_IVP_LV2NX8T_XP, + OPCODE_IVP_SV2NX8T_I, + OPCODE_IVP_SV2NX8T_IP, + OPCODE_IVP_SV2NX8T_X, + OPCODE_IVP_SV2NX8T_XP, + OPCODE_IVP_RADDNX16T, + OPCODE_IVP_RMAXNX16T, + OPCODE_IVP_RMINNX16T, + OPCODE_IVP_RMAXUNX16T, + OPCODE_IVP_RMINUNX16T, + OPCODE_IVP_ADDNX16T, + OPCODE_IVP_SUBNX16T, + OPCODE_IVP_NEGNX16T, + OPCODE_IVP_MAXNX16T, + OPCODE_IVP_MINNX16T, + OPCODE_IVP_MAXUNX16T, + OPCODE_IVP_MINUNX16T, + OPCODE_IVP_MULANX16PACKLT, + OPCODE_IVP_MULANX16PACKQT, + OPCODE_IVP_ADDSNX16T, + OPCODE_IVP_SUBSNX16T, + OPCODE_IVP_NEGSNX16T, + OPCODE_IVP_LALIGN_I, + OPCODE_IVP_LALIGN_IP, + OPCODE_IVP_SALIGN_I, + OPCODE_IVP_SALIGN_IP, + OPCODE_IVP_LA_PP, + OPCODE_IVP_SAPOS_FP, + OPCODE_IVP_MALIGN, + OPCODE_IVP_ZALIGN, + OPCODE_IVP_LA2NX8_IP, + OPCODE_IVP_SA2NX8_IP, + OPCODE_IVP_LAV2NX8_XP, + OPCODE_IVP_SAV2NX8_XP, + OPCODE_IVP_SELNX16, + OPCODE_IVP_SHFLNX16, + OPCODE_IVP_MOVPINT16, + OPCODE_IVP_MOVPA16, + OPCODE_IVP_MULNX16PACKP, + OPCODE_IVP_MULANX16PACKP, + OPCODE_IVP_MULSNX16PACKP, + OPCODE_IVP_MULANX16PACKPT, + OPCODE_IVP_ADDMOD16U, + OPCODE_IVP_LVNX8S_I, + OPCODE_IVP_LVNX8S_IP, + OPCODE_IVP_LVNX8S_X, + OPCODE_IVP_LVNX8S_XP, + OPCODE_IVP_LVNX8U_I, + OPCODE_IVP_LVNX8U_IP, + OPCODE_IVP_LVNX8U_X, + OPCODE_IVP_LVNX8U_XP, + OPCODE_IVP_SVNX8U_I, + OPCODE_IVP_SVNX8U_IP, + OPCODE_IVP_SVNX8U_X, + OPCODE_IVP_SVNX8U_XP, + OPCODE_IVP_LVNX8ST_I, + OPCODE_IVP_LVNX8ST_IP, + OPCODE_IVP_LVNX8ST_X, + OPCODE_IVP_LVNX8ST_XP, + OPCODE_IVP_LVNX8UT_I, + OPCODE_IVP_LVNX8UT_IP, + OPCODE_IVP_LVNX8UT_X, + OPCODE_IVP_LVNX8UT_XP, + OPCODE_IVP_SVNX8UT_I, + OPCODE_IVP_SVNX8UT_IP, + OPCODE_IVP_SVNX8UT_X, + OPCODE_IVP_SVNX8UT_XP, + OPCODE_IVP_LAVNX8S_XP, + OPCODE_IVP_LAVNX8U_XP, + OPCODE_IVP_SAVNX8U_XP, + OPCODE_IVP_LANX8S_IP, + OPCODE_IVP_LANX8U_IP, + OPCODE_IVP_SANX8U_IP, + OPCODE_IVP_EXTRACTBL, + OPCODE_IVP_EXTRACTBH, + OPCODE_IVP_MOVVINT16, + OPCODE_IVP_MOVQINT16, + OPCODE_IVP_MOVQA16, + OPCODE_IVP_MOVVINX16, + OPCODE_IVP_SEQNX16, + OPCODE_IVP_MULNX16PACKL, + OPCODE_IVP_MULNX16PACKQ, + OPCODE_IVP_MOVAV16, + OPCODE_IVP_MOVAVU16, + OPCODE_IVP_EXTRNX16, + OPCODE_IVP_LSNX8S_I, + OPCODE_IVP_LSNX8S_IP, + OPCODE_IVP_LSNX8S_X, + OPCODE_IVP_LSNX8S_XP, + OPCODE_IVP_SVNX8S_I, + OPCODE_IVP_SVNX8S_IP, + OPCODE_IVP_SVNX8S_X, + OPCODE_IVP_SVNX8S_XP, + OPCODE_IVP_SSNX8S_I, + OPCODE_IVP_SSNX8S_IP, + OPCODE_IVP_SSNX8S_X, + OPCODE_IVP_SSNX8S_XP, + OPCODE_IVP_SAVNX8S_XP, + OPCODE_IVP_SANX8S_IP, + OPCODE_IVP_SVNX8ST_I, + OPCODE_IVP_SVNX8ST_IP, + OPCODE_IVP_SVNX8ST_X, + OPCODE_IVP_SVNX8ST_XP, + OPCODE_IVP_MOVBA1, + OPCODE_IVP_MOVAB1, + OPCODE_IVP_NOTB1, + OPCODE_IVP_ANDNOTB1, + OPCODE_IVP_ORNOTB1, + OPCODE_IVP_CVT32S2NX24LL, + OPCODE_IVP_CVT32S2NX24LH, + OPCODE_IVP_CVT32S2NX24HL, + OPCODE_IVP_CVT32S2NX24HH, + OPCODE_IVP_CVT64SNX48LL, + OPCODE_IVP_CVT64SNX48LH, + OPCODE_IVP_CVT64SNX48HL, + OPCODE_IVP_CVT64SNX48HH, + OPCODE_IVP_CVT16S2NX24L, + OPCODE_IVP_CVT16S2NX24H, + OPCODE_IVP_CVT32SNX48L, + OPCODE_IVP_CVT32SNX48H, + OPCODE_IVP_CVT16U2NX24H, + OPCODE_IVP_CVT32UNX48H, + OPCODE_IVP_CVT64UN_2X96H, + OPCODE_IVP_CVT16U2NX24L, + OPCODE_IVP_CVT24U2NX16, + OPCODE_IVP_CVT24S2NX16, + OPCODE_IVP_CVT32S24, + OPCODE_IVP_CVT24U32, + OPCODE_IVP_CVT24UNX32L, + OPCODE_IVP_CVT24UNX32H, + OPCODE_IVP_CVT32UNX48L, + OPCODE_IVP_CVT48UNX32L, + OPCODE_IVP_CVT48UNX32, + OPCODE_IVP_CVT48SNX32L, + OPCODE_IVP_CVT48SNX32, + OPCODE_IVP_CVT64S48, + OPCODE_IVP_CVT48U64, + OPCODE_IVP_CVT48UN_2X64L, + OPCODE_IVP_CVT48UN_2X64H, + OPCODE_IVP_CVT64UN_2X96L, + OPCODE_IVP_CVT96UN_2X64, + OPCODE_IVP_CVT96U64, + OPCODE_IVP_CVT64U96, + OPCODE_IVP_LB2N_I, + OPCODE_IVP_LB2N_IP, + OPCODE_IVP_SB2N_I, + OPCODE_IVP_SB2N_IP, + OPCODE_IVP_LTR2N, + OPCODE_IVP_LTR2NI, + OPCODE_IVP_LVN_2X16U_I, + OPCODE_IVP_LVN_2X16U_IP, + OPCODE_IVP_LVN_2X16U_X, + OPCODE_IVP_LVN_2X16U_XP, + OPCODE_IVP_LVN_2X16UT_I, + OPCODE_IVP_LVN_2X16UT_IP, + OPCODE_IVP_LVN_2X16UT_X, + OPCODE_IVP_LVN_2X16UT_XP, + OPCODE_IVP_LVN_2X16S_I, + OPCODE_IVP_LVN_2X16S_IP, + OPCODE_IVP_LVN_2X16S_X, + OPCODE_IVP_LVN_2X16S_XP, + OPCODE_IVP_LVN_2X16ST_I, + OPCODE_IVP_LVN_2X16ST_IP, + OPCODE_IVP_LVN_2X16ST_X, + OPCODE_IVP_LVN_2X16ST_XP, + OPCODE_IVP_SVN_2X16U_I, + OPCODE_IVP_SVN_2X16UT_I, + OPCODE_IVP_SVN_2X16U_IP, + OPCODE_IVP_SVN_2X16UT_IP, + OPCODE_IVP_SVN_2X16U_X, + OPCODE_IVP_SVN_2X16UT_X, + OPCODE_IVP_SVN_2X16U_XP, + OPCODE_IVP_SVN_2X16UT_XP, + OPCODE_IVP_SVN_2X16S_I, + OPCODE_IVP_SVN_2X16ST_I, + OPCODE_IVP_SVN_2X16S_IP, + OPCODE_IVP_SVN_2X16ST_IP, + OPCODE_IVP_SVN_2X16S_X, + OPCODE_IVP_SVN_2X16ST_X, + OPCODE_IVP_SVN_2X16S_XP, + OPCODE_IVP_SVN_2X16ST_XP, + OPCODE_IVP_LAN_2X16S_IP, + OPCODE_IVP_LAN_2X16U_IP, + OPCODE_IVP_LAN_2X16U_XP, + OPCODE_IVP_LAN_2X16S_XP, + OPCODE_IVP_SAN_2X16U_IP, + OPCODE_IVP_SAN_2X16S_IP, + OPCODE_IVP_LAVN_2X16S_XP, + OPCODE_IVP_LAVN_2X16U_XP, + OPCODE_IVP_SAVN_2X16U_XP, + OPCODE_IVP_SAVN_2X16S_XP, + OPCODE_IVP_LSN_2X16S_I, + OPCODE_IVP_LSN_2X16S_IP, + OPCODE_IVP_LSN_2X16S_X, + OPCODE_IVP_LSN_2X16S_XP, + OPCODE_IVP_SSN_2X16S_I, + OPCODE_IVP_SSN_2X16S_IP, + OPCODE_IVP_SSN_2X16S_X, + OPCODE_IVP_SSN_2X16S_XP, + OPCODE_IVP_LSN_2X32_I, + OPCODE_IVP_LSN_2X32_IP, + OPCODE_IVP_LSN_2X32_X, + OPCODE_IVP_LSN_2X32_XP, + OPCODE_IVP_SSN_2X32_I, + OPCODE_IVP_SSN_2X32_IP, + OPCODE_IVP_SSN_2X32_X, + OPCODE_IVP_SSN_2X32_XP, + OPCODE_IVP_BMAXUNX16, + OPCODE_IVP_BMINUNX16, + OPCODE_IVP_RBMINUNX16, + OPCODE_IVP_RBMAXUNX16, + OPCODE_IVP_BMAX2NX8, + OPCODE_IVP_BMIN2NX8, + OPCODE_IVP_BMAXU2NX8, + OPCODE_IVP_BMINU2NX8, + OPCODE_IVP_BMAXN_2X32, + OPCODE_IVP_BMINN_2X32, + OPCODE_IVP_BMAXUN_2X32, + OPCODE_IVP_BMINUN_2X32, + OPCODE_IVP_ADDN_2X32T, + OPCODE_IVP_SUBN_2X32T, + OPCODE_IVP_ADD2NX8, + OPCODE_IVP_SUB2NX8, + OPCODE_IVP_NEG2NX8, + OPCODE_IVP_MIN2NX8, + OPCODE_IVP_MINU2NX8, + OPCODE_IVP_MAX2NX8, + OPCODE_IVP_MAXU2NX8, + OPCODE_IVP_LT2NX8, + OPCODE_IVP_LE2NX8, + OPCODE_IVP_EQ2NX8, + OPCODE_IVP_NEQ2NX8, + OPCODE_IVP_LTU2NX8, + OPCODE_IVP_LEU2NX8, + OPCODE_IVP_ADD2NX8T, + OPCODE_IVP_SUB2NX8T, + OPCODE_IVP_SELNX16T, + OPCODE_IVP_SELN_2X32, + OPCODE_IVP_SELN_2X32T, + OPCODE_IVP_SHFLN_2X32, + OPCODE_IVP_SLLIN_2X32, + OPCODE_IVP_SLSIN_2X32, + OPCODE_IVP_SRAIN_2X32, + OPCODE_IVP_SRLIN_2X32, + OPCODE_IVP_SLLN_2X32, + OPCODE_IVP_SRLN_2X32, + OPCODE_IVP_SLAN_2X32, + OPCODE_IVP_SRAN_2X32, + OPCODE_IVP_SLSN_2X32, + OPCODE_IVP_SRSN_2X32, + OPCODE_IVP_RADDN_2X32, + OPCODE_IVP_RMAXN_2X32, + OPCODE_IVP_RMINN_2X32, + OPCODE_IVP_RMAXUN_2X32, + OPCODE_IVP_RMINUN_2X32, + OPCODE_IVP_RADDN_2X32T, + OPCODE_IVP_ABS2NX8, + OPCODE_IVP_ABSN_2X32, + OPCODE_IVP_MULSGNSNX16, + OPCODE_IVP_ROTRI2NX8, + OPCODE_IVP_ROTRINX16, + OPCODE_IVP_ROTRIN_2X32, + OPCODE_IVP_ROTRNX16, + OPCODE_IVP_ROTRN_2X32, + OPCODE_IVP_ADDN_2X32, + OPCODE_IVP_SUBN_2X32, + OPCODE_IVP_NEGN_2X32, + OPCODE_IVP_MINN_2X32, + OPCODE_IVP_MINUN_2X32, + OPCODE_IVP_MAXN_2X32, + OPCODE_IVP_MAXUN_2X32, + OPCODE_IVP_MULSGNN_2X32, + OPCODE_IVP_NSAN_2X32, + OPCODE_IVP_NSAUN_2X32, + OPCODE_IVP_LTN_2X32, + OPCODE_IVP_LEN_2X32, + OPCODE_IVP_EQN_2X32, + OPCODE_IVP_NEQN_2X32, + OPCODE_IVP_LTUN_2X32, + OPCODE_IVP_LEUN_2X32, + OPCODE_IVP_LAT2NX8_XP, + OPCODE_IVP_MULUU2NX8, + OPCODE_IVP_MULUUA2NX8, + OPCODE_IVP_MULUS2NX8, + OPCODE_IVP_MULUSA2NX8, + OPCODE_IVP_MULI2NX8X16, + OPCODE_IVP_MULAI2NX8X16, + OPCODE_IVP_MULUSI2NX8X16, + OPCODE_IVP_MULUSAI2NX8X16, + OPCODE_IVP_MULI2NR8X16, + OPCODE_IVP_MULAI2NR8X16, + OPCODE_IVP_MULUSI2NR8X16, + OPCODE_IVP_MULUSAI2NR8X16, + OPCODE_IVP_MULUSA2N8XR16, + OPCODE_IVP_MULUS2N8XR16, + OPCODE_IVP_MULA2N8XR16, + OPCODE_IVP_MUL2N8XR16, + OPCODE_IVP_DSEL2NX8I, + OPCODE_IVP_DSEL2NX8I_H, + OPCODE_IVP_DSELNX16, + OPCODE_IVP_DSELNX16T, + OPCODE_IVP_INJBI2NX8, + OPCODE_IVP_EXTBI2NX8, + OPCODE_IVP_MOVVA32, + OPCODE_IVP_MOVAV32, + OPCODE_IVP_MOVWW, + OPCODE_IVP_LS2NX8_I, + OPCODE_IVP_LS2NX8_IP, + OPCODE_IVP_LS2NX8_X, + OPCODE_IVP_LS2NX8_XP, + OPCODE_IVP_SS2NX8_I, + OPCODE_IVP_SS2NX8_IP, + OPCODE_IVP_SS2NX8_X, + OPCODE_IVP_SS2NX8_XP, + OPCODE_IVP_LANX8S_XP, + OPCODE_IVP_LANX8U_XP, + OPCODE_IVP_LA2NX8_XP, + OPCODE_IVP_ABSSUBU2NX8, + OPCODE_IVP_ABSSUB2NX8, + OPCODE_IVP_MOVVINT8, + OPCODE_IVP_MOVVA8, + OPCODE_IVP_MOVAVU8, + OPCODE_IVP_SLLI2NX8, + OPCODE_IVP_SRAI2NX8, + OPCODE_IVP_SRLI2NX8, + OPCODE_IVP_PACKL2NX24, + OPCODE_IVP_PACKVR2NX24, + OPCODE_IVP_PACKVRU2NX24, + OPCODE_IVP_PACKLNX48, + OPCODE_IVP_PACKL2NX24_1, + OPCODE_IVP_PACKVR2NX24_0, + OPCODE_IVP_PACKVR2NX24_1, + OPCODE_IVP_PACKVRU2NX24_0, + OPCODE_IVP_PACKVRU2NX24_1, + OPCODE_IVP_PACKVRNR2NX24_0, + OPCODE_IVP_PACKVRNR2NX24_1, + OPCODE_IVP_PACKMNX48, + OPCODE_IVP_PACKVRNX48, + OPCODE_IVP_UNPKS2NX8_0, + OPCODE_IVP_UNPKS2NX8_1, + OPCODE_IVP_UNPKSNX16_L, + OPCODE_IVP_UNPKSNX16_H, + OPCODE_IVP_SEL2NX8I, + OPCODE_IVP_SEL2NX8I_S0, + OPCODE_IVP_SEL2NX8I_S2, + OPCODE_IVP_SEL2NX8I_S4, + OPCODE_IVP_SHFL2NX8I, + OPCODE_IVP_SHFL2NX8I_S0, + OPCODE_IVP_SHFL2NX8I_S2, + OPCODE_IVP_SHFL2NX8I_S4, + OPCODE_IVP_SEL2NX8, + OPCODE_IVP_SHFL2NX8, + OPCODE_IVP_SEL2NX8T, + OPCODE_IVP_SQZN, + OPCODE_IVP_UNSQZN, + OPCODE_IVP_MULNX16, + OPCODE_IVP_MULANX16, + OPCODE_IVP_MULUUNX16, + OPCODE_IVP_MULUUANX16, + OPCODE_IVP_MULUSNX16, + OPCODE_IVP_MULUSANX16, + OPCODE_IVP_MUL2NX8, + OPCODE_IVP_MULA2NX8, + OPCODE_IVP_ADDW2NX8, + OPCODE_IVP_ADDWA2NX8, + OPCODE_IVP_ADDWS2NX8, + OPCODE_IVP_ADDWU2NX8, + OPCODE_IVP_ADDWUA2NX8, + OPCODE_IVP_ADDWUS2NX8, + OPCODE_IVP_DIVN_2X32X16S_4STEP0, + OPCODE_IVP_DIVN_2X32X16S_4STEP, + OPCODE_IVP_DIVN_2X32X16S_4STEPN, + OPCODE_IVP_DIVN_2X32X16U_4STEP0, + OPCODE_IVP_DIVN_2X32X16U_4STEP, + OPCODE_IVP_DIVN_2X32X16U_4STEPN, + OPCODE_IVP_DIVNX16S_4STEP0, + OPCODE_IVP_DIVNX16S_4STEP, + OPCODE_IVP_DIVNX16S_4STEPN, + OPCODE_IVP_DIVNX16U_4STEP0, + OPCODE_IVP_DIVNX16U_4STEP, + OPCODE_IVP_DIVNX16U_4STEPN, + OPCODE_IVP_DIVNX16SQ_4STEP0, + OPCODE_IVP_DIVNX16Q_4STEP0, + OPCODE_IVP_MULSNX16, + OPCODE_IVP_MULUUSNX16, + OPCODE_IVP_MULUSSNX16, + OPCODE_IVP_MULN_2X16X32_0, + OPCODE_IVP_MULUUN_2X16X32_0, + OPCODE_IVP_MULUSN_2X16X32_0, + OPCODE_IVP_MULSUN_2X16X32_0, + OPCODE_IVP_MULN_2X16X32_1, + OPCODE_IVP_MULUUN_2X16X32_1, + OPCODE_IVP_MULUSN_2X16X32_1, + OPCODE_IVP_MULSUN_2X16X32_1, + OPCODE_IVP_MULHN_2X16X32_1, + OPCODE_IVP_MULUUHN_2X16X32_1, + OPCODE_IVP_MULUSHN_2X16X32_1, + OPCODE_IVP_MULSUHN_2X16X32_1, + OPCODE_IVP_MULAN_2X16X32_0, + OPCODE_IVP_MULUUAN_2X16X32_0, + OPCODE_IVP_MULUSAN_2X16X32_0, + OPCODE_IVP_MULSUAN_2X16X32_0, + OPCODE_IVP_MULAHN_2X16X32_1, + OPCODE_IVP_MULUUAHN_2X16X32_1, + OPCODE_IVP_MULUSAHN_2X16X32_1, + OPCODE_IVP_MULSUAHN_2X16X32_1, + OPCODE_IVP_MULAN_2X16X32_1, + OPCODE_IVP_MULUUAN_2X16X32_1, + OPCODE_IVP_MULUSAN_2X16X32_1, + OPCODE_IVP_MULSUAN_2X16X32_1, + OPCODE_IVP_MULSHN_2X16X32_1, + OPCODE_IVP_MULUUSHN_2X16X32_1, + OPCODE_IVP_MULUSSHN_2X16X32_1, + OPCODE_IVP_MULSUSHN_2X16X32_1, + OPCODE_IVP_MULSN_2X16X32_0, + OPCODE_IVP_MULUUSN_2X16X32_0, + OPCODE_IVP_MULUSSN_2X16X32_0, + OPCODE_IVP_MULSUSN_2X16X32_0, + OPCODE_IVP_MULSN_2X16X32_1, + OPCODE_IVP_MULUUSN_2X16X32_1, + OPCODE_IVP_MULUSSN_2X16X32_1, + OPCODE_IVP_MULSUSN_2X16X32_1, + OPCODE_IVP_PACKLN_2X96, + OPCODE_IVP_PACKHN_2X64W, + OPCODE_IVP_PACKVRN_2X64W, + OPCODE_IVP_PACKVRNRN_2X64W, + OPCODE_IVP_PACKVRNX48_0, + OPCODE_IVP_PACKVRNX48_1, + OPCODE_IVP_PACKVRNRNX48_0, + OPCODE_IVP_PACKVRNRNX48_1, + OPCODE_IVP_PACKVRNRNX48, + OPCODE_IVP_PACKVRNR2NX24, + OPCODE_IVP_L2A4NX8_IP, + OPCODE_IVP_L2AU2NX8_IP, + OPCODE_IVP_L2U2NX8_XP, + OPCODE_IVP_AVGU2NX8, + OPCODE_IVP_AVGRU2NX8, + OPCODE_IVP_RADD2NX8, + OPCODE_IVP_RADD2NX8T, + OPCODE_IVP_RADDUNX16, + OPCODE_IVP_RADDUNX16T, + OPCODE_IVP_RADDU2NX8, + OPCODE_IVP_RADDU2NX8T, + OPCODE_IVP_LTRS2N, + OPCODE_IVP_LTRSN, + OPCODE_IVP_LTRSN_2, + OPCODE_IVP_SEQ2NX8, + OPCODE_IVP_SEQN_2X32, + OPCODE_IVP_EXTRN_2X32, + OPCODE_IVP_UNPKU2NX8_0, + OPCODE_IVP_UNPKU2NX8_1, + OPCODE_IVP_BADDNORMNX16, + OPCODE_IVP_BSUBNORMNX16, + OPCODE_IVP_RADDSNX16, + OPCODE_IVP_RADDSNX16T, + OPCODE_IVP_ORNOTB, + OPCODE_IVP_EXTR2NX8, + OPCODE_IVP_EXTRVRN_2X32, + OPCODE_IVP_MOVAV8, + OPCODE_IVP_MULPN16XR16, + OPCODE_IVP_MULPAN16XR16, + OPCODE_IVP_MULUSPN16XR16, + OPCODE_IVP_MULUSPAN16XR16, + OPCODE_IVP_MULP2N8XR16, + OPCODE_IVP_MULPA2N8XR16, + OPCODE_IVP_MULUSP2N8XR16, + OPCODE_IVP_MULUSPA2N8XR16, + OPCODE_IVP_MULPNX16, + OPCODE_IVP_MULPANX16, + OPCODE_IVP_MULUSPNX16, + OPCODE_IVP_MULUSPANX16, + OPCODE_IVP_MULUUPNX16, + OPCODE_IVP_MULUUPANX16, + OPCODE_IVP_MULP2NX8, + OPCODE_IVP_MULPA2NX8, + OPCODE_IVP_MULUSP2NX8, + OPCODE_IVP_MULUSPA2NX8, + OPCODE_IVP_MULUUP2NX8, + OPCODE_IVP_MULUUPA2NX8, + OPCODE_IVP_MULPI2NR8X16, + OPCODE_IVP_MULPAI2NR8X16, + OPCODE_IVP_MULUSPI2NR8X16, + OPCODE_IVP_MULUSPAI2NR8X16, + OPCODE_IVP_MULQ2N8XR8, + OPCODE_IVP_MULQA2N8XR8, + OPCODE_IVP_MULUSQ2N8XR8, + OPCODE_IVP_MULUSQA2N8XR8, + OPCODE_IVP_MUL4T2N8XR8, + OPCODE_IVP_MUL4TA2N8XR8, + OPCODE_IVP_MULUS4T2N8XR8, + OPCODE_IVP_MULUS4TA2N8XR8, + OPCODE_IVP_ADDWNX16, + OPCODE_IVP_ADDWANX16, + OPCODE_IVP_ADDWSNX16, + OPCODE_IVP_ADDWUNX16, + OPCODE_IVP_ADDWUANX16, + OPCODE_IVP_ADDWUSNX16, + OPCODE_IVP_SUBWNX16, + OPCODE_IVP_SUBWANX16, + OPCODE_IVP_SUBWUNX16, + OPCODE_IVP_SUBWUANX16, + OPCODE_IVP_SUBW2NX8, + OPCODE_IVP_SUBWA2NX8, + OPCODE_IVP_SUBWU2NX8, + OPCODE_IVP_SUBWUA2NX8, + OPCODE_IVP_RANDB2N, + OPCODE_IVP_RORB2N, + OPCODE_IVP_RANDBN, + OPCODE_IVP_RORBN, + OPCODE_IVP_RANDBN_2, + OPCODE_IVP_RORBN_2, + OPCODE_IVP_AVGNX16, + OPCODE_IVP_AVGUNX16, + OPCODE_IVP_AVG2NX8, + OPCODE_IVP_AVGR2NX8, + OPCODE_IVP_AVGRNX16, + OPCODE_IVP_AVGRUNX16, + OPCODE_IVP_GATHERANX8U, + OPCODE_IVP_GATHERANX16, + OPCODE_IVP_GATHERAN_2X32, + OPCODE_IVP_GATHERANX8UT, + OPCODE_IVP_GATHERANX16T, + OPCODE_IVP_GATHERAN_2X32T, + OPCODE_IVP_GATHERDNX16, + OPCODE_IVP_GATHERDNX8S, + OPCODE_IVP_GATHERD2NX8_L, + OPCODE_IVP_GATHERD2NX8_H, + OPCODE_IVP_MOVGATHERD, + OPCODE_IVP_SCATTERNX8U, + OPCODE_IVP_SCATTER2NX8_L, + OPCODE_IVP_SCATTER2NX8_H, + OPCODE_IVP_SCATTERNX16, + OPCODE_IVP_SCATTERN_2X32, + OPCODE_IVP_SCATTERNX8UT, + OPCODE_IVP_SCATTER2NX8T_L, + OPCODE_IVP_SCATTER2NX8T_H, + OPCODE_IVP_SCATTERNX16T, + OPCODE_IVP_SCATTERN_2X32T, + OPCODE_IVP_SCATTERW, + OPCODE_IVP_COUNTEQZ4NX8, + OPCODE_IVP_COUNTEQ4NX8, + OPCODE_IVP_COUNTEQMZ4NX8, + OPCODE_IVP_COUNTEQM4NX8, + OPCODE_IVP_COUNTLEZ4NX8, + OPCODE_IVP_COUNTLE4NX8, + OPCODE_IVP_COUNTLEMZ4NX8, + OPCODE_IVP_COUNTLEM4NX8, + OPCODE_IVP_LSR2NX8_I, + OPCODE_IVP_LSR2NX8_IP, + OPCODE_IVP_LSR2NX8_X, + OPCODE_IVP_LSR2NX8_XP, + OPCODE_IVP_LSRNX16_I, + OPCODE_IVP_LSRNX16_IP, + OPCODE_IVP_LSRNX16_X, + OPCODE_IVP_LSRNX16_XP, + OPCODE_IVP_LSRN_2X32_I, + OPCODE_IVP_LSRN_2X32_IP, + OPCODE_IVP_LSRN_2X32_X, + OPCODE_IVP_LSRN_2X32_XP, + OPCODE_IVP_ABSNX16, + OPCODE_IVP_ABSSNX16, + OPCODE_IVP_ABSSUBNX16, + OPCODE_IVP_ABSSUBUNX16, + OPCODE_IVP_ABSSSUBNX16, + OPCODE_EXCW, + OPCODE_RFE, + OPCODE_RFDE, + OPCODE_SYSCALL, + OPCODE_CALL12, + OPCODE_CALL8, + OPCODE_CALL4, + OPCODE_CALLX12, + OPCODE_CALLX8, + OPCODE_CALLX4, + OPCODE_ENTRY, + OPCODE_MOVSP, + OPCODE_ROTW, + OPCODE_RETW, + OPCODE_RETW_N, + OPCODE_RFWO, + OPCODE_RFWU, + OPCODE_L32E, + OPCODE_S32E, + OPCODE_RSR_WINDOWBASE, + OPCODE_WSR_WINDOWBASE, + OPCODE_XSR_WINDOWBASE, + OPCODE_RSR_WINDOWSTART, + OPCODE_WSR_WINDOWSTART, + OPCODE_XSR_WINDOWSTART, + OPCODE_ADD_N, + OPCODE_ADDI_N, + OPCODE_BEQZ_N, + OPCODE_BNEZ_N, + OPCODE_ILL_N, + OPCODE_L32I_N, + OPCODE_MOV_N, + OPCODE_MOVI_N, + OPCODE_NOP_N, + OPCODE_RET_N, + OPCODE_S32I_N, + OPCODE_RUR_THREADPTR, + OPCODE_WUR_THREADPTR, + OPCODE_ADDI, + OPCODE_ADDMI, + OPCODE_ADD, + OPCODE_SUB, + OPCODE_ADDX2, + OPCODE_ADDX4, + OPCODE_ADDX8, + OPCODE_SUBX2, + OPCODE_SUBX4, + OPCODE_SUBX8, + OPCODE_AND, + OPCODE_OR, + OPCODE_XOR, + OPCODE_BEQI, + OPCODE_BNEI, + OPCODE_BGEI, + OPCODE_BLTI, + OPCODE_BBCI, + OPCODE_BBSI, + OPCODE_BGEUI, + OPCODE_BLTUI, + OPCODE_BEQ, + OPCODE_BNE, + OPCODE_BGE, + OPCODE_BLT, + OPCODE_BGEU, + OPCODE_BLTU, + OPCODE_BANY, + OPCODE_BNONE, + OPCODE_BALL, + OPCODE_BNALL, + OPCODE_BBC, + OPCODE_BBS, + OPCODE_BEQZ, + OPCODE_BNEZ, + OPCODE_BGEZ, + OPCODE_BLTZ, + OPCODE_CALL0, + OPCODE_CALLX0, + OPCODE_CONST16, + OPCODE_EXTUI, + OPCODE_ILL, + OPCODE_J, + OPCODE_JX, + OPCODE_L16UI, + OPCODE_L16SI, + OPCODE_L32I, + OPCODE_L32R, + OPCODE_L8UI, + OPCODE_LOOP, + OPCODE_LOOPNEZ, + OPCODE_LOOPGTZ, + OPCODE_MOVI, + OPCODE_MOVEQZ, + OPCODE_MOVNEZ, + OPCODE_MOVLTZ, + OPCODE_MOVGEZ, + OPCODE_NEG, + OPCODE_ABS, + OPCODE_NOP, + OPCODE_L32EX, + OPCODE_S32EX, + OPCODE_GETEX, + OPCODE_CLREX, + OPCODE_RET, + OPCODE_SIMCALL, + OPCODE_S16I, + OPCODE_S32I, + OPCODE_S32NB, + OPCODE_S8I, + OPCODE_SSR, + OPCODE_SSL, + OPCODE_SSA8L, + OPCODE_SSA8B, + OPCODE_SSAI, + OPCODE_SLL, + OPCODE_SRC, + OPCODE_SRL, + OPCODE_SRA, + OPCODE_SLLI, + OPCODE_SRAI, + OPCODE_SRLI, + OPCODE_MEMW, + OPCODE_EXTW, + OPCODE_ISYNC, + OPCODE_RSYNC, + OPCODE_ESYNC, + OPCODE_DSYNC, + OPCODE_RSIL, + OPCODE_RSR_LEND, + OPCODE_WSR_LEND, + OPCODE_XSR_LEND, + OPCODE_RSR_LCOUNT, + OPCODE_WSR_LCOUNT, + OPCODE_XSR_LCOUNT, + OPCODE_RSR_LBEG, + OPCODE_WSR_LBEG, + OPCODE_XSR_LBEG, + OPCODE_RSR_SAR, + OPCODE_WSR_SAR, + OPCODE_XSR_SAR, + OPCODE_RSR_MEMCTL, + OPCODE_WSR_MEMCTL, + OPCODE_XSR_MEMCTL, + OPCODE_RSR_LITBASE, + OPCODE_WSR_LITBASE, + OPCODE_XSR_LITBASE, + OPCODE_RSR_CONFIGID0, + OPCODE_WSR_CONFIGID0, + OPCODE_RSR_CONFIGID1, + OPCODE_RSR_PS, + OPCODE_WSR_PS, + OPCODE_XSR_PS, + OPCODE_RSR_EPC1, + OPCODE_WSR_EPC1, + OPCODE_XSR_EPC1, + OPCODE_RSR_EXCSAVE1, + OPCODE_WSR_EXCSAVE1, + OPCODE_XSR_EXCSAVE1, + OPCODE_RSR_EPC2, + OPCODE_WSR_EPC2, + OPCODE_XSR_EPC2, + OPCODE_RSR_EXCSAVE2, + OPCODE_WSR_EXCSAVE2, + OPCODE_XSR_EXCSAVE2, + OPCODE_RSR_EPC3, + OPCODE_WSR_EPC3, + OPCODE_XSR_EPC3, + OPCODE_RSR_EXCSAVE3, + OPCODE_WSR_EXCSAVE3, + OPCODE_XSR_EXCSAVE3, + OPCODE_RSR_EPC4, + OPCODE_WSR_EPC4, + OPCODE_XSR_EPC4, + OPCODE_RSR_EXCSAVE4, + OPCODE_WSR_EXCSAVE4, + OPCODE_XSR_EXCSAVE4, + OPCODE_RSR_EPS2, + OPCODE_WSR_EPS2, + OPCODE_XSR_EPS2, + OPCODE_RSR_EPS3, + OPCODE_WSR_EPS3, + OPCODE_XSR_EPS3, + OPCODE_RSR_EPS4, + OPCODE_WSR_EPS4, + OPCODE_XSR_EPS4, + OPCODE_RSR_EXCVADDR, + OPCODE_WSR_EXCVADDR, + OPCODE_XSR_EXCVADDR, + OPCODE_RSR_DEPC, + OPCODE_WSR_DEPC, + OPCODE_XSR_DEPC, + OPCODE_RSR_EXCCAUSE, + OPCODE_WSR_EXCCAUSE, + OPCODE_XSR_EXCCAUSE, + OPCODE_RSR_PRID, + OPCODE_RSR_VECBASE, + OPCODE_WSR_VECBASE, + OPCODE_XSR_VECBASE, + OPCODE_RSR_MPUCFG, + OPCODE_WSR_MPUCFG, + OPCODE_RSR_GSERR, + OPCODE_WSR_GSERR, + OPCODE_XSR_GSERR, + OPCODE_SALT, + OPCODE_SALTU, + OPCODE_MUL16U, + OPCODE_MUL16S, + OPCODE_MULL, + OPCODE_MULUH, + OPCODE_MULSH, + OPCODE_RFI, + OPCODE_WAITI, + OPCODE_RSR_INTERRUPT, + OPCODE_WSR_INTSET, + OPCODE_WSR_INTCLEAR, + OPCODE_RSR_INTENABLE, + OPCODE_WSR_INTENABLE, + OPCODE_XSR_INTENABLE, + OPCODE_BREAK, + OPCODE_BREAK_N, + OPCODE_RSR_DBREAKA0, + OPCODE_WSR_DBREAKA0, + OPCODE_XSR_DBREAKA0, + OPCODE_RSR_DBREAKC0, + OPCODE_WSR_DBREAKC0, + OPCODE_XSR_DBREAKC0, + OPCODE_RSR_IBREAKA0, + OPCODE_WSR_IBREAKA0, + OPCODE_XSR_IBREAKA0, + OPCODE_RSR_IBREAKENABLE, + OPCODE_WSR_IBREAKENABLE, + OPCODE_XSR_IBREAKENABLE, + OPCODE_RSR_DEBUGCAUSE, + OPCODE_WSR_DEBUGCAUSE, + OPCODE_XSR_DEBUGCAUSE, + OPCODE_RSR_ICOUNT, + OPCODE_WSR_ICOUNT, + OPCODE_XSR_ICOUNT, + OPCODE_RSR_ICOUNTLEVEL, + OPCODE_WSR_ICOUNTLEVEL, + OPCODE_XSR_ICOUNTLEVEL, + OPCODE_RSR_DDR, + OPCODE_WSR_DDR, + OPCODE_XSR_DDR, + OPCODE_LDDR32_P, + OPCODE_SDDR32_P, + OPCODE_RFDO, + OPCODE_RFDD, + OPCODE_WSR_MMID, + OPCODE_ANDB, + OPCODE_ANDBC, + OPCODE_ORB, + OPCODE_ORBC, + OPCODE_XORB, + OPCODE_ANY4, + OPCODE_ALL4, + OPCODE_ANY8, + OPCODE_ALL8, + OPCODE_BF, + OPCODE_BT, + OPCODE_MOVF, + OPCODE_MOVT, + OPCODE_RSR_BR, + OPCODE_WSR_BR, + OPCODE_XSR_BR, + OPCODE_RSR_CCOUNT, + OPCODE_WSR_CCOUNT, + OPCODE_XSR_CCOUNT, + OPCODE_RSR_CCOMPARE0, + OPCODE_WSR_CCOMPARE0, + OPCODE_XSR_CCOMPARE0, + OPCODE_RSR_CCOMPARE1, + OPCODE_WSR_CCOMPARE1, + OPCODE_XSR_CCOMPARE1, + OPCODE_IPF, + OPCODE_IHI, + OPCODE_IPFL, + OPCODE_IHU, + OPCODE_IIU, + OPCODE_III, + OPCODE_LICT, + OPCODE_LICW, + OPCODE_SICT, + OPCODE_SICW, + OPCODE_WSR_CACHEADRDIS, + OPCODE_RSR_CACHEADRDIS, + OPCODE_XSR_CACHEADRDIS, + OPCODE_RPTLB0, + OPCODE_PPTLB, + OPCODE_RPTLB1, + OPCODE_WPTLB, + OPCODE_RSR_MPUENB, + OPCODE_WSR_MPUENB, + OPCODE_XSR_MPUENB, + OPCODE_RSR_CPENABLE, + OPCODE_WSR_CPENABLE, + OPCODE_XSR_CPENABLE, + OPCODE_CLAMPS, + OPCODE_MIN, + OPCODE_MAX, + OPCODE_MINU, + OPCODE_MAXU, + OPCODE_NSA, + OPCODE_NSAU, + OPCODE_SEXT, + OPCODE_L32AI, + OPCODE_S32RI, + OPCODE_RSR_ATOMCTL, + OPCODE_WSR_ATOMCTL, + OPCODE_XSR_ATOMCTL, + OPCODE_QUOU, + OPCODE_QUOS, + OPCODE_REMU, + OPCODE_REMS, + OPCODE_RSR_ERACCESS, + OPCODE_WSR_ERACCESS, + OPCODE_XSR_ERACCESS, + OPCODE_RER, + OPCODE_WER, + OPCODE_BEQZ_W15, + OPCODE_BNEZ_W15, + OPCODE_BGEZ_W15, + OPCODE_BLTZ_W15, + OPCODE_BEQI_W15, + OPCODE_BNEI_W15, + OPCODE_BGEI_W15, + OPCODE_BLTI_W15, + OPCODE_BGEUI_W15, + OPCODE_BLTUI_W15, + OPCODE_BBCI_W15, + OPCODE_BBSI_W15, + OPCODE_BEQ_W15, + OPCODE_BNE_W15, + OPCODE_BGE_W15, + OPCODE_BLT_W15, + OPCODE_BGEU_W15, + OPCODE_BLTU_W15, + OPCODE_BANY_W15, + OPCODE_BNONE_W15, + OPCODE_BALL_W15, + OPCODE_BNALL_W15, + OPCODE_BBC_W15, + OPCODE_BBS_W15, + OPCODE_MTK_AndPOPC, + OPCODE_iq_tie2apb_inq0_pop, + OPCODE_iq_tie2apb_inq0_is_ready, + OPCODE_iq_tie2apb_inq0_nonblocking_peek, + OPCODE_iq_tie2apb_inq0_nonblocking_pop, + OPCODE_iq_tie2apb_inq0_blocking_peek, + OPCODE_oq_tie2apb_outq0_push_read, + OPCODE_oq_tie2apb_outq0_push_write, + OPCODE_oq_tie2apb_outq0_is_ready, + OPCODE_oq_tie2apb_outq0_nonblocking_push_read, + OPCODE_oq_tie2apb_outq0_nonblocking_push_write, + OPCODE_RUR_APB_PIPE, + OPCODE_WUR_APB_PIPE +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_f0_s0_ldst_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f0_s0_ldst_33_11_Slot_f0_s0_ldst_get (insn) == 135587) + return OPCODE_IVP_GATHERANX16; + if (Field_fld_f0_s0_ldst_33_11_Slot_f0_s0_ldst_get (insn) == 135591) + return OPCODE_IVP_GATHERANX8U; + if (Field_fld_f0_s0_ldst_33_11_Slot_f0_s0_ldst_get (insn) == 135595) + return OPCODE_IVP_GATHERAN_2X32; + if (Field_fld_f0_s0_ldst_33_11_Slot_f0_s0_ldst_get (insn) == 136300 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 5) + return OPCODE_IVP_MOVGATHERD; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68046) + return OPCODE_ADD; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68047) + return OPCODE_ADDX2; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68050) + return OPCODE_MAXU; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68051) + return OPCODE_MIN; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68054) + return OPCODE_MINU; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68055) + return OPCODE_MOVEQZ; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68058) + return OPCODE_MOVGEZ; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68059) + return OPCODE_MOVLTZ; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68062) + return OPCODE_MOVNEZ; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68063) + return OPCODE_MUL16S; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68116) + return OPCODE_ADDX4; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68117) + return OPCODE_AND; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68118) + return OPCODE_ADDX8; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68119) + return OPCODE_MAX; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68120) + return OPCODE_MUL16U; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68121) + return OPCODE_MULSH; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68122) + return OPCODE_MULL; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68123) + return OPCODE_MULUH; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68124) + return OPCODE_OR; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68125) + return OPCODE_SALTU; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68126) + return OPCODE_SALT; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68127) + return OPCODE_SRC; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68129) + return OPCODE_SUB; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68131) + return OPCODE_SUBX2; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68133) + return OPCODE_SUBX4; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68135) + return OPCODE_SUBX8; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68137) + return OPCODE_XOR; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68139) + return OPCODE_CLAMPS; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68141) + return OPCODE_SEXT; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68143) + return OPCODE_SRLI; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68148 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 5) + return OPCODE_SLL; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68152 && + Field_fld_f0_s0_ldst_3_0_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68152 && + Field_fld_f0_s0_ldst_3_0_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68152 && + Field_fld_f0_s0_ldst_3_0_Slot_f0_s0_ldst_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get (insn) == 68152 && + Field_fld_f0_s0_ldst_3_0_Slot_f0_s0_ldst_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33892) + return OPCODE_IVP_LS2NX8_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33893) + return OPCODE_IVP_LS2NX8_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33894) + return OPCODE_IVP_LSNX16_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33895) + return OPCODE_IVP_LSNX16_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33904) + return OPCODE_IVP_LSNX8S_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33905) + return OPCODE_IVP_LSNX8S_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33906) + return OPCODE_IVP_LSN_2X16S_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33907) + return OPCODE_IVP_LSN_2X16S_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33908) + return OPCODE_IVP_LSN_2X32_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33909) + return OPCODE_IVP_LSN_2X32_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33910) + return OPCODE_IVP_LSR2NX8_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33911) + return OPCODE_IVP_LSR2NX8_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33912) + return OPCODE_IVP_LSRNX16_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33913) + return OPCODE_IVP_LSRNX16_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33914) + return OPCODE_IVP_LSRN_2X32_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33915) + return OPCODE_IVP_LSRN_2X32_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33916) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33917) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33918) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33919) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33921) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33923) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33925) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33927) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33929) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33931) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33933) + return OPCODE_IVP_SS2NX8_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33935) + return OPCODE_IVP_SS2NX8_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33937) + return OPCODE_IVP_SSNX16_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33939) + return OPCODE_IVP_SSNX16_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33941) + return OPCODE_IVP_SSNX8S_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33943) + return OPCODE_IVP_SSNX8S_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33945) + return OPCODE_IVP_SSN_2X16S_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33947) + return OPCODE_IVP_SSN_2X16S_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33949) + return OPCODE_IVP_SSN_2X32_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33951) + return OPCODE_IVP_SSN_2X32_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33953) + return OPCODE_IVP_SV2NX8_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33955) + return OPCODE_IVP_SV2NX8_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33957) + return OPCODE_IVP_SVNX8S_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33959) + return OPCODE_IVP_SVNX8S_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33961) + return OPCODE_IVP_SVNX8U_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33963) + return OPCODE_IVP_SVNX8U_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33965) + return OPCODE_IVP_SVN_2X16S_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33967) + return OPCODE_IVP_SVN_2X16S_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33969) + return OPCODE_IVP_SVN_2X16U_X; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33971) + return OPCODE_IVP_SVN_2X16U_XP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33973) + return OPCODE_SLLI; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33975) + return OPCODE_IVP_LS2NX8_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33977) + return OPCODE_IVP_LSNX16_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33979) + return OPCODE_IVP_LSNX8S_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33981) + return OPCODE_IVP_LSN_2X16S_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33983) + return OPCODE_IVP_LSN_2X32_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33985) + return OPCODE_IVP_LSR2NX8_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33987) + return OPCODE_IVP_LSRNX16_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33989) + return OPCODE_IVP_LSRN_2X32_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33991) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33993) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33995) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33997) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 33999) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34001) + return OPCODE_IVP_SS2NX8_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34003) + return OPCODE_IVP_SSNX16_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34005) + return OPCODE_IVP_SSNX8S_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34007) + return OPCODE_IVP_SSN_2X16S_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34009) + return OPCODE_IVP_SSN_2X32_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34011) + return OPCODE_IVP_SV2NX8_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34013) + return OPCODE_IVP_SVNX8S_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34015) + return OPCODE_IVP_SVNX8U_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34017) + return OPCODE_IVP_SVN_2X16S_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34019) + return OPCODE_IVP_SVN_2X16U_IP; + if (Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get (insn) == 34021) + return OPCODE_SRAI; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 16944) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 16945) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17025 && + Field_fld_f0_s0_ldst_7_7_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17026 && + Field_fld_f0_s0_ldst_7_7_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17028 && + Field_fld_f0_s0_ldst_7_7_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17028 && + Field_fld_f0_s0_ldst_7_7_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17036 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 10) + return OPCODE_IVP_MOVVV; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17036 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 12) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17036 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 11) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17036 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 4) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17036 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17036 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 14) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17036 && + Field_fld_f0_s0_ldst_7_5_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_SHFL2NX8I_S0; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17036 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 5) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17036 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 9) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17037 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get (insn) == 17037 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4214 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4215 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4216 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4217 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4218 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4219 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SA2NX8_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4220 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SANX8S_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4221 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SANX8U_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4222 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SAN_2X16S_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 4223 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SAN_2X16U_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8444) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8445) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8446) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8447) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8448) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8449) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8450) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8451) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8452) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8453) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8454) + return OPCODE_IVP_SAV2NX8_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8455) + return OPCODE_IVP_SAVNX8S_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8456) + return OPCODE_IVP_SAVNX8U_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8457) + return OPCODE_IVP_SAVN_2X16S_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8458) + return OPCODE_IVP_SAVN_2X16U_XP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8459) + return OPCODE_IVP_LS2NX8_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8460) + return OPCODE_IVP_LSNX16_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8461) + return OPCODE_IVP_LSNX8S_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8462) + return OPCODE_IVP_LSN_2X16S_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8463) + return OPCODE_IVP_LSR2NX8_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8464) + return OPCODE_IVP_LSRNX16_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8465) + return OPCODE_IVP_LSRN_2X32_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8466) + return OPCODE_IVP_SS2NX8_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8467) + return OPCODE_IVP_SSNX16_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8468) + return OPCODE_IVP_SSNX8S_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8469) + return OPCODE_IVP_SSN_2X16S_I; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8516 && + Field_fld_f0_s0_ldst_12_4_Slot_f0_s0_ldst_get (insn) == 15) + return OPCODE_IVP_LA_PP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8516 && + Field_fld_f0_s0_ldst_12_4_Slot_f0_s0_ldst_get (insn) == 31) + return OPCODE_IVP_SAPOS_FP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8516 && + Field_fld_f0_s0_ldst_12_2_Slot_f0_s0_ldst_get (insn) == 188) + return OPCODE_IVP_MALIGN; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8516 && + Field_fld_f0_s0_ldst_12_0_Slot_f0_s0_ldst_get (insn) == 756) + return OPCODE_IVP_ZALIGN; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8520 && + Field_fld_f0_s0_ldst_12_8_Slot_f0_s0_ldst_get (insn) == 2) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get (insn) == 8520 && + Field_fld_f0_s0_ldst_12_8_Slot_f0_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SALIGN_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 2104 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_LOOP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 2105 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_LOOPGTZ; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 2106 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_LOOPNEZ; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4182) + return OPCODE_ADDI; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4183) + return OPCODE_ADDMI; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4184) + return OPCODE_IVP_LV2NX8T_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4185) + return OPCODE_IVP_LV2NX8T_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4186) + return OPCODE_IVP_LVNX8ST_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4187) + return OPCODE_IVP_LVNX8ST_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4188) + return OPCODE_IVP_LVNX8UT_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4189) + return OPCODE_IVP_LVNX8UT_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4190) + return OPCODE_IVP_LVN_2X16ST_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4191) + return OPCODE_IVP_LVN_2X16ST_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4192) + return OPCODE_IVP_LVN_2X16UT_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4193) + return OPCODE_IVP_LVN_2X16UT_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4194) + return OPCODE_IVP_SV2NX8T_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4195) + return OPCODE_IVP_SV2NX8T_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4196) + return OPCODE_IVP_SVNX8ST_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4197) + return OPCODE_IVP_SVNX8ST_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4198) + return OPCODE_IVP_SVNX8UT_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4199) + return OPCODE_IVP_SVNX8UT_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4200) + return OPCODE_IVP_SVN_2X16ST_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4201) + return OPCODE_IVP_SVN_2X16ST_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4202) + return OPCODE_IVP_SVN_2X16UT_X; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4203) + return OPCODE_IVP_SVN_2X16UT_XP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4204) + return OPCODE_L16SI; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4205) + return OPCODE_L16UI; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4206) + return OPCODE_L32I; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4207) + return OPCODE_L8UI; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4208) + return OPCODE_S16I; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4209) + return OPCODE_S32I; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4210) + return OPCODE_S8I; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4211) + return OPCODE_IVP_LV2NX8T_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4212) + return OPCODE_IVP_LVNX8ST_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4213) + return OPCODE_IVP_LVNX8UT_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4214) + return OPCODE_IVP_LVN_2X16ST_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4215) + return OPCODE_IVP_LVN_2X16UT_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4216) + return OPCODE_IVP_SV2NX8T_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4217) + return OPCODE_IVP_SVNX8ST_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4218) + return OPCODE_IVP_SVNX8UT_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4219) + return OPCODE_IVP_SVN_2X16ST_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4220) + return OPCODE_IVP_SVN_2X16UT_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4221) + return OPCODE_MOVI; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4237 && + Field_fld_f0_s0_ldst_12_11_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_GATHERANX8UT; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4237 && + Field_fld_f0_s0_ldst_12_11_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_GATHERANX16T; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4237 && + Field_fld_f0_s0_ldst_12_11_Slot_f0_s0_ldst_get (insn) == 2) + return OPCODE_IVP_GATHERAN_2X32T; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4258 && + Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_7_6_Slot_f0_s0_ldst_get (insn) == 2) + return OPCODE_IVP_SBN_I; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4258 && + Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 14) + return OPCODE_IVP_SBN_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4258 && + Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_7_6_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SBN_2_I; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4258 && + Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 13) + return OPCODE_IVP_SBN_2_IP; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4258 && + Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_7_6_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_SB2N_I; + if (Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get (insn) == 4258 && + Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 12) + return OPCODE_IVP_SB2N_IP; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2078) + return OPCODE_IVP_LSN_2X32_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2079) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2080) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2081) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2082) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2083) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2084) + return OPCODE_IVP_SSN_2X32_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2085) + return OPCODE_IVP_SV2NX8_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2086) + return OPCODE_IVP_SVNX8S_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2087) + return OPCODE_IVP_SVNX8U_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2088) + return OPCODE_IVP_SVN_2X16S_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2089) + return OPCODE_IVP_SVN_2X16U_I; + if (Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get (insn) == 2090) + return OPCODE_EXTUI; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 524 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 525 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1028) + return OPCODE_IVP_LV2NX8T_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1029) + return OPCODE_IVP_LVNX8ST_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1030) + return OPCODE_IVP_LVNX8UT_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1031) + return OPCODE_IVP_LVN_2X16ST_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1032) + return OPCODE_IVP_LVN_2X16UT_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1033) + return OPCODE_IVP_SV2NX8T_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1034) + return OPCODE_IVP_SVNX8ST_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1035) + return OPCODE_IVP_SVNX8UT_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1036) + return OPCODE_IVP_SVN_2X16ST_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1037) + return OPCODE_IVP_SVN_2X16UT_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1038) + return OPCODE_J; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1062 && + Field_fld_f0_s0_ldst_13_9_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1065 && + Field_fld_f0_s0_ldst_15_15_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_12_8_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get (insn) == 1065 && + Field_fld_f0_s0_ldst_15_15_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_12_8_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SALIGN_I; + if (Field_fld_f0_s0_ldst_33_19_Slot_f0_s0_ldst_get (insn) == 260 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_REPNX16; + if (Field_fld_f0_s0_ldst_33_19_Slot_f0_s0_ldst_get (insn) == 261 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f0_s0_ldst_33_19_Slot_f0_s0_ldst_get (insn) == 530 && + Field_fld_f0_s0_ldst_13_9_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f0_s0_ldst_33_20_Slot_f0_s0_ldst_get (insn) == 128 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f0_s0_ldst_33_20_Slot_f0_s0_ldst_get (insn) == 129 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f0_s0_ldst_33_20_Slot_f0_s0_ldst_get (insn) == 256) + return OPCODE_CONST16; + if (Field_fld_f0_s0_ldst_33_20_Slot_f0_s0_ldst_get (insn) == 265 && + Field_fld_f0_s0_ldst_13_9_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_9_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_9_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_BBSI_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 8) + return OPCODE_BEQ_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 14) + return OPCODE_BNE_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 10) + return OPCODE_BGE_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 12) + return OPCODE_BLT_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 9) + return OPCODE_BGEU_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 11) + return OPCODE_BLTU_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 5) + return OPCODE_BANY_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 4) + return OPCODE_BALL_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 13) + return OPCODE_BNALL_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 6) + return OPCODE_BBC_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 0 && + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get (insn) == 7) + return OPCODE_BBS_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_11_4_Slot_f0_s0_ldst_get (insn) == 6) + return OPCODE_BEQZ_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_11_4_Slot_f0_s0_ldst_get (insn) == 54) + return OPCODE_BNEZ_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_11_4_Slot_f0_s0_ldst_get (insn) == 22) + return OPCODE_BGEZ_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_11_4_Slot_f0_s0_ldst_get (insn) == 38) + return OPCODE_BLTZ_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 5) + return OPCODE_BNEI_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 1) + return OPCODE_BGEI_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 3) + return OPCODE_BLTI_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 2) + return OPCODE_BGEUI_W15; + if (Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get (insn) == 1 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 4) + return OPCODE_BLTUI_W15; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 542396) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 542397) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 542398) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 542399) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 545025 && + Field_fld_f0_s0_ldst_8_0_Slot_f0_s0_ldst_get (insn) == 245) + return OPCODE_IVP_SCATTERW; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 545041 && + Field_fld_f0_s0_ldst_8_0_Slot_f0_s0_ldst_get (insn) == 245) + return OPCODE_NOP; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 545204 && + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get (insn) == 5) + return OPCODE_SSAI; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 545205 && + Field_fld_f0_s0_ldst_8_4_Slot_f0_s0_ldst_get (insn) == 21) + return OPCODE_SSL; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 545205 && + Field_fld_f0_s0_ldst_8_4_Slot_f0_s0_ldst_get (insn) == 5) + return OPCODE_SSA8L; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 545206 && + Field_fld_f0_s0_ldst_8_4_Slot_f0_s0_ldst_get (insn) == 5) + return OPCODE_SSR; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 545409) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 545441 && + Field_fld_f0_s0_ldst_8_8_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_NSA; + if (Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get (insn) == 545457 && + Field_fld_f0_s0_ldst_8_8_Slot_f0_s0_ldst_get (insn) == 0) + return OPCODE_NSAU; + return XTENSA_UNDEFINED; +} + +static int +Slot_f0_s3_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (insn) == 119328) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (insn) == 119332) + return OPCODE_IVP_EXTRVRN_2X32; + if (Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (insn) == 119336 && + Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_get (insn) == 13) + return OPCODE_IVP_MOVBRBV; + if (Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (insn) == 119336 && + Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (insn) == 119336 && + Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_get (insn) == 7) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (insn) == 119336 && + Field_fld_f0_s3_alu_7_7_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_INJBI2NX8; + if (Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (insn) == 119336 && + Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (insn) == 119336 && + Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_get (insn) == 9) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get (insn) == 119336 && + Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_get (insn) == 5) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f0_s3_alu_33_18_Slot_f0_s3_alu_get (insn) == 3728 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 532 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SRAIN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 533 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_3_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SLLINX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 533 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_3_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_ROTRINX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 564 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SRANX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 565 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_3_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SLSINX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 565 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_3_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 596 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SRAN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 597 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_3_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 597 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_2_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_ROTRI2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 597 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_2_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SLLI2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 628 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SRLIN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 629 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 12 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 7) + return OPCODE_IVP_MOVVV; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 629 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 14 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 7) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 629 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 13 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 7) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 629 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 12 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 5) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 629 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 15 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 5) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 629 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_2_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 629 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_2_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 629 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 13 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 5) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 629 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 13 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 6) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 660 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SRLNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 692 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SRLN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 724 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SRSNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 756 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SRSN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 760 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 7 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RADD2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 771 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_MINNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 772) + return OPCODE_IVP_SEL2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 44 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 56 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NSANX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 33 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NSAUNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 40 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_get (insn) == 1 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SHFLNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SHFLN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 32 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 60 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NSAN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get (insn) == 37 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NSAUN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 774 && + Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SHFL2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 804) + return OPCODE_IVP_SELNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 835 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 836) + return OPCODE_IVP_SELN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 837 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 1 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 837 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 1 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 867 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 868 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 868 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 868 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 868 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 8 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 9 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 10 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 9 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMAXUNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 10 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMINUNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 8 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 9 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMAXN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 10 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMINN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 10 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXUN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 11 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINUN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 9 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDUNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 8 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RADDU2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 869 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 8 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RADDSNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 899 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 900 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 14) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 900 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 11) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 900 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 900 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 15) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 900 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 10) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 900 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 9) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 901 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 14) + return OPCODE_IVP_SLANX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 901 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 8) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 901 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 15) + return OPCODE_IVP_SLLN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 931 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 931 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 932 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 11) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 932 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 15) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 932 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 12) + return OPCODE_IVP_MINNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 932 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 10) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 932 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 13) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 932 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 14) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 932 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 9) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 933 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 15) + return OPCODE_IVP_SLSIN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 933 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 14) + return OPCODE_IVP_SLAN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 933 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 13) + return OPCODE_IVP_ROTRIN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 963 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 10) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 13) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 7) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 14) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 15) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 11) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 964 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 9) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 965 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 15) + return OPCODE_IVP_SLSNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 965 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 14) + return OPCODE_IVP_SLLIN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 965 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 13) + return OPCODE_IVP_ROTRNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 995 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 14) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 15) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 5) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 10) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 12) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 13) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 4) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 9) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 11) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 996 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 997 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 14) + return OPCODE_IVP_SLLNX16; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 997 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 15) + return OPCODE_IVP_SLSN_2X32; + if (Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get (insn) == 997 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 13) + return OPCODE_IVP_ROTRN_2X32; + if (Field_fld_f0_s3_alu_33_25_Slot_f0_s3_alu_get (insn) == 8) + return OPCODE_IVP_DSELNX16; + if (Field_fld_f0_s3_alu_33_26_Slot_f0_s3_alu_get (insn) == 12 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 5 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 1 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_REPNX16; + if (Field_fld_f0_s3_alu_33_26_Slot_f0_s3_alu_get (insn) == 12 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 5 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 1 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f0_s3_alu_33_26_Slot_f0_s3_alu_get (insn) == 14 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 720) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f0_s3_alu_33_27_Slot_f0_s3_alu_get (insn) == 4 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_DSEL2NX8I_H; + if (Field_fld_f0_s3_alu_33_27_Slot_f0_s3_alu_get (insn) == 6 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 5 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 1 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f0_s3_alu_33_27_Slot_f0_s3_alu_get (insn) == 6 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 5 && + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get (insn) == 1 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f0_s3_alu_33_27_Slot_f0_s3_alu_get (insn) == 6 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 720) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f0_s3_alu_33_27_Slot_f0_s3_alu_get (insn) == 7 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 4 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 8) + return OPCODE_IVP_SHFL2NX8I; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_DSELNX16T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 24323 && + Field_fld_f0_s3_alu_7_3_Slot_f0_s3_alu_get (insn) == 16 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_MOVBVBR; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RBMINNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 14 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RBMAXNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 8 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 9 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDNX16T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMAXNX16T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 4 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMINNX16T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMAXUNX16T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 5 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMINUNX16T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 5 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 11 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 1 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_RBMINUNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 15 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RBMAXUNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 1 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 7 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 4 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 10 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 9 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 6 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 12 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 10 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDN_2X32T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_14_11_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_DSEL2NX8I; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 24323 && + Field_fld_f0_s3_alu_7_7_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTBI2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 8 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADD2NX8T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 13 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDUNX16T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 12 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDU2NX8T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 13 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 2 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 24 && + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get (insn) == 11 && + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDSNX16T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_7_Slot_f0_s3_alu_get (insn) == 0 && + Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 50) + return OPCODE_IVP_NOTB; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 34) + return OPCODE_IVP_MB; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5825) + return OPCODE_IVP_LTNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5796) + return OPCODE_IVP_LENX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5793) + return OPCODE_IVP_EQNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5828) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5858) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5799) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 18) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 66) + return OPCODE_IVP_NOTB1; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5856) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5795) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5792) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5859) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5826) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5798) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SELNX16T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 2) + return OPCODE_IVP_SELN_2X32T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5857) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5797) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5794) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5860) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5827) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get (insn) == 5824) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_14_14_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8I; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8T; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 82) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 4) + return OPCODE_IVP_RORB2N; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 98) + return OPCODE_IVP_RANDBN; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 6) + return OPCODE_IVP_RORBN; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 114) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get (insn) == 3 && + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get (insn) == 736 && + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get (insn) == 20) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f0_s3_alu_33_9_Slot_f0_s3_alu_get (insn) == 1584640 && + Field_fld_f0_s3_alu_8_8_Slot_f0_s3_alu_get (insn) == 1) + return OPCODE_MOV_N; + if (Field_fld_f0_s3_alu_33_9_Slot_f0_s3_alu_get (insn) == 1584640 && + Field_fld_f0_s3_alu_8_0_Slot_f0_s3_alu_get (insn) == 22) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_f1_s0_ldstalu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 4369 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 13) + return OPCODE_SLL; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 4371 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 13) + return OPCODE_IVP_MOVGATHERD; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5064) + return OPCODE_ADD; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5065) + return OPCODE_ADDX2; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5072) + return OPCODE_ADDX4; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5073) + return OPCODE_ADDX8; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5080) + return OPCODE_AND; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5081) + return OPCODE_MAX; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5088) + return OPCODE_MUL16U; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5089) + return OPCODE_MULL; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5096) + return OPCODE_MULSH; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5097) + return OPCODE_MULUH; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5104) + return OPCODE_OR; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5105) + return OPCODE_SALT; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5112) + return OPCODE_SALTU; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5113) + return OPCODE_SRC; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5185 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_GATHERANX16; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5189) + return OPCODE_SUB; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5190) + return OPCODE_MAXU; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5191) + return OPCODE_SUBX2; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5193 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_GATHERANX8U; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5197) + return OPCODE_SUBX4; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5198) + return OPCODE_MIN; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5199) + return OPCODE_SUBX8; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5201 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_GATHERAN_2X32; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5205) + return OPCODE_XOR; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5206) + return OPCODE_MINU; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5207) + return OPCODE_CLAMPS; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5213) + return OPCODE_SEXT; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5214) + return OPCODE_MOVEQZ; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5215) + return OPCODE_SRLI; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5221 && + Field_fld_f1_s0_ldstalu_3_0_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5221 && + Field_fld_f1_s0_ldstalu_3_0_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5221 && + Field_fld_f1_s0_ldstalu_3_0_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5221 && + Field_fld_f1_s0_ldstalu_3_0_Slot_f1_s0_ldstalu_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5222) + return OPCODE_MOVGEZ; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5230) + return OPCODE_MOVLTZ; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5238) + return OPCODE_MOVNEZ; + if (Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get (insn) == 5246) + return OPCODE_MUL16S; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 1782) + return OPCODE_IVP_LS2NX8_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 1783) + return OPCODE_IVP_LS2NX8_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 1786) + return OPCODE_IVP_LSNX16_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 1787) + return OPCODE_IVP_LSNX8S_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 1790) + return OPCODE_IVP_LSNX16_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 1791) + return OPCODE_IVP_LSNX8S_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2496) + return OPCODE_IVP_SVNX8S_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2497) + return OPCODE_SLLI; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2498) + return OPCODE_IVP_LSRN_2X32_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2499) + return OPCODE_IVP_SSNX8S_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2500) + return OPCODE_IVP_SVNX8S_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2501) + return OPCODE_IVP_LS2NX8_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2502) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2503) + return OPCODE_IVP_SSN_2X16S_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2504) + return OPCODE_IVP_SVNX8U_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2505) + return OPCODE_IVP_LSNX16_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2506) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2507) + return OPCODE_IVP_SSN_2X32_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2508) + return OPCODE_IVP_SVNX8U_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2509) + return OPCODE_IVP_LSNX8S_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2510) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2511) + return OPCODE_IVP_SV2NX8_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2512) + return OPCODE_IVP_SVN_2X16S_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2513) + return OPCODE_IVP_LSN_2X16S_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2514) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2515) + return OPCODE_IVP_SVNX8S_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2516) + return OPCODE_IVP_SVN_2X16S_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2517) + return OPCODE_IVP_LSN_2X32_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2518) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2519) + return OPCODE_IVP_SVNX8U_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2520) + return OPCODE_IVP_SVN_2X16U_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2521) + return OPCODE_IVP_LSR2NX8_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2522) + return OPCODE_IVP_SS2NX8_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2523) + return OPCODE_IVP_SVN_2X16S_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2524) + return OPCODE_IVP_SVN_2X16U_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2525) + return OPCODE_IVP_LSRNX16_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2526) + return OPCODE_IVP_SSNX16_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2527) + return OPCODE_IVP_SVN_2X16U_IP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2528) + return OPCODE_SRAI; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2561) + return OPCODE_IVP_LSN_2X16S_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2565) + return OPCODE_IVP_LSN_2X16S_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2569) + return OPCODE_IVP_LSN_2X32_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2573) + return OPCODE_IVP_LSN_2X32_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2577) + return OPCODE_IVP_LSR2NX8_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2581) + return OPCODE_IVP_LSR2NX8_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2585) + return OPCODE_IVP_LSRNX16_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2589) + return OPCODE_IVP_LSRNX16_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2593) + return OPCODE_IVP_LSRN_2X32_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2597) + return OPCODE_IVP_LSRN_2X32_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2601) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2605) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2609) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2613) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2617) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2621) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2625) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2629) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2633) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2637) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2641) + return OPCODE_IVP_SS2NX8_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2645) + return OPCODE_IVP_SS2NX8_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2649) + return OPCODE_IVP_SSNX16_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2653) + return OPCODE_IVP_SSNX16_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2657) + return OPCODE_IVP_SSNX8S_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2661) + return OPCODE_IVP_SSNX8S_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2665) + return OPCODE_IVP_SSN_2X16S_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2669) + return OPCODE_IVP_SSN_2X16S_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2673) + return OPCODE_IVP_SSN_2X32_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2677) + return OPCODE_IVP_SSN_2X32_XP; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2681) + return OPCODE_IVP_SV2NX8_X; + if (Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get (insn) == 2685) + return OPCODE_IVP_SV2NX8_XP; + if (Field_fld_f1_s0_ldstalu_30_14_Slot_f1_s0_ldstalu_get (insn) == 881) + return OPCODE_IVP_SCATTER2NX8_H; + if (Field_fld_f1_s0_ldstalu_30_14_Slot_f1_s0_ldstalu_get (insn) == 883) + return OPCODE_IVP_SCATTER2NX8_L; + if (Field_fld_f1_s0_ldstalu_30_14_Slot_f1_s0_ldstalu_get (insn) == 885) + return OPCODE_IVP_SCATTERNX16; + if (Field_fld_f1_s0_ldstalu_30_14_Slot_f1_s0_ldstalu_get (insn) == 887) + return OPCODE_IVP_SCATTERNX8U; + if (Field_fld_f1_s0_ldstalu_30_14_Slot_f1_s0_ldstalu_get (insn) == 889) + return OPCODE_IVP_SCATTERN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 524) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 525) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 526) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 527) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 528) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 529) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 530) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 531) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 532) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 533) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 534) + return OPCODE_IVP_SAV2NX8_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 535) + return OPCODE_IVP_SAVNX8S_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 536) + return OPCODE_IVP_SAVNX8U_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 537) + return OPCODE_IVP_SAVN_2X16S_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 538) + return OPCODE_IVP_SAVN_2X16U_XP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 539) + return OPCODE_IVP_LS2NX8_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 540) + return OPCODE_IVP_LSNX16_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 541) + return OPCODE_IVP_LSNX8S_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 542) + return OPCODE_IVP_LSN_2X16S_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 543) + return OPCODE_IVP_LSR2NX8_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 544 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_7_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 544 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_7_7_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 545 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 14) + return OPCODE_IVP_MOVVV; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 545 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 12) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 545 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 9) + return OPCODE_IVP_SANX8U_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 545 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 8) + return OPCODE_IVP_SANX8S_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 545 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 11) + return OPCODE_IVP_SAN_2X16U_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 545 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 10) + return OPCODE_IVP_SAN_2X16S_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 545 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 15) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 545 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 14) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 545 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 13) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 546 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 9) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 546 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 10) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 546 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 11) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 546 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_5_Slot_f1_s0_ldstalu_get (insn) == 7) + return OPCODE_IVP_SHFL2NX8I_S0; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 547 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 11) + return OPCODE_IVP_SA2NX8_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 547 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 9) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 547 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 10) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 547 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 14) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 547 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 15) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 547 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 15) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 576) + return OPCODE_IVP_LSRNX16_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 577) + return OPCODE_IVP_LSRN_2X32_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 578) + return OPCODE_IVP_SS2NX8_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 579) + return OPCODE_IVP_SSNX16_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 580) + return OPCODE_IVP_SSNX8S_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 581) + return OPCODE_IVP_SSN_2X16S_I; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 582) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 583) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 584) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 585) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 586) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 587) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 588) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 589) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 590) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 591) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 592) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 593) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 594) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 595) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 596) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 597) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 598) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 599) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 600) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 601) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 602) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 603) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 604) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 605) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 606) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 607) + return OPCODE_IVP_MINNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 608) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 609) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 610) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 611) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 612) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 613) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 614) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 615) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 616) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 617) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 618) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 619) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 620) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 623 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 623 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 672 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 672 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 672 && + Field_fld_f1_s0_ldstalu_12_8_Slot_f1_s0_ldstalu_get (insn) == 4) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 672 && + Field_fld_f1_s0_ldstalu_12_8_Slot_f1_s0_ldstalu_get (insn) == 5) + return OPCODE_IVP_SALIGN_IP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 672 && + Field_fld_f1_s0_ldstalu_12_4_Slot_f1_s0_ldstalu_get (insn) == 37) + return OPCODE_IVP_LA_PP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 672 && + Field_fld_f1_s0_ldstalu_12_4_Slot_f1_s0_ldstalu_get (insn) == 53) + return OPCODE_IVP_SAPOS_FP; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 672 && + Field_fld_f1_s0_ldstalu_12_2_Slot_f1_s0_ldstalu_get (insn) == 404) + return OPCODE_IVP_MALIGN; + if (Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get (insn) == 672 && + Field_fld_f1_s0_ldstalu_12_0_Slot_f1_s0_ldstalu_get (insn) == 1620) + return OPCODE_IVP_ZALIGN; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 210) + return OPCODE_ADDI; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 211) + return OPCODE_ADDMI; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 224) + return OPCODE_IVP_LV2NX8T_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 225) + return OPCODE_IVP_LV2NX8T_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 226) + return OPCODE_IVP_LVNX8ST_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 227) + return OPCODE_IVP_LVNX8ST_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 228) + return OPCODE_IVP_LVNX8UT_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 229) + return OPCODE_IVP_LVNX8UT_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 230) + return OPCODE_IVP_LVN_2X16ST_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 231) + return OPCODE_IVP_LVN_2X16ST_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 232) + return OPCODE_IVP_LVN_2X16UT_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 233) + return OPCODE_IVP_LVN_2X16UT_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 234) + return OPCODE_IVP_SV2NX8T_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 235) + return OPCODE_IVP_SV2NX8T_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 236) + return OPCODE_IVP_SVNX8ST_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 237) + return OPCODE_IVP_SVNX8ST_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 238) + return OPCODE_IVP_SVNX8UT_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 239) + return OPCODE_IVP_SVNX8UT_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 240) + return OPCODE_IVP_SVN_2X16ST_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 241) + return OPCODE_IVP_SVN_2X16ST_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 242) + return OPCODE_IVP_SVN_2X16UT_X; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 243) + return OPCODE_IVP_SVN_2X16UT_XP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 244) + return OPCODE_L16SI; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 245) + return OPCODE_L16UI; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 246) + return OPCODE_L32I; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 247) + return OPCODE_L8UI; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 248) + return OPCODE_S16I; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 249) + return OPCODE_S32I; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 250) + return OPCODE_S8I; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 251) + return OPCODE_IVP_LV2NX8T_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 252) + return OPCODE_IVP_LVNX8ST_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 253) + return OPCODE_IVP_LVNX8UT_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 254) + return OPCODE_IVP_LVN_2X16ST_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 255) + return OPCODE_IVP_LVN_2X16UT_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 256) + return OPCODE_IVP_SV2NX8T_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 257) + return OPCODE_IVP_SVNX8ST_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 258) + return OPCODE_IVP_SVNX8UT_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 259) + return OPCODE_IVP_SVN_2X16ST_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 260) + return OPCODE_IVP_SVN_2X16UT_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 261) + return OPCODE_MOVI; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 272 && + Field_fld_f1_s0_ldstalu_7_5_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_IVP_SB2N_I; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 273 && + Field_fld_f1_s0_ldstalu_12_12_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 13) + return OPCODE_IVP_SBN_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 273 && + Field_fld_f1_s0_ldstalu_7_5_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_IVP_SBN_2_I; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 273 && + Field_fld_f1_s0_ldstalu_12_12_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 12) + return OPCODE_IVP_SBN_2_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 273 && + Field_fld_f1_s0_ldstalu_12_12_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 12) + return OPCODE_IVP_SB2N_IP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 273 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 8) + return OPCODE_LOOPNEZ; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 274 && + Field_fld_f1_s0_ldstalu_7_5_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_IVP_SBN_I; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 275 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 6) + return OPCODE_LOOP; + if (Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get (insn) == 275 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 7) + return OPCODE_LOOPGTZ; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 92) + return OPCODE_IVP_LSN_2X32_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 93) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 94) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 95) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 96) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 97) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 98) + return OPCODE_IVP_SSN_2X32_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 99) + return OPCODE_IVP_SV2NX8_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 100) + return OPCODE_IVP_SVNX8S_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 101) + return OPCODE_IVP_SVNX8U_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 102) + return OPCODE_IVP_SVN_2X16S_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 103) + return OPCODE_IVP_SVN_2X16U_I; + if (Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get (insn) == 104) + return OPCODE_EXTUI; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 8) + return OPCODE_IVP_LV2NX8T_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 9) + return OPCODE_IVP_LVNX8ST_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 10) + return OPCODE_IVP_LVNX8UT_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 11) + return OPCODE_IVP_LVN_2X16ST_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 12) + return OPCODE_IVP_LVN_2X16UT_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 13) + return OPCODE_IVP_SV2NX8T_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 14) + return OPCODE_IVP_SVNX8ST_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 15) + return OPCODE_IVP_SVNX8UT_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 16) + return OPCODE_IVP_SVN_2X16ST_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 17) + return OPCODE_IVP_SVN_2X16UT_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 18) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 19) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 20) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 21) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 22) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 23) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 24) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 25) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 26) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 27) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 28) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 29) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 30) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 31) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 32) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 33) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 34) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 35) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 36) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 37) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 38) + return OPCODE_IVP_MINNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 39) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 40) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 41) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 42) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 43) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 44) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 45) + return OPCODE_J; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 53 && + Field_fld_f1_s0_ldstalu_14_14_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_SCATTER2NX8T_L; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 53 && + Field_fld_f1_s0_ldstalu_14_14_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_SCATTER2NX8T_H; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 54 && + Field_fld_f1_s0_ldstalu_14_14_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_SCATTERNX8UT; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 54 && + Field_fld_f1_s0_ldstalu_14_14_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_SCATTERNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 55 && + Field_fld_f1_s0_ldstalu_14_14_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_SCATTERN_2X32T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 68 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 5) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 70 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 2) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 70 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 71 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 2) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 80 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 2) + return OPCODE_IVP_LTNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 80 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 80 && + Field_fld_f1_s0_ldstalu_14_12_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_GATHERANX8UT; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 80 && + Field_fld_f1_s0_ldstalu_14_12_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_GATHERANX16T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 81 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 81 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 2) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 81 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 16) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 81 && + Field_fld_f1_s0_ldstalu_14_12_Slot_f1_s0_ldstalu_get (insn) == 1 && + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_GATHERAN_2X32T; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 82 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 6) + return OPCODE_IVP_LENX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 82 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 5) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 82 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 82 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 82 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 7) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 82 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 4) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 82 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 2) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 83 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_EQNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 83 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 2) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 83 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 5) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 83 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 7) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 83 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 4) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 83 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 83 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 6) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 84 && + Field_fld_f1_s0_ldstalu_15_15_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_12_8_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get (insn) == 84 && + Field_fld_f1_s0_ldstalu_15_15_Slot_f1_s0_ldstalu_get (insn) == 0 && + Field_fld_f1_s0_ldstalu_12_8_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_SALIGN_I; + if (Field_fld_f1_s0_ldstalu_30_19_Slot_f1_s0_ldstalu_get (insn) == 34 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 2) + return OPCODE_IVP_REPNX16; + if (Field_fld_f1_s0_ldstalu_30_19_Slot_f1_s0_ldstalu_get (insn) == 34 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 3) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f1_s0_ldstalu_30_19_Slot_f1_s0_ldstalu_get (insn) == 40 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f1_s0_ldstalu_30_20_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_CONST16; + if (Field_fld_f1_s0_ldstalu_30_20_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_SEL2NX8I_S0; + if (Field_fld_f1_s0_ldstalu_30_20_Slot_f1_s0_ldstalu_get (insn) == 17 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f1_s0_ldstalu_30_20_Slot_f1_s0_ldstalu_get (insn) == 17 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f1_s0_ldstalu_30_20_Slot_f1_s0_ldstalu_get (insn) == 20 && + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get (insn) == 0) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f1_s0_ldstalu_30_6_Slot_f1_s0_ldstalu_get (insn) == 279771 && + Field_fld_f1_s0_ldstalu_5_4_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_SSA8L; + if (Field_fld_f1_s0_ldstalu_30_6_Slot_f1_s0_ldstalu_get (insn) == 279775 && + Field_fld_f1_s0_ldstalu_5_4_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_SSL; + if (Field_fld_f1_s0_ldstalu_30_6_Slot_f1_s0_ldstalu_get (insn) == 279787 && + Field_fld_f1_s0_ldstalu_5_4_Slot_f1_s0_ldstalu_get (insn) == 1) + return OPCODE_SSR; + if (Field_fld_f1_s0_ldstalu_30_6_Slot_f1_s0_ldstalu_get (insn) == 344089 && + Field_fld_f1_s0_ldstalu_5_0_Slot_f1_s0_ldstalu_get (insn) == 21) + return OPCODE_IVP_SCATTERW; + if (Field_fld_f1_s0_ldstalu_30_6_Slot_f1_s0_ldstalu_get (insn) == 344217 && + Field_fld_f1_s0_ldstalu_5_0_Slot_f1_s0_ldstalu_get (insn) == 21) + return OPCODE_NOP; + if (Field_fld_f1_s0_ldstalu_30_8_Slot_f1_s0_ldstalu_get (insn) == 86340) + return OPCODE_NSA; + if (Field_fld_f1_s0_ldstalu_30_8_Slot_f1_s0_ldstalu_get (insn) == 86372) + return OPCODE_NSAU; + if (Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_get (insn) == 34969 && + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get (insn) == 13) + return OPCODE_SSAI; + if (Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_get (insn) == 41673) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_get (insn) == 41675) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_get (insn) == 41677) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_get (insn) == 41679) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_get (insn) == 43138) + return OPCODE_IVP_MOVAVU8; + return XTENSA_UNDEFINED; +} + +static int +Slot_f1_s2_mul_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4000) + return OPCODE_ADD; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4001) + return OPCODE_ADDX4; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4002) + return OPCODE_AND; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4003) + return OPCODE_SUB; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4004) + return OPCODE_ADDX2; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4005) + return OPCODE_ADDX8; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4006) + return OPCODE_OR; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4007) + return OPCODE_SUBX2; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4008) + return OPCODE_SUBX4; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4009) + return OPCODE_XOR; + if (Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get (insn) == 4012) + return OPCODE_SUBX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 390) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 391) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 392) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 393) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 394) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 395) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 396) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 397) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 398) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 399) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 400) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 401) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 402) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 403) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 404) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 405) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 406) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 407) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 408) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 411) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 413) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 415) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 416) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 417) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 418) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 421) + return OPCODE_IVP_MINNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 423) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 425) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 426) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 427) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 428) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 429) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 430) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 431) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 432) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 433) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 434) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 435) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 436) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 445) + return OPCODE_IVP_MULNX16PACKL; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 446) + return OPCODE_IVP_MULNX16PACKP; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 447) + return OPCODE_IVP_MULNX16PACKQ; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 460) + return OPCODE_IVP_REPNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 461) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 462 && + Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_SLSINX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 462 && + Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_ROTRINX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 463 && + Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_SLLINX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 463 && + Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 464 && + Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 464 && + Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 465 && + Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 465 && + Field_fld_f1_s2_mul_3_2_Slot_f1_s2_mul_get (insn) == 2) + return OPCODE_IVP_ROTRI2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 465 && + Field_fld_f1_s2_mul_3_2_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_SLLI2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 466 && + Field_fld_f1_s2_mul_3_2_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 467 && + Field_fld_f1_s2_mul_3_2_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 488 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 488 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 488 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 488 && + Field_fld_f1_s2_mul_9_6_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_SHFL2NX8I_S2; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 489 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 490 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 490 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_UNPKS2NX8_0; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 490 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_UNPKSNX16_H; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 490 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_UNPKU2NX8_0; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 491 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_UNPKS2NX8_1; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 491 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_UNPKSNX16_L; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 491 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_UNPKU2NX8_1; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 491 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 493 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 2) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 493 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 494 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MOVVV; + if (Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get (insn) == 495 && + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 180) + return OPCODE_IVP_MUL4T2N8XR8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 181) + return OPCODE_IVP_MUL4TA2N8XR8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 182) + return OPCODE_IVP_MULP2N8XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 183) + return OPCODE_IVP_MULPA2N8XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 184) + return OPCODE_IVP_MULPAN16XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 185) + return OPCODE_IVP_MULPN16XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 186) + return OPCODE_IVP_MULUS4T2N8XR8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 187) + return OPCODE_IVP_MULUS4TA2N8XR8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 188) + return OPCODE_IVP_MULUSP2N8XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 189) + return OPCODE_IVP_MULUSPA2N8XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 190) + return OPCODE_IVP_MULUSPAN16XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 191) + return OPCODE_IVP_MULUSPN16XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 192) + return OPCODE_ADDI; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 193) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 194) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_ADDW2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_ADDWA2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 8) + return OPCODE_IVP_ADDWS2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 10) + return OPCODE_IVP_ADDWU2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 11) + return OPCODE_IVP_ADDWUA2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 14) + return OPCODE_IVP_ADDWUS2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 7) + return OPCODE_IVP_ADDWNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_ADDWANX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 9) + return OPCODE_IVP_ADDWSNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 13) + return OPCODE_IVP_ADDWUNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 12) + return OPCODE_IVP_ADDWUANX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 233 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 15) + return OPCODE_IVP_ADDWUSNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULANX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULA2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULSNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULAN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULSUAN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULAHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULSUAHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULAN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULSHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULSN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 234 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULSN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUS2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSA2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUSNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUSANX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUSN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULSUN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULSUN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUSHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULSUHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUSAN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUSAHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUSAN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULSUAN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSUSHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULSUSN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 235 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULSUSN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 240 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 13) + return OPCODE_IVP_CVT24S2NX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 240 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 15) + return OPCODE_IVP_CVT48UNX32; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 240 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 14) + return OPCODE_IVP_CVT48SNX32; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 241 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 13) + return OPCODE_IVP_CVT24U2NX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 241 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 15) + return OPCODE_IVP_CVT48UN_2X64L; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 241 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 14) + return OPCODE_IVP_CVT48UN_2X64H; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 242 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 13) + return OPCODE_IVP_CVT24UNX32H; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 242 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 14) + return OPCODE_IVP_CVT96UN_2X64; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 242 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 15 && + Field_fld_f1_s2_mul_4_4_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULA2N8XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 242 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 15 && + Field_fld_f1_s2_mul_4_4_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL2N8XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 243 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 13) + return OPCODE_IVP_CVT24UNX32L; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 243 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 14 && + Field_fld_f1_s2_mul_4_4_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUSA2N8XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 243 && + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get (insn) == 14 && + Field_fld_f1_s2_mul_4_4_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUS2N8XR16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 245 && + Field_fld_f1_s2_mul_13_5_Slot_f1_s2_mul_get (insn) == 7) + return OPCODE_IVP_CVT24U32; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 245 && + Field_fld_f1_s2_mul_13_5_Slot_f1_s2_mul_get (insn) == 103) + return OPCODE_IVP_CVT48UNX32L; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 245 && + Field_fld_f1_s2_mul_13_5_Slot_f1_s2_mul_get (insn) == 39) + return OPCODE_IVP_CVT48SNX32L; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 245 && + Field_fld_f1_s2_mul_13_5_Slot_f1_s2_mul_get (insn) == 71) + return OPCODE_IVP_CVT48U64; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 245 && + Field_fld_f1_s2_mul_13_5_Slot_f1_s2_mul_get (insn) == 135) + return OPCODE_IVP_CVT96U64; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 245 && + Field_fld_f1_s2_mul_13_2_Slot_f1_s2_mul_get (insn) == 1592) + return OPCODE_IVP_MOVWW; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUU2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUUA2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUUNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUUANX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSSNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUUN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUUN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUSN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUUHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUUAN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUUAHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUAN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUUSHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUSSHN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSSN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 248 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUSSN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUUSNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUUSN_2X16X32_0; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUUSN_2X16X32_1; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_SUBWNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_SUBWANX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 10) + return OPCODE_IVP_SUBWUNX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 9) + return OPCODE_IVP_SUBWUANX16; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_SUBW2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_SUBWA2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 7) + return OPCODE_IVP_SUBWU2NX8; + if (Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get (insn) == 249 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 8) + return OPCODE_IVP_SUBWUA2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 7) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 8) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 9) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 10) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 11) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 12) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 13) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 14) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 15) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 16) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 17) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 18) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 19) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 20) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 21) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 24) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 27) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 30) + return OPCODE_IVP_MINNX16T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 33) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 34) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 35) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 36) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 37) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 38) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 5) + return OPCODE_IVP_LTNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 2) + return OPCODE_IVP_LENX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 16) + return OPCODE_IVP_EQNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 8) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 22) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 19) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 20) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 17) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 23) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 6) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 3) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 21) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 18) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 1) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 24) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 7) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get (insn) == 59 && + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f1_s2_mul_28_20_Slot_f1_s2_mul_get (insn) == 0) + return OPCODE_IVP_SEL2NX8I_S2; + if (Field_fld_f1_s2_mul_28_4_Slot_f1_s2_mul_get (insn) == 1003918 && + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get (insn) == 4) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_f1_s3_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_get (insn) == 1542 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_EXTRVRN_2X32; + if (Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_get (insn) == 1543 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_get (insn) == 1543 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_get (insn) == 1543 && + Field_fld_f1_s3_alu_9_7_Slot_f1_s3_alu_get (insn) == 4 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_INJBI2NX8; + if (Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_get (insn) == 1543 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_get (insn) == 1543 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_get (insn) == 9) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_get (insn) == 1543 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f1_s3_alu_30_17_Slot_f1_s3_alu_get (insn) == 384 && + Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_ADDI; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 24 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_MINNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 24 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 25 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 25 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 25 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 25 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 25 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 25 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 25 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 27 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 27 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_ROTRIN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 28 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 29 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 30 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 31 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 32) + return OPCODE_IVP_SEL2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 33) + return OPCODE_IVP_SELNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 34) + return OPCODE_IVP_SELN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 35 && + Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_COUNTEQZ4NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 35 && + Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_COUNTEQ4NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 36 && + Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_COUNTLE4NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 37 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 37 && + Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_COUNTLEZ4NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 38 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 38 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 38 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 39 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 39 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 40 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 40 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 41 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 41 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 42 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 43 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_MINNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 43 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 43 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 44 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 44 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 45 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 45 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 45 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 45 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 46 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 46 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 46 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 47 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 47 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 47 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 47 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 48 && + Field_fld_f1_s3_alu_14_14_Slot_f1_s3_alu_get (insn) == 1 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLLINX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 48 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_SLSNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 48 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_SRSNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 48 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 69) + return OPCODE_IVP_RADDNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 48 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 85) + return OPCODE_IVP_RADDN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 48 && + Field_fld_f1_s3_alu_14_14_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_ROTRINX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 48 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_ROTRNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 48 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 117) + return OPCODE_IVP_RADDU2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 48 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 101) + return OPCODE_IVP_RADDSNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_14_14_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLSINX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_14_14_Slot_f1_s3_alu_get (insn) == 1 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 85) + return OPCODE_IVP_RMAXNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 117) + return OPCODE_IVP_RMAXUNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_SLSN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_SRSN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 101) + return OPCODE_IVP_RMAXN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_ROTRN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 49 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 69) + return OPCODE_IVP_RADDUNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 50 && + Field_fld_f1_s3_alu_14_14_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 50 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLANX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 50 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 85) + return OPCODE_IVP_RMINNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 50 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 117) + return OPCODE_IVP_RMINUNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 50 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_SRAIN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 50 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 101) + return OPCODE_IVP_RMINN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 50 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 69) + return OPCODE_IVP_RMAXUN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 50 && + Field_fld_f1_s3_alu_14_13_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_ROTRI2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 50 && + Field_fld_f1_s3_alu_14_13_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLLI2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 112 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_MOVVV; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_SRANX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 120 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 116 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLAN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 69) + return OPCODE_IVP_RMINUN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 80 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 92 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_14_13_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_14_13_Slot_f1_s3_alu_get (insn) == 1 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 84 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 51 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 100 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 52 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLLIN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 52 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_SRAN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 53 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLLNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 53 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_SRLIN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 54 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_SRLNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 54 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLLN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 55 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLSIN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 55 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_SRLN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 55 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 116) + return OPCODE_IVP_RADD2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 17 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 17 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_NSANX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 21 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_NSAUNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 17 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 16) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 28) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_10_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_SHFLNX16; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_10_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_SHFLN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 17 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 17 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_NSAN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get (insn) == 21 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_NSAUN_2X32; + if (Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get (insn) == 56 && + Field_fld_f1_s3_alu_14_10_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_SHFL2NX8; + if (Field_fld_f1_s3_alu_30_22_Slot_f1_s3_alu_get (insn) == 10 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_SHFL2NX8I; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_SELNX16T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_SELN_2X32T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8I; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_14_Slot_f1_s3_alu_get (insn) == 62 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 908) + return OPCODE_IVP_MOVBVBR; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 20 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_LTNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 22 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_LENX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 21 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_EQNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 22 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 23 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 23 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 1 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 21 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_2_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 1 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 7) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 1 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 1 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 1 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 23 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 23 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 21 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 21 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 22 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 22 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 21 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 4) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 23 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 22 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 23 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 20 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 22 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 3) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 31 && + Field_fld_f1_s3_alu_9_7_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_get (insn) == 12) + return OPCODE_IVP_EXTBI2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 30 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 6) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 0 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 1 && + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get (insn) == 5) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 5 && + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get (insn) == 20 && + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get (insn) == 3 && + Field_fld_f1_s3_alu_3_3_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_2_Slot_f1_s3_alu_get (insn) == 8) + return OPCODE_IVP_REPNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_2_Slot_f1_s3_alu_get (insn) == 12) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_3_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_3_Slot_f1_s3_alu_get (insn) == 2) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_1_Slot_f1_s3_alu_get (insn) == 18) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_1_Slot_f1_s3_alu_get (insn) == 26) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_7_Slot_f1_s3_alu_get (insn) == 2 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 27 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_NOTB; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 26 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_MB; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 67) + return OPCODE_IVP_RBMINNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 98) + return OPCODE_IVP_RBMAXNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 81) + return OPCODE_IVP_RADDNX16T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 99) + return OPCODE_IVP_RMAXNX16T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 68) + return OPCODE_IVP_RMINNX16T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 115) + return OPCODE_IVP_RMAXUNX16T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 84) + return OPCODE_IVP_RMINUNX16T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 25 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 24 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 28 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_NOTB1; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 83) + return OPCODE_IVP_RBMINUNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 114) + return OPCODE_IVP_RBMAXUNX16; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 97) + return OPCODE_IVP_RADDN_2X32T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 65) + return OPCODE_IVP_RADD2NX8T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 82) + return OPCODE_IVP_RADDUNX16T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 66) + return OPCODE_IVP_RADDU2NX8T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get (insn) == 113) + return OPCODE_IVP_RADDSNX16T; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 29 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 16 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_RORB2N; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 30 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_RANDBN; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 17 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_RORBN; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 31 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get (insn) == 6 && + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get (insn) == 18 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 1) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f1_s3_alu_30_6_Slot_f1_s3_alu_get (insn) == 786436 && + Field_fld_f1_s3_alu_5_0_Slot_f1_s3_alu_get (insn) == 49) + return OPCODE_NOP; + if (Field_fld_f1_s3_alu_30_8_Slot_f1_s3_alu_get (insn) == 196613) + return OPCODE_MOV_N; + if (Field_fld_f1_s3_alu_30_8_Slot_f1_s3_alu_get (insn) == 200709 && + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get (insn) == 0) + return OPCODE_IVP_MOVBRBV; + return XTENSA_UNDEFINED; +} + +static int +Slot_f2_s2_mul_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 7809) + return OPCODE_ADD; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 7817) + return OPCODE_ADDX4; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 7825) + return OPCODE_AND; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 7833) + return OPCODE_SUB; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 7841) + return OPCODE_SUBX4; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 7849) + return OPCODE_XOR; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 8065) + return OPCODE_ADDX2; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 8073) + return OPCODE_ADDX8; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 8081) + return OPCODE_OR; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 8089) + return OPCODE_SUBX2; + if (Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get (insn) == 8097) + return OPCODE_SUBX8; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 973 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 973 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 18) + return OPCODE_IVP_UNPKSNX16_L; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 973 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_UNPKSNX16_H; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1004 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_MOVVV; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1004 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1004 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 22) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1004 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1004 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 19) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1004 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 18) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1004 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 20) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1005 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 16) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1005 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1005 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_UNPKS2NX8_0; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1005 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 17) + return OPCODE_IVP_UNPKS2NX8_1; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1005 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_UNPKU2NX8_0; + if (Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get (insn) == 1005 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 18) + return OPCODE_IVP_UNPKU2NX8_1; + if (Field_fld_f2_s2_mul_30_18_Slot_f2_s2_mul_get (insn) == 118 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 17) + return OPCODE_IVP_ROTRI2NX8; + if (Field_fld_f2_s2_mul_30_18_Slot_f2_s2_mul_get (insn) == 119 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 17) + return OPCODE_IVP_SLLI2NX8; + if (Field_fld_f2_s2_mul_30_18_Slot_f2_s2_mul_get (insn) == 122 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f2_s2_mul_30_18_Slot_f2_s2_mul_get (insn) == 126 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_get (insn) == 56 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 17) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_get (insn) == 56 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 16) + return OPCODE_IVP_ROTRINX16; + if (Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_get (insn) == 57 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 17) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_get (insn) == 57 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 16) + return OPCODE_IVP_SLLINX16; + if (Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_get (insn) == 58 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 17) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_get (insn) == 58 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 16) + return OPCODE_IVP_SLSINX16; + if (Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_get (insn) == 59 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 16) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 12 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 12 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 12 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 12 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 13 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 13 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 13 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 13 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 16 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 16 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 16 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 17 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 18 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_MINNX16T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 20 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 20 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULANX16PACKQT; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 20 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULANX16PACKPT; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 20 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 21 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULANX16PACKLT; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 21 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 31) + return OPCODE_IVP_MINNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 26) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 13) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 14) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 28) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 27) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 29) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 24) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 22) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 26) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 30) + return OPCODE_IVP_MULANX16PACKQ; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 31) + return OPCODE_IVP_MULSNX16PACKL; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 27) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULANX16PACKP; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULNX16PACKQ; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 21) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 24) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 25) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 20) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 23) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 26) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 29) + return OPCODE_IVP_MULANX16PACKL; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 31) + return OPCODE_IVP_MULSNX16PACKQ; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 30) + return OPCODE_IVP_MULNX16PACKP; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULSNX16PACKP; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULNX16PACKL; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 24) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 21) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 25) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 20) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 22) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 23) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 13) + return OPCODE_IVP_REPNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_11_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_LENX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 18 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_EQNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 20 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 18 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 18 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 20 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 18 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 13) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_11_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 18 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 18 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 18 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 18 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 19 && + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_DIVNX16Q_4STEP0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_DIVNX16SQ_4STEP0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_DIVNX16S_4STEP0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_DIVNX16U_4STEP0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_DIVN_2X32X16S_4STEP0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_DIVN_2X32X16U_4STEP0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 13 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULI2NX8X16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 13 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULAI2NX8X16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 13 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSI2NX8X16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 13 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSAI2NX8X16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 24 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT24U2NX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_CVT24S2NX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT24UNX32L; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT24UNX32H; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT48UNX32; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT48SNX32; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT48UN_2X64L; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT48UN_2X64H; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT96UN_2X64; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUU2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUUA2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUS2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSA2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULANX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 24 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUUANX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSANX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MUL2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULA2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADDW2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_ADDWA2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_ADDWS2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_ADDWU2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_ADDWUA2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADDWUS2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULSNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUSNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSSNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULSUN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULSUN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUUHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULSUHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULAN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUUAN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSAN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSUAN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULAHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUUAHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSAHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSUAHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULAN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUUAN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 24 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSAN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULSUAN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULSHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUSHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSSHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULSUSHN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUSN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSSN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULSUSN_2X16X32_0; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUSN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 24 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUSSN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULSUSN_2X16X32_1; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULPN16XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULPAN16XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUSPN16XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUSPAN16XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULP2N8XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULPA2N8XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSP2N8XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUSPA2N8XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL4T2N8XR8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MUL4TA2N8XR8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUS4T2N8XR8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUS4TA2N8XR8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_ADDWNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_ADDWANX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_ADDWSNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADDWUNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADDWUANX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADDWUSNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 26 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 25 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWANX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 30 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWUNX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 29 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWUANX16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 31 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_SUBW2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 24 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWA2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 27 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWU2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 28 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWUA2NX8; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 14 && + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get (insn) == 12) + return OPCODE_ADDI; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_10_Slot_f2_s2_mul_get (insn) == 416 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT24U32; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_10_Slot_f2_s2_mul_get (insn) == 419 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT48UNX32L; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_10_Slot_f2_s2_mul_get (insn) == 417 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT48SNX32L; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_10_Slot_f2_s2_mul_get (insn) == 418 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT48U64; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_10_Slot_f2_s2_mul_get (insn) == 420 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT96U64; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULI2NR8X16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULAI2NR8X16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSI2NR8X16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSAI2NR8X16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_7_Slot_f2_s2_mul_get (insn) == 3376 && + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MOVWW; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 8) + return OPCODE_IVP_DIVN_2X32X16S_4STEP; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 9) + return OPCODE_IVP_DIVN_2X32X16S_4STEPN; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 10) + return OPCODE_IVP_DIVN_2X32X16U_4STEP; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 11) + return OPCODE_IVP_DIVN_2X32X16U_4STEPN; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 4) + return OPCODE_IVP_DIVNX16S_4STEP; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 5) + return OPCODE_IVP_DIVNX16S_4STEPN; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 6) + return OPCODE_IVP_DIVNX16U_4STEP; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 15 && + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get (insn) == 7) + return OPCODE_IVP_DIVNX16U_4STEPN; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 17 && + Field_fld_f2_s2_mul_14_5_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSA2N8XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 17 && + Field_fld_f2_s2_mul_14_5_Slot_f2_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUS2N8XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 17 && + Field_fld_f2_s2_mul_14_5_Slot_f2_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULA2N8XR16; + if (Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get (insn) == 17 && + Field_fld_f2_s2_mul_14_5_Slot_f2_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL2N8XR16; + if (Field_fld_f2_s2_mul_30_6_Slot_f2_s2_mul_get (insn) == 498274 && + Field_fld_f2_s2_mul_5_0_Slot_f2_s2_mul_get (insn) == 3) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_f2_s3_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_get (insn) == 810 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_EXTRVRN_2X32; + if (Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_get (insn) == 811 && + Field_fld_f2_s3_alu_9_7_Slot_f2_s3_alu_get (insn) == 4 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_INJBI2NX8; + if (Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_get (insn) == 1311 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_get (insn) == 13) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_get (insn) == 1343 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_get (insn) == 13) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_get (insn) == 1375 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_get (insn) == 13) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_get (insn) == 1407 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_get (insn) == 13) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_get (insn) == 1439 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_get (insn) == 13) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_f2_s3_alu_30_18_Slot_f2_s3_alu_get (insn) == 100 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 24 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 26 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 26 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 26 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 26 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 26 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 27 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 27 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 27 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_MINNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 27 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 27 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 27 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 27 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 28 && + Field_fld_f2_s3_alu_14_14_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLLINX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 28 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_SLSNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 28 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_SRSNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 28 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRAN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 28 && + Field_fld_f2_s3_alu_14_14_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ROTRINX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 29 && + Field_fld_f2_s3_alu_14_14_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLSINX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 29 && + Field_fld_f2_s3_alu_14_14_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 29 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRLIN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 29 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_SLSN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 29 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_SRSN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 30 && + Field_fld_f2_s3_alu_14_14_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 30 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRLNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 30 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRAIN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 30 && + Field_fld_f2_s3_alu_14_13_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ROTRI2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 30 && + Field_fld_f2_s3_alu_14_13_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLLI2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 114 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_MOVVV; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRANX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 122 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 118 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRLN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 82 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 94 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_14_13_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_14_13_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 86 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 102 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 32) + return OPCODE_IVP_SEL2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 33) + return OPCODE_IVP_SELNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 34) + return OPCODE_IVP_SELN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 35 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 35 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 35 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 35 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 36 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 36 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_MINNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 37 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 37 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 38 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 38 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 39 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 39 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 40 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 837) + return OPCODE_IVP_RADDNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 40 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 853) + return OPCODE_IVP_RADDN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 40 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_ROTRNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 40 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 40 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 885) + return OPCODE_IVP_RADDU2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 40 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 869) + return OPCODE_IVP_RADDSNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 40 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 40 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 41 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 41 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 853) + return OPCODE_IVP_RMAXNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 41 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 885) + return OPCODE_IVP_RMAXUNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 41 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 41 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 41 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 869) + return OPCODE_IVP_RMAXN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 41 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_ROTRN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 41 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 837) + return OPCODE_IVP_RADDUNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 41 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 42 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLANX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 42 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 42 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 42 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 853) + return OPCODE_IVP_RMINNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 42 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 885) + return OPCODE_IVP_RMINUNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 42 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 869) + return OPCODE_IVP_RMINN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 42 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 837) + return OPCODE_IVP_RMAXUN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 42 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 43 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLAN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 43 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 837) + return OPCODE_IVP_RMINUN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 43 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 43 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 43 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 44 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 44 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLLIN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 44 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 44 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 45 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLLNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 45 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 45 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 45 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 45 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 46 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 46 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 46 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLLN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 46 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 46 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 47 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLSIN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 47 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_ROTRIN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 47 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 47 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 47 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 884) + return OPCODE_IVP_RADD2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 47 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 17 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 17 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_NSANX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 21 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_NSAUNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 17 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 16) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 28) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_10_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_SHFLNX16; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_10_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_SHFLN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 17 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 17 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_NSAN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get (insn) == 21 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_NSAUN_2X32; + if (Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get (insn) == 48 && + Field_fld_f2_s3_alu_14_10_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_SHFL2NX8; + if (Field_fld_f2_s3_alu_30_22_Slot_f2_s3_alu_get (insn) == 10 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_SHFL2NX8I; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_SELNX16T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_SELN_2X32T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 7) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_9_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8I; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 3 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_2_Slot_f2_s3_alu_get (insn) == 200) + return OPCODE_IVP_REPNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_2_Slot_f2_s3_alu_get (insn) == 204) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_3_Slot_f2_s3_alu_get (insn) == 96) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_3_Slot_f2_s3_alu_get (insn) == 98) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_1_Slot_f2_s3_alu_get (insn) == 402) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_1_Slot_f2_s3_alu_get (insn) == 410) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_14_Slot_f2_s3_alu_get (insn) == 62 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 652) + return OPCODE_IVP_MOVBVBR; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 20 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_LTNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 22 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_LENX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 21 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_EQNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 22 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 23 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 23 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 835) + return OPCODE_IVP_RBMINNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 866) + return OPCODE_IVP_RBMAXNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 849) + return OPCODE_IVP_RADDNX16T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 867) + return OPCODE_IVP_RMAXNX16T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 836) + return OPCODE_IVP_RMINNX16T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 883) + return OPCODE_IVP_RMAXUNX16T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 852) + return OPCODE_IVP_RMINUNX16T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 21 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_2_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 851) + return OPCODE_IVP_RBMINUNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 882) + return OPCODE_IVP_RBMAXUNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 23 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 23 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 21 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 21 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 22 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 22 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 2) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 865) + return OPCODE_IVP_RADDN_2X32T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 21 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 4) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 23 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 22 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 23 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 20 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 22 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 3) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 31 && + Field_fld_f2_s3_alu_9_7_Slot_f2_s3_alu_get (insn) == 4 && + Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_get (insn) == 12) + return OPCODE_IVP_EXTBI2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 833) + return OPCODE_IVP_RADD2NX8T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 850) + return OPCODE_IVP_RADDUNX16T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 834) + return OPCODE_IVP_RADDU2NX8T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 30 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 6) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get (insn) == 5) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get (insn) == 881) + return OPCODE_IVP_RADDSNX16T; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 5 && + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get (insn) == 20 && + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_3_3_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_7_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 11 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_NOTB; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 10 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_MB; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 9 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 8 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 12 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_NOTB1; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 13 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 0 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_RORB2N; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 14 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_RANDBN; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 1 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_RORBN; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 15 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get (insn) == 7 && + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get (insn) == 2 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 1) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f2_s3_alu_30_6_Slot_f2_s3_alu_get (insn) == 917504 && + Field_fld_f2_s3_alu_5_0_Slot_f2_s3_alu_get (insn) == 49) + return OPCODE_NOP; + if (Field_fld_f2_s3_alu_30_8_Slot_f2_s3_alu_get (insn) == 229380) + return OPCODE_MOV_N; + if (Field_fld_f2_s3_alu_30_8_Slot_f2_s3_alu_get (insn) == 233476 && + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get (insn) == 0) + return OPCODE_IVP_MOVBRBV; + return XTENSA_UNDEFINED; +} + +static int +Slot_f3_s0_ldst_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f3_s0_ldst_25_1_Slot_f3_s0_ldst_get (insn) == 4296040 && + Field_fld_f3_s0_ldst_0_0_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SCATTERW; + if (Field_fld_f3_s0_ldst_25_1_Slot_f3_s0_ldst_get (insn) == 4300136 && + Field_fld_f3_s0_ldst_0_0_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_f3_s0_ldst_25_11_Slot_f3_s0_ldst_get (insn) == 5027) + return OPCODE_IVP_GATHERANX16; + if (Field_fld_f3_s0_ldst_25_11_Slot_f3_s0_ldst_get (insn) == 5031) + return OPCODE_IVP_GATHERANX8U; + if (Field_fld_f3_s0_ldst_25_11_Slot_f3_s0_ldst_get (insn) == 5035) + return OPCODE_IVP_GATHERAN_2X32; + if (Field_fld_f3_s0_ldst_25_11_Slot_f3_s0_ldst_get (insn) == 5652 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 5) + return OPCODE_IVP_MOVGATHERD; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2561) + return OPCODE_XOR; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2565) + return OPCODE_CLAMPS; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2569) + return OPCODE_SEXT; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2573) + return OPCODE_SRLI; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2766) + return OPCODE_ADD; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2767) + return OPCODE_ADDX2; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2770) + return OPCODE_ADDX4; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2771) + return OPCODE_ADDX8; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2774) + return OPCODE_AND; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2775) + return OPCODE_MAX; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2778) + return OPCODE_MAXU; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2779) + return OPCODE_MIN; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2782) + return OPCODE_MINU; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2783) + return OPCODE_MOVEQZ; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2786) + return OPCODE_MOVGEZ; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2787) + return OPCODE_MOVLTZ; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2790) + return OPCODE_MOVNEZ; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2791) + return OPCODE_MUL16S; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2794) + return OPCODE_MUL16U; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2795) + return OPCODE_MULL; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2798) + return OPCODE_MULSH; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2799) + return OPCODE_MULUH; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2802) + return OPCODE_OR; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2803) + return OPCODE_SALT; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2806) + return OPCODE_SALTU; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2807) + return OPCODE_SRC; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2810) + return OPCODE_SUB; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2811) + return OPCODE_SUBX2; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2814) + return OPCODE_SUBX4; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2815) + return OPCODE_SUBX8; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2824 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 5) + return OPCODE_SLL; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2828 && + Field_fld_f3_s0_ldst_3_0_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2828 && + Field_fld_f3_s0_ldst_3_0_Slot_f3_s0_ldst_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2828 && + Field_fld_f3_s0_ldst_3_0_Slot_f3_s0_ldst_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get (insn) == 2828 && + Field_fld_f3_s0_ldst_3_0_Slot_f3_s0_ldst_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1252) + return OPCODE_IVP_LS2NX8_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1253) + return OPCODE_IVP_LS2NX8_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1254) + return OPCODE_IVP_LSNX16_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1255) + return OPCODE_IVP_LSNX16_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1264) + return OPCODE_IVP_LSNX8S_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1265) + return OPCODE_IVP_LSNX8S_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1266) + return OPCODE_IVP_LSN_2X16S_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1267) + return OPCODE_IVP_LSN_2X16S_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1268) + return OPCODE_IVP_LSN_2X32_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1269) + return OPCODE_IVP_LSN_2X32_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1270) + return OPCODE_IVP_LSR2NX8_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1271) + return OPCODE_IVP_LSR2NX8_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1272) + return OPCODE_IVP_LSRNX16_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1273) + return OPCODE_IVP_LSRNX16_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1274) + return OPCODE_IVP_LSRN_2X32_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1275) + return OPCODE_IVP_LSRN_2X32_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1276) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1277) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1278) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1279) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1281) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1283) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1285) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1287) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1289) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1291) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1293) + return OPCODE_IVP_SS2NX8_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1295) + return OPCODE_IVP_SS2NX8_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1297) + return OPCODE_IVP_SSNX16_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1299) + return OPCODE_IVP_SSNX16_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1301) + return OPCODE_IVP_SSNX8S_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1303) + return OPCODE_IVP_SSNX8S_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1305) + return OPCODE_IVP_SSN_2X16S_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1307) + return OPCODE_IVP_SSN_2X16S_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1309) + return OPCODE_IVP_SSN_2X32_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1311) + return OPCODE_IVP_SSN_2X32_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1313) + return OPCODE_IVP_SV2NX8_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1315) + return OPCODE_IVP_SV2NX8_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1317) + return OPCODE_IVP_SVNX8S_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1319) + return OPCODE_IVP_SVNX8S_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1321) + return OPCODE_IVP_SVNX8U_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1323) + return OPCODE_IVP_SVNX8U_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1325) + return OPCODE_IVP_SVN_2X16S_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1327) + return OPCODE_IVP_SVN_2X16S_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1329) + return OPCODE_IVP_SVN_2X16U_X; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1331) + return OPCODE_IVP_SVN_2X16U_XP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1333) + return OPCODE_SLLI; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1335) + return OPCODE_IVP_LS2NX8_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1337) + return OPCODE_IVP_LSNX16_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1339) + return OPCODE_IVP_LSNX8S_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1341) + return OPCODE_IVP_LSN_2X16S_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1343) + return OPCODE_IVP_LSN_2X32_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1345) + return OPCODE_IVP_LSR2NX8_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1347) + return OPCODE_IVP_LSRNX16_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1349) + return OPCODE_IVP_LSRN_2X32_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1351) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1353) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1355) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1357) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1359) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1361) + return OPCODE_IVP_SS2NX8_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1363) + return OPCODE_IVP_SSNX16_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1365) + return OPCODE_IVP_SSNX8S_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1367) + return OPCODE_IVP_SSN_2X16S_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1369) + return OPCODE_IVP_SSN_2X32_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1371) + return OPCODE_IVP_SV2NX8_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1373) + return OPCODE_IVP_SVNX8S_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1375) + return OPCODE_IVP_SVNX8U_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1377) + return OPCODE_IVP_SVN_2X16S_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1379) + return OPCODE_IVP_SVN_2X16U_IP; + if (Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get (insn) == 1381) + return OPCODE_SRAI; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 514 && + Field_fld_f3_s0_ldst_7_7_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 517 && + Field_fld_f3_s0_ldst_7_7_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 520 && + Field_fld_f3_s0_ldst_7_7_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 521 && + Field_fld_f3_s0_ldst_7_7_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 522 && + Field_fld_f3_s0_ldst_7_5_Slot_f3_s0_ldst_get (insn) == 6) + return OPCODE_IVP_SHFL2NX8I_S0; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 523 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 12) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 523 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 15) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 523 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 13) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 524 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 15) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 525 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 14) + return OPCODE_IVP_MOVVV; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 525 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 15) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 526 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 14) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 527 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 14) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 624) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 625) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 706 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get (insn) == 706 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 0) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 252) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 253) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 254) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 255) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 261 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 9) + return OPCODE_IVP_SANX8U_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 261 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 8) + return OPCODE_IVP_SANX8S_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 261 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 11) + return OPCODE_IVP_SAN_2X16U_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 261 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 10) + return OPCODE_IVP_SAN_2X16S_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 262 && + Field_fld_f3_s0_ldst_12_4_Slot_f3_s0_ldst_get (insn) == 269) + return OPCODE_IVP_LA_PP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 262 && + Field_fld_f3_s0_ldst_12_4_Slot_f3_s0_ldst_get (insn) == 285) + return OPCODE_IVP_SAPOS_FP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 262 && + Field_fld_f3_s0_ldst_12_11_Slot_f3_s0_ldst_get (insn) == 3 && + Field_fld_f3_s0_ldst_8_0_Slot_f3_s0_ldst_get (insn) == 208) + return OPCODE_IVP_MALIGN; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 262 && + Field_fld_f3_s0_ldst_12_0_Slot_f3_s0_ldst_get (insn) == 6353) + return OPCODE_IVP_ZALIGN; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 262 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 9) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 262 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 10) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 262 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 11) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 263 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 11) + return OPCODE_IVP_SA2NX8_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 263 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 9) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 263 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 10) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 288) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 289) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 290) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 291) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 292) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 293) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 294) + return OPCODE_IVP_SAV2NX8_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 295) + return OPCODE_IVP_SAVNX8S_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 296) + return OPCODE_IVP_SAVNX8U_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 297) + return OPCODE_IVP_SAVN_2X16S_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 298) + return OPCODE_IVP_SAVN_2X16U_XP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 299) + return OPCODE_IVP_LS2NX8_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 300) + return OPCODE_IVP_LSNX16_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 301) + return OPCODE_IVP_LSNX8S_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 302) + return OPCODE_IVP_LSN_2X16S_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 303) + return OPCODE_IVP_LSR2NX8_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 304) + return OPCODE_IVP_LSRNX16_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 305) + return OPCODE_IVP_LSRN_2X32_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 306) + return OPCODE_IVP_SS2NX8_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 307) + return OPCODE_IVP_SSNX16_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 308) + return OPCODE_IVP_SSNX8S_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 309) + return OPCODE_IVP_SSN_2X16S_I; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 315 && + Field_fld_f3_s0_ldst_12_8_Slot_f3_s0_ldst_get (insn) == 24) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get (insn) == 315 && + Field_fld_f3_s0_ldst_12_8_Slot_f3_s0_ldst_get (insn) == 25) + return OPCODE_IVP_SALIGN_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 86) + return OPCODE_ADDI; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 87) + return OPCODE_ADDMI; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 88) + return OPCODE_IVP_LV2NX8T_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 89) + return OPCODE_IVP_LV2NX8T_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 90) + return OPCODE_IVP_LVNX8ST_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 91) + return OPCODE_IVP_LVNX8ST_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 92) + return OPCODE_IVP_LVNX8UT_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 93) + return OPCODE_IVP_LVNX8UT_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 94) + return OPCODE_IVP_LVN_2X16ST_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 95) + return OPCODE_IVP_LVN_2X16ST_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 96) + return OPCODE_IVP_LVN_2X16UT_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 97) + return OPCODE_IVP_LVN_2X16UT_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 98) + return OPCODE_IVP_SV2NX8T_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 99) + return OPCODE_IVP_SV2NX8T_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 100) + return OPCODE_IVP_SVNX8ST_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 101) + return OPCODE_IVP_SVNX8ST_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 102) + return OPCODE_IVP_SVNX8UT_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 103) + return OPCODE_IVP_SVNX8UT_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 104) + return OPCODE_IVP_SVN_2X16ST_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 105) + return OPCODE_IVP_SVN_2X16ST_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 106) + return OPCODE_IVP_SVN_2X16UT_X; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 107) + return OPCODE_IVP_SVN_2X16UT_XP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 108) + return OPCODE_L16SI; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 109) + return OPCODE_L16UI; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 110) + return OPCODE_L32I; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 111) + return OPCODE_L8UI; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 112) + return OPCODE_S16I; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 113) + return OPCODE_S32I; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 114) + return OPCODE_S8I; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 115) + return OPCODE_IVP_LV2NX8T_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 116) + return OPCODE_IVP_LVNX8ST_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 117) + return OPCODE_IVP_LVNX8UT_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 118) + return OPCODE_IVP_LVN_2X16ST_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 119) + return OPCODE_IVP_LVN_2X16UT_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 120) + return OPCODE_IVP_SV2NX8T_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 121) + return OPCODE_IVP_SVNX8ST_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 122) + return OPCODE_IVP_SVNX8UT_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 123) + return OPCODE_IVP_SVN_2X16ST_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 124) + return OPCODE_IVP_SVN_2X16UT_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 125) + return OPCODE_MOVI; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 131 && + Field_fld_f3_s0_ldst_12_12_Slot_f3_s0_ldst_get (insn) == 0 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 13) + return OPCODE_IVP_SBN_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 131 && + Field_fld_f3_s0_ldst_12_12_Slot_f3_s0_ldst_get (insn) == 1 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 12) + return OPCODE_IVP_SBN_2_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 131 && + Field_fld_f3_s0_ldst_12_12_Slot_f3_s0_ldst_get (insn) == 0 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 12) + return OPCODE_IVP_SB2N_IP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 131 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 8) + return OPCODE_LOOPNEZ; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 140 && + Field_fld_f3_s0_ldst_7_5_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SB2N_I; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 141 && + Field_fld_f3_s0_ldst_7_5_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SBN_2_I; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 142 && + Field_fld_f3_s0_ldst_7_5_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SBN_I; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 143 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 2) + return OPCODE_LOOP; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 143 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 3) + return OPCODE_LOOPGTZ; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 157 && + Field_fld_f3_s0_ldst_12_11_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_GATHERANX8UT; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 157 && + Field_fld_f3_s0_ldst_12_11_Slot_f3_s0_ldst_get (insn) == 0) + return OPCODE_IVP_GATHERANX16T; + if (Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get (insn) == 157 && + Field_fld_f3_s0_ldst_12_11_Slot_f3_s0_ldst_get (insn) == 2) + return OPCODE_IVP_GATHERAN_2X32T; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 30) + return OPCODE_IVP_LSN_2X32_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 31) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 32) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 33) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 34) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 35) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 36) + return OPCODE_IVP_SSN_2X32_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 37) + return OPCODE_IVP_SV2NX8_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 38) + return OPCODE_IVP_SVNX8S_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 39) + return OPCODE_IVP_SVNX8U_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 40) + return OPCODE_IVP_SVN_2X16S_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 41) + return OPCODE_IVP_SVN_2X16U_I; + if (Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get (insn) == 42) + return OPCODE_EXTUI; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 4) + return OPCODE_IVP_LV2NX8T_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 5) + return OPCODE_IVP_LVNX8ST_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 6) + return OPCODE_IVP_LVNX8UT_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 7) + return OPCODE_IVP_LVN_2X16ST_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 8) + return OPCODE_IVP_LVN_2X16UT_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 9) + return OPCODE_IVP_SV2NX8T_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 10) + return OPCODE_IVP_SVNX8ST_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 11) + return OPCODE_IVP_SVNX8UT_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 12) + return OPCODE_IVP_SVN_2X16ST_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 13) + return OPCODE_IVP_SVN_2X16UT_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 14) + return OPCODE_J; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 34 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 2) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 34 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 42 && + Field_fld_f3_s0_ldst_13_9_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 44 && + Field_fld_f3_s0_ldst_15_15_Slot_f3_s0_ldst_get (insn) == 0 && + Field_fld_f3_s0_ldst_12_8_Slot_f3_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get (insn) == 44 && + Field_fld_f3_s0_ldst_15_15_Slot_f3_s0_ldst_get (insn) == 0 && + Field_fld_f3_s0_ldst_12_8_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SALIGN_I; + if (Field_fld_f3_s0_ldst_25_19_Slot_f3_s0_ldst_get (insn) == 16 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 2) + return OPCODE_IVP_REPNX16; + if (Field_fld_f3_s0_ldst_25_19_Slot_f3_s0_ldst_get (insn) == 16 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f3_s0_ldst_25_19_Slot_f3_s0_ldst_get (insn) == 20 && + Field_fld_f3_s0_ldst_13_9_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f3_s0_ldst_25_20_Slot_f3_s0_ldst_get (insn) == 0) + return OPCODE_CONST16; + if (Field_fld_f3_s0_ldst_25_20_Slot_f3_s0_ldst_get (insn) == 8 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 0) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f3_s0_ldst_25_20_Slot_f3_s0_ldst_get (insn) == 8 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f3_s0_ldst_25_20_Slot_f3_s0_ldst_get (insn) == 10 && + Field_fld_f3_s0_ldst_13_9_Slot_f3_s0_ldst_get (insn) == 0) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f3_s0_ldst_25_4_Slot_f3_s0_ldst_get (insn) == 723621) + return OPCODE_SSA8L; + if (Field_fld_f3_s0_ldst_25_4_Slot_f3_s0_ldst_get (insn) == 723637) + return OPCODE_SSL; + if (Field_fld_f3_s0_ldst_25_4_Slot_f3_s0_ldst_get (insn) == 723653) + return OPCODE_SSR; + if (Field_fld_f3_s0_ldst_25_8_Slot_f3_s0_ldst_get (insn) == 40316) + return OPCODE_NSA; + if (Field_fld_f3_s0_ldst_25_8_Slot_f3_s0_ldst_get (insn) == 40317) + return OPCODE_NSAU; + if (Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_get (insn) == 20156) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_get (insn) == 20173) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_get (insn) == 20189) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_get (insn) == 20205) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_get (insn) == 20221) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_get (insn) == 22612 && + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get (insn) == 5) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_f3_s3_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f3_s3_alu_28_12_Slot_f3_s3_alu_get (insn) == 38924 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_EXTBI2NX8; + if (Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_get (insn) == 19457) + return OPCODE_IVP_EXTRVRN_2X32; + if (Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_get (insn) == 19463 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 8) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_get (insn) == 19463 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 11) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_get (insn) == 19463 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 9) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_get (insn) == 19463 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 12) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_get (insn) == 19463 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 10) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9236 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LTNX16; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9237 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9238 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9239 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9268 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9269 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9270 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9271 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9729 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9730 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9761 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9793 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LENX16; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9825 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9857 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9889 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9921 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9921 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9953 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_EQNX16; + if (Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get (insn) == 9953 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 264) + return OPCODE_IVP_COUNTEQ4NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 265) + return OPCODE_IVP_COUNTEQZ4NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 266) + return OPCODE_IVP_COUNTLE4NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 267) + return OPCODE_IVP_COUNTLEZ4NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 268 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 268 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 269 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 269 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 270 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 270 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 271 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 271 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 280 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 13) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 280 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 15) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 280 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 11) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 281 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 14) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 281 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 11) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 281 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 13) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 281 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 15) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 282 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 11) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 282 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 15) + return OPCODE_IVP_MINNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 282 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 12) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 283 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 15) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 283 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 11) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 283 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 13) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 284 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 12) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 284 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 14) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 284 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 11) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 284 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 13) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 284 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 15) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 285 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 11) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 285 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 13) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 285 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 15) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 285 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 14) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 285 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 12) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 286 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 14) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 286 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 13) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 286 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 12) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 286 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 11) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 287 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 11) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 288 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 289 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 290 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 291 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 292 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 293 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 294 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 7) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 294 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 5) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 294 && + Field_fld_f3_s3_alu_3_2_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_SHFL2NX8I; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 294 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 6) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 294 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 295 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 295 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 4) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 295 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 2) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 295 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 5) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 295 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 295 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 295 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 3) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 296 && + Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_get (insn) == 1 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 14) + return OPCODE_IVP_SLLINX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 296 && + Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_get (insn) == 0 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 15) + return OPCODE_IVP_SLSINX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 296 && + Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_get (insn) == 1 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 15) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 296 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 8) + return OPCODE_IVP_SRSNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 296 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 9) + return OPCODE_IVP_SRSN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 296 && + Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_get (insn) == 0 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 14) + return OPCODE_IVP_ROTRINX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 457) + return OPCODE_IVP_MOVVV; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_get (insn) == 0 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 8) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 489) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 473) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 201) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 249) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_7_6_Slot_f3_s3_alu_get (insn) == 2 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 8) + return OPCODE_IVP_ROTRI2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_7_6_Slot_f3_s3_alu_get (insn) == 3 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 8) + return OPCODE_IVP_SLLI2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_7_6_Slot_f3_s3_alu_get (insn) == 0 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 9) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_7_6_Slot_f3_s3_alu_get (insn) == 1 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 9) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 217) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 297 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 409) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 298 && + Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_get (insn) == 4) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 298 && + Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_get (insn) == 6) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 298 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 2 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_RBMINNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 298 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 0 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_RBMAXNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 298 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 3 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_RBMINUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 298 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 1 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_RBMAXUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 299 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 35) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 299 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 38) + return OPCODE_IVP_NSANX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 299 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 48) + return OPCODE_IVP_NSAUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 299 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 34) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 299 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 32) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 299 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 39) + return OPCODE_IVP_NSAN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 299 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 49) + return OPCODE_IVP_NSAUN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 301 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 7) + return OPCODE_IVP_ROTRIN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 302 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 5) + return OPCODE_IVP_SLLNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 302 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 2) + return OPCODE_IVP_SLANX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 302 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 4) + return OPCODE_IVP_SLLIN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 302 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 7) + return OPCODE_IVP_SLSIN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 302 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 6) + return OPCODE_IVP_SLLN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 302 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 3) + return OPCODE_IVP_SLAN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 302 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_ROTRNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 302 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_ROTRN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 303 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 6) + return OPCODE_IVP_SRLNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 303 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 3) + return OPCODE_IVP_SRANX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 303 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_SLSNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 303 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 2) + return OPCODE_IVP_SRAIN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 303 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 5) + return OPCODE_IVP_SRLIN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 303 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 7) + return OPCODE_IVP_SRLN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 303 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 4) + return OPCODE_IVP_SRAN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 303 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_SLSN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 312 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 20 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 312 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 21 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 312 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 23 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDU2NX8; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 312 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 22 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDSNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 313 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 21 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 313 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 23 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 313 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 22 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 313 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 20 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 314 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 21 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 314 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 23 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINUNX16; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 314 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 22 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 314 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 20 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXUN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 315 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 20 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINUN_2X32; + if (Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get (insn) == 319 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 19 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADD2NX8; + if (Field_fld_f3_s3_alu_28_20_Slot_f3_s3_alu_get (insn) == 148 && + Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_get (insn) == 4) + return OPCODE_IVP_REPNX16; + if (Field_fld_f3_s3_alu_28_20_Slot_f3_s3_alu_get (insn) == 148 && + Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_get (insn) == 6) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f3_s3_alu_28_20_Slot_f3_s3_alu_get (insn) == 154 && + Field_fld_f3_s3_alu_18_14_Slot_f3_s3_alu_get (insn) == 1 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f3_s3_alu_28_21_Slot_f3_s3_alu_get (insn) == 74 && + Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f3_s3_alu_28_21_Slot_f3_s3_alu_get (insn) == 74 && + Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_get (insn) == 2) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f3_s3_alu_28_21_Slot_f3_s3_alu_get (insn) == 76 && + Field_fld_f3_s3_alu_18_14_Slot_f3_s3_alu_get (insn) == 1 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 32) + return OPCODE_IVP_SEL2NX8I; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 34 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 34 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 6) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 34 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 12) + return OPCODE_IVP_MINNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 34 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 9) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 34 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 15) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 34 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 3) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 34 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 2) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 34 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 35 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 35 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 2) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 35 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 4) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 35 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 3) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 35 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_7_Slot_f3_s3_alu_get (insn) == 512 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8215) + return OPCODE_IVP_NOTB; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8213) + return OPCODE_IVP_MB; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_8_Slot_f3_s3_alu_get (insn) == 257 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 8) + return OPCODE_IVP_MOVBRBV; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8211) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8209) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8217) + return OPCODE_IVP_NOTB1; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8219) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8257) + return OPCODE_IVP_RORB2N; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8221) + return OPCODE_IVP_RANDBN; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8259) + return OPCODE_IVP_RORBN; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8223) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get (insn) == 8261) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 38 && + Field_fld_f3_s3_alu_18_13_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 9 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 14 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 16 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 15 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXUNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 17 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINUNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 257) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get (insn) == 305) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 10 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDN_2X32T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_18_12_Slot_f3_s3_alu_get (insn) == 3 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_INJBI2NX8; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 8 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADD2NX8T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 13 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDUNX16T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 12 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDU2NX8T; + if (Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get (insn) == 39 && + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get (insn) == 11 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDSNX16T; + if (Field_fld_f3_s3_alu_28_25_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_COUNTEQM4NX8; + if (Field_fld_f3_s3_alu_28_25_Slot_f3_s3_alu_get (insn) == 1) + return OPCODE_IVP_COUNTEQMZ4NX8; + if (Field_fld_f3_s3_alu_28_25_Slot_f3_s3_alu_get (insn) == 2) + return OPCODE_IVP_COUNTLEM4NX8; + if (Field_fld_f3_s3_alu_28_25_Slot_f3_s3_alu_get (insn) == 3) + return OPCODE_IVP_COUNTLEMZ4NX8; + if (Field_fld_f3_s3_alu_28_4_Slot_f3_s3_alu_get (insn) == 9965603 && + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get (insn) == 8) + return OPCODE_NOP; + if (Field_fld_f3_s3_alu_28_8_Slot_f3_s3_alu_get (insn) == 624672) + return OPCODE_MOV_N; + if (Field_fld_f3_s3_alu_28_9_Slot_f3_s3_alu_get (insn) == 312337 && + Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_get (insn) == 0 && + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get (insn) == 0) + return OPCODE_IVP_MOVBVBR; + return XTENSA_UNDEFINED; +} + +static int +Slot_f4_s3_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_get (insn) == 57351) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_get (insn) == 57479) + return OPCODE_IVP_EXTRVRN_2X32; + if (Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_get (insn) == 57607 && + Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_get (insn) == 57607 && + Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_get (insn) == 57607 && + Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_get (insn) == 57735 && + Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_get (insn) == 57735 && + Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f4_s3_alu_31_19_Slot_f4_s3_alu_get (insn) == 972 && + Field_fld_f4_s3_alu_14_6_Slot_f4_s3_alu_get (insn) == 440 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 7) + return OPCODE_IVP_MOVBVBR; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 448 && + Field_fld_f4_s3_alu_14_14_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_COUNTEQ4NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 449 && + Field_fld_f4_s3_alu_14_14_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_COUNTLE4NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 449 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 23) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 449 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 22) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 451 && + Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 451 && + Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 480 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 29) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 480 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 26) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 480 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 28) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 480 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 25) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 480 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 27) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 480 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 480 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 480 && + Field_fld_f4_s3_alu_14_14_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_COUNTEQZ4NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 480 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 24) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31) + return OPCODE_IVP_MINNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 25) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 28) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 24) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 27) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 26) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 29) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 23) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 22) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 481 && + Field_fld_f4_s3_alu_14_14_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_COUNTLEZ4NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 482 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 482 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 26) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 482 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 28) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 482 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 25) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 482 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 482 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 24) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 482 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 27) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 482 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 29) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 28) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 25) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 27) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 9 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RADDNX16T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 24) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 10 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RADDN_2X32T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 29) + return OPCODE_IVP_ROTRIN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30) + return OPCODE_IVP_ROTRNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31) + return OPCODE_IVP_ROTRN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 26) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 8 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RADD2NX8T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 483 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 11 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RADDSNX16T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 484 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 27) + return OPCODE_IVP_SLLNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 484 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 24) + return OPCODE_IVP_SLANX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 484 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30) + return OPCODE_IVP_SLSNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 484 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 26) + return OPCODE_IVP_SLLIN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 484 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 29) + return OPCODE_IVP_SLSIN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 484 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 28) + return OPCODE_IVP_SLLN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 484 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 25) + return OPCODE_IVP_SLAN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 484 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31) + return OPCODE_IVP_SLSN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 485 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 28) + return OPCODE_IVP_SRLNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 485 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 25) + return OPCODE_IVP_SRANX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 485 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30) + return OPCODE_IVP_SRSNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 485 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 24) + return OPCODE_IVP_SRAIN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 485 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 27) + return OPCODE_IVP_SRLIN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 485 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 29) + return OPCODE_IVP_SRLN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 485 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 26) + return OPCODE_IVP_SRAN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 485 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31) + return OPCODE_IVP_SRSN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 108 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 5) + return OPCODE_IVP_MOVVV; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 24 && + Field_fld_f4_s3_alu_3_3_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_SLLINX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 25 && + Field_fld_f4_s3_alu_3_3_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_SLSINX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 25 && + Field_fld_f4_s3_alu_3_3_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 26 && + Field_fld_f4_s3_alu_3_3_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 109 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 6) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 110 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 5) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 110 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 6) + return OPCODE_IVP_NSANX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 108 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 7) + return OPCODE_IVP_NSAUNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 5 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 6 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 6 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMINNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMAXUNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMINUNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 14 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 4) + return OPCODE_IVP_RBMINNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 14 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_RBMAXNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 108 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 6) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 14 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 6) + return OPCODE_IVP_RMAXNX16T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 15 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINNX16T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 14 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 7) + return OPCODE_IVP_RMAXUNX16T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 15 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMINUNX16T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 14 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 5) + return OPCODE_IVP_RBMINUNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 14 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_RBMAXUNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 109 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 5) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 6 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMINN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 5 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMAXUN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 5 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RMINUN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 108 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 110 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 26 && + Field_fld_f4_s3_alu_3_2_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_ROTRI2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 24 && + Field_fld_f4_s3_alu_3_3_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_ROTRINX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 111 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 5) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 111 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 6) + return OPCODE_IVP_NSAN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 109 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 7) + return OPCODE_IVP_NSAUN_2X32; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 26 && + Field_fld_f4_s3_alu_3_2_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_SLLI2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 27 && + Field_fld_f4_s3_alu_3_2_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 27 && + Field_fld_f4_s3_alu_3_2_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADD2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 5 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDUNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 14 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_RADDUNX16T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 31 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDU2NX8; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 14 && + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDU2NX8T; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get (insn) == 30 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDSNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 109 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get (insn) == 486 && + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get (insn) == 111 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 4) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_get (insn) == 56 && + Field_fld_f4_s3_alu_19_6_Slot_f4_s3_alu_get (insn) == 1411 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_NOTB; + if (Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_get (insn) == 56 && + Field_fld_f4_s3_alu_19_6_Slot_f4_s3_alu_get (insn) == 1410 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_MB; + if (Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_get (insn) == 56 && + Field_fld_f4_s3_alu_19_8_Slot_f4_s3_alu_get (insn) == 352 && + Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_MOVBRBV; + if (Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_get (insn) == 56 && + Field_fld_f4_s3_alu_19_6_Slot_f4_s3_alu_get (insn) == 1409 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_get (insn) == 56 && + Field_fld_f4_s3_alu_19_6_Slot_f4_s3_alu_get (insn) == 1408 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_get (insn) == 56 && + Field_fld_f4_s3_alu_19_6_Slot_f4_s3_alu_get (insn) == 1920 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_NOTB1; + if (Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_get (insn) == 56 && + Field_fld_f4_s3_alu_19_13_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_ADDI; + if (Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get (insn) == 8) + return OPCODE_IVP_COUNTEQM4NX8; + if (Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get (insn) == 9) + return OPCODE_IVP_COUNTEQMZ4NX8; + if (Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get (insn) == 10) + return OPCODE_IVP_COUNTLEM4NX8; + if (Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get (insn) == 11) + return OPCODE_IVP_COUNTLEMZ4NX8; + if (Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get (insn) == 12) + return OPCODE_IVP_DSELNX16; + if (Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get (insn) == 13 && + Field_fld_f4_s3_alu_14_14_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_DSEL2NX8I; + if (Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get (insn) == 13 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 4) + return OPCODE_IVP_DSEL2NX8I_H; + if (Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get (insn) == 13 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 5) + return OPCODE_IVP_SEL2NX8I; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_REPNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_21_Slot_f4_s3_alu_get (insn) == 1 && + Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_21_Slot_f4_s3_alu_get (insn) == 1 && + Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1060) + return OPCODE_IVP_LTNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1045) + return OPCODE_IVP_LENX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1293) + return OPCODE_IVP_EQNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1077) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1084) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1308) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 3 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 6 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 0 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 4) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 6 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_9_8_Slot_f4_s3_alu_get (insn) == 0 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 5 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 6 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_MINNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 5 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 6 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 3 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 1 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 4) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 6 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_9_8_Slot_f4_s3_alu_get (insn) == 1 && + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_13_Slot_f4_s3_alu_get (insn) == 518) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 5 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 3 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 6 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 1) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 5 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 3 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 0 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 5) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1309) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1052) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1292) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1069) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1076) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1300) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1068) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1053) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1044) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1085) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1061) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get (insn) == 1301) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_18_Slot_f4_s3_alu_get (insn) == 17 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 0 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_INJBI2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_18_Slot_f4_s3_alu_get (insn) == 17 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get (insn) == 1 && + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTBI2NX8; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 1 && + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get (insn) == 10) + return OPCODE_IVP_SHFL2NX8I; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get (insn) == 4 && + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get (insn) == 3) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get (insn) == 7 && + Field_fld_f4_s3_alu_24_21_Slot_f4_s3_alu_get (insn) == 2 && + Field_fld_f4_s3_alu_19_13_Slot_f4_s3_alu_get (insn) == 2) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f4_s3_alu_31_28_Slot_f4_s3_alu_get (insn) == 0) + return OPCODE_IVP_DSELNX16T; + if (Field_fld_f4_s3_alu_31_7_Slot_f4_s3_alu_get (insn) == 3670976 && + Field_fld_f4_s3_alu_6_0_Slot_f4_s3_alu_get (insn) == 66) + return OPCODE_NOP; + if (Field_fld_f4_s3_alu_31_8_Slot_f4_s3_alu_get (insn) == 1851616) + return OPCODE_MOV_N; + return XTENSA_UNDEFINED; +} + +static int +Slot_f11_s3_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f11_s3_alu_25_1_Slot_f11_s3_alu_get (insn) == 7084145 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_NOP; + if (Field_fld_f11_s3_alu_25_11_Slot_f11_s3_alu_get (insn) == 6648 && + Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_get (insn) == 13) + return OPCODE_IVP_MOVBRBV; + if (Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_get (insn) == 1662 && + Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_get (insn) == 1662 && + Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_get (insn) == 7) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_get (insn) == 1662 && + Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_get (insn) == 3) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_get (insn) == 1662 && + Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_get (insn) == 9) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_get (insn) == 1662 && + Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_get (insn) == 5) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_get (insn) == 1684) + return OPCODE_IVP_EXTRVRN_2X32; + if (Field_fld_f11_s3_alu_25_14_Slot_f11_s3_alu_get (insn) == 830 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 1) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f11_s3_alu_25_14_Slot_f11_s3_alu_get (insn) == 838) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_f11_s3_alu_25_14_Slot_f11_s3_alu_get (insn) == 839) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 354) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 355) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 356) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 357) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 358) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 359) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 360) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 361) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 362) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 363) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 364) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 365) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 366) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 367) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 368) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 369) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 370) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 371) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 372) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 373) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 374) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 375) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 376) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 377) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 378) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 379) + return OPCODE_IVP_MINNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 380) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 381) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 382) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 383) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 384) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 385) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 386) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 387) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 388) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 389) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 390) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 391) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 392) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 393) + return OPCODE_IVP_ROTRIN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 394) + return OPCODE_IVP_ROTRNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 395) + return OPCODE_IVP_ROTRN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 396) + return OPCODE_IVP_SLANX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 397) + return OPCODE_IVP_SLAN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 398) + return OPCODE_IVP_SLLIN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 399) + return OPCODE_IVP_SLLNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 400) + return OPCODE_IVP_SLLN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 401) + return OPCODE_IVP_SLSIN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 402) + return OPCODE_IVP_SLSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 403) + return OPCODE_IVP_SLSN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 404) + return OPCODE_IVP_SRAIN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 405) + return OPCODE_IVP_SRANX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 406) + return OPCODE_IVP_SRAN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 407) + return OPCODE_IVP_SRLIN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 408) + return OPCODE_IVP_SRLNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 409) + return OPCODE_IVP_SRLN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 410) + return OPCODE_IVP_SRSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 411) + return OPCODE_IVP_SRSN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 412) + return OPCODE_IVP_REPNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 413) + return OPCODE_IVP_SELSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 414 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 1) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 416 && + Field_fld_f11_s3_alu_9_9_Slot_f11_s3_alu_get (insn) == 1) + return OPCODE_IVP_SLLINX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 416 && + Field_fld_f11_s3_alu_9_9_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_ROTRINX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 417 && + Field_fld_f11_s3_alu_9_9_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_SLSINX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 417 && + Field_fld_f11_s3_alu_9_9_Slot_f11_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRAINX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 418 && + Field_fld_f11_s3_alu_9_9_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRLINX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 418 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 2) + return OPCODE_IVP_ROTRI2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 418 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 3) + return OPCODE_IVP_SLLI2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 2) + return OPCODE_IVP_MOVVV; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 3 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 4) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 3) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 5) + return OPCODE_IVP_NSANX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 6) + return OPCODE_IVP_NSAUNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 4) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 3 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 2) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 1) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 3 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 3) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 3 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 5) + return OPCODE_IVP_NSAN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 3 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 6) + return OPCODE_IVP_NSAUN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 3 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 420 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 3 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 1) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 422 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 1 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 422 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 0 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXUNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 422 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINUNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 423 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 1 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 423 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 0 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXUN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 423 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINUN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 432 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 15 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADD2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 433 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 15 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 434 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 15 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDN_2X32; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 435 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 15 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDSNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 436 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 15 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDU2NX8; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 437 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 15 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDUNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 438 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 15 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXNX16; + if (Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get (insn) == 439 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 15 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXN_2X32; + if (Field_fld_f11_s3_alu_25_16_Slot_f11_s3_alu_get (insn) == 174) + return OPCODE_IVP_REP2NX8; + if (Field_fld_f11_s3_alu_25_16_Slot_f11_s3_alu_get (insn) == 175) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_f11_s3_alu_25_16_Slot_f11_s3_alu_get (insn) == 176) + return OPCODE_ADDI; + if (Field_fld_f11_s3_alu_25_16_Slot_f11_s3_alu_get (insn) == 207 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f11_s3_alu_25_17_Slot_f11_s3_alu_get (insn) == 86) + return OPCODE_IVP_SHFL2NX8I; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 16) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 17) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 18) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 19) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 20) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 21) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 22) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 23) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 24) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 25) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 26) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 27) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 28) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 29) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 30) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 31) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 32) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 33) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 34) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 35) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 36) + return OPCODE_IVP_MINNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 37) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 38) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 39) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 40) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 41) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 42) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 10) + return OPCODE_IVP_LTNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 4) + return OPCODE_IVP_LENX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 1) + return OPCODE_IVP_EQNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 16) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 13) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 7) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 9) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 3) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 15) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 12) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 6) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 11) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 5) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 2) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 17) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 14) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 53 && + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get (insn) == 8) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 4 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 14 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 5 && + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (insn) == 226) + return OPCODE_IVP_NOTB; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 5 && + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (insn) == 224) + return OPCODE_IVP_MB; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 8 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RBMINNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 6 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RBMAXNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 1 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 10 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 12 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 11 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMAXUNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 13 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RMINUNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 5 && + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (insn) == 228) + return OPCODE_IVP_NOTB1; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 9 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RBMINUNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 7 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RBMAXUNX16; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDN_2X32T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_13_Slot_f11_s3_alu_get (insn) == 0 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 14 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTBI2NX8; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 0 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADD2NX8T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 5 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDUNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 4 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDU2NX8T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get (insn) == 3 && + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_RADDSNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 5 && + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (insn) == 230) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 5 && + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (insn) == 236) + return OPCODE_IVP_RORB2N; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 5 && + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (insn) == 232) + return OPCODE_IVP_RANDBN; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 5 && + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (insn) == 238) + return OPCODE_IVP_RORBN; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 5 && + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (insn) == 234) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 54 && + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get (insn) == 6 && + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get (insn) == 224) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 55 && + Field_fld_f11_s3_alu_14_8_Slot_f11_s3_alu_get (insn) == 2 && + Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_MOVBVBR; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 55 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 0 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get (insn) == 55 && + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get (insn) == 1 && + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_f11_s3_alu_25_22_Slot_f11_s3_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8I; + if (Field_fld_f11_s3_alu_25_8_Slot_f11_s3_alu_get (insn) == 53920) + return OPCODE_MOV_N; + return XTENSA_UNDEFINED; +} + +static int +Slot_n0_s3_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8976) + return OPCODE_ADD; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8977) + return OPCODE_ADDX2; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8978) + return OPCODE_ADDX4; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8979) + return OPCODE_ADDX8; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8980) + return OPCODE_AND; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8981) + return OPCODE_OR; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8982) + return OPCODE_SUB; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8983) + return OPCODE_SUBX2; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8984) + return OPCODE_SUBX4; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8985) + return OPCODE_SUBX8; + if (Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get (insn) == 8986) + return OPCODE_XOR; + if (Field_fld_n0_s3_alu_27_13_Slot_n0_s3_alu_get (insn) == 8004 && + Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVBRBV; + if (Field_fld_n0_s3_alu_27_15_Slot_n0_s3_alu_get (insn) == 1809 && + Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAV16; + if (Field_fld_n0_s3_alu_27_15_Slot_n0_s3_alu_get (insn) == 1841 && + Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAV32; + if (Field_fld_n0_s3_alu_27_15_Slot_n0_s3_alu_get (insn) == 1873 && + Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAV8; + if (Field_fld_n0_s3_alu_27_15_Slot_n0_s3_alu_get (insn) == 1905 && + Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_n0_s3_alu_27_15_Slot_n0_s3_alu_get (insn) == 1937 && + Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_n0_s3_alu_27_16_Slot_n0_s3_alu_get (insn) == 560) + return OPCODE_ADDI; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 32) + return OPCODE_IVP_SEL2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 33) + return OPCODE_IVP_SELNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 34) + return OPCODE_IVP_SELN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 36 && + Field_fld_n0_s3_alu_14_14_Slot_n0_s3_alu_get (insn) == 1 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 10) + return OPCODE_IVP_SLLINX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 36 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRSNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 36 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRAN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 36 && + Field_fld_n0_s3_alu_14_14_Slot_n0_s3_alu_get (insn) == 0 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 10) + return OPCODE_IVP_ROTRINX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 37 && + Field_fld_n0_s3_alu_14_14_Slot_n0_s3_alu_get (insn) == 0 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 10) + return OPCODE_IVP_SLSINX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 37 && + Field_fld_n0_s3_alu_14_14_Slot_n0_s3_alu_get (insn) == 1 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 10) + return OPCODE_IVP_SRAINX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 37 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRLIN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 37 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SRSN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 38 && + Field_fld_n0_s3_alu_14_14_Slot_n0_s3_alu_get (insn) == 0 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 10) + return OPCODE_IVP_SRLINX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 38 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRLNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 38 && + Field_fld_n0_s3_alu_14_13_Slot_n0_s3_alu_get (insn) == 2 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 10) + return OPCODE_IVP_ROTRI2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 38 && + Field_fld_n0_s3_alu_14_13_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 10) + return OPCODE_IVP_SLLI2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 906) + return OPCODE_IVP_MOVVV; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 970) + return OPCODE_IVP_NEGNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 938) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SRLN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 650) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 746) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_14_13_Slot_n0_s3_alu_get (insn) == 0 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 10) + return OPCODE_IVP_SRAI2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_14_13_Slot_n0_s3_alu_get (insn) == 1 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 10) + return OPCODE_IVP_SRLI2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 682) + return OPCODE_IVP_ABSNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 39 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 810) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 28) + return OPCODE_IVP_MINUNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 453) + return OPCODE_IVP_RMINNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 455) + return OPCODE_IVP_RMINUNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 23) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 31) + return OPCODE_IVP_SLLIN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 454) + return OPCODE_IVP_RMINN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 452) + return OPCODE_IVP_RMAXUN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 468) + return OPCODE_IVP_RMINUN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 29) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 21) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 40 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 20) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 41 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 31) + return OPCODE_IVP_SLLNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 41 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 22) + return OPCODE_IVP_MAXNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 41 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 29) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 41 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 20) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 41 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 28) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 41 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 21) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 42 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 29) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 42 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 20) + return OPCODE_IVP_ADDNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 42 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 28) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 42 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 31) + return OPCODE_IVP_SLLN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 42 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 21) + return OPCODE_IVP_AVGRU2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 43 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 23) + return OPCODE_IVP_MINNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 43 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 31) + return OPCODE_IVP_SLSIN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 43 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 30) + return OPCODE_IVP_ROTRIN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 43 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 20) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 43 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 22) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 43 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 28) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 43 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 439) + return OPCODE_IVP_RADD2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 43 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 21) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 44 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 31) + return OPCODE_IVP_SLSNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 44 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 438) + return OPCODE_IVP_RADDNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 44 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 20) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 44 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 439) + return OPCODE_IVP_RADDN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 44 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 28) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 44 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 30) + return OPCODE_IVP_ROTRNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 44 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 21) + return OPCODE_IVP_AVGU2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 44 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 7) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 20) + return OPCODE_IVP_AND2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 28) + return OPCODE_IVP_OR2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 22) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 31) + return OPCODE_IVP_SLSN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 30) + return OPCODE_IVP_ROTRN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 23) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 7) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 439) + return OPCODE_IVP_RADDU2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 438) + return OPCODE_IVP_RADDSNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 45 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 21) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 46 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 30) + return OPCODE_IVP_SLANX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 46 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 22) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 46 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 439) + return OPCODE_IVP_RMAXNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 46 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 28) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 46 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 21) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 46 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 31) + return OPCODE_IVP_SRAIN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 46 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 438) + return OPCODE_IVP_RADDUNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 46 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 20) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 46 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 7) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 47 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 31) + return OPCODE_IVP_SRANX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 47 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 28) + return OPCODE_IVP_SUBNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 47 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 439) + return OPCODE_IVP_RMAXUNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 47 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 23) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 47 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 30) + return OPCODE_IVP_SLAN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 47 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 438) + return OPCODE_IVP_RMAXN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 47 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 22) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 47 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 7) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 47 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 20) + return OPCODE_IVP_AVGNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 120) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 113) + return OPCODE_IVP_NSANX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 98) + return OPCODE_IVP_NSAUNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 112) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_10_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SHFLNX16; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_10_Slot_n0_s3_alu_get (insn) == 2) + return OPCODE_IVP_SHFLN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 96) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 121) + return OPCODE_IVP_NSAN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 106) + return OPCODE_IVP_NSAUN_2X32; + if (Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get (insn) == 48 && + Field_fld_n0_s3_alu_14_10_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SHFL2NX8; + if (Field_fld_n0_s3_alu_27_22_Slot_n0_s3_alu_get (insn) == 10 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 7) + return OPCODE_IVP_SHFL2NX8I; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SELNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 2) + return OPCODE_IVP_SELN_2X32T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 26) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 28) + return OPCODE_IVP_BMINNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 17) + return OPCODE_IVP_ADDNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 19) + return OPCODE_IVP_ADDSNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 21) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 31) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 25) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 23) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 20) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 30) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 27) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 29) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 22) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 18) + return OPCODE_IVP_ADDN_2X32T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 16) + return OPCODE_IVP_ADD2NX8T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_9_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8I; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 24) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_6_Slot_n0_s3_alu_get (insn) == 6 && + Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_get (insn) == 2) + return OPCODE_IVP_REPNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_6_Slot_n0_s3_alu_get (insn) == 6 && + Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SELSNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_7_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_REP2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_7_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_SELS2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 14 && + Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_get (insn) == 2) + return OPCODE_IVP_REPN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 14 && + Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_get (insn) == 3) + return OPCODE_IVP_SELSN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 407) + return OPCODE_IVP_RBMINNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 405) + return OPCODE_IVP_RBMAXNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 26) + return OPCODE_IVP_MOV2NX8T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 388) + return OPCODE_IVP_RADDNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 421) + return OPCODE_IVP_RMAXNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 423) + return OPCODE_IVP_RMINNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 422) + return OPCODE_IVP_RMAXUNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 436) + return OPCODE_IVP_RMINUNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 4) + return OPCODE_IVP_SUBNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 8) + return OPCODE_IVP_MAXNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 18) + return OPCODE_IVP_MINNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 11) + return OPCODE_IVP_MAXUNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 25) + return OPCODE_IVP_MINUNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 6) + return OPCODE_IVP_SUBSNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 420) + return OPCODE_IVP_RBMINUNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 406) + return OPCODE_IVP_RBMAXUNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 5) + return OPCODE_IVP_SUBN_2X32T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 27) + return OPCODE_IVP_SUB2NX8T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 389) + return OPCODE_IVP_RADDN_2X32T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 499) + return OPCODE_IVP_RADD2NX8T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 404) + return OPCODE_IVP_RADDUNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 391) + return OPCODE_IVP_RADDU2NX8T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 390) + return OPCODE_IVP_RADDSNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_13_Slot_n0_s3_alu_get (insn) == 0 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 641) + return OPCODE_IVP_MB; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_12_Slot_n0_s3_alu_get (insn) == 0 && + Field_fld_n0_s3_alu_7_0_Slot_n0_s3_alu_get (insn) == 128) + return OPCODE_IVP_MOVBVBR; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 4 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_LTNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 2 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_LENX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 1 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 3) + return OPCODE_IVP_EQNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 6 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEQNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_LTUNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 2) + return OPCODE_IVP_LEUNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 136) + return OPCODE_IVP_NEGNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get (insn) == 232) + return OPCODE_IVP_NEGSNX16T; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_13_Slot_n0_s3_alu_get (insn) == 0 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 385) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_13_Slot_n0_s3_alu_get (insn) == 0 && + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get (insn) == 129) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 1 && + Field_fld_n0_s3_alu_9_6_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 3) + return OPCODE_IVP_LT2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_LE2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 1 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 2) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 6 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 2 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 2) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 5 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 3 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 2 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 4 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 2 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 3) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 17 && + Field_fld_n0_s3_alu_9_3_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTBI2NX8; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 16 && + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get (insn) == 7 && + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get (insn) == 0 && + Field_fld_n0_s3_alu_9_7_Slot_n0_s3_alu_get (insn) == 0) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_n0_s3_alu_27_3_Slot_n0_s3_alu_get (insn) == 7340144 && + Field_fld_n0_s3_alu_2_0_Slot_n0_s3_alu_get (insn) == 1) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_f0_s1_ld_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f0_s1_ld_24_0_Slot_f0_s1_ld_get (insn) == 1853188) + return OPCODE_NOP; + if (Field_fld_f0_s1_ld_24_11_Slot_f0_s1_ld_get (insn) == 954 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 4) + return OPCODE_IVP_MOVAB1; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 449) + return OPCODE_SUBX8; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 451) + return OPCODE_SEXT; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 456) + return OPCODE_XOR; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 457) + return OPCODE_ADDX8; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 458) + return OPCODE_SRLI; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 459) + return OPCODE_IVP_ADDMOD16U; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 460 && + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get (insn) == 10) + return OPCODE_NEG; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 460 && + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get (insn) == 11) + return OPCODE_SRA; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 461 && + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get (insn) == 10) + return OPCODE_SRL; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 464) + return OPCODE_MUL16S; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 465) + return OPCODE_MOVEQZ; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 466) + return OPCODE_OR; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 467) + return OPCODE_MOVLTZ; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 472) + return OPCODE_SALTU; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 473) + return OPCODE_SUB; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 474) + return OPCODE_SUBX2; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 475) + return OPCODE_SUBX4; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 476 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 4) + return OPCODE_SLL; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 480) + return OPCODE_ADD; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 481) + return OPCODE_ADDX4; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 482) + return OPCODE_ADDX2; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 483) + return OPCODE_AND; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 488) + return OPCODE_MAX; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 489) + return OPCODE_MAXU; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 496) + return OPCODE_MUL16U; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 497) + return OPCODE_MOVGEZ; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 498) + return OPCODE_SALT; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 499) + return OPCODE_MOVNEZ; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 504) + return OPCODE_MIN; + if (Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get (insn) == 505) + return OPCODE_MINU; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 168) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 169) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 170) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 171) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 172) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 173) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 174) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 175) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 176) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 177) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 178) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 179) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 180) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 181) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 182) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 183) + return OPCODE_SRAI; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 184 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT32UNX48L; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 184 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 54) + return OPCODE_IVP_CVT64UN_2X96L; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 184 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 55) + return OPCODE_IVP_GATHERD2NX8_L; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 185 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT64S48; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 185 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 54) + return OPCODE_IVP_PACKHN_2X64W; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 185 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 55) + return OPCODE_IVP_GATHERDNX16; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 186 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT64SNX48HH; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 186 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 54) + return OPCODE_IVP_PACKL2NX24; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 186 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 55) + return OPCODE_IVP_GATHERDNX8S; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 187 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 222) + return OPCODE_IVP_SEQNX16; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 187 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT64SNX48HL; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 187 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 54) + return OPCODE_IVP_PACKL2NX24_1; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 187 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 221) + return OPCODE_IVP_SEQ2NX8; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 187 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 223) + return OPCODE_IVP_SEQN_2X32; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 188 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT64SNX48LH; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 188 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 54) + return OPCODE_IVP_PACKLNX48; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 189 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT64SNX48LL; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 189 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 54) + return OPCODE_IVP_PACKLN_2X96; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 190 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT64U96; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 190 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 54) + return OPCODE_IVP_PACKMNX48; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 191 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT64UN_2X96H; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 191 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 54) + return OPCODE_IVP_GATHERD2NX8_H; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 227 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVR2NX24; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 227 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVR2NX24_0; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 227 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVR2NX24_1; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 227 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNR2NX24; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 230 && + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get (insn) == 6) + return OPCODE_IVP_MOVVA16; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 230 && + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get (insn) == 4) + return OPCODE_IVP_MOVPA16; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 230 && + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get (insn) == 5) + return OPCODE_IVP_MOVQA16; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 230 && + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get (insn) == 7) + return OPCODE_IVP_MOVVA32; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 230 && + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get (insn) == 8) + return OPCODE_IVP_MOVVA8; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 230 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRU2NX24_1; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 235 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNR2NX24_0; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 235 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNR2NX24_1; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 235 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNRNX48_0; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 235 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNRNX48; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_6_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINX16; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 28) + return OPCODE_IVP_CVT32S2NX24LL; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 27) + return OPCODE_IVP_CVT32S2NX24LH; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 26) + return OPCODE_IVP_CVT32S2NX24HL; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 25) + return OPCODE_IVP_CVT32S2NX24HH; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 21) + return OPCODE_IVP_CVT16S2NX24L; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 20) + return OPCODE_IVP_CVT16S2NX24H; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 30) + return OPCODE_IVP_CVT32SNX48L; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 29) + return OPCODE_IVP_CVT32SNX48H; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 22) + return OPCODE_IVP_CVT16U2NX24H; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 31) + return OPCODE_IVP_CVT32UNX48H; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 23) + return OPCODE_IVP_CVT16U2NX24L; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 238 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 24) + return OPCODE_IVP_CVT32S24; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 243 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNX48; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 243 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNRN_2X64W; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 243 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNX48_0; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 243 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNRNX48_1; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 245 && + Field_fld_f0_s1_ld_7_7_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVPINT16; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 245 && + Field_fld_f0_s1_ld_7_7_Slot_f0_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVVINT16; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 251 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRU2NX24; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 251 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRU2NX24_0; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 251 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRN_2X64W; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 251 && + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNX48_1; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 253 && + Field_fld_f0_s1_ld_7_7_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVQINT16; + if (Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get (insn) == 253 && + Field_fld_f0_s1_ld_7_7_Slot_f0_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVVINT8; + if (Field_fld_f0_s1_ld_24_14_Slot_f0_s1_ld_get (insn) == 112 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_SLLI; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 14) + return OPCODE_ADDI; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 15) + return OPCODE_ADDMI; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 20) + return OPCODE_L32I; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 24) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 211) + return OPCODE_IVP_NOTB; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 2 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 15) + return OPCODE_IVP_ANDB; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 3 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 24) + return OPCODE_IVP_ORB; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 2 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 25) + return OPCODE_IVP_XORB; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 3 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 15) + return OPCODE_IVP_ANDNOTB; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 210) + return OPCODE_IVP_MB; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_get (insn) == 30) + return OPCODE_IVP_LTRN; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 3 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 25) + return OPCODE_IVP_LTRNI; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 0 && + Field_fld_f0_s1_ld_7_6_Slot_f0_s1_ld_get (insn) == 1) + return OPCODE_IVP_LBN_I; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 6) + return OPCODE_IVP_LBN_IP; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 2 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 24) + return OPCODE_IVP_JOINB; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_get (insn) == 46) + return OPCODE_IVP_LTRN_2; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 0 && + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get (insn) == 52) + return OPCODE_IVP_LTRN_2I; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_6_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_LBN_2_I; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 5) + return OPCODE_IVP_LBN_2_IP; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 209) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 208) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_get (insn) == 110) + return OPCODE_IVP_MOVBA1; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 2 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 208) + return OPCODE_IVP_NOTB1; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 0 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 24) + return OPCODE_IVP_ANDNOTB1; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 25) + return OPCODE_IVP_ORNOTB1; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 0 && + Field_fld_f0_s1_ld_7_6_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_LB2N_I; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 4) + return OPCODE_IVP_LB2N_IP; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_get (insn) == 14) + return OPCODE_IVP_LTR2N; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 14) + return OPCODE_IVP_LTR2NI; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 0 && + Field_fld_f0_s1_ld_7_5_Slot_f0_s1_ld_get (insn) == 5) + return OPCODE_IVP_SQZN; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get (insn) == 1 && + Field_fld_f0_s1_ld_7_5_Slot_f0_s1_ld_get (insn) == 5) + return OPCODE_IVP_UNSQZN; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_get (insn) == 62) + return OPCODE_IVP_LTRS2N; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_get (insn) == 78) + return OPCODE_IVP_LTRSN; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_get (insn) == 94) + return OPCODE_IVP_LTRSN_2; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 0 && + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get (insn) == 25) + return OPCODE_IVP_ORNOTB; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 3 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 208) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 2 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 210) + return OPCODE_IVP_RORB2N; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 2 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 209) + return OPCODE_IVP_RANDBN; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 3 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 210) + return OPCODE_IVP_RORBN; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 3 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 209) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get (insn) == 23 && + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get (insn) == 2 && + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get (insn) == 211) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f0_s1_ld_24_17_Slot_f0_s1_ld_get (insn) == 2) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_f0_s1_ld_24_17_Slot_f0_s1_ld_get (insn) == 3) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_f0_s1_ld_24_17_Slot_f0_s1_ld_get (insn) == 4) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_f0_s1_ld_24_17_Slot_f0_s1_ld_get (insn) == 5) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_f0_s1_ld_24_17_Slot_f0_s1_ld_get (insn) == 6) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_LAT2NX8_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 4 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 7) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 4 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 6) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 4 && + Field_fld_f0_s1_ld_15_15_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 4 && + Field_fld_f0_s1_ld_15_14_Slot_f0_s1_ld_get (insn) == 2) + return OPCODE_MOVI; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 6 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 3) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 6 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 4) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 6 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 5) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 6 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 2) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 6 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 1) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 6 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 6) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 6 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 7) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 6 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_15_10_Slot_f0_s1_ld_get (insn) == 16) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_15_8_Slot_f0_s1_ld_get (insn) == 68) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_15_4_Slot_f0_s1_ld_get (insn) == 1120) + return OPCODE_IVP_LA_PP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_15_2_Slot_f0_s1_ld_get (insn) == 4544) + return OPCODE_IVP_MALIGN; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 0) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 1) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 2) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 3) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get (insn) == 7 && + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get (insn) == 4) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_f0_s1_ld_24_8_Slot_f0_s1_ld_get (insn) == 7237) + return OPCODE_NSA; + if (Field_fld_f0_s1_ld_24_8_Slot_f0_s1_ld_get (insn) == 7493) + return OPCODE_NSAU; + return XTENSA_UNDEFINED; +} + +static int +Slot_f1_s1_ld_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f1_s1_ld_26_11_Slot_f1_s1_ld_get (insn) == 1294 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_IVP_MOVAB1; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 570) + return OPCODE_ADD; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 571) + return OPCODE_ADDX2; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 572) + return OPCODE_ADDX4; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 573) + return OPCODE_ADDX8; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 574) + return OPCODE_AND; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 575) + return OPCODE_MAX; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 576) + return OPCODE_MAXU; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 577) + return OPCODE_MIN; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 578) + return OPCODE_MINU; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 579) + return OPCODE_MOVEQZ; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 580) + return OPCODE_MOVGEZ; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 581) + return OPCODE_MOVLTZ; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 582) + return OPCODE_MOVNEZ; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 583) + return OPCODE_OR; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 584) + return OPCODE_SALT; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 585) + return OPCODE_SALTU; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 586) + return OPCODE_SUB; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 587) + return OPCODE_SUBX2; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 588) + return OPCODE_SUBX4; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 589) + return OPCODE_SUBX8; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 590) + return OPCODE_XOR; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 591) + return OPCODE_SEXT; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 592) + return OPCODE_SRLI; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 593 && + Field_fld_f1_s1_ld_3_0_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 593 && + Field_fld_f1_s1_ld_3_0_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_SRA; + if (Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get (insn) == 646 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_SLL; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 229) + return OPCODE_SLLI; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 230) + return OPCODE_IVP_LSNX16_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 231) + return OPCODE_IVP_LSNX8S_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 237) + return OPCODE_IVP_LS2NX8_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 238) + return OPCODE_IVP_LSNX8S_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 239) + return OPCODE_IVP_LSN_2X16S_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 245) + return OPCODE_IVP_LS2NX8_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 246) + return OPCODE_IVP_LSN_2X16S_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 247) + return OPCODE_IVP_LSN_2X32_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 253) + return OPCODE_IVP_LSNX16_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 254) + return OPCODE_IVP_LSN_2X32_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 255) + return OPCODE_IVP_LSR2NX8_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 256) + return OPCODE_IVP_LSR2NX8_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 257) + return OPCODE_IVP_LSRNX16_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 258) + return OPCODE_IVP_LSRNX16_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 259) + return OPCODE_IVP_LSRN_2X32_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 260) + return OPCODE_IVP_LSRN_2X32_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 261) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 262) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 263) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 264) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 265) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 266) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 267) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 268) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 269) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 270) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 271) + return OPCODE_IVP_LS2NX8_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 272) + return OPCODE_IVP_LSNX16_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 273) + return OPCODE_IVP_LSNX8S_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 274) + return OPCODE_IVP_LSN_2X16S_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 275) + return OPCODE_IVP_LSN_2X32_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 276) + return OPCODE_IVP_LSR2NX8_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 277) + return OPCODE_IVP_LSRNX16_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 278) + return OPCODE_IVP_LSRN_2X32_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 279) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 280) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 281) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 282) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 283) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 284) + return OPCODE_SRAI; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 297 && + Field_fld_f1_s1_ld_7_7_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVPINT16; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 297 && + Field_fld_f1_s1_ld_7_7_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVQINT16; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 298 && + Field_fld_f1_s1_ld_7_7_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINT16; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 298 && + Field_fld_f1_s1_ld_7_6_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_IVP_MOVVINX16; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 299 && + Field_fld_f1_s1_ld_7_7_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINT8; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 300 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVR2NX24; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 300 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVR2NX24_0; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 300 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNRN_2X64W; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 300 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNRNX48_1; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 301 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVR2NX24_1; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 301 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNX48; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 301 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNX48_0; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 301 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNR2NX24; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 302 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNR2NX24_0; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 302 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNR2NX24_1; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 302 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRN_2X64W; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 302 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNX48_1; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 303 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRU2NX24; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 303 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRU2NX24_0; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 303 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNRNX48_0; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 303 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNRNX48; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 304 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 22) + return OPCODE_IVP_CVT32UNX48L; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 304 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 23) + return OPCODE_IVP_PACKMNX48; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 305 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 22) + return OPCODE_IVP_CVT64S48; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 305 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 23) + return OPCODE_IVP_GATHERD2NX8_H; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 306 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 22) + return OPCODE_IVP_CVT64U96; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 306 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 23) + return OPCODE_IVP_GATHERD2NX8_L; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 307 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 22) + return OPCODE_IVP_PACKHN_2X64W; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 307 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 23) + return OPCODE_IVP_GATHERDNX16; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 308 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 22) + return OPCODE_IVP_PACKL2NX24; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 308 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 23) + return OPCODE_IVP_GATHERDNX8S; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 309 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 94) + return OPCODE_IVP_SEQNX16; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 309 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 22) + return OPCODE_IVP_PACKL2NX24_1; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 309 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 93) + return OPCODE_IVP_SEQ2NX8; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 309 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 95) + return OPCODE_IVP_SEQN_2X32; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 310 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 22) + return OPCODE_IVP_PACKLNX48; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 311 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 22) + return OPCODE_IVP_PACKLN_2X96; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 321 && + Field_fld_f1_s1_ld_3_0_Slot_f1_s1_ld_get (insn) == 4) + return OPCODE_IVP_MOVVA16; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 321 && + Field_fld_f1_s1_ld_3_0_Slot_f1_s1_ld_get (insn) == 5) + return OPCODE_IVP_MOVVA32; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 321 && + Field_fld_f1_s1_ld_3_0_Slot_f1_s1_ld_get (insn) == 6) + return OPCODE_IVP_MOVVA8; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 321 && + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRU2NX24_1; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 331 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 9) + return OPCODE_IVP_CVT16S2NX24L; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 331 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 8) + return OPCODE_IVP_CVT16S2NX24H; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 331 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 10) + return OPCODE_IVP_CVT16U2NX24H; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 331 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 11) + return OPCODE_IVP_CVT16U2NX24L; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 339 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 11) + return OPCODE_IVP_CVT32S2NX24LH; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 339 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 10) + return OPCODE_IVP_CVT32S2NX24HL; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 339 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 9) + return OPCODE_IVP_CVT32S2NX24HH; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 339 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 8) + return OPCODE_IVP_CVT32S24; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 347 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 8) + return OPCODE_IVP_CVT32S2NX24LL; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 347 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 10) + return OPCODE_IVP_CVT32SNX48L; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 347 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 9) + return OPCODE_IVP_CVT32SNX48H; + if (Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get (insn) == 347 && + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get (insn) == 11) + return OPCODE_IVP_CVT32UNX48H; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (insn) == 8) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 81) + return OPCODE_IVP_NOTB; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 1 && + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (insn) == 8) + return OPCODE_IVP_ANDB; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (insn) == 9) + return OPCODE_IVP_ORB; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (insn) == 10) + return OPCODE_IVP_XORB; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 1 && + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (insn) == 9) + return OPCODE_IVP_ANDNOTB; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 80) + return OPCODE_IVP_MB; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_get (insn) == 118) + return OPCODE_IVP_LTRN; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_10_Slot_f1_s1_ld_get (insn) == 0 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 6) + return OPCODE_IVP_LTRNI; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (insn) == 9) + return OPCODE_IVP_JOINB; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_get (insn) == 134) + return OPCODE_IVP_LTRN_2; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_9_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 6) + return OPCODE_IVP_LTRN_2I; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_get (insn) == 198) + return OPCODE_IVP_MOVBA1; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 82) + return OPCODE_IVP_NOTB1; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (insn) == 8) + return OPCODE_IVP_ANDNOTB1; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 1 && + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (insn) == 10) + return OPCODE_IVP_ORNOTB1; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_get (insn) == 102) + return OPCODE_IVP_LTR2N; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 0 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 4) + return OPCODE_IVP_LTR2NI; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_12_Slot_f1_s1_ld_get (insn) == 0 && + Field_fld_f1_s1_ld_7_5_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_SQZN; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_12_Slot_f1_s1_ld_get (insn) == 1 && + Field_fld_f1_s1_ld_7_5_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_UNSQZN; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_get (insn) == 150) + return OPCODE_IVP_LTRS2N; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_get (insn) == 166) + return OPCODE_IVP_LTRSN; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_get (insn) == 182) + return OPCODE_IVP_LTRSN_2; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 0 && + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get (insn) == 10) + return OPCODE_IVP_ORNOTB; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 83) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 86) + return OPCODE_IVP_RORB2N; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 84) + return OPCODE_IVP_RANDBN; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 87) + return OPCODE_IVP_RORBN; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 85) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get (insn) == 38 && + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get (insn) == 96) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_LAT2NX8_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 1 && + Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 1 && + Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_LSN_2X32_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 4 && + Field_fld_f1_s1_ld_15_14_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 4 && + Field_fld_f1_s1_ld_15_14_Slot_f1_s1_ld_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 4 && + Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 5 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 7) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 5 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 5) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 5 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 6) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 5 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 4) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 5 && + Field_fld_f1_s1_ld_15_14_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_L32I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 5 && + Field_fld_f1_s1_ld_15_14_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_MOVI; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 6 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 7) + return OPCODE_IVP_LSNX16_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 6 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 6 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 6 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 3) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 6 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 6 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 4) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 6 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 5) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 6 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 6) + return OPCODE_IVP_LS2NX8_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 7 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_LSNX8S_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 7 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_LSN_2X16S_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 7 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_IVP_LSR2NX8_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 7 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 3) + return OPCODE_IVP_LSRNX16_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 7 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 4) + return OPCODE_IVP_LSRN_2X32_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 10 && + Field_fld_f1_s1_ld_15_10_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 10 && + Field_fld_f1_s1_ld_15_8_Slot_f1_s1_ld_get (insn) == 4) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 10 && + Field_fld_f1_s1_ld_15_4_Slot_f1_s1_ld_get (insn) == 80) + return OPCODE_IVP_LA_PP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 10 && + Field_fld_f1_s1_ld_15_2_Slot_f1_s1_ld_get (insn) == 324) + return OPCODE_IVP_MALIGN; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 10 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 10 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 10 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 10 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 3 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 1) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get (insn) == 10 && + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get (insn) == 2 && + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get (insn) == 2) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_f1_s1_ld_26_2_Slot_f1_s1_ld_get (insn) == 655685 && + Field_fld_f1_s1_ld_1_0_Slot_f1_s1_ld_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_f2_s1_ld_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f2_s1_ld_26_11_Slot_f2_s1_ld_get (insn) == 1294 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_MOVAB1; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 570) + return OPCODE_ADD; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 571) + return OPCODE_ADDX2; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 572) + return OPCODE_ADDX4; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 573) + return OPCODE_ADDX8; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 574) + return OPCODE_AND; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 575) + return OPCODE_IVP_ADDMOD16U; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 576) + return OPCODE_MAX; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 577) + return OPCODE_MAXU; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 578) + return OPCODE_MIN; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 579) + return OPCODE_MINU; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 580) + return OPCODE_MOVEQZ; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 581) + return OPCODE_MOVGEZ; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 582) + return OPCODE_MOVLTZ; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 583) + return OPCODE_MOVNEZ; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 584) + return OPCODE_OR; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 585) + return OPCODE_SALT; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 586) + return OPCODE_SALTU; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 587) + return OPCODE_SUB; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 588) + return OPCODE_SUBX2; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 589) + return OPCODE_SUBX4; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 590) + return OPCODE_SUBX8; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 591) + return OPCODE_XOR; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 592) + return OPCODE_SEXT; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 593) + return OPCODE_SRLI; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 642 && + Field_fld_f2_s1_ld_3_0_Slot_f2_s1_ld_get (insn) == 9) + return OPCODE_SRL; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 642 && + Field_fld_f2_s1_ld_3_0_Slot_f2_s1_ld_get (insn) == 8) + return OPCODE_SRA; + if (Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get (insn) == 646 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_SLL; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 229) + return OPCODE_IVP_LS2NX8_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 230) + return OPCODE_IVP_LSNX8S_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 231) + return OPCODE_IVP_LSNX8S_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 237) + return OPCODE_IVP_LS2NX8_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 238) + return OPCODE_IVP_LSN_2X16S_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 239) + return OPCODE_IVP_LSN_2X16S_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 245) + return OPCODE_IVP_LSNX16_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 246) + return OPCODE_IVP_LSN_2X32_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 247) + return OPCODE_IVP_LSN_2X32_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 253) + return OPCODE_IVP_LSNX16_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 254) + return OPCODE_IVP_LSR2NX8_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 255) + return OPCODE_IVP_LSR2NX8_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 256) + return OPCODE_IVP_LSRNX16_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 257) + return OPCODE_IVP_LSRNX16_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 258) + return OPCODE_IVP_LSRN_2X32_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 259) + return OPCODE_IVP_LSRN_2X32_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 260) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 261) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 262) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 263) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 264) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 265) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 266) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 267) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 268) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 269) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 270) + return OPCODE_SLLI; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 271) + return OPCODE_IVP_LS2NX8_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 272) + return OPCODE_IVP_LSNX16_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 273) + return OPCODE_IVP_LSNX8S_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 274) + return OPCODE_IVP_LSN_2X16S_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 275) + return OPCODE_IVP_LSN_2X32_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 276) + return OPCODE_IVP_LSR2NX8_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 277) + return OPCODE_IVP_LSRNX16_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 278) + return OPCODE_IVP_LSRN_2X32_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 279) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 280) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 281) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 282) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 283) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 284) + return OPCODE_SRAI; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 297 && + Field_fld_f2_s1_ld_7_7_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVPINT16; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 297 && + Field_fld_f2_s1_ld_7_7_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVQINT16; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 298 && + Field_fld_f2_s1_ld_7_7_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINT16; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 298 && + Field_fld_f2_s1_ld_7_6_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_MOVVINX16; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 299 && + Field_fld_f2_s1_ld_7_7_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINT8; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 300 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVR2NX24; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 300 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVR2NX24_0; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 300 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNRN_2X64W; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 300 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNRNX48_1; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 301 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVR2NX24_1; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 301 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNX48; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 301 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNX48_0; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 301 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNR2NX24; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 302 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNR2NX24_0; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 302 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNR2NX24_1; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 302 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRN_2X64W; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 302 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNX48_1; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 303 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRU2NX24; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 303 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRU2NX24_0; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 303 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNRNX48_0; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 303 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNRNX48; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_3_0_Slot_f2_s1_ld_get (insn) == 4) + return OPCODE_IVP_MOVVA16; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 222) + return OPCODE_IVP_SEQNX16; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 3) + return OPCODE_IVP_CVT32UNX48L; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 7) + return OPCODE_IVP_CVT64S48; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 11) + return OPCODE_IVP_CVT64U96; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_3_0_Slot_f2_s1_ld_get (insn) == 5) + return OPCODE_IVP_MOVVA32; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_3_0_Slot_f2_s1_ld_get (insn) == 6) + return OPCODE_IVP_MOVVA8; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 19) + return OPCODE_IVP_PACKL2NX24; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 27) + return OPCODE_IVP_PACKLNX48; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 23) + return OPCODE_IVP_PACKL2NX24_1; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRU2NX24_1; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 35) + return OPCODE_IVP_PACKMNX48; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 31) + return OPCODE_IVP_PACKLN_2X96; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 15) + return OPCODE_IVP_PACKHN_2X64W; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 221) + return OPCODE_IVP_SEQ2NX8; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 223) + return OPCODE_IVP_SEQN_2X32; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 47) + return OPCODE_IVP_GATHERDNX16; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 51) + return OPCODE_IVP_GATHERDNX8S; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 43) + return OPCODE_IVP_GATHERD2NX8_L; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 321 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 39) + return OPCODE_IVP_GATHERD2NX8_H; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 331 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 9) + return OPCODE_IVP_CVT16S2NX24L; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 331 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 8) + return OPCODE_IVP_CVT16S2NX24H; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 331 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 10) + return OPCODE_IVP_CVT16U2NX24H; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 331 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 11) + return OPCODE_IVP_CVT16U2NX24L; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 339 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 11) + return OPCODE_IVP_CVT32S2NX24LH; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 339 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 10) + return OPCODE_IVP_CVT32S2NX24HL; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 339 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 9) + return OPCODE_IVP_CVT32S2NX24HH; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 339 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 8) + return OPCODE_IVP_CVT32S24; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 347 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 8) + return OPCODE_IVP_CVT32S2NX24LL; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 347 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 10) + return OPCODE_IVP_CVT32SNX48L; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 347 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 9) + return OPCODE_IVP_CVT32SNX48H; + if (Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get (insn) == 347 && + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get (insn) == 11) + return OPCODE_IVP_CVT32UNX48H; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 19) + return OPCODE_IVP_NOTB; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 1 && + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_ANDB; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_ORB; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_XORB; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 1 && + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_ANDNOTB; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 18) + return OPCODE_IVP_MB; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_get (insn) == 114) + return OPCODE_IVP_LTRN; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_10_Slot_f2_s1_ld_get (insn) == 0 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_LTRNI; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_JOINB; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_get (insn) == 130) + return OPCODE_IVP_LTRN_2; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_9_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_LTRN_2I; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 17) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 16) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_get (insn) == 194) + return OPCODE_IVP_MOVBA1; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 20) + return OPCODE_IVP_NOTB1; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_ANDNOTB1; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 1 && + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_ORNOTB1; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_get (insn) == 98) + return OPCODE_IVP_LTR2N; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 0 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTR2NI; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_get (insn) == 146) + return OPCODE_IVP_LTRS2N; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_get (insn) == 162) + return OPCODE_IVP_LTRSN; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_get (insn) == 178) + return OPCODE_IVP_LTRSN_2; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 0 && + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_ORNOTB; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 21) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 32) + return OPCODE_IVP_RORB2N; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 22) + return OPCODE_IVP_RANDBN; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 32) + return OPCODE_IVP_RORBN; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 23) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get (insn) == 38 && + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get (insn) == 33) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LAT2NX8_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 1 && + Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 1 && + Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LSN_2X32_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 4 && + Field_fld_f2_s1_ld_15_14_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 4 && + Field_fld_f2_s1_ld_15_14_Slot_f2_s1_ld_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 4 && + Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 5 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 7) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 5 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 5) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 5 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 6) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 5 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 4) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 5 && + Field_fld_f2_s1_ld_15_14_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_L32I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 5 && + Field_fld_f2_s1_ld_15_14_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_MOVI; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 6 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 7) + return OPCODE_IVP_LSNX16_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 6 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 6 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 6 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 3) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 6 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 6 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 4) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 6 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 5) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 6 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 6) + return OPCODE_IVP_LS2NX8_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 7 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LSNX8S_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 7 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LSN_2X16S_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 7 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_LSR2NX8_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 7 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 3) + return OPCODE_IVP_LSRNX16_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 7 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 4) + return OPCODE_IVP_LSRN_2X32_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 10 && + Field_fld_f2_s1_ld_15_10_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 10 && + Field_fld_f2_s1_ld_15_8_Slot_f2_s1_ld_get (insn) == 4) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 10 && + Field_fld_f2_s1_ld_15_4_Slot_f2_s1_ld_get (insn) == 80) + return OPCODE_IVP_LA_PP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 10 && + Field_fld_f2_s1_ld_15_2_Slot_f2_s1_ld_get (insn) == 324) + return OPCODE_IVP_MALIGN; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 10 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 10 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 10 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 10 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 3 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get (insn) == 10 && + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get (insn) == 2 && + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get (insn) == 2) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_f2_s1_ld_26_2_Slot_f2_s1_ld_get (insn) == 655685 && + Field_fld_f2_s1_ld_1_0_Slot_f2_s1_ld_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_f3_s1_ld_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f3_s1_ld_21_0_Slot_f3_s1_ld_get (insn) == 1769748) + return OPCODE_NOP; + if (Field_fld_f3_s1_ld_21_10_Slot_f3_s1_ld_get (insn) == 1729 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRNI; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 830 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTR2NI; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 831 && + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_ANDB; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 831 && + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_ANDNOTB; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 848 && + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_ANDNOTB1; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 848 && + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_ORNOTB; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 849 && + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 849 && + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_ORNOTB1; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 850 && + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_XORB; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 850 && + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_JOINB; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 851 && + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_ORB; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 851 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 24) + return OPCODE_IVP_RORB2N; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 851 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 25) + return OPCODE_IVP_RORBN; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 851 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 26) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 854 && + Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_get (insn) == 8) + return OPCODE_IVP_MOVAB1; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 866 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_MB; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 866 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 2) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 866 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 18) + return OPCODE_IVP_NOTB1; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 866 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 19) + return OPCODE_IVP_RANDBN; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 867 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_NOTB; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 867 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 2) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 867 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 18) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get (insn) == 867 && + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get (insn) == 19) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 376) + return OPCODE_ADD; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 377) + return OPCODE_ADDX2; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 378) + return OPCODE_ADDX4; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 379) + return OPCODE_ADDX8; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 380) + return OPCODE_AND; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 381) + return OPCODE_IVP_ADDMOD16U; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 382) + return OPCODE_MAX; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 383) + return OPCODE_MAXU; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 384) + return OPCODE_MIN; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 385) + return OPCODE_MINU; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 386) + return OPCODE_MOVEQZ; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 387) + return OPCODE_MOVGEZ; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 388) + return OPCODE_MOVLTZ; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 389) + return OPCODE_MOVNEZ; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 390) + return OPCODE_OR; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 391) + return OPCODE_SALT; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 392) + return OPCODE_SALTU; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 393) + return OPCODE_SUB; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 394) + return OPCODE_SUBX2; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 395) + return OPCODE_SUBX4; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 396) + return OPCODE_SUBX8; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 397) + return OPCODE_XOR; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 398) + return OPCODE_SEXT; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 399) + return OPCODE_SRLI; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 400) + return OPCODE_IVP_SQZN; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 401) + return OPCODE_IVP_UNSQZN; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 409 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LB2N_IP; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 411 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LBN_2_IP; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 413 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LBN_IP; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 426 && + Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_get (insn) == 8) + return OPCODE_SLL; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 433 && + Field_fld_f3_s1_ld_3_0_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get (insn) == 433 && + Field_fld_f3_s1_ld_3_0_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_SRA; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 168) + return OPCODE_SLLI; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 169) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 170) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 171) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 172) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 173) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 174) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 175) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 176) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 177) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 178) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 179) + return OPCODE_IVP_LB2N_I; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 180) + return OPCODE_IVP_LBN_2_I; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 181) + return OPCODE_IVP_LBN_I; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 182) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 183) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 184) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 185) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 186) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 187) + return OPCODE_SRAI; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 202 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVPINT16; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 202 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVQINT16; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 203 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINT16; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 203 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVVINT8; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 204 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 52) + return OPCODE_IVP_CVT32UNX48L; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 204 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 60) + return OPCODE_IVP_CVT64S48; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 204 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT64U96; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 204 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 54) + return OPCODE_IVP_PACKL2NX24; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 204 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 55) + return OPCODE_IVP_PACKLNX48; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 204 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 62) + return OPCODE_IVP_PACKL2NX24_1; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 204 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 63) + return OPCODE_IVP_PACKLN_2X96; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 204 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 61) + return OPCODE_IVP_PACKHN_2X64W; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 205 && + Field_fld_f3_s1_ld_7_0_Slot_f3_s1_ld_get (insn) == 250) + return OPCODE_IVP_SEQNX16; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 205 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 52) + return OPCODE_IVP_PACKMNX48; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 205 && + Field_fld_f3_s1_ld_7_0_Slot_f3_s1_ld_get (insn) == 249) + return OPCODE_IVP_SEQ2NX8; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 205 && + Field_fld_f3_s1_ld_7_0_Slot_f3_s1_ld_get (insn) == 251) + return OPCODE_IVP_SEQN_2X32; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 205 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 61) + return OPCODE_IVP_GATHERDNX16; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 205 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 54) + return OPCODE_IVP_GATHERDNX8S; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 205 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 53) + return OPCODE_IVP_GATHERD2NX8_L; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 205 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 60) + return OPCODE_IVP_GATHERD2NX8_H; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 208 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVR2NX24; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 208 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVR2NX24_0; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 208 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVR2NX24_1; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 208 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNR2NX24; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 209 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNR2NX24_0; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 209 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNR2NX24_1; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 209 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNRNX48_0; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 209 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNRNX48; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 210 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNX48; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 210 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNRN_2X64W; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 210 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNX48_0; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 210 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNRNX48_1; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 211 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRU2NX24; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 211 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRU2NX24_0; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 211 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRN_2X64W; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 211 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNX48_1; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 212 && + Field_fld_f3_s1_ld_3_0_Slot_f3_s1_ld_get (insn) == 4) + return OPCODE_IVP_MOVVA16; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 212 && + Field_fld_f3_s1_ld_3_0_Slot_f3_s1_ld_get (insn) == 5) + return OPCODE_IVP_MOVVA32; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 212 && + Field_fld_f3_s1_ld_3_0_Slot_f3_s1_ld_get (insn) == 6) + return OPCODE_IVP_MOVVA8; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 212 && + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRU2NX24_1; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_7_Slot_f3_s1_ld_get (insn) == 0 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINX16; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 50) + return OPCODE_IVP_CVT32S2NX24LL; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 57) + return OPCODE_IVP_CVT32S2NX24LH; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 49) + return OPCODE_IVP_CVT32S2NX24HL; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 56) + return OPCODE_IVP_CVT32S2NX24HH; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 41) + return OPCODE_IVP_CVT16S2NX24L; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 40) + return OPCODE_IVP_CVT16S2NX24H; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 51) + return OPCODE_IVP_CVT32SNX48L; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 58) + return OPCODE_IVP_CVT32SNX48H; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 42) + return OPCODE_IVP_CVT16U2NX24H; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 59) + return OPCODE_IVP_CVT32UNX48H; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 43) + return OPCODE_IVP_CVT16U2NX24L; + if (Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get (insn) == 213 && + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get (insn) == 48) + return OPCODE_IVP_CVT32S24; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 32) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 33) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 34) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 35) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 36) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 37) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 38) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 39) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 40) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 41) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 51 && + Field_fld_f3_s1_ld_12_11_Slot_f3_s1_ld_get (insn) == 0 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 51 && + Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 51 && + Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 51 && + Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_get (insn) == 5) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 51 && + Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_get (insn) == 7) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 51 && + Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_get (insn) == 9) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 54 && + Field_fld_f3_s1_ld_12_8_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 54 && + Field_fld_f3_s1_ld_12_4_Slot_f3_s1_ld_get (insn) == 16) + return OPCODE_IVP_LA_PP; + if (Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get (insn) == 54 && + Field_fld_f3_s1_ld_12_2_Slot_f3_s1_ld_get (insn) == 68) + return OPCODE_IVP_MALIGN; + if (Field_fld_f3_s1_ld_21_16_Slot_f3_s1_ld_get (insn) == 12) + return OPCODE_ADDI; + if (Field_fld_f3_s1_ld_21_16_Slot_f3_s1_ld_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_fld_f3_s1_ld_21_16_Slot_f3_s1_ld_get (insn) == 14) + return OPCODE_L32I; + if (Field_fld_f3_s1_ld_21_16_Slot_f3_s1_ld_get (insn) == 15) + return OPCODE_MOVI; + if (Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_get (insn) == 2) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_get (insn) == 3) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_get (insn) == 4) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_get (insn) == 5) + return OPCODE_EXTUI; + if (Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_get (insn) == 6918 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTR2N; + if (Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_get (insn) == 6919 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTRN; + if (Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_get (insn) == 6948 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRN_2; + if (Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_get (insn) == 6948 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVBA1; + if (Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_get (insn) == 6949 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRS2N; + if (Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_get (insn) == 6950 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRSN; + if (Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_get (insn) == 6951 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRSN_2; + if (Field_fld_f3_s1_ld_21_9_Slot_f3_s1_ld_get (insn) == 3458 && + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTRN_2I; + return XTENSA_UNDEFINED; +} + +static int +Slot_f11_s1_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f11_s1_alu_22_0_Slot_f11_s1_alu_get (insn) == 794628) + return OPCODE_NOP; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 165) + return OPCODE_ADD; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 167) + return OPCODE_ADDX2; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 168) + return OPCODE_ADDX4; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 169) + return OPCODE_MAXU; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 170) + return OPCODE_ADDX8; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 171) + return OPCODE_MIN; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 172) + return OPCODE_AND; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 173) + return OPCODE_MINU; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 174) + return OPCODE_MAX; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 175) + return OPCODE_MOVEQZ; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 176) + return OPCODE_MOVGEZ; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 177) + return OPCODE_SUBX4; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 178) + return OPCODE_MOVLTZ; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 179) + return OPCODE_SUBX8; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 180) + return OPCODE_MOVNEZ; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 181) + return OPCODE_XOR; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 182) + return OPCODE_OR; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 183) + return OPCODE_SEXT; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 184) + return OPCODE_SALT; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 185) + return OPCODE_SRLI; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 186) + return OPCODE_SALTU; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 187 && + Field_fld_f11_s1_alu_3_0_Slot_f11_s1_alu_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 187 && + Field_fld_f11_s1_alu_3_0_Slot_f11_s1_alu_get (insn) == 0) + return OPCODE_SRA; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 188) + return OPCODE_SUB; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 190) + return OPCODE_SUBX2; + if (Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get (insn) == 208 && + Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_get (insn) == 1) + return OPCODE_SLL; + if (Field_fld_f11_s1_alu_22_13_Slot_f11_s1_alu_get (insn) == 80) + return OPCODE_IVP_L2U2NX8_XP; + if (Field_fld_f11_s1_alu_22_13_Slot_f11_s1_alu_get (insn) == 81) + return OPCODE_SRAI; + if (Field_fld_f11_s1_alu_22_14_Slot_f11_s1_alu_get (insn) == 41 && + Field_fld_f11_s1_alu_12_12_Slot_f11_s1_alu_get (insn) == 0) + return OPCODE_SLLI; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 8) + return OPCODE_ADDI; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 9) + return OPCODE_ADDMI; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 12 && + Field_fld_f11_s1_alu_12_10_Slot_f11_s1_alu_get (insn) == 2 && + Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_get (insn) == 1) + return OPCODE_IVP_EXT0IB; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 12 && + Field_fld_f11_s1_alu_12_10_Slot_f11_s1_alu_get (insn) == 3 && + Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_get (insn) == 1) + return OPCODE_IVP_LTRNI; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 12 && + Field_fld_f11_s1_alu_12_11_Slot_f11_s1_alu_get (insn) == 0 && + Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_get (insn) == 1) + return OPCODE_IVP_LTR2NI; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 14 && + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (insn) == 130) + return OPCODE_IVP_MB; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 14 && + Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_get (insn) == 33) + return OPCODE_IVP_LTRN_2; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 14 && + Field_fld_f11_s1_alu_12_9_Slot_f11_s1_alu_get (insn) == 0 && + Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_get (insn) == 1) + return OPCODE_IVP_LTRN_2I; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 14 && + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (insn) == 131) + return OPCODE_IVP_NOTB1; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 14 && + Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_get (insn) == 49) + return OPCODE_IVP_LTRSN; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 14 && + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (insn) == 163) + return OPCODE_IVP_RORB2N; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 14 && + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (insn) == 162) + return OPCODE_IVP_RANDBN; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 14 && + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (insn) == 194) + return OPCODE_IVP_RORBN_2; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 15 && + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (insn) == 130) + return OPCODE_IVP_NOTB; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 15 && + Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_get (insn) == 17) + return OPCODE_IVP_LTRN; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 15 && + Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_get (insn) == 1) + return OPCODE_IVP_LTR2N; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 15 && + Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_get (insn) == 33) + return OPCODE_IVP_LTRS2N; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 15 && + Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_get (insn) == 49) + return OPCODE_IVP_LTRSN_2; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 15 && + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (insn) == 131) + return OPCODE_IVP_RANDB2N; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 15 && + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (insn) == 163) + return OPCODE_IVP_RORBN; + if (Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get (insn) == 15 && + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get (insn) == 162) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_get (insn) == 0) + return OPCODE_IVP_LAT2NX8_XP; + if (Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_get (insn) == 1 && + Field_fld_f11_s1_alu_15_14_Slot_f11_s1_alu_get (insn) == 2) + return OPCODE_IVP_L2A4NX8_IP; + if (Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_get (insn) == 1 && + Field_fld_f11_s1_alu_15_15_Slot_f11_s1_alu_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_get (insn) == 1 && + Field_fld_f11_s1_alu_15_14_Slot_f11_s1_alu_get (insn) == 3) + return OPCODE_MOVI; + if (Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_get (insn) == 3 && + Field_fld_f11_s1_alu_15_2_Slot_f11_s1_alu_get (insn) == 2048) + return OPCODE_IVP_MALIGN; + if (Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_get (insn) == 3 && + Field_fld_f11_s1_alu_15_13_Slot_f11_s1_alu_get (insn) == 0 && + Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_get (insn) == 0) + return OPCODE_IVP_L2AU2NX8_IP; + return XTENSA_UNDEFINED; +} + +static int +Slot_n2_s1_ld_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_n2_s1_ld_26_10_Slot_n2_s1_ld_get (insn) == 1840 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTRNI; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 908 && + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_ANDNOTB1; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 908 && + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_ORNOTB; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 909 && + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_EXT0IB; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 909 && + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_ORNOTB1; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 910 && + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_XORB; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 910 && + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_JOINB; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 911 && + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_ORB; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 911 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 24) + return OPCODE_IVP_NOTB1; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 911 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 25) + return OPCODE_IVP_RANDB2N; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 911 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 28) + return OPCODE_IVP_RORB2N; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 911 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 26) + return OPCODE_IVP_RANDBN; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 911 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 29) + return OPCODE_IVP_RORBN; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 911 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 27) + return OPCODE_IVP_RANDBN_2; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 911 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 30) + return OPCODE_IVP_RORBN_2; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 918 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTR2NI; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 919 && + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (insn) == 2) + return OPCODE_IVP_ANDB; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 919 && + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_ANDNOTB; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 922 && + Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_MOVAB1; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 934 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 19) + return OPCODE_IVP_MB; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 934 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 935 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 19) + return OPCODE_IVP_NOTB; + if (Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get (insn) == 935 && + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 408) + return OPCODE_ADD; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 409) + return OPCODE_ADDX2; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 410) + return OPCODE_ADDX4; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 411) + return OPCODE_ADDX8; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 412) + return OPCODE_AND; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 413) + return OPCODE_MAX; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 414) + return OPCODE_MAXU; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 415) + return OPCODE_MIN; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 416) + return OPCODE_MINU; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 417) + return OPCODE_MOVEQZ; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 418) + return OPCODE_MOVGEZ; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 419) + return OPCODE_MOVLTZ; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 420) + return OPCODE_MOVNEZ; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 421) + return OPCODE_OR; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 422) + return OPCODE_SALT; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 423) + return OPCODE_SALTU; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 424) + return OPCODE_SUB; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 425) + return OPCODE_SUBX2; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 426) + return OPCODE_SUBX4; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 427) + return OPCODE_SUBX8; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 428) + return OPCODE_XOR; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 429) + return OPCODE_SEXT; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 430) + return OPCODE_L32I_N; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 431) + return OPCODE_SRLI; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 432) + return OPCODE_IVP_SQZN; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 433) + return OPCODE_IVP_UNSQZN; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 456 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LB2N_IP; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 457 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LBN_2_IP; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 458 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LBN_IP; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 461 && + Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_SLL; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 466 && + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 466 && + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get (insn) == 467 && + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get (insn) == 2) + return OPCODE_SRL; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 184) + return OPCODE_SLLI; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 185) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 186) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 187) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 188) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 189) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 190) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 191) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 192) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 193) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 194) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 195) + return OPCODE_IVP_LB2N_I; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 196) + return OPCODE_IVP_LBN_2_I; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 197) + return OPCODE_IVP_LBN_I; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 198) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 199) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 200) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 201) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 202) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 203) + return OPCODE_SRAI; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 217 && + Field_fld_n2_s1_ld_7_7_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVPINT16; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 217 && + Field_fld_n2_s1_ld_7_7_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVQINT16; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 218 && + Field_fld_n2_s1_ld_7_7_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINT16; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 218 && + Field_fld_n2_s1_ld_7_7_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVVINT8; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 219 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVR2NX24; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 219 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVR2NX24_0; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 219 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVR2NX24_1; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 219 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNR2NX24; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 224 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNR2NX24_0; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 224 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNR2NX24_1; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 224 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNRNX48_0; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 224 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNRNX48; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 225 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNX48; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 225 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNRN_2X64W; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 225 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNX48_0; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 225 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNRNX48_1; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 226 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRU2NX24; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 226 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRU2NX24_0; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 226 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRN_2X64W; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 226 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNX48_1; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 227 && + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get (insn) == 6) + return OPCODE_IVP_MOVVA16; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 227 && + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get (insn) == 4) + return OPCODE_IVP_MOVPA16; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 227 && + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get (insn) == 5) + return OPCODE_IVP_MOVQA16; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 227 && + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get (insn) == 7) + return OPCODE_IVP_MOVVA32; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 227 && + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRU2NX24_1; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 228 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 41) + return OPCODE_IVP_CVT64SNX48LL; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 228 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 40) + return OPCODE_IVP_CVT64SNX48LH; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 228 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 43) + return OPCODE_IVP_CVT64UN_2X96H; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 228 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 42) + return OPCODE_IVP_CVT64U96; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 229 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 40) + return OPCODE_IVP_CVT64UN_2X96L; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 229 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 42) + return OPCODE_IVP_PACKL2NX24; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 229 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 43) + return OPCODE_IVP_PACKL2NX24_1; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 229 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 41) + return OPCODE_IVP_PACKHN_2X64W; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 230 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 40) + return OPCODE_IVP_PACKLNX48; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 230 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 42) + return OPCODE_IVP_PACKMNX48; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 230 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 41) + return OPCODE_IVP_PACKLN_2X96; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 230 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 43) + return OPCODE_IVP_GATHERD2NX8_H; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 231 && + Field_fld_n2_s1_ld_7_0_Slot_n2_s1_ld_get (insn) == 173) + return OPCODE_IVP_SEQNX16; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 231 && + Field_fld_n2_s1_ld_7_0_Slot_n2_s1_ld_get (insn) == 172) + return OPCODE_IVP_SEQ2NX8; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 231 && + Field_fld_n2_s1_ld_7_0_Slot_n2_s1_ld_get (insn) == 174) + return OPCODE_IVP_SEQN_2X32; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 231 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 41) + return OPCODE_IVP_GATHERDNX16; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 231 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 42) + return OPCODE_IVP_GATHERDNX8S; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 231 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 40) + return OPCODE_IVP_GATHERD2NX8_L; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 232 && + Field_fld_n2_s1_ld_7_6_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINX16; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 5) + return OPCODE_IVP_CVT32S2NX24LL; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 57) + return OPCODE_IVP_CVT32S2NX24LH; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 49) + return OPCODE_IVP_CVT32S2NX24HL; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 41) + return OPCODE_IVP_CVT32S2NX24HH; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 61) + return OPCODE_IVP_CVT64SNX48HL; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 53) + return OPCODE_IVP_CVT64SNX48HH; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 9) + return OPCODE_IVP_CVT16S2NX24L; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_CVT16S2NX24H; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 21) + return OPCODE_IVP_CVT32SNX48L; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 13) + return OPCODE_IVP_CVT32SNX48H; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 17) + return OPCODE_IVP_CVT16U2NX24H; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 29) + return OPCODE_IVP_CVT32UNX48H; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 25) + return OPCODE_IVP_CVT16U2NX24L; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 33) + return OPCODE_IVP_CVT32S24; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 37) + return OPCODE_IVP_CVT32UNX48L; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get (insn) == 45) + return OPCODE_IVP_CVT64S48; + if (Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get (insn) == 233 && + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVA8; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 36) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 37) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 38) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 39) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 40) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 41) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 42) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 43) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 44) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 45) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 55 && + Field_fld_n2_s1_ld_12_10_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 55 && + Field_fld_n2_s1_ld_12_8_Slot_n2_s1_ld_get (insn) == 4) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 55 && + Field_fld_n2_s1_ld_12_4_Slot_n2_s1_ld_get (insn) == 96) + return OPCODE_IVP_LA_PP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 55 && + Field_fld_n2_s1_ld_12_2_Slot_n2_s1_ld_get (insn) == 448) + return OPCODE_IVP_MALIGN; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 57 && + Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 57 && + Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_get (insn) == 2) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 57 && + Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_get (insn) == 4) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 57 && + Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_get (insn) == 6) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get (insn) == 57 && + Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_get (insn) == 8) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_get (insn) == 12) + return OPCODE_ADDI; + if (Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_get (insn) == 14) + return OPCODE_L16SI; + if (Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_get (insn) == 15) + return OPCODE_L16UI; + if (Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_get (insn) == 16) + return OPCODE_L8UI; + if (Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_get (insn) == 17) + return OPCODE_MOVI; + if (Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_get (insn) == 2) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_get (insn) == 3) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_get (insn) == 4) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_get (insn) == 5) + return OPCODE_EXTUI; + if (Field_fld_n2_s1_ld_26_2_Slot_n2_s1_ld_get (insn) == 451009 && + Field_fld_n2_s1_ld_1_0_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_NOP; + if (Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (insn) == 7045) + return OPCODE_NSA; + if (Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (insn) == 7077) + return OPCODE_NSAU; + if (Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (insn) == 7109 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRN_2; + if (Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (insn) == 7109 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTRSN; + if (Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (insn) == 7141 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRS2N; + if (Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (insn) == 7141 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTRSN_2; + if (Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (insn) == 7366 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTR2N; + if (Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (insn) == 7367 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTRN; + if (Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get (insn) == 7368 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVBA1; + if (Field_fld_n2_s1_ld_26_9_Slot_n2_s1_ld_get (insn) == 3682 && + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get (insn) == 1) + return OPCODE_IVP_LTRN_2I; + return XTENSA_UNDEFINED; +} + +static int +Slot_f4_s1_ld_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f4_s1_ld_23_0_Slot_f4_s1_ld_get (insn) == 1672468) + return OPCODE_NOP; + if (Field_fld_f4_s1_ld_23_10_Slot_f4_s1_ld_get (insn) == 1720 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRNI; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 848 && + Field_fld_f4_s1_ld_4_0_Slot_f4_s1_ld_get (insn) == 25) + return OPCODE_IVP_MB; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 848 && + Field_fld_f4_s1_ld_4_0_Slot_f4_s1_ld_get (insn) == 9) + return OPCODE_IVP_EXTRACTBH; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 848 && + Field_fld_f4_s1_ld_4_0_Slot_f4_s1_ld_get (insn) == 10) + return OPCODE_IVP_NOTB1; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 849 && + Field_fld_f4_s1_ld_4_0_Slot_f4_s1_ld_get (insn) == 25) + return OPCODE_IVP_NOTB; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 849 && + Field_fld_f4_s1_ld_4_0_Slot_f4_s1_ld_get (insn) == 9) + return OPCODE_IVP_EXTRACTBL; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 852 && + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_ANDNOTB1; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 852 && + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get (insn) == 3) + return OPCODE_IVP_ORNOTB1; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 853 && + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get (insn) == 3) + return OPCODE_IVP_XORB; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 853 && + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_JOINB; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 854 && + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_ORB; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 854 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTR2NI; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 855 && + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_ANDB; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 855 && + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get (insn) == 1) + return OPCODE_IVP_ANDNOTB; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 855 && + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_ORNOTB; + if (Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get (insn) == 858 && + Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_get (insn) == 4) + return OPCODE_IVP_MOVAB1; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 376) + return OPCODE_ADD; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 377) + return OPCODE_ADDX2; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 378) + return OPCODE_ADDX4; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 379) + return OPCODE_ADDX8; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 380) + return OPCODE_AND; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 381) + return OPCODE_IVP_ADDMOD16U; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 382) + return OPCODE_MAX; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 383) + return OPCODE_MAXU; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 384) + return OPCODE_MIN; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 385) + return OPCODE_MINU; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 386) + return OPCODE_MOVEQZ; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 387) + return OPCODE_MOVGEZ; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 388) + return OPCODE_MOVLTZ; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 389) + return OPCODE_MOVNEZ; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 390) + return OPCODE_OR; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 391) + return OPCODE_SALT; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 392) + return OPCODE_SALTU; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 393) + return OPCODE_SUB; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 394) + return OPCODE_SUBX2; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 395) + return OPCODE_SUBX4; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 396) + return OPCODE_SUBX8; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 397) + return OPCODE_XOR; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 398) + return OPCODE_CLAMPS; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 399) + return OPCODE_SEXT; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 400) + return OPCODE_SRLI; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 401) + return OPCODE_IVP_SQZN; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 402) + return OPCODE_IVP_UNSQZN; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 403 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 1) + return OPCODE_IVP_LBN_2_IP; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 403 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LB2N_IP; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 424 && + Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_get (insn) == 7) + return OPCODE_ABS; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 424 && + Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_get (insn) == 8) + return OPCODE_SRL; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 425 && + Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_get (insn) == 7) + return OPCODE_SRA; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 426 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LBN_IP; + if (Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get (insn) == 428 && + Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_get (insn) == 4) + return OPCODE_SLL; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 168) + return OPCODE_SLLI; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 169) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 170) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 171) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 172) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 173) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 174) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 175) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 176) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 177) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 178) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 179) + return OPCODE_IVP_LB2N_I; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 180) + return OPCODE_IVP_LBN_2_I; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 181) + return OPCODE_IVP_LBN_I; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 182) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 183) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 184) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 185) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 186) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 187) + return OPCODE_SRAI; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 202 && + Field_fld_f4_s1_ld_7_7_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVPINT16; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 202 && + Field_fld_f4_s1_ld_7_7_Slot_f4_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVQINT16; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 203 && + Field_fld_f4_s1_ld_7_7_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINT16; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 203 && + Field_fld_f4_s1_ld_7_7_Slot_f4_s1_ld_get (insn) == 1) + return OPCODE_IVP_MOVVINT8; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 208 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVR2NX24; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 208 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVR2NX24_0; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 208 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVR2NX24_1; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 208 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNR2NX24; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 209 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNR2NX24_0; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 209 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNR2NX24_1; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 209 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNRNX48_0; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 209 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNRNX48; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 210 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRNX48; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 210 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRNRN_2X64W; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 210 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRNX48_0; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 210 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNRNX48_1; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 211 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_PACKVRU2NX24; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 211 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 3) + return OPCODE_IVP_PACKVRU2NX24_0; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 211 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 1) + return OPCODE_IVP_PACKVRN_2X64W; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 211 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRNX48_1; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 212 && + Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_get (insn) == 4) + return OPCODE_IVP_MOVVA16; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 212 && + Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_get (insn) == 5) + return OPCODE_IVP_MOVVA32; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 212 && + Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_get (insn) == 6) + return OPCODE_IVP_MOVVA8; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 212 && + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_PACKVRU2NX24_1; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_6_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVVINX16; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 22) + return OPCODE_IVP_CVT32S2NX24LL; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 29) + return OPCODE_IVP_CVT32S2NX24LH; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 21) + return OPCODE_IVP_CVT32S2NX24HL; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 28) + return OPCODE_IVP_CVT32S2NX24HH; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 25) + return OPCODE_IVP_CVT16S2NX24L; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 24) + return OPCODE_IVP_CVT16S2NX24H; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 23) + return OPCODE_IVP_CVT32SNX48L; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 30) + return OPCODE_IVP_CVT32SNX48H; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 26) + return OPCODE_IVP_CVT16U2NX24H; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 31) + return OPCODE_IVP_CVT32UNX48H; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 27) + return OPCODE_IVP_CVT16U2NX24L; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 214 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 20) + return OPCODE_IVP_CVT32S24; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 216 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 40) + return OPCODE_IVP_CVT32UNX48L; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 216 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 41) + return OPCODE_IVP_CVT64S48; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 216 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 42) + return OPCODE_IVP_CVT64U96; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 216 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 43) + return OPCODE_IVP_PACKHN_2X64W; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 217 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 40) + return OPCODE_IVP_PACKL2NX24; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 217 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 42) + return OPCODE_IVP_PACKLNX48; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 217 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 41) + return OPCODE_IVP_PACKL2NX24_1; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 217 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 43) + return OPCODE_IVP_PACKLN_2X96; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 218 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 40) + return OPCODE_IVP_PACKMNX48; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 218 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 43) + return OPCODE_IVP_GATHERDNX16; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 218 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 42) + return OPCODE_IVP_GATHERD2NX8_L; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 218 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 41) + return OPCODE_IVP_GATHERD2NX8_H; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 219 && + Field_fld_f4_s1_ld_7_0_Slot_f4_s1_ld_get (insn) == 165) + return OPCODE_IVP_SEQNX16; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 219 && + Field_fld_f4_s1_ld_7_0_Slot_f4_s1_ld_get (insn) == 164) + return OPCODE_IVP_SEQ2NX8; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 219 && + Field_fld_f4_s1_ld_7_0_Slot_f4_s1_ld_get (insn) == 166) + return OPCODE_IVP_SEQN_2X32; + if (Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get (insn) == 219 && + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get (insn) == 40) + return OPCODE_IVP_GATHERDNX8S; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 32) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 33) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 34) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 35) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 36) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 37) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 38) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 39) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 40) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 41) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 51 && + Field_fld_f4_s1_ld_12_10_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 51 && + Field_fld_f4_s1_ld_12_8_Slot_f4_s1_ld_get (insn) == 4) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 51 && + Field_fld_f4_s1_ld_12_4_Slot_f4_s1_ld_get (insn) == 80) + return OPCODE_IVP_LA_PP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 51 && + Field_fld_f4_s1_ld_12_2_Slot_f4_s1_ld_get (insn) == 324) + return OPCODE_IVP_MALIGN; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 54 && + Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 54 && + Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 54 && + Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_get (insn) == 4) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 54 && + Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_get (insn) == 6) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get (insn) == 54 && + Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_get (insn) == 8) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_f4_s1_ld_23_16_Slot_f4_s1_ld_get (insn) == 12) + return OPCODE_ADDI; + if (Field_fld_f4_s1_ld_23_16_Slot_f4_s1_ld_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_fld_f4_s1_ld_23_16_Slot_f4_s1_ld_get (insn) == 14) + return OPCODE_L32I; + if (Field_fld_f4_s1_ld_23_16_Slot_f4_s1_ld_get (insn) == 15) + return OPCODE_MOVI; + if (Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_get (insn) == 1) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_get (insn) == 2) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_get (insn) == 3) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_get (insn) == 4) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_get (insn) == 5) + return OPCODE_EXTUI; + if (Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_get (insn) == 6886 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTR2N; + if (Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_get (insn) == 6887 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRN; + if (Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_get (insn) == 6888 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRN_2; + if (Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_get (insn) == 6889 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRS2N; + if (Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_get (insn) == 6890 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRSN; + if (Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_get (insn) == 6891 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRSN_2; + if (Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_get (insn) == 6892 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_MOVBA1; + if (Field_fld_f4_s1_ld_23_9_Slot_f4_s1_ld_get (insn) == 3442 && + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get (insn) == 0) + return OPCODE_IVP_LTRN_2I; + return XTENSA_UNDEFINED; +} + +static int +Slot_f2_s0_ldst_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f2_s0_ldst_28_11_Slot_f2_s0_ldst_get (insn) == 2708 && + Field_fld_f2_s0_ldst_7_2_Slot_f2_s0_ldst_get (insn) == 7) + return OPCODE_SSAI; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1352 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 15) + return OPCODE_NEG; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1352 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 14) + return OPCODE_ABS; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1353 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 15) + return OPCODE_SRL; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1353 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 14) + return OPCODE_SRA; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1430) + return OPCODE_ADD; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1431) + return OPCODE_ADDX2; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1432) + return OPCODE_ADDX4; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1433) + return OPCODE_MAXU; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1434) + return OPCODE_ADDX8; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1435) + return OPCODE_MIN; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1436) + return OPCODE_AND; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1437) + return OPCODE_MINU; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1438) + return OPCODE_MAX; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1439) + return OPCODE_MOVEQZ; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1441) + return OPCODE_MOVGEZ; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1443) + return OPCODE_MOVLTZ; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1445) + return OPCODE_MOVNEZ; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1447) + return OPCODE_MUL16S; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1449) + return OPCODE_MUL16U; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1451) + return OPCODE_MULL; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1453) + return OPCODE_MULSH; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1455) + return OPCODE_MULUH; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1456) + return OPCODE_OR; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1457) + return OPCODE_SUB; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1458) + return OPCODE_SALT; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1459) + return OPCODE_SUBX2; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1460) + return OPCODE_SALTU; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1461) + return OPCODE_SUBX4; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1462) + return OPCODE_SRC; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1463) + return OPCODE_SUBX8; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1464) + return OPCODE_XOR; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1466) + return OPCODE_CLAMPS; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1468) + return OPCODE_SEXT; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1470) + return OPCODE_SRLI; + if (Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get (insn) == 1472 && + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (insn) == 7) + return OPCODE_SLL; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 672 && + Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_get (insn) == 3) + return OPCODE_IVP_GATHERANX16; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 673 && + Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_get (insn) == 3) + return OPCODE_IVP_GATHERANX8U; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 674 && + Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_get (insn) == 3) + return OPCODE_IVP_GATHERAN_2X32; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 675 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 12) + return OPCODE_IVP_MOVAV16; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 675 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 15) + return OPCODE_IVP_MOVAVU16; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 675 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 13) + return OPCODE_IVP_MOVAV32; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 675 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 14) + return OPCODE_IVP_MOVAV8; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 676 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 12) + return OPCODE_IVP_MOVAVU8; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 677 && + Field_fld_f2_s0_ldst_7_2_Slot_f2_s0_ldst_get (insn) == 3) + return OPCODE_IVP_MOVGATHERD; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 682) + return OPCODE_IVP_SS2NX8_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 683) + return OPCODE_IVP_SS2NX8_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 684) + return OPCODE_IVP_SSNX16_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 685) + return OPCODE_IVP_SSNX16_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 686) + return OPCODE_IVP_SSNX8S_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 687) + return OPCODE_IVP_SSNX8S_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 688) + return OPCODE_IVP_SSN_2X16S_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 689) + return OPCODE_IVP_SSN_2X16S_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 690) + return OPCODE_IVP_SSN_2X32_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 691) + return OPCODE_IVP_SSN_2X32_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 692) + return OPCODE_IVP_SV2NX8_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 693) + return OPCODE_IVP_SV2NX8_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 694) + return OPCODE_IVP_SVNX8S_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 695) + return OPCODE_IVP_SVNX8S_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 696) + return OPCODE_IVP_SVNX8U_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 697) + return OPCODE_IVP_SVNX8U_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 698) + return OPCODE_IVP_SVN_2X16S_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 699) + return OPCODE_IVP_SVN_2X16S_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 700) + return OPCODE_IVP_SVN_2X16U_X; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 701) + return OPCODE_IVP_SVN_2X16U_XP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 702) + return OPCODE_SLLI; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 703) + return OPCODE_IVP_SS2NX8_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 704) + return OPCODE_IVP_SSNX16_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 705) + return OPCODE_IVP_SSNX8S_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 706) + return OPCODE_IVP_SSN_2X16S_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 707) + return OPCODE_IVP_SSN_2X32_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 708) + return OPCODE_IVP_SV2NX8_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 709) + return OPCODE_IVP_SVNX8S_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 710) + return OPCODE_IVP_SVNX8U_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 711) + return OPCODE_IVP_SVN_2X16S_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 712) + return OPCODE_IVP_SVN_2X16U_IP; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 713) + return OPCODE_SRAI; + if (Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get (insn) == 714) + return OPCODE_IVP_EXTRN_2X32; + if (Field_fld_f2_s0_ldst_28_14_Slot_f2_s0_ldst_get (insn) == 340) + return OPCODE_IVP_EXTRNX16; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 158) + return OPCODE_IVP_SAV2NX8_XP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 159) + return OPCODE_IVP_SAVNX8S_XP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 160) + return OPCODE_IVP_SAVNX8U_XP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 161) + return OPCODE_IVP_SAVN_2X16S_XP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 162) + return OPCODE_IVP_SAVN_2X16U_XP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 163) + return OPCODE_IVP_SS2NX8_I; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 164) + return OPCODE_IVP_SSNX16_I; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 165) + return OPCODE_IVP_SSNX8S_I; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 166) + return OPCODE_IVP_SSN_2X16S_I; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 167) + return OPCODE_IVP_EXTR2NX8; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 180 && + Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_get (insn) == 15) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 181 && + Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_get (insn) == 15) + return OPCODE_IVP_SALIGN_IP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 184 && + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SA2NX8_IP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 184 && + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (insn) == 4) + return OPCODE_IVP_SANX8U_IP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 184 && + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (insn) == 6) + return OPCODE_IVP_SAN_2X16U_IP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 184 && + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (insn) == 5) + return OPCODE_IVP_SAN_2X16S_IP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 185 && + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SANX8S_IP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 192 && + Field_fld_f2_s0_ldst_12_4_Slot_f2_s0_ldst_get (insn) == 48) + return OPCODE_IVP_LA_PP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 192 && + Field_fld_f2_s0_ldst_12_4_Slot_f2_s0_ldst_get (insn) == 49) + return OPCODE_IVP_SAPOS_FP; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 192 && + Field_fld_f2_s0_ldst_12_2_Slot_f2_s0_ldst_get (insn) == 204) + return OPCODE_IVP_MALIGN; + if (Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get (insn) == 192 && + Field_fld_f2_s0_ldst_12_0_Slot_f2_s0_ldst_get (insn) == 820) + return OPCODE_IVP_ZALIGN; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 54) + return OPCODE_ADDI; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 55) + return OPCODE_ADDMI; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 56) + return OPCODE_IVP_SV2NX8T_X; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 57) + return OPCODE_IVP_SV2NX8T_XP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 58) + return OPCODE_IVP_SVNX8ST_X; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 59) + return OPCODE_IVP_SVNX8ST_XP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 60) + return OPCODE_IVP_SVNX8UT_X; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 61) + return OPCODE_IVP_SVNX8UT_XP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 62) + return OPCODE_IVP_SVN_2X16ST_X; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 63) + return OPCODE_IVP_SVN_2X16ST_XP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 64) + return OPCODE_IVP_SVN_2X16UT_X; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 65) + return OPCODE_IVP_SVN_2X16UT_XP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 66) + return OPCODE_L16SI; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 67) + return OPCODE_L16UI; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 68) + return OPCODE_L32I; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 69) + return OPCODE_L8UI; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 70) + return OPCODE_S16I; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 71) + return OPCODE_S32I; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 72) + return OPCODE_S8I; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 73) + return OPCODE_IVP_SV2NX8T_IP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 74) + return OPCODE_IVP_SVNX8ST_IP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 75) + return OPCODE_IVP_SVNX8UT_IP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 76) + return OPCODE_IVP_SVN_2X16ST_IP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 77) + return OPCODE_IVP_SVN_2X16UT_IP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 78) + return OPCODE_MOVI; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 84 && + Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_get (insn) == 1) + return OPCODE_IVP_GATHERANX8UT; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 84 && + Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_get (insn) == 0) + return OPCODE_IVP_GATHERANX16T; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 84 && + Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_get (insn) == 2) + return OPCODE_IVP_GATHERAN_2X32T; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 90 && + Field_fld_f2_s0_ldst_12_10_Slot_f2_s0_ldst_get (insn) == 2) + return OPCODE_IVP_SBN_I; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 90 && + Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_get (insn) == 14) + return OPCODE_IVP_SBN_IP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 90 && + Field_fld_f2_s0_ldst_12_10_Slot_f2_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SBN_2_I; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 90 && + Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_get (insn) == 13) + return OPCODE_IVP_SBN_2_IP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 90 && + Field_fld_f2_s0_ldst_12_10_Slot_f2_s0_ldst_get (insn) == 0) + return OPCODE_IVP_SB2N_I; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 90 && + Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_get (insn) == 12) + return OPCODE_IVP_SB2N_IP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 92 && + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 92 && + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get (insn) == 92 && + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_get (insn) == 20) + return OPCODE_IVP_SSN_2X32_I; + if (Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_get (insn) == 21) + return OPCODE_IVP_SV2NX8_I; + if (Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_get (insn) == 22) + return OPCODE_IVP_SVNX8S_I; + if (Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_get (insn) == 23) + return OPCODE_IVP_SVNX8U_I; + if (Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_get (insn) == 24) + return OPCODE_IVP_SVN_2X16S_I; + if (Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_get (insn) == 25) + return OPCODE_IVP_SVN_2X16U_I; + if (Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_get (insn) == 26) + return OPCODE_EXTUI; + if (Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get (insn) == 4) + return OPCODE_IVP_SV2NX8T_I; + if (Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get (insn) == 5) + return OPCODE_IVP_SVNX8ST_I; + if (Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get (insn) == 6) + return OPCODE_IVP_SVNX8UT_I; + if (Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SVN_2X16ST_I; + if (Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get (insn) == 8) + return OPCODE_IVP_SVN_2X16UT_I; + if (Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get (insn) == 9) + return OPCODE_J; + if (Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get (insn) == 24 && + Field_fld_f2_s0_ldst_15_15_Slot_f2_s0_ldst_get (insn) == 0 && + Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get (insn) == 24 && + Field_fld_f2_s0_ldst_15_15_Slot_f2_s0_ldst_get (insn) == 0 && + Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SALIGN_I; + if (Field_fld_f2_s0_ldst_28_20_Slot_f2_s0_ldst_get (insn) == 0) + return OPCODE_CONST16; + if (Field_fld_f2_s0_ldst_28_4_Slot_f2_s0_ldst_get (insn) == 393266) + return OPCODE_SSA8L; + if (Field_fld_f2_s0_ldst_28_4_Slot_f2_s0_ldst_get (insn) == 393267 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 5) + return OPCODE_IVP_SCATTERW; + if (Field_fld_f2_s0_ldst_28_4_Slot_f2_s0_ldst_get (insn) == 393778) + return OPCODE_SSL; + if (Field_fld_f2_s0_ldst_28_4_Slot_f2_s0_ldst_get (insn) == 393779 && + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get (insn) == 5) + return OPCODE_NOP; + if (Field_fld_f2_s0_ldst_28_4_Slot_f2_s0_ldst_get (insn) == 394290) + return OPCODE_SSR; + if (Field_fld_f2_s0_ldst_28_8_Slot_f2_s0_ldst_get (insn) == 24578) + return OPCODE_NSA; + if (Field_fld_f2_s0_ldst_28_8_Slot_f2_s0_ldst_get (insn) == 24610) + return OPCODE_NSAU; + return XTENSA_UNDEFINED; +} + +static int +Slot_n1_s0_ldst_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 1974 && + Field_fld_n1_s0_ldst_3_0_Slot_n1_s0_ldst_get (insn) == 13) + return OPCODE_NEG; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 1974 && + Field_fld_n1_s0_ldst_3_0_Slot_n1_s0_ldst_get (insn) == 12) + return OPCODE_ABS; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 1974 && + Field_fld_n1_s0_ldst_3_0_Slot_n1_s0_ldst_get (insn) == 15) + return OPCODE_SRL; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 1974 && + Field_fld_n1_s0_ldst_3_0_Slot_n1_s0_ldst_get (insn) == 14) + return OPCODE_SRA; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2040) + return OPCODE_MIN; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2041) + return OPCODE_MOVLTZ; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2042) + return OPCODE_MINU; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2043) + return OPCODE_MOVNEZ; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2044) + return OPCODE_MOVEQZ; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2045) + return OPCODE_MUL16S; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2046) + return OPCODE_MOVGEZ; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2047) + return OPCODE_MUL16U; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2049) + return OPCODE_ADD; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2051) + return OPCODE_ADDX2; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2053) + return OPCODE_ADDX4; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2055) + return OPCODE_ADDX8; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2057) + return OPCODE_AND; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2059) + return OPCODE_L32I_N; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2061) + return OPCODE_MAX; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2063) + return OPCODE_MAXU; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2064) + return OPCODE_MULL; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2065) + return OPCODE_S32I_N; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2066) + return OPCODE_MULSH; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2067) + return OPCODE_SALT; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2068) + return OPCODE_MULUH; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2069) + return OPCODE_SALTU; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2070) + return OPCODE_OR; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2071) + return OPCODE_SRC; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2072) + return OPCODE_SUB; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2073) + return OPCODE_XOR; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2074) + return OPCODE_SUBX2; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2075) + return OPCODE_CLAMPS; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2076) + return OPCODE_SUBX4; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2077) + return OPCODE_SEXT; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2078) + return OPCODE_SUBX8; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2079) + return OPCODE_SRLI; + if (Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get (insn) == 2082 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 14) + return OPCODE_SLL; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 980) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 981) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 982) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 983) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 984 && + Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_get (insn) == 3) + return OPCODE_IVP_GATHERANX16; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 985 && + Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_get (insn) == 3) + return OPCODE_IVP_GATHERANX8U; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 986 && + Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_get (insn) == 3) + return OPCODE_IVP_GATHERAN_2X32; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 992) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 993) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 994) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 995) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 996) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 997) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 998) + return OPCODE_IVP_SV2NX8_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 999) + return OPCODE_IVP_SV2NX8_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1000) + return OPCODE_IVP_SVNX8S_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1001) + return OPCODE_IVP_SVNX8S_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1002) + return OPCODE_IVP_SVNX8U_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1003) + return OPCODE_IVP_SVNX8U_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1004) + return OPCODE_IVP_SVN_2X16S_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1005) + return OPCODE_IVP_SVN_2X16S_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1006) + return OPCODE_IVP_SVN_2X16U_X; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1007) + return OPCODE_IVP_SVN_2X16U_XP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1008) + return OPCODE_SLLI; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1009) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1010) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1011) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1012) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1013) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1014) + return OPCODE_IVP_SV2NX8_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1015) + return OPCODE_IVP_SVNX8S_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1016) + return OPCODE_IVP_SVNX8U_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1017) + return OPCODE_IVP_SVN_2X16S_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1018) + return OPCODE_IVP_SVN_2X16U_IP; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1019) + return OPCODE_SRAI; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1040 && + Field_fld_n1_s0_ldst_7_6_Slot_n1_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SHFL2NX8I_S0; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1041 && + Field_fld_n1_s0_ldst_7_5_Slot_n1_s0_ldst_get (insn) == 6) + return OPCODE_IVP_MOVVV; + if (Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get (insn) == 1041 && + Field_fld_n1_s0_ldst_7_2_Slot_n1_s0_ldst_get (insn) == 60) + return OPCODE_IVP_MOVGATHERD; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 230) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 231) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 232) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 233) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 234) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 235) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 236) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 237) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 238) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 239) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 240) + return OPCODE_IVP_SAV2NX8_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 241) + return OPCODE_IVP_SAVNX8S_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 242) + return OPCODE_IVP_SAVNX8U_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 243) + return OPCODE_IVP_SAVN_2X16S_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 244) + return OPCODE_IVP_SAVN_2X16U_XP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 5) + return OPCODE_IVP_SA2NX8_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 1) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 2) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SANX8U_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 6) + return OPCODE_IVP_SANX8S_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 3) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 4) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 9) + return OPCODE_IVP_SAN_2X16U_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 260 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 8) + return OPCODE_IVP_SAN_2X16S_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 264 && + Field_fld_n1_s0_ldst_12_8_Slot_n1_s0_ldst_get (insn) == 2) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 264 && + Field_fld_n1_s0_ldst_12_8_Slot_n1_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SALIGN_IP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 266 && + Field_fld_n1_s0_ldst_12_4_Slot_n1_s0_ldst_get (insn) == 48) + return OPCODE_IVP_LA_PP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 266 && + Field_fld_n1_s0_ldst_12_4_Slot_n1_s0_ldst_get (insn) == 49) + return OPCODE_IVP_SAPOS_FP; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 266 && + Field_fld_n1_s0_ldst_12_2_Slot_n1_s0_ldst_get (insn) == 200) + return OPCODE_IVP_MALIGN; + if (Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get (insn) == 266 && + Field_fld_n1_s0_ldst_12_0_Slot_n1_s0_ldst_get (insn) == 804) + return OPCODE_IVP_ZALIGN; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 78) + return OPCODE_ADDI; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 79) + return OPCODE_ADDMI; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 80) + return OPCODE_IVP_LV2NX8T_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 81) + return OPCODE_IVP_LV2NX8T_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 82) + return OPCODE_IVP_LVNX8ST_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 83) + return OPCODE_IVP_LVNX8ST_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 84) + return OPCODE_IVP_LVNX8UT_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 85) + return OPCODE_IVP_LVNX8UT_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 86) + return OPCODE_IVP_LVN_2X16ST_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 87) + return OPCODE_IVP_LVN_2X16ST_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 88) + return OPCODE_IVP_LVN_2X16UT_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 89) + return OPCODE_IVP_LVN_2X16UT_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 90) + return OPCODE_IVP_SV2NX8T_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 91) + return OPCODE_IVP_SV2NX8T_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 92) + return OPCODE_IVP_SVNX8ST_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 93) + return OPCODE_IVP_SVNX8ST_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 94) + return OPCODE_IVP_SVNX8UT_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 95) + return OPCODE_IVP_SVNX8UT_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 96) + return OPCODE_IVP_SVN_2X16ST_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 97) + return OPCODE_IVP_SVN_2X16ST_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 98) + return OPCODE_IVP_SVN_2X16UT_X; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 99) + return OPCODE_IVP_SVN_2X16UT_XP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 100) + return OPCODE_L16SI; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 101) + return OPCODE_L16UI; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 102) + return OPCODE_L8UI; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 103) + return OPCODE_S16I; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 104) + return OPCODE_IVP_LV2NX8T_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 105) + return OPCODE_IVP_LVNX8ST_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 106) + return OPCODE_IVP_LVNX8UT_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 107) + return OPCODE_IVP_LVN_2X16ST_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 108) + return OPCODE_IVP_LVN_2X16UT_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 109) + return OPCODE_IVP_SV2NX8T_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 110) + return OPCODE_IVP_SVNX8ST_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 111) + return OPCODE_IVP_SVNX8UT_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 112) + return OPCODE_IVP_SVN_2X16ST_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 113) + return OPCODE_IVP_SVN_2X16UT_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 114) + return OPCODE_MOVI; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 123 && + Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_get (insn) == 1) + return OPCODE_IVP_GATHERANX8UT; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 123 && + Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_get (insn) == 0) + return OPCODE_IVP_GATHERANX16T; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 123 && + Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_get (insn) == 2) + return OPCODE_IVP_GATHERAN_2X32T; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 128 && + Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_get (insn) == 0 && + Field_fld_n1_s0_ldst_7_6_Slot_n1_s0_ldst_get (insn) == 2) + return OPCODE_IVP_SBN_I; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 128 && + Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_get (insn) == 0 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 14) + return OPCODE_IVP_SBN_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 128 && + Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_get (insn) == 0 && + Field_fld_n1_s0_ldst_7_6_Slot_n1_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SBN_2_I; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 128 && + Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_get (insn) == 0 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 13) + return OPCODE_IVP_SBN_2_IP; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 128 && + Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_get (insn) == 0 && + Field_fld_n1_s0_ldst_7_6_Slot_n1_s0_ldst_get (insn) == 0) + return OPCODE_IVP_SB2N_I; + if (Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get (insn) == 128 && + Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_get (insn) == 0 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 12) + return OPCODE_IVP_SB2N_IP; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 28) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 29) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 30) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 31) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 32) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 33) + return OPCODE_IVP_SV2NX8_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 34) + return OPCODE_IVP_SVNX8S_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 35) + return OPCODE_IVP_SVNX8U_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 36) + return OPCODE_IVP_SVN_2X16S_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 37) + return OPCODE_IVP_SVN_2X16U_I; + if (Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get (insn) == 38) + return OPCODE_EXTUI; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 4) + return OPCODE_IVP_LV2NX8T_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 5) + return OPCODE_IVP_LVNX8ST_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 6) + return OPCODE_IVP_LVNX8UT_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 7) + return OPCODE_IVP_LVN_2X16ST_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 8) + return OPCODE_IVP_LVN_2X16UT_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 9) + return OPCODE_IVP_SV2NX8T_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 10) + return OPCODE_IVP_SVNX8ST_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 11) + return OPCODE_IVP_SVNX8UT_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 12) + return OPCODE_IVP_SVN_2X16ST_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 13) + return OPCODE_IVP_SVN_2X16UT_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 33 && + Field_fld_n1_s0_ldst_15_15_Slot_n1_s0_ldst_get (insn) == 0 && + Field_fld_n1_s0_ldst_12_8_Slot_n1_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get (insn) == 33 && + Field_fld_n1_s0_ldst_15_15_Slot_n1_s0_ldst_get (insn) == 0 && + Field_fld_n1_s0_ldst_12_8_Slot_n1_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SALIGN_I; + if (Field_fld_n1_s0_ldst_26_2_Slot_n1_s0_ldst_get (insn) == 2179273 && + Field_fld_n1_s0_ldst_1_0_Slot_n1_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SCATTERW; + if (Field_fld_n1_s0_ldst_26_2_Slot_n1_s0_ldst_get (insn) == 2181321 && + Field_fld_n1_s0_ldst_1_0_Slot_n1_s0_ldst_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_n1_s0_ldst_26_20_Slot_n1_s0_ldst_get (insn) == 0) + return OPCODE_CONST16; + if (Field_fld_n1_s0_ldst_26_4_Slot_n1_s0_ldst_get (insn) == 533294) + return OPCODE_SSA8L; + if (Field_fld_n1_s0_ldst_26_4_Slot_n1_s0_ldst_get (insn) == 533310) + return OPCODE_SSL; + if (Field_fld_n1_s0_ldst_26_4_Slot_n1_s0_ldst_get (insn) == 533326) + return OPCODE_SSR; + if (Field_fld_n1_s0_ldst_26_8_Slot_n1_s0_ldst_get (insn) == 34050) + return OPCODE_NSA; + if (Field_fld_n1_s0_ldst_26_8_Slot_n1_s0_ldst_get (insn) == 34082) + return OPCODE_NSAU; + if (Field_fld_n1_s0_ldst_26_9_Slot_n1_s0_ldst_get (insn) == 16664 && + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get (insn) == 14) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_n2_s0_ldst_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_n2_s0_ldst_29_10_Slot_n2_s0_ldst_get (insn) == 10190 && + Field_fld_n2_s0_ldst_8_4_Slot_n2_s0_ldst_get (insn) == 15) + return OPCODE_SSAI; + if (Field_fld_n2_s0_ldst_29_11_Slot_n2_s0_ldst_get (insn) == 5089) + return OPCODE_IVP_GATHERANX16; + if (Field_fld_n2_s0_ldst_29_11_Slot_n2_s0_ldst_get (insn) == 5093) + return OPCODE_IVP_GATHERANX8U; + if (Field_fld_n2_s0_ldst_29_11_Slot_n2_s0_ldst_get (insn) == 5094 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 15) + return OPCODE_IVP_MOVGATHERD; + if (Field_fld_n2_s0_ldst_29_11_Slot_n2_s0_ldst_get (insn) == 5097) + return OPCODE_IVP_GATHERAN_2X32; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2545 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 15) + return OPCODE_SLL; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2620) + return OPCODE_ADD; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2621) + return OPCODE_ADDX4; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2622) + return OPCODE_ADDX2; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2623) + return OPCODE_ADDX8; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2624) + return OPCODE_AND; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2625) + return OPCODE_MIN; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2626) + return OPCODE_L32I_N; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2627) + return OPCODE_MINU; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2628) + return OPCODE_MAX; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2629) + return OPCODE_MOVEQZ; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2630) + return OPCODE_MAXU; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2631) + return OPCODE_MOVGEZ; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2632) + return OPCODE_MOVLTZ; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2633) + return OPCODE_MULL; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2634) + return OPCODE_MOVNEZ; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2635) + return OPCODE_MULSH; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2636) + return OPCODE_MUL16S; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2637) + return OPCODE_MULUH; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2638) + return OPCODE_MUL16U; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2639) + return OPCODE_OR; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2640) + return OPCODE_S32I_N; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2641) + return OPCODE_SUB; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2642) + return OPCODE_SALT; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2643) + return OPCODE_SUBX2; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2644) + return OPCODE_SALTU; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2645) + return OPCODE_SUBX4; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2646) + return OPCODE_SRC; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2647) + return OPCODE_SUBX8; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2648) + return OPCODE_XOR; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2649 && + Field_fld_n2_s0_ldst_3_0_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2649 && + Field_fld_n2_s0_ldst_3_0_Slot_n2_s0_ldst_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2649 && + Field_fld_n2_s0_ldst_3_0_Slot_n2_s0_ldst_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2649 && + Field_fld_n2_s0_ldst_3_0_Slot_n2_s0_ldst_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2650) + return OPCODE_CLAMPS; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2652) + return OPCODE_SEXT; + if (Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get (insn) == 2654) + return OPCODE_SRLI; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1206) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1207) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1280) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1281) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1282) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1283) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1284) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1285) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1286) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1287) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1288) + return OPCODE_IVP_SV2NX8_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1289) + return OPCODE_IVP_SV2NX8_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1290) + return OPCODE_IVP_SVNX8S_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1291) + return OPCODE_IVP_SVNX8S_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1292) + return OPCODE_IVP_SVNX8U_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1293) + return OPCODE_IVP_SVNX8U_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1294) + return OPCODE_IVP_SVN_2X16S_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1295) + return OPCODE_IVP_SVN_2X16S_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1296) + return OPCODE_IVP_SVN_2X16U_X; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1297) + return OPCODE_IVP_SVN_2X16U_XP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1298) + return OPCODE_SLLI; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1299) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1300) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1301) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1302) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1303) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1304) + return OPCODE_IVP_SV2NX8_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1305) + return OPCODE_IVP_SVNX8S_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1306) + return OPCODE_IVP_SVNX8U_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1307) + return OPCODE_IVP_SVN_2X16S_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1308) + return OPCODE_IVP_SVN_2X16U_IP; + if (Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get (insn) == 1309) + return OPCODE_SRAI; + if (Field_fld_n2_s0_ldst_29_14_Slot_n2_s0_ldst_get (insn) == 598) + return OPCODE_IVP_SCATTER2NX8_H; + if (Field_fld_n2_s0_ldst_29_14_Slot_n2_s0_ldst_get (insn) == 599) + return OPCODE_IVP_SCATTER2NX8_L; + if (Field_fld_n2_s0_ldst_29_14_Slot_n2_s0_ldst_get (insn) == 600) + return OPCODE_IVP_SCATTERNX16; + if (Field_fld_n2_s0_ldst_29_14_Slot_n2_s0_ldst_get (insn) == 601) + return OPCODE_IVP_SCATTERNX8U; + if (Field_fld_n2_s0_ldst_29_14_Slot_n2_s0_ldst_get (insn) == 602) + return OPCODE_IVP_SCATTERN_2X32; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 284) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 285) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 286) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 287) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 288) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 289) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 290) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 291) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 292) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 293) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 294) + return OPCODE_IVP_SAV2NX8_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 295) + return OPCODE_IVP_SAVNX8S_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 296) + return OPCODE_IVP_SAVNX8U_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 297) + return OPCODE_IVP_SAVN_2X16S_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 298) + return OPCODE_IVP_SAVN_2X16U_XP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 319 && + Field_fld_n2_s0_ldst_12_8_Slot_n2_s0_ldst_get (insn) == 8) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 319 && + Field_fld_n2_s0_ldst_12_8_Slot_n2_s0_ldst_get (insn) == 10) + return OPCODE_IVP_SALIGN_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 319 && + Field_fld_n2_s0_ldst_12_11_Slot_n2_s0_ldst_get (insn) == 2 && + Field_fld_n2_s0_ldst_8_0_Slot_n2_s0_ldst_get (insn) == 240) + return OPCODE_IVP_MALIGN; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 319 && + Field_fld_n2_s0_ldst_12_0_Slot_n2_s0_ldst_get (insn) == 4337) + return OPCODE_IVP_ZALIGN; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_9_5_Slot_n2_s0_ldst_get (insn) == 22) + return OPCODE_IVP_MOVVV; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_12_4_Slot_n2_s0_ldst_get (insn) == 46) + return OPCODE_IVP_LA_PP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_12_4_Slot_n2_s0_ldst_get (insn) == 110) + return OPCODE_IVP_SAPOS_FP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 5) + return OPCODE_IVP_SA2NX8_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 2) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SANX8U_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 6) + return OPCODE_IVP_SANX8S_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 3) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 4) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 9) + return OPCODE_IVP_SAN_2X16U_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 8) + return OPCODE_IVP_SAN_2X16S_IP; + if (Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get (insn) == 332 && + Field_fld_n2_s0_ldst_9_6_Slot_n2_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SHFL2NX8I_S0; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 104) + return OPCODE_ADDI; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 105) + return OPCODE_ADDMI; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 106) + return OPCODE_IVP_LV2NX8T_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 107) + return OPCODE_IVP_LV2NX8T_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 108) + return OPCODE_IVP_LVNX8ST_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 109) + return OPCODE_IVP_LVNX8ST_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 110) + return OPCODE_IVP_LVNX8UT_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 111) + return OPCODE_IVP_LVNX8UT_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 112) + return OPCODE_IVP_LVN_2X16ST_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 113) + return OPCODE_IVP_LVN_2X16ST_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 114) + return OPCODE_IVP_LVN_2X16UT_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 115) + return OPCODE_IVP_LVN_2X16UT_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 116) + return OPCODE_IVP_SV2NX8T_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 117) + return OPCODE_IVP_SV2NX8T_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 118) + return OPCODE_IVP_SVNX8ST_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 119) + return OPCODE_IVP_SVNX8ST_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 120) + return OPCODE_IVP_SVNX8UT_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 121) + return OPCODE_IVP_SVNX8UT_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 122) + return OPCODE_IVP_SVN_2X16ST_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 123) + return OPCODE_IVP_SVN_2X16ST_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 124) + return OPCODE_IVP_SVN_2X16UT_X; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 125) + return OPCODE_IVP_SVN_2X16UT_XP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 126) + return OPCODE_L16SI; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 127) + return OPCODE_L16UI; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 128) + return OPCODE_L8UI; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 129) + return OPCODE_S16I; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 130) + return OPCODE_S8I; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 131) + return OPCODE_IVP_LV2NX8T_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 132) + return OPCODE_IVP_LVNX8ST_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 133) + return OPCODE_IVP_LVNX8UT_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 134) + return OPCODE_IVP_LVN_2X16ST_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 135) + return OPCODE_IVP_LVN_2X16UT_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 136) + return OPCODE_IVP_SV2NX8T_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 137) + return OPCODE_IVP_SVNX8ST_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 138) + return OPCODE_IVP_SVNX8UT_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 139) + return OPCODE_IVP_SVN_2X16ST_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 140) + return OPCODE_IVP_SVN_2X16UT_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 141) + return OPCODE_MOVI; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 151 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 4) + return OPCODE_IVP_LENX16; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 151 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_IVP_EQNX16; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 151 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 7) + return OPCODE_IVP_LEUNX16; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 151 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 3) + return OPCODE_IVP_LE2NX8; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 151 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 151 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 6) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 151 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 5) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 151 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 2) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 152 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 6) + return OPCODE_IVP_LTNX16; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 152 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 5) + return OPCODE_IVP_LT2NX8; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 152 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 7) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 152 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 4) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 153 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 5) + return OPCODE_IVP_LTUNX16; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 153 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 7) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 153 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 4) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 153 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 6) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 154 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 0) + return OPCODE_IVP_NEQNX16; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 154 && + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 159 && + Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_get (insn) == 1 && + Field_fld_n2_s0_ldst_7_6_Slot_n2_s0_ldst_get (insn) == 2) + return OPCODE_IVP_SBN_I; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 159 && + Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_get (insn) == 1 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 14) + return OPCODE_IVP_SBN_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 159 && + Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_get (insn) == 1 && + Field_fld_n2_s0_ldst_7_6_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SBN_2_I; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 159 && + Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_get (insn) == 1 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 13) + return OPCODE_IVP_SBN_2_IP; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 159 && + Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_get (insn) == 1 && + Field_fld_n2_s0_ldst_7_6_Slot_n2_s0_ldst_get (insn) == 0) + return OPCODE_IVP_SB2N_I; + if (Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get (insn) == 159 && + Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_get (insn) == 1 && + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get (insn) == 12) + return OPCODE_IVP_SB2N_IP; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 36) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 37) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 38) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 39) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 40) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 41) + return OPCODE_IVP_SV2NX8_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 42) + return OPCODE_IVP_SVNX8S_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 43) + return OPCODE_IVP_SVNX8U_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 44) + return OPCODE_IVP_SVN_2X16S_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 45) + return OPCODE_IVP_SVN_2X16U_I; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 46) + return OPCODE_EXTUI; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 47) + return OPCODE_IVP_SCATTER2NX8T_H; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 48) + return OPCODE_IVP_SCATTER2NX8T_L; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 49) + return OPCODE_IVP_SCATTERNX16T; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 50) + return OPCODE_IVP_SCATTERNX8UT; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 51) + return OPCODE_IVP_SCATTERN_2X32T; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 76 && + Field_fld_n2_s0_ldst_13_11_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_IVP_GATHERANX8UT; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 76 && + Field_fld_n2_s0_ldst_13_11_Slot_n2_s0_ldst_get (insn) == 0) + return OPCODE_IVP_GATHERANX16T; + if (Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get (insn) == 76 && + Field_fld_n2_s0_ldst_13_11_Slot_n2_s0_ldst_get (insn) == 4) + return OPCODE_IVP_GATHERAN_2X32T; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 8) + return OPCODE_IVP_LV2NX8T_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 9) + return OPCODE_IVP_LVNX8ST_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 10) + return OPCODE_IVP_LVNX8UT_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 11) + return OPCODE_IVP_LVN_2X16ST_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 12) + return OPCODE_IVP_LVN_2X16UT_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 13) + return OPCODE_IVP_SV2NX8T_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 14) + return OPCODE_IVP_SVNX8ST_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 15) + return OPCODE_IVP_SVNX8UT_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 16) + return OPCODE_IVP_SVN_2X16ST_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 17) + return OPCODE_IVP_SVN_2X16UT_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 42 && + Field_fld_n2_s0_ldst_15_15_Slot_n2_s0_ldst_get (insn) == 0 && + Field_fld_n2_s0_ldst_12_8_Slot_n2_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get (insn) == 42 && + Field_fld_n2_s0_ldst_15_15_Slot_n2_s0_ldst_get (insn) == 0 && + Field_fld_n2_s0_ldst_12_8_Slot_n2_s0_ldst_get (insn) == 4) + return OPCODE_IVP_SALIGN_I; + if (Field_fld_n2_s0_ldst_29_20_Slot_n2_s0_ldst_get (insn) == 0) + return OPCODE_CONST16; + if (Field_fld_n2_s0_ldst_29_20_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SEL2NX8I_S0; + if (Field_fld_n2_s0_ldst_29_5_Slot_n2_s0_ldst_get (insn) == 326095 && + Field_fld_n2_s0_ldst_4_4_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_SSR; + if (Field_fld_n2_s0_ldst_29_5_Slot_n2_s0_ldst_get (insn) == 326119 && + Field_fld_n2_s0_ldst_4_4_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_SSA8L; + if (Field_fld_n2_s0_ldst_29_5_Slot_n2_s0_ldst_get (insn) == 326135 && + Field_fld_n2_s0_ldst_4_4_Slot_n2_s0_ldst_get (insn) == 1) + return OPCODE_SSL; + if (Field_fld_n2_s0_ldst_29_5_Slot_n2_s0_ldst_get (insn) == 326807 && + Field_fld_n2_s0_ldst_4_0_Slot_n2_s0_ldst_get (insn) == 17) + return OPCODE_IVP_SCATTERW; + if (Field_fld_n2_s0_ldst_29_5_Slot_n2_s0_ldst_get (insn) == 327063 && + Field_fld_n2_s0_ldst_4_0_Slot_n2_s0_ldst_get (insn) == 17) + return OPCODE_NOP; + if (Field_fld_n2_s0_ldst_29_8_Slot_n2_s0_ldst_get (insn) == 40844) + return OPCODE_NSA; + if (Field_fld_n2_s0_ldst_29_8_Slot_n2_s0_ldst_get (insn) == 40846) + return OPCODE_NSAU; + return XTENSA_UNDEFINED; +} + +static int +Slot_f4_s0_ld_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67018) + return OPCODE_ADD; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67019) + return OPCODE_ADDX2; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67020) + return OPCODE_ADDX4; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67021) + return OPCODE_AND; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67022) + return OPCODE_ADDX8; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67023) + return OPCODE_MAX; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67024) + return OPCODE_MAXU; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67025) + return OPCODE_MOVGEZ; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67026) + return OPCODE_MIN; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67027) + return OPCODE_MOVLTZ; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67028) + return OPCODE_MINU; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67029) + return OPCODE_MOVNEZ; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67030) + return OPCODE_MOVEQZ; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67031) + return OPCODE_MUL16S; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67032) + return OPCODE_MUL16U; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67033) + return OPCODE_OR; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67034) + return OPCODE_MULL; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67035) + return OPCODE_SALT; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67036) + return OPCODE_MULSH; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67037) + return OPCODE_SALTU; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67038) + return OPCODE_MULUH; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67039) + return OPCODE_SRC; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67040) + return OPCODE_SUB; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67041) + return OPCODE_XOR; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67042) + return OPCODE_SUBX2; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67043) + return OPCODE_CLAMPS; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67044) + return OPCODE_SUBX4; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67045) + return OPCODE_SEXT; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67046) + return OPCODE_SUBX8; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67047) + return OPCODE_SRLI; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67048 && + Field_fld_f4_s0_ld_3_0_Slot_f4_s0_ld_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67048 && + Field_fld_f4_s0_ld_3_0_Slot_f4_s0_ld_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67048 && + Field_fld_f4_s0_ld_3_0_Slot_f4_s0_ld_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67048 && + Field_fld_f4_s0_ld_3_0_Slot_f4_s0_ld_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get (insn) == 67056 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 7) + return OPCODE_SLL; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33468) + return OPCODE_IVP_LS2NX8_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33469) + return OPCODE_IVP_LS2NX8_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33470) + return OPCODE_IVP_LSNX16_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33471) + return OPCODE_IVP_LSNX16_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33472) + return OPCODE_IVP_LSNX8S_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33473) + return OPCODE_IVP_LSNX8S_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33474) + return OPCODE_IVP_LSN_2X16S_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33475) + return OPCODE_IVP_LSN_2X16S_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33476) + return OPCODE_IVP_LSN_2X32_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33477) + return OPCODE_IVP_LSN_2X32_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33478) + return OPCODE_IVP_LSR2NX8_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33479) + return OPCODE_IVP_LSR2NX8_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33480) + return OPCODE_IVP_LSRNX16_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33481) + return OPCODE_IVP_LSRNX16_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33482) + return OPCODE_IVP_LSRN_2X32_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33483) + return OPCODE_IVP_LSRN_2X32_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33484) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33485) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33486) + return OPCODE_IVP_LVNX8S_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33487) + return OPCODE_IVP_LVNX8S_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33488) + return OPCODE_IVP_LVNX8U_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33489) + return OPCODE_IVP_LVNX8U_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33490) + return OPCODE_IVP_LVN_2X16S_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33491) + return OPCODE_IVP_LVN_2X16S_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33492) + return OPCODE_IVP_LVN_2X16U_X; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33493) + return OPCODE_IVP_LVN_2X16U_XP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33494) + return OPCODE_SLLI; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33495) + return OPCODE_IVP_LS2NX8_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33496) + return OPCODE_IVP_LSNX16_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33497) + return OPCODE_IVP_LSNX8S_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33498) + return OPCODE_IVP_LSN_2X16S_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33499) + return OPCODE_IVP_LSN_2X32_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33500) + return OPCODE_IVP_LSR2NX8_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33501) + return OPCODE_IVP_LSRNX16_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33502) + return OPCODE_IVP_LSRN_2X32_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33503) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33504) + return OPCODE_IVP_LVNX8S_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33505) + return OPCODE_IVP_LVNX8U_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33506) + return OPCODE_IVP_LVN_2X16S_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33507) + return OPCODE_IVP_LVN_2X16U_IP; + if (Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get (insn) == 33508) + return OPCODE_SRAI; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8350) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8351) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8352) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8353) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8354) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8355) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8356) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8357) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8358) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8359) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8360) + return OPCODE_IVP_LS2NX8_I; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8361) + return OPCODE_IVP_LSNX16_I; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8362) + return OPCODE_IVP_LSNX8S_I; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8363) + return OPCODE_IVP_LSN_2X16S_I; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8364) + return OPCODE_IVP_LSR2NX8_I; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8365) + return OPCODE_IVP_LSRNX16_I; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8366) + return OPCODE_IVP_LSRN_2X32_I; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8382 && + Field_fld_f4_s0_ld_12_4_Slot_f4_s0_ld_get (insn) == 263) + return OPCODE_IVP_LA_PP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8382 && + Field_fld_f4_s0_ld_12_2_Slot_f4_s0_ld_get (insn) == 1308) + return OPCODE_IVP_MALIGN; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8382 && + Field_fld_f4_s0_ld_12_0_Slot_f4_s0_ld_get (insn) == 5236) + return OPCODE_IVP_ZALIGN; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8382 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 3) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8382 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 4) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8382 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 5) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8382 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 6) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8383 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 3) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get (insn) == 8384 && + Field_fld_f4_s0_ld_12_8_Slot_f4_s0_ld_get (insn) == 1) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4150) + return OPCODE_ADDI; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4151) + return OPCODE_ADDMI; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4152) + return OPCODE_IVP_LV2NX8T_X; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4153) + return OPCODE_IVP_LV2NX8T_XP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4154) + return OPCODE_IVP_LVNX8ST_X; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4155) + return OPCODE_IVP_LVNX8ST_XP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4156) + return OPCODE_IVP_LVNX8UT_X; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4157) + return OPCODE_IVP_LVNX8UT_XP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4158) + return OPCODE_IVP_LVN_2X16ST_X; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4159) + return OPCODE_IVP_LVN_2X16ST_XP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4160) + return OPCODE_IVP_LVN_2X16UT_X; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4161) + return OPCODE_IVP_LVN_2X16UT_XP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4162) + return OPCODE_L16SI; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4163) + return OPCODE_L16UI; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4164) + return OPCODE_L32I; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4165) + return OPCODE_L8UI; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4166) + return OPCODE_S16I; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4167) + return OPCODE_S32I; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4168) + return OPCODE_S8I; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4169) + return OPCODE_IVP_LV2NX8T_IP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4170) + return OPCODE_IVP_LVNX8ST_IP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4171) + return OPCODE_IVP_LVNX8UT_IP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4172) + return OPCODE_IVP_LVN_2X16ST_IP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4173) + return OPCODE_IVP_LVN_2X16UT_IP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4174) + return OPCODE_MOVI; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4191 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4191 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get (insn) == 4191 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_get (insn) == 2068) + return OPCODE_IVP_LSN_2X32_I; + if (Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_get (insn) == 2069) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_get (insn) == 2070) + return OPCODE_IVP_LVNX8S_I; + if (Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_get (insn) == 2071) + return OPCODE_IVP_LVNX8U_I; + if (Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_get (insn) == 2072) + return OPCODE_IVP_LVN_2X16S_I; + if (Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_get (insn) == 2073) + return OPCODE_IVP_LVN_2X16U_I; + if (Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_get (insn) == 2074) + return OPCODE_EXTUI; + if (Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_get (insn) == 1028) + return OPCODE_IVP_LV2NX8T_I; + if (Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_get (insn) == 1029) + return OPCODE_IVP_LVNX8ST_I; + if (Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_get (insn) == 1030) + return OPCODE_IVP_LVNX8UT_I; + if (Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_get (insn) == 1031) + return OPCODE_IVP_LVN_2X16ST_I; + if (Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_get (insn) == 1032) + return OPCODE_IVP_LVN_2X16UT_I; + if (Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_get (insn) == 1033) + return OPCODE_J; + if (Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_get (insn) == 1048 && + Field_fld_f4_s0_ld_15_15_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_12_8_Slot_f4_s0_ld_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_f4_s0_ld_31_20_Slot_f4_s0_ld_get (insn) == 256) + return OPCODE_CONST16; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_9_Slot_f4_s0_ld_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_9_Slot_f4_s0_ld_get (insn) == 1) + return OPCODE_BBSI_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 8) + return OPCODE_BEQ_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 14) + return OPCODE_BNE_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 10) + return OPCODE_BGE_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 12) + return OPCODE_BLT_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 9) + return OPCODE_BGEU_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 11) + return OPCODE_BLTU_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 5) + return OPCODE_BANY_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 4) + return OPCODE_BALL_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 13) + return OPCODE_BNALL_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 6) + return OPCODE_BBC_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 0 && + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get (insn) == 7) + return OPCODE_BBS_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_11_4_Slot_f4_s0_ld_get (insn) == 6) + return OPCODE_BEQZ_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_11_4_Slot_f4_s0_ld_get (insn) == 54) + return OPCODE_BNEZ_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_11_4_Slot_f4_s0_ld_get (insn) == 22) + return OPCODE_BGEZ_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_11_4_Slot_f4_s0_ld_get (insn) == 38) + return OPCODE_BLTZ_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 5) + return OPCODE_BNEI_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 1) + return OPCODE_BGEI_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 3) + return OPCODE_BLTI_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 2) + return OPCODE_BGEUI_W15; + if (Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get (insn) == 1 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 4) + return OPCODE_BLTUI_W15; + if (Field_fld_f4_s0_ld_31_7_Slot_f4_s0_ld_get (insn) == 2145826 && + Field_fld_f4_s0_ld_6_4_Slot_f4_s0_ld_get (insn) == 7) + return OPCODE_SSR; + if (Field_fld_f4_s0_ld_31_7_Slot_f4_s0_ld_get (insn) == 2145832 && + Field_fld_f4_s0_ld_6_0_Slot_f4_s0_ld_get (insn) == 117) + return OPCODE_IVP_SCATTERW; + if (Field_fld_f4_s0_ld_31_7_Slot_f4_s0_ld_get (insn) == 2145892 && + Field_fld_f4_s0_ld_6_4_Slot_f4_s0_ld_get (insn) == 7) + return OPCODE_SSA8L; + if (Field_fld_f4_s0_ld_31_7_Slot_f4_s0_ld_get (insn) == 2145894 && + Field_fld_f4_s0_ld_6_4_Slot_f4_s0_ld_get (insn) == 7) + return OPCODE_SSL; + if (Field_fld_f4_s0_ld_31_7_Slot_f4_s0_ld_get (insn) == 2145896 && + Field_fld_f4_s0_ld_6_0_Slot_f4_s0_ld_get (insn) == 117) + return OPCODE_NOP; + if (Field_fld_f4_s0_ld_31_8_Slot_f4_s0_ld_get (insn) == 1073409) + return OPCODE_NSA; + if (Field_fld_f4_s0_ld_31_8_Slot_f4_s0_ld_get (insn) == 1073441) + return OPCODE_NSAU; + if (Field_fld_f4_s0_ld_31_9_Slot_f4_s0_ld_get (insn) == 536457 && + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get (insn) == 7) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_n0_s0_ldst_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_n0_s0_ldst_22_0_Slot_n0_s0_ldst_get (insn) == 1933861) + return OPCODE_NOP; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 432) + return OPCODE_ADD; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 433) + return OPCODE_AND; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 434) + return OPCODE_ADDX2; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 435) + return OPCODE_L32I_N; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 436) + return OPCODE_ADDX4; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 437) + return OPCODE_MAX; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 438) + return OPCODE_ADDX8; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 439) + return OPCODE_MAXU; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 440) + return OPCODE_MIN; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 441) + return OPCODE_MOVLTZ; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 442) + return OPCODE_MINU; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 443) + return OPCODE_MOVNEZ; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 444) + return OPCODE_MOVEQZ; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 445) + return OPCODE_OR; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 446) + return OPCODE_MOVGEZ; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 447) + return OPCODE_S32I_N; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 448) + return OPCODE_SALT; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 449) + return OPCODE_SUBX4; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 450) + return OPCODE_SALTU; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 451) + return OPCODE_SUBX8; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 452) + return OPCODE_SUB; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 453) + return OPCODE_XOR; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 454) + return OPCODE_SUBX2; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 455) + return OPCODE_SEXT; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 456) + return OPCODE_SRLI; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 458 && + Field_fld_n0_s0_ldst_3_0_Slot_n0_s0_ldst_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 458 && + Field_fld_n0_s0_ldst_3_0_Slot_n0_s0_ldst_get (insn) == 0) + return OPCODE_SRA; + if (Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get (insn) == 466 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 14) + return OPCODE_SLL; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 196) + return OPCODE_IVP_LV2NX8_X; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 197) + return OPCODE_IVP_LV2NX8_XP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 198) + return OPCODE_IVP_SV2NX8_X; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 199) + return OPCODE_IVP_SV2NX8_XP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 200) + return OPCODE_IVP_SVNX8S_X; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 201) + return OPCODE_IVP_SVNX8S_XP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 202) + return OPCODE_IVP_SVNX8U_X; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 203) + return OPCODE_IVP_SVNX8U_XP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 204) + return OPCODE_IVP_SVN_2X16S_X; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 205) + return OPCODE_IVP_SVN_2X16S_XP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 206) + return OPCODE_IVP_SVN_2X16U_X; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 207) + return OPCODE_IVP_SVN_2X16U_XP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 208) + return OPCODE_SLLI; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 209) + return OPCODE_IVP_LV2NX8_IP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 210) + return OPCODE_IVP_SV2NX8_IP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 211) + return OPCODE_IVP_SVNX8S_IP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 212) + return OPCODE_IVP_SVNX8U_IP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 213) + return OPCODE_IVP_SVN_2X16S_IP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 214) + return OPCODE_IVP_SVN_2X16U_IP; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 215) + return OPCODE_SRAI; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 232 && + Field_fld_n0_s0_ldst_7_6_Slot_n0_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SHFL2NX8I_S0; + if (Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get (insn) == 233 && + Field_fld_n0_s0_ldst_7_5_Slot_n0_s0_ldst_get (insn) == 6) + return OPCODE_IVP_MOVVV; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 34) + return OPCODE_IVP_LA2NX8_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 35) + return OPCODE_IVP_LANX8S_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 36) + return OPCODE_IVP_LANX8U_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 37) + return OPCODE_IVP_LAN_2X16S_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 38) + return OPCODE_IVP_LAN_2X16U_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 39) + return OPCODE_IVP_LAV2NX8_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 40) + return OPCODE_IVP_LAVNX8S_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 41) + return OPCODE_IVP_LAVNX8U_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 42) + return OPCODE_IVP_LAVN_2X16S_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 43) + return OPCODE_IVP_LAVN_2X16U_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 44) + return OPCODE_IVP_SAV2NX8_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 45) + return OPCODE_IVP_SAVNX8S_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 46) + return OPCODE_IVP_SAVNX8U_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 47) + return OPCODE_IVP_SAVN_2X16S_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 48) + return OPCODE_IVP_SAVN_2X16U_XP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 57 && + Field_fld_n0_s0_ldst_12_12_Slot_n0_s0_ldst_get (insn) == 1 && + Field_fld_n0_s0_ldst_7_6_Slot_n0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LALIGN_I; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 57 && + Field_fld_n0_s0_ldst_12_12_Slot_n0_s0_ldst_get (insn) == 1 && + Field_fld_n0_s0_ldst_7_6_Slot_n0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SALIGN_I; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LA2NX8_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 5) + return OPCODE_IVP_SA2NX8_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_LANX8S_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 2) + return OPCODE_IVP_LANX8U_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 7) + return OPCODE_IVP_SANX8U_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 6) + return OPCODE_IVP_SANX8S_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 3) + return OPCODE_IVP_LAN_2X16S_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 4) + return OPCODE_IVP_LAN_2X16U_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 9) + return OPCODE_IVP_SAN_2X16U_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 58 && + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get (insn) == 8) + return OPCODE_IVP_SAN_2X16S_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 59 && + Field_fld_n0_s0_ldst_12_8_Slot_n0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LALIGN_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 59 && + Field_fld_n0_s0_ldst_12_8_Slot_n0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SALIGN_IP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 59 && + Field_fld_n0_s0_ldst_12_4_Slot_n0_s0_ldst_get (insn) == 32) + return OPCODE_IVP_LA_PP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 59 && + Field_fld_n0_s0_ldst_12_4_Slot_n0_s0_ldst_get (insn) == 33) + return OPCODE_IVP_SAPOS_FP; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 59 && + Field_fld_n0_s0_ldst_12_2_Slot_n0_s0_ldst_get (insn) == 136) + return OPCODE_IVP_MALIGN; + if (Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get (insn) == 59 && + Field_fld_n0_s0_ldst_12_0_Slot_n0_s0_ldst_get (insn) == 548) + return OPCODE_IVP_ZALIGN; + if (Field_fld_n0_s0_ldst_22_16_Slot_n0_s0_ldst_get (insn) == 14) + return OPCODE_ADDI; + if (Field_fld_n0_s0_ldst_22_16_Slot_n0_s0_ldst_get (insn) == 15) + return OPCODE_ADDMI; + if (Field_fld_n0_s0_ldst_22_16_Slot_n0_s0_ldst_get (insn) == 16) + return OPCODE_MOVI; + if (Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_get (insn) == 0) + return OPCODE_IVP_LV2NX8_I; + if (Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_get (insn) == 1) + return OPCODE_IVP_SV2NX8_I; + if (Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_get (insn) == 2) + return OPCODE_IVP_SVNX8S_I; + if (Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_get (insn) == 3) + return OPCODE_IVP_SVNX8U_I; + if (Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_get (insn) == 4) + return OPCODE_IVP_SVN_2X16S_I; + if (Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_get (insn) == 5) + return OPCODE_IVP_SVN_2X16U_I; + if (Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_get (insn) == 6) + return OPCODE_EXTUI; + return XTENSA_UNDEFINED; +} + +static int +Slot_f3_s4_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f3_s4_alu_23_0_Slot_f3_s4_alu_get (insn) == 5931392) + return OPCODE_NOP; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 144) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 145) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 146) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 147) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 148) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 149) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 150) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 151) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 152) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 153) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 154) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 155) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 156) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 157) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 158) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 159) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 160) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 161) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 162) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 163) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 164) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 165) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 166) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 167) + return OPCODE_IVP_MINNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 168) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 169) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 170) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 171) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 172) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 173) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 174) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 175) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 176) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 177) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 178) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 179) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 180) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 6) + return OPCODE_IVP_MOVVV; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 11) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 8) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 10) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 7) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 2) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 4) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 9) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_6_Slot_f3_s4_alu_get (insn) == 0) + return OPCODE_IVP_SHFL2NX8I_S4; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 3) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get (insn) == 181 && + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get (insn) == 5) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f3_s4_alu_23_16_Slot_f3_s4_alu_get (insn) == 160) + return OPCODE_MTK_AndPOPC; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 4) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 5) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 6) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 7) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 8) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 9) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 10) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 11) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 12) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 13) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 14) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 15) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 16) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 17) + return OPCODE_IVP_BSUBNORMNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 10) + return OPCODE_IVP_LTNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 4) + return OPCODE_IVP_LENX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 1) + return OPCODE_IVP_EQNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 16) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 13) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 7) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 9) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 3) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 15) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 12) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 6) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 11) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 5) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 2) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 17) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 14) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get (insn) == 23 && + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get (insn) == 8) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f3_s4_alu_23_20_Slot_f3_s4_alu_get (insn) == 0) + return OPCODE_IVP_SEL2NX8I_S4; + return XTENSA_UNDEFINED; +} + +static int +Slot_f11_s4_alu_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f11_s4_alu_24_0_Slot_f11_s4_alu_get (insn) == 4882752) + return OPCODE_NOP; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 112) + return OPCODE_IVP_ABSSSUBNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 113) + return OPCODE_IVP_ABSSUB2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 114) + return OPCODE_IVP_ABSSUBNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 115) + return OPCODE_IVP_ABSSUBU2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 116) + return OPCODE_IVP_ABSSUBUNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 117) + return OPCODE_IVP_ADD2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 118) + return OPCODE_IVP_ADDNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 119) + return OPCODE_IVP_ADDN_2X32; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 120) + return OPCODE_IVP_ADDSNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 121) + return OPCODE_IVP_AND2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 122) + return OPCODE_IVP_AVG2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 123) + return OPCODE_IVP_AVGNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 124) + return OPCODE_IVP_AVGR2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 125) + return OPCODE_IVP_AVGRNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 126) + return OPCODE_IVP_AVGRUNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 127) + return OPCODE_IVP_AVGUNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 128) + return OPCODE_IVP_MAX2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 129) + return OPCODE_IVP_MAXNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 130) + return OPCODE_IVP_MAXN_2X32; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 131) + return OPCODE_IVP_MAXU2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 132) + return OPCODE_IVP_MAXUNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 133) + return OPCODE_IVP_MAXUN_2X32; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 134) + return OPCODE_IVP_MIN2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 135) + return OPCODE_IVP_MINNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 136) + return OPCODE_IVP_MINN_2X32; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 137) + return OPCODE_IVP_MINU2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 138) + return OPCODE_IVP_MINUNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 139) + return OPCODE_IVP_MINUN_2X32; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 140) + return OPCODE_IVP_MULSGNNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 141) + return OPCODE_IVP_MULSGNN_2X32; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 142) + return OPCODE_IVP_MULSGNSNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 143) + return OPCODE_IVP_OR2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 144) + return OPCODE_IVP_SUB2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 145) + return OPCODE_IVP_SUBNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 146) + return OPCODE_IVP_SUBN_2X32; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 147) + return OPCODE_IVP_SUBSNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 148) + return OPCODE_IVP_XOR2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 4) + return OPCODE_IVP_MOVVV; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 9) + return OPCODE_IVP_NOT2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 6) + return OPCODE_IVP_NEGNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 8) + return OPCODE_IVP_NEGSNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 5) + return OPCODE_IVP_NEG2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 0) + return OPCODE_IVP_ABS2NX8; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 2) + return OPCODE_IVP_ABSN_2X32; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 7) + return OPCODE_IVP_NEGN_2X32; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 1) + return OPCODE_IVP_ABSNX16; + if (Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get (insn) == 149 && + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get (insn) == 3) + return OPCODE_IVP_ABSSNX16; + if (Field_fld_f11_s4_alu_24_16_Slot_f11_s4_alu_get (insn) == 75) + return OPCODE_MTK_AndPOPC; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 0) + return OPCODE_IVP_BADDNORMNX16; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 1) + return OPCODE_IVP_BMAX2NX8; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 2) + return OPCODE_IVP_BMAXNX16; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 3) + return OPCODE_IVP_BMAXN_2X32; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 4) + return OPCODE_IVP_BMAXU2NX8; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 5) + return OPCODE_IVP_BMAXUNX16; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 6) + return OPCODE_IVP_BMAXUN_2X32; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 7) + return OPCODE_IVP_BMIN2NX8; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 8) + return OPCODE_IVP_BMINNX16; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 9) + return OPCODE_IVP_BMINN_2X32; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 10) + return OPCODE_IVP_BMINU2NX8; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 11) + return OPCODE_IVP_BMINUNX16; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 12) + return OPCODE_IVP_BMINUN_2X32; + if (Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get (insn) == 13) + return OPCODE_IVP_BSUBNORMNX16; + return XTENSA_UNDEFINED; +} + +static int +Slot_n1_s2_mul_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_n1_s2_mul_25_1_Slot_n1_s2_mul_get (insn) == 3332098 && + Field_fld_n1_s2_mul_0_0_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1624) + return OPCODE_MOVNEZ; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1625) + return OPCODE_SUB; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1626) + return OPCODE_XOR; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1628 && + Field_fld_n1_s2_mul_7_4_Slot_n1_s2_mul_get (insn) == 4) + return OPCODE_SRL; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1732) + return OPCODE_ADD; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1733) + return OPCODE_ADDX2; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1734) + return OPCODE_ADDX4; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1735) + return OPCODE_ADDX8; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1752) + return OPCODE_OR; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1753) + return OPCODE_SUBX2; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1754) + return OPCODE_CLAMPS; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1860) + return OPCODE_AND; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1861) + return OPCODE_MAXU; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1862) + return OPCODE_MINU; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1863) + return OPCODE_MOVGEZ; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1880) + return OPCODE_SALT; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1881) + return OPCODE_SUBX4; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1882 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1988) + return OPCODE_MAX; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1989) + return OPCODE_MIN; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1990) + return OPCODE_MOVEQZ; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 1991) + return OPCODE_MOVLTZ; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 2008) + return OPCODE_SALTU; + if (Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get (insn) == 2009) + return OPCODE_SUBX8; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 397 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_LENX16; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 397 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 398 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 398 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 399 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEQNX16; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 401 && + Field_fld_n1_s2_mul_8_8_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_EXTRVRN_2X32; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 429 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQNX16; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 429 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 430 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTUNX16; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 430 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_LT2NX8; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 431 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 461 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 461 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 462 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_LTNX16; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 462 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 493 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEUNX16; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 493 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_LE2NX8; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 494 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get (insn) == 494 && + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 7 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULANX16PACKL; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 7 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULANX16PACKQ; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 7 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULSNX16PACKL; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 7 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULNX16PACKP; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 7 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULANX16PACKP; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 7 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULSNX16PACKP; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 7 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULNX16PACKL; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 7 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULNX16PACKQ; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 8 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSNX16PACKQ; + if (Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get (insn) == 10 && + Field_fld_n1_s2_mul_13_9_Slot_n1_s2_mul_get (insn) == 0 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 9) + return OPCODE_IVP_MOVVV; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 2 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULI2NX8X16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 2 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULAI2NX8X16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 2 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSI2NX8X16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 2 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSAI2NX8X16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 21 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_CVT24U2NX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_9_Slot_n1_s2_mul_get (insn) == 728 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_CVT24U32; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 21 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT24UNX32L; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 21 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 2) + return OPCODE_IVP_CVT24UNX32H; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_9_Slot_n1_s2_mul_get (insn) == 728 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 2) + return OPCODE_IVP_CVT48UNX32L; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 21 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 4) + return OPCODE_IVP_CVT48UNX32; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_9_Slot_n1_s2_mul_get (insn) == 728 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_CVT48U64; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 21 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 6) + return OPCODE_IVP_CVT48UN_2X64L; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 21 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 5) + return OPCODE_IVP_CVT48UN_2X64H; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 21 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 7) + return OPCODE_IVP_CVT96UN_2X64; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_9_Slot_n1_s2_mul_get (insn) == 728 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT96U64; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUU2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUUA2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUS2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUSA2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 23 && + Field_fld_n1_s2_mul_8_4_Slot_n1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSA2N8XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 23 && + Field_fld_n1_s2_mul_8_4_Slot_n1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUS2N8XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 23 && + Field_fld_n1_s2_mul_8_4_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULA2N8XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 23 && + Field_fld_n1_s2_mul_8_4_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL2N8XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_6_Slot_n1_s2_mul_get (insn) == 5824 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 4) + return OPCODE_IVP_MOVWW; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULNX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULANX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUNX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUUANX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUSNX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSANX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 16 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 14) + return OPCODE_IVP_MUL2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 16 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULA2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 16 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 8) + return OPCODE_IVP_ADDW2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 16 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 9) + return OPCODE_IVP_ADDWA2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 16 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 10) + return OPCODE_IVP_ADDWS2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 16 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 11) + return OPCODE_IVP_ADDWU2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 16 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 12) + return OPCODE_IVP_ADDWUA2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 16 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 13) + return OPCODE_IVP_ADDWUS2NX8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULSNX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUUSNX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUSSNX16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUUN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUSN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULSUN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUUN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUSN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULSUN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUUHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUSHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULSUHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULAN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUUAN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUSAN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULSUAN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULAHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUUAHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSAHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULSUAHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULAN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUUAN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUSAN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULSUAN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULSHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUUSHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUSSHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULSUSHN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULSN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUUSN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUSSN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULSUSN_2X16X32_0; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 18 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULSN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 21 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUUSN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 20 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSSN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 19 && + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSUSN_2X16X32_1; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULPN16XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULPAN16XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUSPN16XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUSPAN16XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULP2N8XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULPA2N8XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSP2N8XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUSPA2N8XR16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL4T2N8XR8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MUL4TA2N8XR8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUS4T2N8XR8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUS4TA2N8XR8; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 3 && + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get (insn) == 12) + return OPCODE_ADDI; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 4 && + Field_fld_n1_s2_mul_13_9_Slot_n1_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULI2NR8X16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 4 && + Field_fld_n1_s2_mul_13_9_Slot_n1_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULAI2NR8X16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 4 && + Field_fld_n1_s2_mul_13_9_Slot_n1_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSI2NR8X16; + if (Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get (insn) == 4 && + Field_fld_n1_s2_mul_13_9_Slot_n1_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSAI2NR8X16; + return XTENSA_UNDEFINED; +} + +static int +Slot_f0_s2_mul_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 597) + return OPCODE_SUBX2; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 620 && + Field_fld_f0_s2_mul_7_4_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_ABS; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 725) + return OPCODE_SUBX4; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 726) + return OPCODE_ADD; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 727) + return OPCODE_ADDX2; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 748 && + Field_fld_f0_s2_mul_7_4_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_SRA; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 848 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 852) + return OPCODE_ADDX4; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 853) + return OPCODE_SUBX8; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 854) + return OPCODE_AND; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 855) + return OPCODE_SRLI; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 876 && + Field_fld_f0_s2_mul_7_4_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 980) + return OPCODE_ADDX8; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 981) + return OPCODE_XOR; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 982) + return OPCODE_OR; + if (Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get (insn) == 983) + return OPCODE_SUB; + if (Field_fld_f0_s2_mul_26_13_Slot_f0_s2_mul_get (insn) == 299) + return OPCODE_SLLI; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 141 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_LENX16; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 141 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 142 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 142 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 143 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 173 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQNX16; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 173 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 174 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 174 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 175 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 205 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 205 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 206 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_LTNX16; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 206 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 237 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 237 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 238 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get (insn) == 238 && + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f0_s2_mul_26_2_Slot_f0_s2_mul_get (insn) == 630915 && + Field_fld_f0_s2_mul_1_0_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_f0_s2_mul_26_20_Slot_f0_s2_mul_get (insn) == 2 && + Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_get (insn) == 84) + return OPCODE_SRAI; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULI2NX8X16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULAI2NX8X16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSI2NX8X16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSAI2NX8X16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 26 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_CVT24U2NX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 15) + return OPCODE_IVP_CVT24S2NX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_get (insn) == 104 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 8) + return OPCODE_IVP_CVT24U32; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 26 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 2) + return OPCODE_IVP_CVT24UNX32L; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 26 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_CVT24UNX32H; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_get (insn) == 104 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 11) + return OPCODE_IVP_CVT48UNX32L; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 26 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 4) + return OPCODE_IVP_CVT48UNX32; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_get (insn) == 104 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 9) + return OPCODE_IVP_CVT48SNX32L; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 26 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT48SNX32; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_get (insn) == 104 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 10) + return OPCODE_IVP_CVT48U64; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 26 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 6) + return OPCODE_IVP_CVT48UN_2X64L; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 26 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 5) + return OPCODE_IVP_CVT48UN_2X64H; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 26 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 7) + return OPCODE_IVP_CVT96UN_2X64; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_get (insn) == 104 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT96U64; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUU2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUA2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUS2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUSA2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 27 && + Field_fld_f0_s2_mul_11_8_Slot_f0_s2_mul_get (insn) == 3 && + Field_fld_f0_s2_mul_4_4_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUSA2N8XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 27 && + Field_fld_f0_s2_mul_11_8_Slot_f0_s2_mul_get (insn) == 2 && + Field_fld_f0_s2_mul_4_4_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUS2N8XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 27 && + Field_fld_f0_s2_mul_11_8_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_4_4_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULA2N8XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 27 && + Field_fld_f0_s2_mul_11_8_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_4_4_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL2N8XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_9_Slot_f0_s2_mul_get (insn) == 832 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 13) + return OPCODE_IVP_MOVWW; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULANX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUUNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUUANX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUSANX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 4) + return OPCODE_IVP_MUL2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULA2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 20 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 8) + return OPCODE_IVP_ADDW2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 20 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 9) + return OPCODE_IVP_ADDWA2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 20 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 12) + return OPCODE_IVP_ADDWS2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 20 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 14) + return OPCODE_IVP_ADDWU2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 20 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 15) + return OPCODE_IVP_ADDWUA2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 2) + return OPCODE_IVP_ADDWUS2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULSNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUUSNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUSSNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUUN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULSUN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUUN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUSN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULSUN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUUHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUSHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULSUHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULAN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUUAN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUSAN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULSUAN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULAHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUUAHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUSAHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULSUAHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULAN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUUAN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUSAN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSUAN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULSHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUUSHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUSSHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULSUSHN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULSN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUUSN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSSN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULSUSN_2X16X32_0; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULSN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUUSN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 24 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSSN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 23 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULSUSN_2X16X32_1; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULPN16XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULPAN16XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUSPN16XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUSPAN16XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULP2N8XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULPA2N8XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSP2N8XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUSPA2N8XR16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL4T2N8XR8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_MUL4TA2N8XR8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUS4T2N8XR8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUS4TA2N8XR8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 20 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 11) + return OPCODE_IVP_ADDWNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 20 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 10) + return OPCODE_IVP_ADDWANX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 20 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 13) + return OPCODE_IVP_ADDWSNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_ADDWUNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADDWUANX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 22 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 3) + return OPCODE_IVP_ADDWUSNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 10) + return OPCODE_IVP_SUBWNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 9) + return OPCODE_IVP_SUBWANX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 14) + return OPCODE_IVP_SUBWUNX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 13) + return OPCODE_IVP_SUBWUANX16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 7) + return OPCODE_IVP_SUBW2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 8) + return OPCODE_IVP_SUBWA2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWU2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 25 && + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get (insn) == 12) + return OPCODE_IVP_SUBWUA2NX8; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 1 && + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get (insn) == 12) + return OPCODE_ADDI; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 2 && + Field_fld_f0_s2_mul_13_12_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULI2NR8X16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 2 && + Field_fld_f0_s2_mul_13_12_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULAI2NR8X16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 2 && + Field_fld_f0_s2_mul_13_12_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSI2NR8X16; + if (Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get (insn) == 2 && + Field_fld_f0_s2_mul_13_12_Slot_f0_s2_mul_get (insn) == 0 && + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSAI2NR8X16; + return XTENSA_UNDEFINED; +} + +static int +Slot_f3_s2_mul_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f3_s2_mul_21_0_Slot_f3_s2_mul_get (insn) == 1703951) + return OPCODE_NOP; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 337) + return OPCODE_SUBX2; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 341) + return OPCODE_SUBX4; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 342) + return OPCODE_ADD; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 343) + return OPCODE_ADDX2; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 344) + return OPCODE_ADDX4; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 345) + return OPCODE_SUBX8; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 346) + return OPCODE_AND; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 347) + return OPCODE_SRLI; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 348) + return OPCODE_ADDX8; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 349) + return OPCODE_XOR; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 350) + return OPCODE_OR; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 351) + return OPCODE_SUB; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 432 && + Field_fld_f3_s2_mul_7_4_Slot_f3_s2_mul_get (insn) == 10) + return OPCODE_SRL; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 432 && + Field_fld_f3_s2_mul_7_4_Slot_f3_s2_mul_get (insn) == 8) + return OPCODE_SRA; + if (Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get (insn) == 433 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_f3_s2_mul_21_13_Slot_f3_s2_mul_get (insn) == 169) + return OPCODE_SLLI; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 52 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_LENX16; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 52 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 53 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQNX16; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 53 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 54 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 54 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 55 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 55 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 56 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 56 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 57 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 57 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 58 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_LTNX16; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 58 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 59 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 59 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 60 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get (insn) == 61 && + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f3_s2_mul_21_15_Slot_f3_s2_mul_get (insn) == 42 && + Field_fld_f3_s2_mul_13_12_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_SRAI; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL4T2N8XR8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_MUL4TA2N8XR8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULP2N8XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULPA2N8XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULPAN16XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULPN16XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUS4T2N8XR8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUS4TA2N8XR8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSP2N8XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUSPA2N8XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUSPAN16XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUSPN16XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 12) + return OPCODE_ADDI; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 20 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 8) + return OPCODE_IVP_ADDW2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 20 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 9) + return OPCODE_IVP_ADDWA2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 20 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 12) + return OPCODE_IVP_ADDWS2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 20 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 14) + return OPCODE_IVP_ADDWU2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 20 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 15) + return OPCODE_IVP_ADDWUA2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 20 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 11) + return OPCODE_IVP_ADDWNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 20 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 10) + return OPCODE_IVP_ADDWANX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 20 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 13) + return OPCODE_IVP_ADDWSNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULANX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 4) + return OPCODE_IVP_MUL2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULA2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 2) + return OPCODE_IVP_ADDWUS2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULSNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULAN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULAHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULAN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULSHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_ADDWUNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADDWUANX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 22 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 3) + return OPCODE_IVP_ADDWUSNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUS2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUSA2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUSANX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULSUN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULSUN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULSUHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUSAN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULSUAN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUSAHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULSUAHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSUAN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULSUSHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULSN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULSUSN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULSN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 23 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULSUSN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUU2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUA2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUUANX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUSSNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUSN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUUHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUSHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUUAN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUUAHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUUAN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUSAN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUSSHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSSN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 24 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSSN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 15) + return OPCODE_IVP_CVT24S2NX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUUNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUUSNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUUN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUUN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUUSHN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUUSN_2X16X32_0; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUUSN_2X16X32_1; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 10) + return OPCODE_IVP_SUBWNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 9) + return OPCODE_IVP_SUBWANX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 14) + return OPCODE_IVP_SUBWUNX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 13) + return OPCODE_IVP_SUBWUANX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 7) + return OPCODE_IVP_SUBW2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 8) + return OPCODE_IVP_SUBWA2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWU2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 25 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 12) + return OPCODE_IVP_SUBWUA2NX8; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_CVT24U2NX16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_11_8_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_get (insn) == 8) + return OPCODE_IVP_CVT24U32; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 2) + return OPCODE_IVP_CVT24UNX32L; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_CVT24UNX32H; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_11_8_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_get (insn) == 11) + return OPCODE_IVP_CVT48UNX32L; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 4) + return OPCODE_IVP_CVT48UNX32; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_11_8_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_get (insn) == 9) + return OPCODE_IVP_CVT48SNX32L; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT48SNX32; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_11_8_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_get (insn) == 10) + return OPCODE_IVP_CVT48U64; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 6) + return OPCODE_IVP_CVT48UN_2X64L; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 5) + return OPCODE_IVP_CVT48UN_2X64H; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get (insn) == 7) + return OPCODE_IVP_CVT96UN_2X64; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_11_8_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_get (insn) == 12) + return OPCODE_IVP_CVT96U64; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 26 && + Field_fld_f3_s2_mul_13_7_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_get (insn) == 14) + return OPCODE_IVP_MOVWW; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 27 && + Field_fld_f3_s2_mul_13_12_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_7_5_Slot_f3_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSA2N8XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 27 && + Field_fld_f3_s2_mul_13_12_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_7_5_Slot_f3_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUS2N8XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 27 && + Field_fld_f3_s2_mul_13_12_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_7_5_Slot_f3_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULA2N8XR16; + if (Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get (insn) == 27 && + Field_fld_f3_s2_mul_13_12_Slot_f3_s2_mul_get (insn) == 0 && + Field_fld_f3_s2_mul_7_5_Slot_f3_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL2N8XR16; + return XTENSA_UNDEFINED; +} + +static int +Slot_f11_s2_mul_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f11_s2_mul_22_0_Slot_f11_s2_mul_get (insn) == 1392651) + return OPCODE_NOP; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 248 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 258) + return OPCODE_ADDX4; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 259) + return OPCODE_SRC; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 262) + return OPCODE_ADDX8; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 263) + return OPCODE_SUB; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 265) + return OPCODE_ADD; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 266) + return OPCODE_AND; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 267) + return OPCODE_SUBX2; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 269) + return OPCODE_ADDX2; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 270) + return OPCODE_OR; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 271) + return OPCODE_SUBX4; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 352) + return OPCODE_SUBX8; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 356) + return OPCODE_XOR; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 360) + return OPCODE_SRLI; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 364 && + Field_fld_f11_s2_mul_7_4_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 364 && + Field_fld_f11_s2_mul_7_4_Slot_f11_s2_mul_get (insn) == 4) + return OPCODE_SRL; + if (Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get (insn) == 364 && + Field_fld_f11_s2_mul_7_4_Slot_f11_s2_mul_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_f11_s2_mul_22_13_Slot_f11_s2_mul_get (insn) == 128) + return OPCODE_SLLI; + if (Field_fld_f11_s2_mul_22_13_Slot_f11_s2_mul_get (insn) == 130) + return OPCODE_IVP_EXTRVRN_2X32; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 52 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_LENX16; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 52 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQ2NX8; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 53 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQNX16; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 53 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEN_2X32; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 54 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEU2NX8; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 54 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_EQN_2X32; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 55 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_LEUNX16; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 55 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_LE2NX8; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 56 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTU2NX8; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 56 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_LEUN_2X32; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 57 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTUNX16; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 57 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_LT2NX8; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 58 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_LTNX16; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 58 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_LTUN_2X32; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 59 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_NEQ2NX8; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 59 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_LTN_2X32; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 60 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEQNX16; + if (Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get (insn) == 61 && + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_NEQN_2X32; + if (Field_fld_f11_s2_mul_22_15_Slot_f11_s2_mul_get (insn) == 33 && + Field_fld_f11_s2_mul_13_12_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_SRAI; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL4T2N8XR8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_MUL4TA2N8XR8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULP2N8XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULPA2N8XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULPAN16XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULPN16XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUS4T2N8XR8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUS4TA2N8XR8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSP2N8XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUSPA2N8XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUSPAN16XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUSPN16XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 12) + return OPCODE_ADDI; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 15 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 8) + return OPCODE_IVP_ADDW2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 15 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 9) + return OPCODE_IVP_ADDWA2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 15 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 12) + return OPCODE_IVP_ADDWS2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 15 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 14) + return OPCODE_IVP_ADDWU2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 15 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 15) + return OPCODE_IVP_ADDWUA2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 15 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 11) + return OPCODE_IVP_ADDWNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 15 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 10) + return OPCODE_IVP_ADDWANX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 15 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 13) + return OPCODE_IVP_ADDWSNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULANX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 4) + return OPCODE_IVP_MUL2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULA2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 2) + return OPCODE_IVP_ADDWUS2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULSNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULAN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULAHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULAN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULSHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_ADDWUNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_ADDWUANX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 17 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 3) + return OPCODE_IVP_ADDWUSNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUS2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUSA2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUSANX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULSUN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULSUN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULSUHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUSAN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULSUAN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUSAHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULSUAHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULSUAN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULSUSHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULSN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULSUSN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULSN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 18 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULSUSN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUU2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUA2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 12) + return OPCODE_IVP_MULUUANX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUSNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUSSNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUSN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 15) + return OPCODE_IVP_MULUUHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUSHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 13) + return OPCODE_IVP_MULUUAN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUUAHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 14) + return OPCODE_IVP_MULUUAN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUSAN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUSSHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSSN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 19 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUSSN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 15) + return OPCODE_IVP_CVT24S2NX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULUUNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUUSNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULUUN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUUN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUUSHN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUUSN_2X16X32_0; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUUSN_2X16X32_1; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 10) + return OPCODE_IVP_SUBWNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 9) + return OPCODE_IVP_SUBWANX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 14) + return OPCODE_IVP_SUBWUNX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 13) + return OPCODE_IVP_SUBWUANX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 7) + return OPCODE_IVP_SUBW2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 8) + return OPCODE_IVP_SUBWA2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 11) + return OPCODE_IVP_SUBWU2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 20 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 12) + return OPCODE_IVP_SUBWUA2NX8; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_CVT24U2NX16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_11_8_Slot_f11_s2_mul_get (insn) == 0 && + Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_get (insn) == 8) + return OPCODE_IVP_CVT24U32; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 2) + return OPCODE_IVP_CVT24UNX32L; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_CVT24UNX32H; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_11_8_Slot_f11_s2_mul_get (insn) == 0 && + Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_get (insn) == 25) + return OPCODE_IVP_CVT48UNX32L; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 4) + return OPCODE_IVP_CVT48UNX32; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_11_8_Slot_f11_s2_mul_get (insn) == 0 && + Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_get (insn) == 24) + return OPCODE_IVP_CVT48SNX32L; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 3) + return OPCODE_IVP_CVT48SNX32; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_11_8_Slot_f11_s2_mul_get (insn) == 0 && + Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_get (insn) == 9) + return OPCODE_IVP_CVT48U64; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 6) + return OPCODE_IVP_CVT48UN_2X64L; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 5) + return OPCODE_IVP_CVT48UN_2X64H; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 7) + return OPCODE_IVP_CVT96UN_2X64; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_11_8_Slot_f11_s2_mul_get (insn) == 0 && + Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_get (insn) == 10) + return OPCODE_IVP_CVT96U64; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 21 && + Field_fld_f11_s2_mul_13_7_Slot_f11_s2_mul_get (insn) == 32 && + Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_get (insn) == 11) + return OPCODE_IVP_MOVWW; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 22 && + Field_fld_f11_s2_mul_13_12_Slot_f11_s2_mul_get (insn) == 1 && + Field_fld_f11_s2_mul_7_5_Slot_f11_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULUSA2N8XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 22 && + Field_fld_f11_s2_mul_13_12_Slot_f11_s2_mul_get (insn) == 1 && + Field_fld_f11_s2_mul_7_5_Slot_f11_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULUS2N8XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 22 && + Field_fld_f11_s2_mul_13_12_Slot_f11_s2_mul_get (insn) == 1 && + Field_fld_f11_s2_mul_7_5_Slot_f11_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULA2N8XR16; + if (Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get (insn) == 22 && + Field_fld_f11_s2_mul_13_12_Slot_f11_s2_mul_get (insn) == 1 && + Field_fld_f11_s2_mul_7_5_Slot_f11_s2_mul_get (insn) == 0) + return OPCODE_IVP_MUL2N8XR16; + if (Field_fld_f11_s2_mul_22_8_Slot_f11_s2_mul_get (insn) == 5376 && + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get (insn) == 11) + return OPCODE_SSR; + return XTENSA_UNDEFINED; +} + +static int +Slot_f11_s0_ld_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f11_s0_ld_23_0_Slot_f11_s0_ld_get (insn) == 1486897) + return OPCODE_NOP; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 340) + return OPCODE_ADD; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 341) + return OPCODE_ADDX2; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 342) + return OPCODE_ADDX4; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 343) + return OPCODE_ADDX8; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 344) + return OPCODE_AND; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 345) + return OPCODE_MAX; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 346) + return OPCODE_MAXU; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 347) + return OPCODE_MIN; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 348) + return OPCODE_MINU; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 349) + return OPCODE_MOVEQZ; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 350) + return OPCODE_MOVGEZ; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 351) + return OPCODE_MOVLTZ; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 352) + return OPCODE_MOVNEZ; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 353) + return OPCODE_OR; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 354) + return OPCODE_SALT; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 355) + return OPCODE_SALTU; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 356) + return OPCODE_SRLI; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 357) + return OPCODE_SUB; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 358) + return OPCODE_SUBX2; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 359) + return OPCODE_SUBX4; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 360) + return OPCODE_SUBX8; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 361) + return OPCODE_XOR; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 362) + return OPCODE_SEXT; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 363 && + Field_fld_f11_s0_ld_7_4_Slot_f11_s0_ld_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 363 && + Field_fld_f11_s0_ld_7_4_Slot_f11_s0_ld_get (insn) == 0) + return OPCODE_SRA; + if (Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get (insn) == 364 && + Field_fld_f11_s0_ld_3_0_Slot_f11_s0_ld_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_f11_s0_ld_23_13_Slot_f11_s0_ld_get (insn) == 168) + return OPCODE_SRAI; + if (Field_fld_f11_s0_ld_23_13_Slot_f11_s0_ld_get (insn) == 169) + return OPCODE_SLLI; + if (Field_fld_f11_s0_ld_23_16_Slot_f11_s0_ld_get (insn) == 18) + return OPCODE_ADDI; + if (Field_fld_f11_s0_ld_23_16_Slot_f11_s0_ld_get (insn) == 19) + return OPCODE_ADDMI; + if (Field_fld_f11_s0_ld_23_16_Slot_f11_s0_ld_get (insn) == 20) + return OPCODE_MOVI; + if (Field_fld_f11_s0_ld_23_17_Slot_f11_s0_ld_get (insn) == 8) + return OPCODE_EXTUI; + if (Field_fld_f11_s0_ld_23_20_Slot_f11_s0_ld_get (insn) == 0) + return OPCODE_CONST16; + if (Field_fld_f11_s0_ld_23_4_Slot_f11_s0_ld_get (insn) == 92930) + return OPCODE_IVP_MALIGN; + if (Field_fld_f11_s0_ld_23_4_Slot_f11_s0_ld_get (insn) == 92931 && + Field_fld_f11_s0_ld_1_0_Slot_f11_s0_ld_get (insn) == 0) + return OPCODE_IVP_ZALIGN; + return XTENSA_UNDEFINED; +} + +static int +Slot_f4_s2_mul_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULPAI2NR8X16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULPI2NR8X16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULQ2N8XR8; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULQA2N8XR8; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUSPAI2NR8X16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUSPI2NR8X16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUSQ2N8XR8; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSQA2N8XR8; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 3) + return OPCODE_IVP_MULPNX16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 2) + return OPCODE_IVP_MULPANX16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 7) + return OPCODE_IVP_MULUSPNX16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 6) + return OPCODE_IVP_MULUSPANX16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 11) + return OPCODE_IVP_MULUUPNX16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 10) + return OPCODE_IVP_MULUUPANX16; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 0) + return OPCODE_IVP_MULP2NX8; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 1) + return OPCODE_IVP_MULPA2NX8; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 4) + return OPCODE_IVP_MULUSP2NX8; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 5) + return OPCODE_IVP_MULUSPA2NX8; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 8) + return OPCODE_IVP_MULUUP2NX8; + if (Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get (insn) == 8 && + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get (insn) == 9) + return OPCODE_IVP_MULUUPA2NX8; + if (Field_fld_f4_s2_mul_32_8_Slot_f4_s2_mul_get (insn) == 2097152 && + Field_fld_f4_s2_mul_7_0_Slot_f4_s2_mul_get (insn) == 12) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_inst_23_12_Slot_inst_get (insn) == 864 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_oq_tie2apb_outq0_push_read; + if (Field_fld_inst_23_12_Slot_inst_get (insn) == 865 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_oq_tie2apb_outq0_push_write; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 6 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_oq_tie2apb_outq0_nonblocking_push_read; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 22 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_oq_tie2apb_outq0_nonblocking_push_write; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 38 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 0 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_iq_tie2apb_inq0_nonblocking_peek; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 38 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 1 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_iq_tie2apb_inq0_nonblocking_pop; + if (Field_fld_inst_23_8_Slot_inst_get (insn) == 13856 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_iq_tie2apb_inq0_blocking_peek; + if (Field_fld_inst_23_8_Slot_inst_get (insn) == 13857 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_iq_tie2apb_inq0_is_ready; + if (Field_fld_inst_23_8_Slot_inst_get (insn) == 13858 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_iq_tie2apb_inq0_pop; + if (Field_fld_inst_23_8_Slot_inst_get (insn) == 13859 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_oq_tie2apb_outq0_is_ready; + if (Field_op0_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 0) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_r_Slot_inst_get (insn) == 0) + { + if (Field_m_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return OPCODE_ILL; + if (Field_m_Slot_inst_get (insn) == 2) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_RET; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_RETW; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_JX; + } + if (Field_m_Slot_inst_get (insn) == 3) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALLX0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALLX4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALLX8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALLX12; + } + } + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_MOVSP; + if (Field_r_Slot_inst_get (insn) == 2) + { + if (Field_s_Slot_inst_get (insn) == 0) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_ISYNC; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RSYNC; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_ESYNC; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DSYNC; + if (Field_t_Slot_inst_get (insn) == 8) + return OPCODE_EXCW; + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_MEMW; + if (Field_t_Slot_inst_get (insn) == 13) + return OPCODE_EXTW; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_NOP; + } + } + if (Field_r_Slot_inst_get (insn) == 3) + { + if (Field_t_Slot_inst_get (insn) == 0) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_RFE; + if (Field_s_Slot_inst_get (insn) == 2) + return OPCODE_RFDE; + if (Field_s_Slot_inst_get (insn) == 4) + return OPCODE_RFWO; + if (Field_s_Slot_inst_get (insn) == 5) + return OPCODE_RFWU; + } + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFI; + if (Field_t_Slot_inst_get (insn) == 2 && + Field_s_Slot_inst_get (insn) == 1) + return OPCODE_CLREX; + } + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BREAK; + if (Field_r_Slot_inst_get (insn) == 5) + { + if (Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SYSCALL; + if (Field_s_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SIMCALL; + } + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RSIL; + if (Field_r_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_WAITI; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_LDDR32_P; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_SDDR32_P; + } + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_ANY4; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_ALL4; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_ANY8; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_ALL8; + } + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_AND; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OR; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_XOR; + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSR; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSL; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8L; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8B; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_thi3_Slot_inst_get (insn) == 0) + return OPCODE_SSAI; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RER; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_WER; + if (Field_r_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_ROTW; + if (Field_r_Slot_inst_get (insn) == 10 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_GETEX; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_NSA; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_NSAU; + } + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_RPTLB0; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_PPTLB; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_WPTLB; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_RPTLB1; + } + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_NEG; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_ABS; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_ADD; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_ADDX2; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_ADDX4; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_ADDX8; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_SUB; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_SUBX2; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_SUBX4; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_SUBX8; + } + if (Field_op1_Slot_inst_get (insn) == 1) + { + if ((Field_op2_Slot_inst_get (insn) == 0 || + Field_op2_Slot_inst_get (insn) == 1)) + return OPCODE_SLLI; + if ((Field_op2_Slot_inst_get (insn) == 2 || + Field_op2_Slot_inst_get (insn) == 3)) + return OPCODE_SRAI; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_SRLI; + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_XSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_XSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_XSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_XSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_XSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_XSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_XSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_XSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_XSR_MPUENB; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_XSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_XSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_XSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 98) + return OPCODE_XSR_CACHEADRDIS; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_XSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_XSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 116) + return OPCODE_XSR_GSERR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_XSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_XSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_XSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_XSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_XSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_XSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_XSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_XSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_XSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_XSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_XSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_XSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_XSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_XSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_XSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_XSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_XSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_XSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_XSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_XSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_XSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_XSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_XSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_XSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_XSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_XSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_XSR_CCOMPARE1; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_SRC; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRL; + if (Field_op2_Slot_inst_get (insn) == 10 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SLL; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRA; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MUL16U; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MUL16S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_LICT; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_SICT; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_LICW; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_SICW; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_L32EX; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S32EX; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_RFDO; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFDD; + } + } + if (Field_op1_Slot_inst_get (insn) == 2) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_ANDB; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_ANDBC; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_ORB; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_ORBC; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_XORB; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_SALTU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_SALT; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MULL; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MULUH; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MULSH; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_QUOU; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_QUOS; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_REMU; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_REMS; + } + if (Field_op1_Slot_inst_get (insn) == 3) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_RSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_RSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_RSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_RSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_RSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_RSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_RSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_RSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_RSR_MPUENB; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_RSR_MPUCFG; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_RSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_RSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_RSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 98) + return OPCODE_RSR_CACHEADRDIS; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_RSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_RSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 116) + return OPCODE_RSR_GSERR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_RSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_RSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_RSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_RSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_RSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_RSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_RSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_RSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_RSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_RSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_RSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_RSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 208) + return OPCODE_RSR_CONFIGID1; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_RSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_RSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_RSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_RSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_RSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_RSR_INTERRUPT; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_RSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_RSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_RSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_RSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_RSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_RSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 235) + return OPCODE_RSR_PRID; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_RSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_RSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_RSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_RSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_RSR_CCOMPARE1; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_WSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_WSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_WSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_WSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_WSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_WSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_WSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_WSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 89) + return OPCODE_WSR_MMID; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_WSR_MPUENB; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_WSR_MPUCFG; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_WSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_WSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_WSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 98) + return OPCODE_WSR_CACHEADRDIS; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_WSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_WSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 116) + return OPCODE_WSR_GSERR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_WSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_WSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_WSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_WSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_WSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_WSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_WSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_WSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_WSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_WSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_WSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_WSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_WSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_WSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_WSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_WSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_WSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_WSR_INTSET; + if (Field_sr_Slot_inst_get (insn) == 227) + return OPCODE_WSR_INTCLEAR; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_WSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_WSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_WSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_WSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_WSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WSR_CCOMPARE1; + } + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_SEXT; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_CLAMPS; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MIN; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MAX; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MINU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_MAXU; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MOVLTZ; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MOVF; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MOVT; + if (Field_op2_Slot_inst_get (insn) == 14) + { + if (Field_st_Slot_inst_get (insn) == 0) + return OPCODE_RUR_APB_PIPE; + if (Field_st_Slot_inst_get (insn) == 231) + return OPCODE_RUR_THREADPTR; + } + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_WUR_APB_PIPE; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WUR_THREADPTR; + } + } + if ((Field_op1_Slot_inst_get (insn) == 4 || + Field_op1_Slot_inst_get (insn) == 5)) + return OPCODE_EXTUI; + if (Field_op1_Slot_inst_get (insn) == 9) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_L32E; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_S32E; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_S32NB; + } + } + if (Field_op0_Slot_inst_get (insn) == 1) + return OPCODE_L32R; + if (Field_op0_Slot_inst_get (insn) == 2) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_L8UI; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_L16UI; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_L32I; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_S8I; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S16I; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_S32I; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_IPF; + if (Field_t_Slot_inst_get (insn) == 13) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_IPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_IHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_IIU; + } + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_IHI; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_III; + } + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_L16SI; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_MOVI; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_L32AI; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_ADDI; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_S32RI; + } + if (Field_op0_Slot_inst_get (insn) == 4) + return OPCODE_CONST16; + if (Field_op0_Slot_inst_get (insn) == 5) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALL0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALL4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALL8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALL12; + } + if (Field_op0_Slot_inst_get (insn) == 6) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_J; + if (Field_n_Slot_inst_get (insn) == 1) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQZ; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEZ; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTZ; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEZ; + } + if (Field_n_Slot_inst_get (insn) == 2) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQI; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEI; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEI; + } + if (Field_n_Slot_inst_get (insn) == 3) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_ENTRY; + if (Field_m_Slot_inst_get (insn) == 1) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BF; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BT; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LOOP; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_LOOPNEZ; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LOOPGTZ; + } + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTUI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEUI; + } + } + if (Field_op0_Slot_inst_get (insn) == 7) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BNONE; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BEQ; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_BLT; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_BLTU; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BALL; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_BBC; + if ((Field_r_Slot_inst_get (insn) == 6 || + Field_r_Slot_inst_get (insn) == 7)) + return OPCODE_BBCI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_BANY; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_BNE; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_BGE; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_BGEU; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_BNALL; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_BBS; + if ((Field_r_Slot_inst_get (insn) == 14 || + Field_r_Slot_inst_get (insn) == 15)) + return OPCODE_BBSI; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16b_get (insn) == 12) + { + if (Field_i_Slot_inst16b_get (insn) == 0) + return OPCODE_MOVI_N; + if (Field_i_Slot_inst16b_get (insn) == 1) + { + if (Field_z_Slot_inst16b_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_z_Slot_inst16b_get (insn) == 1) + return OPCODE_BNEZ_N; + } + } + if (Field_op0_Slot_inst16b_get (insn) == 13) + { + if (Field_r_Slot_inst16b_get (insn) == 0) + return OPCODE_MOV_N; + if (Field_r_Slot_inst16b_get (insn) == 15) + { + if (Field_t_Slot_inst16b_get (insn) == 0) + return OPCODE_RET_N; + if (Field_t_Slot_inst16b_get (insn) == 1) + return OPCODE_RETW_N; + if (Field_t_Slot_inst16b_get (insn) == 2) + return OPCODE_BREAK_N; + if (Field_t_Slot_inst16b_get (insn) == 3 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_NOP_N; + if (Field_t_Slot_inst16b_get (insn) == 6 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_ILL_N; + } + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16a_get (insn) == 8) + return OPCODE_L32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 9) + return OPCODE_S32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 10) + return OPCODE_ADD_N; + if (Field_op0_Slot_inst16a_get (insn) == 11) + return OPCODE_ADDI_N; + return XTENSA_UNDEFINED; +} + +static int +Slot_f5_s3_base_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f5_s3_base_25_1_Slot_f5_s3_base_get (insn) == 65664 && + Field_fld_f5_s3_base_0_0_Slot_f5_s3_base_get (insn) == 0) + return OPCODE_NOP; + if (Field_fld_f5_s3_base_25_16_Slot_f5_s3_base_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_f5_s3_base_25_16_Slot_f5_s3_base_get (insn) == 1) + return OPCODE_MOVI; + if (Field_fld_f5_s3_base_25_8_Slot_f5_s3_base_get (insn) == 512) + return OPCODE_MOV_N; + return XTENSA_UNDEFINED; +} + +static int +Slot_f5_s0_base_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66052) + return OPCODE_ADD; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66053) + return OPCODE_ADDX2; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66054) + return OPCODE_ADDX4; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66055) + return OPCODE_ADDX8; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66056) + return OPCODE_AND; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66057) + return OPCODE_MAX; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66058) + return OPCODE_MAXU; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66059) + return OPCODE_MIN; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66060) + return OPCODE_MINU; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66061) + return OPCODE_MOVEQZ; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66062) + return OPCODE_MOVGEZ; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66063) + return OPCODE_MOVLTZ; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66064) + return OPCODE_MOVNEZ; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66065) + return OPCODE_MUL16S; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66066) + return OPCODE_MUL16U; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66067) + return OPCODE_MULL; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66068) + return OPCODE_MULSH; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66069) + return OPCODE_MULUH; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66070) + return OPCODE_OR; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66071) + return OPCODE_SALT; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66072) + return OPCODE_SALTU; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66073) + return OPCODE_SRC; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66074) + return OPCODE_SUB; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66075) + return OPCODE_SUBX2; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66076) + return OPCODE_SUBX4; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66077) + return OPCODE_SUBX8; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66078) + return OPCODE_XOR; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66079) + return OPCODE_CLAMPS; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66080) + return OPCODE_SEXT; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66081) + return OPCODE_SRLI; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66082 && + Field_fld_f5_s0_base_7_4_Slot_f5_s0_base_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66082 && + Field_fld_f5_s0_base_7_4_Slot_f5_s0_base_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66082 && + Field_fld_f5_s0_base_7_4_Slot_f5_s0_base_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66082 && + Field_fld_f5_s0_base_7_4_Slot_f5_s0_base_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66083 && + Field_fld_f5_s0_base_11_0_Slot_f5_s0_base_get (insn) == 517) + return OPCODE_NOP; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66083 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 2 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 4) + return OPCODE_SSR; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66083 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 2 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 3) + return OPCODE_SSL; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66083 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 2 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 2) + return OPCODE_SSA8L; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66083 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 2 && + Field_fld_f5_s0_base_3_1_Slot_f5_s0_base_get (insn) == 0) + return OPCODE_SSAI; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66083 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 0) + return OPCODE_NSA; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66083 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 1) + return OPCODE_NSAU; + if (Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get (insn) == 66096 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_f5_s0_base_36_13_Slot_f5_s0_base_get (insn) == 33024) + return OPCODE_SLLI; + if (Field_fld_f5_s0_base_36_13_Slot_f5_s0_base_get (insn) == 33025) + return OPCODE_SRAI; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4118) + return OPCODE_ADDI; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4119) + return OPCODE_ADDMI; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4120) + return OPCODE_L16SI; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4121) + return OPCODE_L16UI; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4122) + return OPCODE_L32I; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4123) + return OPCODE_L8UI; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4124) + return OPCODE_S16I; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4125) + return OPCODE_S32I; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4126) + return OPCODE_S8I; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4127) + return OPCODE_MOVI; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4131 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4131 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get (insn) == 4131 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_f5_s0_base_36_17_Slot_f5_s0_base_get (insn) == 2058) + return OPCODE_EXTUI; + if (Field_fld_f5_s0_base_36_18_Slot_f5_s0_base_get (insn) == 1028) + return OPCODE_J; + if (Field_fld_f5_s0_base_36_20_Slot_f5_s0_base_get (insn) == 256) + return OPCODE_CONST16; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_9_Slot_f5_s0_base_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_9_Slot_f5_s0_base_get (insn) == 1) + return OPCODE_BBSI_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 8) + return OPCODE_BEQ_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 14) + return OPCODE_BNE_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 10) + return OPCODE_BGE_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 12) + return OPCODE_BLT_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 9) + return OPCODE_BGEU_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 11) + return OPCODE_BLTU_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 5) + return OPCODE_BANY_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 4) + return OPCODE_BALL_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 13) + return OPCODE_BNALL_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 6) + return OPCODE_BBC_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 7) + return OPCODE_BBS_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 0 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 6) + return OPCODE_BEQZ_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 3 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 6) + return OPCODE_BNEZ_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 6) + return OPCODE_BGEZ_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get (insn) == 2 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 6) + return OPCODE_BLTZ_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 5) + return OPCODE_BNEI_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 1) + return OPCODE_BGEI_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 3) + return OPCODE_BLTI_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 2) + return OPCODE_BGEUI_W15; + if (Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get (insn) == 1 && + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get (insn) == 4) + return OPCODE_BLTUI_W15; + return XTENSA_UNDEFINED; +} + +static int +Slot_f5_s1_base_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 148) + return OPCODE_ADD; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 149) + return OPCODE_ADDX2; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 150) + return OPCODE_ADDX4; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 151) + return OPCODE_ADDX8; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 152) + return OPCODE_AND; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 153) + return OPCODE_MAX; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 154) + return OPCODE_MAXU; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 155) + return OPCODE_MIN; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 156) + return OPCODE_MINU; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 157) + return OPCODE_MOVEQZ; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 158) + return OPCODE_MOVGEZ; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 159) + return OPCODE_MOVLTZ; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 160) + return OPCODE_MOVNEZ; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 161) + return OPCODE_OR; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 162) + return OPCODE_SALT; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 163) + return OPCODE_SALTU; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 164) + return OPCODE_SRLI; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 165) + return OPCODE_SUB; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 166) + return OPCODE_SUBX2; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 167) + return OPCODE_SUBX4; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 168) + return OPCODE_SUBX8; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 169) + return OPCODE_XOR; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 170) + return OPCODE_CLAMPS; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 171) + return OPCODE_SEXT; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 172 && + Field_fld_f5_s1_base_7_4_Slot_f5_s1_base_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 172 && + Field_fld_f5_s1_base_7_4_Slot_f5_s1_base_get (insn) == 2) + return OPCODE_SRL; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 172 && + Field_fld_f5_s1_base_7_4_Slot_f5_s1_base_get (insn) == 1) + return OPCODE_SRA; + if (Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get (insn) == 173 && + Field_fld_f5_s1_base_3_0_Slot_f5_s1_base_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_f5_s1_base_27_13_Slot_f5_s1_base_get (insn) == 72) + return OPCODE_SRAI; + if (Field_fld_f5_s1_base_27_13_Slot_f5_s1_base_get (insn) == 73) + return OPCODE_SLLI; + if (Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_get (insn) == 4) + return OPCODE_L16SI; + if (Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_get (insn) == 5) + return OPCODE_L16UI; + if (Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_get (insn) == 6) + return OPCODE_L32I; + if (Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_get (insn) == 7) + return OPCODE_L8UI; + if (Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_get (insn) == 8) + return OPCODE_MOVI; + if (Field_fld_f5_s1_base_27_17_Slot_f5_s1_base_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_f5_s1_base_27_3_Slot_f5_s1_base_get (insn) == 88070 && + Field_fld_f5_s1_base_2_0_Slot_f5_s1_base_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_f5_s2_base_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 52) + return OPCODE_ADD; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 53) + return OPCODE_ADDX2; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 54) + return OPCODE_ADDX4; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 55) + return OPCODE_ADDX8; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 56) + return OPCODE_AND; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 57) + return OPCODE_MAX; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 58) + return OPCODE_MAXU; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 59) + return OPCODE_MIN; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 60) + return OPCODE_MINU; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 61) + return OPCODE_MOVEQZ; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 62) + return OPCODE_MOVGEZ; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 63) + return OPCODE_MOVLTZ; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 64) + return OPCODE_MOVNEZ; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 65) + return OPCODE_OR; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 66) + return OPCODE_SALT; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 67) + return OPCODE_SALTU; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 68) + return OPCODE_SRC; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 69) + return OPCODE_SRLI; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 70) + return OPCODE_SUB; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 71) + return OPCODE_SUBX2; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 72) + return OPCODE_SUBX4; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 73) + return OPCODE_SUBX8; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 74) + return OPCODE_XOR; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 75 && + Field_fld_f5_s2_base_7_4_Slot_f5_s2_base_get (insn) == 0) + return OPCODE_NEG; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 75 && + Field_fld_f5_s2_base_7_4_Slot_f5_s2_base_get (insn) == 2) + return OPCODE_SRL; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 75 && + Field_fld_f5_s2_base_7_4_Slot_f5_s2_base_get (insn) == 1) + return OPCODE_SRA; + if (Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get (insn) == 77 && + Field_fld_f5_s2_base_3_0_Slot_f5_s2_base_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_f5_s2_base_26_13_Slot_f5_s2_base_get (insn) == 24) + return OPCODE_SRAI; + if (Field_fld_f5_s2_base_26_13_Slot_f5_s2_base_get (insn) == 25) + return OPCODE_SLLI; + if (Field_fld_f5_s2_base_26_16_Slot_f5_s2_base_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_f5_s2_base_26_16_Slot_f5_s2_base_get (insn) == 1) + return OPCODE_ADDMI; + if (Field_fld_f5_s2_base_26_16_Slot_f5_s2_base_get (insn) == 2) + return OPCODE_MOVI; + if (Field_fld_f5_s2_base_26_2_Slot_f5_s2_base_get (insn) == 78848 && + Field_fld_f5_s2_base_1_0_Slot_f5_s2_base_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_f5_s2_base_26_8_Slot_f5_s2_base_get (insn) == 1216) + return OPCODE_NSA; + if (Field_fld_f5_s2_base_26_8_Slot_f5_s2_base_get (insn) == 1217) + return OPCODE_NSAU; + return XTENSA_UNDEFINED; +} + +static int +Slot_n1_s1_none_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_n1_s1_none_3_0_Slot_n1_s1_none_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_n0_s1_none_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_n0_s1_none_2_0_Slot_n0_s1_none_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_n0_s2_none_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_n0_s2_none_2_0_Slot_n0_s2_none_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_f0_Format_f0_s0_ldst_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[0] & 0x3e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x2) >> 1) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc000) | (((insn[1] & 0x600) >> 9) << 14); + slotbuf[0] = (slotbuf[0] & ~0x1ff0000) | (((insn[2] & 0xff800000) >> 23) << 16); + slotbuf[0] = (slotbuf[0] & ~0x1e000000) | ((insn[3] & 0xf) << 25); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x1000) >> 12) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x2000) >> 13) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x4000) >> 14) << 31); + slotbuf[1] = ((insn[3] & 0x8000) >> 15); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[3] & 0x10000) >> 16) << 1); +} + +static void +Slot_f0_Format_f0_s0_ldst_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0x3e0000) | (((slotbuf[0] & 0x1f00) >> 8) << 17); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x2000) >> 13) << 1); + insn[1] = (insn[1] & ~0x600) | (((slotbuf[0] & 0xc000) >> 14) << 9); + insn[2] = (insn[2] & ~0xff800000) | (((slotbuf[0] & 0x1ff0000) >> 16) << 23); + insn[3] = (insn[3] & ~0xf) | ((slotbuf[0] & 0x1e000000) >> 25); + insn[3] = (insn[3] & ~0x1000) | (((slotbuf[0] & 0x20000000) >> 29) << 12); + insn[3] = (insn[3] & ~0x2000) | (((slotbuf[0] & 0x40000000) >> 30) << 13); + insn[3] = (insn[3] & ~0x4000) | (((slotbuf[0] & 0x80000000) >> 31) << 14); + insn[3] = (insn[3] & ~0x8000) | ((slotbuf[1] & 0x1) << 15); + insn[3] = (insn[3] & ~0x10000) | (((slotbuf[1] & 0x2) >> 1) << 16); +} + +static void +Slot_f0_Format_f0_s1_ld_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xe0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x8) | (((insn[0] & 0x10000) >> 16) << 3); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0x3c00000) >> 22) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf0000000) >> 28) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x8000000) >> 27) << 12); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x4) >> 2) << 13); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[1] & 0x20000) >> 17) << 14); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[1] & 0x4000000) >> 26) << 15); + slotbuf[0] = (slotbuf[0] & ~0x30000) | (((insn[0] & 0xc000000) >> 26) << 16); + slotbuf[0] = (slotbuf[0] & ~0x1c0000) | (((insn[3] & 0x70) >> 4) << 18); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x80000) >> 19) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x100000) >> 20) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x200000) >> 21) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x400000) >> 22) << 24); +} + +static void +Slot_f0_Format_f0_s1_ld_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xe0) | ((slotbuf[0] & 0x7) << 5); + insn[0] = (insn[0] & ~0x10000) | (((slotbuf[0] & 0x8) >> 3) << 16); + insn[0] = (insn[0] & ~0x3c00000) | (((slotbuf[0] & 0xf0) >> 4) << 22); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf00) >> 8) << 28); + insn[1] = (insn[1] & ~0x8000000) | (((slotbuf[0] & 0x1000) >> 12) << 27); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[0] & 0x2000) >> 13) << 2); + insn[1] = (insn[1] & ~0x20000) | (((slotbuf[0] & 0x4000) >> 14) << 17); + insn[1] = (insn[1] & ~0x4000000) | (((slotbuf[0] & 0x8000) >> 15) << 26); + insn[0] = (insn[0] & ~0xc000000) | (((slotbuf[0] & 0x30000) >> 16) << 26); + insn[3] = (insn[3] & ~0x70) | (((slotbuf[0] & 0x1c0000) >> 18) << 4); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x200000) >> 21) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x400000) >> 22) << 20); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x800000) >> 23) << 21); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x1000000) >> 24) << 22); +} + +static void +Slot_f0_Format_f0_s2_mul_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x10) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x2) | ((insn[1] & 0x1) << 1); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[1] & 0x6000) >> 13) << 2); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[1] & 0x40000) >> 18) << 4); + slotbuf[0] = (slotbuf[0] & ~0xe0) | (((insn[1] & 0x3800000) >> 23) << 5); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[1] & 0x780000) >> 19) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x80000000) >> 31) << 12); + slotbuf[0] = (slotbuf[0] & ~0x2000) | ((insn[2] & 0x1) << 13); + slotbuf[0] = (slotbuf[0] & ~0x7c000) | (((insn[2] & 0xf800) >> 11) << 14); + slotbuf[0] = (slotbuf[0] & ~0x180000) | (((insn[1] & 0x18000) >> 15) << 19); + slotbuf[0] = (slotbuf[0] & ~0x600000) | (((insn[3] & 0x180) >> 7) << 21); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x800000) >> 23) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x1000000) >> 24) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x4000000) >> 26) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x8000000) >> 27) << 26); +} + +static void +Slot_f0_Format_f0_s2_mul_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x10) | ((slotbuf[0] & 0x1) << 4); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x2) >> 1); + insn[1] = (insn[1] & ~0x6000) | (((slotbuf[0] & 0xc) >> 2) << 13); + insn[1] = (insn[1] & ~0x40000) | (((slotbuf[0] & 0x10) >> 4) << 18); + insn[1] = (insn[1] & ~0x3800000) | (((slotbuf[0] & 0xe0) >> 5) << 23); + insn[1] = (insn[1] & ~0x780000) | (((slotbuf[0] & 0xf00) >> 8) << 19); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x1000) >> 12) << 31); + insn[2] = (insn[2] & ~0x1) | ((slotbuf[0] & 0x2000) >> 13); + insn[2] = (insn[2] & ~0xf800) | (((slotbuf[0] & 0x7c000) >> 14) << 11); + insn[1] = (insn[1] & ~0x18000) | (((slotbuf[0] & 0x180000) >> 19) << 15); + insn[3] = (insn[3] & ~0x180) | (((slotbuf[0] & 0x600000) >> 21) << 7); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x800000) >> 23) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x1000000) >> 24) << 24); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x2000000) >> 25) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x4000000) >> 26) << 27); +} + +static void +Slot_f0_Format_f0_s3_alu_35_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0x400000) >> 22); + slotbuf[0] = (slotbuf[0] & ~0x7e) | (((insn[1] & 0x1f8) >> 3) << 1); + slotbuf[0] = (slotbuf[0] & ~0x180) | (((insn[1] & 0x1800) >> 11) << 7); + slotbuf[0] = (slotbuf[0] & ~0x200) | (((insn[1] & 0x10000000) >> 28) << 9); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[2] & 0x7c0) >> 6) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[2] & 0x3e) >> 1) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[2] & 0x1f0000) >> 16) << 20); + slotbuf[0] = (slotbuf[0] & ~0x6000000) | (((insn[1] & 0x60000000) >> 29) << 25); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[2] & 0x200000) >> 21) << 27); + slotbuf[0] = (slotbuf[0] & ~0x30000000) | (((insn[3] & 0x600) >> 9) << 28); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x10000000) >> 28) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x20000000) >> 29) << 31); + slotbuf[1] = ((insn[3] & 0x40000000) >> 30); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[3] & 0x80000000) >> 31) << 1); +} + +static void +Slot_f0_Format_f0_s3_alu_35_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0x400000) | ((slotbuf[0] & 0x1) << 22); + insn[1] = (insn[1] & ~0x1f8) | (((slotbuf[0] & 0x7e) >> 1) << 3); + insn[1] = (insn[1] & ~0x1800) | (((slotbuf[0] & 0x180) >> 7) << 11); + insn[1] = (insn[1] & ~0x10000000) | (((slotbuf[0] & 0x200) >> 9) << 28); + insn[2] = (insn[2] & ~0x7c0) | (((slotbuf[0] & 0x7c00) >> 10) << 6); + insn[2] = (insn[2] & ~0x3e) | (((slotbuf[0] & 0xf8000) >> 15) << 1); + insn[2] = (insn[2] & ~0x1f0000) | (((slotbuf[0] & 0x1f00000) >> 20) << 16); + insn[1] = (insn[1] & ~0x60000000) | (((slotbuf[0] & 0x6000000) >> 25) << 29); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[0] & 0x8000000) >> 27) << 21); + insn[3] = (insn[3] & ~0x600) | (((slotbuf[0] & 0x30000000) >> 28) << 9); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x40000000) >> 30) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x80000000) >> 31) << 29); + insn[3] = (insn[3] & ~0x40000000) | ((slotbuf[1] & 0x1) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x2) >> 1) << 31); +} + +static void +Slot_f1_Format_f1_s0_ldstalu_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[0] & 0x3e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[1] & 0x300000) >> 20) << 13); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[1] & 0x2) >> 1) << 15); + slotbuf[0] = (slotbuf[0] & ~0x30000) | (((insn[1] & 0x600) >> 9) << 16); + slotbuf[0] = (slotbuf[0] & ~0x1c0000) | (((insn[2] & 0xe) >> 1) << 18); + slotbuf[0] = (slotbuf[0] & ~0x1e00000) | (((insn[2] & 0x7800) >> 11) << 21); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x80) >> 7) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x100) >> 8) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x200) >> 9) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x400) >> 10) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x1000) >> 12) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x2000) >> 13) << 30); +} + +static void +Slot_f1_Format_f1_s0_ldstalu_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0x3e0000) | (((slotbuf[0] & 0x1f00) >> 8) << 17); + insn[1] = (insn[1] & ~0x300000) | (((slotbuf[0] & 0x6000) >> 13) << 20); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x8000) >> 15) << 1); + insn[1] = (insn[1] & ~0x600) | (((slotbuf[0] & 0x30000) >> 16) << 9); + insn[2] = (insn[2] & ~0xe) | (((slotbuf[0] & 0x1c0000) >> 18) << 1); + insn[2] = (insn[2] & ~0x7800) | (((slotbuf[0] & 0x1e00000) >> 21) << 11); + insn[3] = (insn[3] & ~0x80) | (((slotbuf[0] & 0x2000000) >> 25) << 7); + insn[3] = (insn[3] & ~0x100) | (((slotbuf[0] & 0x4000000) >> 26) << 8); + insn[3] = (insn[3] & ~0x200) | (((slotbuf[0] & 0x8000000) >> 27) << 9); + insn[3] = (insn[3] & ~0x400) | (((slotbuf[0] & 0x10000000) >> 28) << 10); + insn[3] = (insn[3] & ~0x1000) | (((slotbuf[0] & 0x20000000) >> 29) << 12); + insn[3] = (insn[3] & ~0x2000) | (((slotbuf[0] & 0x40000000) >> 30) << 13); +} + +static void +Slot_f1_Format_f1_s1_ld_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xe0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x8) | (((insn[0] & 0x10000) >> 16) << 3); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0x3c00000) >> 22) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf0000000) >> 28) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | ((insn[2] & 0x1) << 12); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x80000) >> 19) << 13); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[1] & 0x20000) >> 17) << 14); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[1] & 0x1c000000) >> 26) << 15); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x8000) >> 15) << 18); + slotbuf[0] = (slotbuf[0] & ~0x180000) | (((insn[2] & 0xc00000) >> 22) << 19); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[2] & 0x8000000) >> 27) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x4000) >> 14) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x8000) >> 15) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x10000) >> 16) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x80000) >> 19) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x100000) >> 20) << 26); +} + +static void +Slot_f1_Format_f1_s1_ld_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xe0) | ((slotbuf[0] & 0x7) << 5); + insn[0] = (insn[0] & ~0x10000) | (((slotbuf[0] & 0x8) >> 3) << 16); + insn[0] = (insn[0] & ~0x3c00000) | (((slotbuf[0] & 0xf0) >> 4) << 22); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf00) >> 8) << 28); + insn[2] = (insn[2] & ~0x1) | ((slotbuf[0] & 0x1000) >> 12); + insn[1] = (insn[1] & ~0x80000) | (((slotbuf[0] & 0x2000) >> 13) << 19); + insn[1] = (insn[1] & ~0x20000) | (((slotbuf[0] & 0x4000) >> 14) << 17); + insn[1] = (insn[1] & ~0x1c000000) | (((slotbuf[0] & 0x38000) >> 15) << 26); + insn[2] = (insn[2] & ~0x8000) | (((slotbuf[0] & 0x40000) >> 18) << 15); + insn[2] = (insn[2] & ~0xc00000) | (((slotbuf[0] & 0x180000) >> 19) << 22); + insn[2] = (insn[2] & ~0x8000000) | (((slotbuf[0] & 0x200000) >> 21) << 27); + insn[3] = (insn[3] & ~0x4000) | (((slotbuf[0] & 0x400000) >> 22) << 14); + insn[3] = (insn[3] & ~0x8000) | (((slotbuf[0] & 0x800000) >> 23) << 15); + insn[3] = (insn[3] & ~0x10000) | (((slotbuf[0] & 0x1000000) >> 24) << 16); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x2000000) >> 25) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x4000000) >> 26) << 20); +} + +static void +Slot_f1_Format_f1_s2_mul_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x10) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x2) | ((insn[1] & 0x1) << 1); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[1] & 0x6000) >> 13) << 2); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[1] & 0x40000) >> 18) << 4); + slotbuf[0] = (slotbuf[0] & ~0xe0) | (((insn[1] & 0x3800000) >> 23) << 5); + slotbuf[0] = (slotbuf[0] & ~0x100) | (((insn[1] & 0x80000000) >> 31) << 8); + slotbuf[0] = (slotbuf[0] & ~0x200) | (((insn[1] & 0x400000) >> 22) << 9); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[2] & 0x1f0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x7000000) >> 24) << 15); + slotbuf[0] = (slotbuf[0] & ~0x3c0000) | (((insn[2] & 0xf0000000) >> 28) << 18); + slotbuf[0] = (slotbuf[0] & ~0xc00000) | ((insn[3] & 0x3) << 22); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x200000) >> 21) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x400000) >> 22) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x800000) >> 23) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x1000000) >> 24) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x4000000) >> 26) << 28); +} + +static void +Slot_f1_Format_f1_s2_mul_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x10) | ((slotbuf[0] & 0x1) << 4); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x2) >> 1); + insn[1] = (insn[1] & ~0x6000) | (((slotbuf[0] & 0xc) >> 2) << 13); + insn[1] = (insn[1] & ~0x40000) | (((slotbuf[0] & 0x10) >> 4) << 18); + insn[1] = (insn[1] & ~0x3800000) | (((slotbuf[0] & 0xe0) >> 5) << 23); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x100) >> 8) << 31); + insn[1] = (insn[1] & ~0x400000) | (((slotbuf[0] & 0x200) >> 9) << 22); + insn[2] = (insn[2] & ~0x1f0000) | (((slotbuf[0] & 0x7c00) >> 10) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0x38000) >> 15) << 24); + insn[2] = (insn[2] & ~0xf0000000) | (((slotbuf[0] & 0x3c0000) >> 18) << 28); + insn[3] = (insn[3] & ~0x3) | ((slotbuf[0] & 0xc00000) >> 22); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x1000000) >> 24) << 21); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x2000000) >> 25) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x4000000) >> 26) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x8000000) >> 27) << 24); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x10000000) >> 28) << 26); +} + +static void +Slot_f1_Format_f1_s3_alu_26_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x3c) >> 2); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[0] & 0x8000000) >> 27) << 4); + slotbuf[0] = (slotbuf[0] & ~0x20) | (((insn[0] & 0x4000000) >> 26) << 5); + slotbuf[0] = (slotbuf[0] & ~0xc0) | (((insn[1] & 0x18000) >> 15) << 6); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[2] & 0x600) >> 9) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1c00) | (((insn[1] & 0x1c0) >> 6) << 10); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[1] & 0x1800) >> 11) << 13); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x1c0) >> 6) << 15); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[2] & 0x30) >> 4) << 18); + slotbuf[0] = (slotbuf[0] & ~0x300000) | (((insn[1] & 0x60000000) >> 29) << 20); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[2] & 0x200000) >> 21) << 22); + slotbuf[0] = (slotbuf[0] & ~0x3800000) | (((insn[3] & 0x1c) >> 2) << 23); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x8000000) >> 27) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x10000000) >> 28) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x20000000) >> 29) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x40000000) >> 30) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x80000000) >> 31) << 30); +} + +static void +Slot_f1_Format_f1_s3_alu_26_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x3c) | ((slotbuf[0] & 0xf) << 2); + insn[0] = (insn[0] & ~0x8000000) | (((slotbuf[0] & 0x10) >> 4) << 27); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x20) >> 5) << 26); + insn[1] = (insn[1] & ~0x18000) | (((slotbuf[0] & 0xc0) >> 6) << 15); + insn[2] = (insn[2] & ~0x600) | (((slotbuf[0] & 0x300) >> 8) << 9); + insn[1] = (insn[1] & ~0x1c0) | (((slotbuf[0] & 0x1c00) >> 10) << 6); + insn[1] = (insn[1] & ~0x1800) | (((slotbuf[0] & 0x6000) >> 13) << 11); + insn[2] = (insn[2] & ~0x1c0) | (((slotbuf[0] & 0x38000) >> 15) << 6); + insn[2] = (insn[2] & ~0x30) | (((slotbuf[0] & 0xc0000) >> 18) << 4); + insn[1] = (insn[1] & ~0x60000000) | (((slotbuf[0] & 0x300000) >> 20) << 29); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[0] & 0x400000) >> 22) << 21); + insn[3] = (insn[3] & ~0x1c) | (((slotbuf[0] & 0x3800000) >> 23) << 2); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x4000000) >> 26) << 27); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x8000000) >> 27) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x10000000) >> 28) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x20000000) >> 29) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x40000000) >> 30) << 31); +} + +static void +Slot_f2_Format_f2_s0_ldst_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0x1e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[2] & 0x400) >> 10) << 12); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x2) >> 1) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc000) | (((insn[1] & 0x600) >> 9) << 14); + slotbuf[0] = (slotbuf[0] & ~0x70000) | (((insn[2] & 0xe) >> 1) << 16); + slotbuf[0] = (slotbuf[0] & ~0x380000) | (((insn[2] & 0x70000) >> 16) << 19); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[2] & 0x800000) >> 23) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x80) >> 7) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x100) >> 8) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x200) >> 9) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x400) >> 10) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x1000) >> 12) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x2000) >> 13) << 28); +} + +static void +Slot_f2_Format_f2_s0_ldst_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0x1e0000) | (((slotbuf[0] & 0xf00) >> 8) << 17); + insn[2] = (insn[2] & ~0x400) | (((slotbuf[0] & 0x1000) >> 12) << 10); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x2000) >> 13) << 1); + insn[1] = (insn[1] & ~0x600) | (((slotbuf[0] & 0xc000) >> 14) << 9); + insn[2] = (insn[2] & ~0xe) | (((slotbuf[0] & 0x70000) >> 16) << 1); + insn[2] = (insn[2] & ~0x70000) | (((slotbuf[0] & 0x380000) >> 19) << 16); + insn[2] = (insn[2] & ~0x800000) | (((slotbuf[0] & 0x400000) >> 22) << 23); + insn[3] = (insn[3] & ~0x80) | (((slotbuf[0] & 0x800000) >> 23) << 7); + insn[3] = (insn[3] & ~0x100) | (((slotbuf[0] & 0x1000000) >> 24) << 8); + insn[3] = (insn[3] & ~0x200) | (((slotbuf[0] & 0x2000000) >> 25) << 9); + insn[3] = (insn[3] & ~0x400) | (((slotbuf[0] & 0x4000000) >> 26) << 10); + insn[3] = (insn[3] & ~0x1000) | (((slotbuf[0] & 0x8000000) >> 27) << 12); + insn[3] = (insn[3] & ~0x2000) | (((slotbuf[0] & 0x10000000) >> 28) << 13); +} + +static void +Slot_f2_Format_f2_s1_ld_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xe0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x8) | (((insn[0] & 0x10000) >> 16) << 3); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0x3c00000) >> 22) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf0000000) >> 28) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | ((insn[2] & 0x1) << 12); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x4) >> 2) << 13); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[1] & 0x20000) >> 17) << 14); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[1] & 0x1c000000) >> 26) << 15); + slotbuf[0] = (slotbuf[0] & ~0x3c0000) | (((insn[2] & 0x1e000000) >> 25) << 18); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x4000) >> 14) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x8000) >> 15) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x10000) >> 16) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x80000) >> 19) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x100000) >> 20) << 26); +} + +static void +Slot_f2_Format_f2_s1_ld_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xe0) | ((slotbuf[0] & 0x7) << 5); + insn[0] = (insn[0] & ~0x10000) | (((slotbuf[0] & 0x8) >> 3) << 16); + insn[0] = (insn[0] & ~0x3c00000) | (((slotbuf[0] & 0xf0) >> 4) << 22); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf00) >> 8) << 28); + insn[2] = (insn[2] & ~0x1) | ((slotbuf[0] & 0x1000) >> 12); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[0] & 0x2000) >> 13) << 2); + insn[1] = (insn[1] & ~0x20000) | (((slotbuf[0] & 0x4000) >> 14) << 17); + insn[1] = (insn[1] & ~0x1c000000) | (((slotbuf[0] & 0x38000) >> 15) << 26); + insn[2] = (insn[2] & ~0x1e000000) | (((slotbuf[0] & 0x3c0000) >> 18) << 25); + insn[3] = (insn[3] & ~0x4000) | (((slotbuf[0] & 0x400000) >> 22) << 14); + insn[3] = (insn[3] & ~0x8000) | (((slotbuf[0] & 0x800000) >> 23) << 15); + insn[3] = (insn[3] & ~0x10000) | (((slotbuf[0] & 0x1000000) >> 24) << 16); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x2000000) >> 25) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x4000000) >> 26) << 20); +} + +static void +Slot_f2_Format_f2_s2_mul_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x10) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x2) | ((insn[1] & 0x1) << 1); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[1] & 0x6000) >> 13) << 2); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[1] & 0x40000) >> 18) << 4); + slotbuf[0] = (slotbuf[0] & ~0xe0) | (((insn[1] & 0x3800000) >> 23) << 5); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[2] & 0x180000) >> 19) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[2] & 0xf800) >> 11) << 10); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[0] & 0x8000000) >> 27) << 15); + slotbuf[0] = (slotbuf[0] & ~0xf0000) | (((insn[1] & 0x780000) >> 19) << 16); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[1] & 0x80000000) >> 31) << 20); + slotbuf[0] = (slotbuf[0] & ~0xe00000) | (((insn[2] & 0xe0000000) >> 29) << 21); + slotbuf[0] = (slotbuf[0] & ~0x3000000) | ((insn[3] & 0x3) << 24); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x200000) >> 21) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x400000) >> 22) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x800000) >> 23) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x1000000) >> 24) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x4000000) >> 26) << 30); +} + +static void +Slot_f2_Format_f2_s2_mul_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x10) | ((slotbuf[0] & 0x1) << 4); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x2) >> 1); + insn[1] = (insn[1] & ~0x6000) | (((slotbuf[0] & 0xc) >> 2) << 13); + insn[1] = (insn[1] & ~0x40000) | (((slotbuf[0] & 0x10) >> 4) << 18); + insn[1] = (insn[1] & ~0x3800000) | (((slotbuf[0] & 0xe0) >> 5) << 23); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x300) >> 8) << 19); + insn[2] = (insn[2] & ~0xf800) | (((slotbuf[0] & 0x7c00) >> 10) << 11); + insn[0] = (insn[0] & ~0x8000000) | (((slotbuf[0] & 0x8000) >> 15) << 27); + insn[1] = (insn[1] & ~0x780000) | (((slotbuf[0] & 0xf0000) >> 16) << 19); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x100000) >> 20) << 31); + insn[2] = (insn[2] & ~0xe0000000) | (((slotbuf[0] & 0xe00000) >> 21) << 29); + insn[3] = (insn[3] & ~0x3) | ((slotbuf[0] & 0x3000000) >> 24); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x4000000) >> 26) << 21); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x8000000) >> 27) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x10000000) >> 28) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x20000000) >> 29) << 24); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x40000000) >> 30) << 26); +} + +static void +Slot_f2_Format_f2_s3_alu_21_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0x400000) >> 22); + slotbuf[0] = (slotbuf[0] & ~0xe) | (((insn[1] & 0x38) >> 3) << 1); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[0] & 0x200000) >> 21) << 4); + slotbuf[0] = (slotbuf[0] & ~0x20) | (((insn[0] & 0x4000000) >> 26) << 5); + slotbuf[0] = (slotbuf[0] & ~0xc0) | (((insn[1] & 0x18000) >> 15) << 6); + slotbuf[0] = (slotbuf[0] & ~0x100) | (((insn[2] & 0x200) >> 9) << 8); + slotbuf[0] = (slotbuf[0] & ~0x200) | (((insn[2] & 0x1000000) >> 24) << 9); + slotbuf[0] = (slotbuf[0] & ~0x1c00) | (((insn[1] & 0x1c0) >> 6) << 10); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[1] & 0x1800) >> 11) << 13); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x1c0) >> 6) << 15); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[2] & 0x30) >> 4) << 18); + slotbuf[0] = (slotbuf[0] & ~0x300000) | (((insn[1] & 0x60000000) >> 29) << 20); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[2] & 0x200000) >> 21) << 22); + slotbuf[0] = (slotbuf[0] & ~0x3800000) | (((insn[3] & 0x1c) >> 2) << 23); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x8000000) >> 27) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x10000000) >> 28) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x20000000) >> 29) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x40000000) >> 30) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x80000000) >> 31) << 30); +} + +static void +Slot_f2_Format_f2_s3_alu_21_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0x400000) | ((slotbuf[0] & 0x1) << 22); + insn[1] = (insn[1] & ~0x38) | (((slotbuf[0] & 0xe) >> 1) << 3); + insn[0] = (insn[0] & ~0x200000) | (((slotbuf[0] & 0x10) >> 4) << 21); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x20) >> 5) << 26); + insn[1] = (insn[1] & ~0x18000) | (((slotbuf[0] & 0xc0) >> 6) << 15); + insn[2] = (insn[2] & ~0x200) | (((slotbuf[0] & 0x100) >> 8) << 9); + insn[2] = (insn[2] & ~0x1000000) | (((slotbuf[0] & 0x200) >> 9) << 24); + insn[1] = (insn[1] & ~0x1c0) | (((slotbuf[0] & 0x1c00) >> 10) << 6); + insn[1] = (insn[1] & ~0x1800) | (((slotbuf[0] & 0x6000) >> 13) << 11); + insn[2] = (insn[2] & ~0x1c0) | (((slotbuf[0] & 0x38000) >> 15) << 6); + insn[2] = (insn[2] & ~0x30) | (((slotbuf[0] & 0xc0000) >> 18) << 4); + insn[1] = (insn[1] & ~0x60000000) | (((slotbuf[0] & 0x300000) >> 20) << 29); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[0] & 0x400000) >> 22) << 21); + insn[3] = (insn[3] & ~0x1c) | (((slotbuf[0] & 0x3800000) >> 23) << 2); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x4000000) >> 26) << 27); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x8000000) >> 27) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x10000000) >> 28) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x20000000) >> 29) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x40000000) >> 30) << 31); +} + +static void +Slot_f3_Format_f3_s0_ldst_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[0] & 0x3e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x2) >> 1) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc000) | (((insn[1] & 0x600) >> 9) << 14); + slotbuf[0] = (slotbuf[0] & ~0x30000) | (((insn[2] & 0xc0000000) >> 30) << 16); + slotbuf[0] = (slotbuf[0] & ~0xfc0000) | ((insn[3] & 0x3f) << 18); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x4000000) >> 26) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x8000000) >> 27) << 25); +} + +static void +Slot_f3_Format_f3_s0_ldst_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0x3e0000) | (((slotbuf[0] & 0x1f00) >> 8) << 17); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x2000) >> 13) << 1); + insn[1] = (insn[1] & ~0x600) | (((slotbuf[0] & 0xc000) >> 14) << 9); + insn[2] = (insn[2] & ~0xc0000000) | (((slotbuf[0] & 0x30000) >> 16) << 30); + insn[3] = (insn[3] & ~0x3f) | ((slotbuf[0] & 0xfc0000) >> 18); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x1000000) >> 24) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x2000000) >> 25) << 27); +} + +static void +Slot_f3_Format_f3_s1_ld_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xe0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x8) | (((insn[0] & 0x10000) >> 16) << 3); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0x3c00000) >> 22) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf0000000) >> 28) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x20000) >> 17) << 12); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[0] & 0xc000000) >> 26) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1f8000) | (((insn[3] & 0xfc0) >> 6) << 15); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x10000000) >> 28) << 21); +} + +static void +Slot_f3_Format_f3_s1_ld_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xe0) | ((slotbuf[0] & 0x7) << 5); + insn[0] = (insn[0] & ~0x10000) | (((slotbuf[0] & 0x8) >> 3) << 16); + insn[0] = (insn[0] & ~0x3c00000) | (((slotbuf[0] & 0xf0) >> 4) << 22); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf00) >> 8) << 28); + insn[1] = (insn[1] & ~0x20000) | (((slotbuf[0] & 0x1000) >> 12) << 17); + insn[0] = (insn[0] & ~0xc000000) | (((slotbuf[0] & 0x6000) >> 13) << 26); + insn[3] = (insn[3] & ~0xfc0) | (((slotbuf[0] & 0x1f8000) >> 15) << 6); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x200000) >> 21) << 28); +} + +static void +Slot_f3_Format_f3_s2_mul_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x10) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x2) | ((insn[1] & 0x1) << 1); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[1] & 0x6000) >> 13) << 2); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[1] & 0x40000) >> 18) << 4); + slotbuf[0] = (slotbuf[0] & ~0xe0) | (((insn[1] & 0x3800000) >> 23) << 5); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[1] & 0x780000) >> 19) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3000) | (((insn[1] & 0xc000000) >> 26) << 12); + slotbuf[0] = (slotbuf[0] & ~0xc000) | (((insn[1] & 0x18000) >> 15) << 14); + slotbuf[0] = (slotbuf[0] & ~0x1f0000) | (((insn[3] & 0x1f000) >> 12) << 16); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x20000000) >> 29) << 21); +} + +static void +Slot_f3_Format_f3_s2_mul_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x10) | ((slotbuf[0] & 0x1) << 4); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x2) >> 1); + insn[1] = (insn[1] & ~0x6000) | (((slotbuf[0] & 0xc) >> 2) << 13); + insn[1] = (insn[1] & ~0x40000) | (((slotbuf[0] & 0x10) >> 4) << 18); + insn[1] = (insn[1] & ~0x3800000) | (((slotbuf[0] & 0xe0) >> 5) << 23); + insn[1] = (insn[1] & ~0x780000) | (((slotbuf[0] & 0xf00) >> 8) << 19); + insn[1] = (insn[1] & ~0xc000000) | (((slotbuf[0] & 0x3000) >> 12) << 26); + insn[1] = (insn[1] & ~0x18000) | (((slotbuf[0] & 0xc000) >> 14) << 15); + insn[3] = (insn[3] & ~0x1f000) | (((slotbuf[0] & 0x1f0000) >> 16) << 12); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x200000) >> 21) << 29); +} + +static void +Slot_f3_Format_f3_s3_alu_34_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1fc) >> 2); + slotbuf[0] = (slotbuf[0] & ~0x180) | (((insn[1] & 0x1800) >> 11) << 7); + slotbuf[0] = (slotbuf[0] & ~0x1e00) | (((insn[1] & 0xf0000000) >> 28) << 9); + slotbuf[0] = (slotbuf[0] & ~0x7e000) | ((insn[2] & 0x3f) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1f80000) | (((insn[2] & 0x7e00000) >> 21) << 19); + slotbuf[0] = (slotbuf[0] & ~0xe000000) | (((insn[3] & 0xe0000) >> 17) << 25); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x40000000) >> 30) << 28); +} + +static void +Slot_f3_Format_f3_s3_alu_34_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1fc) | ((slotbuf[0] & 0x7f) << 2); + insn[1] = (insn[1] & ~0x1800) | (((slotbuf[0] & 0x180) >> 7) << 11); + insn[1] = (insn[1] & ~0xf0000000) | (((slotbuf[0] & 0x1e00) >> 9) << 28); + insn[2] = (insn[2] & ~0x3f) | ((slotbuf[0] & 0x7e000) >> 13); + insn[2] = (insn[2] & ~0x7e00000) | (((slotbuf[0] & 0x1f80000) >> 19) << 21); + insn[3] = (insn[3] & ~0xe0000) | (((slotbuf[0] & 0xe000000) >> 25) << 17); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x10000000) >> 28) << 30); +} + +static void +Slot_f3_Format_f3_s4_alu_70_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0x1fffc0) >> 6); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x38000000) >> 27) << 15); + slotbuf[0] = (slotbuf[0] & ~0x7c0000) | (((insn[3] & 0x1f00000) >> 20) << 18); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x80000000) >> 31) << 23); +} + +static void +Slot_f3_Format_f3_s4_alu_70_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0x1fffc0) | ((slotbuf[0] & 0x7fff) << 6); + insn[2] = (insn[2] & ~0x38000000) | (((slotbuf[0] & 0x38000) >> 15) << 27); + insn[3] = (insn[3] & ~0x1f00000) | (((slotbuf[0] & 0x7c0000) >> 18) << 20); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x800000) >> 23) << 31); +} + +static void +Slot_f4_Format_f4_s0_ld_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[0] & 0x3e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x2) >> 1) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc000) | (((insn[1] & 0x600) >> 9) << 14); + slotbuf[0] = (slotbuf[0] & ~0x7f0000) | (((insn[2] & 0xfe000000) >> 25) << 16); + slotbuf[0] = (slotbuf[0] & ~0x1f800000) | ((insn[3] & 0x3f) << 23); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x80000) >> 19) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x100000) >> 20) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x200000) >> 21) << 31); +} + +static void +Slot_f4_Format_f4_s0_ld_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0x3e0000) | (((slotbuf[0] & 0x1f00) >> 8) << 17); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x2000) >> 13) << 1); + insn[1] = (insn[1] & ~0x600) | (((slotbuf[0] & 0xc000) >> 14) << 9); + insn[2] = (insn[2] & ~0xfe000000) | (((slotbuf[0] & 0x7f0000) >> 16) << 25); + insn[3] = (insn[3] & ~0x3f) | ((slotbuf[0] & 0x1f800000) >> 23); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x20000000) >> 29) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x40000000) >> 30) << 20); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x80000000) >> 31) << 21); +} + +static void +Slot_f4_Format_f4_s1_ld_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xe0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x8) | (((insn[0] & 0x10000) >> 16) << 3); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0x3c00000) >> 22) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf0000000) >> 28) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x20000) >> 17) << 12); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[0] & 0xc000000) >> 26) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1f8000) | (((insn[3] & 0xfc0) >> 6) << 15); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x400000) >> 22) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x800000) >> 23) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x1000000) >> 24) << 23); +} + +static void +Slot_f4_Format_f4_s1_ld_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xe0) | ((slotbuf[0] & 0x7) << 5); + insn[0] = (insn[0] & ~0x10000) | (((slotbuf[0] & 0x8) >> 3) << 16); + insn[0] = (insn[0] & ~0x3c00000) | (((slotbuf[0] & 0xf0) >> 4) << 22); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf00) >> 8) << 28); + insn[1] = (insn[1] & ~0x20000) | (((slotbuf[0] & 0x1000) >> 12) << 17); + insn[0] = (insn[0] & ~0xc000000) | (((slotbuf[0] & 0x6000) >> 13) << 26); + insn[3] = (insn[3] & ~0xfc0) | (((slotbuf[0] & 0x1f8000) >> 15) << 6); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x200000) >> 21) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x400000) >> 22) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x800000) >> 23) << 24); +} + +static void +Slot_f4_Format_f4_s2_mul_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x10) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x2) | ((insn[1] & 0x1) << 1); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[1] & 0x6000) >> 13) << 2); + slotbuf[0] = (slotbuf[0] & ~0x1f0) | (((insn[2] & 0x7c0) >> 6) << 4); + slotbuf[0] = (slotbuf[0] & ~0x3e00) | (((insn[1] & 0xf800000) >> 23) << 9); + slotbuf[0] = (slotbuf[0] & ~0x7c000) | (((insn[1] & 0x7c0000) >> 18) << 14); + slotbuf[0] = (slotbuf[0] & ~0xf80000) | (((insn[2] & 0xf800) >> 11) << 19); + slotbuf[0] = (slotbuf[0] & ~0x3000000) | (((insn[1] & 0x18000) >> 15) << 24); + slotbuf[0] = (slotbuf[0] & ~0x3c000000) | (((insn[3] & 0xf000) >> 12) << 26); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x4000000) >> 26) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x8000000) >> 27) << 31); + slotbuf[1] = ((insn[3] & 0x10000000) >> 28); +} + +static void +Slot_f4_Format_f4_s2_mul_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x10) | ((slotbuf[0] & 0x1) << 4); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x2) >> 1); + insn[1] = (insn[1] & ~0x6000) | (((slotbuf[0] & 0xc) >> 2) << 13); + insn[2] = (insn[2] & ~0x7c0) | (((slotbuf[0] & 0x1f0) >> 4) << 6); + insn[1] = (insn[1] & ~0xf800000) | (((slotbuf[0] & 0x3e00) >> 9) << 23); + insn[1] = (insn[1] & ~0x7c0000) | (((slotbuf[0] & 0x7c000) >> 14) << 18); + insn[2] = (insn[2] & ~0xf800) | (((slotbuf[0] & 0xf80000) >> 19) << 11); + insn[1] = (insn[1] & ~0x18000) | (((slotbuf[0] & 0x3000000) >> 24) << 15); + insn[3] = (insn[3] & ~0xf000) | (((slotbuf[0] & 0x3c000000) >> 26) << 12); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x40000000) >> 30) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x80000000) >> 31) << 27); + insn[3] = (insn[3] & ~0x10000000) | ((slotbuf[1] & 0x1) << 28); +} + +static void +Slot_f4_Format_f4_s3_alu_34_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1fc) >> 2); + slotbuf[0] = (slotbuf[0] & ~0x180) | (((insn[1] & 0x1800) >> 11) << 7); + slotbuf[0] = (slotbuf[0] & ~0x1e00) | (((insn[1] & 0xf0000000) >> 28) << 9); + slotbuf[0] = (slotbuf[0] & ~0x2000) | ((insn[2] & 0x1) << 13); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[2] & 0x1000000) >> 24) << 14); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[2] & 0x3e) >> 1) << 15); + slotbuf[0] = (slotbuf[0] & ~0xff00000) | (((insn[2] & 0xff0000) >> 16) << 20); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x10000) >> 16) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x20000000) >> 29) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x40000000) >> 30) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x80000000) >> 31) << 31); +} + +static void +Slot_f4_Format_f4_s3_alu_34_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1fc) | ((slotbuf[0] & 0x7f) << 2); + insn[1] = (insn[1] & ~0x1800) | (((slotbuf[0] & 0x180) >> 7) << 11); + insn[1] = (insn[1] & ~0xf0000000) | (((slotbuf[0] & 0x1e00) >> 9) << 28); + insn[2] = (insn[2] & ~0x1) | ((slotbuf[0] & 0x2000) >> 13); + insn[2] = (insn[2] & ~0x1000000) | (((slotbuf[0] & 0x4000) >> 14) << 24); + insn[2] = (insn[2] & ~0x3e) | (((slotbuf[0] & 0xf8000) >> 15) << 1); + insn[2] = (insn[2] & ~0xff0000) | (((slotbuf[0] & 0xff00000) >> 20) << 16); + insn[3] = (insn[3] & ~0x10000) | (((slotbuf[0] & 0x10000000) >> 28) << 16); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x20000000) >> 29) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x40000000) >> 30) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x80000000) >> 31) << 31); +} + +static void +Slot_f5_Format_f5_s0_base_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf000) >> 12); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf00) >> 8) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0x1e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7000) | ((insn[1] & 0x7) << 12); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[1] & 0x600) >> 9) << 15); + slotbuf[0] = (slotbuf[0] & ~0x7e0000) | (((insn[1] & 0x3f000) >> 12) << 17); + slotbuf[0] = (slotbuf[0] & ~0x7800000) | (((insn[1] & 0x780000) >> 19) << 23); + slotbuf[0] = (slotbuf[0] & ~0x18000000) | (((insn[1] & 0xc000000) >> 26) << 27); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[2] & 0x4000000) >> 26) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[2] & 0x8000000) >> 27) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[2] & 0x10000000) >> 28) << 31); + slotbuf[1] = ((insn[2] & 0x20000000) >> 29); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[2] & 0x40000000) >> 30) << 1); + slotbuf[1] = (slotbuf[1] & ~0x4) | (((insn[2] & 0x80000000) >> 31) << 2); + slotbuf[1] = (slotbuf[1] & ~0x8) | ((insn[3] & 0x1) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x2) >> 1) << 4); +} + +static void +Slot_f5_Format_f5_s0_base_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf000) | ((slotbuf[0] & 0xf) << 12); + insn[0] = (insn[0] & ~0xf00) | (((slotbuf[0] & 0xf0) >> 4) << 8); + insn[0] = (insn[0] & ~0x1e0000) | (((slotbuf[0] & 0xf00) >> 8) << 17); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x7000) >> 12); + insn[1] = (insn[1] & ~0x600) | (((slotbuf[0] & 0x18000) >> 15) << 9); + insn[1] = (insn[1] & ~0x3f000) | (((slotbuf[0] & 0x7e0000) >> 17) << 12); + insn[1] = (insn[1] & ~0x780000) | (((slotbuf[0] & 0x7800000) >> 23) << 19); + insn[1] = (insn[1] & ~0xc000000) | (((slotbuf[0] & 0x18000000) >> 27) << 26); + insn[2] = (insn[2] & ~0x4000000) | (((slotbuf[0] & 0x20000000) >> 29) << 26); + insn[2] = (insn[2] & ~0x8000000) | (((slotbuf[0] & 0x40000000) >> 30) << 27); + insn[2] = (insn[2] & ~0x10000000) | (((slotbuf[0] & 0x80000000) >> 31) << 28); + insn[2] = (insn[2] & ~0x20000000) | ((slotbuf[1] & 0x1) << 29); + insn[2] = (insn[2] & ~0x40000000) | (((slotbuf[1] & 0x2) >> 1) << 30); + insn[2] = (insn[2] & ~0x80000000) | (((slotbuf[1] & 0x4) >> 2) << 31); + insn[3] = (insn[3] & ~0x1) | ((slotbuf[1] & 0x8) >> 3); + insn[3] = (insn[3] & ~0x2) | (((slotbuf[1] & 0x10) >> 4) << 1); +} + +static void +Slot_f5_Format_f5_s1_base_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x3c00000) >> 22); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[0] & 0x10) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0x20) | (((insn[0] & 0x200000) >> 21) << 5); + slotbuf[0] = (slotbuf[0] & ~0xfc0) | (((insn[0] & 0xfc000000) >> 26) << 6); + slotbuf[0] = (slotbuf[0] & ~0xf000) | (((insn[1] & 0xf0000000) >> 28) << 12); + slotbuf[0] = (slotbuf[0] & ~0xf0000) | ((insn[2] & 0xf) << 16); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[3] & 0x4) >> 2) << 20); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x8) >> 3) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x10) >> 4) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x80) >> 7) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x100) >> 8) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x200) >> 9) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x400) >> 10) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x1000) >> 12) << 27); +} + +static void +Slot_f5_Format_f5_s1_base_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3c00000) | ((slotbuf[0] & 0xf) << 22); + insn[0] = (insn[0] & ~0x10) | (((slotbuf[0] & 0x10) >> 4) << 4); + insn[0] = (insn[0] & ~0x200000) | (((slotbuf[0] & 0x20) >> 5) << 21); + insn[0] = (insn[0] & ~0xfc000000) | (((slotbuf[0] & 0xfc0) >> 6) << 26); + insn[1] = (insn[1] & ~0xf0000000) | (((slotbuf[0] & 0xf000) >> 12) << 28); + insn[2] = (insn[2] & ~0xf) | ((slotbuf[0] & 0xf0000) >> 16); + insn[3] = (insn[3] & ~0x4) | (((slotbuf[0] & 0x100000) >> 20) << 2); + insn[3] = (insn[3] & ~0x8) | (((slotbuf[0] & 0x200000) >> 21) << 3); + insn[3] = (insn[3] & ~0x10) | (((slotbuf[0] & 0x400000) >> 22) << 4); + insn[3] = (insn[3] & ~0x80) | (((slotbuf[0] & 0x800000) >> 23) << 7); + insn[3] = (insn[3] & ~0x100) | (((slotbuf[0] & 0x1000000) >> 24) << 8); + insn[3] = (insn[3] & ~0x200) | (((slotbuf[0] & 0x2000000) >> 25) << 9); + insn[3] = (insn[3] & ~0x400) | (((slotbuf[0] & 0x4000000) >> 26) << 10); + insn[3] = (insn[3] & ~0x1000) | (((slotbuf[0] & 0x8000000) >> 27) << 12); +} + +static void +Slot_f5_Format_f5_s2_base_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x10000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0xe) | (((insn[0] & 0xe0) >> 5) << 1); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[1] & 0x40000) >> 18) << 4); + slotbuf[0] = (slotbuf[0] & ~0xe0) | (((insn[1] & 0x3800000) >> 23) << 5); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[2] & 0x180000) >> 19) << 8); + slotbuf[0] = (slotbuf[0] & ~0xc00) | (((insn[2] & 0x1800) >> 11) << 10); + slotbuf[0] = (slotbuf[0] & ~0x7f000) | (((insn[2] & 0x7f0) >> 4) << 12); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[3] & 0x2000) >> 13) << 19); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[3] & 0x4000) >> 14) << 20); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x8000) >> 15) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x10000) >> 16) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x80000) >> 19) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x100000) >> 20) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x200000) >> 21) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x400000) >> 22) << 26); +} + +static void +Slot_f5_Format_f5_s2_base_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x10000) | ((slotbuf[0] & 0x1) << 16); + insn[0] = (insn[0] & ~0xe0) | (((slotbuf[0] & 0xe) >> 1) << 5); + insn[1] = (insn[1] & ~0x40000) | (((slotbuf[0] & 0x10) >> 4) << 18); + insn[1] = (insn[1] & ~0x3800000) | (((slotbuf[0] & 0xe0) >> 5) << 23); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x300) >> 8) << 19); + insn[2] = (insn[2] & ~0x1800) | (((slotbuf[0] & 0xc00) >> 10) << 11); + insn[2] = (insn[2] & ~0x7f0) | (((slotbuf[0] & 0x7f000) >> 12) << 4); + insn[3] = (insn[3] & ~0x2000) | (((slotbuf[0] & 0x80000) >> 19) << 13); + insn[3] = (insn[3] & ~0x4000) | (((slotbuf[0] & 0x100000) >> 20) << 14); + insn[3] = (insn[3] & ~0x8000) | (((slotbuf[0] & 0x200000) >> 21) << 15); + insn[3] = (insn[3] & ~0x10000) | (((slotbuf[0] & 0x400000) >> 22) << 16); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x800000) >> 23) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x1000000) >> 24) << 20); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x2000000) >> 25) << 21); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x4000000) >> 26) << 22); +} + +static void +Slot_f5_Format_f5_s3_base_35_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0x400000) >> 22); + slotbuf[0] = (slotbuf[0] & ~0x7e) | (((insn[1] & 0x1f8) >> 3) << 1); + slotbuf[0] = (slotbuf[0] & ~0x80) | (((insn[1] & 0x800) >> 11) << 7); + slotbuf[0] = (slotbuf[0] & ~0x3f00) | (((insn[2] & 0x7e000) >> 13) << 8); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[2] & 0x200000) >> 21) << 14); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x3800000) >> 23) << 15); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[3] & 0x800000) >> 23) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[3] & 0x1000000) >> 24) << 19); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[3] & 0x4000000) >> 26) << 20); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x8000000) >> 27) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x10000000) >> 28) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x20000000) >> 29) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x40000000) >> 30) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x80000000) >> 31) << 25); +} + +static void +Slot_f5_Format_f5_s3_base_35_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0x400000) | ((slotbuf[0] & 0x1) << 22); + insn[1] = (insn[1] & ~0x1f8) | (((slotbuf[0] & 0x7e) >> 1) << 3); + insn[1] = (insn[1] & ~0x800) | (((slotbuf[0] & 0x80) >> 7) << 11); + insn[2] = (insn[2] & ~0x7e000) | (((slotbuf[0] & 0x3f00) >> 8) << 13); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[0] & 0x4000) >> 14) << 21); + insn[2] = (insn[2] & ~0x3800000) | (((slotbuf[0] & 0x38000) >> 15) << 23); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x40000) >> 18) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x80000) >> 19) << 24); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x100000) >> 20) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x200000) >> 21) << 27); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x400000) >> 22) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x800000) >> 23) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x1000000) >> 24) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x2000000) >> 25) << 31); +} + +static void +Slot_f11_Format_f11_s0_ld_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf000) >> 12); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf00) >> 8) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0x1e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0xf000) | ((insn[2] & 0xf) << 12); + slotbuf[0] = (slotbuf[0] & ~0xf0000) | (((insn[2] & 0x7800000) >> 23) << 16); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[2] & 0x40000000) >> 30) << 20); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x80000) >> 19) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x100000) >> 20) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x200000) >> 21) << 23); +} + +static void +Slot_f11_Format_f11_s0_ld_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf000) | ((slotbuf[0] & 0xf) << 12); + insn[0] = (insn[0] & ~0xf00) | (((slotbuf[0] & 0xf0) >> 4) << 8); + insn[0] = (insn[0] & ~0x1e0000) | (((slotbuf[0] & 0xf00) >> 8) << 17); + insn[2] = (insn[2] & ~0xf) | ((slotbuf[0] & 0xf000) >> 12); + insn[2] = (insn[2] & ~0x7800000) | (((slotbuf[0] & 0xf0000) >> 16) << 23); + insn[2] = (insn[2] & ~0x40000000) | (((slotbuf[0] & 0x100000) >> 20) << 30); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x200000) >> 21) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x400000) >> 22) << 20); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x800000) >> 23) << 21); +} + +static void +Slot_f11_Format_f11_s1_alu_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xe0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x8) | (((insn[0] & 0x10000) >> 16) << 3); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0x3c00000) >> 22) << 4); + slotbuf[0] = (slotbuf[0] & ~0x100) | (((insn[0] & 0x200000) >> 21) << 8); + slotbuf[0] = (slotbuf[0] & ~0x200) | (((insn[1] & 0x2) >> 1) << 9); + slotbuf[0] = (slotbuf[0] & ~0xc00) | (((insn[1] & 0x600) >> 9) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x8000000) >> 27) << 12); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x4) >> 2) << 13); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[1] & 0x20000) >> 17) << 14); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[1] & 0x4000000) >> 26) << 15); + slotbuf[0] = (slotbuf[0] & ~0x10000) | (((insn[0] & 0x4000000) >> 26) << 16); + slotbuf[0] = (slotbuf[0] & ~0x20000) | (((insn[0] & 0x80000000) >> 31) << 17); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x80000000) >> 31) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | ((insn[3] & 0x1) << 19); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[3] & 0x400000) >> 22) << 20); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x800000) >> 23) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x1000000) >> 24) << 22); +} + +static void +Slot_f11_Format_f11_s1_alu_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xe0) | ((slotbuf[0] & 0x7) << 5); + insn[0] = (insn[0] & ~0x10000) | (((slotbuf[0] & 0x8) >> 3) << 16); + insn[0] = (insn[0] & ~0x3c00000) | (((slotbuf[0] & 0xf0) >> 4) << 22); + insn[0] = (insn[0] & ~0x200000) | (((slotbuf[0] & 0x100) >> 8) << 21); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x200) >> 9) << 1); + insn[1] = (insn[1] & ~0x600) | (((slotbuf[0] & 0xc00) >> 10) << 9); + insn[1] = (insn[1] & ~0x8000000) | (((slotbuf[0] & 0x1000) >> 12) << 27); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[0] & 0x2000) >> 13) << 2); + insn[1] = (insn[1] & ~0x20000) | (((slotbuf[0] & 0x4000) >> 14) << 17); + insn[1] = (insn[1] & ~0x4000000) | (((slotbuf[0] & 0x8000) >> 15) << 26); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x10000) >> 16) << 26); + insn[0] = (insn[0] & ~0x80000000) | (((slotbuf[0] & 0x20000) >> 17) << 31); + insn[2] = (insn[2] & ~0x80000000) | (((slotbuf[0] & 0x40000) >> 18) << 31); + insn[3] = (insn[3] & ~0x1) | ((slotbuf[0] & 0x80000) >> 19); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x100000) >> 20) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x200000) >> 21) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x400000) >> 22) << 24); +} + +static void +Slot_f11_Format_f11_s2_mul_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x10) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x2) | ((insn[1] & 0x1) << 1); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[1] & 0x6000) >> 13) << 2); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0x78000000) >> 27) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[1] & 0x780000) >> 19) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x40000) >> 18) << 12); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x800000) >> 23) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc000) | (((insn[1] & 0x18000) >> 15) << 14); + slotbuf[0] = (slotbuf[0] & ~0x1f0000) | (((insn[3] & 0x3e) >> 1) << 16); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x4000000) >> 26) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x8000000) >> 27) << 22); +} + +static void +Slot_f11_Format_f11_s2_mul_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x10) | ((slotbuf[0] & 0x1) << 4); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x2) >> 1); + insn[1] = (insn[1] & ~0x6000) | (((slotbuf[0] & 0xc) >> 2) << 13); + insn[0] = (insn[0] & ~0x78000000) | (((slotbuf[0] & 0xf0) >> 4) << 27); + insn[1] = (insn[1] & ~0x780000) | (((slotbuf[0] & 0xf00) >> 8) << 19); + insn[1] = (insn[1] & ~0x40000) | (((slotbuf[0] & 0x1000) >> 12) << 18); + insn[1] = (insn[1] & ~0x800000) | (((slotbuf[0] & 0x2000) >> 13) << 23); + insn[1] = (insn[1] & ~0x18000) | (((slotbuf[0] & 0xc000) >> 14) << 15); + insn[3] = (insn[3] & ~0x3e) | (((slotbuf[0] & 0x1f0000) >> 16) << 1); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x200000) >> 21) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x400000) >> 22) << 27); +} + +static void +Slot_f11_Format_f11_s3_alu_35_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0x400000) >> 22); + slotbuf[0] = (slotbuf[0] & ~0x7e) | (((insn[1] & 0x1f8) >> 3) << 1); + slotbuf[0] = (slotbuf[0] & ~0x180) | (((insn[1] & 0x1800) >> 11) << 7); + slotbuf[0] = (slotbuf[0] & ~0x200) | (((insn[1] & 0x10000000) >> 28) << 9); + slotbuf[0] = (slotbuf[0] & ~0x1c00) | (((insn[2] & 0x1c0) >> 6) << 10); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[2] & 0x30) >> 4) << 13); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[1] & 0x60000000) >> 29) << 15); + slotbuf[0] = (slotbuf[0] & ~0x20000) | (((insn[2] & 0x200000) >> 21) << 17); + slotbuf[0] = (slotbuf[0] & ~0xfc0000) | (((insn[3] & 0xfc0) >> 6) << 18); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x10000000) >> 28) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x20000000) >> 29) << 25); +} + +static void +Slot_f11_Format_f11_s3_alu_35_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0x400000) | ((slotbuf[0] & 0x1) << 22); + insn[1] = (insn[1] & ~0x1f8) | (((slotbuf[0] & 0x7e) >> 1) << 3); + insn[1] = (insn[1] & ~0x1800) | (((slotbuf[0] & 0x180) >> 7) << 11); + insn[1] = (insn[1] & ~0x10000000) | (((slotbuf[0] & 0x200) >> 9) << 28); + insn[2] = (insn[2] & ~0x1c0) | (((slotbuf[0] & 0x1c00) >> 10) << 6); + insn[2] = (insn[2] & ~0x30) | (((slotbuf[0] & 0x6000) >> 13) << 4); + insn[1] = (insn[1] & ~0x60000000) | (((slotbuf[0] & 0x18000) >> 15) << 29); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[0] & 0x20000) >> 17) << 21); + insn[3] = (insn[3] & ~0xfc0) | (((slotbuf[0] & 0xfc0000) >> 18) << 6); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x1000000) >> 24) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x2000000) >> 25) << 29); +} + +static void +Slot_f11_Format_f11_s4_alu_56_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x3000000) >> 24); + slotbuf[0] = (slotbuf[0] & ~0x4) | (((insn[1] & 0x80000000) >> 31) << 2); + slotbuf[0] = (slotbuf[0] & ~0x7ff8) | (((insn[2] & 0x1ffe00) >> 9) << 3); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x38000000) >> 27) << 15); + slotbuf[0] = (slotbuf[0] & ~0x7c0000) | (((insn[3] & 0x1f000) >> 12) << 18); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x40000000) >> 30) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x80000000) >> 31) << 24); +} + +static void +Slot_f11_Format_f11_s4_alu_56_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x3000000) | ((slotbuf[0] & 0x3) << 24); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x4) >> 2) << 31); + insn[2] = (insn[2] & ~0x1ffe00) | (((slotbuf[0] & 0x7ff8) >> 3) << 9); + insn[2] = (insn[2] & ~0x38000000) | (((slotbuf[0] & 0x38000) >> 15) << 27); + insn[3] = (insn[3] & ~0x1f000) | (((slotbuf[0] & 0x7c0000) >> 18) << 12); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x800000) >> 23) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x1000000) >> 24) << 31); +} + +static void +Slot_n1_Format_n1_s0_ldst_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[0] & 0x3e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0x6000) | ((insn[1] & 0x3) << 13); + slotbuf[0] = (slotbuf[0] & ~0xff8000) | (((insn[1] & 0x3fe00) >> 9) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[1] & 0x1000000) >> 24) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[1] & 0x2000000) >> 25) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[1] & 0x4000000) >> 26) << 26); +} + +static void +Slot_n1_Format_n1_s0_ldst_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0x3e0000) | (((slotbuf[0] & 0x1f00) >> 8) << 17); + insn[1] = (insn[1] & ~0x3) | ((slotbuf[0] & 0x6000) >> 13); + insn[1] = (insn[1] & ~0x3fe00) | (((slotbuf[0] & 0xff8000) >> 15) << 9); + insn[1] = (insn[1] & ~0x1000000) | (((slotbuf[0] & 0x1000000) >> 24) << 24); + insn[1] = (insn[1] & ~0x2000000) | (((slotbuf[0] & 0x2000000) >> 25) << 25); + insn[1] = (insn[1] & ~0x4000000) | (((slotbuf[0] & 0x4000000) >> 26) << 26); +} + +static void +Slot_n1_Format_n1_s1_none_50_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x40000) >> 18); + slotbuf[0] = (slotbuf[0] & ~0x2) | (((insn[1] & 0x8000000) >> 27) << 1); + slotbuf[0] = (slotbuf[0] & ~0x4) | (((insn[1] & 0x10000000) >> 28) << 2); + slotbuf[0] = (slotbuf[0] & ~0x8) | (((insn[1] & 0x20000000) >> 29) << 3); +} + +static void +Slot_n1_Format_n1_s1_none_50_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x40000) | ((slotbuf[0] & 0x1) << 18); + insn[1] = (insn[1] & ~0x8000000) | (((slotbuf[0] & 0x2) >> 1) << 27); + insn[1] = (insn[1] & ~0x10000000) | (((slotbuf[0] & 0x4) >> 2) << 28); + insn[1] = (insn[1] & ~0x20000000) | (((slotbuf[0] & 0x8) >> 3) << 29); +} + +static void +Slot_n1_Format_n1_s2_mul_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x10000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0xe) | (((insn[0] & 0xe0) >> 5) << 1); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0x78000000) >> 27) << 4); + slotbuf[0] = (slotbuf[0] & ~0x3f00) | (((insn[1] & 0x1f8) >> 3) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7c000) | (((insn[0] & 0x7c00000) >> 22) << 14); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[0] & 0x80000000) >> 31) << 19); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[1] & 0x4) >> 2) << 20); + slotbuf[0] = (slotbuf[0] & ~0xe00000) | (((insn[1] & 0x380000) >> 19) << 21); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[1] & 0x40000000) >> 30) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[1] & 0x80000000) >> 31) << 25); +} + +static void +Slot_n1_Format_n1_s2_mul_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x10000) | ((slotbuf[0] & 0x1) << 16); + insn[0] = (insn[0] & ~0xe0) | (((slotbuf[0] & 0xe) >> 1) << 5); + insn[0] = (insn[0] & ~0x78000000) | (((slotbuf[0] & 0xf0) >> 4) << 27); + insn[1] = (insn[1] & ~0x1f8) | (((slotbuf[0] & 0x3f00) >> 8) << 3); + insn[0] = (insn[0] & ~0x7c00000) | (((slotbuf[0] & 0x7c000) >> 14) << 22); + insn[0] = (insn[0] & ~0x80000000) | (((slotbuf[0] & 0x80000) >> 19) << 31); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[0] & 0x100000) >> 20) << 2); + insn[1] = (insn[1] & ~0x380000) | (((slotbuf[0] & 0xe00000) >> 21) << 19); + insn[1] = (insn[1] & ~0x40000000) | (((slotbuf[0] & 0x1000000) >> 24) << 30); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x2000000) >> 25) << 31); +} + +static void +Slot_n2_Format_n2_s0_ldst_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[0] & 0x3e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0x6000) | ((insn[1] & 0x3) << 13); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[1] & 0x600) >> 9) << 15); + slotbuf[0] = (slotbuf[0] & ~0x7e0000) | (((insn[1] & 0x1f8) >> 3) << 17); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[1] & 0x800) >> 11) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[1] & 0x40000) >> 18) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[1] & 0x80000) >> 19) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[1] & 0x100000) >> 20) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[1] & 0x200000) >> 21) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[1] & 0x1000000) >> 24) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[1] & 0x2000000) >> 25) << 29); +} + +static void +Slot_n2_Format_n2_s0_ldst_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0x3e0000) | (((slotbuf[0] & 0x1f00) >> 8) << 17); + insn[1] = (insn[1] & ~0x3) | ((slotbuf[0] & 0x6000) >> 13); + insn[1] = (insn[1] & ~0x600) | (((slotbuf[0] & 0x18000) >> 15) << 9); + insn[1] = (insn[1] & ~0x1f8) | (((slotbuf[0] & 0x7e0000) >> 17) << 3); + insn[1] = (insn[1] & ~0x800) | (((slotbuf[0] & 0x800000) >> 23) << 11); + insn[1] = (insn[1] & ~0x40000) | (((slotbuf[0] & 0x1000000) >> 24) << 18); + insn[1] = (insn[1] & ~0x80000) | (((slotbuf[0] & 0x2000000) >> 25) << 19); + insn[1] = (insn[1] & ~0x100000) | (((slotbuf[0] & 0x4000000) >> 26) << 20); + insn[1] = (insn[1] & ~0x200000) | (((slotbuf[0] & 0x8000000) >> 27) << 21); + insn[1] = (insn[1] & ~0x1000000) | (((slotbuf[0] & 0x10000000) >> 28) << 24); + insn[1] = (insn[1] & ~0x2000000) | (((slotbuf[0] & 0x20000000) >> 29) << 25); +} + +static void +Slot_n2_Format_n2_s1_ld_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xe0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x8) | (((insn[0] & 0x10000) >> 16) << 3); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0x3c00000) >> 22) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf0000000) >> 28) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x4) >> 2) << 12); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[0] & 0xc000000) >> 26) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1f8000) | (((insn[1] & 0x3f000) >> 12) << 15); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[1] & 0x4000000) >> 26) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[1] & 0x8000000) >> 27) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[1] & 0x10000000) >> 28) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[1] & 0x20000000) >> 29) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[1] & 0x40000000) >> 30) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[1] & 0x80000000) >> 31) << 26); +} + +static void +Slot_n2_Format_n2_s1_ld_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xe0) | ((slotbuf[0] & 0x7) << 5); + insn[0] = (insn[0] & ~0x10000) | (((slotbuf[0] & 0x8) >> 3) << 16); + insn[0] = (insn[0] & ~0x3c00000) | (((slotbuf[0] & 0xf0) >> 4) << 22); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf00) >> 8) << 28); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[0] & 0x1000) >> 12) << 2); + insn[0] = (insn[0] & ~0xc000000) | (((slotbuf[0] & 0x6000) >> 13) << 26); + insn[1] = (insn[1] & ~0x3f000) | (((slotbuf[0] & 0x1f8000) >> 15) << 12); + insn[1] = (insn[1] & ~0x4000000) | (((slotbuf[0] & 0x200000) >> 21) << 26); + insn[1] = (insn[1] & ~0x8000000) | (((slotbuf[0] & 0x400000) >> 22) << 27); + insn[1] = (insn[1] & ~0x10000000) | (((slotbuf[0] & 0x800000) >> 23) << 28); + insn[1] = (insn[1] & ~0x20000000) | (((slotbuf[0] & 0x1000000) >> 24) << 29); + insn[1] = (insn[1] & ~0x40000000) | (((slotbuf[0] & 0x2000000) >> 25) << 30); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x4000000) >> 26) << 31); +} + +static void +Slot_n0_Format_n0_s0_ldst_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[0] & 0x3e0000) >> 17) << 8); + slotbuf[0] = (slotbuf[0] & ~0x6000) | ((insn[1] & 0x3) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1f8000) | (((insn[1] & 0x1f800) >> 11) << 15); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[1] & 0x1000000) >> 24) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[1] & 0x2000000) >> 25) << 22); +} + +static void +Slot_n0_Format_n0_s0_ldst_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0x3e0000) | (((slotbuf[0] & 0x1f00) >> 8) << 17); + insn[1] = (insn[1] & ~0x3) | ((slotbuf[0] & 0x6000) >> 13); + insn[1] = (insn[1] & ~0x1f800) | (((slotbuf[0] & 0x1f8000) >> 15) << 11); + insn[1] = (insn[1] & ~0x1000000) | (((slotbuf[0] & 0x200000) >> 21) << 24); + insn[1] = (insn[1] & ~0x2000000) | (((slotbuf[0] & 0x400000) >> 22) << 25); +} + +static void +Slot_n0_Format_n0_s1_none_49_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x20000) >> 17); + slotbuf[0] = (slotbuf[0] & ~0x2) | (((insn[1] & 0x4000000) >> 26) << 1); + slotbuf[0] = (slotbuf[0] & ~0x4) | (((insn[1] & 0x8000000) >> 27) << 2); +} + +static void +Slot_n0_Format_n0_s1_none_49_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x20000) | ((slotbuf[0] & 0x1) << 17); + insn[1] = (insn[1] & ~0x4000000) | (((slotbuf[0] & 0x2) >> 1) << 26); + insn[1] = (insn[1] & ~0x8000000) | (((slotbuf[0] & 0x4) >> 2) << 27); +} + +static void +Slot_n0_Format_n0_s2_none_50_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x40000) >> 18); + slotbuf[0] = (slotbuf[0] & ~0x2) | (((insn[1] & 0x10000000) >> 28) << 1); + slotbuf[0] = (slotbuf[0] & ~0x4) | (((insn[1] & 0x20000000) >> 29) << 2); +} + +static void +Slot_n0_Format_n0_s2_none_50_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x40000) | ((slotbuf[0] & 0x1) << 18); + insn[1] = (insn[1] & ~0x10000000) | (((slotbuf[0] & 0x2) >> 1) << 28); + insn[1] = (insn[1] & ~0x20000000) | (((slotbuf[0] & 0x4) >> 2) << 29); +} + +static void +Slot_n0_Format_n0_s3_alu_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x10000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0xe) | (((insn[0] & 0xe0) >> 5) << 1); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[1] & 0x3c) >> 2) << 4); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[0] & 0x18000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x7c00000) >> 22) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[1] & 0x7c0) >> 6) << 15); + slotbuf[0] = (slotbuf[0] & ~0x700000) | (((insn[0] & 0xe0000000) >> 29) << 20); + slotbuf[0] = (slotbuf[0] & ~0x3800000) | (((insn[1] & 0x380000) >> 19) << 23); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[1] & 0x40000000) >> 30) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[1] & 0x80000000) >> 31) << 27); +} + +static void +Slot_n0_Format_n0_s3_alu_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x10000) | ((slotbuf[0] & 0x1) << 16); + insn[0] = (insn[0] & ~0xe0) | (((slotbuf[0] & 0xe) >> 1) << 5); + insn[1] = (insn[1] & ~0x3c) | (((slotbuf[0] & 0xf0) >> 4) << 2); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x300) >> 8) << 27); + insn[0] = (insn[0] & ~0x7c00000) | (((slotbuf[0] & 0x7c00) >> 10) << 22); + insn[1] = (insn[1] & ~0x7c0) | (((slotbuf[0] & 0xf8000) >> 15) << 6); + insn[0] = (insn[0] & ~0xe0000000) | (((slotbuf[0] & 0x700000) >> 20) << 29); + insn[1] = (insn[1] & ~0x380000) | (((slotbuf[0] & 0x3800000) >> 23) << 19); + insn[1] = (insn[1] & ~0x40000000) | (((slotbuf[0] & 0x4000000) >> 26) << 30); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x8000000) >> 27) << 31); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst_get, + Field_s2_Slot_inst_get, + Field_r2_Slot_inst_get, + Field_t4_Slot_inst_get, + Field_s4_Slot_inst_get, + Field_r4_Slot_inst_get, + Field_t8_Slot_inst_get, + Field_s8_Slot_inst_get, + Field_r8_Slot_inst_get, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wbr18_imm_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 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+ 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_iq_tie2apb_inq0_pop_qdata_Slot_inst_get, + Field_fld_iq_tie2apb_inq0_is_ready_is_ready_Slot_inst_get, + Field_fld_inst_11_8_Slot_inst_get, + Field_fld_iq_tie2apb_inq0_nonblocking_peek_success_Slot_inst_get, + Field_fld_iq_tie2apb_inq0_nonblocking_peek_qdata_Slot_inst_get, + Field_fld_iq_tie2apb_inq0_nonblocking_pop_success_Slot_inst_get, + Field_fld_iq_tie2apb_inq0_nonblocking_pop_qdata_Slot_inst_get, + Field_fld_inst_23_8_Slot_inst_get, + Field_fld_iq_tie2apb_inq0_blocking_peek_qdata_Slot_inst_get, + Field_fld_inst_23_12_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_push_read_qaddr_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_push_read_qdata_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_push_write_qaddr_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_push_write_qdata_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_is_ready_is_ready_Slot_inst_get, + Field_fld_inst_3_0_Slot_inst_get, + Field_fld_inst_23_16_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_nonblocking_push_read_success_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_nonblocking_push_read_qaddr_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_nonblocking_push_read_qdata_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_nonblocking_push_write_success_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_nonblocking_push_write_qaddr_Slot_inst_get, + Field_fld_oq_tie2apb_outq0_nonblocking_push_write_qdata_Slot_inst_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst_set, + Field_s2_Slot_inst_set, + Field_r2_Slot_inst_set, + Field_t4_Slot_inst_set, + Field_s4_Slot_inst_set, + Field_r4_Slot_inst_set, + Field_t8_Slot_inst_set, + Field_s8_Slot_inst_set, + Field_r8_Slot_inst_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wbr18_imm_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_iq_tie2apb_inq0_pop_qdata_Slot_inst_set, + Field_fld_iq_tie2apb_inq0_is_ready_is_ready_Slot_inst_set, + Field_fld_inst_11_8_Slot_inst_set, + Field_fld_iq_tie2apb_inq0_nonblocking_peek_success_Slot_inst_set, + Field_fld_iq_tie2apb_inq0_nonblocking_peek_qdata_Slot_inst_set, + Field_fld_iq_tie2apb_inq0_nonblocking_pop_success_Slot_inst_set, + Field_fld_iq_tie2apb_inq0_nonblocking_pop_qdata_Slot_inst_set, + Field_fld_inst_23_8_Slot_inst_set, + Field_fld_iq_tie2apb_inq0_blocking_peek_qdata_Slot_inst_set, + Field_fld_inst_23_12_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_push_read_qaddr_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_push_read_qdata_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_push_write_qaddr_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_push_write_qdata_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_is_ready_is_ready_Slot_inst_set, + Field_fld_inst_3_0_Slot_inst_set, + Field_fld_inst_23_16_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_nonblocking_push_read_success_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_nonblocking_push_read_qaddr_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_nonblocking_push_read_qdata_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_nonblocking_push_write_success_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_nonblocking_push_write_qaddr_Slot_inst_set, + Field_fld_oq_tie2apb_outq0_nonblocking_push_write_qdata_Slot_inst_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_get, + Field_st_Slot_inst16a_get, + 0, + Field_imm4_Slot_inst16a_get, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + Field_imm6_Slot_inst16a_get, + Field_imm7_Slot_inst16a_get, + Field_t2_Slot_inst16a_get, + Field_s2_Slot_inst16a_get, + Field_r2_Slot_inst16a_get, + Field_t4_Slot_inst16a_get, + Field_s4_Slot_inst16a_get, + Field_r4_Slot_inst16a_get, + Field_t8_Slot_inst16a_get, + Field_s8_Slot_inst16a_get, + Field_r8_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 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+ 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_set, + Field_st_Slot_inst16a_set, + 0, + Field_imm4_Slot_inst16a_set, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + Field_imm6_Slot_inst16a_set, + Field_imm7_Slot_inst16a_set, + Field_t2_Slot_inst16a_set, + Field_s2_Slot_inst16a_set, + Field_r2_Slot_inst16a_set, + Field_t4_Slot_inst16a_set, + Field_s4_Slot_inst16a_set, + Field_r4_Slot_inst16a_set, + Field_t8_Slot_inst16a_set, + Field_s8_Slot_inst16a_set, + Field_r8_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 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+ 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_get, + Field_st_Slot_inst16b_get, + 0, + Field_imm4_Slot_inst16b_get, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + Field_t2_Slot_inst16b_get, + Field_s2_Slot_inst16b_get, + Field_r2_Slot_inst16b_get, + Field_t4_Slot_inst16b_get, + Field_s4_Slot_inst16b_get, + Field_r4_Slot_inst16b_get, + Field_t8_Slot_inst16b_get, + Field_s8_Slot_inst16b_get, + Field_r8_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 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+ 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_set, + Field_st_Slot_inst16b_set, + 0, + Field_imm4_Slot_inst16b_set, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + Field_t2_Slot_inst16b_set, + Field_s2_Slot_inst16b_set, + Field_r2_Slot_inst16b_set, + Field_t4_Slot_inst16b_set, + Field_s4_Slot_inst16b_set, + Field_r4_Slot_inst16b_set, + Field_t8_Slot_inst16b_set, + Field_s8_Slot_inst16b_set, + Field_r8_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f0_s0_ldst_get_field_fns[] = { + Field_t_Slot_f0_s0_ldst_get, + 0, + Field_bbi_Slot_f0_s0_ldst_get, + 0, + Field_imm8_Slot_f0_s0_ldst_get, + Field_s_Slot_f0_s0_ldst_get, + Field_imm12b_Slot_f0_s0_ldst_get, + Field_imm16_Slot_f0_s0_ldst_get, + 0, + 0, + Field_offset_Slot_f0_s0_ldst_get, + 0, + 0, + Field_op2_Slot_f0_s0_ldst_get, + Field_r_Slot_f0_s0_ldst_get, + 0, + 0, + Field_sae_Slot_f0_s0_ldst_get, + Field_sal_Slot_f0_s0_ldst_get, + Field_sargt_Slot_f0_s0_ldst_get, + 0, + Field_sas_Slot_f0_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_f0_s0_ldst_get, + 0, + Field_fld_f0_s0_ldst_11_4_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_11_9_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_12_0_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_12_11_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_12_2_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_12_4_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_12_8_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_13_9_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_15_15_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_11_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_19_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_20_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_3_0_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_7_5_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_7_6_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_7_7_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_8_0_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_8_4_Slot_f0_s0_ldst_get, + Field_fld_f0_s0_ldst_8_8_Slot_f0_s0_ldst_get, + Field_fld_bbe_shflimm_s0_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uus_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_valignr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vbre_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vrr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vrul_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_arr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_shift_vr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f0_s0_ldst_get, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f0_s0_ldst_get, + Field_fld_saimm4_Slot_f0_s0_ldst_get, + Field_fld_saimm5_Slot_f0_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f0_s0_ldst_set_field_fns[] = { + Field_t_Slot_f0_s0_ldst_set, + 0, + Field_bbi_Slot_f0_s0_ldst_set, + 0, + Field_imm8_Slot_f0_s0_ldst_set, + Field_s_Slot_f0_s0_ldst_set, + Field_imm12b_Slot_f0_s0_ldst_set, + Field_imm16_Slot_f0_s0_ldst_set, + 0, + 0, + Field_offset_Slot_f0_s0_ldst_set, + 0, + 0, + Field_op2_Slot_f0_s0_ldst_set, + Field_r_Slot_f0_s0_ldst_set, + 0, + 0, + Field_sae_Slot_f0_s0_ldst_set, + Field_sal_Slot_f0_s0_ldst_set, + Field_sargt_Slot_f0_s0_ldst_set, + 0, + Field_sas_Slot_f0_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_f0_s0_ldst_set, + 0, + Field_fld_f0_s0_ldst_11_4_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_11_8_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_11_9_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_12_0_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_12_11_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_12_12_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_12_2_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_12_4_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_12_8_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_13_9_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_15_15_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_11_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_12_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_13_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_14_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_15_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_16_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_17_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_18_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_19_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_20_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_27_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_33_9_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_3_0_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_7_4_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_7_5_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_7_6_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_7_7_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_8_0_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_8_4_Slot_f0_s0_ldst_set, + Field_fld_f0_s0_ldst_8_8_Slot_f0_s0_ldst_set, + Field_fld_bbe_shflimm_s0_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uus_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_valignr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vbre_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vrr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vrul_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_arr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_shift_vr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f0_s0_ldst_set, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f0_s0_ldst_set, + Field_fld_saimm4_Slot_f0_s0_ldst_set, + Field_fld_saimm5_Slot_f0_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f0_s1_ld_get_field_fns[] = { + Field_t_Slot_f0_s1_ld_get, + 0, + 0, + 0, + Field_imm8_Slot_f0_s1_ld_get, + Field_s_Slot_f0_s1_ld_get, + Field_imm12b_Slot_f0_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f0_s1_ld_get, + Field_r_Slot_f0_s1_ld_get, + 0, + 0, + Field_sae_Slot_f0_s1_ld_get, + Field_sal_Slot_f0_s1_ld_get, + Field_sargt_Slot_f0_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f0_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f0_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f0_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f0_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f0_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f0_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f0_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f0_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_f0_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_15_10_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_15_14_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_15_15_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_15_2_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_15_4_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_15_8_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_24_0_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_24_11_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_24_14_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_24_17_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_24_8_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_7_5_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_7_6_Slot_f0_s1_ld_get, + Field_fld_f0_s1_ld_7_7_Slot_f0_s1_ld_get, + Field_fld_bbe_ltrx2nimm_Slot_f0_s1_ld_get, + Field_fld_bbe_ltrxn_2imm_Slot_f0_s1_ld_get, + Field_fld_bbe_ltrxnimm_Slot_f0_s1_ld_get, + Field_fld_imm1_2n_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_sqz_vbr_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_sqz_vt_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vec_mov_arr_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vec_mov_vbr_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vec_mov_vt_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f0_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f0_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f0_s1_ld_set_field_fns[] = { + Field_t_Slot_f0_s1_ld_set, + 0, + 0, + 0, + Field_imm8_Slot_f0_s1_ld_set, + Field_s_Slot_f0_s1_ld_set, + Field_imm12b_Slot_f0_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f0_s1_ld_set, + Field_r_Slot_f0_s1_ld_set, + 0, + 0, + Field_sae_Slot_f0_s1_ld_set, + Field_sal_Slot_f0_s1_ld_set, + Field_sargt_Slot_f0_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f0_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f0_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f0_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f0_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f0_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f0_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f0_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f0_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_f0_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f0_s1_ld_12_11_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_12_12_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_12_4_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_15_10_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_15_13_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_15_14_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_15_15_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_15_2_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_15_4_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_15_8_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_24_0_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_24_11_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_24_12_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_24_13_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_24_14_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_24_16_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_24_17_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_24_18_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_24_8_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_3_0_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_3_2_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_7_0_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_7_2_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_7_3_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_7_4_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_7_5_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_7_6_Slot_f0_s1_ld_set, + Field_fld_f0_s1_ld_7_7_Slot_f0_s1_ld_set, + Field_fld_bbe_ltrx2nimm_Slot_f0_s1_ld_set, + Field_fld_bbe_ltrxn_2imm_Slot_f0_s1_ld_set, + Field_fld_bbe_ltrxnimm_Slot_f0_s1_ld_set, + Field_fld_imm1_2n_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_sqz_vbr_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_sqz_vt_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vec_mov_arr_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vec_mov_vbr_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vec_mov_vt_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f0_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f0_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f0_s2_mul_get_field_fns[] = { + Field_t_Slot_f0_s2_mul_get, + 0, + 0, + 0, + Field_imm8_Slot_f0_s2_mul_get, + Field_s_Slot_f0_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f0_s2_mul_get, + 0, + 0, + 0, + Field_sal_Slot_f0_s2_mul_get, + Field_sargt_Slot_f0_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f0_s2_mul_11_8_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_13_12_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_18_9_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_1_0_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_26_13_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_26_2_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_26_20_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_4_4_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_7_4_Slot_f0_s2_mul_get, + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_multiply_arr_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_multiply_vp_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_multiply_vr_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_multiply_vs_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_multiply_wvt_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f0_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f0_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f0_s2_mul_set_field_fns[] = { + Field_t_Slot_f0_s2_mul_set, + 0, + 0, + 0, + Field_imm8_Slot_f0_s2_mul_set, + Field_s_Slot_f0_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f0_s2_mul_set, + 0, + 0, + 0, + Field_sal_Slot_f0_s2_mul_set, + Field_sargt_Slot_f0_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f0_s2_mul_11_8_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_13_12_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_18_12_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_18_14_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_18_9_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_1_0_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_26_12_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_26_13_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_26_14_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_26_2_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_26_20_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_26_21_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_3_0_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_3_3_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_4_4_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_7_4_Slot_f0_s2_mul_set, + Field_fld_f0_s2_mul_7_5_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_multiply_arr_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_multiply_vp_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_multiply_vr_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_multiply_vs_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_multiply_wvt_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f0_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f0_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f0_s3_alu_get_field_fns[] = { + Field_t_Slot_f0_s3_alu_get, + 0, + 0, + 0, + Field_imm8_Slot_f0_s3_alu_get, + Field_s_Slot_f0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f0_s3_alu_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f0_s3_alu_get, + 0, + 0, + Field_fld_saimm4_Slot_f0_s3_alu_get, + Field_fld_saimm5_Slot_f0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f0_s3_alu_get, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f0_s3_alu_get, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_14_11_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_14_14_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_24_19_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_10_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_18_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_19_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_25_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_26_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_27_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_33_9_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_3_2_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_3_3_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_7_3_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_7_7_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_8_0_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_8_8_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_9_7_Slot_f0_s3_alu_get, + Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_get, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f0_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vbr_Slot_f0_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vr_Slot_f0_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vs_Slot_f0_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vt_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vt_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_spmisc_vbr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_spmisc_vr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_spmisc_vs_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_spmisc_vsm_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_spmisc_vt_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_arr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_isel_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_slct_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_slct_h_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_sr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_vbr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_vr_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_vs_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_vt_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_select_vu_Slot_f0_s3_alu_get, + Field_fld_ivp_sem_vec_shift_vs_Slot_f0_s3_alu_get, + Field_fld_saimm6_31_Slot_f0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f0_s3_alu_set_field_fns[] = { + Field_t_Slot_f0_s3_alu_set, + 0, + 0, + 0, + Field_imm8_Slot_f0_s3_alu_set, + Field_s_Slot_f0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f0_s3_alu_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f0_s3_alu_set, + 0, + 0, + Field_fld_saimm4_Slot_f0_s3_alu_set, + Field_fld_saimm5_Slot_f0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f0_s3_alu_set, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f0_s3_alu_set, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_0_0_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_14_10_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_14_11_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_14_13_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_14_14_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_14_8_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_24_10_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_24_13_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_24_19_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_24_20_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_10_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_13_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_18_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_19_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_20_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_25_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_26_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_27_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_28_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_33_9_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_3_0_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_3_1_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_3_2_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_3_3_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_7_3_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_7_4_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_7_7_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_8_0_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_8_8_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_9_0_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_9_7_Slot_f0_s3_alu_set, + Field_fld_f0_s3_alu_9_8_Slot_f0_s3_alu_set, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f0_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vbr_Slot_f0_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vr_Slot_f0_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vs_Slot_f0_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vt_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vt_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_spmisc_vbr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_spmisc_vr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_spmisc_vs_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_spmisc_vsm_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_spmisc_vt_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_arr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_isel_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_slct_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_slct_h_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_sr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_vbr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_vr_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_vs_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_vt_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_select_vu_Slot_f0_s3_alu_set, + Field_fld_ivp_sem_vec_shift_vs_Slot_f0_s3_alu_set, + Field_fld_saimm6_31_Slot_f0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 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+ 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f1_s0_ldstalu_get_field_fns[] = { + Field_t_Slot_f1_s0_ldstalu_get, + 0, + 0, + 0, + Field_imm8_Slot_f1_s0_ldstalu_get, + Field_s_Slot_f1_s0_ldstalu_get, + Field_imm12b_Slot_f1_s0_ldstalu_get, + Field_imm16_Slot_f1_s0_ldstalu_get, + 0, + 0, + Field_offset_Slot_f1_s0_ldstalu_get, + 0, + 0, + Field_op2_Slot_f1_s0_ldstalu_get, + Field_r_Slot_f1_s0_ldstalu_get, + 0, + 0, + Field_sae_Slot_f1_s0_ldstalu_get, + Field_sal_Slot_f1_s0_ldstalu_get, + Field_sargt_Slot_f1_s0_ldstalu_get, + 0, + Field_sas_Slot_f1_s0_ldstalu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_uus_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_valignr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_vbre_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_vr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_vrr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_ld_st_vrul_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_alu_arr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f1_s0_ldstalu_get, + Field_fld_saimm4_Slot_f1_s0_ldstalu_get, + Field_fld_saimm5_Slot_f1_s0_ldstalu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s0_ldstalu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f1_s0_ldstalu_12_0_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_12_12_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_12_2_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_12_4_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_12_8_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_14_12_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_14_14_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_15_15_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_14_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_19_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_20_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_6_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_8_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_3_0_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_5_0_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_5_4_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_7_5_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_7_7_Slot_f1_s0_ldstalu_get, + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_get, + Field_fld_bbe_selimm_s0_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_scatter_gather_vr_Slot_f1_s0_ldstalu_get, + Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f1_s0_ldstalu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f1_s0_ldstalu_set_field_fns[] = { + Field_t_Slot_f1_s0_ldstalu_set, + 0, + 0, + 0, + Field_imm8_Slot_f1_s0_ldstalu_set, + Field_s_Slot_f1_s0_ldstalu_set, + Field_imm12b_Slot_f1_s0_ldstalu_set, + Field_imm16_Slot_f1_s0_ldstalu_set, + 0, + 0, + Field_offset_Slot_f1_s0_ldstalu_set, + 0, + 0, + Field_op2_Slot_f1_s0_ldstalu_set, + Field_r_Slot_f1_s0_ldstalu_set, + 0, + 0, + Field_sae_Slot_f1_s0_ldstalu_set, + Field_sal_Slot_f1_s0_ldstalu_set, + Field_sargt_Slot_f1_s0_ldstalu_set, + 0, + Field_sas_Slot_f1_s0_ldstalu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_uus_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_valignr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_vbre_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_vr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_vrr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_ld_st_vrul_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_alu_arr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f1_s0_ldstalu_set, + Field_fld_saimm4_Slot_f1_s0_ldstalu_set, + Field_fld_saimm5_Slot_f1_s0_ldstalu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s0_ldstalu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f1_s0_ldstalu_12_0_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_12_12_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_12_2_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_12_4_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_12_8_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_14_10_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_14_12_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_14_14_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_15_15_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_12_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_13_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_14_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_15_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_16_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_17_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_18_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_19_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_20_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_6_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_8_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_30_9_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_3_0_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_5_0_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_5_4_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_7_4_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_7_5_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_7_7_Slot_f1_s0_ldstalu_set, + Field_fld_f1_s0_ldstalu_9_9_Slot_f1_s0_ldstalu_set, + Field_fld_bbe_selimm_s0_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_scatter_gather_vr_Slot_f1_s0_ldstalu_set, + Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f1_s0_ldstalu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f1_s1_ld_get_field_fns[] = { + Field_t_Slot_f1_s1_ld_get, + 0, + 0, + 0, + Field_imm8_Slot_f1_s1_ld_get, + Field_s_Slot_f1_s1_ld_get, + Field_imm12b_Slot_f1_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f1_s1_ld_get, + Field_r_Slot_f1_s1_ld_get, + 0, + 0, + Field_sae_Slot_f1_s1_ld_get, + Field_sal_Slot_f1_s1_ld_get, + Field_sargt_Slot_f1_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f1_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f1_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f1_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f1_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f1_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f1_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_vrr_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_ld_st_vrul_Slot_f1_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f1_s1_ld_get, + Field_fld_bbe_ltrxn_2imm_Slot_f1_s1_ld_get, + Field_fld_bbe_ltrxnimm_Slot_f1_s1_ld_get, + Field_fld_imm1_2n_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_sqz_vbr_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_sqz_vt_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vec_mov_arr_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vec_mov_vbr_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vec_mov_vt_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f1_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f1_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f1_s1_ld_12_10_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_12_12_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_12_9_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_15_10_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_15_14_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_15_2_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_15_4_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_15_8_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_1_0_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_26_11_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_26_2_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_3_0_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_7_5_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_7_6_Slot_f1_s1_ld_get, + Field_fld_f1_s1_ld_7_7_Slot_f1_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f1_s1_ld_set_field_fns[] = { + Field_t_Slot_f1_s1_ld_set, + 0, + 0, + 0, + Field_imm8_Slot_f1_s1_ld_set, + Field_s_Slot_f1_s1_ld_set, + Field_imm12b_Slot_f1_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f1_s1_ld_set, + Field_r_Slot_f1_s1_ld_set, + 0, + 0, + Field_sae_Slot_f1_s1_ld_set, + Field_sal_Slot_f1_s1_ld_set, + Field_sargt_Slot_f1_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f1_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f1_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f1_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f1_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f1_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f1_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_vrr_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_ld_st_vrul_Slot_f1_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f1_s1_ld_set, + Field_fld_bbe_ltrxn_2imm_Slot_f1_s1_ld_set, + Field_fld_bbe_ltrxnimm_Slot_f1_s1_ld_set, + Field_fld_imm1_2n_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_sqz_vbr_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_sqz_vt_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vec_mov_arr_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vec_mov_vbr_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vec_mov_vt_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f1_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f1_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f1_s1_ld_12_10_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_12_11_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_12_12_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_12_4_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_12_9_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_15_10_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_15_13_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_15_14_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_15_15_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_15_2_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_15_4_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_15_8_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_1_0_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_26_11_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_26_12_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_26_13_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_26_16_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_26_18_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_26_2_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_3_0_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_3_2_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_7_0_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_7_2_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_7_3_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_7_4_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_7_5_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_7_6_Slot_f1_s1_ld_set, + Field_fld_f1_s1_ld_7_7_Slot_f1_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f1_s2_mul_get_field_fns[] = { + Field_t_Slot_f1_s2_mul_get, + 0, + 0, + 0, + Field_imm8_Slot_f1_s2_mul_get, + Field_s_Slot_f1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s2_mul_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f1_s2_mul_get, + Field_fld_saimm4_Slot_f1_s2_mul_get, + Field_fld_saimm5_Slot_f1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f1_s2_mul_get, + 0, + Field_fld_ivp_sem_multiply_vr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_multiply_vs_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_multiply_wvt_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_13_2_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_13_5_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_28_20_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_28_4_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_28_5_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_3_2_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_4_4_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_get, + Field_fld_f1_s2_mul_9_6_Slot_f1_s2_mul_get, + Field_fld_bbe_selimm_s2_Slot_f1_s2_mul_get, + Field_fld_bbe_shflimm_s2_Slot_f1_s2_mul_get, + Field_fld_fp_sem_hp_fma_vbr_Slot_f1_s2_mul_get, + Field_fld_fp_sem_hp_fma_vr_Slot_f1_s2_mul_get, + Field_fld_fp_sem_hp_fma_vs_Slot_f1_s2_mul_get, + Field_fld_fp_sem_hp_fma_vt_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_multiply_vt_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_spfma_vbr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_spfma_vr_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_spfma_vs_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_spfma_vt_Slot_f1_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vt_Slot_f1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f1_s2_mul_set_field_fns[] = { + Field_t_Slot_f1_s2_mul_set, + 0, + 0, + 0, + Field_imm8_Slot_f1_s2_mul_set, + Field_s_Slot_f1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s2_mul_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f1_s2_mul_set, + Field_fld_saimm4_Slot_f1_s2_mul_set, + Field_fld_saimm5_Slot_f1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f1_s2_mul_set, + 0, + Field_fld_ivp_sem_multiply_vr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_multiply_vs_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_multiply_wvt_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f1_s2_mul_13_10_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_13_2_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_13_5_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_14_10_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_28_12_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_28_15_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_28_16_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_28_18_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_28_20_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_28_4_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_28_5_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_3_0_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_3_2_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_3_3_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_4_4_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_9_5_Slot_f1_s2_mul_set, + Field_fld_f1_s2_mul_9_6_Slot_f1_s2_mul_set, + Field_fld_bbe_selimm_s2_Slot_f1_s2_mul_set, + Field_fld_bbe_shflimm_s2_Slot_f1_s2_mul_set, + Field_fld_fp_sem_hp_fma_vbr_Slot_f1_s2_mul_set, + Field_fld_fp_sem_hp_fma_vr_Slot_f1_s2_mul_set, + Field_fld_fp_sem_hp_fma_vs_Slot_f1_s2_mul_set, + Field_fld_fp_sem_hp_fma_vt_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_multiply_vt_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_spfma_vbr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_spfma_vr_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_spfma_vs_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_spfma_vt_Slot_f1_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vt_Slot_f1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f1_s3_alu_get_field_fns[] = { + Field_t_Slot_f1_s3_alu_get, + 0, + 0, + 0, + Field_imm8_Slot_f1_s3_alu_get, + Field_s_Slot_f1_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f1_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s3_alu_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s3_alu_get, + 0, + 0, + Field_fld_saimm4_Slot_f1_s3_alu_get, + Field_fld_saimm5_Slot_f1_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f1_s3_alu_get, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f1_s3_alu_get, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f1_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f1_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vbr_Slot_f1_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vr_Slot_f1_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vs_Slot_f1_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vt_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vt_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_spmisc_vbr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_spmisc_vr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_spmisc_vs_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_spmisc_vsm_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_spmisc_vt_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_rep_arr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_select_isel_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f1_s3_alu_get, + 0, + 0, + Field_fld_ivp_sem_vec_select_sr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_select_vbr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_select_vr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_select_vs_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_select_vt_Slot_f1_s3_alu_get, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_f1_s3_alu_get, + Field_fld_saimm6_31_Slot_f1_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_14_10_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_14_13_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_14_14_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_19_14_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_19_19_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_19_7_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_30_17_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_30_19_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_30_22_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_30_6_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_30_8_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_3_2_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_3_3_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_5_0_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_9_1_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_9_2_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_9_3_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_9_7_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_get, + Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_arr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vr_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vs_Slot_f1_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vt_Slot_f1_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f1_s3_alu_set_field_fns[] = { + Field_t_Slot_f1_s3_alu_set, + 0, + 0, + 0, + Field_imm8_Slot_f1_s3_alu_set, + Field_s_Slot_f1_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f1_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f1_s3_alu_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f1_s3_alu_set, + 0, + 0, + Field_fld_saimm4_Slot_f1_s3_alu_set, + Field_fld_saimm5_Slot_f1_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f1_s3_alu_set, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f1_s3_alu_set, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f1_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f1_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f1_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vbr_Slot_f1_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vr_Slot_f1_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vs_Slot_f1_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vt_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vt_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_spmisc_vbr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_spmisc_vr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_spmisc_vs_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_spmisc_vsm_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_spmisc_vt_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_rep_arr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_select_isel_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f1_s3_alu_set, + 0, + 0, + Field_fld_ivp_sem_vec_select_sr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_select_vbr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_select_vr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_select_vs_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_select_vt_Slot_f1_s3_alu_set, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_f1_s3_alu_set, + Field_fld_saimm6_31_Slot_f1_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f1_s3_alu_0_0_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_14_10_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_14_13_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_14_14_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_14_8_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_19_14_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_19_15_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_19_19_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_19_4_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_19_7_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_30_15_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_30_17_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_30_19_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_30_20_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_30_22_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_30_23_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_30_6_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_30_8_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_3_0_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_3_1_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_3_2_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_3_3_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_5_0_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_9_0_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_9_1_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_9_2_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_9_3_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_9_7_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_9_8_Slot_f1_s3_alu_set, + Field_fld_f1_s3_alu_9_9_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_arr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vr_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vs_Slot_f1_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vt_Slot_f1_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f2_s0_ldst_get_field_fns[] = { + Field_t_Slot_f2_s0_ldst_get, + 0, + 0, + 0, + Field_imm8_Slot_f2_s0_ldst_get, + Field_s_Slot_f2_s0_ldst_get, + Field_imm12b_Slot_f2_s0_ldst_get, + Field_imm16_Slot_f2_s0_ldst_get, + 0, + 0, + Field_offset_Slot_f2_s0_ldst_get, + 0, + 0, + Field_op2_Slot_f2_s0_ldst_get, + Field_r_Slot_f2_s0_ldst_get, + 0, + 0, + Field_sae_Slot_f2_s0_ldst_get, + Field_sal_Slot_f2_s0_ldst_get, + Field_sargt_Slot_f2_s0_ldst_get, + 0, + Field_sas_Slot_f2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f2_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uus_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_valignr_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f2_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_i_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s0_ldst_get, + 0, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f2_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f2_s0_ldst_12_0_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_12_10_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_12_2_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_12_4_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_15_15_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_11_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_14_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_20_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_4_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_28_8_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_7_2_Slot_f2_s0_ldst_get, + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f2_s0_ldst_set_field_fns[] = { + Field_t_Slot_f2_s0_ldst_set, + 0, + 0, + 0, + Field_imm8_Slot_f2_s0_ldst_set, + Field_s_Slot_f2_s0_ldst_set, + Field_imm12b_Slot_f2_s0_ldst_set, + Field_imm16_Slot_f2_s0_ldst_set, + 0, + 0, + Field_offset_Slot_f2_s0_ldst_set, + 0, + 0, + Field_op2_Slot_f2_s0_ldst_set, + Field_r_Slot_f2_s0_ldst_set, + 0, + 0, + Field_sae_Slot_f2_s0_ldst_set, + Field_sal_Slot_f2_s0_ldst_set, + Field_sargt_Slot_f2_s0_ldst_set, + 0, + Field_sas_Slot_f2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f2_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uus_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_valignr_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f2_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_i_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s0_ldst_set, + 0, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f2_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f2_s0_ldst_12_0_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_12_10_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_12_2_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_12_4_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_12_8_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_15_15_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_11_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_12_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_13_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_14_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_15_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_16_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_17_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_18_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_20_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_4_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_28_8_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_3_0_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_3_2_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_7_2_Slot_f2_s0_ldst_set, + Field_fld_f2_s0_ldst_7_4_Slot_f2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f2_s1_ld_get_field_fns[] = { + Field_t_Slot_f2_s1_ld_get, + 0, + 0, + 0, + Field_imm8_Slot_f2_s1_ld_get, + Field_s_Slot_f2_s1_ld_get, + Field_imm12b_Slot_f2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f2_s1_ld_get, + Field_r_Slot_f2_s1_ld_get, + 0, + 0, + Field_sae_Slot_f2_s1_ld_get, + Field_sal_Slot_f2_s1_ld_get, + Field_sargt_Slot_f2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f2_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f2_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_vrr_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_ld_st_vrul_Slot_f2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f2_s1_ld_get, + Field_fld_bbe_ltrxn_2imm_Slot_f2_s1_ld_get, + Field_fld_bbe_ltrxnimm_Slot_f2_s1_ld_get, + Field_fld_imm1_2n_Slot_f2_s1_ld_get, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_arr_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f2_s1_ld_get, + 0, + Field_fld_ivp_sem_vec_mov_vt_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f2_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f2_s1_ld_12_10_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_12_9_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_15_10_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_15_14_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_15_2_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_15_4_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_15_8_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_1_0_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_26_11_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_26_2_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_3_0_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_7_6_Slot_f2_s1_ld_get, + Field_fld_f2_s1_ld_7_7_Slot_f2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f2_s1_ld_set_field_fns[] = { + Field_t_Slot_f2_s1_ld_set, + 0, + 0, + 0, + Field_imm8_Slot_f2_s1_ld_set, + Field_s_Slot_f2_s1_ld_set, + Field_imm12b_Slot_f2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f2_s1_ld_set, + Field_r_Slot_f2_s1_ld_set, + 0, + 0, + Field_sae_Slot_f2_s1_ld_set, + Field_sal_Slot_f2_s1_ld_set, + Field_sargt_Slot_f2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f2_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f2_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_vrr_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_ld_st_vrul_Slot_f2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f2_s1_ld_set, + Field_fld_bbe_ltrxn_2imm_Slot_f2_s1_ld_set, + Field_fld_bbe_ltrxnimm_Slot_f2_s1_ld_set, + Field_fld_imm1_2n_Slot_f2_s1_ld_set, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_arr_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f2_s1_ld_set, + 0, + Field_fld_ivp_sem_vec_mov_vt_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f2_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f2_s1_ld_12_10_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_12_11_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_12_4_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_12_9_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_15_10_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_15_13_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_15_14_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_15_15_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_15_2_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_15_4_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_15_8_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_1_0_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_26_11_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_26_12_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_26_13_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_26_16_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_26_18_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_26_2_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_3_0_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_3_2_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_7_0_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_7_2_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_7_3_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_7_4_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_7_6_Slot_f2_s1_ld_set, + Field_fld_f2_s1_ld_7_7_Slot_f2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f2_s2_mul_get_field_fns[] = { + Field_t_Slot_f2_s2_mul_get, + 0, + 0, + 0, + Field_imm8_Slot_f2_s2_mul_get, + Field_s_Slot_f2_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f2_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f2_s2_mul_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f2_s2_mul_get, + 0, + 0, + Field_fld_saimm4_Slot_f2_s2_mul_get, + Field_fld_saimm5_Slot_f2_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_multiply_vp_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_multiply_vr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_multiply_vs_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_multiply_wvt_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f2_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_fma_vbr_Slot_f2_s2_mul_get, + Field_fld_fp_sem_hp_fma_vr_Slot_f2_s2_mul_get, + Field_fld_fp_sem_hp_fma_vs_Slot_f2_s2_mul_get, + Field_fld_fp_sem_hp_fma_vt_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_multiply_vt_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_spfma_vbr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_spfma_vr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_spfma_vs_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_spfma_vt_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vt_Slot_f2_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_14_11_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_14_5_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_19_10_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_19_7_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_30_10_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_30_18_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_30_6_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_get, + Field_fld_f2_s2_mul_5_0_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_divide_lane_ctrl_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_divide_vr_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_divide_vs_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_divide_vt_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_divide_vu_Slot_f2_s2_mul_get, + Field_fld_ivp_sem_multiply_vbr_Slot_f2_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f2_s2_mul_set_field_fns[] = { + Field_t_Slot_f2_s2_mul_set, + 0, + 0, + 0, + Field_imm8_Slot_f2_s2_mul_set, + Field_s_Slot_f2_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f2_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f2_s2_mul_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f2_s2_mul_set, + 0, + 0, + Field_fld_saimm4_Slot_f2_s2_mul_set, + Field_fld_saimm5_Slot_f2_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_multiply_vp_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_multiply_vr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_multiply_vs_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_multiply_wvt_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f2_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_fma_vbr_Slot_f2_s2_mul_set, + Field_fld_fp_sem_hp_fma_vr_Slot_f2_s2_mul_set, + Field_fld_fp_sem_hp_fma_vs_Slot_f2_s2_mul_set, + Field_fld_fp_sem_hp_fma_vt_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_multiply_vt_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_spfma_vbr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_spfma_vr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_spfma_vs_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_spfma_vt_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vt_Slot_f2_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f2_s2_mul_14_10_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_14_11_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_14_5_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_19_10_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_19_15_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_19_7_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_30_10_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_30_12_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_30_15_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_30_18_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_30_19_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_30_20_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_30_21_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_30_6_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_3_0_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_4_0_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_4_3_Slot_f2_s2_mul_set, + Field_fld_f2_s2_mul_5_0_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_divide_lane_ctrl_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_divide_vr_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_divide_vs_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_divide_vt_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_divide_vu_Slot_f2_s2_mul_set, + Field_fld_ivp_sem_multiply_vbr_Slot_f2_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f2_s3_alu_get_field_fns[] = { + Field_t_Slot_f2_s3_alu_get, + 0, + 0, + 0, + Field_imm8_Slot_f2_s3_alu_get, + Field_s_Slot_f2_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f2_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f2_s3_alu_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f2_s3_alu_get, + 0, + 0, + Field_fld_saimm4_Slot_f2_s3_alu_get, + Field_fld_saimm5_Slot_f2_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f2_s3_alu_get, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f2_s3_alu_get, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f2_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f2_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f2_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vbr_Slot_f2_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vr_Slot_f2_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vs_Slot_f2_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vt_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vt_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_spmisc_vbr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_spmisc_vr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_spmisc_vs_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_spmisc_vsm_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_spmisc_vt_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_rep_arr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_select_isel_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f2_s3_alu_get, + 0, + 0, + Field_fld_ivp_sem_vec_select_sr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_select_vbr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_select_vr_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_select_vs_Slot_f2_s3_alu_get, + Field_fld_ivp_sem_vec_select_vt_Slot_f2_s3_alu_get, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_f2_s3_alu_get, + Field_fld_saimm6_31_Slot_f2_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_14_10_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_14_13_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_14_14_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_19_14_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_19_19_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_19_7_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_30_18_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_30_19_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_30_22_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_30_6_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_30_8_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_3_2_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_3_3_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_5_0_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_9_1_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_9_2_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_9_3_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_9_7_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_get, + Field_fld_f2_s3_alu_9_9_Slot_f2_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f2_s3_alu_set_field_fns[] = { + Field_t_Slot_f2_s3_alu_set, + 0, + 0, + 0, + Field_imm8_Slot_f2_s3_alu_set, + Field_s_Slot_f2_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f2_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f2_s3_alu_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f2_s3_alu_set, + 0, + 0, + Field_fld_saimm4_Slot_f2_s3_alu_set, + Field_fld_saimm5_Slot_f2_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f2_s3_alu_set, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f2_s3_alu_set, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f2_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f2_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f2_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vbr_Slot_f2_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vr_Slot_f2_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vs_Slot_f2_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vt_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vt_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_spmisc_vbr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_spmisc_vr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_spmisc_vs_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_spmisc_vsm_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_spmisc_vt_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_rep_arr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_select_isel_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f2_s3_alu_set, + 0, + 0, + Field_fld_ivp_sem_vec_select_sr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_select_vbr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_select_vr_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_select_vs_Slot_f2_s3_alu_set, + Field_fld_ivp_sem_vec_select_vt_Slot_f2_s3_alu_set, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_f2_s3_alu_set, + Field_fld_saimm6_31_Slot_f2_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f2_s3_alu_0_0_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_14_10_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_14_13_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_14_14_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_14_8_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_19_14_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_19_15_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_19_19_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_19_4_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_19_7_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_30_15_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_30_18_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_30_19_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_30_20_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_30_22_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_30_23_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_30_6_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_30_8_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_3_0_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_3_1_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_3_2_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_3_3_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_5_0_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_9_0_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_9_1_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_9_2_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_9_3_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_9_7_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_9_8_Slot_f2_s3_alu_set, + Field_fld_f2_s3_alu_9_9_Slot_f2_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f3_s0_ldst_get_field_fns[] = { + Field_t_Slot_f3_s0_ldst_get, + 0, + 0, + 0, + Field_imm8_Slot_f3_s0_ldst_get, + Field_s_Slot_f3_s0_ldst_get, + Field_imm12b_Slot_f3_s0_ldst_get, + Field_imm16_Slot_f3_s0_ldst_get, + 0, + 0, + Field_offset_Slot_f3_s0_ldst_get, + 0, + 0, + Field_op2_Slot_f3_s0_ldst_get, + Field_r_Slot_f3_s0_ldst_get, + 0, + 0, + Field_sae_Slot_f3_s0_ldst_get, + Field_sal_Slot_f3_s0_ldst_get, + Field_sargt_Slot_f3_s0_ldst_get, + 0, + Field_sas_Slot_f3_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uus_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_valignr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vbre_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vrr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vrul_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_arr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_shift_vr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f3_s0_ldst_get, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f3_s0_ldst_get, + Field_fld_saimm4_Slot_f3_s0_ldst_get, + Field_fld_saimm5_Slot_f3_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s0_ldst_0_0_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_12_0_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_12_11_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_12_12_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_12_4_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_12_8_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_13_9_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_15_15_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_1_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_11_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_19_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_20_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_4_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_8_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_3_0_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_7_5_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_7_7_Slot_f3_s0_ldst_get, + Field_fld_f3_s0_ldst_8_0_Slot_f3_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f3_s0_ldst_set_field_fns[] = { + Field_t_Slot_f3_s0_ldst_set, + 0, + 0, + 0, + Field_imm8_Slot_f3_s0_ldst_set, + Field_s_Slot_f3_s0_ldst_set, + Field_imm12b_Slot_f3_s0_ldst_set, + Field_imm16_Slot_f3_s0_ldst_set, + 0, + 0, + Field_offset_Slot_f3_s0_ldst_set, + 0, + 0, + Field_op2_Slot_f3_s0_ldst_set, + Field_r_Slot_f3_s0_ldst_set, + 0, + 0, + Field_sae_Slot_f3_s0_ldst_set, + Field_sal_Slot_f3_s0_ldst_set, + Field_sargt_Slot_f3_s0_ldst_set, + 0, + Field_sas_Slot_f3_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uus_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_valignr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vbre_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vrr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vrul_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_arr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_shift_vr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f3_s0_ldst_set, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f3_s0_ldst_set, + Field_fld_saimm4_Slot_f3_s0_ldst_set, + Field_fld_saimm5_Slot_f3_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s0_ldst_0_0_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_12_0_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_12_11_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_12_12_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_12_4_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_12_8_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_13_9_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_15_15_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_1_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_11_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_12_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_13_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_14_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_15_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_16_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_17_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_18_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_19_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_20_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_4_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_8_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_25_9_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_3_0_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_7_4_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_7_5_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_7_7_Slot_f3_s0_ldst_set, + Field_fld_f3_s0_ldst_8_0_Slot_f3_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f3_s1_ld_get_field_fns[] = { + Field_t_Slot_f3_s1_ld_get, + 0, + 0, + 0, + Field_imm8_Slot_f3_s1_ld_get, + Field_s_Slot_f3_s1_ld_get, + Field_imm12b_Slot_f3_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f3_s1_ld_get, + Field_r_Slot_f3_s1_ld_get, + 0, + 0, + Field_sae_Slot_f3_s1_ld_get, + Field_sal_Slot_f3_s1_ld_get, + Field_sargt_Slot_f3_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f3_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f3_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f3_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f3_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f3_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f3_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f3_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f3_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_f3_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f3_s1_ld_get, + Field_fld_bbe_ltrxn_2imm_Slot_f3_s1_ld_get, + Field_fld_bbe_ltrxnimm_Slot_f3_s1_ld_get, + Field_fld_imm1_2n_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_sqz_vbr_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_sqz_vt_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vec_mov_arr_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vec_mov_vbr_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vec_mov_vt_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f3_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f3_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s1_ld_12_11_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_12_2_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_12_4_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_12_8_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_0_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_10_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_16_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_21_9_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_3_0_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_7_0_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_get, + Field_fld_f3_s1_ld_7_7_Slot_f3_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f3_s1_ld_set_field_fns[] = { + Field_t_Slot_f3_s1_ld_set, + 0, + 0, + 0, + Field_imm8_Slot_f3_s1_ld_set, + Field_s_Slot_f3_s1_ld_set, + Field_imm12b_Slot_f3_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f3_s1_ld_set, + Field_r_Slot_f3_s1_ld_set, + 0, + 0, + Field_sae_Slot_f3_s1_ld_set, + Field_sal_Slot_f3_s1_ld_set, + Field_sargt_Slot_f3_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f3_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f3_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f3_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f3_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f3_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f3_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f3_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f3_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_f3_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f3_s1_ld_set, + Field_fld_bbe_ltrxn_2imm_Slot_f3_s1_ld_set, + Field_fld_bbe_ltrxnimm_Slot_f3_s1_ld_set, + Field_fld_imm1_2n_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_sqz_vbr_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_sqz_vt_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vec_mov_arr_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vec_mov_vbr_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vec_mov_vt_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f3_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f3_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s1_ld_12_11_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_12_2_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_12_4_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_12_8_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_0_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_10_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_11_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_12_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_13_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_15_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_16_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_17_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_8_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_21_9_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_3_0_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_3_2_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_4_0_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_4_3_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_4_4_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_7_0_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_7_2_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_7_4_Slot_f3_s1_ld_set, + Field_fld_f3_s1_ld_7_7_Slot_f3_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f3_s2_mul_get_field_fns[] = { + Field_t_Slot_f3_s2_mul_get, + 0, + 0, + 0, + Field_imm8_Slot_f3_s2_mul_get, + Field_s_Slot_f3_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f3_s2_mul_get, + 0, + 0, + 0, + Field_sal_Slot_f3_s2_mul_get, + Field_sargt_Slot_f3_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f3_s2_mul_get, + 0, + Field_fld_ivp_sem_multiply_vr_Slot_f3_s2_mul_get, + Field_fld_ivp_sem_multiply_vs_Slot_f3_s2_mul_get, + Field_fld_ivp_sem_multiply_wvt_Slot_f3_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f3_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f3_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f3_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f3_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s2_mul_11_8_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_13_12_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_13_7_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_21_0_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_21_13_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_21_15_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_7_4_Slot_f3_s2_mul_get, + Field_fld_f3_s2_mul_7_5_Slot_f3_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f3_s2_mul_set_field_fns[] = { + Field_t_Slot_f3_s2_mul_set, + 0, + 0, + 0, + Field_imm8_Slot_f3_s2_mul_set, + Field_s_Slot_f3_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f3_s2_mul_set, + 0, + 0, + 0, + Field_sal_Slot_f3_s2_mul_set, + Field_sargt_Slot_f3_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f3_s2_mul_set, + 0, + Field_fld_ivp_sem_multiply_vr_Slot_f3_s2_mul_set, + Field_fld_ivp_sem_multiply_vs_Slot_f3_s2_mul_set, + Field_fld_ivp_sem_multiply_wvt_Slot_f3_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f3_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f3_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f3_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f3_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s2_mul_11_8_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_13_12_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_13_7_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_21_0_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_21_12_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_21_13_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_21_14_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_21_15_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_21_16_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_3_0_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_3_3_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_4_0_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_7_4_Slot_f3_s2_mul_set, + Field_fld_f3_s2_mul_7_5_Slot_f3_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f3_s3_alu_get_field_fns[] = { + Field_t_Slot_f3_s3_alu_get, + 0, + 0, + 0, + Field_imm8_Slot_f3_s3_alu_get, + Field_s_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f3_s3_alu_get, + 0, + 0, + Field_fld_saimm4_Slot_f3_s3_alu_get, + Field_fld_saimm5_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f3_s3_alu_get, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f3_s3_alu_get, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f3_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vbr_Slot_f3_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vr_Slot_f3_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vs_Slot_f3_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vt_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vt_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_spmisc_vbr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_spmisc_vr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_spmisc_vs_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_spmisc_vsm_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_spmisc_vt_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_rep_arr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_select_isel_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_select_vr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_select_vs_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_select_vt_Slot_f3_s3_alu_get, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_f3_s3_alu_get, + Field_fld_saimm6_31_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_histogram_arr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vs_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vt_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_18_12_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_18_13_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_18_14_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_18_18_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_18_7_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_18_8_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_12_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_18_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_20_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_21_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_25_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_4_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_8_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_28_9_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_3_2_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_7_6_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_get, + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vbr_Slot_f3_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vbs_Slot_f3_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f3_s3_alu_set_field_fns[] = { + Field_t_Slot_f3_s3_alu_set, + 0, + 0, + 0, + Field_imm8_Slot_f3_s3_alu_set, + Field_s_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f3_s3_alu_set, + 0, + 0, + Field_fld_saimm4_Slot_f3_s3_alu_set, + Field_fld_saimm5_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f3_s3_alu_set, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f3_s3_alu_set, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_f3_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vbr_Slot_f3_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vr_Slot_f3_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vs_Slot_f3_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vt_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vt_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_spmisc_vbr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_spmisc_vr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_spmisc_vs_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_spmisc_vsm_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_spmisc_vt_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_rep_arr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_select_isel_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_select_vr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_select_vs_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_select_vt_Slot_f3_s3_alu_set, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_f3_s3_alu_set, + Field_fld_saimm6_31_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_histogram_arr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vs_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vt_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s3_alu_13_9_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_18_12_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_18_13_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_18_14_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_18_18_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_18_3_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_18_7_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_18_8_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_12_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_13_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_14_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_18_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_19_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_20_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_21_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_22_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_25_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_4_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_8_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_28_9_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_3_0_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_3_2_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_3_3_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_7_3_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_7_6_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_7_7_Slot_f3_s3_alu_set, + Field_fld_f3_s3_alu_8_0_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vbr_Slot_f3_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vbs_Slot_f3_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f3_s4_alu_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s4_alu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f3_s4_alu_get, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f3_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s4_alu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f3_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_get, + Field_fld_f3_s4_alu_23_0_Slot_f3_s4_alu_get, + Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_get, + Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_get, + Field_fld_f3_s4_alu_23_20_Slot_f3_s4_alu_get, + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_get, + Field_fld_f3_s4_alu_9_6_Slot_f3_s4_alu_get, + Field_fld_bbe_selimm_s4_Slot_f3_s4_alu_get, + Field_fld_bbe_shflimm_s4_Slot_f3_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_mtk_andpopc_c_Slot_f3_s4_alu_get, + Field_fld_mtk_andpopc_inb_Slot_f3_s4_alu_get, + Field_fld_mtk_andpopc_ina_Slot_f3_s4_alu_get, + Field_fld_mtk_andpopc_odata_Slot_f3_s4_alu_get, + 0, + Field_fld_f3_s4_alu_23_16_Slot_f3_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f3_s4_alu_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f3_s4_alu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f3_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_f3_s4_alu_set, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_f3_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f3_s4_alu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f3_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_f3_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f3_s4_alu_14_10_Slot_f3_s4_alu_set, + Field_fld_f3_s4_alu_23_0_Slot_f3_s4_alu_set, + Field_fld_f3_s4_alu_23_15_Slot_f3_s4_alu_set, + Field_fld_f3_s4_alu_23_18_Slot_f3_s4_alu_set, + Field_fld_f3_s4_alu_23_20_Slot_f3_s4_alu_set, + Field_fld_f3_s4_alu_9_5_Slot_f3_s4_alu_set, + Field_fld_f3_s4_alu_9_6_Slot_f3_s4_alu_set, + Field_fld_bbe_selimm_s4_Slot_f3_s4_alu_set, + Field_fld_bbe_shflimm_s4_Slot_f3_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_mtk_andpopc_c_Slot_f3_s4_alu_set, + Field_fld_mtk_andpopc_inb_Slot_f3_s4_alu_set, + Field_fld_mtk_andpopc_ina_Slot_f3_s4_alu_set, + Field_fld_mtk_andpopc_odata_Slot_f3_s4_alu_set, + 0, + Field_fld_f3_s4_alu_23_16_Slot_f3_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f4_s0_ld_get_field_fns[] = { + Field_t_Slot_f4_s0_ld_get, + 0, + Field_bbi_Slot_f4_s0_ld_get, + 0, + Field_imm8_Slot_f4_s0_ld_get, + Field_s_Slot_f4_s0_ld_get, + Field_imm12b_Slot_f4_s0_ld_get, + Field_imm16_Slot_f4_s0_ld_get, + 0, + 0, + Field_offset_Slot_f4_s0_ld_get, + 0, + 0, + Field_op2_Slot_f4_s0_ld_get, + Field_r_Slot_f4_s0_ld_get, + 0, + 0, + Field_sae_Slot_f4_s0_ld_get, + Field_sal_Slot_f4_s0_ld_get, + Field_sargt_Slot_f4_s0_ld_get, + 0, + Field_sas_Slot_f4_s0_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_f4_s0_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f4_s0_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f4_s0_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f4_s0_ld_get, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f4_s0_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vbre_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_vr_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_vrr_Slot_f4_s0_ld_get, + Field_fld_ivp_sem_ld_st_vrul_Slot_f4_s0_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f4_s0_ld_11_4_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_11_9_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_12_0_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_12_2_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_12_4_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_12_8_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_15_15_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_20_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_7_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_8_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_31_9_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_3_0_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_6_0_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_6_4_Slot_f4_s0_ld_get, + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f4_s0_ld_set_field_fns[] = { + Field_t_Slot_f4_s0_ld_set, + 0, + Field_bbi_Slot_f4_s0_ld_set, + 0, + Field_imm8_Slot_f4_s0_ld_set, + Field_s_Slot_f4_s0_ld_set, + Field_imm12b_Slot_f4_s0_ld_set, + Field_imm16_Slot_f4_s0_ld_set, + 0, + 0, + Field_offset_Slot_f4_s0_ld_set, + 0, + 0, + Field_op2_Slot_f4_s0_ld_set, + Field_r_Slot_f4_s0_ld_set, + 0, + 0, + Field_sae_Slot_f4_s0_ld_set, + Field_sal_Slot_f4_s0_ld_set, + Field_sargt_Slot_f4_s0_ld_set, + 0, + Field_sas_Slot_f4_s0_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_f4_s0_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f4_s0_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4x1_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4x2_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4x4_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f4_s0_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6x1_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6x2_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6x4_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm8x4_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f4_s0_ld_set, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f4_s0_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vbre_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_vr_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_vrr_Slot_f4_s0_ld_set, + Field_fld_ivp_sem_ld_st_vrul_Slot_f4_s0_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f4_s0_ld_11_4_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_11_8_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_11_9_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_12_0_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_12_2_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_12_4_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_12_8_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_15_15_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_12_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_13_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_15_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_16_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_17_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_18_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_20_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_27_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_7_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_8_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_31_9_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_3_0_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_6_0_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_6_4_Slot_f4_s0_ld_set, + Field_fld_f4_s0_ld_7_4_Slot_f4_s0_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f4_s1_ld_get_field_fns[] = { + Field_t_Slot_f4_s1_ld_get, + 0, + 0, + 0, + Field_imm8_Slot_f4_s1_ld_get, + Field_s_Slot_f4_s1_ld_get, + Field_imm12b_Slot_f4_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f4_s1_ld_get, + Field_r_Slot_f4_s1_ld_get, + 0, + 0, + Field_sae_Slot_f4_s1_ld_get, + Field_sal_Slot_f4_s1_ld_get, + Field_sargt_Slot_f4_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f4_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f4_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f4_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f4_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f4_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_ld_st_uul_Slot_f4_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f4_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f4_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_f4_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f4_s1_ld_get, + Field_fld_bbe_ltrxn_2imm_Slot_f4_s1_ld_get, + Field_fld_bbe_ltrxnimm_Slot_f4_s1_ld_get, + 0, + Field_fld_ivp_sem_sqz_vbr_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_sqz_vt_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_vec_mov_arr_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f4_s1_ld_get, + 0, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f4_s1_ld_get, + 0, + Field_fld_ivp_sem_vec_mov_vt_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f4_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f4_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f4_s1_ld_12_10_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_12_2_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_12_4_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_12_8_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_0_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_10_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_16_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_23_9_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_4_0_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_7_0_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_7_6_Slot_f4_s1_ld_get, + Field_fld_f4_s1_ld_7_7_Slot_f4_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f4_s1_ld_set_field_fns[] = { + Field_t_Slot_f4_s1_ld_set, + 0, + 0, + 0, + Field_imm8_Slot_f4_s1_ld_set, + Field_s_Slot_f4_s1_ld_set, + Field_imm12b_Slot_f4_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f4_s1_ld_set, + Field_r_Slot_f4_s1_ld_set, + 0, + 0, + Field_sae_Slot_f4_s1_ld_set, + Field_sal_Slot_f4_s1_ld_set, + Field_sargt_Slot_f4_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_f4_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_f4_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_f4_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_f4_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_f4_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_ld_st_uul_Slot_f4_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f4_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_f4_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_f4_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f4_s1_ld_set, + Field_fld_bbe_ltrxn_2imm_Slot_f4_s1_ld_set, + Field_fld_bbe_ltrxnimm_Slot_f4_s1_ld_set, + 0, + Field_fld_ivp_sem_sqz_vbr_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_sqz_vt_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_vec_mov_arr_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_f4_s1_ld_set, + 0, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_f4_s1_ld_set, + 0, + Field_fld_ivp_sem_vec_mov_vt_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_vec_mov_wvr_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_arr_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_vt_Slot_f4_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_f4_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f4_s1_ld_12_10_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_12_2_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_12_4_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_12_8_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_0_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_10_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_11_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_12_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_13_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_15_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_16_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_17_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_8_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_23_9_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_3_0_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_3_2_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_4_0_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_4_3_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_4_4_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_7_0_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_7_2_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_7_4_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_7_6_Slot_f4_s1_ld_set, + Field_fld_f4_s1_ld_7_7_Slot_f4_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f4_s2_mul_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f4_s2_mul_get, + Field_fld_ivp_sem_multiply_vp_Slot_f4_s2_mul_get, + Field_fld_ivp_sem_multiply_vr_Slot_f4_s2_mul_get, + Field_fld_ivp_sem_multiply_vs_Slot_f4_s2_mul_get, + Field_fld_ivp_sem_multiply_wvt_Slot_f4_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_get, + Field_fld_f4_s2_mul_32_8_Slot_f4_s2_mul_get, + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_get, + Field_fld_f4_s2_mul_7_0_Slot_f4_s2_mul_get, + Field_fld_ivp_sem_multiply_vq_Slot_f4_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f4_s2_mul_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f4_s2_mul_set, + Field_fld_ivp_sem_multiply_vp_Slot_f4_s2_mul_set, + Field_fld_ivp_sem_multiply_vr_Slot_f4_s2_mul_set, + Field_fld_ivp_sem_multiply_vs_Slot_f4_s2_mul_set, + Field_fld_ivp_sem_multiply_wvt_Slot_f4_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f4_s2_mul_32_26_Slot_f4_s2_mul_set, + Field_fld_f4_s2_mul_32_8_Slot_f4_s2_mul_set, + Field_fld_f4_s2_mul_3_0_Slot_f4_s2_mul_set, + Field_fld_f4_s2_mul_7_0_Slot_f4_s2_mul_set, + Field_fld_ivp_sem_multiply_vq_Slot_f4_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f4_s3_alu_get_field_fns[] = { + Field_t_Slot_f4_s3_alu_get, + 0, + 0, + 0, + Field_imm8_Slot_f4_s3_alu_get, + Field_s_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f4_s3_alu_get, + 0, + 0, + Field_fld_saimm4_Slot_f4_s3_alu_get, + Field_fld_saimm5_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f4_s3_alu_get, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_rep_arr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_isel_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_slct_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_slct_h_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_sr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_vbr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_vr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_vs_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_vt_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_select_vu_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_shift_vs_Slot_f4_s3_alu_get, + Field_fld_saimm6_31_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_histogram_arr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vs_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vt_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_histogram_vbr_Slot_f4_s3_alu_get, + Field_fld_ivp_sem_vec_histogram_vbs_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_14_14_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_14_6_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_19_13_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_19_6_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_19_8_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_24_13_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_24_18_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_24_21_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_31_19_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_31_28_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_31_7_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_31_8_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_3_2_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_3_3_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_6_0_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_get, + Field_fld_f4_s3_alu_9_8_Slot_f4_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f4_s3_alu_set_field_fns[] = { + Field_t_Slot_f4_s3_alu_set, + 0, + 0, + 0, + Field_imm8_Slot_f4_s3_alu_set, + Field_s_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f4_s3_alu_set, + 0, + 0, + Field_fld_saimm4_Slot_f4_s3_alu_set, + Field_fld_saimm5_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f4_s3_alu_set, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_rep_arr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_isel_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_slct_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_slct_h_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_sr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_vbr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_vr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_vs_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_vt_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_select_vu_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_shift_vs_Slot_f4_s3_alu_set, + Field_fld_saimm6_31_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_histogram_arr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vs_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vt_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_histogram_vbr_Slot_f4_s3_alu_set, + Field_fld_ivp_sem_vec_histogram_vbs_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f4_s3_alu_0_0_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_14_10_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_14_11_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_14_12_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_14_13_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_14_14_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_14_6_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_14_8_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_19_13_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_19_6_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_19_8_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_24_12_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_24_13_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_24_18_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_24_20_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_24_21_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_31_13_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_31_19_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_31_20_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_31_23_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_31_25_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_31_26_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_31_28_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_31_7_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_31_8_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_3_0_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_3_1_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_3_2_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_3_3_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_6_0_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_7_4_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_7_5_Slot_f4_s3_alu_set, + Field_fld_f4_s3_alu_9_8_Slot_f4_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f5_s0_base_get_field_fns[] = { + Field_t_Slot_f5_s0_base_get, + 0, + Field_bbi_Slot_f5_s0_base_get, + 0, + Field_imm8_Slot_f5_s0_base_get, + Field_s_Slot_f5_s0_base_get, + Field_imm12b_Slot_f5_s0_base_get, + Field_imm16_Slot_f5_s0_base_get, + 0, + 0, + Field_offset_Slot_f5_s0_base_get, + 0, + 0, + Field_op2_Slot_f5_s0_base_get, + Field_r_Slot_f5_s0_base_get, + 0, + 0, + Field_sae_Slot_f5_s0_base_get, + Field_sal_Slot_f5_s0_base_get, + Field_sargt_Slot_f5_s0_base_get, + 0, + Field_sas_Slot_f5_s0_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_f5_s0_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f5_s0_base_11_0_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_11_9_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_36_13_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_36_17_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_36_18_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_36_20_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_3_1_Slot_f5_s0_base_get, + Field_fld_f5_s0_base_7_4_Slot_f5_s0_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f5_s0_base_set_field_fns[] = { + Field_t_Slot_f5_s0_base_set, + 0, + Field_bbi_Slot_f5_s0_base_set, + 0, + Field_imm8_Slot_f5_s0_base_set, + Field_s_Slot_f5_s0_base_set, + Field_imm12b_Slot_f5_s0_base_set, + Field_imm16_Slot_f5_s0_base_set, + 0, + 0, + Field_offset_Slot_f5_s0_base_set, + 0, + 0, + Field_op2_Slot_f5_s0_base_set, + Field_r_Slot_f5_s0_base_set, + 0, + 0, + Field_sae_Slot_f5_s0_base_set, + Field_sal_Slot_f5_s0_base_set, + Field_sargt_Slot_f5_s0_base_set, + 0, + Field_sas_Slot_f5_s0_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_f5_s0_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f5_s0_base_11_0_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_11_8_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_11_9_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_36_12_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_36_13_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_36_16_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_36_17_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_36_18_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_36_20_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_36_27_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_3_0_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_3_1_Slot_f5_s0_base_set, + Field_fld_f5_s0_base_7_4_Slot_f5_s0_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f5_s1_base_get_field_fns[] = { + Field_t_Slot_f5_s1_base_get, + 0, + 0, + 0, + Field_imm8_Slot_f5_s1_base_get, + Field_s_Slot_f5_s1_base_get, + Field_imm12b_Slot_f5_s1_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f5_s1_base_get, + Field_r_Slot_f5_s1_base_get, + 0, + 0, + Field_sae_Slot_f5_s1_base_get, + Field_sal_Slot_f5_s1_base_get, + Field_sargt_Slot_f5_s1_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_get, + Field_fld_f5_s1_base_27_13_Slot_f5_s1_base_get, + Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_get, + Field_fld_f5_s1_base_27_17_Slot_f5_s1_base_get, + Field_fld_f5_s1_base_27_3_Slot_f5_s1_base_get, + Field_fld_f5_s1_base_2_0_Slot_f5_s1_base_get, + Field_fld_f5_s1_base_3_0_Slot_f5_s1_base_get, + Field_fld_f5_s1_base_7_4_Slot_f5_s1_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f5_s1_base_set_field_fns[] = { + Field_t_Slot_f5_s1_base_set, + 0, + 0, + 0, + Field_imm8_Slot_f5_s1_base_set, + Field_s_Slot_f5_s1_base_set, + Field_imm12b_Slot_f5_s1_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f5_s1_base_set, + Field_r_Slot_f5_s1_base_set, + 0, + 0, + Field_sae_Slot_f5_s1_base_set, + Field_sal_Slot_f5_s1_base_set, + Field_sargt_Slot_f5_s1_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f5_s1_base_27_12_Slot_f5_s1_base_set, + Field_fld_f5_s1_base_27_13_Slot_f5_s1_base_set, + Field_fld_f5_s1_base_27_16_Slot_f5_s1_base_set, + Field_fld_f5_s1_base_27_17_Slot_f5_s1_base_set, + Field_fld_f5_s1_base_27_3_Slot_f5_s1_base_set, + Field_fld_f5_s1_base_2_0_Slot_f5_s1_base_set, + Field_fld_f5_s1_base_3_0_Slot_f5_s1_base_set, + Field_fld_f5_s1_base_7_4_Slot_f5_s1_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f5_s2_base_get_field_fns[] = { + Field_t_Slot_f5_s2_base_get, + 0, + 0, + 0, + Field_imm8_Slot_f5_s2_base_get, + Field_s_Slot_f5_s2_base_get, + Field_imm12b_Slot_f5_s2_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f5_s2_base_get, + 0, + 0, + 0, + Field_sal_Slot_f5_s2_base_get, + Field_sargt_Slot_f5_s2_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f5_s2_base_1_0_Slot_f5_s2_base_get, + Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_get, + Field_fld_f5_s2_base_26_13_Slot_f5_s2_base_get, + Field_fld_f5_s2_base_26_16_Slot_f5_s2_base_get, + Field_fld_f5_s2_base_26_2_Slot_f5_s2_base_get, + Field_fld_f5_s2_base_26_8_Slot_f5_s2_base_get, + Field_fld_f5_s2_base_3_0_Slot_f5_s2_base_get, + Field_fld_f5_s2_base_7_4_Slot_f5_s2_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f5_s2_base_set_field_fns[] = { + Field_t_Slot_f5_s2_base_set, + 0, + 0, + 0, + Field_imm8_Slot_f5_s2_base_set, + Field_s_Slot_f5_s2_base_set, + Field_imm12b_Slot_f5_s2_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f5_s2_base_set, + 0, + 0, + 0, + Field_sal_Slot_f5_s2_base_set, + Field_sargt_Slot_f5_s2_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f5_s2_base_1_0_Slot_f5_s2_base_set, + Field_fld_f5_s2_base_26_12_Slot_f5_s2_base_set, + Field_fld_f5_s2_base_26_13_Slot_f5_s2_base_set, + Field_fld_f5_s2_base_26_16_Slot_f5_s2_base_set, + Field_fld_f5_s2_base_26_2_Slot_f5_s2_base_set, + Field_fld_f5_s2_base_26_8_Slot_f5_s2_base_set, + Field_fld_f5_s2_base_3_0_Slot_f5_s2_base_set, + Field_fld_f5_s2_base_7_4_Slot_f5_s2_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f5_s3_base_get_field_fns[] = { + Field_t_Slot_f5_s3_base_get, + 0, + 0, + 0, + Field_imm8_Slot_f5_s3_base_get, + Field_s_Slot_f5_s3_base_get, + Field_imm12b_Slot_f5_s3_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f5_s3_base_0_0_Slot_f5_s3_base_get, + Field_fld_f5_s3_base_25_1_Slot_f5_s3_base_get, + Field_fld_f5_s3_base_25_16_Slot_f5_s3_base_get, + Field_fld_f5_s3_base_25_8_Slot_f5_s3_base_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f5_s3_base_set_field_fns[] = { + Field_t_Slot_f5_s3_base_set, + 0, + 0, + 0, + Field_imm8_Slot_f5_s3_base_set, + Field_s_Slot_f5_s3_base_set, + Field_imm12b_Slot_f5_s3_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f5_s3_base_0_0_Slot_f5_s3_base_set, + Field_fld_f5_s3_base_25_1_Slot_f5_s3_base_set, + Field_fld_f5_s3_base_25_16_Slot_f5_s3_base_set, + Field_fld_f5_s3_base_25_8_Slot_f5_s3_base_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f11_s0_ld_get_field_fns[] = { + Field_t_Slot_f11_s0_ld_get, + 0, + 0, + 0, + Field_imm8_Slot_f11_s0_ld_get, + Field_s_Slot_f11_s0_ld_get, + Field_imm12b_Slot_f11_s0_ld_get, + Field_imm16_Slot_f11_s0_ld_get, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f11_s0_ld_get, + Field_r_Slot_f11_s0_ld_get, + 0, + 0, + Field_sae_Slot_f11_s0_ld_get, + Field_sal_Slot_f11_s0_ld_get, + Field_sargt_Slot_f11_s0_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_uul_Slot_f11_s0_ld_get, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f11_s0_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s0_ld_1_0_Slot_f11_s0_ld_get, + Field_fld_f11_s0_ld_23_0_Slot_f11_s0_ld_get, + Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_get, + Field_fld_f11_s0_ld_23_13_Slot_f11_s0_ld_get, + Field_fld_f11_s0_ld_23_16_Slot_f11_s0_ld_get, + Field_fld_f11_s0_ld_23_17_Slot_f11_s0_ld_get, + Field_fld_f11_s0_ld_23_20_Slot_f11_s0_ld_get, + Field_fld_f11_s0_ld_23_4_Slot_f11_s0_ld_get, + Field_fld_f11_s0_ld_3_0_Slot_f11_s0_ld_get, + Field_fld_f11_s0_ld_7_4_Slot_f11_s0_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f11_s0_ld_set_field_fns[] = { + Field_t_Slot_f11_s0_ld_set, + 0, + 0, + 0, + Field_imm8_Slot_f11_s0_ld_set, + Field_s_Slot_f11_s0_ld_set, + Field_imm12b_Slot_f11_s0_ld_set, + Field_imm16_Slot_f11_s0_ld_set, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f11_s0_ld_set, + Field_r_Slot_f11_s0_ld_set, + 0, + 0, + Field_sae_Slot_f11_s0_ld_set, + Field_sal_Slot_f11_s0_ld_set, + Field_sargt_Slot_f11_s0_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_uul_Slot_f11_s0_ld_set, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f11_s0_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s0_ld_1_0_Slot_f11_s0_ld_set, + Field_fld_f11_s0_ld_23_0_Slot_f11_s0_ld_set, + Field_fld_f11_s0_ld_23_12_Slot_f11_s0_ld_set, + Field_fld_f11_s0_ld_23_13_Slot_f11_s0_ld_set, + Field_fld_f11_s0_ld_23_16_Slot_f11_s0_ld_set, + Field_fld_f11_s0_ld_23_17_Slot_f11_s0_ld_set, + Field_fld_f11_s0_ld_23_20_Slot_f11_s0_ld_set, + Field_fld_f11_s0_ld_23_4_Slot_f11_s0_ld_set, + Field_fld_f11_s0_ld_3_0_Slot_f11_s0_ld_set, + Field_fld_f11_s0_ld_7_4_Slot_f11_s0_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f11_s1_alu_get_field_fns[] = { + Field_t_Slot_f11_s1_alu_get, + 0, + 0, + 0, + Field_imm8_Slot_f11_s1_alu_get, + Field_s_Slot_f11_s1_alu_get, + Field_imm12b_Slot_f11_s1_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f11_s1_alu_get, + Field_r_Slot_f11_s1_alu_get, + 0, + 0, + Field_sae_Slot_f11_s1_alu_get, + Field_sal_Slot_f11_s1_alu_get, + Field_sargt_Slot_f11_s1_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_uul_Slot_f11_s1_alu_get, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f11_s1_alu_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_f11_s1_alu_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_f11_s1_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f11_s1_alu_get, + Field_fld_bbe_ltrxn_2imm_Slot_f11_s1_alu_get, + Field_fld_bbe_ltrxnimm_Slot_f11_s1_alu_get, + Field_fld_imm1_2n_Slot_f11_s1_alu_get, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f11_s1_alu_get, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f11_s1_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s1_alu_12_10_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_12_11_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_12_12_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_12_9_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_15_13_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_15_14_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_15_15_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_15_2_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_22_0_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_22_13_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_22_14_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_3_0_Slot_f11_s1_alu_get, + Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_get, + Field_fld_ivp_sem_ld_st_vrul2_Slot_f11_s1_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f11_s1_alu_set_field_fns[] = { + Field_t_Slot_f11_s1_alu_set, + 0, + 0, + 0, + Field_imm8_Slot_f11_s1_alu_set, + Field_s_Slot_f11_s1_alu_set, + Field_imm12b_Slot_f11_s1_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_f11_s1_alu_set, + Field_r_Slot_f11_s1_alu_set, + 0, + 0, + Field_sae_Slot_f11_s1_alu_set, + Field_sal_Slot_f11_s1_alu_set, + Field_sargt_Slot_f11_s1_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_uul_Slot_f11_s1_alu_set, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_f11_s1_alu_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_f11_s1_alu_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_f11_s1_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_f11_s1_alu_set, + Field_fld_bbe_ltrxn_2imm_Slot_f11_s1_alu_set, + Field_fld_bbe_ltrxnimm_Slot_f11_s1_alu_set, + Field_fld_imm1_2n_Slot_f11_s1_alu_set, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f11_s1_alu_set, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f11_s1_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s1_alu_12_10_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_12_11_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_12_12_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_12_3_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_12_4_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_12_9_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_15_13_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_15_14_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_15_15_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_15_2_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_22_0_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_22_12_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_22_13_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_22_14_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_22_16_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_22_18_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_3_0_Slot_f11_s1_alu_set, + Field_fld_f11_s1_alu_7_4_Slot_f11_s1_alu_set, + Field_fld_ivp_sem_ld_st_vrul2_Slot_f11_s1_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f11_s2_mul_get_field_fns[] = { + Field_t_Slot_f11_s2_mul_get, + 0, + 0, + 0, + Field_imm8_Slot_f11_s2_mul_get, + Field_s_Slot_f11_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f11_s2_mul_get, + 0, + 0, + 0, + Field_sal_Slot_f11_s2_mul_get, + Field_sargt_Slot_f11_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s2_mul_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_vr_Slot_f11_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f11_s2_mul_get, + 0, + Field_fld_ivp_sem_multiply_vr_Slot_f11_s2_mul_get, + Field_fld_ivp_sem_multiply_vs_Slot_f11_s2_mul_get, + Field_fld_ivp_sem_multiply_wvt_Slot_f11_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f11_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f11_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f11_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f11_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_arr_Slot_f11_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s2_mul_11_8_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_13_12_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_13_7_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_22_0_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_22_13_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_22_15_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_22_8_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_7_4_Slot_f11_s2_mul_get, + Field_fld_f11_s2_mul_7_5_Slot_f11_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f11_s2_mul_set_field_fns[] = { + Field_t_Slot_f11_s2_mul_set, + 0, + 0, + 0, + Field_imm8_Slot_f11_s2_mul_set, + Field_s_Slot_f11_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f11_s2_mul_set, + 0, + 0, + 0, + Field_sal_Slot_f11_s2_mul_set, + Field_sargt_Slot_f11_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s2_mul_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_vr_Slot_f11_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_f11_s2_mul_set, + 0, + Field_fld_ivp_sem_multiply_vr_Slot_f11_s2_mul_set, + Field_fld_ivp_sem_multiply_vs_Slot_f11_s2_mul_set, + Field_fld_ivp_sem_multiply_wvt_Slot_f11_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_f11_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_f11_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_f11_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_f11_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_arr_Slot_f11_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s2_mul_11_8_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_13_12_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_13_7_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_22_0_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_22_12_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_22_13_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_22_14_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_22_15_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_22_16_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_22_8_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_3_0_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_3_3_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_4_0_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_7_4_Slot_f11_s2_mul_set, + Field_fld_f11_s2_mul_7_5_Slot_f11_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f11_s3_alu_get_field_fns[] = { + Field_t_Slot_f11_s3_alu_get, + 0, + 0, + 0, + Field_imm8_Slot_f11_s3_alu_get, + Field_s_Slot_f11_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f11_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_f11_s3_alu_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_f11_s3_alu_get, + 0, + 0, + Field_fld_saimm4_Slot_f11_s3_alu_get, + Field_fld_saimm5_Slot_f11_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f11_s3_alu_get, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f11_s3_alu_get, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f11_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_rep_arr_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_select_isel_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f11_s3_alu_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_select_vr_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_select_vs_Slot_f11_s3_alu_get, + Field_fld_ivp_sem_vec_select_vt_Slot_f11_s3_alu_get, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_f11_s3_alu_get, + Field_fld_saimm6_31_Slot_f11_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_14_13_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_14_8_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_1_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_11_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_14_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_16_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_17_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_22_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_25_8_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_get, + Field_fld_f11_s3_alu_9_9_Slot_f11_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f11_s3_alu_set_field_fns[] = { + Field_t_Slot_f11_s3_alu_set, + 0, + 0, + 0, + Field_imm8_Slot_f11_s3_alu_set, + Field_s_Slot_f11_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_f11_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_f11_s3_alu_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_f11_s3_alu_set, + 0, + 0, + Field_fld_saimm4_Slot_f11_s3_alu_set, + Field_fld_saimm5_Slot_f11_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_imm1_2n_Slot_f11_s3_alu_set, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_f11_s3_alu_set, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_f11_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vr_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vt_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_rep_arr_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_select_isel_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_select_ishfl_Slot_f11_s3_alu_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_select_vr_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_select_vs_Slot_f11_s3_alu_set, + Field_fld_ivp_sem_vec_select_vt_Slot_f11_s3_alu_set, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_f11_s3_alu_set, + Field_fld_saimm6_31_Slot_f11_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s3_alu_0_0_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_14_10_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_14_11_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_14_13_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_14_8_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_1_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_11_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_13_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_14_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_15_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_16_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_17_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_18_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_22_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_25_8_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_3_0_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_3_1_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_7_0_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_7_4_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_9_8_Slot_f11_s3_alu_set, + Field_fld_f11_s3_alu_9_9_Slot_f11_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_f11_s4_alu_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s4_alu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_f11_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s4_alu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s4_alu_24_0_Slot_f11_s4_alu_get, + Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_get, + Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_get, + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_mtk_andpopc_c_Slot_f11_s4_alu_get, + Field_fld_mtk_andpopc_inb_Slot_f11_s4_alu_get, + Field_fld_mtk_andpopc_ina_Slot_f11_s4_alu_get, + Field_fld_mtk_andpopc_odata_Slot_f11_s4_alu_get, + Field_fld_f11_s4_alu_24_16_Slot_f11_s4_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_f11_s4_alu_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_f11_s4_alu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_f11_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_f11_s4_alu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_f11_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_f11_s4_alu_24_0_Slot_f11_s4_alu_set, + Field_fld_f11_s4_alu_24_15_Slot_f11_s4_alu_set, + Field_fld_f11_s4_alu_24_18_Slot_f11_s4_alu_set, + Field_fld_f11_s4_alu_9_5_Slot_f11_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_mtk_andpopc_c_Slot_f11_s4_alu_set, + Field_fld_mtk_andpopc_inb_Slot_f11_s4_alu_set, + Field_fld_mtk_andpopc_ina_Slot_f11_s4_alu_set, + Field_fld_mtk_andpopc_odata_Slot_f11_s4_alu_set, + Field_fld_f11_s4_alu_24_16_Slot_f11_s4_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_n1_s0_ldst_get_field_fns[] = { + Field_t_Slot_n1_s0_ldst_get, + 0, + 0, + 0, + Field_imm8_Slot_n1_s0_ldst_get, + Field_s_Slot_n1_s0_ldst_get, + Field_imm12b_Slot_n1_s0_ldst_get, + Field_imm16_Slot_n1_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_n1_s0_ldst_get, + Field_r_Slot_n1_s0_ldst_get, + 0, + 0, + Field_sae_Slot_n1_s0_ldst_get, + Field_sal_Slot_n1_s0_ldst_get, + Field_sargt_Slot_n1_s0_ldst_get, + 0, + Field_sas_Slot_n1_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n1_s0_ldst_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n1_s0_ldst_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n1_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uul_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uus_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_valignr_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vbre_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vr_Slot_n1_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_n1_s0_ldst_get, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_n1_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_n1_s0_ldst_get, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n1_s0_ldst_get, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n1_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n1_s0_ldst_12_0_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_12_2_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_12_4_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_12_8_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_15_15_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_1_0_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_2_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_20_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_4_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_8_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_26_9_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_3_0_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_7_2_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_7_5_Slot_n1_s0_ldst_get, + Field_fld_n1_s0_ldst_7_6_Slot_n1_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_n1_s0_ldst_set_field_fns[] = { + Field_t_Slot_n1_s0_ldst_set, + 0, + 0, + 0, + Field_imm8_Slot_n1_s0_ldst_set, + Field_s_Slot_n1_s0_ldst_set, + Field_imm12b_Slot_n1_s0_ldst_set, + Field_imm16_Slot_n1_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_n1_s0_ldst_set, + Field_r_Slot_n1_s0_ldst_set, + 0, + 0, + Field_sae_Slot_n1_s0_ldst_set, + Field_sal_Slot_n1_s0_ldst_set, + Field_sargt_Slot_n1_s0_ldst_set, + 0, + Field_sas_Slot_n1_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n1_s0_ldst_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n1_s0_ldst_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n1_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uul_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uus_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_valignr_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vbre_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vr_Slot_n1_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_n1_s0_ldst_set, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_n1_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_n1_s0_ldst_set, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n1_s0_ldst_set, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n1_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n1_s0_ldst_12_0_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_12_12_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_12_2_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_12_4_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_12_8_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_15_15_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_1_0_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_12_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_13_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_15_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_16_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_17_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_18_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_2_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_20_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_4_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_8_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_26_9_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_3_0_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_3_2_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_7_2_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_7_4_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_7_5_Slot_n1_s0_ldst_set, + Field_fld_n1_s0_ldst_7_6_Slot_n1_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_n1_s1_none_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 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+ 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n1_s1_none_3_0_Slot_n1_s1_none_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_n1_s1_none_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n1_s1_none_3_0_Slot_n1_s1_none_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_n1_s2_mul_get_field_fns[] = { + Field_t_Slot_n1_s2_mul_get, + 0, + 0, + 0, + Field_imm8_Slot_n1_s2_mul_get, + Field_s_Slot_n1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_n1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_n1_s2_mul_get, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_vr_Slot_n1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_multiply_vp_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_multiply_vr_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_multiply_vs_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_multiply_wvt_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vbt_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_n1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_arr_Slot_n1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_fma_vbr_Slot_n1_s2_mul_get, + Field_fld_fp_sem_hp_fma_vr_Slot_n1_s2_mul_get, + Field_fld_fp_sem_hp_fma_vs_Slot_n1_s2_mul_get, + Field_fld_fp_sem_hp_fma_vt_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_multiply_vt_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_spfma_vbr_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_spfma_vr_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_spfma_vs_Slot_n1_s2_mul_get, + Field_fld_ivp_sem_spfma_vt_Slot_n1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n1_s2_mul_0_0_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_13_9_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_18_6_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_18_9_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_25_1_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_7_4_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_8_4_Slot_n1_s2_mul_get, + Field_fld_n1_s2_mul_8_8_Slot_n1_s2_mul_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_n1_s2_mul_set_field_fns[] = { + Field_t_Slot_n1_s2_mul_set, + 0, + 0, + 0, + Field_imm8_Slot_n1_s2_mul_set, + Field_s_Slot_n1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_n1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_n1_s2_mul_set, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_vr_Slot_n1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_multiply_arr_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_multiply_vp_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_multiply_vr_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_multiply_vs_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_multiply_wvt_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vr_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_vs_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvr_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_unpack_wvec_mov_wvt_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vbt_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_n1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_rep_arr_Slot_n1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_fma_vbr_Slot_n1_s2_mul_set, + Field_fld_fp_sem_hp_fma_vr_Slot_n1_s2_mul_set, + Field_fld_fp_sem_hp_fma_vs_Slot_n1_s2_mul_set, + Field_fld_fp_sem_hp_fma_vt_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_multiply_vt_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_spfma_vbr_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_spfma_vr_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_spfma_vs_Slot_n1_s2_mul_set, + Field_fld_ivp_sem_spfma_vt_Slot_n1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n1_s2_mul_0_0_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_13_9_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_18_14_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_18_6_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_18_9_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_25_1_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_25_12_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_25_14_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_25_19_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_25_21_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_3_0_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_3_3_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_7_4_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_8_4_Slot_n1_s2_mul_set, + Field_fld_n1_s2_mul_8_8_Slot_n1_s2_mul_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_n2_s0_ldst_get_field_fns[] = { + Field_t_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + Field_imm8_Slot_n2_s0_ldst_get, + Field_s_Slot_n2_s0_ldst_get, + Field_imm12b_Slot_n2_s0_ldst_get, + Field_imm16_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_n2_s0_ldst_get, + Field_r_Slot_n2_s0_ldst_get, + 0, + 0, + Field_sae_Slot_n2_s0_ldst_get, + Field_sal_Slot_n2_s0_ldst_get, + Field_sargt_Slot_n2_s0_ldst_get, + 0, + Field_sas_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n2_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uul_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uus_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_valignr_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vbre_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_ld_st_vr_Slot_n2_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_n2_s0_ldst_get, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_n2_s0_ldst_get, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_selimm_s0_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_vec_scatter_gather_vr_Slot_n2_s0_ldst_get, + Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n2_s0_ldst_12_0_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_12_11_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_12_4_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_12_8_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_13_11_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_15_15_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_10_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_11_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_14_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_20_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_5_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_29_8_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_3_0_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_4_0_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_4_4_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_7_6_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_8_0_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_8_4_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_9_5_Slot_n2_s0_ldst_get, + Field_fld_n2_s0_ldst_9_6_Slot_n2_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_n2_s0_ldst_set_field_fns[] = { + Field_t_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + Field_imm8_Slot_n2_s0_ldst_set, + Field_s_Slot_n2_s0_ldst_set, + Field_imm12b_Slot_n2_s0_ldst_set, + Field_imm16_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_n2_s0_ldst_set, + Field_r_Slot_n2_s0_ldst_set, + 0, + 0, + Field_sae_Slot_n2_s0_ldst_set, + Field_sal_Slot_n2_s0_ldst_set, + Field_sargt_Slot_n2_s0_ldst_set, + 0, + Field_sas_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n2_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb6_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh6_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uul_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uus_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_valignr_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vbre_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_ld_st_vr_Slot_n2_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_n2_s0_ldst_set, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_scatter_gather_ars_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_gt_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vbr_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vs_Slot_n2_s0_ldst_set, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_selimm_s0_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_vec_scatter_gather_vr_Slot_n2_s0_ldst_set, + Field_fld_ivp_sem_vec_specialized_seli_vs_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n2_s0_ldst_12_0_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_12_10_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_12_11_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_12_12_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_12_4_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_12_8_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_13_11_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_15_15_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_10_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_11_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_12_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_13_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_14_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_15_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_16_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_17_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_18_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_20_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_5_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_29_8_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_3_0_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_4_0_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_4_4_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_7_4_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_7_6_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_8_0_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_8_4_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_9_5_Slot_n2_s0_ldst_set, + Field_fld_n2_s0_ldst_9_6_Slot_n2_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_n2_s1_ld_get_field_fns[] = { + Field_t_Slot_n2_s1_ld_get, + 0, + 0, + 0, + Field_imm8_Slot_n2_s1_ld_get, + Field_s_Slot_n2_s1_ld_get, + Field_imm12b_Slot_n2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_n2_s1_ld_get, + Field_r_Slot_n2_s1_ld_get, + 0, + 0, + Field_sae_Slot_n2_s1_ld_get, + Field_sal_Slot_n2_s1_ld_get, + Field_sargt_Slot_n2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n2_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n2_s1_ld_get, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_ld_st_uul_Slot_n2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_ld_st_vbr_Slot_n2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_n2_s1_ld_get, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_n2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_n2_s1_ld_get, + Field_fld_bbe_ltrxn_2imm_Slot_n2_s1_ld_get, + Field_fld_bbe_ltrxnimm_Slot_n2_s1_ld_get, + Field_fld_imm1_2n_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_sqz_vbr_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_sqz_vt_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_arr_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_n2_s1_ld_get, + 0, + Field_fld_ivp_sem_vec_mov_vt_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vec_mov_wvr_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_arr_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_vt_Slot_n2_s1_ld_get, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_n2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n2_s1_ld_12_10_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_12_2_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_12_4_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_12_8_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_1_0_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_10_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_2_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_26_9_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_7_0_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_7_6_Slot_n2_s1_ld_get, + Field_fld_n2_s1_ld_7_7_Slot_n2_s1_ld_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_n2_s1_ld_set_field_fns[] = { + Field_t_Slot_n2_s1_ld_set, + 0, + 0, + 0, + Field_imm8_Slot_n2_s1_ld_set, + Field_s_Slot_n2_s1_ld_set, + Field_imm12b_Slot_n2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_n2_s1_ld_set, + Field_r_Slot_n2_s1_ld_set, + 0, + 0, + Field_sae_Slot_n2_s1_ld_set, + Field_sal_Slot_n2_s1_ld_set, + Field_sargt_Slot_n2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4b2n_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm4bn_2_Slot_n2_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6b2n_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimm6bn_2_Slot_n2_s1_ld_set, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_ld_st_uul_Slot_n2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_valignr_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_ld_st_vbr_Slot_n2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_n2_s1_ld_set, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_n2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_ltrx2nimm_Slot_n2_s1_ld_set, + Field_fld_bbe_ltrxn_2imm_Slot_n2_s1_ld_set, + Field_fld_bbe_ltrxnimm_Slot_n2_s1_ld_set, + Field_fld_imm1_2n_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_sqz_vbr_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_sqz_vt_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_art_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbs_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_arr_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm_movint_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_i_imm4_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_immmovvi_Slot_n2_s1_ld_set, + 0, + Field_fld_ivp_sem_vec_mov_vt_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vec_mov_wvr_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_gs_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_vec_scatter_gather_vt_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_arr_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_vt_Slot_n2_s1_ld_set, + Field_fld_ivp_sem_wvec_pack_wvr_Slot_n2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n2_s1_ld_12_10_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_12_2_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_12_4_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_12_8_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_1_0_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_10_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_11_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_12_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_13_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_15_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_16_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_17_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_2_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_8_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_26_9_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_3_0_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_3_2_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_4_0_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_4_3_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_4_4_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_7_0_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_7_2_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_7_4_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_7_6_Slot_n2_s1_ld_set, + Field_fld_n2_s1_ld_7_7_Slot_n2_s1_ld_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_n0_s0_ldst_get_field_fns[] = { + Field_t_Slot_n0_s0_ldst_get, + 0, + 0, + 0, + Field_imm8_Slot_n0_s0_ldst_get, + Field_s_Slot_n0_s0_ldst_get, + Field_imm12b_Slot_n0_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_n0_s0_ldst_get, + Field_r_Slot_n0_s0_ldst_get, + 0, + 0, + Field_sae_Slot_n0_s0_ldst_get, + Field_sal_Slot_n0_s0_ldst_get, + Field_sargt_Slot_n0_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_n0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n0_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n0_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n0_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n0_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n0_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uul_Slot_n0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_uus_Slot_n0_s0_ldst_get, + Field_fld_ivp_sem_ld_st_valignr_Slot_n0_s0_ldst_get, + 0, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_n0_s0_ldst_get, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_n0_s0_ldst_get, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_n0_s0_ldst_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_n0_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n0_s0_ldst_get, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n0_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n0_s0_ldst_12_0_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_12_12_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_12_2_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_12_4_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_12_8_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_22_0_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_22_16_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_3_0_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_7_5_Slot_n0_s0_ldst_get, + Field_fld_n0_s0_ldst_7_6_Slot_n0_s0_ldst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_n0_s0_ldst_set_field_fns[] = { + Field_t_Slot_n0_s0_ldst_set, + 0, + 0, + 0, + Field_imm8_Slot_n0_s0_ldst_set, + Field_s_Slot_n0_s0_ldst_set, + Field_imm12b_Slot_n0_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_n0_s0_ldst_set, + Field_r_Slot_n0_s0_ldst_set, + 0, + 0, + Field_sae_Slot_n0_s0_ldst_set, + Field_sal_Slot_n0_s0_ldst_set, + Field_sargt_Slot_n0_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_bbe_shflimm_s0_Slot_n0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimm4_Slot_n0_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm6_Slot_n0_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_ld_st_i_bimm8_Slot_n0_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb4_Slot_n0_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmb8_Slot_n0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_i_bimmh4_Slot_n0_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_i_bimmh8_Slot_n0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uul_Slot_n0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_uus_Slot_n0_s0_ldst_set, + Field_fld_ivp_sem_ld_st_valignr_Slot_n0_s0_ldst_set, + 0, + 0, + Field_fld_ivp_sem_ld_st_vr_Slot_n0_s0_ldst_set, + 0, + Field_fld_ivp_sem_ld_st_vrul_Slot_n0_s0_ldst_set, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vr_Slot_n0_s0_ldst_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_n0_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_specialized_seli_vr_Slot_n0_s0_ldst_set, + Field_fld_ivp_sem_vec_specialized_seli_vt_Slot_n0_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n0_s0_ldst_12_0_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_12_12_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_12_2_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_12_4_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_12_8_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_22_0_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_22_12_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_22_13_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_22_15_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_22_16_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_22_17_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_3_0_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_7_4_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_7_5_Slot_n0_s0_ldst_set, + Field_fld_n0_s0_ldst_7_6_Slot_n0_s0_ldst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_n0_s1_none_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n0_s1_none_2_0_Slot_n0_s1_none_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_n0_s1_none_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 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0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_n0_s2_none_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n0_s2_none_2_0_Slot_n0_s2_none_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_n0_s3_alu_get_field_fns[] = { + Field_t_Slot_n0_s3_alu_get, + 0, + 0, + 0, + Field_imm8_Slot_n0_s3_alu_get, + Field_s_Slot_n0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_n0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vt_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i32_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_i8_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_rep_vt_Slot_n0_s3_alu_get, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_shift_vt_Slot_n0_s3_alu_get, + 0, + 0, + Field_fld_saimm4_Slot_n0_s3_alu_get, + Field_fld_saimm5_Slot_n0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_n0_s3_alu_get, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_n0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_alu_vs_Slot_n0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_n0_s3_alu_get, + 0, + Field_fld_fp_sem_hp_cnv_vr_Slot_n0_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vs_Slot_n0_s3_alu_get, + Field_fld_fp_sem_hp_cnv_vt_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_sp32cvt_vt_Slot_n0_s3_alu_get, + 0, + Field_fld_ivp_sem_spmisc_vr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_spmisc_vs_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_spmisc_vsm_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_spmisc_vt_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_reduce_vt_Slot_n0_s3_alu_get, + 0, + Field_fld_ivp_sem_vec_select_isel_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_select_ishfl_Slot_n0_s3_alu_get, + 0, + 0, + Field_fld_ivp_sem_vec_select_sr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_select_vbr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_select_vr_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_select_vs_Slot_n0_s3_alu_get, + Field_fld_ivp_sem_vec_select_vt_Slot_n0_s3_alu_get, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_n0_s3_alu_get, + Field_fld_saimm6_31_Slot_n0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n0_s3_alu_14_10_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_14_13_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_14_14_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_19_12_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_19_13_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_27_13_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_27_15_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_27_16_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_27_19_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_27_22_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_27_3_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_2_0_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_7_0_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_9_3_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_9_6_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_9_7_Slot_n0_s3_alu_get, + Field_fld_n0_s3_alu_9_9_Slot_n0_s3_alu_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_n0_s3_alu_set_field_fns[] = { + Field_t_Slot_n0_s3_alu_set, + 0, + 0, + 0, + Field_imm8_Slot_n0_s3_alu_set, + Field_s_Slot_n0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_n0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vt_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i32_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_i8_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_rep_vt_Slot_n0_s3_alu_set, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_shift_vr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_shift_vt_Slot_n0_s3_alu_set, + 0, + 0, + Field_fld_saimm4_Slot_n0_s3_alu_set, + Field_fld_saimm5_Slot_n0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbr_Slot_n0_s3_alu_set, + 0, + Field_fld_ivp_sem_vbool_alu_ltr_vbt_Slot_n0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ivp_sem_vec_alu_vbt_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_alu_vs_Slot_n0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_fp_sem_hp_cnv_i_imm4_Slot_n0_s3_alu_set, + 0, + Field_fld_fp_sem_hp_cnv_vr_Slot_n0_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vs_Slot_n0_s3_alu_set, + Field_fld_fp_sem_hp_cnv_vt_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_i_imm5_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vbr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_sp32cvt_vt_Slot_n0_s3_alu_set, + 0, + Field_fld_ivp_sem_spmisc_vr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_spmisc_vs_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_spmisc_vsm_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_spmisc_vt_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_alu_i_imm3_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vbt_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_reduce_vt_Slot_n0_s3_alu_set, + 0, + Field_fld_ivp_sem_vec_select_isel_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_select_ishfl_Slot_n0_s3_alu_set, + 0, + 0, + Field_fld_ivp_sem_vec_select_sr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_select_vbr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_select_vr_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_select_vs_Slot_n0_s3_alu_set, + Field_fld_ivp_sem_vec_select_vt_Slot_n0_s3_alu_set, + 0, + Field_fld_ivp_sem_vec_shift_vs_Slot_n0_s3_alu_set, + Field_fld_saimm6_31_Slot_n0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_n0_s3_alu_14_10_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_14_13_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_14_14_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_14_5_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_19_12_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_19_13_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_19_15_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_27_12_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_27_13_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_27_15_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_27_16_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_27_19_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_27_20_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_27_22_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_27_23_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_27_3_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_2_0_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_3_0_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_7_0_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_9_0_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_9_3_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_9_4_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_9_5_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_9_6_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_9_7_Slot_n0_s3_alu_set, + Field_fld_n0_s3_alu_9_9_Slot_n0_s3_alu_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" }, + { "F0_S0_LdSt", "F0", 0, + Slot_f0_Format_f0_s0_ldst_8_get, Slot_f0_Format_f0_s0_ldst_8_set, + Slot_f0_s0_ldst_get_field_fns, Slot_f0_s0_ldst_set_field_fns, + Slot_f0_s0_ldst_decode, "nop" }, + { "F0_S1_Ld", "F0", 1, + Slot_f0_Format_f0_s1_ld_5_get, Slot_f0_Format_f0_s1_ld_5_set, + Slot_f0_s1_ld_get_field_fns, Slot_f0_s1_ld_set_field_fns, + Slot_f0_s1_ld_decode, "nop" }, + { "F0_S2_Mul", "F0", 2, + Slot_f0_Format_f0_s2_mul_4_get, Slot_f0_Format_f0_s2_mul_4_set, + Slot_f0_s2_mul_get_field_fns, Slot_f0_s2_mul_set_field_fns, + Slot_f0_s2_mul_decode, "nop" }, + { "F0_S3_ALU", "F0", 3, + Slot_f0_Format_f0_s3_alu_35_get, Slot_f0_Format_f0_s3_alu_35_set, + Slot_f0_s3_alu_get_field_fns, Slot_f0_s3_alu_set_field_fns, + Slot_f0_s3_alu_decode, "nop" }, + { "F1_S0_LdStALU", "F1", 0, + Slot_f1_Format_f1_s0_ldstalu_8_get, Slot_f1_Format_f1_s0_ldstalu_8_set, + Slot_f1_s0_ldstalu_get_field_fns, Slot_f1_s0_ldstalu_set_field_fns, + Slot_f1_s0_ldstalu_decode, "nop" }, + { "F1_S1_Ld", "F1", 1, + Slot_f1_Format_f1_s1_ld_5_get, Slot_f1_Format_f1_s1_ld_5_set, + Slot_f1_s1_ld_get_field_fns, Slot_f1_s1_ld_set_field_fns, + Slot_f1_s1_ld_decode, "nop" }, + { "F1_S2_Mul", "F1", 2, + Slot_f1_Format_f1_s2_mul_4_get, Slot_f1_Format_f1_s2_mul_4_set, + Slot_f1_s2_mul_get_field_fns, Slot_f1_s2_mul_set_field_fns, + Slot_f1_s2_mul_decode, "nop" }, + { "F1_S3_ALU", "F1", 3, + Slot_f1_Format_f1_s3_alu_26_get, Slot_f1_Format_f1_s3_alu_26_set, + Slot_f1_s3_alu_get_field_fns, Slot_f1_s3_alu_set_field_fns, + Slot_f1_s3_alu_decode, "nop" }, + { "F2_S0_LdSt", "F2", 0, + Slot_f2_Format_f2_s0_ldst_8_get, Slot_f2_Format_f2_s0_ldst_8_set, + Slot_f2_s0_ldst_get_field_fns, Slot_f2_s0_ldst_set_field_fns, + Slot_f2_s0_ldst_decode, "nop" }, + { "F2_S1_Ld", "F2", 1, + Slot_f2_Format_f2_s1_ld_5_get, Slot_f2_Format_f2_s1_ld_5_set, + Slot_f2_s1_ld_get_field_fns, Slot_f2_s1_ld_set_field_fns, + Slot_f2_s1_ld_decode, "nop" }, + { "F2_S2_Mul", "F2", 2, + Slot_f2_Format_f2_s2_mul_4_get, Slot_f2_Format_f2_s2_mul_4_set, + Slot_f2_s2_mul_get_field_fns, Slot_f2_s2_mul_set_field_fns, + Slot_f2_s2_mul_decode, "nop" }, + { "F2_S3_ALU", "F2", 3, + Slot_f2_Format_f2_s3_alu_21_get, Slot_f2_Format_f2_s3_alu_21_set, + Slot_f2_s3_alu_get_field_fns, Slot_f2_s3_alu_set_field_fns, + Slot_f2_s3_alu_decode, "nop" }, + { "F3_S0_LdSt", "F3", 0, + Slot_f3_Format_f3_s0_ldst_8_get, Slot_f3_Format_f3_s0_ldst_8_set, + Slot_f3_s0_ldst_get_field_fns, Slot_f3_s0_ldst_set_field_fns, + Slot_f3_s0_ldst_decode, "nop" }, + { "F3_S1_Ld", "F3", 1, + Slot_f3_Format_f3_s1_ld_5_get, Slot_f3_Format_f3_s1_ld_5_set, + Slot_f3_s1_ld_get_field_fns, Slot_f3_s1_ld_set_field_fns, + Slot_f3_s1_ld_decode, "nop" }, + { "F3_S2_Mul", "F3", 2, + Slot_f3_Format_f3_s2_mul_4_get, Slot_f3_Format_f3_s2_mul_4_set, + Slot_f3_s2_mul_get_field_fns, Slot_f3_s2_mul_set_field_fns, + Slot_f3_s2_mul_decode, "nop" }, + { "F3_S3_ALU", "F3", 3, + Slot_f3_Format_f3_s3_alu_34_get, Slot_f3_Format_f3_s3_alu_34_set, + Slot_f3_s3_alu_get_field_fns, Slot_f3_s3_alu_set_field_fns, + Slot_f3_s3_alu_decode, "nop" }, + { "F3_S4_ALU", "F3", 4, + Slot_f3_Format_f3_s4_alu_70_get, Slot_f3_Format_f3_s4_alu_70_set, + Slot_f3_s4_alu_get_field_fns, Slot_f3_s4_alu_set_field_fns, + Slot_f3_s4_alu_decode, "nop" }, + { "F4_S0_Ld", "F4", 0, + Slot_f4_Format_f4_s0_ld_8_get, Slot_f4_Format_f4_s0_ld_8_set, + Slot_f4_s0_ld_get_field_fns, Slot_f4_s0_ld_set_field_fns, + Slot_f4_s0_ld_decode, "nop" }, + { "F4_S1_Ld", "F4", 1, + Slot_f4_Format_f4_s1_ld_5_get, Slot_f4_Format_f4_s1_ld_5_set, + Slot_f4_s1_ld_get_field_fns, Slot_f4_s1_ld_set_field_fns, + Slot_f4_s1_ld_decode, "nop" }, + { "F4_S2_Mul", "F4", 2, + Slot_f4_Format_f4_s2_mul_4_get, Slot_f4_Format_f4_s2_mul_4_set, + Slot_f4_s2_mul_get_field_fns, Slot_f4_s2_mul_set_field_fns, + Slot_f4_s2_mul_decode, "nop" }, + { "F4_S3_ALU", "F4", 3, + Slot_f4_Format_f4_s3_alu_34_get, Slot_f4_Format_f4_s3_alu_34_set, + Slot_f4_s3_alu_get_field_fns, Slot_f4_s3_alu_set_field_fns, + Slot_f4_s3_alu_decode, "nop" }, + { "F5_S0_Base", "F5", 0, + Slot_f5_Format_f5_s0_base_8_get, Slot_f5_Format_f5_s0_base_8_set, + Slot_f5_s0_base_get_field_fns, Slot_f5_s0_base_set_field_fns, + Slot_f5_s0_base_decode, "nop" }, + { "F5_S1_Base", "F5", 1, + Slot_f5_Format_f5_s1_base_4_get, Slot_f5_Format_f5_s1_base_4_set, + Slot_f5_s1_base_get_field_fns, Slot_f5_s1_base_set_field_fns, + Slot_f5_s1_base_decode, "nop" }, + { "F5_S2_Base", "F5", 2, + Slot_f5_Format_f5_s2_base_5_get, Slot_f5_Format_f5_s2_base_5_set, + Slot_f5_s2_base_get_field_fns, Slot_f5_s2_base_set_field_fns, + Slot_f5_s2_base_decode, "nop" }, + { "F5_S3_Base", "F5", 3, + Slot_f5_Format_f5_s3_base_35_get, Slot_f5_Format_f5_s3_base_35_set, + Slot_f5_s3_base_get_field_fns, Slot_f5_s3_base_set_field_fns, + Slot_f5_s3_base_decode, "nop" }, + { "F11_S0_Ld", "F11", 0, + Slot_f11_Format_f11_s0_ld_8_get, Slot_f11_Format_f11_s0_ld_8_set, + Slot_f11_s0_ld_get_field_fns, Slot_f11_s0_ld_set_field_fns, + Slot_f11_s0_ld_decode, "nop" }, + { "F11_S1_ALU", "F11", 1, + Slot_f11_Format_f11_s1_alu_5_get, Slot_f11_Format_f11_s1_alu_5_set, + Slot_f11_s1_alu_get_field_fns, Slot_f11_s1_alu_set_field_fns, + Slot_f11_s1_alu_decode, "nop" }, + { "F11_S2_Mul", "F11", 2, + Slot_f11_Format_f11_s2_mul_4_get, Slot_f11_Format_f11_s2_mul_4_set, + Slot_f11_s2_mul_get_field_fns, Slot_f11_s2_mul_set_field_fns, + Slot_f11_s2_mul_decode, "nop" }, + { "F11_S3_ALU", "F11", 3, + Slot_f11_Format_f11_s3_alu_35_get, Slot_f11_Format_f11_s3_alu_35_set, + Slot_f11_s3_alu_get_field_fns, Slot_f11_s3_alu_set_field_fns, + Slot_f11_s3_alu_decode, "nop" }, + { "F11_S4_ALU", "F11", 4, + Slot_f11_Format_f11_s4_alu_56_get, Slot_f11_Format_f11_s4_alu_56_set, + Slot_f11_s4_alu_get_field_fns, Slot_f11_s4_alu_set_field_fns, + Slot_f11_s4_alu_decode, "nop" }, + { "N1_S0_LdSt", "N1", 0, + Slot_n1_Format_n1_s0_ldst_8_get, Slot_n1_Format_n1_s0_ldst_8_set, + Slot_n1_s0_ldst_get_field_fns, Slot_n1_s0_ldst_set_field_fns, + Slot_n1_s0_ldst_decode, "nop" }, + { "N1_S1_None", "N1", 1, + Slot_n1_Format_n1_s1_none_50_get, Slot_n1_Format_n1_s1_none_50_set, + Slot_n1_s1_none_get_field_fns, Slot_n1_s1_none_set_field_fns, + Slot_n1_s1_none_decode, "nop" }, + { "N1_S2_Mul", "N1", 2, + Slot_n1_Format_n1_s2_mul_5_get, Slot_n1_Format_n1_s2_mul_5_set, + Slot_n1_s2_mul_get_field_fns, Slot_n1_s2_mul_set_field_fns, + Slot_n1_s2_mul_decode, "nop" }, + { "N2_S0_LdSt", "N2", 0, + Slot_n2_Format_n2_s0_ldst_8_get, Slot_n2_Format_n2_s0_ldst_8_set, + Slot_n2_s0_ldst_get_field_fns, Slot_n2_s0_ldst_set_field_fns, + Slot_n2_s0_ldst_decode, "nop" }, + { "N2_S1_Ld", "N2", 1, + Slot_n2_Format_n2_s1_ld_5_get, Slot_n2_Format_n2_s1_ld_5_set, + Slot_n2_s1_ld_get_field_fns, Slot_n2_s1_ld_set_field_fns, + Slot_n2_s1_ld_decode, "nop" }, + { "N0_S0_LdSt", "N0", 0, + Slot_n0_Format_n0_s0_ldst_8_get, Slot_n0_Format_n0_s0_ldst_8_set, + Slot_n0_s0_ldst_get_field_fns, Slot_n0_s0_ldst_set_field_fns, + Slot_n0_s0_ldst_decode, "nop" }, + { "N0_S1_None", "N0", 1, + Slot_n0_Format_n0_s1_none_49_get, Slot_n0_Format_n0_s1_none_49_set, + Slot_n0_s1_none_get_field_fns, Slot_n0_s1_none_set_field_fns, + Slot_n0_s1_none_decode, "nop" }, + { "N0_S2_None", "N0", 2, + Slot_n0_Format_n0_s2_none_50_get, Slot_n0_Format_n0_s2_none_50_set, + Slot_n0_s2_none_get_field_fns, Slot_n0_s2_none_set_field_fns, + Slot_n0_s2_none_decode, "nop" }, + { "N0_S3_ALU", "N0", 3, + Slot_n0_Format_n0_s3_alu_5_get, Slot_n0_Format_n0_s3_alu_5_set, + Slot_n0_s3_alu_get_field_fns, Slot_n0_s3_alu_set_field_fns, + Slot_n0_s3_alu_decode, "nop" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_F0_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0x2040000; +} + +static void +Format_F1_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0x2040800; +} + +static void +Format_F2_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0x2040820; +} + +static void +Format_F3_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_F4_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0x2000000; +} + +static void +Format_F5_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0x2040840; +} + +static void +Format_F11_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0x2020000; +} + +static void +Format_N1_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xf; + insn[1] = 0x400000; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_N2_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xf; + insn[1] = 0x800000; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_N0_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xf; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static int Format_F0_slots[] = { 5, 4, 3, 6 }; + +static int Format_F1_slots[] = { 9, 8, 7, 10 }; + +static int Format_F2_slots[] = { 13, 12, 11, 14 }; + +static int Format_F3_slots[] = { 17, 16, 15, 18, 19 }; + +static int Format_F4_slots[] = { 22, 21, 20, 23 }; + +static int Format_F5_slots[] = { 25, 26, 24, 27 }; + +static int Format_F11_slots[] = { 30, 29, 28, 31, 32 }; + +static int Format_N1_slots[] = { 35, 33, 34 }; + +static int Format_N2_slots[] = { 37, 36 }; + +static int Format_N0_slots[] = { 41, 38, 39, 40 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, + { "F0", 16, Format_F0_encode, 4, Format_F0_slots }, + { "F1", 16, Format_F1_encode, 4, Format_F1_slots }, + { "F2", 16, Format_F2_encode, 4, Format_F2_slots }, + { "F3", 16, Format_F3_encode, 5, Format_F3_slots }, + { "F4", 16, Format_F4_encode, 4, Format_F4_slots }, + { "F5", 16, Format_F5_encode, 4, Format_F5_slots }, + { "F11", 16, Format_F11_encode, 5, Format_F11_slots }, + { "N1", 8, Format_N1_encode, 3, Format_N1_slots }, + { "N2", 8, Format_N2_encode, 2, Format_N2_slots }, + { "N0", 8, Format_N0_encode, 4, Format_N0_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 1; /* x16a */ + if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 2; /* x16b */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0x2060800) == 0x2040000) + return 3; /* F0 */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0x2060860) == 0x2040800) + return 4; /* F1 */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0x2060860) == 0x2040820) + return 5; /* F2 */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0x2000000) == 0) + return 6; /* F3 */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0x2060000) == 0x2000000) + return 7; /* F4 */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0x2060860) == 0x2040840) + return 8; /* F5 */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0x2060000) == 0x2020000) + return 9; /* F11 */ + if ((insn[0] & 0x1f) == 0xf && (insn[1] & 0xc00000) == 0x400000 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 10; /* N1 */ + if ((insn[0] & 0x1f) == 0xf && (insn[1] & 0xc00000) == 0x800000 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 11; /* N2 */ + if ((insn[0] & 0x1f) == 0xf && (insn[1] & 0xc00000) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 12; /* N0 */ + return -1; +} + +static int length_table[256] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 16, + -1 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int l = insn[0]; + return length_table[l]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, + 16 /* insn_size */, 0, + 13, formats, format_decoder, length_decoder, + 42, slots, + 955 /* num_fields */, + 1145, operands, + 930, iclasses, + 1015, opcodes, 0, + 11, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 13, interfaces, 0, + 0, funcUnits, 0 +}; diff --git a/overlays/xtensa_mtk_mvpu6_0226/gdb/gdb/regformats/reg-xtensa.dat b/overlays/xtensa_mtk_mvpu6_0226/gdb/gdb/regformats/reg-xtensa.dat new file mode 100644 index 00000000..d37762e1 --- /dev/null +++ b/overlays/xtensa_mtk_mvpu6_0226/gdb/gdb/regformats/reg-xtensa.dat @@ -0,0 +1,99 @@ +name:xtensa +expedite:pc,windowbase,windowstart +32:pc +32:ar0 +32:ar1 +32:ar2 +32:ar3 +32:ar4 +32:ar5 +32:ar6 +32:ar7 +32:ar8 +32:ar9 +32:ar10 +32:ar11 +32:ar12 +32:ar13 +32:ar14 +32:ar15 +32:ar16 +32:ar17 +32:ar18 +32:ar19 +32:ar20 +32:ar21 +32:ar22 +32:ar23 +32:ar24 +32:ar25 +32:ar26 +32:ar27 +32:ar28 +32:ar29 +32:ar30 +32:ar31 +32:lbeg +32:lend +32:lcount +32:sar +32:windowbase +32:windowstart +32:configid0 +32:configid1 +32:ps +32:threadptr +32:br +32:apb_pipe +512:v0 +512:v1 +512:v2 +512:v3 +512:v4 +512:v5 +512:v6 +512:v7 +512:v8 +512:v9 +512:v10 +512:v11 +512:v12 +512:v13 +512:v14 +512:v15 +512:v16 +512:v17 +512:v18 +512:v19 +512:v20 +512:v21 +512:v22 +512:v23 +512:v24 +512:v25 +512:v26 +512:v27 +512:v28 +512:v29 +512:v30 +512:v31 +64:vb0 +64:vb1 +64:vb2 +64:vb3 +64:vb4 +64:vb5 +64:vb6 +64:vb7 +512:u0 +512:u1 +512:u2 +512:u3 +2048:wv0 +2048:wv1 +2048:wv2 +2048:wv3 +512:gr0 +512:gr1 +512:gr2 +512:gr3 diff --git a/overlays/xtensa_mtk_mvpu6_0226/gdb/gdb/xtensa-config.c b/overlays/xtensa_mtk_mvpu6_0226/gdb/gdb/xtensa-config.c new file mode 100644 index 00000000..1d7085d2 --- /dev/null +++ b/overlays/xtensa_mtk_mvpu6_0226/gdb/gdb/xtensa-config.c @@ -0,0 +1,471 @@ +/* Configuration for the Xtensa architecture for GDB, the GNU debugger. + + Copyright (c) 2003-2018 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#define XTENSA_CONFIG_VERSION 0x60 + +#include "xtensa-config.h" +#include "xtensa-tdep.h" + + + +/* Masked registers. */ +xtensa_reg_mask_t xtensa_submask0[] = { { 43, 0, 1 } }; +const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 }; +xtensa_reg_mask_t xtensa_submask1[] = { { 43, 1, 1 } }; +const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 }; +xtensa_reg_mask_t xtensa_submask2[] = { { 43, 2, 1 } }; +const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 }; +xtensa_reg_mask_t xtensa_submask3[] = { { 43, 3, 1 } }; +const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 }; +xtensa_reg_mask_t xtensa_submask4[] = { { 43, 4, 1 } }; +const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 }; +xtensa_reg_mask_t xtensa_submask5[] = { { 43, 5, 1 } }; +const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 }; +xtensa_reg_mask_t xtensa_submask6[] = { { 43, 6, 1 } }; +const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 }; +xtensa_reg_mask_t xtensa_submask7[] = { { 43, 7, 1 } }; +const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 }; +xtensa_reg_mask_t xtensa_submask8[] = { { 43, 8, 1 } }; +const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 }; +xtensa_reg_mask_t xtensa_submask9[] = { { 43, 9, 1 } }; +const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 }; +xtensa_reg_mask_t xtensa_submask10[] = { { 43, 10, 1 } }; +const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 }; +xtensa_reg_mask_t xtensa_submask11[] = { { 43, 11, 1 } }; +const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 }; +xtensa_reg_mask_t xtensa_submask12[] = { { 43, 12, 1 } }; +const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 }; +xtensa_reg_mask_t xtensa_submask13[] = { { 43, 13, 1 } }; +const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 }; +xtensa_reg_mask_t xtensa_submask14[] = { { 43, 14, 1 } }; +const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 }; +xtensa_reg_mask_t xtensa_submask15[] = { { 43, 15, 1 } }; +const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 }; +xtensa_reg_mask_t xtensa_submask16[] = { { 41, 0, 4 } }; +const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 }; +xtensa_reg_mask_t xtensa_submask17[] = { { 41, 5, 1 } }; +const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 }; +xtensa_reg_mask_t xtensa_submask18[] = { { 41, 18, 1 } }; +const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 }; +xtensa_reg_mask_t xtensa_submask19[] = { { 41, 6, 2 } }; +const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 }; +xtensa_reg_mask_t xtensa_submask20[] = { { 41, 4, 1 } }; +const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 }; +xtensa_reg_mask_t xtensa_submask21[] = { { 41, 16, 2 } }; +const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 }; +xtensa_reg_mask_t xtensa_submask22[] = { { 41, 8, 4 } }; +const xtensa_mask_t xtensa_mask22 = { 1, xtensa_submask22 }; +xtensa_reg_mask_t xtensa_submask23[] = { { 107, 28, 2 } }; +const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 }; +xtensa_reg_mask_t xtensa_submask24[] = { { 127, 8, 4 } }; +const xtensa_mask_t xtensa_mask24 = { 1, xtensa_submask24 }; + + +/* Register map. */ +xtensa_register_t rmap[] = +{ + /* idx ofs bi sz al targno flags cp typ group name */ + XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0) + XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) + XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) + XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) + XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) + XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) + XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) + XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) + XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) + XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) + XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) + XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) + XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) + XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) + XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) + XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) + XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) + XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) + XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) + XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) + XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) + XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) + XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) + XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) + XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) + XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) + XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) + XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) + XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) + XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) + XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) + XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) + XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) + XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0) + XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0) + XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0) + XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) + XTREG( 37,148, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) + XTREG( 38,152, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) + XTREG( 39,156,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) + XTREG( 40,160,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) + XTREG( 41,164,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) + XTREG( 42,168,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0) + XTREG( 43,172,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0) + XTREG( 44,176, 1, 4, 4,0x0300,0x0006,-1, 3,0x0210,apb_pipe, 0,0,0,0,0,0) + XTREG( 45,180,512,64,64,0x1000,0x0006, 1, 4,0x0101,v0, + "10:9e:04:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 46,244,512,64,64,0x1001,0x0006, 1, 4,0x0101,v1, + "10:9e:04:02:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:02:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 47,308,512,64,64,0x1002,0x0006, 1, 4,0x0101,v2, + "10:9e:04:04:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:04:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 48,372,512,64,64,0x1003,0x0006, 1, 4,0x0101,v3, + "10:9e:04:06:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:06:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 49,436,512,64,64,0x1004,0x0006, 1, 4,0x0101,v4, + "10:9e:04:08:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:08:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 50,500,512,64,64,0x1005,0x0006, 1, 4,0x0101,v5, + "10:9e:04:0a:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:0a:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 51,564,512,64,64,0x1006,0x0006, 1, 4,0x0101,v6, + "10:9e:04:0c:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:0c:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 52,628,512,64,64,0x1007,0x0006, 1, 4,0x0101,v7, + "10:9e:04:0e:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:0e:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 53,692,512,64,64,0x1008,0x0006, 1, 4,0x0101,v8, + "10:9e:04:10:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:10:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 54,756,512,64,64,0x1009,0x0006, 1, 4,0x0101,v9, + "10:9e:04:12:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:12:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 55,820,512,64,64,0x100a,0x0006, 1, 4,0x0101,v10, + "10:9e:04:14:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:14:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 56,884,512,64,64,0x100b,0x0006, 1, 4,0x0101,v11, + "10:9e:04:16:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:16:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 57,948,512,64,64,0x100c,0x0006, 1, 4,0x0101,v12, + "10:9e:04:18:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:18:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 58,1012,512,64,64,0x100d,0x0006, 1, 4,0x0101,v13, + "10:9e:04:1a:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:1a:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 59,1076,512,64,64,0x100e,0x0006, 1, 4,0x0101,v14, + "10:9e:04:1c:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:1c:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 60,1140,512,64,64,0x100f,0x0006, 1, 4,0x0101,v15, + "10:9e:04:1e:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:1e:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 61,1204,512,64,64,0x1010,0x0006, 1, 4,0x0101,v16, + "10:9e:04:20:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:20:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 62,1268,512,64,64,0x1011,0x0006, 1, 4,0x0101,v17, + "10:9e:04:22:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:22:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 63,1332,512,64,64,0x1012,0x0006, 1, 4,0x0101,v18, + "10:9e:04:24:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:24:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 64,1396,512,64,64,0x1013,0x0006, 1, 4,0x0101,v19, + "10:9e:04:26:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:26:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 65,1460,512,64,64,0x1014,0x0006, 1, 4,0x0101,v20, + "10:9e:04:28:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:28:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 66,1524,512,64,64,0x1015,0x0006, 1, 4,0x0101,v21, + "10:9e:04:2a:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:2a:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 67,1588,512,64,64,0x1016,0x0006, 1, 4,0x0101,v22, + "10:9e:04:2c:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:2c:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 68,1652,512,64,64,0x1017,0x0006, 1, 4,0x0101,v23, + "10:9e:04:2e:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:2e:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 69,1716,512,64,64,0x1018,0x0006, 1, 4,0x0101,v24, + "10:9e:04:30:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:30:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 70,1780,512,64,64,0x1019,0x0006, 1, 4,0x0101,v25, + "10:9e:04:32:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:32:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 71,1844,512,64,64,0x101a,0x0006, 1, 4,0x0101,v26, + "10:9e:04:34:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:34:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 72,1908,512,64,64,0x101b,0x0006, 1, 4,0x0101,v27, + "10:9e:04:36:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:36:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 73,1972,512,64,64,0x101c,0x0006, 1, 4,0x0101,v28, + "10:9e:04:38:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:38:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 74,2036,512,64,64,0x101d,0x0006, 1, 4,0x0101,v29, + "10:9e:04:3a:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:3a:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 75,2100,512,64,64,0x101e,0x0006, 1, 4,0x0101,v30, + "10:9e:04:3c:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:3c:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 76,2164,512,64,64,0x101f,0x0006, 1, 4,0x0101,v31, + "10:9e:04:3e:70:58:60:12:00:30:d0:05:25:f8:06:04:02","10:9e:04:3e:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 77,2228,64, 8, 8,0x1020,0x0006, 1, 4,0x0101,vb0, + "10:9e:04:00:70:58:60:12:00:30:d0:05:51:f8:06:04:02","10:9e:f5:04:0c:5a:60:10:00:30:d0:05:51:d8:06:04:02",0,0,0,0) + XTREG( 78,2236,64, 8, 8,0x1021,0x0006, 1, 4,0x0101,vb1, + "10:9e:04:00:70:5a:60:12:00:30:d0:05:51:f8:06:04:02","10:9e:f5:04:0c:5e:60:10:00:30:d0:05:51:d8:06:04:02",0,0,0,0) + XTREG( 79,2244,64, 8, 8,0x1022,0x0006, 1, 4,0x0101,vb2, + "10:9e:04:00:70:58:62:12:00:30:d0:05:51:f8:06:04:02","10:9e:f5:04:0c:5a:60:12:00:30:d0:05:51:d8:06:04:02",0,0,0,0) + XTREG( 80,2252,64, 8, 8,0x1023,0x0006, 1, 4,0x0101,vb3, + "10:9e:04:00:70:5a:62:12:00:30:d0:05:51:f8:06:04:02","10:9e:f5:04:0c:5e:60:12:00:30:d0:05:51:d8:06:04:02",0,0,0,0) + XTREG( 81,2260,64, 8, 8,0x1024,0x0006, 1, 4,0x0101,vb4, + "10:9e:04:00:70:58:64:12:00:30:d0:05:51:f8:06:04:02","10:9e:f5:04:0c:5a:60:10:04:30:d0:05:51:d8:06:04:02",0,0,0,0) + XTREG( 82,2268,64, 8, 8,0x1025,0x0006, 1, 4,0x0101,vb5, + "10:9e:04:00:70:5a:64:12:00:30:d0:05:51:f8:06:04:02","10:9e:f5:04:0c:5e:60:10:04:30:d0:05:51:d8:06:04:02",0,0,0,0) + XTREG( 83,2276,64, 8, 8,0x1026,0x0006, 1, 4,0x0101,vb6, + "10:9e:04:00:70:58:66:12:00:30:d0:05:51:f8:06:04:02","10:9e:f5:04:0c:5a:60:12:04:30:d0:05:51:d8:06:04:02",0,0,0,0) + XTREG( 84,2284,64, 8, 8,0x1027,0x0006, 1, 4,0x0101,vb7, + "10:9e:04:00:70:5a:66:12:00:30:d0:05:51:f8:06:04:02","10:9e:f5:04:0c:5e:60:12:04:30:d0:05:51:d8:06:04:02",0,0,0,0) + XTREG( 85,2292,512,64,64,0x1028,0x0006, 1, 4,0x0101,u0, + "10:9e:04:02:70:58:60:12:00:30:d0:05:52:f8:06:04:02","10:9e:04:00:70:58:60:12:00:30:d0:05:52:f8:06:04:02",0,0,0,0) + XTREG( 86,2356,512,64,64,0x1029,0x0006, 1, 4,0x0101,u1, + "10:9e:04:02:70:5a:60:12:00:30:d0:05:52:f8:06:04:02","10:9e:04:00:70:5a:60:12:00:30:d0:05:52:f8:06:04:02",0,0,0,0) + XTREG( 87,2420,512,64,64,0x102a,0x0006, 1, 4,0x0101,u2, + "10:9e:04:02:70:58:62:12:00:30:d0:05:52:f8:06:04:02","10:9e:04:00:70:58:62:12:00:30:d0:05:52:f8:06:04:02",0,0,0,0) + XTREG( 88,2484,512,64,64,0x102b,0x0006, 1, 4,0x0101,u3, + "10:9e:04:02:70:5a:62:12:00:30:d0:05:52:f8:06:04:02","10:9e:04:00:70:5a:62:12:00:30:d0:05:52:f8:06:04:02",0,0,0,0) + XTREG( 89,2548,1536,256,64,0x102c,0x0006, 1, 4,0x0101,wv0, + "10:9e:44:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:54:02:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:64:04:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:74:06:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:1e:f5:c4:05:5a:60:12:04:30:d0:05:51:f8:06:04:02:10:9e:f5:85:15:5a:60:12:04:30:d0:05:51:f8:06:04:02:10:1e:f5:85:25:5a:60:12:04:30:d0:05:51:f8:06:04:02:10:9e:f5:84:35:5a:60:12:04:30:d0:05:51:f8:06:04:02:10:9e:04:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:14:02:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:24:04:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:34:06:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:44:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:54:02:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:64:04:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:74:06:70:58:60:12:00:30:d0:05:1f:f8:06:04:02","10:9e:44:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:54:02:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:64:04:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:74:06:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:04:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:14:02:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:24:04:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:34:06:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:8e:f5:04:70:5b:00:82:00:30:d0:05:51:f8:06:04:02:10:9e:f5:04:70:5a:00:8a:01:30:d0:05:51:f8:06:04:02:10:9e:44:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:54:02:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:64:04:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:74:06:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 90,2804,1536,256,64,0x102d,0x0006, 1, 4,0x0101,wv1, + "10:9e:44:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:54:02:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:64:04:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:74:06:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:3e:f5:c4:05:5a:60:12:04:30:d0:05:51:f8:06:04:02:10:be:f5:85:15:5a:60:12:04:30:d0:05:51:f8:06:04:02:10:3e:f5:85:25:5a:60:12:04:30:d0:05:51:f8:06:04:02:10:be:f5:84:35:5a:60:12:04:30:d0:05:51:f8:06:04:02:10:9e:04:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:14:02:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:24:04:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:34:06:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:44:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:54:02:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:64:04:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:74:06:70:58:60:12:00:30:d0:05:1f:f8:06:04:02","10:9e:44:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:54:02:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:64:04:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:74:06:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:04:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:14:02:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:24:04:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:34:06:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:8e:f5:04:70:5b:80:82:00:30:d0:05:51:f8:06:04:02:10:9e:f5:04:70:5a:80:8a:01:30:d0:05:51:f8:06:04:02:10:9e:44:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:54:02:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:64:04:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:74:06:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 91,3060,1536,256,64,0x102e,0x0006, 1, 4,0x0101,wv2, + "10:9e:44:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:54:02:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:64:04:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:74:06:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:5e:f5:c4:05:5a:60:12:04:30:d0:05:51:f8:06:04:02:10:de:f5:85:15:5a:60:12:04:30:d0:05:51:f8:06:04:02:10:5e:f5:85:25:5a:60:12:04:30:d0:05:51:f8:06:04:02:10:de:f5:84:35:5a:60:12:04:30:d0:05:51:f8:06:04:02:10:9e:04:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:14:02:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:24:04:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:34:06:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:44:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:54:02:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:64:04:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:74:06:70:58:60:12:00:30:d0:05:1f:f8:06:04:02","10:9e:44:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:54:02:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:64:04:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:74:06:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:04:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:14:02:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:24:04:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:34:06:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:8e:f5:04:70:5b:00:83:00:30:d0:05:51:f8:06:04:02:10:9e:f5:04:70:5a:00:8b:01:30:d0:05:51:f8:06:04:02:10:9e:44:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:54:02:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:64:04:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:74:06:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 92,3316,1536,256,64,0x102f,0x0006, 1, 4,0x0101,wv3, + "10:9e:44:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:54:02:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:64:04:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:74:06:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:7e:f5:c4:05:5a:60:12:04:30:d0:05:51:f8:06:04:02:10:fe:f5:85:15:5a:60:12:04:30:d0:05:51:f8:06:04:02:10:7e:f5:85:25:5a:60:12:04:30:d0:05:51:f8:06:04:02:10:fe:f5:84:35:5a:60:12:04:30:d0:05:51:f8:06:04:02:10:9e:04:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:14:02:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:24:04:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:34:06:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:44:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:54:02:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:64:04:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:74:06:70:58:60:12:00:30:d0:05:1f:f8:06:04:02","10:9e:44:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:54:02:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:64:04:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:74:06:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:04:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:14:02:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:24:04:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:34:06:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:8e:f5:04:70:5b:80:83:00:30:d0:05:51:f8:06:04:02:10:9e:f5:04:70:5a:80:8b:01:30:d0:05:51:f8:06:04:02:10:9e:44:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:54:02:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:64:04:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:74:06:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 93,3572,512,64,64,0x1030,0x0006, 1, 4,0x0101,gr0, + "10:9e:14:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:f5:45:0f:5e:60:10:00:30:d0:05:51:d8:06:04:02:10:9e:04:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:14:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02","10:9e:14:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:04:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:50:00:70:5a:62:12:00:30:d0:85:51:f8:06:04:02:10:9e:14:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 94,3636,512,64,64,0x1031,0x0006, 1, 4,0x0101,gr1, + "10:9e:14:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:be:f5:45:0f:5e:60:10:00:30:d0:05:51:d8:06:04:02:10:9e:04:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:14:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02","10:9e:14:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:04:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:50:04:70:5a:62:12:00:30:d0:85:51:f8:06:04:02:10:9e:14:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 95,3700,512,64,64,0x1032,0x0006, 1, 4,0x0101,gr2, + "10:9e:14:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:de:f5:45:0f:5e:60:10:00:30:d0:05:51:d8:06:04:02:10:9e:04:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:14:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02","10:9e:14:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:04:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:50:08:70:5a:62:12:00:30:d0:85:51:f8:06:04:02:10:9e:14:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 96,3764,512,64,64,0x1033,0x0006, 1, 4,0x0101,gr3, + "10:9e:14:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:fe:f5:45:0f:5e:60:10:00:30:d0:05:51:d8:06:04:02:10:9e:04:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:14:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02","10:9e:14:00:70:58:60:12:00:30:d0:05:25:f8:06:04:02:10:9e:04:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02:10:9e:50:0c:70:5a:62:12:00:30:d0:85:51:f8:06:04:02:10:9e:14:00:70:58:60:12:00:30:d0:05:1f:f8:06:04:02",0,0,0,0) + XTREG( 97,3828,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0) + XTREG( 98,3832,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,mpuenb, 0,0,0,0,0,0) + XTREG( 99,3836, 1, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) + XTREG(100,3840,24, 4, 4,0x0261,0x0007,-2, 2,0x1000,memctl, 0,0,0,0,0,0) + XTREG(101,3844, 8, 4, 4,0x0262,0x0007,-2, 2,0x1000,cacheadrdis, 0,0,0,0,0,0) + XTREG(102,3848, 9, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) + XTREG(103,3852,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) + XTREG(104,3856,32, 4, 4,0x0274,0x0007,-2, 2,0x1000,gserr, 0,0,0,0,0,0) + XTREG(105,3860,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) + XTREG(106,3864,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) + XTREG(107,3868,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) + XTREG(108,3872,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) + XTREG(109,3876,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) + XTREG(110,3880,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) + XTREG(111,3884,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) + XTREG(112,3888,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) + XTREG(113,3892,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) + XTREG(114,3896,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) + XTREG(115,3900,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) + XTREG(116,3904,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) + XTREG(117,3908,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) + XTREG(118,3912,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) + XTREG(119,3916,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) + XTREG(120,3920, 3, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0) + XTREG(121,3924,25, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) + XTREG(122,3928,25, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) + XTREG(123,3932,25, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) + XTREG(124,3936,25, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) + XTREG(125,3940,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) + XTREG(126,3944, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) + XTREG(127,3948,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) + XTREG(128,3952,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) + XTREG(129,3956,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) + XTREG(130,3960,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) + XTREG(131,3964, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) + XTREG(132,3968,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) + XTREG(133,3972,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) + XTREG(134,3976,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) + XTREG(135,3980,32, 4, 4,0x2014,0x000f,-2, 4,0x0101,pwrctl, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(136,3984,32, 4, 4,0x2015,0x000f,-2, 4,0x0101,pwrstat, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(137,3988, 1, 4, 4,0x2016,0x000f,-2, 4,0x0101,eristat, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(138,3992,32, 4, 4,0x2017,0x000f,-2, 4,0x0101,cs_itctrl, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(139,3996,16, 4, 4,0x2018,0x000f,-2, 4,0x0101,cs_claimset, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(140,4000,16, 4, 4,0x2019,0x000f,-2, 4,0x0101,cs_claimclr, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(141,4004,32, 4, 4,0x201a,0x000d,-2, 4,0x0101,cs_lockaccess, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(142,4008,32, 4, 4,0x201b,0x000b,-2, 4,0x0101,cs_lockstatus, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(143,4012, 1, 4, 4,0x201c,0x000b,-2, 4,0x0101,cs_authstatus, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(144,4016,32, 4, 4,0x202b,0x000f,-2, 4,0x0101,fault_info, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:30:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:30:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(145,4020,32, 4, 4,0x202c,0x0003,-2, 4,0x0101,trax_id, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(146,4024,32, 4, 4,0x202d,0x000f,-2, 4,0x0101,trax_control, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(147,4028,32, 4, 4,0x202e,0x000b,-2, 4,0x0101,trax_status, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(148,4032,32, 4, 4,0x202f,0x000f,-2, 4,0x0101,trax_data, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(149,4036,32, 4, 4,0x2030,0x000f,-2, 4,0x0101,trax_address, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(150,4040,32, 4, 4,0x2031,0x000f,-2, 4,0x0101,trax_pctrigger, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(151,4044,32, 4, 4,0x2032,0x000f,-2, 4,0x0101,trax_pcmatch, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(152,4048,32, 4, 4,0x2033,0x000f,-2, 4,0x0101,trax_delay, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(153,4052,32, 4, 4,0x2034,0x000f,-2, 4,0x0101,trax_memstart, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(154,4056,32, 4, 4,0x2035,0x000f,-2, 4,0x0101,trax_memend, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(155,4060,32, 4, 4,0x2043,0x000f,-2, 4,0x0101,pmg, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(156,4064,32, 4, 4,0x2044,0x000f,-2, 4,0x0101,pmpc, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(157,4068,32, 4, 4,0x2045,0x000f,-2, 4,0x0101,pm0, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(158,4072,32, 4, 4,0x2046,0x000f,-2, 4,0x0101,pm1, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(159,4076,32, 4, 4,0x2047,0x000f,-2, 4,0x0101,pm2, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(160,4080,32, 4, 4,0x2048,0x000f,-2, 4,0x0101,pm3, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(161,4084,32, 4, 4,0x2049,0x000f,-2, 4,0x0101,pm4, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(162,4088,32, 4, 4,0x204a,0x000f,-2, 4,0x0101,pm5, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(163,4092,32, 4, 4,0x204b,0x000f,-2, 4,0x0101,pm6, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(164,4096,32, 4, 4,0x204c,0x000f,-2, 4,0x0101,pm7, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(165,4100,32, 4, 4,0x204d,0x000f,-2, 4,0x0101,pmctrl0, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(166,4104,32, 4, 4,0x204e,0x000f,-2, 4,0x0101,pmctrl1, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(167,4108,32, 4, 4,0x204f,0x000f,-2, 4,0x0101,pmctrl2, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(168,4112,32, 4, 4,0x2050,0x000f,-2, 4,0x0101,pmctrl3, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(169,4116,32, 4, 4,0x2051,0x000f,-2, 4,0x0101,pmctrl4, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(170,4120,32, 4, 4,0x2052,0x000f,-2, 4,0x0101,pmctrl5, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(171,4124,32, 4, 4,0x2053,0x000f,-2, 4,0x0101,pmctrl6, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(172,4128,32, 4, 4,0x2054,0x000f,-2, 4,0x0101,pmctrl7, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(173,4132,32, 4, 4,0x2055,0x000f,-2, 4,0x0101,pmstat0, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(174,4136,32, 4, 4,0x2056,0x000f,-2, 4,0x0101,pmstat1, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(175,4140,32, 4, 4,0x2057,0x000f,-2, 4,0x0101,pmstat2, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(176,4144,32, 4, 4,0x2058,0x000f,-2, 4,0x0101,pmstat3, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(177,4148,32, 4, 4,0x2059,0x000f,-2, 4,0x0101,pmstat4, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(178,4152,32, 4, 4,0x205a,0x000f,-2, 4,0x0101,pmstat5, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(179,4156,32, 4, 4,0x205b,0x000f,-2, 4,0x0101,pmstat6, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(180,4160,32, 4, 4,0x205c,0x000f,-2, 4,0x0101,pmstat7, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(181,4164,32, 4, 4,0x205d,0x0003,-2, 4,0x0101,ocdid, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(182,4168,32, 4, 4,0x205e,0x000f,-2, 4,0x0101,ocd_dcrclr, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(183,4172,32, 4, 4,0x205f,0x000f,-2, 4,0x0101,ocd_dcrset, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(184,4176,32, 4, 4,0x2060,0x000f,-2, 4,0x0101,ocd_dsr, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(185,4180,32, 4, 4,0x2068,0x000f,-2, 4,0x0101,idma_settings, + "03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(186,4184,32, 4, 4,0x2069,0x000f,-2, 4,0x0101,idma_timeout, + "03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(187,4188,32, 4, 4,0x206a,0x000f,-2, 4,0x0101,idma_desc_start, + "03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(188,4192, 8, 4, 4,0x206b,0x000b,-2, 4,0x0101,idma_desc_num, + "03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(189,4196, 8, 4, 4,0x206c,0x000d,-2, 4,0x0101,idma_desc_inc, + "03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(190,4200, 2, 4, 4,0x206d,0x000f,-2, 4,0x0101,idma_control, + "03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:14:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:14:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(191,4204, 1, 4, 4,0x206e,0x000f,-2, 4,0x0101,idma_userpriv, + "03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:18:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:18:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(192,4208,32, 4, 4,0x206f,0x000b,-2, 4,0x0101,idma_status, + "03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:40:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:40:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(193,4212,32, 4, 4,0x2070,0x000b,-2, 4,0x0101,idma_desc_curaddr, + "03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:44:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:44:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(194,4216, 3, 4, 4,0x2071,0x000b,-2, 4,0x0101,idma_desc_curtype, + "03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:48:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:48:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(195,4220,32, 4, 4,0x2072,0x000b,-2, 4,0x0101,idma_src, + "03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:4c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:4c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(196,4224,32, 4, 4,0x2073,0x000b,-2, 4,0x0101,idma_dst, + "03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:50:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:40:03:60:55:11:03:52:c5:50:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(197,4228,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0) + XTREG(198,4232,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0) + XTREG(199,4236,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0) + XTREG(200,4240,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0) + XTREG(201,4244,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0) + XTREG(202,4248,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0) + XTREG(203,4252,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0) + XTREG(204,4256,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0) + XTREG(205,4260,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0) + XTREG(206,4264,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0) + XTREG(207,4268,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0) + XTREG(208,4272,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0) + XTREG(209,4276,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0) + XTREG(210,4280,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0) + XTREG(211,4284,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0) + XTREG(212,4288,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0) + XTREG(213,4292, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0, + 0,0,&xtensa_mask0,0,0,0) + XTREG(214,4293, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1, + 0,0,&xtensa_mask1,0,0,0) + XTREG(215,4294, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2, + 0,0,&xtensa_mask2,0,0,0) + XTREG(216,4295, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3, + 0,0,&xtensa_mask3,0,0,0) + XTREG(217,4296, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4, + 0,0,&xtensa_mask4,0,0,0) + XTREG(218,4297, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5, + 0,0,&xtensa_mask5,0,0,0) + XTREG(219,4298, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6, + 0,0,&xtensa_mask6,0,0,0) + XTREG(220,4299, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7, + 0,0,&xtensa_mask7,0,0,0) + XTREG(221,4300, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8, + 0,0,&xtensa_mask8,0,0,0) + XTREG(222,4301, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9, + 0,0,&xtensa_mask9,0,0,0) + XTREG(223,4302, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10, + 0,0,&xtensa_mask10,0,0,0) + XTREG(224,4303, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11, + 0,0,&xtensa_mask11,0,0,0) + XTREG(225,4304, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12, + 0,0,&xtensa_mask12,0,0,0) + XTREG(226,4305, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13, + 0,0,&xtensa_mask13,0,0,0) + XTREG(227,4306, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14, + 0,0,&xtensa_mask14,0,0,0) + XTREG(228,4307, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15, + 0,0,&xtensa_mask15,0,0,0) + XTREG(229,4308, 4, 4, 4,0x2005,0x0006,-2, 6,0x1010,psintlevel, + 0,0,&xtensa_mask16,0,0,0) + XTREG(230,4312, 1, 4, 4,0x2006,0x0006,-2, 6,0x1010,psum, + 0,0,&xtensa_mask17,0,0,0) + XTREG(231,4316, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,pswoe, + 0,0,&xtensa_mask18,0,0,0) + XTREG(232,4320, 2, 4, 4,0x2008,0x0006,-2, 6,0x1010,psring, + 0,0,&xtensa_mask19,0,0,0) + XTREG(233,4324, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psexcm, + 0,0,&xtensa_mask20,0,0,0) + XTREG(234,4328, 2, 4, 4,0x200a,0x0006,-2, 6,0x1010,pscallinc, + 0,0,&xtensa_mask21,0,0,0) + XTREG(235,4332, 4, 4, 4,0x200b,0x0006,-2, 6,0x1010,psowb, + 0,0,&xtensa_mask22,0,0,0) + XTREG(236,4336, 2, 4, 4,0x200f,0x0006,-2, 6,0x1010,dbreakc_sg0, + 0,0,&xtensa_mask23,0,0,0) + XTREG_END +}; + + + +#ifdef XTENSA_CONFIG_INSTANTIATE +XTENSA_CONFIG_INSTANTIATE(rmap,512) +#endif + diff --git a/overlays/xtensa_mtk_mvpu6_0226/gdb/gdb/xtensa-config.h b/overlays/xtensa_mtk_mvpu6_0226/gdb/gdb/xtensa-config.h new file mode 100644 index 00000000..0bfb2b65 --- /dev/null +++ b/overlays/xtensa_mtk_mvpu6_0226/gdb/gdb/xtensa-config.h @@ -0,0 +1,189 @@ +/* Xtensa configuration settings. + Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 + Free Software Foundation, Inc. + Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +/* The macros defined here match those with the same names in the Xtensa + compile-time HAL (Hardware Abstraction Layer). Please refer to the + Xtensa System Software Reference Manual for documentation of these + macros. */ + +#undef XCHAL_HAVE_BE +#define XCHAL_HAVE_BE 0 + +#undef XCHAL_HAVE_DENSITY +#define XCHAL_HAVE_DENSITY 1 + +#undef XCHAL_HAVE_CONST16 +#define XCHAL_HAVE_CONST16 1 + +#undef XCHAL_HAVE_ABS +#define XCHAL_HAVE_ABS 1 + +#undef XCHAL_HAVE_ADDX +#define XCHAL_HAVE_ADDX 1 + +#undef XCHAL_HAVE_L32R +#define XCHAL_HAVE_L32R 1 + +#undef XSHAL_USE_ABSOLUTE_LITERALS +#define XSHAL_USE_ABSOLUTE_LITERALS 0 + +#undef XSHAL_HAVE_TEXT_SECTION_LITERALS +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#undef XCHAL_HAVE_MAC16 +#define XCHAL_HAVE_MAC16 0 + +#undef XCHAL_HAVE_MUL16 +#define XCHAL_HAVE_MUL16 1 + +#undef XCHAL_HAVE_MUL32 +#define XCHAL_HAVE_MUL32 1 + +#undef XCHAL_HAVE_MUL32_HIGH +#define XCHAL_HAVE_MUL32_HIGH 1 + +#undef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 1 + +#undef XCHAL_HAVE_NSA +#define XCHAL_HAVE_NSA 1 + +#undef XCHAL_HAVE_MINMAX +#define XCHAL_HAVE_MINMAX 1 + +#undef XCHAL_HAVE_SEXT +#define XCHAL_HAVE_SEXT 1 + +#undef XCHAL_HAVE_LOOPS +#define XCHAL_HAVE_LOOPS 1 + +#undef XCHAL_HAVE_THREADPTR +#define XCHAL_HAVE_THREADPTR 1 + +#undef XCHAL_HAVE_RELEASE_SYNC +#define XCHAL_HAVE_RELEASE_SYNC 1 + +#undef XCHAL_HAVE_S32C1I +#define XCHAL_HAVE_S32C1I 0 + +#undef XCHAL_HAVE_BOOLEANS +#define XCHAL_HAVE_BOOLEANS 1 + +#undef XCHAL_HAVE_FP +#define XCHAL_HAVE_FP 0 + +#undef XCHAL_HAVE_FP_DIV +#define XCHAL_HAVE_FP_DIV 0 + +#undef XCHAL_HAVE_FP_RECIP +#define XCHAL_HAVE_FP_RECIP 0 + +#undef XCHAL_HAVE_FP_SQRT +#define XCHAL_HAVE_FP_SQRT 0 + +#undef XCHAL_HAVE_FP_RSQRT +#define XCHAL_HAVE_FP_RSQRT 0 + +#undef XCHAL_HAVE_DFP_ACCEL +#define XCHAL_HAVE_DFP_ACCEL 0 +/* For backward compatibility */ +#undef XCHAL_HAVE_DFP_accel +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL + +#undef XCHAL_HAVE_WINDOWED +#define XCHAL_HAVE_WINDOWED 1 + +#undef XCHAL_NUM_AREGS +#define XCHAL_NUM_AREGS 32 + +#undef XCHAL_HAVE_WIDE_BRANCHES +#define XCHAL_HAVE_WIDE_BRANCHES 0 + +#undef XCHAL_HAVE_PREDICTED_BRANCHES +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 + + +#undef XCHAL_ICACHE_SIZE +#define XCHAL_ICACHE_SIZE 131072 + +#undef XCHAL_DCACHE_SIZE +#define XCHAL_DCACHE_SIZE 0 + +#undef XCHAL_ICACHE_LINESIZE +#define XCHAL_ICACHE_LINESIZE 128 + +#undef XCHAL_DCACHE_LINESIZE +#define XCHAL_DCACHE_LINESIZE 16 + +#undef XCHAL_ICACHE_LINEWIDTH +#define XCHAL_ICACHE_LINEWIDTH 7 + +#undef XCHAL_DCACHE_LINEWIDTH +#define XCHAL_DCACHE_LINEWIDTH 4 + +#undef XCHAL_DCACHE_IS_WRITEBACK +#define XCHAL_DCACHE_IS_WRITEBACK 0 + + +#undef XCHAL_HAVE_MMU +#define XCHAL_HAVE_MMU 0 + + +#undef XCHAL_HAVE_DEBUG +#define XCHAL_HAVE_DEBUG 1 + +#undef XCHAL_NUM_IBREAK +#define XCHAL_NUM_IBREAK 1 + +#undef XCHAL_NUM_DBREAK +#define XCHAL_NUM_DBREAK 1 + +#undef XCHAL_DEBUGLEVEL +#define XCHAL_DEBUGLEVEL 3 + + +#undef XCHAL_MAX_INSTRUCTION_SIZE +#define XCHAL_MAX_INSTRUCTION_SIZE 16 + +#undef XCHAL_INST_FETCH_WIDTH +#define XCHAL_INST_FETCH_WIDTH 16 + + +#undef XSHAL_ABI +#undef XTHAL_ABI_WINDOWED +#undef XTHAL_ABI_CALL0 +#define XSHAL_ABI XTHAL_ABI_WINDOWED +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 + + +#undef XCHAL_M_STAGE +#define XCHAL_M_STAGE 3 + +#undef XTENSA_MARCH_LATEST +#define XTENSA_MARCH_LATEST 270008 + +#undef XTENSA_MARCH_EARLIEST +#define XTENSA_MARCH_EARLIEST 270008 + + +#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_mtk_mvpu6_0226/gdb/gdbserver/xtensa-xtregs.c b/overlays/xtensa_mtk_mvpu6_0226/gdb/gdbserver/xtensa-xtregs.c new file mode 100644 index 00000000..1f667674 --- /dev/null +++ b/overlays/xtensa_mtk_mvpu6_0226/gdb/gdbserver/xtensa-xtregs.c @@ -0,0 +1,96 @@ +/* Customized table mapping between kernel xtregset and GDB register cache. + + Copyright (c) 2007-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +typedef struct { + int gdb_regnum; + int gdb_offset; + int ptrace_cp_offset; + int ptrace_offset; + int size; + int coproc; + int dbnum; + char* name +;} xtensa_regtable_t; + +#define XTENSA_ELF_XTREG_SIZE 3712 + +const xtensa_regtable_t xtensa_regmap_table[] = { + /* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */ + { 43, 172, 0, 0, 4, -1, 0x0204, "br" }, + { 44, 176, 4, 4, 4, -1, 0x0300, "apb_pipe" }, + { 45, 180, 320, 384, 64, 1, 0x1000, "v0" }, + { 46, 244, 384, 448, 64, 1, 0x1001, "v1" }, + { 47, 308, 448, 512, 64, 1, 0x1002, "v2" }, + { 48, 372, 512, 576, 64, 1, 0x1003, "v3" }, + { 49, 436, 576, 640, 64, 1, 0x1004, "v4" }, + { 50, 500, 640, 704, 64, 1, 0x1005, "v5" }, + { 51, 564, 704, 768, 64, 1, 0x1006, "v6" }, + { 52, 628, 768, 832, 64, 1, 0x1007, "v7" }, + { 53, 692, 832, 896, 64, 1, 0x1008, "v8" }, + { 54, 756, 896, 960, 64, 1, 0x1009, "v9" }, + { 55, 820, 960,1024, 64, 1, 0x100a, "v10" }, + { 56, 884,1024,1088, 64, 1, 0x100b, "v11" }, + { 57, 948,1088,1152, 64, 1, 0x100c, "v12" }, + { 58,1012,1152,1216, 64, 1, 0x100d, "v13" }, + { 59,1076,1216,1280, 64, 1, 0x100e, "v14" }, + { 60,1140,1280,1344, 64, 1, 0x100f, "v15" }, + { 61,1204,1344,1408, 64, 1, 0x1010, "v16" }, + { 62,1268,1408,1472, 64, 1, 0x1011, "v17" }, + { 63,1332,1472,1536, 64, 1, 0x1012, "v18" }, + { 64,1396,1536,1600, 64, 1, 0x1013, "v19" }, + { 65,1460,1600,1664, 64, 1, 0x1014, "v20" }, + { 66,1524,1664,1728, 64, 1, 0x1015, "v21" }, + { 67,1588,1728,1792, 64, 1, 0x1016, "v22" }, + { 68,1652,1792,1856, 64, 1, 0x1017, "v23" }, + { 69,1716,1856,1920, 64, 1, 0x1018, "v24" }, + { 70,1780,1920,1984, 64, 1, 0x1019, "v25" }, + { 71,1844,1984,2048, 64, 1, 0x101a, "v26" }, + { 72,1908,2048,2112, 64, 1, 0x101b, "v27" }, + { 73,1972,2112,2176, 64, 1, 0x101c, "v28" }, + { 74,2036,2176,2240, 64, 1, 0x101d, "v29" }, + { 75,2100,2240,2304, 64, 1, 0x101e, "v30" }, + { 76,2164,2304,2368, 64, 1, 0x101f, "v31" }, + { 77,2228, 256, 320, 8, 1, 0x1020, "vb0" }, + { 78,2236, 264, 328, 8, 1, 0x1021, "vb1" }, + { 79,2244, 272, 336, 8, 1, 0x1022, "vb2" }, + { 80,2252, 280, 344, 8, 1, 0x1023, "vb3" }, + { 81,2260, 288, 352, 8, 1, 0x1024, "vb4" }, + { 82,2268, 296, 360, 8, 1, 0x1025, "vb5" }, + { 83,2276, 304, 368, 8, 1, 0x1026, "vb6" }, + { 84,2284, 312, 376, 8, 1, 0x1027, "vb7" }, + { 85,2292, 0, 64, 64, 1, 0x1028, "u0" }, + { 86,2356, 64, 128, 64, 1, 0x1029, "u1" }, + { 87,2420, 128, 192, 64, 1, 0x102a, "u2" }, + { 88,2484, 192, 256, 64, 1, 0x102b, "u3" }, + { 89,2548,2624,2688,256, 1, 0x102c, "wv0" }, + { 90,2804,2880,2944,256, 1, 0x102d, "wv1" }, + { 91,3060,3136,3200,256, 1, 0x102e, "wv2" }, + { 92,3316,3392,3456,256, 1, 0x102f, "wv3" }, + { 93,3572,2368,2432, 64, 1, 0x1030, "gr0" }, + { 94,3636,2432,2496, 64, 1, 0x1031, "gr1" }, + { 95,3700,2496,2560, 64, 1, 0x1032, "gr2" }, + { 96,3764,2560,2624, 64, 1, 0x1033, "gr3" }, + { 0 } +}; + diff --git a/overlays/xtensa_mtk_mvpu6_0226/gdb/include/xtensa-config.h b/overlays/xtensa_mtk_mvpu6_0226/gdb/include/xtensa-config.h new file mode 100644 index 00000000..0bfb2b65 --- /dev/null +++ b/overlays/xtensa_mtk_mvpu6_0226/gdb/include/xtensa-config.h @@ -0,0 +1,189 @@ +/* Xtensa configuration settings. + Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 + Free Software Foundation, Inc. + Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +/* The macros defined here match those with the same names in the Xtensa + compile-time HAL (Hardware Abstraction Layer). Please refer to the + Xtensa System Software Reference Manual for documentation of these + macros. */ + +#undef XCHAL_HAVE_BE +#define XCHAL_HAVE_BE 0 + +#undef XCHAL_HAVE_DENSITY +#define XCHAL_HAVE_DENSITY 1 + +#undef XCHAL_HAVE_CONST16 +#define XCHAL_HAVE_CONST16 1 + +#undef XCHAL_HAVE_ABS +#define XCHAL_HAVE_ABS 1 + +#undef XCHAL_HAVE_ADDX +#define XCHAL_HAVE_ADDX 1 + +#undef XCHAL_HAVE_L32R +#define XCHAL_HAVE_L32R 1 + +#undef XSHAL_USE_ABSOLUTE_LITERALS +#define XSHAL_USE_ABSOLUTE_LITERALS 0 + +#undef XSHAL_HAVE_TEXT_SECTION_LITERALS +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#undef XCHAL_HAVE_MAC16 +#define XCHAL_HAVE_MAC16 0 + +#undef XCHAL_HAVE_MUL16 +#define XCHAL_HAVE_MUL16 1 + +#undef XCHAL_HAVE_MUL32 +#define XCHAL_HAVE_MUL32 1 + +#undef XCHAL_HAVE_MUL32_HIGH +#define XCHAL_HAVE_MUL32_HIGH 1 + +#undef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 1 + +#undef XCHAL_HAVE_NSA +#define XCHAL_HAVE_NSA 1 + +#undef XCHAL_HAVE_MINMAX +#define XCHAL_HAVE_MINMAX 1 + +#undef XCHAL_HAVE_SEXT +#define XCHAL_HAVE_SEXT 1 + +#undef XCHAL_HAVE_LOOPS +#define XCHAL_HAVE_LOOPS 1 + +#undef XCHAL_HAVE_THREADPTR +#define XCHAL_HAVE_THREADPTR 1 + +#undef XCHAL_HAVE_RELEASE_SYNC +#define XCHAL_HAVE_RELEASE_SYNC 1 + +#undef XCHAL_HAVE_S32C1I +#define XCHAL_HAVE_S32C1I 0 + +#undef XCHAL_HAVE_BOOLEANS +#define XCHAL_HAVE_BOOLEANS 1 + +#undef XCHAL_HAVE_FP +#define XCHAL_HAVE_FP 0 + +#undef XCHAL_HAVE_FP_DIV +#define XCHAL_HAVE_FP_DIV 0 + +#undef XCHAL_HAVE_FP_RECIP +#define XCHAL_HAVE_FP_RECIP 0 + +#undef XCHAL_HAVE_FP_SQRT +#define XCHAL_HAVE_FP_SQRT 0 + +#undef XCHAL_HAVE_FP_RSQRT +#define XCHAL_HAVE_FP_RSQRT 0 + +#undef XCHAL_HAVE_DFP_ACCEL +#define XCHAL_HAVE_DFP_ACCEL 0 +/* For backward compatibility */ +#undef XCHAL_HAVE_DFP_accel +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL + +#undef XCHAL_HAVE_WINDOWED +#define XCHAL_HAVE_WINDOWED 1 + +#undef XCHAL_NUM_AREGS +#define XCHAL_NUM_AREGS 32 + +#undef XCHAL_HAVE_WIDE_BRANCHES +#define XCHAL_HAVE_WIDE_BRANCHES 0 + +#undef XCHAL_HAVE_PREDICTED_BRANCHES +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 + + +#undef XCHAL_ICACHE_SIZE +#define XCHAL_ICACHE_SIZE 131072 + +#undef XCHAL_DCACHE_SIZE +#define XCHAL_DCACHE_SIZE 0 + +#undef XCHAL_ICACHE_LINESIZE +#define XCHAL_ICACHE_LINESIZE 128 + +#undef XCHAL_DCACHE_LINESIZE +#define XCHAL_DCACHE_LINESIZE 16 + +#undef XCHAL_ICACHE_LINEWIDTH +#define XCHAL_ICACHE_LINEWIDTH 7 + +#undef XCHAL_DCACHE_LINEWIDTH +#define XCHAL_DCACHE_LINEWIDTH 4 + +#undef XCHAL_DCACHE_IS_WRITEBACK +#define XCHAL_DCACHE_IS_WRITEBACK 0 + + +#undef XCHAL_HAVE_MMU +#define XCHAL_HAVE_MMU 0 + + +#undef XCHAL_HAVE_DEBUG +#define XCHAL_HAVE_DEBUG 1 + +#undef XCHAL_NUM_IBREAK +#define XCHAL_NUM_IBREAK 1 + +#undef XCHAL_NUM_DBREAK +#define XCHAL_NUM_DBREAK 1 + +#undef XCHAL_DEBUGLEVEL +#define XCHAL_DEBUGLEVEL 3 + + +#undef XCHAL_MAX_INSTRUCTION_SIZE +#define XCHAL_MAX_INSTRUCTION_SIZE 16 + +#undef XCHAL_INST_FETCH_WIDTH +#define XCHAL_INST_FETCH_WIDTH 16 + + +#undef XSHAL_ABI +#undef XTHAL_ABI_WINDOWED +#undef XTHAL_ABI_CALL0 +#define XSHAL_ABI XTHAL_ABI_WINDOWED +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 + + +#undef XCHAL_M_STAGE +#define XCHAL_M_STAGE 3 + +#undef XTENSA_MARCH_LATEST +#define XTENSA_MARCH_LATEST 270008 + +#undef XTENSA_MARCH_EARLIEST +#define XTENSA_MARCH_EARLIEST 270008 + + +#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_mtk_mvpu6_0226/newlib/newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h b/overlays/xtensa_mtk_mvpu6_0226/newlib/newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h new file mode 100644 index 00000000..da82844f --- /dev/null +++ b/overlays/xtensa_mtk_mvpu6_0226/newlib/newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h @@ -0,0 +1,644 @@ +/* + * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa + * processor CORE configuration + * + * See , which includes this file, for more details. + */ + +/* Xtensa processor core configuration information. + + Copyright (c) 1999-2018 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _XTENSA_CORE_CONFIGURATION_H +#define _XTENSA_CORE_CONFIGURATION_H + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 16 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 1 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_EXCLUSIVE 1 /* L32EX/S32EX instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 3 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion*/ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ +#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 + + + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */ +#define XCHAL_HAVE_FP 0 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ + +#define XCHAL_HAVE_FUSIONG 0 /* FusionG */ +#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ +#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ +#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ +#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ +#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ + +#define XCHAL_HAVE_PDX 0 /* PDX */ +#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ +#define XCHAL_HAVE_PDX4 0 /* PDX4 */ +#define XCHAL_HAVE_PDX8 0 /* PDX8 */ +#define XCHAL_HAVE_PDX16 0 /* PDX16 */ + +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + +#define XCHAL_HAVE_VISION 1 /* Vision P5/P6 */ +#define XCHAL_VISION_SIMD16 32 /* simd16 for Vision P5/P6 */ +#define XCHAL_VISION_TYPE 6 /* Vision P5, P6, or P3 */ +#define XCHAL_VISION_QUAD_MAC_TYPE 1 /* quad_mac option on Vision P6 */ +#define XCHAL_HAVE_VISION_HISTOGRAM 1 /* histogram option on Vision P5/P6 */ +#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */ +#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */ + +#define XCHAL_HAVE_VISIONC 0 /* Vision C */ + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_LOADSTORE_UNITS 2 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 16 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 64 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay + (1 = 5-stage, 2 = 7-stage) */ +#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ + +#define XCHAL_SW_VERSION 1200008 /* sw version of this header */ + +#define XCHAL_CORE_ID "MVPU6_0226" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x00071B8D /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC0F1FBFE /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x22071B8D /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX7.0.8" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2700 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 8 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 270008 /* major*100+minor */ +#define XCHAL_HW_REL_LX7 1 +#define XCHAL_HW_REL_LX7_0 1 +#define XCHAL_HW_REL_LX7_0_8 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2700 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 8 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 270008 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2700 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 8 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 270008 /* latest targeted hw */ + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 6 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 131072 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ +#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 1 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound bus present */ + +#define XCHAL_HAVE_AXI 1 /* AXI bus */ +#define XCHAL_HAVE_AXI_ECC 1 /* ECC on AXI bus */ +#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ + +#define XCHAL_HAVE_PIF_WR_RESP 1 /* pif write response */ +#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 8 +#define XCHAL_DCACHE_SETWIDTH 0 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 4 +#define XCHAL_DCACHE_WAYS 1 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 1 +#define XCHAL_DCACHE_LINE_LOCKABLE 0 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 + +/* Cache access size in bytes (affects operation of SICW instruction): */ +#define XCHAL_ICACHE_ACCESS_SIZE 16 +#define XCHAL_DCACHE_ACCESS_SIZE 1 + +#define XCHAL_DCACHE_BANKS 0 /* number of banks */ + +/* Number of encoded cache attr bits (see for decoded bits): */ + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ + +/* Instruction RAM 0: */ +#define XCHAL_INSTRAM0_VADDR 0x7FF40000 /* virtual address */ +#define XCHAL_INSTRAM0_PADDR 0x7FF40000 /* physical address */ +#define XCHAL_INSTRAM0_SIZE 262144 /* size in bytes */ +#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_HAVE_INSTRAM0 1 +#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Data RAM 0: */ +#define XCHAL_DATARAM0_VADDR 0x7FF00000 /* virtual address */ +#define XCHAL_DATARAM0_PADDR 0x7FF00000 /* physical address */ +#define XCHAL_DATARAM0_SIZE 131072 /* size in bytes */ +#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM0_BANKS 2 /* number of banks */ +#define XCHAL_HAVE_DATARAM0 1 +#define XCHAL_DATARAM0_HAVE_IDMA 1 /* idma supported by this local memory */ + +/* Data RAM 1: */ +#define XCHAL_DATARAM1_VADDR 0x7FF20000 /* virtual address */ +#define XCHAL_DATARAM1_PADDR 0x7FF20000 /* physical address */ +#define XCHAL_DATARAM1_SIZE 131072 /* size in bytes */ +#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM1_BANKS 2 /* number of banks */ +#define XCHAL_HAVE_DATARAM1 1 +#define XCHAL_DATARAM1_HAVE_IDMA 1 /* idma supported by this local memory */ + +#define XCHAL_HAVE_IDMA 1 +#define XCHAL_HAVE_IDMA_TRANSPOSE 0 + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 25 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 16 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 3 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_EXCM_LEVEL 2 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x000103FF +#define XCHAL_INTLEVEL2_MASK 0x00FEFC00 +#define XCHAL_INTLEVEL3_MASK 0x00000000 +#define XCHAL_INTLEVEL4_MASK 0x01000000 +#define XCHAL_INTLEVEL5_MASK 0x00000000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00000000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000103FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00FFFFFF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00FFFFFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x01FFFFFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x01FFFFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x01FFFFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x01FFFFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 1 +#define XCHAL_INT9_LEVEL 1 +#define XCHAL_INT10_LEVEL 2 +#define XCHAL_INT11_LEVEL 2 +#define XCHAL_INT12_LEVEL 2 +#define XCHAL_INT13_LEVEL 2 +#define XCHAL_INT14_LEVEL 2 +#define XCHAL_INT15_LEVEL 2 +#define XCHAL_INT16_LEVEL 1 +#define XCHAL_INT17_LEVEL 2 +#define XCHAL_INT18_LEVEL 2 +#define XCHAL_INT19_LEVEL 2 +#define XCHAL_INT20_LEVEL 2 +#define XCHAL_INT21_LEVEL 2 +#define XCHAL_INT22_LEVEL 2 +#define XCHAL_INT23_LEVEL 2 +#define XCHAL_INT24_LEVEL 4 +#define XCHAL_DEBUGLEVEL 3 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 4 /* NMI "level" (for use with + EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_PROFILING +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_IDMA_DONE +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_IDMA_ERR +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_GS_ERR +#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT23_TYPE XTHAL_INTTYPE_WRITE_ERROR +#define XCHAL_INT24_TYPE XTHAL_INTTYPE_NMI + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFE000000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00008200 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00430000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x00003CFF +#define XCHAL_INTTYPE_MASK_TIMER 0x00004100 +#define XCHAL_INTTYPE_MASK_NMI 0x01000000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00800000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x00040000 +#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00080000 +#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00100000 +#define XCHAL_INTTYPE_MASK_GS_ERR 0x00200000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 8 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 14 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 24 /* non-maskable interrupt */ +#define XCHAL_WRITE_ERROR_INTERRUPT 23 +#define XCHAL_PROFILING_INTERRUPT 18 +#define XCHAL_IDMA_DONE_INTERRUPT 19 +#define XCHAL_IDMA_ERR_INTERRUPT 20 +#define XCHAL_GS_ERR_INTERRUPT 21 + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL4_NUM 24 +/* (There are many interrupts each at level(s) 1, 2.) */ + + +/* + * External interrupt mapping. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */ +#define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */ +#define XCHAL_EXTINT8_NUM 10 /* (intlevel 2) */ +#define XCHAL_EXTINT9_NUM 11 /* (intlevel 2) */ +#define XCHAL_EXTINT10_NUM 12 /* (intlevel 2) */ +#define XCHAL_EXTINT11_NUM 13 /* (intlevel 2) */ +#define XCHAL_EXTINT12_NUM 16 /* (intlevel 1) */ +#define XCHAL_EXTINT13_NUM 17 /* (intlevel 2) */ +#define XCHAL_EXTINT14_NUM 22 /* (intlevel 2) */ +#define XCHAL_EXTINT15_NUM 24 /* (intlevel 4) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ +#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ +#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ +#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ +#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT6_EXTNUM 6 /* (intlevel 1) */ +#define XCHAL_INT7_EXTNUM 7 /* (intlevel 1) */ +#define XCHAL_INT10_EXTNUM 8 /* (intlevel 2) */ +#define XCHAL_INT11_EXTNUM 9 /* (intlevel 2) */ +#define XCHAL_INT12_EXTNUM 10 /* (intlevel 2) */ +#define XCHAL_INT13_EXTNUM 11 /* (intlevel 2) */ +#define XCHAL_INT16_EXTNUM 12 /* (intlevel 1) */ +#define XCHAL_INT17_EXTNUM 13 /* (intlevel 2) */ +#define XCHAL_INT22_EXTNUM 14 /* (intlevel 2) */ +#define XCHAL_INT24_EXTNUM 15 /* (intlevel 4) */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (old) + 2 == XEA2 (new) + 0 == XEAX (extern) or TX */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x60000000 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x60000000 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0x50000000 +#define XCHAL_RESET_VECTOR0_PADDR 0x50000000 +#define XCHAL_RESET_VECTOR1_VADDR 0x7FF40000 +#define XCHAL_RESET_VECTOR1_PADDR 0x7FF40000 +#define XCHAL_RESET_VECTOR_VADDR 0x50000000 +#define XCHAL_RESET_VECTOR_PADDR 0x50000000 +#define XCHAL_USER_VECOFS 0x00000280 +#define XCHAL_USER_VECTOR_VADDR 0x60000280 +#define XCHAL_USER_VECTOR_PADDR 0x60000280 +#define XCHAL_KERNEL_VECOFS 0x00000240 +#define XCHAL_KERNEL_VECTOR_VADDR 0x60000240 +#define XCHAL_KERNEL_VECTOR_PADDR 0x60000240 +#define XCHAL_DOUBLEEXC_VECOFS 0x00000300 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x60000300 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x60000300 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x60000000 +#define XCHAL_WINDOW_VECTORS_PADDR 0x60000000 +#define XCHAL_INTLEVEL2_VECOFS 0x00000180 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x60000180 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x60000180 +#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x600001C0 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x600001C0 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL3_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL3_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL3_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x00000200 +#define XCHAL_NMI_VECTOR_VADDR 0x60000200 +#define XCHAL_NMI_VECTOR_PADDR 0x60000200 +#define XCHAL_INTLEVEL4_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL4_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL4_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG MODULE + ----------------------------------------------------------------------*/ + +/* Misc */ +#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 1 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 1 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ +#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ +#define XCHAL_NUM_PERF_COUNTERS 8 /* performance counters */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 0 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */ +#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ + +/* If none of the above last 5 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +/*---------------------------------------------------------------------- + MPU + ----------------------------------------------------------------------*/ +#define XCHAL_HAVE_MPU 1 +#define XCHAL_MPU_ENTRIES 32 + +#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ +#define XCHAL_MPU_BACKGROUND_ENTRIES 2 /* number of entries in bg map*/ +#define XCHAL_MPU_BG_CACHEADRDIS 0xFF /* default CACHEADRDIS for bg */ + +#define XCHAL_MPU_ALIGN_BITS 12 +#define XCHAL_MPU_ALIGN 4096 + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* _XTENSA_CORE_CONFIGURATION_H */ +