From 68cd020a6bc4e6a9a2b767a23a3296afeb891852 Mon Sep 17 00:00:00 2001
From: serge-sans-paille <serge.guelton@telecom-bretagne.eu>
Date: Wed, 15 Jan 2025 22:00:26 +0100
Subject: [PATCH 1/2] Add missing batch cast from rvv types

---
 include/xsimd/types/xsimd_rvv_register.hpp | 40 ++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/include/xsimd/types/xsimd_rvv_register.hpp b/include/xsimd/types/xsimd_rvv_register.hpp
index 4d5258d30..8c727b8fb 100644
--- a/include/xsimd/types/xsimd_rvv_register.hpp
+++ b/include/xsimd/types/xsimd_rvv_register.hpp
@@ -143,6 +143,27 @@ namespace xsimd
                 return __riscv_vreinterpret_i8m1(x);
             }
             template <>
+            XSIMD_INLINE rvv_type_info<int16_t, rvv_width_m1 * 1>::type
+            rvv_type_info<int16_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
+                __rvv_uint8m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_i16m1(x);
+            }
+            template <>
+            XSIMD_INLINE rvv_type_info<int32_t, rvv_width_m1 * 1>::type
+            rvv_type_info<int32_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
+                __rvv_uint8m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_i32m1(x);
+            }
+            template <>
+            XSIMD_INLINE rvv_type_info<int64_t, rvv_width_m1 * 1>::type
+            rvv_type_info<int64_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
+                __rvv_uint8m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_i64m1(x);
+            }
+            template <>
             XSIMD_INLINE rvv_type_info<uint16_t, rvv_width_m1 * 1>::type
             rvv_type_info<uint16_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
                 __rvv_uint8m1_t x) noexcept
@@ -179,6 +200,25 @@ namespace xsimd
                 return __riscv_vreinterpret_u8m1(x);
             }
 
+            template <>
+            XSIMD_INLINE rvv_type_info<int16_t, rvv_width_m1 * 1>::byte_type
+            rvv_type_info<int16_t, rvv_width_m1 * 1>::as_bytes<__rvv_int16m1_t>(__rvv_int16m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_u8m1(x);
+            }
+            template <>
+            XSIMD_INLINE rvv_type_info<int32_t, rvv_width_m1 * 1>::byte_type
+            rvv_type_info<int32_t, rvv_width_m1 * 1>::as_bytes<__rvv_int32m1_t>(__rvv_int32m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_u8m1(x);
+            }
+            template <>
+            XSIMD_INLINE rvv_type_info<int64_t, rvv_width_m1 * 1>::byte_type
+            rvv_type_info<int64_t, rvv_width_m1 * 1>::as_bytes<__rvv_int64m1_t>(__rvv_int64m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_u8m1(x);
+            }
+
             template <>
             XSIMD_INLINE rvv_type_info<uint8_t, rvv_width_m1 * 1>::byte_type
             rvv_type_info<uint8_t, rvv_width_m1 * 1>::as_bytes<__rvv_uint8m1_t>(__rvv_uint8m1_t x) noexcept

From 3015bbde079fab7f2b2c1d59fe96f6237338d175 Mon Sep 17 00:00:00 2001
From: serge-sans-paille <serge.guelton@telecom-bretagne.eu>
Date: Wed, 15 Jan 2025 22:32:29 +0100
Subject: [PATCH 2/2] WIP

---
 include/xsimd/types/xsimd_rvv_register.hpp | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/include/xsimd/types/xsimd_rvv_register.hpp b/include/xsimd/types/xsimd_rvv_register.hpp
index 8c727b8fb..b46790ea5 100644
--- a/include/xsimd/types/xsimd_rvv_register.hpp
+++ b/include/xsimd/types/xsimd_rvv_register.hpp
@@ -147,21 +147,21 @@ namespace xsimd
             rvv_type_info<int16_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
                 __rvv_uint8m1_t x) noexcept
             {
-                return __riscv_vreinterpret_i16m1(x);
+                return __riscv_vreinterpret_i16m1(__riscv_vreinterpret_u16m1(x));
             }
             template <>
             XSIMD_INLINE rvv_type_info<int32_t, rvv_width_m1 * 1>::type
             rvv_type_info<int32_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
                 __rvv_uint8m1_t x) noexcept
             {
-                return __riscv_vreinterpret_i32m1(x);
+                return __riscv_vreinterpret_i32m1(__riscv_vreinterpret_u32m1(x));
             }
             template <>
             XSIMD_INLINE rvv_type_info<int64_t, rvv_width_m1 * 1>::type
             rvv_type_info<int64_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
                 __rvv_uint8m1_t x) noexcept
             {
-                return __riscv_vreinterpret_i64m1(x);
+                return __riscv_vreinterpret_i64m1(__riscv_vreinterpret_u64m1(x));
             }
             template <>
             XSIMD_INLINE rvv_type_info<uint16_t, rvv_width_m1 * 1>::type
@@ -204,19 +204,19 @@ namespace xsimd
             XSIMD_INLINE rvv_type_info<int16_t, rvv_width_m1 * 1>::byte_type
             rvv_type_info<int16_t, rvv_width_m1 * 1>::as_bytes<__rvv_int16m1_t>(__rvv_int16m1_t x) noexcept
             {
-                return __riscv_vreinterpret_u8m1(x);
+                return __riscv_vreinterpret_u8m1(__riscv_vreinterpret_u16m1(x));
             }
             template <>
             XSIMD_INLINE rvv_type_info<int32_t, rvv_width_m1 * 1>::byte_type
             rvv_type_info<int32_t, rvv_width_m1 * 1>::as_bytes<__rvv_int32m1_t>(__rvv_int32m1_t x) noexcept
             {
-                return __riscv_vreinterpret_u8m1(x);
+                return __riscv_vreinterpret_u8m1(__riscv_vreinterpret_u32m1(x));
             }
             template <>
             XSIMD_INLINE rvv_type_info<int64_t, rvv_width_m1 * 1>::byte_type
             rvv_type_info<int64_t, rvv_width_m1 * 1>::as_bytes<__rvv_int64m1_t>(__rvv_int64m1_t x) noexcept
             {
-                return __riscv_vreinterpret_u8m1(x);
+                return __riscv_vreinterpret_u8m1(__riscv_vreinterpret_u64m1(x));
             }
 
             template <>