README.md

This repository contains following laboratory experiments:

• Design of an Arithmetic Circuit
• Design of an Arithmetic Logic Unit (ALU)
• Data Transferring From One Tri-state Buffer Register to Another Through Bus
• Introduction to Verilog Programming

Each experiment contains the following materials:

• Circuit (.circ file)
• Demo Video of circuit
• Report on the experiment
• Sequencial screenshots of circuit design

A Random Screenshot from lab work:

Figure 1: Data Transferring From One Tri-state Buffer Register to Another Through Bus