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spu-tdep.c
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/* SPU target-dependent code for GDB, the GNU debugger.
Copyright (C) 2006-2015 Free Software Foundation, Inc.
Contributed by Ulrich Weigand <[email protected]>.
Based on a port by Sid Manning <[email protected]>.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "defs.h"
#include "arch-utils.h"
#include "gdbtypes.h"
#include "gdbcmd.h"
#include "gdbcore.h"
#include "frame.h"
#include "frame-unwind.h"
#include "frame-base.h"
#include "trad-frame.h"
#include "symtab.h"
#include "symfile.h"
#include "value.h"
#include "inferior.h"
#include "dis-asm.h"
#include "objfiles.h"
#include "language.h"
#include "regcache.h"
#include "reggroups.h"
#include "floatformat.h"
#include "block.h"
#include "observer.h"
#include "infcall.h"
#include "dwarf2.h"
#include "dwarf2-frame.h"
#include "ax.h"
#include "spu-tdep.h"
#include "location.h"
/* The list of available "set spu " and "show spu " commands. */
static struct cmd_list_element *setspucmdlist = NULL;
static struct cmd_list_element *showspucmdlist = NULL;
/* Whether to stop for new SPE contexts. */
static int spu_stop_on_load_p = 0;
/* Whether to automatically flush the SW-managed cache. */
static int spu_auto_flush_cache_p = 1;
/* The tdep structure. */
struct gdbarch_tdep
{
/* The spufs ID identifying our address space. */
int id;
/* SPU-specific vector type. */
struct type *spu_builtin_type_vec128;
};
/* SPU-specific vector type. */
static struct type *
spu_builtin_type_vec128 (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (!tdep->spu_builtin_type_vec128)
{
const struct builtin_type *bt = builtin_type (gdbarch);
struct type *t;
t = arch_composite_type (gdbarch,
"__spu_builtin_type_vec128", TYPE_CODE_UNION);
append_composite_type_field (t, "uint128", bt->builtin_int128);
append_composite_type_field (t, "v2_int64",
init_vector_type (bt->builtin_int64, 2));
append_composite_type_field (t, "v4_int32",
init_vector_type (bt->builtin_int32, 4));
append_composite_type_field (t, "v8_int16",
init_vector_type (bt->builtin_int16, 8));
append_composite_type_field (t, "v16_int8",
init_vector_type (bt->builtin_int8, 16));
append_composite_type_field (t, "v2_double",
init_vector_type (bt->builtin_double, 2));
append_composite_type_field (t, "v4_float",
init_vector_type (bt->builtin_float, 4));
TYPE_VECTOR (t) = 1;
TYPE_NAME (t) = "spu_builtin_type_vec128";
tdep->spu_builtin_type_vec128 = t;
}
return tdep->spu_builtin_type_vec128;
}
/* The list of available "info spu " commands. */
static struct cmd_list_element *infospucmdlist = NULL;
/* Registers. */
static const char *
spu_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] =
{
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
"r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
"r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
"r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
"r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
"r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
"r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
"r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
"r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
"r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
"r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
"id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
};
if (reg_nr < 0)
return NULL;
if (reg_nr >= sizeof register_names / sizeof *register_names)
return NULL;
return register_names[reg_nr];
}
static struct type *
spu_register_type (struct gdbarch *gdbarch, int reg_nr)
{
if (reg_nr < SPU_NUM_GPRS)
return spu_builtin_type_vec128 (gdbarch);
switch (reg_nr)
{
case SPU_ID_REGNUM:
return builtin_type (gdbarch)->builtin_uint32;
case SPU_PC_REGNUM:
return builtin_type (gdbarch)->builtin_func_ptr;
case SPU_SP_REGNUM:
return builtin_type (gdbarch)->builtin_data_ptr;
case SPU_FPSCR_REGNUM:
return builtin_type (gdbarch)->builtin_uint128;
case SPU_SRR0_REGNUM:
return builtin_type (gdbarch)->builtin_uint32;
case SPU_LSLR_REGNUM:
return builtin_type (gdbarch)->builtin_uint32;
case SPU_DECR_REGNUM:
return builtin_type (gdbarch)->builtin_uint32;
case SPU_DECR_STATUS_REGNUM:
return builtin_type (gdbarch)->builtin_uint32;
default:
internal_error (__FILE__, __LINE__, _("invalid regnum"));
}
}
/* Pseudo registers for preferred slots - stack pointer. */
static enum register_status
spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname,
gdb_byte *buf)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
enum register_status status;
gdb_byte reg[32];
char annex[32];
ULONGEST id;
ULONGEST ul;
status = regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
if (status != REG_VALID)
return status;
xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
memset (reg, 0, sizeof reg);
target_read (¤t_target, TARGET_OBJECT_SPU, annex,
reg, 0, sizeof reg);
ul = strtoulst ((char *) reg, NULL, 16);
store_unsigned_integer (buf, 4, byte_order, ul);
return REG_VALID;
}
static enum register_status
spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
int regnum, gdb_byte *buf)
{
gdb_byte reg[16];
char annex[32];
ULONGEST id;
enum register_status status;
switch (regnum)
{
case SPU_SP_REGNUM:
status = regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
if (status != REG_VALID)
return status;
memcpy (buf, reg, 4);
return status;
case SPU_FPSCR_REGNUM:
status = regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
if (status != REG_VALID)
return status;
xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
return status;
case SPU_SRR0_REGNUM:
return spu_pseudo_register_read_spu (regcache, "srr0", buf);
case SPU_LSLR_REGNUM:
return spu_pseudo_register_read_spu (regcache, "lslr", buf);
case SPU_DECR_REGNUM:
return spu_pseudo_register_read_spu (regcache, "decr", buf);
case SPU_DECR_STATUS_REGNUM:
return spu_pseudo_register_read_spu (regcache, "decr_status", buf);
default:
internal_error (__FILE__, __LINE__, _("invalid regnum"));
}
}
static void
spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
const gdb_byte *buf)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
char reg[32];
char annex[32];
ULONGEST id;
regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
xsnprintf (reg, sizeof reg, "0x%s",
phex_nz (extract_unsigned_integer (buf, 4, byte_order), 4));
target_write (¤t_target, TARGET_OBJECT_SPU, annex,
(gdb_byte *) reg, 0, strlen (reg));
}
static void
spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
int regnum, const gdb_byte *buf)
{
gdb_byte reg[16];
char annex[32];
ULONGEST id;
switch (regnum)
{
case SPU_SP_REGNUM:
regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
memcpy (reg, buf, 4);
regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
break;
case SPU_FPSCR_REGNUM:
regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
target_write (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
break;
case SPU_SRR0_REGNUM:
spu_pseudo_register_write_spu (regcache, "srr0", buf);
break;
case SPU_LSLR_REGNUM:
spu_pseudo_register_write_spu (regcache, "lslr", buf);
break;
case SPU_DECR_REGNUM:
spu_pseudo_register_write_spu (regcache, "decr", buf);
break;
case SPU_DECR_STATUS_REGNUM:
spu_pseudo_register_write_spu (regcache, "decr_status", buf);
break;
default:
internal_error (__FILE__, __LINE__, _("invalid regnum"));
}
}
static int
spu_ax_pseudo_register_collect (struct gdbarch *gdbarch,
struct agent_expr *ax, int regnum)
{
switch (regnum)
{
case SPU_SP_REGNUM:
ax_reg_mask (ax, SPU_RAW_SP_REGNUM);
return 0;
case SPU_FPSCR_REGNUM:
case SPU_SRR0_REGNUM:
case SPU_LSLR_REGNUM:
case SPU_DECR_REGNUM:
case SPU_DECR_STATUS_REGNUM:
return -1;
default:
internal_error (__FILE__, __LINE__, _("invalid regnum"));
}
}
static int
spu_ax_pseudo_register_push_stack (struct gdbarch *gdbarch,
struct agent_expr *ax, int regnum)
{
switch (regnum)
{
case SPU_SP_REGNUM:
ax_reg (ax, SPU_RAW_SP_REGNUM);
return 0;
case SPU_FPSCR_REGNUM:
case SPU_SRR0_REGNUM:
case SPU_LSLR_REGNUM:
case SPU_DECR_REGNUM:
case SPU_DECR_STATUS_REGNUM:
return -1;
default:
internal_error (__FILE__, __LINE__, _("invalid regnum"));
}
}
/* Value conversion -- access scalar values at the preferred slot. */
static struct value *
spu_value_from_register (struct gdbarch *gdbarch, struct type *type,
int regnum, struct frame_id frame_id)
{
struct value *value = default_value_from_register (gdbarch, type,
regnum, frame_id);
int len = TYPE_LENGTH (type);
if (regnum < SPU_NUM_GPRS && len < 16)
{
int preferred_slot = len < 4 ? 4 - len : 0;
set_value_offset (value, preferred_slot);
}
return value;
}
/* Register groups. */
static int
spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
struct reggroup *group)
{
/* Registers displayed via 'info regs'. */
if (group == general_reggroup)
return 1;
/* Registers displayed via 'info float'. */
if (group == float_reggroup)
return 0;
/* Registers that need to be saved/restored in order to
push or pop frames. */
if (group == save_reggroup || group == restore_reggroup)
return 1;
return default_register_reggroup_p (gdbarch, regnum, group);
}
/* DWARF-2 register numbers. */
static int
spu_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
{
/* Use cooked instead of raw SP. */
return (reg == SPU_RAW_SP_REGNUM)? SPU_SP_REGNUM : reg;
}
/* Address handling. */
static int
spu_gdbarch_id (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
int id = tdep->id;
/* The objfile architecture of a standalone SPU executable does not
provide an SPU ID. Retrieve it from the objfile's relocated
address range in this special case. */
if (id == -1
&& symfile_objfile && symfile_objfile->obfd
&& bfd_get_arch (symfile_objfile->obfd) == bfd_arch_spu
&& symfile_objfile->sections != symfile_objfile->sections_end)
id = SPUADDR_SPU (obj_section_addr (symfile_objfile->sections));
return id;
}
static int
spu_address_class_type_flags (int byte_size, int dwarf2_addr_class)
{
if (dwarf2_addr_class == 1)
return TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
else
return 0;
}
static const char *
spu_address_class_type_flags_to_name (struct gdbarch *gdbarch, int type_flags)
{
if (type_flags & TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1)
return "__ea";
else
return NULL;
}
static int
spu_address_class_name_to_type_flags (struct gdbarch *gdbarch,
const char *name, int *type_flags_ptr)
{
if (strcmp (name, "__ea") == 0)
{
*type_flags_ptr = TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
return 1;
}
else
return 0;
}
static void
spu_address_to_pointer (struct gdbarch *gdbarch,
struct type *type, gdb_byte *buf, CORE_ADDR addr)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
SPUADDR_ADDR (addr));
}
static CORE_ADDR
spu_pointer_to_address (struct gdbarch *gdbarch,
struct type *type, const gdb_byte *buf)
{
int id = spu_gdbarch_id (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ULONGEST addr
= extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
/* Do not convert __ea pointers. */
if (TYPE_ADDRESS_CLASS_1 (type))
return addr;
return addr? SPUADDR (id, addr) : 0;
}
static CORE_ADDR
spu_integer_to_address (struct gdbarch *gdbarch,
struct type *type, const gdb_byte *buf)
{
int id = spu_gdbarch_id (gdbarch);
ULONGEST addr = unpack_long (type, buf);
return SPUADDR (id, addr);
}
/* Decoding SPU instructions. */
enum
{
op_lqd = 0x34,
op_lqx = 0x3c4,
op_lqa = 0x61,
op_lqr = 0x67,
op_stqd = 0x24,
op_stqx = 0x144,
op_stqa = 0x41,
op_stqr = 0x47,
op_il = 0x081,
op_ila = 0x21,
op_a = 0x0c0,
op_ai = 0x1c,
op_selb = 0x8,
op_br = 0x64,
op_bra = 0x60,
op_brsl = 0x66,
op_brasl = 0x62,
op_brnz = 0x42,
op_brz = 0x40,
op_brhnz = 0x46,
op_brhz = 0x44,
op_bi = 0x1a8,
op_bisl = 0x1a9,
op_biz = 0x128,
op_binz = 0x129,
op_bihz = 0x12a,
op_bihnz = 0x12b,
};
static int
is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
{
if ((insn >> 21) == op)
{
*rt = insn & 127;
*ra = (insn >> 7) & 127;
*rb = (insn >> 14) & 127;
return 1;
}
return 0;
}
static int
is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
{
if ((insn >> 28) == op)
{
*rt = (insn >> 21) & 127;
*ra = (insn >> 7) & 127;
*rb = (insn >> 14) & 127;
*rc = insn & 127;
return 1;
}
return 0;
}
static int
is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
{
if ((insn >> 21) == op)
{
*rt = insn & 127;
*ra = (insn >> 7) & 127;
*i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
return 1;
}
return 0;
}
static int
is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
{
if ((insn >> 24) == op)
{
*rt = insn & 127;
*ra = (insn >> 7) & 127;
*i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
return 1;
}
return 0;
}
static int
is_ri16 (unsigned int insn, int op, int *rt, int *i16)
{
if ((insn >> 23) == op)
{
*rt = insn & 127;
*i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
return 1;
}
return 0;
}
static int
is_ri18 (unsigned int insn, int op, int *rt, int *i18)
{
if ((insn >> 25) == op)
{
*rt = insn & 127;
*i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
return 1;
}
return 0;
}
static int
is_branch (unsigned int insn, int *offset, int *reg)
{
int rt, i7, i16;
if (is_ri16 (insn, op_br, &rt, &i16)
|| is_ri16 (insn, op_brsl, &rt, &i16)
|| is_ri16 (insn, op_brnz, &rt, &i16)
|| is_ri16 (insn, op_brz, &rt, &i16)
|| is_ri16 (insn, op_brhnz, &rt, &i16)
|| is_ri16 (insn, op_brhz, &rt, &i16))
{
*reg = SPU_PC_REGNUM;
*offset = i16 << 2;
return 1;
}
if (is_ri16 (insn, op_bra, &rt, &i16)
|| is_ri16 (insn, op_brasl, &rt, &i16))
{
*reg = -1;
*offset = i16 << 2;
return 1;
}
if (is_ri7 (insn, op_bi, &rt, reg, &i7)
|| is_ri7 (insn, op_bisl, &rt, reg, &i7)
|| is_ri7 (insn, op_biz, &rt, reg, &i7)
|| is_ri7 (insn, op_binz, &rt, reg, &i7)
|| is_ri7 (insn, op_bihz, &rt, reg, &i7)
|| is_ri7 (insn, op_bihnz, &rt, reg, &i7))
{
*offset = 0;
return 1;
}
return 0;
}
/* Prolog parsing. */
struct spu_prologue_data
{
/* Stack frame size. -1 if analysis was unsuccessful. */
int size;
/* How to find the CFA. The CFA is equal to SP at function entry. */
int cfa_reg;
int cfa_offset;
/* Offset relative to CFA where a register is saved. -1 if invalid. */
int reg_offset[SPU_NUM_GPRS];
};
static CORE_ADDR
spu_analyze_prologue (struct gdbarch *gdbarch,
CORE_ADDR start_pc, CORE_ADDR end_pc,
struct spu_prologue_data *data)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int found_sp = 0;
int found_fp = 0;
int found_lr = 0;
int found_bc = 0;
int reg_immed[SPU_NUM_GPRS];
gdb_byte buf[16];
CORE_ADDR prolog_pc = start_pc;
CORE_ADDR pc;
int i;
/* Initialize DATA to default values. */
data->size = -1;
data->cfa_reg = SPU_RAW_SP_REGNUM;
data->cfa_offset = 0;
for (i = 0; i < SPU_NUM_GPRS; i++)
data->reg_offset[i] = -1;
/* Set up REG_IMMED array. This is non-zero for a register if we know its
preferred slot currently holds this immediate value. */
for (i = 0; i < SPU_NUM_GPRS; i++)
reg_immed[i] = 0;
/* Scan instructions until the first branch.
The following instructions are important prolog components:
- The first instruction to set up the stack pointer.
- The first instruction to set up the frame pointer.
- The first instruction to save the link register.
- The first instruction to save the backchain.
We return the instruction after the latest of these four,
or the incoming PC if none is found. The first instruction
to set up the stack pointer also defines the frame size.
Note that instructions saving incoming arguments to their stack
slots are not counted as important, because they are hard to
identify with certainty. This should not matter much, because
arguments are relevant only in code compiled with debug data,
and in such code the GDB core will advance until the first source
line anyway, using SAL data.
For purposes of stack unwinding, we analyze the following types
of instructions in addition:
- Any instruction adding to the current frame pointer.
- Any instruction loading an immediate constant into a register.
- Any instruction storing a register onto the stack.
These are used to compute the CFA and REG_OFFSET output. */
for (pc = start_pc; pc < end_pc; pc += 4)
{
unsigned int insn;
int rt, ra, rb, rc, immed;
if (target_read_memory (pc, buf, 4))
break;
insn = extract_unsigned_integer (buf, 4, byte_order);
/* AI is the typical instruction to set up a stack frame.
It is also used to initialize the frame pointer. */
if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
{
if (rt == data->cfa_reg && ra == data->cfa_reg)
data->cfa_offset -= immed;
if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
&& !found_sp)
{
found_sp = 1;
prolog_pc = pc + 4;
data->size = -immed;
}
else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
&& !found_fp)
{
found_fp = 1;
prolog_pc = pc + 4;
data->cfa_reg = SPU_FP_REGNUM;
data->cfa_offset -= immed;
}
}
/* A is used to set up stack frames of size >= 512 bytes.
If we have tracked the contents of the addend register,
we can handle this as well. */
else if (is_rr (insn, op_a, &rt, &ra, &rb))
{
if (rt == data->cfa_reg && ra == data->cfa_reg)
{
if (reg_immed[rb] != 0)
data->cfa_offset -= reg_immed[rb];
else
data->cfa_reg = -1; /* We don't know the CFA any more. */
}
if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
&& !found_sp)
{
found_sp = 1;
prolog_pc = pc + 4;
if (reg_immed[rb] != 0)
data->size = -reg_immed[rb];
}
}
/* We need to track IL and ILA used to load immediate constants
in case they are later used as input to an A instruction. */
else if (is_ri16 (insn, op_il, &rt, &immed))
{
reg_immed[rt] = immed;
if (rt == SPU_RAW_SP_REGNUM && !found_sp)
found_sp = 1;
}
else if (is_ri18 (insn, op_ila, &rt, &immed))
{
reg_immed[rt] = immed & 0x3ffff;
if (rt == SPU_RAW_SP_REGNUM && !found_sp)
found_sp = 1;
}
/* STQD is used to save registers to the stack. */
else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
{
if (ra == data->cfa_reg)
data->reg_offset[rt] = data->cfa_offset - (immed << 4);
if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
&& !found_lr)
{
found_lr = 1;
prolog_pc = pc + 4;
}
if (ra == SPU_RAW_SP_REGNUM
&& (found_sp? immed == 0 : rt == SPU_RAW_SP_REGNUM)
&& !found_bc)
{
found_bc = 1;
prolog_pc = pc + 4;
}
}
/* _start uses SELB to set up the stack pointer. */
else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
{
if (rt == SPU_RAW_SP_REGNUM && !found_sp)
found_sp = 1;
}
/* We terminate if we find a branch. */
else if (is_branch (insn, &immed, &ra))
break;
}
/* If we successfully parsed until here, and didn't find any instruction
modifying SP, we assume we have a frameless function. */
if (!found_sp)
data->size = 0;
/* Return cooked instead of raw SP. */
if (data->cfa_reg == SPU_RAW_SP_REGNUM)
data->cfa_reg = SPU_SP_REGNUM;
return prolog_pc;
}
/* Return the first instruction after the prologue starting at PC. */
static CORE_ADDR
spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
{
struct spu_prologue_data data;
return spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
}
/* Return the frame pointer in use at address PC. */
static void
spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
int *reg, LONGEST *offset)
{
struct spu_prologue_data data;
spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
if (data.size != -1 && data.cfa_reg != -1)
{
/* The 'frame pointer' address is CFA minus frame size. */
*reg = data.cfa_reg;
*offset = data.cfa_offset - data.size;
}
else
{
/* ??? We don't really know ... */
*reg = SPU_SP_REGNUM;
*offset = 0;
}
}
/* Implement the stack_frame_destroyed_p gdbarch method.
1) scan forward from the point of execution:
a) If you find an instruction that modifies the stack pointer
or transfers control (except a return), execution is not in
an epilogue, return.
b) Stop scanning if you find a return instruction or reach the
end of the function or reach the hard limit for the size of
an epilogue.
2) scan backward from the point of execution:
a) If you find an instruction that modifies the stack pointer,
execution *is* in an epilogue, return.
b) Stop scanning if you reach an instruction that transfers
control or the beginning of the function or reach the hard
limit for the size of an epilogue. */
static int
spu_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
bfd_byte buf[4];
unsigned int insn;
int rt, ra, rb, immed;
/* Find the search limits based on function boundaries and hard limit.
We assume the epilogue can be up to 64 instructions long. */
const int spu_max_epilogue_size = 64 * 4;
if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
return 0;
if (pc - func_start < spu_max_epilogue_size)
epilogue_start = func_start;
else
epilogue_start = pc - spu_max_epilogue_size;
if (func_end - pc < spu_max_epilogue_size)
epilogue_end = func_end;
else
epilogue_end = pc + spu_max_epilogue_size;
/* Scan forward until next 'bi $0'. */
for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
{
if (target_read_memory (scan_pc, buf, 4))
return 0;
insn = extract_unsigned_integer (buf, 4, byte_order);
if (is_branch (insn, &immed, &ra))
{
if (immed == 0 && ra == SPU_LR_REGNUM)
break;
return 0;
}
if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
|| is_rr (insn, op_a, &rt, &ra, &rb)
|| is_ri10 (insn, op_lqd, &rt, &ra, &immed))
{
if (rt == SPU_RAW_SP_REGNUM)
return 0;
}
}
if (scan_pc >= epilogue_end)
return 0;
/* Scan backward until adjustment to stack pointer (R1). */
for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
{
if (target_read_memory (scan_pc, buf, 4))
return 0;
insn = extract_unsigned_integer (buf, 4, byte_order);
if (is_branch (insn, &immed, &ra))
return 0;
if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
|| is_rr (insn, op_a, &rt, &ra, &rb)
|| is_ri10 (insn, op_lqd, &rt, &ra, &immed))
{
if (rt == SPU_RAW_SP_REGNUM)
return 1;
}
}
return 0;
}
/* Normal stack frames. */
struct spu_unwind_cache
{
CORE_ADDR func;
CORE_ADDR frame_base;
CORE_ADDR local_base;
struct trad_frame_saved_reg *saved_regs;
};
static struct spu_unwind_cache *
spu_frame_unwind_cache (struct frame_info *this_frame,
void **this_prologue_cache)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
struct spu_unwind_cache *info;
struct spu_prologue_data data;
CORE_ADDR id = tdep->id;
gdb_byte buf[16];